1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; U -- Pointer with short displacement.
54 ;; W -- Pointer with long displacement.
55 ;; Y -- Shift count operand.
57 ;; Special formats used for outputting 390 instructions.
59 ;; %C: print opcode suffix for branch condition.
60 ;; %D: print opcode suffix for inverse branch condition.
61 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
62 ;; %O: print only the displacement of a memory reference.
63 ;; %R: print only the base register of a memory reference.
64 ;; %S: print S-type memory reference (base+displacement).
65 ;; %N: print the second word of a DImode operand.
66 ;; %M: print the second word of a TImode operand.
68 ;; %b: print integer X as if it's an unsigned byte.
69 ;; %x: print integer X as if it's an unsigned word.
70 ;; %h: print integer X as if it's a signed word.
71 ;; %i: print the first nonzero HImode part of X
72 ;; %j: print the first HImode part unequal to 0xffff of X
75 ;; We have a special constraint for pattern matching.
77 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
90 ; GOT/PLT and lt-relative accesses
91 (UNSPEC_LTREL_OFFSET 100)
92 (UNSPEC_LTREL_BASE 101)
100 (UNSPEC_RELOAD_BASE 210)
101 (UNSPEC_MAIN_BASE 211)
106 ; TLS relocation specifiers
111 (UNSPEC_GOTNTPOFF 504)
112 (UNSPEC_INDNTPOFF 505)
115 (UNSPEC_TLSLDM_NTPOFF 511)
116 (UNSPEC_TLS_LOAD 512)
123 ;; UNSPEC_VOLATILE usage
131 (UNSPECV_TPF_PROLOGUE 20)
132 (UNSPECV_TPF_EPILOGUE 21)
136 (UNSPECV_POOL_SECTION 201)
137 (UNSPECV_POOL_ALIGN 202)
138 (UNSPECV_POOL_ENTRY 203)
139 (UNSPECV_MAIN_POOL 300)
146 ;; Instruction operand type as used in the Principles of Operation.
147 ;; Used to determine defaults for length and other attribute values.
149 (define_attr "op_type"
150 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
153 ;; Instruction type attribute used for scheduling.
155 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
156 cs,vs,store,imul,idiv,
157 branch,jsr,fsimpd,fsimps,
158 floadd,floads,fstored, fstores,
159 fmuld,fmuls,fdivd,fdivs,
160 ftoi,itof,fsqrtd,fsqrts,
162 (cond [(eq_attr "op_type" "NN") (const_string "other")
163 (eq_attr "op_type" "SS") (const_string "cs")]
164 (const_string "integer")))
166 ;; Another attribute used for scheduling purposes:
167 ;; agen: Instruction uses the address generation unit
168 ;; reg: Instruction does not use the agen unit
170 (define_attr "atype" "agen,reg"
171 (cond [ (eq_attr "op_type" "E") (const_string "reg")
172 (eq_attr "op_type" "RR") (const_string "reg")
173 (eq_attr "op_type" "RX") (const_string "agen")
174 (eq_attr "op_type" "RI") (const_string "reg")
175 (eq_attr "op_type" "RRE") (const_string "reg")
176 (eq_attr "op_type" "RS") (const_string "agen")
177 (eq_attr "op_type" "RSI") (const_string "agen")
178 (eq_attr "op_type" "S") (const_string "agen")
179 (eq_attr "op_type" "SI") (const_string "agen")
180 (eq_attr "op_type" "SS") (const_string "agen")
181 (eq_attr "op_type" "SSE") (const_string "agen")
182 (eq_attr "op_type" "RXE") (const_string "agen")
183 (eq_attr "op_type" "RSE") (const_string "agen")
184 (eq_attr "op_type" "RIL") (const_string "agen")
185 (eq_attr "op_type" "RXY") (const_string "agen")
186 (eq_attr "op_type" "RSY") (const_string "agen")
187 (eq_attr "op_type" "SIY") (const_string "agen")]
188 (const_string "reg")))
192 (define_attr "length" ""
193 (cond [ (eq_attr "op_type" "E") (const_int 2)
194 (eq_attr "op_type" "RR") (const_int 2)
195 (eq_attr "op_type" "RX") (const_int 4)
196 (eq_attr "op_type" "RI") (const_int 4)
197 (eq_attr "op_type" "RRE") (const_int 4)
198 (eq_attr "op_type" "RS") (const_int 4)
199 (eq_attr "op_type" "RSI") (const_int 4)
200 (eq_attr "op_type" "S") (const_int 4)
201 (eq_attr "op_type" "SI") (const_int 4)
202 (eq_attr "op_type" "SS") (const_int 6)
203 (eq_attr "op_type" "SSE") (const_int 6)
204 (eq_attr "op_type" "RXE") (const_int 6)
205 (eq_attr "op_type" "RSE") (const_int 6)
206 (eq_attr "op_type" "RIL") (const_int 6)
207 (eq_attr "op_type" "RXY") (const_int 6)
208 (eq_attr "op_type" "RSY") (const_int 6)
209 (eq_attr "op_type" "SIY") (const_int 6)]
212 ;; Define attributes for `asm' insns.
214 (define_asm_attributes [(set_attr "type" "other")
215 (set_attr "op_type" "NN")])
218 ;; Processor type. This attribute must exactly match the processor_type
219 ;; enumeration in s390.h. The current machine description does not
220 ;; distinguish between g5 and g6, but there are differences between the two
221 ;; CPUs could in theory be modeled.
223 (define_attr "cpu" "g5,g6,z900,z990"
224 (const (symbol_ref "s390_tune")))
226 ;; Pipeline description for z900. For lack of anything better,
227 ;; this description is also used for the g5 and g6.
230 ;; Pipeline description for z990.
238 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
239 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
240 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
241 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
242 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
245 ; CCZ1 -> CCA/CCU/CCS/CCT
248 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
249 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
253 ;;- Compare instructions.
256 (define_expand "cmpdi"
258 (compare:CC (match_operand:DI 0 "register_operand" "")
259 (match_operand:DI 1 "general_operand" "")))]
262 s390_compare_op0 = operands[0];
263 s390_compare_op1 = operands[1];
267 (define_expand "cmpsi"
269 (compare:CC (match_operand:SI 0 "register_operand" "")
270 (match_operand:SI 1 "general_operand" "")))]
273 s390_compare_op0 = operands[0];
274 s390_compare_op1 = operands[1];
278 (define_expand "cmpdf"
280 (compare:CC (match_operand:DF 0 "register_operand" "")
281 (match_operand:DF 1 "general_operand" "")))]
284 s390_compare_op0 = operands[0];
285 s390_compare_op1 = operands[1];
289 (define_expand "cmpsf"
291 (compare:CC (match_operand:SF 0 "register_operand" "")
292 (match_operand:SF 1 "general_operand" "")))]
295 s390_compare_op0 = operands[0];
296 s390_compare_op1 = operands[1];
301 ; Test-under-Mask instructions
303 (define_insn "*tmqi_mem"
305 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
306 (match_operand:QI 1 "immediate_operand" "n,n"))
307 (match_operand:QI 2 "immediate_operand" "n,n")))]
308 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
312 [(set_attr "op_type" "SI,SIY")])
314 (define_insn "*tmdi_reg"
316 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
317 (match_operand:DI 1 "immediate_operand"
318 "N0HD0,N1HD0,N2HD0,N3HD0"))
319 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
321 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
322 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
328 [(set_attr "op_type" "RI")])
330 (define_insn "*tmsi_reg"
332 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
333 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
334 (match_operand:SI 2 "immediate_operand" "n,n")))]
335 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
336 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
340 [(set_attr "op_type" "RI")])
342 (define_insn "*tmhi_full"
344 (compare (match_operand:HI 0 "register_operand" "d")
345 (match_operand:HI 1 "immediate_operand" "n")))]
346 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
348 [(set_attr "op_type" "RI")])
350 (define_insn "*tmqi_full"
352 (compare (match_operand:QI 0 "register_operand" "d")
353 (match_operand:QI 1 "immediate_operand" "n")))]
354 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
356 [(set_attr "op_type" "RI")])
359 ; Load-and-Test instructions
361 (define_insn "*tstdi_sign"
363 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
364 (const_int 32)) (const_int 32))
365 (match_operand:DI 1 "const0_operand" "")))
366 (set (match_operand:DI 2 "register_operand" "=d")
367 (sign_extend:DI (match_dup 0)))]
368 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
370 [(set_attr "op_type" "RRE")])
372 (define_insn "*tstdi"
374 (compare (match_operand:DI 0 "register_operand" "d")
375 (match_operand:DI 1 "const0_operand" "")))
376 (set (match_operand:DI 2 "register_operand" "=d")
378 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
380 [(set_attr "op_type" "RRE")])
382 (define_insn "*tstdi_cconly"
384 (compare (match_operand:DI 0 "register_operand" "d")
385 (match_operand:DI 1 "const0_operand" "")))]
386 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
388 [(set_attr "op_type" "RRE")])
390 (define_insn "*tstdi_cconly_31"
392 (compare (match_operand:DI 0 "register_operand" "d")
393 (match_operand:DI 1 "const0_operand" "")))]
394 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
396 [(set_attr "op_type" "RS")
397 (set_attr "atype" "reg")])
400 (define_insn "*tstsi"
402 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
403 (match_operand:SI 1 "const0_operand" "")))
404 (set (match_operand:SI 2 "register_operand" "=d,d,d")
406 "s390_match_ccmode(insn, CCSmode)"
411 [(set_attr "op_type" "RR,RS,RSY")])
413 (define_insn "*tstsi_cconly"
415 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
416 (match_operand:SI 1 "const0_operand" "")))
417 (clobber (match_scratch:SI 2 "=X,d,d"))]
418 "s390_match_ccmode(insn, CCSmode)"
423 [(set_attr "op_type" "RR,RS,RSY")])
425 (define_insn "*tstsi_cconly2"
427 (compare (match_operand:SI 0 "register_operand" "d")
428 (match_operand:SI 1 "const0_operand" "")))]
429 "s390_match_ccmode(insn, CCSmode)"
431 [(set_attr "op_type" "RR")])
433 (define_insn "*tsthiCCT"
435 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
436 (match_operand:HI 1 "const0_operand" "")))
437 (set (match_operand:HI 2 "register_operand" "=d,d,0")
439 "s390_match_ccmode(insn, CCTmode)"
444 [(set_attr "op_type" "RS,RSY,RI")])
446 (define_insn "*tsthiCCT_cconly"
448 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
449 (match_operand:HI 1 "const0_operand" "")))
450 (clobber (match_scratch:HI 2 "=d,d,X"))]
451 "s390_match_ccmode(insn, CCTmode)"
456 [(set_attr "op_type" "RS,RSY,RI")])
458 (define_insn "*tsthi"
460 (compare (match_operand:HI 0 "s_operand" "Q,S")
461 (match_operand:HI 1 "const0_operand" "")))
462 (set (match_operand:HI 2 "register_operand" "=d,d")
464 "s390_match_ccmode(insn, CCSmode)"
468 [(set_attr "op_type" "RS,RSY")])
470 (define_insn "*tsthi_cconly"
472 (compare (match_operand:HI 0 "s_operand" "Q,S")
473 (match_operand:HI 1 "const0_operand" "")))
474 (clobber (match_scratch:HI 2 "=d,d"))]
475 "s390_match_ccmode(insn, CCSmode)"
479 [(set_attr "op_type" "RS,RSY")])
481 (define_insn "*tstqiCCT"
483 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
484 (match_operand:QI 1 "const0_operand" "")))
485 (set (match_operand:QI 2 "register_operand" "=d,d,0")
487 "s390_match_ccmode(insn, CCTmode)"
492 [(set_attr "op_type" "RS,RSY,RI")])
494 (define_insn "*tstqiCCT_cconly"
496 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
497 (match_operand:QI 1 "const0_operand" "")))]
498 "s390_match_ccmode(insn, CCTmode)"
503 [(set_attr "op_type" "SI,SIY,RI")])
505 (define_insn "*tstqi"
507 (compare (match_operand:QI 0 "s_operand" "Q,S")
508 (match_operand:QI 1 "const0_operand" "")))
509 (set (match_operand:QI 2 "register_operand" "=d,d")
511 "s390_match_ccmode(insn, CCSmode)"
515 [(set_attr "op_type" "RS,RSY")])
517 (define_insn "*tstqi_cconly"
519 (compare (match_operand:QI 0 "s_operand" "Q,S")
520 (match_operand:QI 1 "const0_operand" "")))
521 (clobber (match_scratch:QI 2 "=d,d"))]
522 "s390_match_ccmode(insn, CCSmode)"
526 [(set_attr "op_type" "RS,RSY")])
529 ; Compare (equality) instructions
531 (define_insn "*cmpdi_cct"
533 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,m,Q")
534 (match_operand:DI 1 "general_operand" "d,K,m,d,Q")))]
535 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT
536 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))"
543 [(set_attr "op_type" "RRE,RI,RXY,RXY,SS")])
545 (define_insn "*cmpsi_cct"
547 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,R,T,Q")
548 (match_operand:SI 1 "general_operand" "d,K,R,T,d,d,Q")))]
549 "s390_match_ccmode (insn, CCTmode)
550 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))"
559 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")])
562 ; Compare (signed) instructions
564 (define_insn "*cmpdi_ccs_sign"
566 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
567 (match_operand:DI 0 "register_operand" "d,d")))]
568 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
572 [(set_attr "op_type" "RRE,RXY")])
574 (define_insn "*cmpdi_ccs"
576 (compare (match_operand:DI 0 "register_operand" "d,d,d")
577 (match_operand:DI 1 "general_operand" "d,K,m")))]
578 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
583 [(set_attr "op_type" "RRE,RI,RXY")])
585 (define_insn "*cmpsi_ccs_sign"
587 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
588 (match_operand:SI 0 "register_operand" "d,d")))]
589 "s390_match_ccmode(insn, CCSRmode)"
593 [(set_attr "op_type" "RX,RXY")])
595 (define_insn "*cmpsi_ccs"
597 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
598 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
599 "s390_match_ccmode(insn, CCSmode)"
605 [(set_attr "op_type" "RR,RI,RX,RXY")])
608 ; Compare (unsigned) instructions
610 (define_insn "*cmpdi_ccu_zero"
612 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
613 (match_operand:DI 0 "register_operand" "d,d")))]
614 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
618 [(set_attr "op_type" "RRE,RXY")])
620 (define_insn "*cmpdi_ccu"
622 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q")
623 (match_operand:DI 1 "general_operand" "d,m,Q")))]
624 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT
625 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))"
630 [(set_attr "op_type" "RRE,RXY,SS")])
632 (define_insn "*cmpsi_ccu"
634 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q")
635 (match_operand:SI 1 "general_operand" "d,R,T,Q")))]
636 "s390_match_ccmode (insn, CCUmode)
637 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))"
643 [(set_attr "op_type" "RR,RX,RXY,SS")])
645 (define_insn "*cmphi_ccu"
647 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q")
648 (match_operand:HI 1 "general_operand" "Q,S,Q")))]
649 "s390_match_ccmode (insn, CCUmode)
650 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
651 && !register_operand (operands[1], HImode)"
656 [(set_attr "op_type" "RS,RSY,SS")])
658 (define_insn "*cmpqi_ccu"
660 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q")
661 (match_operand:QI 1 "general_operand" "Q,S,n,n,Q")))]
662 "s390_match_ccmode (insn, CCUmode)
663 && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))
664 && !register_operand (operands[1], QImode)"
671 [(set_attr "op_type" "RS,RSY,SI,SIY,SS")])
674 ; Block compare (CLC) instruction patterns.
678 (compare (match_operand:BLK 0 "memory_operand" "=Q")
679 (match_operand:BLK 1 "memory_operand" "Q")))
680 (use (match_operand 2 "const_int_operand" "n"))]
681 "s390_match_ccmode (insn, CCUmode)
682 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
683 "clc\t%O0(%2,%R0),%S1"
684 [(set_attr "op_type" "SS")
685 (set_attr "type" "cs")])
689 (compare (match_operand 0 "memory_operand" "")
690 (match_operand 1 "memory_operand" "")))]
692 && s390_match_ccmode (insn, CCUmode)
693 && GET_MODE (operands[0]) == GET_MODE (operands[1])
694 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
696 [(set (match_dup 0) (match_dup 1))
697 (use (match_dup 2))])]
699 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
700 operands[0] = adjust_address (operands[0], BLKmode, 0);
701 operands[1] = adjust_address (operands[1], BLKmode, 0);
703 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
704 operands[0], operands[1]);
705 operands[0] = SET_DEST (PATTERN (curr_insn));
711 (define_insn "*cmpdf_ccs_0"
713 (compare (match_operand:DF 0 "register_operand" "f")
714 (match_operand:DF 1 "const0_operand" "")))]
715 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
717 [(set_attr "op_type" "RRE")
718 (set_attr "type" "fsimpd")])
720 (define_insn "*cmpdf_ccs_0_ibm"
722 (compare (match_operand:DF 0 "register_operand" "f")
723 (match_operand:DF 1 "const0_operand" "")))]
724 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
726 [(set_attr "op_type" "RR")
727 (set_attr "type" "fsimpd")])
729 (define_insn "*cmpdf_ccs"
731 (compare (match_operand:DF 0 "register_operand" "f,f")
732 (match_operand:DF 1 "general_operand" "f,R")))]
733 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
737 [(set_attr "op_type" "RRE,RXE")
738 (set_attr "type" "fsimpd")])
740 (define_insn "*cmpdf_ccs_ibm"
742 (compare (match_operand:DF 0 "register_operand" "f,f")
743 (match_operand:DF 1 "general_operand" "f,R")))]
744 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
748 [(set_attr "op_type" "RR,RX")
749 (set_attr "type" "fsimpd")])
754 (define_insn "*cmpsf_ccs_0"
756 (compare (match_operand:SF 0 "register_operand" "f")
757 (match_operand:SF 1 "const0_operand" "")))]
758 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
760 [(set_attr "op_type" "RRE")
761 (set_attr "type" "fsimps")])
763 (define_insn "*cmpsf_ccs_0_ibm"
765 (compare (match_operand:SF 0 "register_operand" "f")
766 (match_operand:SF 1 "const0_operand" "")))]
767 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
769 [(set_attr "op_type" "RR")
770 (set_attr "type" "fsimps")])
772 (define_insn "*cmpsf_ccs"
774 (compare (match_operand:SF 0 "register_operand" "f,f")
775 (match_operand:SF 1 "general_operand" "f,R")))]
776 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
780 [(set_attr "op_type" "RRE,RXE")
781 (set_attr "type" "fsimps")])
783 (define_insn "*cmpsf_ccs"
785 (compare (match_operand:SF 0 "register_operand" "f,f")
786 (match_operand:SF 1 "general_operand" "f,R")))]
787 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
791 [(set_attr "op_type" "RR,RX")
792 (set_attr "type" "fsimps")])
796 ;;- Move instructions.
800 ; movti instruction pattern(s).
804 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
805 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
813 [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
814 (set_attr "type" "lm,stm,*,*,cs")])
817 [(set (match_operand:TI 0 "nonimmediate_operand" "")
818 (match_operand:TI 1 "general_operand" ""))]
819 "TARGET_64BIT && reload_completed
820 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
821 [(set (match_dup 2) (match_dup 4))
822 (set (match_dup 3) (match_dup 5))]
824 operands[2] = operand_subword (operands[0], 0, 0, TImode);
825 operands[3] = operand_subword (operands[0], 1, 0, TImode);
826 operands[4] = operand_subword (operands[1], 0, 0, TImode);
827 operands[5] = operand_subword (operands[1], 1, 0, TImode);
831 [(set (match_operand:TI 0 "nonimmediate_operand" "")
832 (match_operand:TI 1 "general_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
835 [(set (match_dup 2) (match_dup 4))
836 (set (match_dup 3) (match_dup 5))]
838 operands[2] = operand_subword (operands[0], 1, 0, TImode);
839 operands[3] = operand_subword (operands[0], 0, 0, TImode);
840 operands[4] = operand_subword (operands[1], 1, 0, TImode);
841 operands[5] = operand_subword (operands[1], 0, 0, TImode);
845 [(set (match_operand:TI 0 "register_operand" "")
846 (match_operand:TI 1 "memory_operand" ""))]
847 "TARGET_64BIT && reload_completed
848 && !s_operand (operands[1], VOIDmode)"
849 [(set (match_dup 0) (match_dup 1))]
851 rtx addr = operand_subword (operands[0], 1, 0, TImode);
852 s390_load_address (addr, XEXP (operands[1], 0));
853 operands[1] = replace_equiv_address (operands[1], addr);
856 (define_expand "reload_outti"
857 [(parallel [(match_operand:TI 0 "memory_operand" "")
858 (match_operand:TI 1 "register_operand" "d")
859 (match_operand:DI 2 "register_operand" "=&a")])]
862 s390_load_address (operands[2], XEXP (operands[0], 0));
863 operands[0] = replace_equiv_address (operands[0], operands[2]);
864 emit_move_insn (operands[0], operands[1]);
869 ; movdi instruction pattern(s).
872 (define_expand "movdi"
873 [(set (match_operand:DI 0 "general_operand" "")
874 (match_operand:DI 1 "general_operand" ""))]
877 /* Handle symbolic constants. */
878 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
879 emit_symbolic_move (operands);
882 (define_insn "*movdi_larl"
883 [(set (match_operand:DI 0 "register_operand" "=d")
884 (match_operand:DI 1 "larl_operand" "X"))]
886 && !FP_REG_P (operands[0])"
888 [(set_attr "op_type" "RIL")
889 (set_attr "type" "larl")])
891 (define_insn "*movdi_64"
892 [(set (match_operand:DI 0 "nonimmediate_operand"
893 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
894 (match_operand:DI 1 "general_operand"
895 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
917 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,NN,NN,RS,RS,SS")
918 (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd,
919 fstored,fstored,*,*,*,*,cs")])
922 [(set (match_operand:DI 0 "register_operand" "")
923 (match_operand:DI 1 "register_operand" ""))]
924 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
925 [(set (match_dup 2) (match_dup 3))
926 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
927 (set (strict_low_part (match_dup 2)) (match_dup 4))]
928 "operands[2] = gen_lowpart (SImode, operands[0]);
929 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
932 [(set (match_operand:DI 0 "register_operand" "")
933 (match_operand:DI 1 "register_operand" ""))]
934 "TARGET_64BIT && ACCESS_REG_P (operands[0])
935 && dead_or_set_p (insn, operands[1])"
936 [(set (match_dup 3) (match_dup 2))
937 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
938 (set (match_dup 4) (match_dup 2))]
939 "operands[2] = gen_lowpart (SImode, operands[1]);
940 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
943 [(set (match_operand:DI 0 "register_operand" "")
944 (match_operand:DI 1 "register_operand" ""))]
945 "TARGET_64BIT && ACCESS_REG_P (operands[0])
946 && !dead_or_set_p (insn, operands[1])"
947 [(set (match_dup 3) (match_dup 2))
948 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
949 (set (match_dup 4) (match_dup 2))
950 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
951 "operands[2] = gen_lowpart (SImode, operands[1]);
952 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
954 (define_insn "*movdi_31"
955 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
956 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
969 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
970 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
973 [(set (match_operand:DI 0 "nonimmediate_operand" "")
974 (match_operand:DI 1 "general_operand" ""))]
975 "!TARGET_64BIT && reload_completed
976 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
977 [(set (match_dup 2) (match_dup 4))
978 (set (match_dup 3) (match_dup 5))]
980 operands[2] = operand_subword (operands[0], 0, 0, DImode);
981 operands[3] = operand_subword (operands[0], 1, 0, DImode);
982 operands[4] = operand_subword (operands[1], 0, 0, DImode);
983 operands[5] = operand_subword (operands[1], 1, 0, DImode);
987 [(set (match_operand:DI 0 "nonimmediate_operand" "")
988 (match_operand:DI 1 "general_operand" ""))]
989 "!TARGET_64BIT && reload_completed
990 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
991 [(set (match_dup 2) (match_dup 4))
992 (set (match_dup 3) (match_dup 5))]
994 operands[2] = operand_subword (operands[0], 1, 0, DImode);
995 operands[3] = operand_subword (operands[0], 0, 0, DImode);
996 operands[4] = operand_subword (operands[1], 1, 0, DImode);
997 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1001 [(set (match_operand:DI 0 "register_operand" "")
1002 (match_operand:DI 1 "memory_operand" ""))]
1003 "!TARGET_64BIT && reload_completed
1004 && !FP_REG_P (operands[0])
1005 && !s_operand (operands[1], VOIDmode)"
1006 [(set (match_dup 0) (match_dup 1))]
1008 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1009 s390_load_address (addr, XEXP (operands[1], 0));
1010 operands[1] = replace_equiv_address (operands[1], addr);
1013 (define_expand "reload_outdi"
1014 [(parallel [(match_operand:DI 0 "memory_operand" "")
1015 (match_operand:DI 1 "register_operand" "d")
1016 (match_operand:SI 2 "register_operand" "=&a")])]
1019 s390_load_address (operands[2], XEXP (operands[0], 0));
1020 operands[0] = replace_equiv_address (operands[0], operands[2]);
1021 emit_move_insn (operands[0], operands[1]);
1026 [(set (match_operand:DI 0 "register_operand" "")
1027 (mem:DI (match_operand 1 "address_operand" "")))]
1029 && !FP_REG_P (operands[0])
1030 && GET_CODE (operands[1]) == SYMBOL_REF
1031 && CONSTANT_POOL_ADDRESS_P (operands[1])
1032 && get_pool_mode (operands[1]) == DImode
1033 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1034 [(set (match_dup 0) (match_dup 2))]
1035 "operands[2] = get_pool_constant (operands[1]);")
1037 (define_insn "*la_64"
1038 [(set (match_operand:DI 0 "register_operand" "=d,d")
1039 (match_operand:QI 1 "address_operand" "U,W"))]
1044 [(set_attr "op_type" "RX,RXY")
1045 (set_attr "type" "la")])
1049 [(set (match_operand:DI 0 "register_operand" "")
1050 (match_operand:QI 1 "address_operand" ""))
1051 (clobber (reg:CC 33))])]
1053 && preferred_la_operand_p (operands[1], const0_rtx)"
1054 [(set (match_dup 0) (match_dup 1))]
1058 [(set (match_operand:DI 0 "register_operand" "")
1059 (match_operand:DI 1 "register_operand" ""))
1062 (plus:DI (match_dup 0)
1063 (match_operand:DI 2 "nonmemory_operand" "")))
1064 (clobber (reg:CC 33))])]
1066 && !reg_overlap_mentioned_p (operands[0], operands[2])
1067 && preferred_la_operand_p (operands[1], operands[2])"
1068 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1071 (define_expand "reload_indi"
1072 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1073 (match_operand:DI 1 "s390_plus_operand" "")
1074 (match_operand:DI 2 "register_operand" "=&a")])]
1077 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1082 ; movsi instruction pattern(s).
1085 (define_expand "movsi"
1086 [(set (match_operand:SI 0 "general_operand" "")
1087 (match_operand:SI 1 "general_operand" ""))]
1090 /* Handle symbolic constants. */
1091 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1092 emit_symbolic_move (operands);
1095 (define_insn "*movsi_larl"
1096 [(set (match_operand:SI 0 "register_operand" "=d")
1097 (match_operand:SI 1 "larl_operand" "X"))]
1098 "!TARGET_64BIT && TARGET_CPU_ZARCH
1099 && !FP_REG_P (operands[0])"
1101 [(set_attr "op_type" "RIL")
1102 (set_attr "type" "larl")])
1104 (define_insn "*movsi_zarch"
1105 [(set (match_operand:SI 0 "nonimmediate_operand"
1106 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1107 (match_operand:SI 1 "general_operand"
1108 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1130 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1131 (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,*,*,*,*,cs")])
1133 (define_insn "*movsi_esa"
1134 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1135 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1150 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1151 (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,cs")])
1154 [(set (match_operand:SI 0 "register_operand" "")
1155 (mem:SI (match_operand 1 "address_operand" "")))]
1156 "!FP_REG_P (operands[0])
1157 && GET_CODE (operands[1]) == SYMBOL_REF
1158 && CONSTANT_POOL_ADDRESS_P (operands[1])
1159 && get_pool_mode (operands[1]) == SImode
1160 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1161 [(set (match_dup 0) (match_dup 2))]
1162 "operands[2] = get_pool_constant (operands[1]);")
1164 (define_insn "*la_31"
1165 [(set (match_operand:SI 0 "register_operand" "=d,d")
1166 (match_operand:QI 1 "address_operand" "U,W"))]
1167 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1171 [(set_attr "op_type" "RX,RXY")
1172 (set_attr "type" "la")])
1176 [(set (match_operand:SI 0 "register_operand" "")
1177 (match_operand:QI 1 "address_operand" ""))
1178 (clobber (reg:CC 33))])]
1180 && preferred_la_operand_p (operands[1], const0_rtx)"
1181 [(set (match_dup 0) (match_dup 1))]
1185 [(set (match_operand:SI 0 "register_operand" "")
1186 (match_operand:SI 1 "register_operand" ""))
1189 (plus:SI (match_dup 0)
1190 (match_operand:SI 2 "nonmemory_operand" "")))
1191 (clobber (reg:CC 33))])]
1193 && !reg_overlap_mentioned_p (operands[0], operands[2])
1194 && preferred_la_operand_p (operands[1], operands[2])"
1195 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1198 (define_insn "*la_31_and"
1199 [(set (match_operand:SI 0 "register_operand" "=d,d")
1200 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1201 (const_int 2147483647)))]
1206 [(set_attr "op_type" "RX,RXY")
1207 (set_attr "type" "la")])
1209 (define_insn_and_split "*la_31_and_cc"
1210 [(set (match_operand:SI 0 "register_operand" "=d")
1211 (and:SI (match_operand:QI 1 "address_operand" "p")
1212 (const_int 2147483647)))
1213 (clobber (reg:CC 33))]
1216 "&& reload_completed"
1218 (and:SI (match_dup 1) (const_int 2147483647)))]
1220 [(set_attr "op_type" "RX")
1221 (set_attr "type" "la")])
1223 (define_insn "force_la_31"
1224 [(set (match_operand:SI 0 "register_operand" "=d,d")
1225 (match_operand:QI 1 "address_operand" "U,W"))
1226 (use (const_int 0))]
1231 [(set_attr "op_type" "RX")
1232 (set_attr "type" "la")])
1234 (define_expand "reload_insi"
1235 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1236 (match_operand:SI 1 "s390_plus_operand" "")
1237 (match_operand:SI 2 "register_operand" "=&a")])]
1240 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1245 ; movhi instruction pattern(s).
1248 (define_expand "movhi"
1249 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1250 (match_operand:HI 1 "general_operand" ""))]
1253 /* Make it explicit that loading a register from memory
1254 always sign-extends (at least) to SImode. */
1255 if (optimize && !no_new_pseudos
1256 && register_operand (operands[0], VOIDmode)
1257 && GET_CODE (operands[1]) == MEM)
1259 rtx tmp = gen_reg_rtx (SImode);
1260 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1261 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1262 operands[1] = gen_lowpart (HImode, tmp);
1266 (define_insn "*movhi"
1267 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1268 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1278 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1279 (set_attr "type" "lr,*,*,*,store,store,cs")])
1282 [(set (match_operand:HI 0 "register_operand" "")
1283 (mem:HI (match_operand 1 "address_operand" "")))]
1284 "GET_CODE (operands[1]) == SYMBOL_REF
1285 && CONSTANT_POOL_ADDRESS_P (operands[1])
1286 && get_pool_mode (operands[1]) == HImode
1287 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1288 [(set (match_dup 0) (match_dup 2))]
1289 "operands[2] = get_pool_constant (operands[1]);")
1292 ; movqi instruction pattern(s).
1295 (define_expand "movqi"
1296 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1297 (match_operand:QI 1 "general_operand" ""))]
1300 /* On z/Architecture, zero-extending from memory to register
1301 is just as fast as a QImode load. */
1302 if (TARGET_ZARCH && optimize && !no_new_pseudos
1303 && register_operand (operands[0], VOIDmode)
1304 && GET_CODE (operands[1]) == MEM)
1306 rtx tmp = gen_reg_rtx (word_mode);
1307 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1308 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1309 operands[1] = gen_lowpart (QImode, tmp);
1313 (define_insn "*movqi"
1314 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1315 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1327 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1328 (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
1331 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1332 (mem:QI (match_operand 1 "address_operand" "")))]
1333 "GET_CODE (operands[1]) == SYMBOL_REF
1334 && CONSTANT_POOL_ADDRESS_P (operands[1])
1335 && get_pool_mode (operands[1]) == QImode
1336 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1337 [(set (match_dup 0) (match_dup 2))]
1338 "operands[2] = get_pool_constant (operands[1]);")
1341 ; movstrictqi instruction pattern(s).
1344 (define_insn "*movstrictqi"
1345 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1346 (match_operand:QI 1 "memory_operand" "R,T"))]
1351 [(set_attr "op_type" "RX,RXY")])
1354 ; movstricthi instruction pattern(s).
1357 (define_insn "*movstricthi"
1358 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1359 (match_operand:HI 1 "memory_operand" "Q,S"))
1360 (clobber (reg:CC 33))]
1365 [(set_attr "op_type" "RS,RSY")])
1368 ; movstrictsi instruction pattern(s).
1371 (define_insn "movstrictsi"
1372 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1373 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1380 [(set_attr "op_type" "RR,RX,RXY,RRE")
1381 (set_attr "type" "lr,load,load,*")])
1384 ; movdf instruction pattern(s).
1387 (define_expand "movdf"
1388 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1389 (match_operand:DF 1 "general_operand" ""))]
1393 (define_insn "*movdf_64"
1394 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1395 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1407 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1408 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
1410 (define_insn "*movdf_31"
1411 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1412 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1425 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
1426 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
1429 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1430 (match_operand:DF 1 "general_operand" ""))]
1431 "!TARGET_64BIT && reload_completed
1432 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1433 [(set (match_dup 2) (match_dup 4))
1434 (set (match_dup 3) (match_dup 5))]
1436 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1437 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1438 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1439 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1443 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1444 (match_operand:DF 1 "general_operand" ""))]
1445 "!TARGET_64BIT && reload_completed
1446 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1447 [(set (match_dup 2) (match_dup 4))
1448 (set (match_dup 3) (match_dup 5))]
1450 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1451 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1452 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1453 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1457 [(set (match_operand:DF 0 "register_operand" "")
1458 (match_operand:DF 1 "memory_operand" ""))]
1459 "!TARGET_64BIT && reload_completed
1460 && !FP_REG_P (operands[0])
1461 && !s_operand (operands[1], VOIDmode)"
1462 [(set (match_dup 0) (match_dup 1))]
1464 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1465 s390_load_address (addr, XEXP (operands[1], 0));
1466 operands[1] = replace_equiv_address (operands[1], addr);
1469 (define_expand "reload_outdf"
1470 [(parallel [(match_operand:DF 0 "memory_operand" "")
1471 (match_operand:DF 1 "register_operand" "d")
1472 (match_operand:SI 2 "register_operand" "=&a")])]
1475 s390_load_address (operands[2], XEXP (operands[0], 0));
1476 operands[0] = replace_equiv_address (operands[0], operands[2]);
1477 emit_move_insn (operands[0], operands[1]);
1482 ; movsf instruction pattern(s).
1485 (define_insn "movsf"
1486 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1487 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1501 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1502 (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
1505 ; movcc instruction pattern
1508 (define_insn "movcc"
1509 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1510 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1520 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1521 (set_attr "type" "lr,*,*,store,store,load,load")])
1524 ; Block move (MVC) patterns.
1528 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1529 (match_operand:BLK 1 "memory_operand" "Q"))
1530 (use (match_operand 2 "const_int_operand" "n"))]
1531 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1532 "mvc\t%O0(%2,%R0),%S1"
1533 [(set_attr "op_type" "SS")
1534 (set_attr "type" "cs")])
1537 [(set (match_operand 0 "memory_operand" "")
1538 (match_operand 1 "memory_operand" ""))]
1540 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1541 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1543 [(set (match_dup 0) (match_dup 1))
1544 (use (match_dup 2))])]
1546 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1547 operands[0] = adjust_address (operands[0], BLKmode, 0);
1548 operands[1] = adjust_address (operands[1], BLKmode, 0);
1553 [(set (match_operand:BLK 0 "memory_operand" "")
1554 (match_operand:BLK 1 "memory_operand" ""))
1555 (use (match_operand 2 "const_int_operand" ""))])
1557 [(set (match_operand:BLK 3 "memory_operand" "")
1558 (match_operand:BLK 4 "memory_operand" ""))
1559 (use (match_operand 5 "const_int_operand" ""))])]
1560 "s390_offset_p (operands[0], operands[3], operands[2])
1561 && s390_offset_p (operands[1], operands[4], operands[2])
1562 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1564 [(set (match_dup 6) (match_dup 7))
1565 (use (match_dup 8))])]
1566 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1567 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1568 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1572 ; load_multiple pattern(s).
1574 ; ??? Due to reload problems with replacing registers inside match_parallel
1575 ; we currently support load_multiple/store_multiple only after reload.
1578 (define_expand "load_multiple"
1579 [(match_par_dup 3 [(set (match_operand 0 "" "")
1580 (match_operand 1 "" ""))
1581 (use (match_operand 2 "" ""))])]
1584 enum machine_mode mode;
1590 /* Support only loading a constant number of fixed-point registers from
1591 memory and only bother with this if more than two */
1592 if (GET_CODE (operands[2]) != CONST_INT
1593 || INTVAL (operands[2]) < 2
1594 || INTVAL (operands[2]) > 16
1595 || GET_CODE (operands[1]) != MEM
1596 || GET_CODE (operands[0]) != REG
1597 || REGNO (operands[0]) >= 16)
1600 count = INTVAL (operands[2]);
1601 regno = REGNO (operands[0]);
1602 mode = GET_MODE (operands[0]);
1603 if (mode != SImode && mode != word_mode)
1606 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1609 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1611 from = XEXP (operands[1], 0);
1614 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1615 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1616 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1618 from = XEXP (XEXP (operands[1], 0), 0);
1619 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1626 from = force_reg (Pmode, XEXP (operands[1], 0));
1630 for (i = 0; i < count; i++)
1631 XVECEXP (operands[3], 0, i)
1632 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1633 change_address (operands[1], mode,
1634 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1637 (define_insn "*load_multiple_di"
1638 [(match_parallel 0 "load_multiple_operation"
1639 [(set (match_operand:DI 1 "register_operand" "=r")
1640 (match_operand:DI 2 "s_operand" "QS"))])]
1641 "reload_completed && word_mode == DImode"
1643 int words = XVECLEN (operands[0], 0);
1644 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1645 return "lmg\t%1,%0,%S2";
1647 [(set_attr "op_type" "RSY")
1648 (set_attr "type" "lm")])
1650 (define_insn "*load_multiple_si"
1651 [(match_parallel 0 "load_multiple_operation"
1652 [(set (match_operand:SI 1 "register_operand" "=r,r")
1653 (match_operand:SI 2 "s_operand" "Q,S"))])]
1656 int words = XVECLEN (operands[0], 0);
1657 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1658 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1660 [(set_attr "op_type" "RS,RSY")
1661 (set_attr "type" "lm")])
1664 ; store multiple pattern(s).
1667 (define_expand "store_multiple"
1668 [(match_par_dup 3 [(set (match_operand 0 "" "")
1669 (match_operand 1 "" ""))
1670 (use (match_operand 2 "" ""))])]
1673 enum machine_mode mode;
1679 /* Support only storing a constant number of fixed-point registers to
1680 memory and only bother with this if more than two. */
1681 if (GET_CODE (operands[2]) != CONST_INT
1682 || INTVAL (operands[2]) < 2
1683 || INTVAL (operands[2]) > 16
1684 || GET_CODE (operands[0]) != MEM
1685 || GET_CODE (operands[1]) != REG
1686 || REGNO (operands[1]) >= 16)
1689 count = INTVAL (operands[2]);
1690 regno = REGNO (operands[1]);
1691 mode = GET_MODE (operands[1]);
1692 if (mode != SImode && mode != word_mode)
1695 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1699 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1701 to = XEXP (operands[0], 0);
1704 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1705 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1706 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1708 to = XEXP (XEXP (operands[0], 0), 0);
1709 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1716 to = force_reg (Pmode, XEXP (operands[0], 0));
1720 for (i = 0; i < count; i++)
1721 XVECEXP (operands[3], 0, i)
1722 = gen_rtx_SET (VOIDmode,
1723 change_address (operands[0], mode,
1724 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1725 gen_rtx_REG (mode, regno + i));
1728 (define_insn "*store_multiple_di"
1729 [(match_parallel 0 "store_multiple_operation"
1730 [(set (match_operand:DI 1 "s_operand" "=QS")
1731 (match_operand:DI 2 "register_operand" "r"))])]
1732 "reload_completed && word_mode == DImode"
1734 int words = XVECLEN (operands[0], 0);
1735 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1736 return "stmg\t%2,%0,%S1";
1738 [(set_attr "op_type" "RSY")
1739 (set_attr "type" "stm")])
1742 (define_insn "*store_multiple_si"
1743 [(match_parallel 0 "store_multiple_operation"
1744 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1745 (match_operand:SI 2 "register_operand" "r,r"))])]
1748 int words = XVECLEN (operands[0], 0);
1749 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1750 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1752 [(set_attr "op_type" "RS,RSY")
1753 (set_attr "type" "stm")])
1756 ;; String instructions.
1759 (define_insn "*execute"
1760 [(match_parallel 0 ""
1761 [(unspec [(match_operand 1 "register_operand" "a")
1762 (match_operand:BLK 2 "memory_operand" "R")
1763 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1764 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1765 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1767 [(set_attr "op_type" "RX")
1768 (set_attr "type" "cs")])
1772 ; strlenM instruction pattern(s).
1775 (define_expand "strlendi"
1776 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1779 (unspec:DI [(const_int 0)
1780 (match_operand:BLK 1 "memory_operand" "")
1782 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1783 (clobber (scratch:DI))
1784 (clobber (reg:CC 33))])
1786 [(set (match_operand:DI 0 "register_operand" "")
1787 (minus:DI (match_dup 4) (match_dup 5)))
1788 (clobber (reg:CC 33))])]
1791 operands[4] = gen_reg_rtx (DImode);
1792 operands[5] = gen_reg_rtx (DImode);
1793 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1794 operands[1] = replace_equiv_address (operands[1], operands[5]);
1797 (define_insn "*strlendi"
1798 [(set (match_operand:DI 0 "register_operand" "=a")
1799 (unspec:DI [(match_operand:DI 2 "general_operand" "0")
1800 (mem:BLK (match_operand:DI 3 "register_operand" "1"))
1802 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1803 (clobber (match_scratch:DI 1 "=a"))
1804 (clobber (reg:CC 33))]
1806 "srst\t%0,%1\;jo\t.-4"
1807 [(set_attr "op_type" "NN")
1808 (set_attr "type" "vs")
1809 (set_attr "length" "8")])
1811 (define_expand "strlensi"
1812 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1815 (unspec:SI [(const_int 0)
1816 (match_operand:BLK 1 "memory_operand" "")
1818 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1819 (clobber (scratch:SI))
1820 (clobber (reg:CC 33))])
1822 [(set (match_operand:SI 0 "register_operand" "")
1823 (minus:SI (match_dup 4) (match_dup 5)))
1824 (clobber (reg:CC 33))])]
1827 operands[4] = gen_reg_rtx (SImode);
1828 operands[5] = gen_reg_rtx (SImode);
1829 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1830 operands[1] = replace_equiv_address (operands[1], operands[5]);
1833 (define_insn "*strlensi"
1834 [(set (match_operand:SI 0 "register_operand" "=a")
1835 (unspec:SI [(match_operand:SI 2 "general_operand" "0")
1836 (mem:BLK (match_operand:SI 3 "register_operand" "1"))
1838 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1839 (clobber (match_scratch:SI 1 "=a"))
1840 (clobber (reg:CC 33))]
1842 "srst\t%0,%1\;jo\t.-4"
1843 [(set_attr "op_type" "NN")
1844 (set_attr "type" "vs")
1845 (set_attr "length" "8")])
1848 ; movmemM instruction pattern(s).
1851 (define_expand "movmemdi"
1852 [(set (match_operand:BLK 0 "memory_operand" "")
1853 (match_operand:BLK 1 "memory_operand" ""))
1854 (use (match_operand:DI 2 "general_operand" ""))
1855 (match_operand 3 "" "")]
1857 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1859 (define_expand "movmemsi"
1860 [(set (match_operand:BLK 0 "memory_operand" "")
1861 (match_operand:BLK 1 "memory_operand" ""))
1862 (use (match_operand:SI 2 "general_operand" ""))
1863 (match_operand 3 "" "")]
1865 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1867 ; Move a block that is up to 256 bytes in length.
1868 ; The block length is taken as (operands[2] % 256) + 1.
1870 (define_expand "movmem_short"
1872 [(set (match_operand:BLK 0 "memory_operand" "")
1873 (match_operand:BLK 1 "memory_operand" ""))
1874 (use (match_operand 2 "nonmemory_operand" ""))
1875 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1876 (clobber (match_dup 3))])]
1878 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1880 (define_insn "*movmem_short"
1881 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1882 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1883 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1884 (use (match_operand 3 "immediate_operand" "X,R,X"))
1885 (clobber (match_scratch 4 "=X,X,&a"))]
1886 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1887 && GET_MODE (operands[4]) == Pmode"
1889 [(set_attr "op_type" "SS,RX,RX")
1890 (set_attr "type" "cs")])
1893 [(set (match_operand:BLK 0 "memory_operand" "")
1894 (match_operand:BLK 1 "memory_operand" ""))
1895 (use (match_operand 2 "const_int_operand" ""))
1896 (use (match_operand 3 "immediate_operand" ""))
1897 (clobber (scratch))]
1900 [(set (match_dup 0) (match_dup 1))
1901 (use (match_dup 2))])]
1902 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1905 [(set (match_operand:BLK 0 "memory_operand" "")
1906 (match_operand:BLK 1 "memory_operand" ""))
1907 (use (match_operand 2 "register_operand" ""))
1908 (use (match_operand 3 "memory_operand" ""))
1909 (clobber (scratch))]
1912 [(unspec [(match_dup 2) (match_dup 3)
1913 (const_int 0)] UNSPEC_EXECUTE)
1914 (set (match_dup 0) (match_dup 1))
1915 (use (const_int 1))])]
1919 [(set (match_operand:BLK 0 "memory_operand" "")
1920 (match_operand:BLK 1 "memory_operand" ""))
1921 (use (match_operand 2 "register_operand" ""))
1922 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1923 (clobber (match_operand 3 "register_operand" ""))]
1924 "reload_completed && TARGET_CPU_ZARCH"
1925 [(set (match_dup 3) (label_ref (match_dup 4)))
1927 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1928 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1929 (set (match_dup 0) (match_dup 1))
1930 (use (const_int 1))])]
1931 "operands[4] = gen_label_rtx ();")
1933 ; Move a block of arbitrary length.
1935 (define_expand "movmem_long"
1937 [(clobber (match_dup 2))
1938 (clobber (match_dup 3))
1939 (set (match_operand:BLK 0 "memory_operand" "")
1940 (match_operand:BLK 1 "memory_operand" ""))
1941 (use (match_operand 2 "general_operand" ""))
1943 (clobber (reg:CC 33))])]
1946 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1947 rtx reg0 = gen_reg_rtx (dword_mode);
1948 rtx reg1 = gen_reg_rtx (dword_mode);
1949 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1950 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1951 rtx len0 = gen_lowpart (Pmode, reg0);
1952 rtx len1 = gen_lowpart (Pmode, reg1);
1954 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1955 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1956 emit_move_insn (len0, operands[2]);
1958 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1959 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1960 emit_move_insn (len1, operands[2]);
1962 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1963 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1968 (define_insn "*movmem_long_64"
1969 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1970 (clobber (match_operand:TI 1 "register_operand" "=d"))
1971 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1972 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1975 (clobber (reg:CC 33))]
1977 "mvcle\t%0,%1,0\;jo\t.-4"
1978 [(set_attr "op_type" "NN")
1979 (set_attr "type" "vs")
1980 (set_attr "length" "8")])
1982 (define_insn "*movmem_long_31"
1983 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1984 (clobber (match_operand:DI 1 "register_operand" "=d"))
1985 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1986 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1989 (clobber (reg:CC 33))]
1991 "mvcle\t%0,%1,0\;jo\t.-4"
1992 [(set_attr "op_type" "NN")
1993 (set_attr "type" "vs")
1994 (set_attr "length" "8")])
1997 ; clrmemM instruction pattern(s).
2000 (define_expand "clrmemdi"
2001 [(set (match_operand:BLK 0 "memory_operand" "")
2003 (use (match_operand:DI 1 "general_operand" ""))
2004 (match_operand 2 "" "")]
2006 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
2008 (define_expand "clrmemsi"
2009 [(set (match_operand:BLK 0 "memory_operand" "")
2011 (use (match_operand:SI 1 "general_operand" ""))
2012 (match_operand 2 "" "")]
2014 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
2016 ; Clear a block that is up to 256 bytes in length.
2017 ; The block length is taken as (operands[1] % 256) + 1.
2019 (define_expand "clrmem_short"
2021 [(set (match_operand:BLK 0 "memory_operand" "")
2023 (use (match_operand 1 "nonmemory_operand" ""))
2024 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2025 (clobber (match_dup 2))
2026 (clobber (reg:CC 33))])]
2028 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2030 (define_insn "*clrmem_short"
2031 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2033 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2034 (use (match_operand 2 "immediate_operand" "X,R,X"))
2035 (clobber (match_scratch 3 "=X,X,&a"))
2036 (clobber (reg:CC 33))]
2037 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2038 && GET_MODE (operands[3]) == Pmode"
2040 [(set_attr "op_type" "SS,RX,RX")
2041 (set_attr "type" "cs")])
2044 [(set (match_operand:BLK 0 "memory_operand" "")
2046 (use (match_operand 1 "const_int_operand" ""))
2047 (use (match_operand 2 "immediate_operand" ""))
2049 (clobber (reg:CC 33))]
2052 [(set (match_dup 0) (const_int 0))
2054 (clobber (reg:CC 33))])]
2055 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2058 [(set (match_operand:BLK 0 "memory_operand" "")
2060 (use (match_operand 1 "register_operand" ""))
2061 (use (match_operand 2 "memory_operand" ""))
2063 (clobber (reg:CC 33))]
2066 [(unspec [(match_dup 1) (match_dup 2)
2067 (const_int 0)] UNSPEC_EXECUTE)
2068 (set (match_dup 0) (const_int 0))
2070 (clobber (reg:CC 33))])]
2074 [(set (match_operand:BLK 0 "memory_operand" "")
2076 (use (match_operand 1 "register_operand" ""))
2077 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2078 (clobber (match_operand 2 "register_operand" ""))
2079 (clobber (reg:CC 33))]
2080 "reload_completed && TARGET_CPU_ZARCH"
2081 [(set (match_dup 2) (label_ref (match_dup 3)))
2083 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2084 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2085 (set (match_dup 0) (const_int 0))
2087 (clobber (reg:CC 33))])]
2088 "operands[3] = gen_label_rtx ();")
2090 ; Clear a block of arbitrary length.
2092 (define_expand "clrmem_long"
2094 [(clobber (match_dup 1))
2095 (set (match_operand:BLK 0 "memory_operand" "")
2097 (use (match_operand 1 "general_operand" ""))
2099 (clobber (reg:CC 33))])]
2102 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2103 rtx reg0 = gen_reg_rtx (dword_mode);
2104 rtx reg1 = gen_reg_rtx (dword_mode);
2105 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2106 rtx len0 = gen_lowpart (Pmode, reg0);
2108 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2109 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2110 emit_move_insn (len0, operands[1]);
2112 emit_move_insn (reg1, const0_rtx);
2114 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2119 (define_insn "*clrmem_long_64"
2120 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2121 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2124 (use (match_operand:TI 1 "register_operand" "d"))
2125 (clobber (reg:CC 33))]
2127 "mvcle\t%0,%1,0\;jo\t.-4"
2128 [(set_attr "op_type" "NN")
2129 (set_attr "type" "vs")
2130 (set_attr "length" "8")])
2132 (define_insn "*clrmem_long_31"
2133 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2134 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2137 (use (match_operand:DI 1 "register_operand" "d"))
2138 (clobber (reg:CC 33))]
2140 "mvcle\t%0,%1,0\;jo\t.-4"
2141 [(set_attr "op_type" "NN")
2142 (set_attr "type" "vs")
2143 (set_attr "length" "8")])
2146 ; cmpmemM instruction pattern(s).
2149 (define_expand "cmpmemsi"
2150 [(set (match_operand:SI 0 "register_operand" "")
2151 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2152 (match_operand:BLK 2 "memory_operand" "") ) )
2153 (use (match_operand:SI 3 "general_operand" ""))
2154 (use (match_operand:SI 4 "" ""))]
2156 "s390_expand_cmpmem (operands[0], operands[1],
2157 operands[2], operands[3]); DONE;")
2159 ; Compare a block that is up to 256 bytes in length.
2160 ; The block length is taken as (operands[2] % 256) + 1.
2162 (define_expand "cmpmem_short"
2165 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2166 (match_operand:BLK 1 "memory_operand" "")))
2167 (use (match_operand 2 "nonmemory_operand" ""))
2168 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2169 (clobber (match_dup 3))])]
2171 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2173 (define_insn "*cmpmem_short"
2175 (compare:CCU (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2176 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2177 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2178 (use (match_operand 3 "immediate_operand" "X,R,X"))
2179 (clobber (match_scratch 4 "=X,X,&a"))]
2180 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2181 && GET_MODE (operands[4]) == Pmode"
2183 [(set_attr "op_type" "SS,RX,RX")
2184 (set_attr "type" "cs")])
2188 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2189 (match_operand:BLK 1 "memory_operand" "")))
2190 (use (match_operand 2 "const_int_operand" ""))
2191 (use (match_operand 3 "immediate_operand" ""))
2192 (clobber (scratch))]
2195 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2196 (use (match_dup 2))])]
2197 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2201 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2202 (match_operand:BLK 1 "memory_operand" "")))
2203 (use (match_operand 2 "register_operand" ""))
2204 (use (match_operand 3 "memory_operand" ""))
2205 (clobber (scratch))]
2208 [(unspec [(match_dup 2) (match_dup 3)
2209 (const_int 0)] UNSPEC_EXECUTE)
2210 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2211 (use (const_int 1))])]
2216 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2217 (match_operand:BLK 1 "memory_operand" "")))
2218 (use (match_operand 2 "register_operand" ""))
2219 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2220 (clobber (match_operand 3 "register_operand" ""))]
2221 "reload_completed && TARGET_CPU_ZARCH"
2222 [(set (match_dup 3) (label_ref (match_dup 4)))
2224 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2225 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2226 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2227 (use (const_int 1))])]
2228 "operands[4] = gen_label_rtx ();")
2230 ; Compare a block of arbitrary length.
2232 (define_expand "cmpmem_long"
2234 [(clobber (match_dup 2))
2235 (clobber (match_dup 3))
2237 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2238 (match_operand:BLK 1 "memory_operand" "")))
2239 (use (match_operand 2 "general_operand" ""))
2240 (use (match_dup 3))])]
2243 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2244 rtx reg0 = gen_reg_rtx (dword_mode);
2245 rtx reg1 = gen_reg_rtx (dword_mode);
2246 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2247 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2248 rtx len0 = gen_lowpart (Pmode, reg0);
2249 rtx len1 = gen_lowpart (Pmode, reg1);
2251 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2252 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2253 emit_move_insn (len0, operands[2]);
2255 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2256 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2257 emit_move_insn (len1, operands[2]);
2259 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2260 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2265 (define_insn "*cmpmem_long_64"
2266 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2267 (clobber (match_operand:TI 1 "register_operand" "=d"))
2269 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2270 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2272 (use (match_dup 3))]
2274 "clcle\t%0,%1,0\;jo\t.-4"
2275 [(set_attr "op_type" "NN")
2276 (set_attr "type" "vs")
2277 (set_attr "length" "8")])
2279 (define_insn "*cmpmem_long_31"
2280 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2281 (clobber (match_operand:DI 1 "register_operand" "=d"))
2283 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2284 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2286 (use (match_dup 3))]
2288 "clcle\t%0,%1,0\;jo\t.-4"
2289 [(set_attr "op_type" "NN")
2290 (set_attr "type" "vs")
2291 (set_attr "length" "8")])
2293 ; Convert condition code to integer in range (-1, 0, 1)
2295 (define_insn "*cmpint_si"
2296 [(set (match_operand:SI 0 "register_operand" "=d")
2297 (unspec:SI [(reg:CCU 33)] UNSPEC_CMPINT))]
2300 output_asm_insn ("lhi\t%0,1", operands);
2301 output_asm_insn ("jh\t.+12", operands);
2302 output_asm_insn ("jl\t.+6", operands);
2303 output_asm_insn ("sr\t%0,%0", operands);
2304 return "lcr\t%0,%0";
2306 [(set_attr "op_type" "NN")
2307 (set_attr "length" "16")
2308 (set_attr "type" "other")])
2310 (define_insn "*cmpint_di"
2311 [(set (match_operand:DI 0 "register_operand" "=d")
2312 (sign_extend:DI (unspec:SI [(reg:CCU 33)] UNSPEC_CMPINT)))]
2315 output_asm_insn ("lghi\t%0,1", operands);
2316 output_asm_insn ("jh\t.+16", operands);
2317 output_asm_insn ("jl\t.+8", operands);
2318 output_asm_insn ("sgr\t%0,%0", operands);
2319 return "lcgr\t%0,%0";
2321 [(set_attr "op_type" "NN")
2322 (set_attr "length" "20")
2323 (set_attr "type" "other")])
2327 ;;- Conversion instructions.
2330 (define_insn "*sethighqisi"
2331 [(set (match_operand:SI 0 "register_operand" "=d,d")
2332 (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2333 (clobber (reg:CC 33))]
2338 [(set_attr "op_type" "RS,RSY")])
2340 (define_insn "*sethighhisi"
2341 [(set (match_operand:SI 0 "register_operand" "=d,d")
2342 (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2343 (clobber (reg:CC 33))]
2348 [(set_attr "op_type" "RS,RSY")])
2350 (define_insn "*sethighqidi_64"
2351 [(set (match_operand:DI 0 "register_operand" "=d")
2352 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2353 (clobber (reg:CC 33))]
2356 [(set_attr "op_type" "RSY")])
2358 (define_insn "*sethighqidi_31"
2359 [(set (match_operand:DI 0 "register_operand" "=d,d")
2360 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2361 (clobber (reg:CC 33))]
2366 [(set_attr "op_type" "RS,RSY")])
2368 (define_insn_and_split "*extractqi"
2369 [(set (match_operand:SI 0 "register_operand" "=d")
2370 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2371 (match_operand 2 "const_int_operand" "n")
2373 (clobber (reg:CC 33))]
2375 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2377 "&& reload_completed"
2379 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2380 (clobber (reg:CC 33))])
2381 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2383 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2384 operands[1] = change_address (operands[1], QImode, 0);
2386 [(set_attr "atype" "agen")])
2388 (define_insn_and_split "*extracthi"
2389 [(set (match_operand:SI 0 "register_operand" "=d")
2390 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2391 (match_operand 2 "const_int_operand" "n")
2393 (clobber (reg:CC 33))]
2395 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2397 "&& reload_completed"
2399 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2400 (clobber (reg:CC 33))])
2401 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2403 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2404 operands[1] = change_address (operands[1], HImode, 0);
2406 [(set_attr "atype" "agen")])
2409 ; extendsidi2 instruction pattern(s).
2412 (define_expand "extendsidi2"
2413 [(set (match_operand:DI 0 "register_operand" "")
2414 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2420 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2421 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2422 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2423 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2429 (define_insn "*extendsidi2"
2430 [(set (match_operand:DI 0 "register_operand" "=d,d")
2431 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2436 [(set_attr "op_type" "RRE,RXY")])
2439 ; extendhidi2 instruction pattern(s).
2442 (define_expand "extendhidi2"
2443 [(set (match_operand:DI 0 "register_operand" "")
2444 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2450 rtx tmp = gen_reg_rtx (SImode);
2451 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2452 emit_insn (gen_extendsidi2 (operands[0], tmp));
2457 operands[1] = gen_lowpart (DImode, operands[1]);
2458 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2459 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2465 (define_insn "*extendhidi2"
2466 [(set (match_operand:DI 0 "register_operand" "=d")
2467 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2470 [(set_attr "op_type" "RXY")])
2473 ; extendqidi2 instruction pattern(s).
2476 (define_expand "extendqidi2"
2477 [(set (match_operand:DI 0 "register_operand" "")
2478 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2484 rtx tmp = gen_reg_rtx (SImode);
2485 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2486 emit_insn (gen_extendsidi2 (operands[0], tmp));
2491 operands[1] = gen_lowpart (DImode, operands[1]);
2492 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2493 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2499 (define_insn "*extendqidi2"
2500 [(set (match_operand:DI 0 "register_operand" "=d")
2501 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2502 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2504 [(set_attr "op_type" "RXY")])
2506 (define_insn_and_split "*extendqidi2_short_displ"
2507 [(set (match_operand:DI 0 "register_operand" "=d")
2508 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2509 (clobber (reg:CC 33))]
2510 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2512 "&& reload_completed"
2514 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2515 (clobber (reg:CC 33))])
2517 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2518 (clobber (reg:CC 33))])]
2522 ; extendhisi2 instruction pattern(s).
2525 (define_expand "extendhisi2"
2526 [(set (match_operand:SI 0 "register_operand" "")
2527 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2531 operands[1] = gen_lowpart (SImode, operands[1]);
2532 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2533 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2538 (define_insn "*extendhisi2"
2539 [(set (match_operand:SI 0 "register_operand" "=d,d")
2540 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2545 [(set_attr "op_type" "RX,RXY")])
2548 ; extendqisi2 instruction pattern(s).
2551 (define_expand "extendqisi2"
2552 [(set (match_operand:SI 0 "register_operand" "")
2553 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2557 operands[1] = gen_lowpart (SImode, operands[1]);
2558 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2559 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2564 (define_insn "*extendqisi2"
2565 [(set (match_operand:SI 0 "register_operand" "=d")
2566 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2567 "TARGET_LONG_DISPLACEMENT"
2569 [(set_attr "op_type" "RXY")])
2571 (define_insn_and_split "*extendqisi2_short_displ"
2572 [(set (match_operand:SI 0 "register_operand" "=d")
2573 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2574 (clobber (reg:CC 33))]
2575 "!TARGET_LONG_DISPLACEMENT"
2577 "&& reload_completed"
2579 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2580 (clobber (reg:CC 33))])
2582 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2583 (clobber (reg:CC 33))])]
2587 ; extendqihi2 instruction pattern(s).
2592 ; zero_extendsidi2 instruction pattern(s).
2595 (define_expand "zero_extendsidi2"
2596 [(set (match_operand:DI 0 "register_operand" "")
2597 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2603 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2604 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2605 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2611 (define_insn "*zero_extendsidi2"
2612 [(set (match_operand:DI 0 "register_operand" "=d,d")
2613 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2618 [(set_attr "op_type" "RRE,RXY")])
2621 ; zero_extendhidi2 instruction pattern(s).
2624 (define_expand "zero_extendhidi2"
2625 [(set (match_operand:DI 0 "register_operand" "")
2626 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2632 rtx tmp = gen_reg_rtx (SImode);
2633 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2634 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2639 operands[1] = gen_lowpart (DImode, operands[1]);
2640 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2641 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2647 (define_insn "*zero_extendhidi2"
2648 [(set (match_operand:DI 0 "register_operand" "=d")
2649 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2652 [(set_attr "op_type" "RXY")])
2655 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2658 (define_insn "*llgt_sisi"
2659 [(set (match_operand:SI 0 "register_operand" "=d,d")
2660 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2661 (const_int 2147483647)))]
2666 [(set_attr "op_type" "RRE,RXE")])
2669 [(set (match_operand:SI 0 "register_operand" "")
2670 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2671 (const_int 2147483647)))
2672 (clobber (reg:CC 33))]
2673 "TARGET_64BIT && reload_completed"
2675 (and:SI (match_dup 1)
2676 (const_int 2147483647)))]
2679 (define_insn "*llgt_didi"
2680 [(set (match_operand:DI 0 "register_operand" "=d,d")
2681 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2682 (const_int 2147483647)))]
2687 [(set_attr "op_type" "RRE,RXE")])
2690 [(set (match_operand:DI 0 "register_operand" "")
2691 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
2692 (const_int 2147483647)))
2693 (clobber (reg:CC 33))]
2694 "TARGET_64BIT && reload_completed"
2696 (and:DI (match_dup 1)
2697 (const_int 2147483647)))]
2700 (define_insn "*llgt_sidi"
2701 [(set (match_operand:DI 0 "register_operand" "=d")
2702 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2703 (const_int 2147483647)))]
2706 [(set_attr "op_type" "RXE")])
2708 (define_insn_and_split "*llgt_sidi_split"
2709 [(set (match_operand:DI 0 "register_operand" "=d")
2710 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2711 (const_int 2147483647)))
2712 (clobber (reg:CC 33))]
2715 "&& reload_completed"
2717 (and:DI (subreg:DI (match_dup 1) 0)
2718 (const_int 2147483647)))]
2722 ; zero_extendqidi2 instruction pattern(s)
2725 (define_expand "zero_extendqidi2"
2726 [(set (match_operand:DI 0 "register_operand" "")
2727 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2733 rtx tmp = gen_reg_rtx (SImode);
2734 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2735 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2740 operands[1] = gen_lowpart (DImode, operands[1]);
2741 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2742 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2748 (define_insn "*zero_extendqidi2"
2749 [(set (match_operand:DI 0 "register_operand" "=d")
2750 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2753 [(set_attr "op_type" "RXY")])
2756 ; zero_extendhisi2 instruction pattern(s).
2759 (define_expand "zero_extendhisi2"
2760 [(set (match_operand:SI 0 "register_operand" "")
2761 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2765 operands[1] = gen_lowpart (SImode, operands[1]);
2766 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2771 (define_insn "*zero_extendhisi2_64"
2772 [(set (match_operand:SI 0 "register_operand" "=d")
2773 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2776 [(set_attr "op_type" "RXY")])
2778 (define_insn_and_split "*zero_extendhisi2_31"
2779 [(set (match_operand:SI 0 "register_operand" "=&d")
2780 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2781 (clobber (reg:CC 33))]
2784 "&& reload_completed"
2785 [(set (match_dup 0) (const_int 0))
2787 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2788 (clobber (reg:CC 33))])]
2789 "operands[2] = gen_lowpart (HImode, operands[0]);"
2790 [(set_attr "atype" "agen")])
2793 ; zero_extendqisi2 instruction pattern(s).
2796 (define_expand "zero_extendqisi2"
2797 [(set (match_operand:SI 0 "register_operand" "")
2798 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2802 operands[1] = gen_lowpart (SImode, operands[1]);
2803 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2808 (define_insn "*zero_extendqisi2_64"
2809 [(set (match_operand:SI 0 "register_operand" "=d")
2810 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2813 [(set_attr "op_type" "RXY")])
2815 (define_insn_and_split "*zero_extendqisi2_31"
2816 [(set (match_operand:SI 0 "register_operand" "=&d")
2817 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2820 "&& reload_completed"
2821 [(set (match_dup 0) (const_int 0))
2822 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2823 "operands[2] = gen_lowpart (QImode, operands[0]);"
2824 [(set_attr "atype" "agen")])
2827 ; zero_extendqihi2 instruction pattern(s).
2830 (define_expand "zero_extendqihi2"
2831 [(set (match_operand:HI 0 "register_operand" "")
2832 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2836 operands[1] = gen_lowpart (HImode, operands[1]);
2837 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2842 (define_insn "*zero_extendqihi2_64"
2843 [(set (match_operand:HI 0 "register_operand" "=d")
2844 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2847 [(set_attr "op_type" "RXY")])
2849 (define_insn_and_split "*zero_extendqihi2_31"
2850 [(set (match_operand:HI 0 "register_operand" "=&d")
2851 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2854 "&& reload_completed"
2855 [(set (match_dup 0) (const_int 0))
2856 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2857 "operands[2] = gen_lowpart (QImode, operands[0]);"
2858 [(set_attr "atype" "agen")])
2862 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2865 (define_expand "fixuns_truncdfdi2"
2866 [(set (match_operand:DI 0 "register_operand" "")
2867 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2868 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2870 rtx label1 = gen_label_rtx ();
2871 rtx label2 = gen_label_rtx ();
2872 rtx temp = gen_reg_rtx (DFmode);
2873 operands[1] = force_reg (DFmode, operands[1]);
2875 emit_insn (gen_cmpdf (operands[1],
2876 CONST_DOUBLE_FROM_REAL_VALUE (
2877 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2878 emit_jump_insn (gen_blt (label1));
2879 emit_insn (gen_subdf3 (temp, operands[1],
2880 CONST_DOUBLE_FROM_REAL_VALUE (
2881 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2882 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2885 emit_label (label1);
2886 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2887 emit_label (label2);
2891 (define_expand "fix_truncdfdi2"
2892 [(set (match_operand:DI 0 "register_operand" "")
2893 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2894 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2896 operands[1] = force_reg (DFmode, operands[1]);
2897 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2901 (define_insn "fix_truncdfdi2_ieee"
2902 [(set (match_operand:DI 0 "register_operand" "=d")
2903 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2904 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2905 (clobber (reg:CC 33))]
2906 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2908 [(set_attr "op_type" "RRE")
2909 (set_attr "type" "ftoi")])
2912 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2915 (define_expand "fixuns_truncdfsi2"
2916 [(set (match_operand:SI 0 "register_operand" "")
2917 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2918 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2920 rtx label1 = gen_label_rtx ();
2921 rtx label2 = gen_label_rtx ();
2922 rtx temp = gen_reg_rtx (DFmode);
2924 operands[1] = force_reg (DFmode,operands[1]);
2925 emit_insn (gen_cmpdf (operands[1],
2926 CONST_DOUBLE_FROM_REAL_VALUE (
2927 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2928 emit_jump_insn (gen_blt (label1));
2929 emit_insn (gen_subdf3 (temp, operands[1],
2930 CONST_DOUBLE_FROM_REAL_VALUE (
2931 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2932 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2935 emit_label (label1);
2936 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2937 emit_label (label2);
2941 (define_expand "fix_truncdfsi2"
2942 [(set (match_operand:SI 0 "register_operand" "")
2943 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2946 if (TARGET_IBM_FLOAT)
2948 /* This is the algorithm from POP chapter A.5.7.2. */
2950 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2951 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2952 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2954 operands[1] = force_reg (DFmode, operands[1]);
2955 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2956 two31r, two32, temp));
2960 operands[1] = force_reg (DFmode, operands[1]);
2961 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2967 (define_insn "fix_truncdfsi2_ieee"
2968 [(set (match_operand:SI 0 "register_operand" "=d")
2969 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2970 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2971 (clobber (reg:CC 33))]
2972 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2974 [(set_attr "op_type" "RRE")
2975 (set_attr "type" "ftoi")])
2977 (define_insn "fix_truncdfsi2_ibm"
2978 [(set (match_operand:SI 0 "register_operand" "=d")
2979 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2980 (use (match_operand:DI 2 "immediate_operand" "m"))
2981 (use (match_operand:DI 3 "immediate_operand" "m"))
2982 (use (match_operand:BLK 4 "memory_operand" "m"))
2983 (clobber (reg:CC 33))]
2984 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2986 output_asm_insn ("sd\t%1,%2", operands);
2987 output_asm_insn ("aw\t%1,%3", operands);
2988 output_asm_insn ("std\t%1,%4", operands);
2989 output_asm_insn ("xi\t%N4,128", operands);
2992 [(set_attr "op_type" "NN")
2993 (set_attr "type" "other")
2994 (set_attr "atype" "agen")
2995 (set_attr "length" "20")])
2998 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
3001 (define_expand "fixuns_truncsfdi2"
3002 [(set (match_operand:DI 0 "register_operand" "")
3003 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
3004 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3006 rtx label1 = gen_label_rtx ();
3007 rtx label2 = gen_label_rtx ();
3008 rtx temp = gen_reg_rtx (SFmode);
3010 operands[1] = force_reg (SFmode, operands[1]);
3011 emit_insn (gen_cmpsf (operands[1],
3012 CONST_DOUBLE_FROM_REAL_VALUE (
3013 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
3014 emit_jump_insn (gen_blt (label1));
3016 emit_insn (gen_subsf3 (temp, operands[1],
3017 CONST_DOUBLE_FROM_REAL_VALUE (
3018 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
3019 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
3022 emit_label (label1);
3023 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3024 emit_label (label2);
3028 (define_expand "fix_truncsfdi2"
3029 [(set (match_operand:DI 0 "register_operand" "")
3030 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
3031 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3033 operands[1] = force_reg (SFmode, operands[1]);
3034 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3038 (define_insn "fix_truncsfdi2_ieee"
3039 [(set (match_operand:DI 0 "register_operand" "=d")
3040 (fix:DI (match_operand:SF 1 "register_operand" "f")))
3041 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3042 (clobber (reg:CC 33))]
3043 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3045 [(set_attr "op_type" "RRE")
3046 (set_attr "type" "ftoi")])
3049 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
3052 (define_expand "fixuns_truncsfsi2"
3053 [(set (match_operand:SI 0 "register_operand" "")
3054 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3055 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3057 rtx label1 = gen_label_rtx ();
3058 rtx label2 = gen_label_rtx ();
3059 rtx temp = gen_reg_rtx (SFmode);
3061 operands[1] = force_reg (SFmode, operands[1]);
3062 emit_insn (gen_cmpsf (operands[1],
3063 CONST_DOUBLE_FROM_REAL_VALUE (
3064 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
3065 emit_jump_insn (gen_blt (label1));
3066 emit_insn (gen_subsf3 (temp, operands[1],
3067 CONST_DOUBLE_FROM_REAL_VALUE (
3068 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
3069 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
3072 emit_label (label1);
3073 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3074 emit_label (label2);
3078 (define_expand "fix_truncsfsi2"
3079 [(set (match_operand:SI 0 "register_operand" "")
3080 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3083 if (TARGET_IBM_FLOAT)
3085 /* Convert to DFmode and then use the POP algorithm. */
3086 rtx temp = gen_reg_rtx (DFmode);
3087 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3088 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3092 operands[1] = force_reg (SFmode, operands[1]);
3093 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3099 (define_insn "fix_truncsfsi2_ieee"
3100 [(set (match_operand:SI 0 "register_operand" "=d")
3101 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3102 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3103 (clobber (reg:CC 33))]
3104 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3106 [(set_attr "op_type" "RRE")
3107 (set_attr "type" "ftoi")])
3110 ; floatdidf2 instruction pattern(s).
3113 (define_insn "floatdidf2"
3114 [(set (match_operand:DF 0 "register_operand" "=f")
3115 (float:DF (match_operand:DI 1 "register_operand" "d")))]
3116 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3118 [(set_attr "op_type" "RRE")
3119 (set_attr "type" "itof" )])
3122 ; floatdisf2 instruction pattern(s).
3125 (define_insn "floatdisf2"
3126 [(set (match_operand:SF 0 "register_operand" "=f")
3127 (float:SF (match_operand:DI 1 "register_operand" "d")))]
3128 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3130 [(set_attr "op_type" "RRE")
3131 (set_attr "type" "itof" )])
3134 ; floatsidf2 instruction pattern(s).
3137 (define_expand "floatsidf2"
3138 [(set (match_operand:DF 0 "register_operand" "")
3139 (float:DF (match_operand:SI 1 "register_operand" "")))]
3142 if (TARGET_IBM_FLOAT)
3144 /* This is the algorithm from POP chapter A.5.7.1. */
3146 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3147 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3149 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3154 (define_insn "floatsidf2_ieee"
3155 [(set (match_operand:DF 0 "register_operand" "=f")
3156 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3157 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3159 [(set_attr "op_type" "RRE")
3160 (set_attr "type" "itof" )])
3162 (define_insn "floatsidf2_ibm"
3163 [(set (match_operand:DF 0 "register_operand" "=f")
3164 (float:DF (match_operand:SI 1 "register_operand" "d")))
3165 (use (match_operand:DI 2 "immediate_operand" "m"))
3166 (use (match_operand:BLK 3 "memory_operand" "m"))
3167 (clobber (reg:CC 33))]
3168 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3170 output_asm_insn ("st\t%1,%N3", operands);
3171 output_asm_insn ("xi\t%N3,128", operands);
3172 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3173 output_asm_insn ("ld\t%0,%3", operands);
3176 [(set_attr "op_type" "NN")
3177 (set_attr "type" "other" )
3178 (set_attr "atype" "agen")
3179 (set_attr "length" "20")])
3182 ; floatsisf2 instruction pattern(s).
3185 (define_expand "floatsisf2"
3186 [(set (match_operand:SF 0 "register_operand" "")
3187 (float:SF (match_operand:SI 1 "register_operand" "")))]
3190 if (TARGET_IBM_FLOAT)
3192 /* Use the POP algorithm to convert to DFmode and then truncate. */
3193 rtx temp = gen_reg_rtx (DFmode);
3194 emit_insn (gen_floatsidf2 (temp, operands[1]));
3195 emit_insn (gen_truncdfsf2 (operands[0], temp));
3200 (define_insn "floatsisf2_ieee"
3201 [(set (match_operand:SF 0 "register_operand" "=f")
3202 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3203 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3205 [(set_attr "op_type" "RRE")
3206 (set_attr "type" "itof" )])
3209 ; truncdfsf2 instruction pattern(s).
3212 (define_expand "truncdfsf2"
3213 [(set (match_operand:SF 0 "register_operand" "")
3214 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3218 (define_insn "truncdfsf2_ieee"
3219 [(set (match_operand:SF 0 "register_operand" "=f")
3220 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3221 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3223 [(set_attr "op_type" "RRE")])
3225 (define_insn "truncdfsf2_ibm"
3226 [(set (match_operand:SF 0 "register_operand" "=f,f")
3227 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3228 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3232 [(set_attr "op_type" "RR,RX")
3233 (set_attr "type" "floads,floads")])
3236 ; extendsfdf2 instruction pattern(s).
3239 (define_expand "extendsfdf2"
3240 [(set (match_operand:DF 0 "register_operand" "")
3241 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3244 if (TARGET_IBM_FLOAT)
3246 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3251 (define_insn "extendsfdf2_ieee"
3252 [(set (match_operand:DF 0 "register_operand" "=f,f")
3253 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3254 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3258 [(set_attr "op_type" "RRE,RXE")
3259 (set_attr "type" "floads,floads")])
3261 (define_insn "extendsfdf2_ibm"
3262 [(set (match_operand:DF 0 "register_operand" "=f,f")
3263 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3264 (clobber (reg:CC 33))]
3265 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3267 sdr\t%0,%0\;ler\t%0,%1
3268 sdr\t%0,%0\;le\t%0,%1"
3269 [(set_attr "op_type" "NN,NN")
3270 (set_attr "length" "4,6")
3271 (set_attr "type" "floads,floads")])
3275 ;; ARITHMETIC OPERATIONS
3277 ; arithmetic operations set the ConditionCode,
3278 ; because of unpredictable Bits in Register for Halfword and Byte
3279 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3282 ;;- Add instructions.
3286 ; addti3 instruction pattern(s).
3289 (define_insn_and_split "addti3"
3290 [(set (match_operand:TI 0 "register_operand" "=&d")
3291 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3292 (match_operand:TI 2 "general_operand" "do") ) )
3293 (clobber (reg:CC 33))]
3296 "&& reload_completed"
3299 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3301 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3303 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3304 (ltu:DI (reg:CCL1 33) (const_int 0))))
3305 (clobber (reg:CC 33))])]
3306 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3307 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3308 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3309 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3310 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3311 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
3312 [(set_attr "op_type" "NN")])
3315 ; adddi3 instruction pattern(s).
3318 (define_insn "*adddi3_sign"
3319 [(set (match_operand:DI 0 "register_operand" "=d,d")
3320 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3321 (match_operand:DI 1 "register_operand" "0,0")))
3322 (clobber (reg:CC 33))]
3327 [(set_attr "op_type" "RRE,RXY")])
3329 (define_insn "*adddi3_zero_cc"
3331 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3332 (match_operand:DI 1 "register_operand" "0,0"))
3334 (set (match_operand:DI 0 "register_operand" "=d,d")
3335 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3336 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3340 [(set_attr "op_type" "RRE,RXY")])
3342 (define_insn "*adddi3_zero_cconly"
3344 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3345 (match_operand:DI 1 "register_operand" "0,0"))
3347 (clobber (match_scratch:DI 0 "=d,d"))]
3348 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3352 [(set_attr "op_type" "RRE,RXY")])
3354 (define_insn "*adddi3_zero"
3355 [(set (match_operand:DI 0 "register_operand" "=d,d")
3356 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3357 (match_operand:DI 1 "register_operand" "0,0")))
3358 (clobber (reg:CC 33))]
3363 [(set_attr "op_type" "RRE,RXY")])
3365 (define_insn "*adddi3_imm_cc"
3367 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3368 (match_operand:DI 2 "const_int_operand" "K"))
3370 (set (match_operand:DI 0 "register_operand" "=d")
3371 (plus:DI (match_dup 1) (match_dup 2)))]
3373 && s390_match_ccmode (insn, CCAmode)
3374 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3376 [(set_attr "op_type" "RI")])
3378 (define_insn "*adddi3_carry1_cc"
3380 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3381 (match_operand:DI 2 "general_operand" "d,m"))
3383 (set (match_operand:DI 0 "register_operand" "=d,d")
3384 (plus:DI (match_dup 1) (match_dup 2)))]
3385 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3389 [(set_attr "op_type" "RRE,RXY")])
3391 (define_insn "*adddi3_carry1_cconly"
3393 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3394 (match_operand:DI 2 "general_operand" "d,m"))
3396 (clobber (match_scratch:DI 0 "=d,d"))]
3397 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3401 [(set_attr "op_type" "RRE,RXY")])
3403 (define_insn "*adddi3_carry2_cc"
3405 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3406 (match_operand:DI 2 "general_operand" "d,m"))
3408 (set (match_operand:DI 0 "register_operand" "=d,d")
3409 (plus:DI (match_dup 1) (match_dup 2)))]
3410 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3414 [(set_attr "op_type" "RRE,RXY")])
3416 (define_insn "*adddi3_carry2_cconly"
3418 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3419 (match_operand:DI 2 "general_operand" "d,m"))
3421 (clobber (match_scratch:DI 0 "=d,d"))]
3422 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3426 [(set_attr "op_type" "RRE,RXY")])
3428 (define_insn "*adddi3_cc"
3430 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3431 (match_operand:DI 2 "general_operand" "d,m"))
3433 (set (match_operand:DI 0 "register_operand" "=d,d")
3434 (plus:DI (match_dup 1) (match_dup 2)))]
3435 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3439 [(set_attr "op_type" "RRE,RXY")])
3441 (define_insn "*adddi3_cconly"
3443 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3444 (match_operand:DI 2 "general_operand" "d,m"))
3446 (clobber (match_scratch:DI 0 "=d,d"))]
3447 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3451 [(set_attr "op_type" "RRE,RXY")])
3453 (define_insn "*adddi3_cconly2"
3455 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3456 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3457 (clobber (match_scratch:DI 0 "=d,d"))]
3458 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3462 [(set_attr "op_type" "RRE,RXY")])
3464 (define_insn "*adddi3_64"
3465 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3466 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3467 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3468 (clobber (reg:CC 33))]
3474 [(set_attr "op_type" "RRE,RI,RXY")])
3476 (define_insn_and_split "*adddi3_31z"
3477 [(set (match_operand:DI 0 "register_operand" "=&d")
3478 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3479 (match_operand:DI 2 "general_operand" "do") ) )
3480 (clobber (reg:CC 33))]
3481 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3483 "&& reload_completed"
3486 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3488 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3490 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3491 (ltu:SI (reg:CCL1 33) (const_int 0))))
3492 (clobber (reg:CC 33))])]
3493 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3494 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3495 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3496 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3497 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3498 operands[8] = operand_subword (operands[2], 1, 0, DImode);"
3499 [(set_attr "op_type" "NN")])
3501 (define_insn_and_split "*adddi3_31"
3502 [(set (match_operand:DI 0 "register_operand" "=&d")
3503 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3504 (match_operand:DI 2 "general_operand" "do") ) )
3505 (clobber (reg:CC 33))]
3508 "&& reload_completed"
3510 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3511 (clobber (reg:CC 33))])
3514 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3516 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3518 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3520 (label_ref (match_dup 9))))
3522 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3523 (clobber (reg:CC 33))])
3525 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3526 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3527 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3528 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3529 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3530 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3531 operands[9] = gen_label_rtx ();"
3532 [(set_attr "op_type" "NN")])
3534 (define_expand "adddi3"
3536 [(set (match_operand:DI 0 "register_operand" "")
3537 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3538 (match_operand:DI 2 "general_operand" "")))
3539 (clobber (reg:CC 33))])]
3544 ; addsi3 instruction pattern(s).
3547 (define_insn "*addsi3_imm_cc"
3549 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3550 (match_operand:SI 2 "const_int_operand" "K"))
3552 (set (match_operand:SI 0 "register_operand" "=d")
3553 (plus:SI (match_dup 1) (match_dup 2)))]
3554 "s390_match_ccmode (insn, CCAmode)
3555 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3557 [(set_attr "op_type" "RI")])
3559 (define_insn "*addsi3_carry1_cc"
3561 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3562 (match_operand:SI 2 "general_operand" "d,R,T"))
3564 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3565 (plus:SI (match_dup 1) (match_dup 2)))]
3566 "s390_match_ccmode (insn, CCL1mode)"
3571 [(set_attr "op_type" "RR,RX,RXY")])
3573 (define_insn "*addsi3_carry1_cconly"
3575 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3576 (match_operand:SI 2 "general_operand" "d,R,T"))
3578 (clobber (match_scratch:SI 0 "=d,d,d"))]
3579 "s390_match_ccmode (insn, CCL1mode)"
3584 [(set_attr "op_type" "RR,RX,RXY")])
3586 (define_insn "*addsi3_carry2_cc"
3588 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3589 (match_operand:SI 2 "general_operand" "d,R,T"))
3591 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3592 (plus:SI (match_dup 1) (match_dup 2)))]
3593 "s390_match_ccmode (insn, CCL1mode)"
3598 [(set_attr "op_type" "RR,RX,RXY")])
3600 (define_insn "*addsi3_carry2_cconly"
3602 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3603 (match_operand:SI 2 "general_operand" "d,R,T"))
3605 (clobber (match_scratch:SI 0 "=d,d,d"))]
3606 "s390_match_ccmode (insn, CCL1mode)"
3611 [(set_attr "op_type" "RR,RX,RXY")])
3613 (define_insn "*addsi3_cc"
3615 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3616 (match_operand:SI 2 "general_operand" "d,R,T"))
3618 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3619 (plus:SI (match_dup 1) (match_dup 2)))]
3620 "s390_match_ccmode (insn, CCLmode)"
3625 [(set_attr "op_type" "RR,RX,RXY")])
3627 (define_insn "*addsi3_cconly"
3629 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3630 (match_operand:SI 2 "general_operand" "d,R,T"))
3632 (clobber (match_scratch:SI 0 "=d,d,d"))]
3633 "s390_match_ccmode (insn, CCLmode)"
3638 [(set_attr "op_type" "RR,RX,RXY")])
3640 (define_insn "*addsi3_cconly2"
3642 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3643 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3644 (clobber (match_scratch:SI 0 "=d,d,d"))]
3645 "s390_match_ccmode (insn, CCLmode)"
3650 [(set_attr "op_type" "RR,RX,RXY")])
3652 (define_insn "*addsi3_sign"
3653 [(set (match_operand:SI 0 "register_operand" "=d,d")
3654 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3655 (match_operand:SI 1 "register_operand" "0,0")))
3656 (clobber (reg:CC 33))]
3661 [(set_attr "op_type" "RX,RXY")])
3663 (define_insn "addsi3"
3664 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3665 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3666 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3667 (clobber (reg:CC 33))]
3674 [(set_attr "op_type" "RR,RI,RX,RXY")])
3677 ; adddf3 instruction pattern(s).
3680 (define_expand "adddf3"
3682 [(set (match_operand:DF 0 "register_operand" "=f,f")
3683 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3684 (match_operand:DF 2 "general_operand" "f,R")))
3685 (clobber (reg:CC 33))])]
3689 (define_insn "*adddf3"
3690 [(set (match_operand:DF 0 "register_operand" "=f,f")
3691 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3692 (match_operand:DF 2 "general_operand" "f,R")))
3693 (clobber (reg:CC 33))]
3694 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3698 [(set_attr "op_type" "RRE,RXE")
3699 (set_attr "type" "fsimpd,fsimpd")])
3701 (define_insn "*adddf3_cc"
3703 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3704 (match_operand:DF 2 "general_operand" "f,R"))
3705 (match_operand:DF 3 "const0_operand" "")))
3706 (set (match_operand:DF 0 "register_operand" "=f,f")
3707 (plus:DF (match_dup 1) (match_dup 2)))]
3708 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3712 [(set_attr "op_type" "RRE,RXE")
3713 (set_attr "type" "fsimpd,fsimpd")])
3715 (define_insn "*adddf3_cconly"
3717 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3718 (match_operand:DF 2 "general_operand" "f,R"))
3719 (match_operand:DF 3 "const0_operand" "")))
3720 (clobber (match_scratch:DF 0 "=f,f"))]
3721 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3725 [(set_attr "op_type" "RRE,RXE")
3726 (set_attr "type" "fsimpd,fsimpd")])
3728 (define_insn "*adddf3_ibm"
3729 [(set (match_operand:DF 0 "register_operand" "=f,f")
3730 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3731 (match_operand:DF 2 "general_operand" "f,R")))
3732 (clobber (reg:CC 33))]
3733 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3737 [(set_attr "op_type" "RR,RX")
3738 (set_attr "type" "fsimpd,fsimpd")])
3741 ; addsf3 instruction pattern(s).
3744 (define_expand "addsf3"
3746 [(set (match_operand:SF 0 "register_operand" "=f,f")
3747 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3748 (match_operand:SF 2 "general_operand" "f,R")))
3749 (clobber (reg:CC 33))])]
3753 (define_insn "*addsf3"
3754 [(set (match_operand:SF 0 "register_operand" "=f,f")
3755 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3756 (match_operand:SF 2 "general_operand" "f,R")))
3757 (clobber (reg:CC 33))]
3758 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3762 [(set_attr "op_type" "RRE,RXE")
3763 (set_attr "type" "fsimps,fsimps")])
3765 (define_insn "*addsf3_cc"
3767 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3768 (match_operand:SF 2 "general_operand" "f,R"))
3769 (match_operand:SF 3 "const0_operand" "")))
3770 (set (match_operand:SF 0 "register_operand" "=f,f")
3771 (plus:SF (match_dup 1) (match_dup 2)))]
3772 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3776 [(set_attr "op_type" "RRE,RXE")
3777 (set_attr "type" "fsimps,fsimps")])
3779 (define_insn "*addsf3_cconly"
3781 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3782 (match_operand:SF 2 "general_operand" "f,R"))
3783 (match_operand:SF 3 "const0_operand" "")))
3784 (clobber (match_scratch:SF 0 "=f,f"))]
3785 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3789 [(set_attr "op_type" "RRE,RXE")
3790 (set_attr "type" "fsimps,fsimps")])
3792 (define_insn "*addsf3"
3793 [(set (match_operand:SF 0 "register_operand" "=f,f")
3794 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3795 (match_operand:SF 2 "general_operand" "f,R")))
3796 (clobber (reg:CC 33))]
3797 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3801 [(set_attr "op_type" "RR,RX")
3802 (set_attr "type" "fsimps,fsimps")])
3806 ;;- Subtract instructions.
3810 ; subti3 instruction pattern(s).
3813 (define_insn_and_split "subti3"
3814 [(set (match_operand:TI 0 "register_operand" "=&d")
3815 (minus:TI (match_operand:TI 1 "register_operand" "0")
3816 (match_operand:TI 2 "general_operand" "do") ) )
3817 (clobber (reg:CC 33))]
3820 "&& reload_completed"
3823 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3825 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3827 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3828 (gtu:DI (reg:CCL2 33) (const_int 0))))
3829 (clobber (reg:CC 33))])]
3830 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3831 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3832 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3833 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3834 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3835 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
3836 [(set_attr "op_type" "NN")])
3839 ; subdi3 instruction pattern(s).
3842 (define_insn "*subdi3_sign"
3843 [(set (match_operand:DI 0 "register_operand" "=d,d")
3844 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3845 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3846 (clobber (reg:CC 33))]
3851 [(set_attr "op_type" "RRE,RXY")])
3853 (define_insn "*subdi3_zero_cc"
3855 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3856 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3858 (set (match_operand:DI 0 "register_operand" "=d,d")
3859 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3860 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3864 [(set_attr "op_type" "RRE,RXY")])
3866 (define_insn "*subdi3_zero_cconly"
3868 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3869 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3871 (clobber (match_scratch:DI 0 "=d,d"))]
3872 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3876 [(set_attr "op_type" "RRE,RXY")])
3878 (define_insn "*subdi3_zero"
3879 [(set (match_operand:DI 0 "register_operand" "=d,d")
3880 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3881 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3882 (clobber (reg:CC 33))]
3887 [(set_attr "op_type" "RRE,RXY")])
3889 (define_insn "*subdi3_borrow_cc"
3891 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3892 (match_operand:DI 2 "general_operand" "d,m"))
3894 (set (match_operand:DI 0 "register_operand" "=d,d")
3895 (minus:DI (match_dup 1) (match_dup 2)))]
3896 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3900 [(set_attr "op_type" "RRE,RXY")])
3902 (define_insn "*subdi3_borrow_cconly"
3904 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3905 (match_operand:DI 2 "general_operand" "d,m"))
3907 (clobber (match_scratch:DI 0 "=d,d"))]
3908 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3912 [(set_attr "op_type" "RRE,RXY")])
3914 (define_insn "*subdi3_cc"
3916 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3917 (match_operand:DI 2 "general_operand" "d,m"))
3919 (set (match_operand:DI 0 "register_operand" "=d,d")
3920 (minus:DI (match_dup 1) (match_dup 2)))]
3921 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3925 [(set_attr "op_type" "RRE,RXY")])
3927 (define_insn "*subdi3_cc2"
3929 (compare (match_operand:DI 1 "register_operand" "0,0")
3930 (match_operand:DI 2 "general_operand" "d,m")))
3931 (set (match_operand:DI 0 "register_operand" "=d,d")
3932 (minus:DI (match_dup 1) (match_dup 2)))]
3933 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3937 [(set_attr "op_type" "RRE,RXY")])
3939 (define_insn "*subdi3_cconly"
3941 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3942 (match_operand:DI 2 "general_operand" "d,m"))
3944 (clobber (match_scratch:DI 0 "=d,d"))]
3945 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3949 [(set_attr "op_type" "RRE,RXY")])
3951 (define_insn "*subdi3_cconly2"
3953 (compare (match_operand:DI 1 "register_operand" "0,0")
3954 (match_operand:DI 2 "general_operand" "d,m")))
3955 (clobber (match_scratch:DI 0 "=d,d"))]
3956 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3960 [(set_attr "op_type" "RRE,RXY")])
3962 (define_insn "*subdi3_64"
3963 [(set (match_operand:DI 0 "register_operand" "=d,d")
3964 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3965 (match_operand:DI 2 "general_operand" "d,m") ) )
3966 (clobber (reg:CC 33))]
3971 [(set_attr "op_type" "RRE,RRE")])
3973 (define_insn_and_split "*subdi3_31z"
3974 [(set (match_operand:DI 0 "register_operand" "=&d")
3975 (minus:DI (match_operand:DI 1 "register_operand" "0")
3976 (match_operand:DI 2 "general_operand" "do") ) )
3977 (clobber (reg:CC 33))]
3978 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3980 "&& reload_completed"
3983 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3985 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3987 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3988 (gtu:SI (reg:CCL2 33) (const_int 0))))
3989 (clobber (reg:CC 33))])]
3990 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3991 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3992 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3993 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3994 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3995 operands[8] = operand_subword (operands[2], 1, 0, DImode);"
3996 [(set_attr "op_type" "NN")])
3998 (define_insn_and_split "*subdi3_31"
3999 [(set (match_operand:DI 0 "register_operand" "=&d")
4000 (minus:DI (match_operand:DI 1 "register_operand" "0")
4001 (match_operand:DI 2 "general_operand" "do") ) )
4002 (clobber (reg:CC 33))]
4005 "&& reload_completed"
4007 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4008 (clobber (reg:CC 33))])
4011 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4013 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4015 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
4017 (label_ref (match_dup 9))))
4019 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4020 (clobber (reg:CC 33))])
4022 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4023 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4024 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4025 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4026 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4027 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4028 operands[9] = gen_label_rtx ();"
4029 [(set_attr "op_type" "NN")])
4031 (define_expand "subdi3"
4033 [(set (match_operand:DI 0 "register_operand" "")
4034 (minus:DI (match_operand:DI 1 "register_operand" "")
4035 (match_operand:DI 2 "general_operand" "")))
4036 (clobber (reg:CC 33))])]
4041 ; subsi3 instruction pattern(s).
4044 (define_insn "*subsi3_borrow_cc"
4046 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4047 (match_operand:SI 2 "general_operand" "d,R,T"))
4049 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4050 (minus:SI (match_dup 1) (match_dup 2)))]
4051 "s390_match_ccmode (insn, CCL2mode)"
4056 [(set_attr "op_type" "RR,RX,RXY")])
4058 (define_insn "*subsi3_borrow_cconly"
4060 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4061 (match_operand:SI 2 "general_operand" "d,R,T"))
4063 (clobber (match_scratch:SI 0 "=d,d,d"))]
4064 "s390_match_ccmode (insn, CCL2mode)"
4069 [(set_attr "op_type" "RR,RX,RXY")])
4071 (define_insn "*subsi3_cc"
4073 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4074 (match_operand:SI 2 "general_operand" "d,R,T"))
4076 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4077 (minus:SI (match_dup 1) (match_dup 2)))]
4078 "s390_match_ccmode (insn, CCLmode)"
4083 [(set_attr "op_type" "RR,RX,RXY")])
4085 (define_insn "*subsi3_cc2"
4087 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4088 (match_operand:SI 2 "general_operand" "d,R,T")))
4089 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4090 (minus:SI (match_dup 1) (match_dup 2)))]
4091 "s390_match_ccmode (insn, CCL3mode)"
4096 [(set_attr "op_type" "RR,RX,RXY")])
4098 (define_insn "*subsi3_cconly"
4100 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4101 (match_operand:SI 2 "general_operand" "d,R,T"))
4103 (clobber (match_scratch:SI 0 "=d,d,d"))]
4104 "s390_match_ccmode (insn, CCLmode)"
4109 [(set_attr "op_type" "RR,RX,RXY")])
4111 (define_insn "*subsi3_cconly2"
4113 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4114 (match_operand:SI 2 "general_operand" "d,R,T")))
4115 (clobber (match_scratch:SI 0 "=d,d,d"))]
4116 "s390_match_ccmode (insn, CCL3mode)"
4121 [(set_attr "op_type" "RR,RX,RXY")])
4123 (define_insn "*subsi3_sign"
4124 [(set (match_operand:SI 0 "register_operand" "=d,d")
4125 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4126 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4127 (clobber (reg:CC 33))]
4132 [(set_attr "op_type" "RX,RXY")])
4134 (define_insn "subsi3"
4135 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4136 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4137 (match_operand:SI 2 "general_operand" "d,R,T")))
4138 (clobber (reg:CC 33))]
4144 [(set_attr "op_type" "RR,RX,RXY")])
4148 ; subdf3 instruction pattern(s).
4151 (define_expand "subdf3"
4153 [(set (match_operand:DF 0 "register_operand" "=f,f")
4154 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4155 (match_operand:DF 2 "general_operand" "f,R")))
4156 (clobber (reg:CC 33))])]
4160 (define_insn "*subdf3"
4161 [(set (match_operand:DF 0 "register_operand" "=f,f")
4162 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4163 (match_operand:DF 2 "general_operand" "f,R")))
4164 (clobber (reg:CC 33))]
4165 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4169 [(set_attr "op_type" "RRE,RXE")
4170 (set_attr "type" "fsimpd,fsimpd")])
4172 (define_insn "*subdf3_cc"
4174 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4175 (match_operand:DF 2 "general_operand" "f,R"))
4176 (match_operand:DF 3 "const0_operand" "")))
4177 (set (match_operand:DF 0 "register_operand" "=f,f")
4178 (minus:DF (match_dup 1) (match_dup 2)))]
4179 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4183 [(set_attr "op_type" "RRE,RXE")
4184 (set_attr "type" "fsimpd,fsimpd")])
4186 (define_insn "*subdf3_cconly"
4188 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4189 (match_operand:DF 2 "general_operand" "f,R"))
4190 (match_operand:DF 3 "const0_operand" "")))
4191 (clobber (match_scratch:DF 0 "=f,f"))]
4192 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4196 [(set_attr "op_type" "RRE,RXE")
4197 (set_attr "type" "fsimpd,fsimpd")])
4199 (define_insn "*subdf3_ibm"
4200 [(set (match_operand:DF 0 "register_operand" "=f,f")
4201 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4202 (match_operand:DF 2 "general_operand" "f,R")))
4203 (clobber (reg:CC 33))]
4204 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4208 [(set_attr "op_type" "RR,RX")
4209 (set_attr "type" "fsimpd,fsimpd")])
4212 ; subsf3 instruction pattern(s).
4215 (define_expand "subsf3"
4217 [(set (match_operand:SF 0 "register_operand" "=f,f")
4218 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4219 (match_operand:SF 2 "general_operand" "f,R")))
4220 (clobber (reg:CC 33))])]
4224 (define_insn "*subsf3"
4225 [(set (match_operand:SF 0 "register_operand" "=f,f")
4226 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4227 (match_operand:SF 2 "general_operand" "f,R")))
4228 (clobber (reg:CC 33))]
4229 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4233 [(set_attr "op_type" "RRE,RXE")
4234 (set_attr "type" "fsimps,fsimps")])
4236 (define_insn "*subsf3_cc"
4238 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4239 (match_operand:SF 2 "general_operand" "f,R"))
4240 (match_operand:SF 3 "const0_operand" "")))
4241 (set (match_operand:SF 0 "register_operand" "=f,f")
4242 (minus:SF (match_dup 1) (match_dup 2)))]
4243 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4247 [(set_attr "op_type" "RRE,RXE")
4248 (set_attr "type" "fsimps,fsimps")])
4250 (define_insn "*subsf3_cconly"
4252 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4253 (match_operand:SF 2 "general_operand" "f,R"))
4254 (match_operand:SF 3 "const0_operand" "")))
4255 (clobber (match_scratch:SF 0 "=f,f"))]
4256 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4260 [(set_attr "op_type" "RRE,RXE")
4261 (set_attr "type" "fsimps,fsimps")])
4263 (define_insn "*subsf3_ibm"
4264 [(set (match_operand:SF 0 "register_operand" "=f,f")
4265 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4266 (match_operand:SF 2 "general_operand" "f,R")))
4267 (clobber (reg:CC 33))]
4268 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4272 [(set_attr "op_type" "RR,RX")
4273 (set_attr "type" "fsimps,fsimps")])
4277 ;;- Conditional add/subtract instructions.
4281 ; adddicc instruction pattern(s).
4284 (define_insn "*adddi3_alc_cc"
4287 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4288 (match_operand:DI 2 "general_operand" "d,m"))
4289 (match_operand:DI 3 "s390_alc_comparison" ""))
4291 (set (match_operand:DI 0 "register_operand" "=d,d")
4292 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4293 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4297 [(set_attr "op_type" "RRE,RXY")])
4299 (define_insn "*adddi3_alc"
4300 [(set (match_operand:DI 0 "register_operand" "=d,d")
4301 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4302 (match_operand:DI 2 "general_operand" "d,m"))
4303 (match_operand:DI 3 "s390_alc_comparison" "")))
4304 (clobber (reg:CC 33))]
4309 [(set_attr "op_type" "RRE,RXY")])
4311 (define_insn "*subdi3_slb_cc"
4314 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4315 (match_operand:DI 2 "general_operand" "d,m"))
4316 (match_operand:DI 3 "s390_slb_comparison" ""))
4318 (set (match_operand:DI 0 "register_operand" "=d,d")
4319 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4320 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4324 [(set_attr "op_type" "RRE,RXY")])
4326 (define_insn "*subdi3_slb"
4327 [(set (match_operand:DI 0 "register_operand" "=d,d")
4328 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4329 (match_operand:DI 2 "general_operand" "d,m"))
4330 (match_operand:DI 3 "s390_slb_comparison" "")))
4331 (clobber (reg:CC 33))]
4336 [(set_attr "op_type" "RRE,RXY")])
4338 (define_expand "adddicc"
4339 [(match_operand:DI 0 "register_operand" "")
4340 (match_operand 1 "comparison_operator" "")
4341 (match_operand:DI 2 "register_operand" "")
4342 (match_operand:DI 3 "const_int_operand" "")]
4344 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4345 s390_compare_op0, s390_compare_op1,
4346 operands[0], operands[2],
4347 operands[3])) FAIL; DONE;")
4350 ; addsicc instruction pattern(s).
4353 (define_insn "*addsi3_alc_cc"
4356 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4357 (match_operand:SI 2 "general_operand" "d,m"))
4358 (match_operand:SI 3 "s390_alc_comparison" ""))
4360 (set (match_operand:SI 0 "register_operand" "=d,d")
4361 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4362 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4366 [(set_attr "op_type" "RRE,RXY")])
4368 (define_insn "*addsi3_alc"
4369 [(set (match_operand:SI 0 "register_operand" "=d,d")
4370 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4371 (match_operand:SI 2 "general_operand" "d,m"))
4372 (match_operand:SI 3 "s390_alc_comparison" "")))
4373 (clobber (reg:CC 33))]
4378 [(set_attr "op_type" "RRE,RXY")])
4380 (define_insn "*subsi3_slb_cc"
4383 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4384 (match_operand:SI 2 "general_operand" "d,m"))
4385 (match_operand:SI 3 "s390_slb_comparison" ""))
4387 (set (match_operand:SI 0 "register_operand" "=d,d")
4388 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4389 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4393 [(set_attr "op_type" "RRE,RXY")])
4395 (define_insn "*subsi3_slb"
4396 [(set (match_operand:SI 0 "register_operand" "=d,d")
4397 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4398 (match_operand:SI 2 "general_operand" "d,m"))
4399 (match_operand:SI 3 "s390_slb_comparison" "")))
4400 (clobber (reg:CC 33))]
4405 [(set_attr "op_type" "RRE,RXY")])
4407 (define_expand "addsicc"
4408 [(match_operand:SI 0 "register_operand" "")
4409 (match_operand 1 "comparison_operator" "")
4410 (match_operand:SI 2 "register_operand" "")
4411 (match_operand:SI 3 "const_int_operand" "")]
4413 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4414 s390_compare_op0, s390_compare_op1,
4415 operands[0], operands[2],
4416 operands[3])) FAIL; DONE;")
4419 ; scond instruction pattern(s).
4422 (define_insn_and_split "*sconddi"
4423 [(set (match_operand:DI 0 "register_operand" "=&d")
4424 (match_operand:DI 1 "s390_alc_comparison" ""))
4425 (clobber (reg:CC 33))]
4428 "&& reload_completed"
4429 [(set (match_dup 0) (const_int 0))
4431 [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
4433 (clobber (reg:CC 33))])]
4435 [(set_attr "op_type" "NN")])
4437 (define_insn_and_split "*scondsi"
4438 [(set (match_operand:SI 0 "register_operand" "=&d")
4439 (match_operand:SI 1 "s390_alc_comparison" ""))
4440 (clobber (reg:CC 33))]
4443 "&& reload_completed"
4444 [(set (match_dup 0) (const_int 0))
4446 [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
4448 (clobber (reg:CC 33))])]
4450 [(set_attr "op_type" "NN")])
4452 (define_insn_and_split "*sconddi_neg"
4453 [(set (match_operand:DI 0 "register_operand" "=&d")
4454 (match_operand:DI 1 "s390_slb_comparison" ""))
4455 (clobber (reg:CC 33))]
4458 "&& reload_completed"
4459 [(set (match_dup 0) (const_int 0))
4461 [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
4463 (clobber (reg:CC 33))])
4465 [(set (match_dup 0) (neg:DI (match_dup 0)))
4466 (clobber (reg:CC 33))])]
4468 [(set_attr "op_type" "NN")])
4470 (define_insn_and_split "*scondsi_neg"
4471 [(set (match_operand:SI 0 "register_operand" "=&d")
4472 (match_operand:SI 1 "s390_slb_comparison" ""))
4473 (clobber (reg:CC 33))]
4476 "&& reload_completed"
4477 [(set (match_dup 0) (const_int 0))
4479 [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
4481 (clobber (reg:CC 33))])
4483 [(set (match_dup 0) (neg:SI (match_dup 0)))
4484 (clobber (reg:CC 33))])]
4486 [(set_attr "op_type" "NN")])
4488 (define_expand "sltu"
4489 [(match_operand:SI 0 "register_operand" "")]
4491 "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
4492 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4494 (define_expand "sgtu"
4495 [(match_operand:SI 0 "register_operand" "")]
4497 "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
4498 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4500 (define_expand "sleu"
4501 [(match_operand:SI 0 "register_operand" "")]
4503 "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
4504 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4506 (define_expand "sgeu"
4507 [(match_operand:SI 0 "register_operand" "")]
4509 "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
4510 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4514 ;;- Multiply instructions.
4518 ; muldi3 instruction pattern(s).
4521 (define_insn "*muldi3_sign"
4522 [(set (match_operand:DI 0 "register_operand" "=d,d")
4523 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4524 (match_operand:DI 1 "register_operand" "0,0")))]
4529 [(set_attr "op_type" "RRE,RXY")
4530 (set_attr "type" "imul")])
4532 (define_insn "muldi3"
4533 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4534 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4535 (match_operand:DI 2 "general_operand" "d,K,m")))]
4541 [(set_attr "op_type" "RRE,RI,RXY")
4542 (set_attr "type" "imul")])
4545 ; mulsi3 instruction pattern(s).
4548 (define_insn "*mulsi3_sign"
4549 [(set (match_operand:SI 0 "register_operand" "=d")
4550 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4551 (match_operand:SI 1 "register_operand" "0")))]
4554 [(set_attr "op_type" "RX")
4555 (set_attr "type" "imul")])
4557 (define_insn "mulsi3"
4558 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4559 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4560 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4567 [(set_attr "op_type" "RRE,RI,RX,RXY")
4568 (set_attr "type" "imul")])
4571 ; mulsidi3 instruction pattern(s).
4574 (define_insn "mulsidi3"
4575 [(set (match_operand:DI 0 "register_operand" "=d,d")
4576 (mult:DI (sign_extend:DI
4577 (match_operand:SI 1 "register_operand" "%0,0"))
4579 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4584 [(set_attr "op_type" "RR,RX")
4585 (set_attr "type" "imul")])
4588 ; umulsidi3 instruction pattern(s).
4591 (define_insn "umulsidi3"
4592 [(set (match_operand:DI 0 "register_operand" "=d,d")
4593 (mult:DI (zero_extend:DI
4594 (match_operand:SI 1 "register_operand" "%0,0"))
4596 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4597 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4601 [(set_attr "op_type" "RRE,RXY")
4602 (set_attr "type" "imul")])
4605 ; muldf3 instruction pattern(s).
4608 (define_expand "muldf3"
4609 [(set (match_operand:DF 0 "register_operand" "=f,f")
4610 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4611 (match_operand:DF 2 "general_operand" "f,R")))]
4615 (define_insn "*muldf3"
4616 [(set (match_operand:DF 0 "register_operand" "=f,f")
4617 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4618 (match_operand:DF 2 "general_operand" "f,R")))]
4619 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4623 [(set_attr "op_type" "RRE,RXE")
4624 (set_attr "type" "fmuld")])
4626 (define_insn "*muldf3_ibm"
4627 [(set (match_operand:DF 0 "register_operand" "=f,f")
4628 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4629 (match_operand:DF 2 "general_operand" "f,R")))]
4630 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4634 [(set_attr "op_type" "RR,RX")
4635 (set_attr "type" "fmuld")])
4637 (define_insn "*fmadddf"
4638 [(set (match_operand:DF 0 "register_operand" "=f,f")
4639 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
4640 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4641 (match_operand:DF 3 "register_operand" "0,0")))]
4642 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4646 [(set_attr "op_type" "RRE,RXE")
4647 (set_attr "type" "fmuld")])
4649 (define_insn "*fmsubdf"
4650 [(set (match_operand:DF 0 "register_operand" "=f,f")
4651 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
4652 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4653 (match_operand:DF 3 "register_operand" "0,0")))]
4654 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4658 [(set_attr "op_type" "RRE,RXE")
4659 (set_attr "type" "fmuld")])
4662 ; mulsf3 instruction pattern(s).
4665 (define_expand "mulsf3"
4666 [(set (match_operand:SF 0 "register_operand" "=f,f")
4667 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4668 (match_operand:SF 2 "general_operand" "f,R")))]
4672 (define_insn "*mulsf3"
4673 [(set (match_operand:SF 0 "register_operand" "=f,f")
4674 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4675 (match_operand:SF 2 "general_operand" "f,R")))]
4676 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4680 [(set_attr "op_type" "RRE,RXE")
4681 (set_attr "type" "fmuls")])
4683 (define_insn "*mulsf3_ibm"
4684 [(set (match_operand:SF 0 "register_operand" "=f,f")
4685 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4686 (match_operand:SF 2 "general_operand" "f,R")))]
4687 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4691 [(set_attr "op_type" "RR,RX")
4692 (set_attr "type" "fmuls")])
4694 (define_insn "*fmaddsf"
4695 [(set (match_operand:SF 0 "register_operand" "=f,f")
4696 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
4697 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4698 (match_operand:SF 3 "register_operand" "0,0")))]
4699 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4703 [(set_attr "op_type" "RRE,RXE")
4704 (set_attr "type" "fmuls")])
4706 (define_insn "*fmsubsf"
4707 [(set (match_operand:SF 0 "register_operand" "=f,f")
4708 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
4709 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4710 (match_operand:SF 3 "register_operand" "0,0")))]
4711 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4715 [(set_attr "op_type" "RRE,RXE")
4716 (set_attr "type" "fmuls")])
4719 ;;- Divide and modulo instructions.
4723 ; divmoddi4 instruction pattern(s).
4726 (define_expand "divmoddi4"
4727 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4728 (div:DI (match_operand:DI 1 "register_operand" "")
4729 (match_operand:DI 2 "general_operand" "")))
4730 (set (match_operand:DI 3 "general_operand" "")
4731 (mod:DI (match_dup 1) (match_dup 2)))])
4732 (clobber (match_dup 4))]
4735 rtx insn, div_equal, mod_equal;
4737 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4738 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4740 operands[4] = gen_reg_rtx(TImode);
4741 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4743 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4745 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4747 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4749 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4754 (define_insn "divmodtidi3"
4755 [(set (match_operand:TI 0 "register_operand" "=d,d")
4759 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4760 (match_operand:DI 2 "general_operand" "d,m")))
4762 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4767 [(set_attr "op_type" "RRE,RXY")
4768 (set_attr "type" "idiv")])
4770 (define_insn "divmodtisi3"
4771 [(set (match_operand:TI 0 "register_operand" "=d,d")
4775 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4777 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4780 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4785 [(set_attr "op_type" "RRE,RXY")
4786 (set_attr "type" "idiv")])
4789 ; udivmoddi4 instruction pattern(s).
4792 (define_expand "udivmoddi4"
4793 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4794 (udiv:DI (match_operand:DI 1 "general_operand" "")
4795 (match_operand:DI 2 "nonimmediate_operand" "")))
4796 (set (match_operand:DI 3 "general_operand" "")
4797 (umod:DI (match_dup 1) (match_dup 2)))])
4798 (clobber (match_dup 4))]
4801 rtx insn, div_equal, mod_equal, equal;
4803 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4804 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4805 equal = gen_rtx_IOR (TImode,
4806 gen_rtx_ASHIFT (TImode,
4807 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4809 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4811 operands[4] = gen_reg_rtx(TImode);
4812 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4813 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4814 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4815 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4817 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4819 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4821 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4823 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4825 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4830 (define_insn "udivmodtidi3"
4831 [(set (match_operand:TI 0 "register_operand" "=d,d")
4836 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4838 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4842 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4847 [(set_attr "op_type" "RRE,RXY")
4848 (set_attr "type" "idiv")])
4851 ; divmodsi4 instruction pattern(s).
4854 (define_expand "divmodsi4"
4855 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4856 (div:SI (match_operand:SI 1 "general_operand" "")
4857 (match_operand:SI 2 "nonimmediate_operand" "")))
4858 (set (match_operand:SI 3 "general_operand" "")
4859 (mod:SI (match_dup 1) (match_dup 2)))])
4860 (clobber (match_dup 4))]
4863 rtx insn, div_equal, mod_equal, equal;
4865 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4866 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4867 equal = gen_rtx_IOR (DImode,
4868 gen_rtx_ASHIFT (DImode,
4869 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4871 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4873 operands[4] = gen_reg_rtx(DImode);
4874 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4875 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4877 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4879 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4881 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4883 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4885 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4890 (define_insn "divmoddisi3"
4891 [(set (match_operand:DI 0 "register_operand" "=d,d")
4896 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4898 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4902 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4907 [(set_attr "op_type" "RR,RX")
4908 (set_attr "type" "idiv")])
4911 ; udivsi3 and umodsi3 instruction pattern(s).
4914 (define_expand "udivmodsi4"
4915 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4916 (udiv:SI (match_operand:SI 1 "general_operand" "")
4917 (match_operand:SI 2 "nonimmediate_operand" "")))
4918 (set (match_operand:SI 3 "general_operand" "")
4919 (umod:SI (match_dup 1) (match_dup 2)))])
4920 (clobber (match_dup 4))]
4921 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4923 rtx insn, div_equal, mod_equal, equal;
4925 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4926 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4927 equal = gen_rtx_IOR (DImode,
4928 gen_rtx_ASHIFT (DImode,
4929 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4931 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4933 operands[4] = gen_reg_rtx(DImode);
4934 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4935 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4936 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4937 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4939 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4941 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4943 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4945 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4947 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4952 (define_insn "udivmoddisi3"
4953 [(set (match_operand:DI 0 "register_operand" "=d,d")
4958 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4960 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4964 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4965 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4969 [(set_attr "op_type" "RRE,RXY")
4970 (set_attr "type" "idiv")])
4972 (define_expand "udivsi3"
4973 [(set (match_operand:SI 0 "register_operand" "=d")
4974 (udiv:SI (match_operand:SI 1 "general_operand" "")
4975 (match_operand:SI 2 "general_operand" "")))
4976 (clobber (match_dup 3))]
4977 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4979 rtx insn, udiv_equal, umod_equal, equal;
4981 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4982 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4983 equal = gen_rtx_IOR (DImode,
4984 gen_rtx_ASHIFT (DImode,
4985 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4987 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4989 operands[3] = gen_reg_rtx (DImode);
4991 if (CONSTANT_P (operands[2]))
4993 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4995 rtx label1 = gen_label_rtx ();
4997 operands[1] = make_safe_from (operands[1], operands[0]);
4998 emit_move_insn (operands[0], const0_rtx);
4999 emit_insn (gen_cmpsi (operands[1], operands[2]));
5000 emit_jump_insn (gen_bltu (label1));
5001 emit_move_insn (operands[0], const1_rtx);
5002 emit_label (label1);
5006 operands[2] = force_reg (SImode, operands[2]);
5007 operands[2] = make_safe_from (operands[2], operands[0]);
5009 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5010 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5013 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5015 insn = emit_move_insn (operands[0],
5016 gen_lowpart (SImode, operands[3]));
5018 gen_rtx_EXPR_LIST (REG_EQUAL,
5019 udiv_equal, REG_NOTES (insn));
5024 rtx label1 = gen_label_rtx ();
5025 rtx label2 = gen_label_rtx ();
5026 rtx label3 = gen_label_rtx ();
5028 operands[1] = force_reg (SImode, operands[1]);
5029 operands[1] = make_safe_from (operands[1], operands[0]);
5030 operands[2] = force_reg (SImode, operands[2]);
5031 operands[2] = make_safe_from (operands[2], operands[0]);
5033 emit_move_insn (operands[0], const0_rtx);
5034 emit_insn (gen_cmpsi (operands[2], operands[1]));
5035 emit_jump_insn (gen_bgtu (label3));
5036 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5037 emit_jump_insn (gen_blt (label2));
5038 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5039 emit_jump_insn (gen_beq (label1));
5040 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5041 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5044 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5046 insn = emit_move_insn (operands[0],
5047 gen_lowpart (SImode, operands[3]));
5049 gen_rtx_EXPR_LIST (REG_EQUAL,
5050 udiv_equal, REG_NOTES (insn));
5052 emit_label (label1);
5053 emit_move_insn (operands[0], operands[1]);
5055 emit_label (label2);
5056 emit_move_insn (operands[0], const1_rtx);
5057 emit_label (label3);
5059 emit_move_insn (operands[0], operands[0]);
5063 (define_expand "umodsi3"
5064 [(set (match_operand:SI 0 "register_operand" "=d")
5065 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5066 (match_operand:SI 2 "nonimmediate_operand" "")))
5067 (clobber (match_dup 3))]
5068 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5070 rtx insn, udiv_equal, umod_equal, equal;
5072 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5073 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5074 equal = gen_rtx_IOR (DImode,
5075 gen_rtx_ASHIFT (DImode,
5076 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5078 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5080 operands[3] = gen_reg_rtx (DImode);
5082 if (CONSTANT_P (operands[2]))
5084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5086 rtx label1 = gen_label_rtx ();
5088 operands[1] = make_safe_from (operands[1], operands[0]);
5089 emit_move_insn (operands[0], operands[1]);
5090 emit_insn (gen_cmpsi (operands[0], operands[2]));
5091 emit_jump_insn (gen_bltu (label1));
5092 emit_insn (gen_abssi2 (operands[0], operands[2]));
5093 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5094 emit_label (label1);
5098 operands[2] = force_reg (SImode, operands[2]);
5099 operands[2] = make_safe_from (operands[2], operands[0]);
5101 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5102 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5105 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5107 insn = emit_move_insn (operands[0],
5108 gen_highpart (SImode, operands[3]));
5110 gen_rtx_EXPR_LIST (REG_EQUAL,
5111 umod_equal, REG_NOTES (insn));
5116 rtx label1 = gen_label_rtx ();
5117 rtx label2 = gen_label_rtx ();
5118 rtx label3 = gen_label_rtx ();
5120 operands[1] = force_reg (SImode, operands[1]);
5121 operands[1] = make_safe_from (operands[1], operands[0]);
5122 operands[2] = force_reg (SImode, operands[2]);
5123 operands[2] = make_safe_from (operands[2], operands[0]);
5125 emit_move_insn(operands[0], operands[1]);
5126 emit_insn (gen_cmpsi (operands[2], operands[1]));
5127 emit_jump_insn (gen_bgtu (label3));
5128 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5129 emit_jump_insn (gen_blt (label2));
5130 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5131 emit_jump_insn (gen_beq (label1));
5132 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5133 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5136 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5138 insn = emit_move_insn (operands[0],
5139 gen_highpart (SImode, operands[3]));
5141 gen_rtx_EXPR_LIST (REG_EQUAL,
5142 umod_equal, REG_NOTES (insn));
5144 emit_label (label1);
5145 emit_move_insn (operands[0], const0_rtx);
5147 emit_label (label2);
5148 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5149 emit_label (label3);
5155 ; divdf3 instruction pattern(s).
5158 (define_expand "divdf3"
5159 [(set (match_operand:DF 0 "register_operand" "=f,f")
5160 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5161 (match_operand:DF 2 "general_operand" "f,R")))]
5165 (define_insn "*divdf3"
5166 [(set (match_operand:DF 0 "register_operand" "=f,f")
5167 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5168 (match_operand:DF 2 "general_operand" "f,R")))]
5169 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5173 [(set_attr "op_type" "RRE,RXE")
5174 (set_attr "type" "fdivd")])
5176 (define_insn "*divdf3_ibm"
5177 [(set (match_operand:DF 0 "register_operand" "=f,f")
5178 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5179 (match_operand:DF 2 "general_operand" "f,R")))]
5180 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5184 [(set_attr "op_type" "RR,RX")
5185 (set_attr "type" "fdivd")])
5188 ; divsf3 instruction pattern(s).
5191 (define_expand "divsf3"
5192 [(set (match_operand:SF 0 "register_operand" "=f,f")
5193 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5194 (match_operand:SF 2 "general_operand" "f,R")))]
5198 (define_insn "*divsf3"
5199 [(set (match_operand:SF 0 "register_operand" "=f,f")
5200 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5201 (match_operand:SF 2 "general_operand" "f,R")))]
5202 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5206 [(set_attr "op_type" "RRE,RXE")
5207 (set_attr "type" "fdivs")])
5209 (define_insn "*divsf3"
5210 [(set (match_operand:SF 0 "register_operand" "=f,f")
5211 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5212 (match_operand:SF 2 "general_operand" "f,R")))]
5213 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5217 [(set_attr "op_type" "RR,RX")
5218 (set_attr "type" "fdivs")])
5222 ;;- And instructions.
5226 ; anddi3 instruction pattern(s).
5229 (define_insn "*anddi3_cc"
5231 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5232 (match_operand:DI 2 "general_operand" "d,m"))
5234 (set (match_operand:DI 0 "register_operand" "=d,d")
5235 (and:DI (match_dup 1) (match_dup 2)))]
5236 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5240 [(set_attr "op_type" "RRE,RXY")])
5242 (define_insn "*anddi3_cconly"
5244 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5245 (match_operand:DI 2 "general_operand" "d,m"))
5247 (clobber (match_scratch:DI 0 "=d,d"))]
5248 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5249 /* Do not steal TM patterns. */
5250 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5254 [(set_attr "op_type" "RRE,RXY")])
5256 (define_insn "*anddi3"
5257 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5258 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5259 "%d,o,0,0,0,0,0,0,0,0")
5260 (match_operand:DI 2 "general_operand"
5261 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5262 (clobber (reg:CC 33))]
5263 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5275 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5278 [(set (match_operand:DI 0 "s_operand" "")
5279 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5280 (clobber (reg:CC 33))]
5283 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5284 (clobber (reg:CC 33))])]
5285 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5287 (define_expand "anddi3"
5288 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5289 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
5290 (match_operand:DI 2 "general_operand" "")))
5291 (clobber (reg:CC 33))]
5293 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
5296 ; andsi3 instruction pattern(s).
5299 (define_insn "*andsi3_cc"
5301 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5302 (match_operand:SI 2 "general_operand" "d,R,T"))
5304 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5305 (and:SI (match_dup 1) (match_dup 2)))]
5306 "s390_match_ccmode(insn, CCTmode)"
5311 [(set_attr "op_type" "RR,RX,RXY")])
5313 (define_insn "*andsi3_cconly"
5315 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5316 (match_operand:SI 2 "general_operand" "d,R,T"))
5318 (clobber (match_scratch:SI 0 "=d,d,d"))]
5319 "s390_match_ccmode(insn, CCTmode)
5320 /* Do not steal TM patterns. */
5321 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5326 [(set_attr "op_type" "RR,RX,RXY")])
5328 (define_insn "*andsi3_zarch"
5329 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
5330 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5331 "%d,o,0,0,0,0,0,0,0")
5332 (match_operand:SI 2 "general_operand"
5333 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
5334 (clobber (reg:CC 33))]
5335 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5346 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
5348 (define_insn "*andsi3_esa"
5349 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5350 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5351 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5352 (clobber (reg:CC 33))]
5353 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5359 [(set_attr "op_type" "RR,RX,SI,SS")])
5362 [(set (match_operand:SI 0 "s_operand" "")
5363 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5364 (clobber (reg:CC 33))]
5367 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5368 (clobber (reg:CC 33))])]
5369 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5371 (define_expand "andsi3"
5372 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5373 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
5374 (match_operand:SI 2 "general_operand" "")))
5375 (clobber (reg:CC 33))]
5377 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
5380 ; andhi3 instruction pattern(s).
5383 (define_insn "*andhi3_zarch"
5384 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5385 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5386 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5387 (clobber (reg:CC 33))]
5388 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5394 [(set_attr "op_type" "RR,RI,SI,SS")])
5396 (define_insn "*andhi3_esa"
5397 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5398 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5399 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5400 (clobber (reg:CC 33))]
5401 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5406 [(set_attr "op_type" "RR,SI,SS")])
5409 [(set (match_operand:HI 0 "s_operand" "")
5410 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5411 (clobber (reg:CC 33))]
5414 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5415 (clobber (reg:CC 33))])]
5416 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5418 (define_expand "andhi3"
5419 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5420 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
5421 (match_operand:HI 2 "general_operand" "")))
5422 (clobber (reg:CC 33))]
5424 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
5427 ; andqi3 instruction pattern(s).
5430 (define_insn "*andqi3_zarch"
5431 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5432 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5433 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5434 (clobber (reg:CC 33))]
5435 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5442 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5444 (define_insn "*andqi3_esa"
5445 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5446 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5447 (match_operand:QI 2 "general_operand" "d,n,Q")))
5448 (clobber (reg:CC 33))]
5449 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5454 [(set_attr "op_type" "RR,SI,SS")])
5456 (define_expand "andqi3"
5457 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5458 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
5459 (match_operand:QI 2 "general_operand" "")))
5460 (clobber (reg:CC 33))]
5462 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
5465 ; Block and (NC) patterns.
5469 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5470 (and:BLK (match_dup 0)
5471 (match_operand:BLK 1 "memory_operand" "Q")))
5472 (use (match_operand 2 "const_int_operand" "n"))
5473 (clobber (reg:CC 33))]
5474 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5475 "nc\t%O0(%2,%R0),%S1"
5476 [(set_attr "op_type" "SS")
5477 (set_attr "type" "cs")])
5480 [(set (match_operand 0 "memory_operand" "")
5482 (match_operand 1 "memory_operand" "")))
5483 (clobber (reg:CC 33))]
5485 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5486 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5488 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5490 (clobber (reg:CC 33))])]
5492 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5493 operands[0] = adjust_address (operands[0], BLKmode, 0);
5494 operands[1] = adjust_address (operands[1], BLKmode, 0);
5499 [(set (match_operand:BLK 0 "memory_operand" "")
5500 (and:BLK (match_dup 0)
5501 (match_operand:BLK 1 "memory_operand" "")))
5502 (use (match_operand 2 "const_int_operand" ""))
5503 (clobber (reg:CC 33))])
5505 [(set (match_operand:BLK 3 "memory_operand" "")
5506 (and:BLK (match_dup 3)
5507 (match_operand:BLK 4 "memory_operand" "")))
5508 (use (match_operand 5 "const_int_operand" ""))
5509 (clobber (reg:CC 33))])]
5510 "s390_offset_p (operands[0], operands[3], operands[2])
5511 && s390_offset_p (operands[1], operands[4], operands[2])
5512 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5514 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5516 (clobber (reg:CC 33))])]
5517 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5518 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5519 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5523 ;;- Bit set (inclusive or) instructions.
5527 ; iordi3 instruction pattern(s).
5530 (define_insn "*iordi3_cc"
5532 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5533 (match_operand:DI 2 "general_operand" "d,m"))
5535 (set (match_operand:DI 0 "register_operand" "=d,d")
5536 (ior:DI (match_dup 1) (match_dup 2)))]
5537 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5541 [(set_attr "op_type" "RRE,RXY")])
5543 (define_insn "*iordi3_cconly"
5545 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5546 (match_operand:DI 2 "general_operand" "d,m"))
5548 (clobber (match_scratch:DI 0 "=d,d"))]
5549 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5553 [(set_attr "op_type" "RRE,RXY")])
5555 (define_insn "*iordi3"
5556 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5557 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0,0,0")
5558 (match_operand:DI 2 "general_operand"
5559 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5560 (clobber (reg:CC 33))]
5561 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5571 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5574 [(set (match_operand:DI 0 "s_operand" "")
5575 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5576 (clobber (reg:CC 33))]
5579 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5580 (clobber (reg:CC 33))])]
5581 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5583 (define_expand "iordi3"
5584 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5585 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5586 (match_operand:DI 2 "general_operand" "")))
5587 (clobber (reg:CC 33))]
5589 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5592 ; iorsi3 instruction pattern(s).
5595 (define_insn "*iorsi3_cc"
5597 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5598 (match_operand:SI 2 "general_operand" "d,R,T"))
5600 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5601 (ior:SI (match_dup 1) (match_dup 2)))]
5602 "s390_match_ccmode(insn, CCTmode)"
5607 [(set_attr "op_type" "RR,RX,RXY")])
5609 (define_insn "*iorsi3_cconly"
5611 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5612 (match_operand:SI 2 "general_operand" "d,R,T"))
5614 (clobber (match_scratch:SI 0 "=d,d,d"))]
5615 "s390_match_ccmode(insn, CCTmode)"
5620 [(set_attr "op_type" "RR,RX,RXY")])
5622 (define_insn "*iorsi3_zarch"
5623 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5624 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0,0,0")
5625 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5626 (clobber (reg:CC 33))]
5627 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5636 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5638 (define_insn "*iorsi3_esa"
5639 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5640 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0")
5641 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5642 (clobber (reg:CC 33))]
5643 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5649 [(set_attr "op_type" "RR,RX,SI,SS")])
5652 [(set (match_operand:SI 0 "s_operand" "")
5653 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5654 (clobber (reg:CC 33))]
5657 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5658 (clobber (reg:CC 33))])]
5659 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5661 (define_expand "iorsi3"
5662 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5663 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5664 (match_operand:SI 2 "general_operand" "")))
5665 (clobber (reg:CC 33))]
5667 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5670 ; iorhi3 instruction pattern(s).
5673 (define_insn "*iorhi3_zarch"
5674 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5675 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5676 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5677 (clobber (reg:CC 33))]
5678 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5684 [(set_attr "op_type" "RR,RI,SI,SS")])
5686 (define_insn "*iorhi3_esa"
5687 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5688 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5689 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5690 (clobber (reg:CC 33))]
5691 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5696 [(set_attr "op_type" "RR,SI,SS")])
5699 [(set (match_operand:HI 0 "s_operand" "")
5700 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5701 (clobber (reg:CC 33))]
5704 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5705 (clobber (reg:CC 33))])]
5706 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5708 (define_expand "iorhi3"
5709 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5710 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5711 (match_operand:HI 2 "general_operand" "")))
5712 (clobber (reg:CC 33))]
5714 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5717 ; iorqi3 instruction pattern(s).
5720 (define_insn "*iorqi3_zarch"
5721 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5722 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5723 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5724 (clobber (reg:CC 33))]
5725 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5732 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5734 (define_insn "*iorqi3_esa"
5735 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5736 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5737 (match_operand:QI 2 "general_operand" "d,n,Q")))
5738 (clobber (reg:CC 33))]
5739 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5744 [(set_attr "op_type" "RR,SI,SS")])
5746 (define_expand "iorqi3"
5747 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5748 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5749 (match_operand:QI 2 "general_operand" "")))
5750 (clobber (reg:CC 33))]
5752 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5755 ; Block inclusive or (OC) patterns.
5759 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5760 (ior:BLK (match_dup 0)
5761 (match_operand:BLK 1 "memory_operand" "Q")))
5762 (use (match_operand 2 "const_int_operand" "n"))
5763 (clobber (reg:CC 33))]
5764 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5765 "oc\t%O0(%2,%R0),%S1"
5766 [(set_attr "op_type" "SS")
5767 (set_attr "type" "cs")])
5770 [(set (match_operand 0 "memory_operand" "")
5772 (match_operand 1 "memory_operand" "")))
5773 (clobber (reg:CC 33))]
5775 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5776 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5778 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5780 (clobber (reg:CC 33))])]
5782 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5783 operands[0] = adjust_address (operands[0], BLKmode, 0);
5784 operands[1] = adjust_address (operands[1], BLKmode, 0);
5789 [(set (match_operand:BLK 0 "memory_operand" "")
5790 (ior:BLK (match_dup 0)
5791 (match_operand:BLK 1 "memory_operand" "")))
5792 (use (match_operand 2 "const_int_operand" ""))
5793 (clobber (reg:CC 33))])
5795 [(set (match_operand:BLK 3 "memory_operand" "")
5796 (ior:BLK (match_dup 3)
5797 (match_operand:BLK 4 "memory_operand" "")))
5798 (use (match_operand 5 "const_int_operand" ""))
5799 (clobber (reg:CC 33))])]
5800 "s390_offset_p (operands[0], operands[3], operands[2])
5801 && s390_offset_p (operands[1], operands[4], operands[2])
5802 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5804 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5806 (clobber (reg:CC 33))])]
5807 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5808 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5809 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5813 ;;- Xor instructions.
5817 ; xordi3 instruction pattern(s).
5820 (define_insn "*xordi3_cc"
5822 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5823 (match_operand:DI 2 "general_operand" "d,m"))
5825 (set (match_operand:DI 0 "register_operand" "=d,d")
5826 (xor:DI (match_dup 1) (match_dup 2)))]
5827 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5831 [(set_attr "op_type" "RRE,RXY")])
5833 (define_insn "*xordi3_cconly"
5835 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5836 (match_operand:DI 2 "general_operand" "d,m"))
5838 (clobber (match_scratch:DI 0 "=d,d"))]
5839 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5843 [(set_attr "op_type" "RRE,RXY")])
5845 (define_insn "*xordi3"
5846 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5847 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5848 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5849 (clobber (reg:CC 33))]
5850 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5856 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5859 [(set (match_operand:DI 0 "s_operand" "")
5860 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5861 (clobber (reg:CC 33))]
5864 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5865 (clobber (reg:CC 33))])]
5866 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5868 (define_expand "xordi3"
5869 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5870 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5871 (match_operand:DI 2 "general_operand" "")))
5872 (clobber (reg:CC 33))]
5874 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5877 ; xorsi3 instruction pattern(s).
5880 (define_insn "*xorsi3_cc"
5882 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5883 (match_operand:SI 2 "general_operand" "d,R,T"))
5885 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5886 (xor:SI (match_dup 1) (match_dup 2)))]
5887 "s390_match_ccmode(insn, CCTmode)"
5892 [(set_attr "op_type" "RR,RX,RXY")])
5894 (define_insn "*xorsi3_cconly"
5896 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5897 (match_operand:SI 2 "general_operand" "d,R,T"))
5899 (clobber (match_scratch:SI 0 "=d,d,d"))]
5900 "s390_match_ccmode(insn, CCTmode)"
5905 [(set_attr "op_type" "RR,RX,RXY")])
5907 (define_insn "*xorsi3"
5908 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5909 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5910 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5911 (clobber (reg:CC 33))]
5912 "s390_logical_operator_ok_p (operands)"
5919 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5922 [(set (match_operand:SI 0 "s_operand" "")
5923 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5924 (clobber (reg:CC 33))]
5927 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5928 (clobber (reg:CC 33))])]
5929 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5931 (define_expand "xorsi3"
5932 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5933 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5934 (match_operand:SI 2 "general_operand" "")))
5935 (clobber (reg:CC 33))]
5937 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5940 ; xorhi3 instruction pattern(s).
5943 (define_insn "*xorhi3"
5944 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5945 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5946 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5947 (clobber (reg:CC 33))]
5948 "s390_logical_operator_ok_p (operands)"
5953 [(set_attr "op_type" "RR,SI,SS")])
5956 [(set (match_operand:HI 0 "s_operand" "")
5957 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5958 (clobber (reg:CC 33))]
5961 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5962 (clobber (reg:CC 33))])]
5963 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5965 (define_expand "xorhi3"
5966 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5967 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5968 (match_operand:HI 2 "general_operand" "")))
5969 (clobber (reg:CC 33))]
5971 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5974 ; xorqi3 instruction pattern(s).
5977 (define_insn "*xorqi3"
5978 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5979 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5980 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5981 (clobber (reg:CC 33))]
5982 "s390_logical_operator_ok_p (operands)"
5988 [(set_attr "op_type" "RR,SI,SIY,SS")])
5990 (define_expand "xorqi3"
5991 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5992 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5993 (match_operand:QI 2 "general_operand" "")))
5994 (clobber (reg:CC 33))]
5996 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5999 ; Block exclusive or (XC) patterns.
6003 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6004 (xor:BLK (match_dup 0)
6005 (match_operand:BLK 1 "memory_operand" "Q")))
6006 (use (match_operand 2 "const_int_operand" "n"))
6007 (clobber (reg:CC 33))]
6008 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6009 "xc\t%O0(%2,%R0),%S1"
6010 [(set_attr "op_type" "SS")
6011 (set_attr "type" "cs")])
6014 [(set (match_operand 0 "memory_operand" "")
6016 (match_operand 1 "memory_operand" "")))
6017 (clobber (reg:CC 33))]
6019 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6020 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6022 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6024 (clobber (reg:CC 33))])]
6026 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6027 operands[0] = adjust_address (operands[0], BLKmode, 0);
6028 operands[1] = adjust_address (operands[1], BLKmode, 0);
6033 [(set (match_operand:BLK 0 "memory_operand" "")
6034 (xor:BLK (match_dup 0)
6035 (match_operand:BLK 1 "memory_operand" "")))
6036 (use (match_operand 2 "const_int_operand" ""))
6037 (clobber (reg:CC 33))])
6039 [(set (match_operand:BLK 3 "memory_operand" "")
6040 (xor:BLK (match_dup 3)
6041 (match_operand:BLK 4 "memory_operand" "")))
6042 (use (match_operand 5 "const_int_operand" ""))
6043 (clobber (reg:CC 33))])]
6044 "s390_offset_p (operands[0], operands[3], operands[2])
6045 && s390_offset_p (operands[1], operands[4], operands[2])
6046 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6048 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6050 (clobber (reg:CC 33))])]
6051 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6052 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6053 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6056 ; Block xor (XC) patterns with src == dest.
6059 (define_insn "*xc_zero"
6060 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6062 (use (match_operand 1 "const_int_operand" "n"))
6063 (clobber (reg:CC 33))]
6064 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6065 "xc\t%O0(%1,%R0),%S0"
6066 [(set_attr "op_type" "SS")
6067 (set_attr "type" "cs")])
6071 [(set (match_operand:BLK 0 "memory_operand" "")
6073 (use (match_operand 1 "const_int_operand" ""))
6074 (clobber (reg:CC 33))])
6076 [(set (match_operand:BLK 2 "memory_operand" "")
6078 (use (match_operand 3 "const_int_operand" ""))
6079 (clobber (reg:CC 33))])]
6080 "s390_offset_p (operands[0], operands[2], operands[1])
6081 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6083 [(set (match_dup 4) (const_int 0))
6085 (clobber (reg:CC 33))])]
6086 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6087 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6091 ;;- Negate instructions.
6095 ; negdi2 instruction pattern(s).
6098 (define_expand "negdi2"
6100 [(set (match_operand:DI 0 "register_operand" "=d")
6101 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6102 (clobber (reg:CC 33))])]
6106 (define_insn "*negdi2_64"
6107 [(set (match_operand:DI 0 "register_operand" "=d")
6108 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6109 (clobber (reg:CC 33))]
6112 [(set_attr "op_type" "RR")])
6114 (define_insn "*negdi2_31"
6115 [(set (match_operand:DI 0 "register_operand" "=d")
6116 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6117 (clobber (reg:CC 33))]
6121 xop[0] = gen_label_rtx ();
6122 output_asm_insn ("lcr\t%0,%1", operands);
6123 output_asm_insn ("lcr\t%N0,%N1", operands);
6124 output_asm_insn ("je\t%l0", xop);
6125 output_asm_insn ("bctr\t%0,0", operands);
6126 targetm.asm_out.internal_label (asm_out_file, "L",
6127 CODE_LABEL_NUMBER (xop[0]));
6130 [(set_attr "op_type" "NN")
6131 (set_attr "type" "other")
6132 (set_attr "length" "10")])
6135 ; negsi2 instruction pattern(s).
6138 (define_insn "negsi2"
6139 [(set (match_operand:SI 0 "register_operand" "=d")
6140 (neg:SI (match_operand:SI 1 "register_operand" "d")))
6141 (clobber (reg:CC 33))]
6144 [(set_attr "op_type" "RR")])
6147 ; negdf2 instruction pattern(s).
6150 (define_expand "negdf2"
6152 [(set (match_operand:DF 0 "register_operand" "=f")
6153 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6154 (clobber (reg:CC 33))])]
6158 (define_insn "*negdf2"
6159 [(set (match_operand:DF 0 "register_operand" "=f")
6160 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6161 (clobber (reg:CC 33))]
6162 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6164 [(set_attr "op_type" "RRE")
6165 (set_attr "type" "fsimpd")])
6167 (define_insn "*negdf2_ibm"
6168 [(set (match_operand:DF 0 "register_operand" "=f")
6169 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6170 (clobber (reg:CC 33))]
6171 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6173 [(set_attr "op_type" "RR")
6174 (set_attr "type" "fsimpd")])
6177 ; negsf2 instruction pattern(s).
6180 (define_expand "negsf2"
6182 [(set (match_operand:SF 0 "register_operand" "=f")
6183 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6184 (clobber (reg:CC 33))])]
6188 (define_insn "*negsf2"
6189 [(set (match_operand:SF 0 "register_operand" "=f")
6190 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6191 (clobber (reg:CC 33))]
6192 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6194 [(set_attr "op_type" "RRE")
6195 (set_attr "type" "fsimps")])
6197 (define_insn "*negsf2"
6198 [(set (match_operand:SF 0 "register_operand" "=f")
6199 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6200 (clobber (reg:CC 33))]
6201 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6203 [(set_attr "op_type" "RR")
6204 (set_attr "type" "fsimps")])
6208 ;;- Absolute value instructions.
6212 ; absdi2 instruction pattern(s).
6215 (define_insn "absdi2"
6216 [(set (match_operand:DI 0 "register_operand" "=d")
6217 (abs:DI (match_operand:DI 1 "register_operand" "d")))
6218 (clobber (reg:CC 33))]
6221 [(set_attr "op_type" "RRE")])
6224 ; abssi2 instruction pattern(s).
6227 (define_insn "abssi2"
6228 [(set (match_operand:SI 0 "register_operand" "=d")
6229 (abs:SI (match_operand:SI 1 "register_operand" "d")))
6230 (clobber (reg:CC 33))]
6233 [(set_attr "op_type" "RR")])
6236 ; absdf2 instruction pattern(s).
6239 (define_expand "absdf2"
6241 [(set (match_operand:DF 0 "register_operand" "=f")
6242 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6243 (clobber (reg:CC 33))])]
6247 (define_insn "*absdf2"
6248 [(set (match_operand:DF 0 "register_operand" "=f")
6249 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6250 (clobber (reg:CC 33))]
6251 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6253 [(set_attr "op_type" "RRE")
6254 (set_attr "type" "fsimpd")])
6256 (define_insn "*absdf2_ibm"
6257 [(set (match_operand:DF 0 "register_operand" "=f")
6258 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6259 (clobber (reg:CC 33))]
6260 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6262 [(set_attr "op_type" "RR")
6263 (set_attr "type" "fsimpd")])
6266 ; abssf2 instruction pattern(s).
6269 (define_expand "abssf2"
6271 [(set (match_operand:SF 0 "register_operand" "=f")
6272 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6273 (clobber (reg:CC 33))])]
6277 (define_insn "*abssf2"
6278 [(set (match_operand:SF 0 "register_operand" "=f")
6279 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6280 (clobber (reg:CC 33))]
6281 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6283 [(set_attr "op_type" "RRE")
6284 (set_attr "type" "fsimps")])
6286 (define_insn "*abssf2_ibm"
6287 [(set (match_operand:SF 0 "register_operand" "=f")
6288 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6289 (clobber (reg:CC 33))]
6290 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6292 [(set_attr "op_type" "RR")
6293 (set_attr "type" "fsimps")])
6296 ;;- Negated absolute value instructions
6303 (define_insn "*negabssi2"
6304 [(set (match_operand:SI 0 "register_operand" "=d")
6305 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
6306 (clobber (reg:CC 33))]
6309 [(set_attr "op_type" "RR")])
6311 (define_insn "*negabsdi2"
6312 [(set (match_operand:DI 0 "register_operand" "=d")
6313 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
6314 (clobber (reg:CC 33))]
6317 [(set_attr "op_type" "RRE")])
6323 (define_insn "*negabssf2"
6324 [(set (match_operand:SF 0 "register_operand" "=f")
6325 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6326 (clobber (reg:CC 33))]
6327 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6329 [(set_attr "op_type" "RRE")
6330 (set_attr "type" "fsimps")])
6332 (define_insn "*negabsdf2"
6333 [(set (match_operand:DF 0 "register_operand" "=f")
6334 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6335 (clobber (reg:CC 33))]
6336 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6338 [(set_attr "op_type" "RRE")
6339 (set_attr "type" "fsimpd")])
6342 ;;- Square root instructions.
6346 ; sqrtdf2 instruction pattern(s).
6349 (define_insn "sqrtdf2"
6350 [(set (match_operand:DF 0 "register_operand" "=f,f")
6351 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
6352 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6356 [(set_attr "op_type" "RRE,RXE")
6357 (set_attr "type" "fsqrtd")])
6360 ; sqrtsf2 instruction pattern(s).
6363 (define_insn "sqrtsf2"
6364 [(set (match_operand:SF 0 "register_operand" "=f,f")
6365 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
6366 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6370 [(set_attr "op_type" "RRE,RXE")
6371 (set_attr "type" "fsqrts")])
6374 ;;- One complement instructions.
6378 ; one_cmpldi2 instruction pattern(s).
6381 (define_expand "one_cmpldi2"
6383 [(set (match_operand:DI 0 "register_operand" "")
6384 (xor:DI (match_operand:DI 1 "register_operand" "")
6386 (clobber (reg:CC 33))])]
6391 ; one_cmplsi2 instruction pattern(s).
6394 (define_expand "one_cmplsi2"
6396 [(set (match_operand:SI 0 "register_operand" "")
6397 (xor:SI (match_operand:SI 1 "register_operand" "")
6399 (clobber (reg:CC 33))])]
6404 ; one_cmplhi2 instruction pattern(s).
6407 (define_expand "one_cmplhi2"
6409 [(set (match_operand:HI 0 "register_operand" "")
6410 (xor:HI (match_operand:HI 1 "register_operand" "")
6412 (clobber (reg:CC 33))])]
6417 ; one_cmplqi2 instruction pattern(s).
6420 (define_expand "one_cmplqi2"
6422 [(set (match_operand:QI 0 "register_operand" "")
6423 (xor:QI (match_operand:QI 1 "register_operand" "")
6425 (clobber (reg:CC 33))])]
6431 ;;- Rotate instructions.
6435 ; rotldi3 instruction pattern(s).
6438 (define_insn "rotldi3"
6439 [(set (match_operand:DI 0 "register_operand" "=d")
6440 (rotate:DI (match_operand:DI 1 "register_operand" "d")
6441 (match_operand:SI 2 "shift_count_operand" "Y")))]
6444 [(set_attr "op_type" "RSE")
6445 (set_attr "atype" "reg")])
6448 ; rotlsi3 instruction pattern(s).
6451 (define_insn "rotlsi3"
6452 [(set (match_operand:SI 0 "register_operand" "=d")
6453 (rotate:SI (match_operand:SI 1 "register_operand" "d")
6454 (match_operand:SI 2 "shift_count_operand" "Y")))]
6457 [(set_attr "op_type" "RSE")
6458 (set_attr "atype" "reg")])
6462 ;;- Arithmetic shift instructions.
6466 ; ashldi3 instruction pattern(s).
6469 (define_expand "ashldi3"
6470 [(set (match_operand:DI 0 "register_operand" "")
6471 (ashift:DI (match_operand:DI 1 "register_operand" "")
6472 (match_operand:SI 2 "shift_count_operand" "")))]
6476 (define_insn "*ashldi3_31"
6477 [(set (match_operand:DI 0 "register_operand" "=d")
6478 (ashift:DI (match_operand:DI 1 "register_operand" "0")
6479 (match_operand:SI 2 "shift_count_operand" "Y")))]
6482 [(set_attr "op_type" "RS")
6483 (set_attr "atype" "reg")])
6485 (define_insn "*ashldi3_64"
6486 [(set (match_operand:DI 0 "register_operand" "=d")
6487 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6488 (match_operand:SI 2 "shift_count_operand" "Y")))]
6491 [(set_attr "op_type" "RSE")
6492 (set_attr "atype" "reg")])
6495 ; ashrdi3 instruction pattern(s).
6498 (define_expand "ashrdi3"
6500 [(set (match_operand:DI 0 "register_operand" "")
6501 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6502 (match_operand:SI 2 "shift_count_operand" "")))
6503 (clobber (reg:CC 33))])]
6507 (define_insn "*ashrdi3_cc_31"
6509 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6510 (match_operand:SI 2 "shift_count_operand" "Y"))
6512 (set (match_operand:DI 0 "register_operand" "=d")
6513 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6514 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6516 [(set_attr "op_type" "RS")
6517 (set_attr "atype" "reg")])
6519 (define_insn "*ashrdi3_cconly_31"
6521 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6522 (match_operand:SI 2 "shift_count_operand" "Y"))
6524 (clobber (match_scratch:DI 0 "=d"))]
6525 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6527 [(set_attr "op_type" "RS")
6528 (set_attr "atype" "reg")])
6530 (define_insn "*ashrdi3_31"
6531 [(set (match_operand:DI 0 "register_operand" "=d")
6532 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6533 (match_operand:SI 2 "shift_count_operand" "Y")))
6534 (clobber (reg:CC 33))]
6537 [(set_attr "op_type" "RS")
6538 (set_attr "atype" "reg")])
6540 (define_insn "*ashrdi3_cc_64"
6542 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6543 (match_operand:SI 2 "shift_count_operand" "Y"))
6545 (set (match_operand:DI 0 "register_operand" "=d")
6546 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6547 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6549 [(set_attr "op_type" "RSE")
6550 (set_attr "atype" "reg")])
6552 (define_insn "*ashrdi3_cconly_64"
6554 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6555 (match_operand:SI 2 "shift_count_operand" "Y"))
6557 (clobber (match_scratch:DI 0 "=d"))]
6558 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6560 [(set_attr "op_type" "RSE")
6561 (set_attr "atype" "reg")])
6563 (define_insn "*ashrdi3_64"
6564 [(set (match_operand:DI 0 "register_operand" "=d")
6565 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6566 (match_operand:SI 2 "shift_count_operand" "Y")))
6567 (clobber (reg:CC 33))]
6570 [(set_attr "op_type" "RSE")
6571 (set_attr "atype" "reg")])
6575 ; ashlsi3 instruction pattern(s).
6578 (define_insn "ashlsi3"
6579 [(set (match_operand:SI 0 "register_operand" "=d")
6580 (ashift:SI (match_operand:SI 1 "register_operand" "0")
6581 (match_operand:SI 2 "shift_count_operand" "Y")))]
6584 [(set_attr "op_type" "RS")
6585 (set_attr "atype" "reg")])
6588 ; ashrsi3 instruction pattern(s).
6591 (define_insn "*ashrsi3_cc"
6593 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6594 (match_operand:SI 2 "shift_count_operand" "Y"))
6596 (set (match_operand:SI 0 "register_operand" "=d")
6597 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6598 "s390_match_ccmode(insn, CCSmode)"
6600 [(set_attr "op_type" "RS")
6601 (set_attr "atype" "reg")])
6604 (define_insn "*ashrsi3_cconly"
6606 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6607 (match_operand:SI 2 "shift_count_operand" "Y"))
6609 (clobber (match_scratch:SI 0 "=d"))]
6610 "s390_match_ccmode(insn, CCSmode)"
6612 [(set_attr "op_type" "RS")
6613 (set_attr "atype" "reg")])
6615 (define_insn "ashrsi3"
6616 [(set (match_operand:SI 0 "register_operand" "=d")
6617 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6618 (match_operand:SI 2 "shift_count_operand" "Y")))
6619 (clobber (reg:CC 33))]
6622 [(set_attr "op_type" "RS")
6623 (set_attr "atype" "reg")])
6627 ;;- logical shift instructions.
6631 ; lshrdi3 instruction pattern(s).
6634 (define_expand "lshrdi3"
6635 [(set (match_operand:DI 0 "register_operand" "")
6636 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6637 (match_operand:SI 2 "shift_count_operand" "")))]
6641 (define_insn "*lshrdi3_31"
6642 [(set (match_operand:DI 0 "register_operand" "=d")
6643 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
6644 (match_operand:SI 2 "shift_count_operand" "Y")))]
6647 [(set_attr "op_type" "RS")
6648 (set_attr "atype" "reg")])
6650 (define_insn "*lshrdi3_64"
6651 [(set (match_operand:DI 0 "register_operand" "=d")
6652 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6653 (match_operand:SI 2 "shift_count_operand" "Y")))]
6656 [(set_attr "op_type" "RSE")
6657 (set_attr "atype" "reg")])
6660 ; lshrsi3 instruction pattern(s).
6663 (define_insn "lshrsi3"
6664 [(set (match_operand:SI 0 "register_operand" "=d")
6665 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
6666 (match_operand:SI 2 "shift_count_operand" "Y")))]
6669 [(set_attr "op_type" "RS")
6670 (set_attr "atype" "reg")])
6674 ;; Branch instruction patterns.
6677 (define_expand "beq"
6678 [(match_operand 0 "" "")]
6680 "s390_emit_jump (operands[0],
6681 s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
6683 (define_expand "bne"
6684 [(match_operand 0 "" "")]
6686 "s390_emit_jump (operands[0],
6687 s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
6689 (define_expand "bgt"
6690 [(match_operand 0 "" "")]
6692 "s390_emit_jump (operands[0],
6693 s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
6695 (define_expand "bgtu"
6696 [(match_operand 0 "" "")]
6698 "s390_emit_jump (operands[0],
6699 s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
6701 (define_expand "blt"
6702 [(match_operand 0 "" "")]
6704 "s390_emit_jump (operands[0],
6705 s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
6707 (define_expand "bltu"
6708 [(match_operand 0 "" "")]
6710 "s390_emit_jump (operands[0],
6711 s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
6713 (define_expand "bge"
6714 [(match_operand 0 "" "")]
6716 "s390_emit_jump (operands[0],
6717 s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
6719 (define_expand "bgeu"
6720 [(match_operand 0 "" "")]
6722 "s390_emit_jump (operands[0],
6723 s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
6725 (define_expand "ble"
6726 [(match_operand 0 "" "")]
6728 "s390_emit_jump (operands[0],
6729 s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
6731 (define_expand "bleu"
6732 [(match_operand 0 "" "")]
6734 "s390_emit_jump (operands[0],
6735 s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
6737 (define_expand "bunordered"
6738 [(match_operand 0 "" "")]
6740 "s390_emit_jump (operands[0],
6741 s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
6743 (define_expand "bordered"
6744 [(match_operand 0 "" "")]
6746 "s390_emit_jump (operands[0],
6747 s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
6749 (define_expand "buneq"
6750 [(match_operand 0 "" "")]
6752 "s390_emit_jump (operands[0],
6753 s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
6755 (define_expand "bunlt"
6756 [(match_operand 0 "" "")]
6758 "s390_emit_jump (operands[0],
6759 s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
6761 (define_expand "bungt"
6762 [(match_operand 0 "" "")]
6764 "s390_emit_jump (operands[0],
6765 s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
6767 (define_expand "bunle"
6768 [(match_operand 0 "" "")]
6770 "s390_emit_jump (operands[0],
6771 s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
6773 (define_expand "bunge"
6774 [(match_operand 0 "" "")]
6776 "s390_emit_jump (operands[0],
6777 s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
6779 (define_expand "bltgt"
6780 [(match_operand 0 "" "")]
6782 "s390_emit_jump (operands[0],
6783 s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
6787 ;;- Conditional jump instructions.
6790 (define_insn "*cjump_64"
6793 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6794 (label_ref (match_operand 0 "" ""))
6798 if (get_attr_length (insn) == 4)
6801 return "jg%C1\t%l0";
6803 [(set_attr "op_type" "RI")
6804 (set_attr "type" "branch")
6805 (set (attr "length")
6806 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6807 (const_int 4) (const_int 6)))])
6809 (define_insn "*cjump_31"
6812 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6813 (label_ref (match_operand 0 "" ""))
6817 if (get_attr_length (insn) == 4)
6822 [(set_attr "op_type" "RI")
6823 (set_attr "type" "branch")
6824 (set (attr "length")
6825 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6826 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6827 (const_int 4) (const_int 6))
6828 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6829 (const_int 4) (const_int 8))))])
6831 (define_insn "*cjump_long"
6834 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6835 (match_operand 0 "address_operand" "U")
6839 if (get_attr_op_type (insn) == OP_TYPE_RR)
6844 [(set (attr "op_type")
6845 (if_then_else (match_operand 0 "register_operand" "")
6846 (const_string "RR") (const_string "RX")))
6847 (set_attr "type" "branch")
6848 (set_attr "atype" "agen")])
6852 ;;- Negated conditional jump instructions.
6855 (define_insn "*icjump_64"
6858 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6860 (label_ref (match_operand 0 "" ""))))]
6863 if (get_attr_length (insn) == 4)
6866 return "jg%D1\t%l0";
6868 [(set_attr "op_type" "RI")
6869 (set_attr "type" "branch")
6870 (set (attr "length")
6871 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6872 (const_int 4) (const_int 6)))])
6874 (define_insn "*icjump_31"
6877 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6879 (label_ref (match_operand 0 "" ""))))]
6882 if (get_attr_length (insn) == 4)
6887 [(set_attr "op_type" "RI")
6888 (set_attr "type" "branch")
6889 (set (attr "length")
6890 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6891 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6892 (const_int 4) (const_int 6))
6893 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6894 (const_int 4) (const_int 8))))])
6896 (define_insn "*icjump_long"
6899 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
6901 (match_operand 0 "address_operand" "U")))]
6904 if (get_attr_op_type (insn) == OP_TYPE_RR)
6909 [(set (attr "op_type")
6910 (if_then_else (match_operand 0 "register_operand" "")
6911 (const_string "RR") (const_string "RX")))
6912 (set_attr "type" "branch")
6913 (set_attr "atype" "agen")])
6916 ;;- Trap instructions.
6920 [(trap_if (const_int 1) (const_int 0))]
6923 [(set_attr "op_type" "RI")
6924 (set_attr "type" "branch")])
6926 (define_expand "conditional_trap"
6927 [(trap_if (match_operand 0 "comparison_operator" "")
6928 (match_operand 1 "general_operand" ""))]
6931 if (operands[1] != const0_rtx) FAIL;
6932 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6933 s390_compare_op0, s390_compare_op1);
6936 (define_insn "*trap"
6937 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
6941 [(set_attr "op_type" "RI")
6942 (set_attr "type" "branch")])
6945 ;;- Loop instructions.
6947 ;; This is all complicated by the fact that since this is a jump insn
6948 ;; we must handle our own output reloads.
6950 (define_expand "doloop_end"
6951 [(use (match_operand 0 "" "")) ; loop pseudo
6952 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6953 (use (match_operand 2 "" "")) ; max iterations
6954 (use (match_operand 3 "" "")) ; loop level
6955 (use (match_operand 4 "" ""))] ; label
6958 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6959 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6960 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6961 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6962 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6963 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6970 (define_insn_and_split "doloop_si64"
6973 (ne (match_operand:SI 1 "register_operand" "d,d")
6975 (label_ref (match_operand 0 "" ""))
6977 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6978 (plus:SI (match_dup 1) (const_int -1)))
6979 (clobber (match_scratch:SI 3 "=X,&d"))
6980 (clobber (reg:CC 33))]
6983 if (which_alternative != 0)
6985 else if (get_attr_length (insn) == 4)
6986 return "brct\t%1,%l0";
6988 return "ahi\t%1,-1\;jgne\t%l0";
6990 "&& reload_completed
6991 && (! REG_P (operands[2])
6992 || ! rtx_equal_p (operands[1], operands[2]))"
6993 [(set (match_dup 3) (match_dup 1))
6994 (parallel [(set (reg:CCAN 33)
6995 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6997 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6998 (set (match_dup 2) (match_dup 3))
6999 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7000 (label_ref (match_dup 0))
7003 [(set_attr "op_type" "RI")
7004 (set_attr "type" "branch")
7005 (set (attr "length")
7006 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7007 (const_int 4) (const_int 10)))])
7009 (define_insn_and_split "doloop_si31"
7012 (ne (match_operand:SI 1 "register_operand" "d,d")
7014 (label_ref (match_operand 0 "" ""))
7016 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7017 (plus:SI (match_dup 1) (const_int -1)))
7018 (clobber (match_scratch:SI 3 "=X,&d"))
7019 (clobber (reg:CC 33))]
7022 if (which_alternative != 0)
7024 else if (get_attr_length (insn) == 4)
7025 return "brct\t%1,%l0";
7029 "&& reload_completed
7030 && (! REG_P (operands[2])
7031 || ! rtx_equal_p (operands[1], operands[2]))"
7032 [(set (match_dup 3) (match_dup 1))
7033 (parallel [(set (reg:CCAN 33)
7034 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7036 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7037 (set (match_dup 2) (match_dup 3))
7038 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7039 (label_ref (match_dup 0))
7042 [(set_attr "op_type" "RI")
7043 (set_attr "type" "branch")
7044 (set (attr "length")
7045 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7046 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7047 (const_int 4) (const_int 6))
7048 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7049 (const_int 4) (const_int 8))))])
7051 (define_insn "*doloop_si_long"
7054 (ne (match_operand:SI 1 "register_operand" "d,d")
7056 (match_operand 0 "address_operand" "U,U")
7058 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7059 (plus:SI (match_dup 1) (const_int -1)))
7060 (clobber (match_scratch:SI 3 "=X,&d"))
7061 (clobber (reg:CC 33))]
7064 if (get_attr_op_type (insn) == OP_TYPE_RR)
7065 return "bctr\t%1,%0";
7067 return "bct\t%1,%a0";
7069 [(set (attr "op_type")
7070 (if_then_else (match_operand 0 "register_operand" "")
7071 (const_string "RR") (const_string "RX")))
7072 (set_attr "type" "branch")
7073 (set_attr "atype" "agen")])
7075 (define_insn_and_split "doloop_di"
7078 (ne (match_operand:DI 1 "register_operand" "d,d")
7080 (label_ref (match_operand 0 "" ""))
7082 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r")
7083 (plus:DI (match_dup 1) (const_int -1)))
7084 (clobber (match_scratch:DI 3 "=X,&d"))
7085 (clobber (reg:CC 33))]
7088 if (which_alternative != 0)
7090 else if (get_attr_length (insn) == 4)
7091 return "brctg\t%1,%l0";
7093 return "aghi\t%1,-1\;jgne\t%l0";
7095 "&& reload_completed
7096 && (! REG_P (operands[2])
7097 || ! rtx_equal_p (operands[1], operands[2]))"
7098 [(set (match_dup 3) (match_dup 1))
7099 (parallel [(set (reg:CCAN 33)
7100 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7102 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7103 (set (match_dup 2) (match_dup 3))
7104 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7105 (label_ref (match_dup 0))
7108 [(set_attr "op_type" "RI")
7109 (set_attr "type" "branch")
7110 (set (attr "length")
7111 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7112 (const_int 4) (const_int 10)))])
7115 ;;- Unconditional jump instructions.
7119 ; jump instruction pattern(s).
7122 (define_expand "jump"
7123 [(match_operand 0 "" "")]
7125 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7127 (define_insn "*jump64"
7128 [(set (pc) (label_ref (match_operand 0 "" "")))]
7131 if (get_attr_length (insn) == 4)
7136 [(set_attr "op_type" "RI")
7137 (set_attr "type" "branch")
7138 (set (attr "length")
7139 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7140 (const_int 4) (const_int 6)))])
7142 (define_insn "*jump31"
7143 [(set (pc) (label_ref (match_operand 0 "" "")))]
7146 if (get_attr_length (insn) == 4)
7151 [(set_attr "op_type" "RI")
7152 (set_attr "type" "branch")
7153 (set (attr "length")
7154 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7155 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7156 (const_int 4) (const_int 6))
7157 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7158 (const_int 4) (const_int 8))))])
7161 ; indirect-jump instruction pattern(s).
7164 (define_insn "indirect_jump"
7165 [(set (pc) (match_operand 0 "address_operand" "U"))]
7168 if (get_attr_op_type (insn) == OP_TYPE_RR)
7173 [(set (attr "op_type")
7174 (if_then_else (match_operand 0 "register_operand" "")
7175 (const_string "RR") (const_string "RX")))
7176 (set_attr "type" "branch")
7177 (set_attr "atype" "agen")])
7180 ; casesi instruction pattern(s).
7183 (define_insn "casesi_jump"
7184 [(set (pc) (match_operand 0 "address_operand" "U"))
7185 (use (label_ref (match_operand 1 "" "")))]
7188 if (get_attr_op_type (insn) == OP_TYPE_RR)
7193 [(set (attr "op_type")
7194 (if_then_else (match_operand 0 "register_operand" "")
7195 (const_string "RR") (const_string "RX")))
7196 (set_attr "type" "branch")
7197 (set_attr "atype" "agen")])
7199 (define_expand "casesi"
7200 [(match_operand:SI 0 "general_operand" "")
7201 (match_operand:SI 1 "general_operand" "")
7202 (match_operand:SI 2 "general_operand" "")
7203 (label_ref (match_operand 3 "" ""))
7204 (label_ref (match_operand 4 "" ""))]
7207 rtx index = gen_reg_rtx (SImode);
7208 rtx base = gen_reg_rtx (Pmode);
7209 rtx target = gen_reg_rtx (Pmode);
7211 emit_move_insn (index, operands[0]);
7212 emit_insn (gen_subsi3 (index, index, operands[1]));
7213 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7216 if (Pmode != SImode)
7217 index = convert_to_mode (Pmode, index, 1);
7218 if (GET_CODE (index) != REG)
7219 index = copy_to_mode_reg (Pmode, index);
7222 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7224 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7226 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7228 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7229 emit_move_insn (target, index);
7232 target = gen_rtx_PLUS (Pmode, base, target);
7233 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7240 ;;- Jump to subroutine.
7245 ; untyped call instruction pattern(s).
7248 ;; Call subroutine returning any type.
7249 (define_expand "untyped_call"
7250 [(parallel [(call (match_operand 0 "" "")
7252 (match_operand 1 "" "")
7253 (match_operand 2 "" "")])]
7258 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7260 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7262 rtx set = XVECEXP (operands[2], 0, i);
7263 emit_move_insn (SET_DEST (set), SET_SRC (set));
7266 /* The optimizer does not know that the call sets the function value
7267 registers we stored in the result block. We avoid problems by
7268 claiming that all hard registers are used and clobbered at this
7270 emit_insn (gen_blockage ());
7275 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7276 ;; all of memory. This blocks insns from being moved across this point.
7278 (define_insn "blockage"
7279 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7282 [(set_attr "type" "none")
7283 (set_attr "length" "0")])
7289 (define_expand "sibcall"
7290 [(call (match_operand 0 "" "")
7291 (match_operand 1 "" ""))]
7294 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7298 (define_insn "*sibcall_br"
7299 [(call (mem:QI (reg 1))
7300 (match_operand 0 "const_int_operand" "n"))]
7301 "SIBLING_CALL_P (insn)
7302 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7304 [(set_attr "op_type" "RR")
7305 (set_attr "type" "branch")
7306 (set_attr "atype" "agen")])
7308 (define_insn "*sibcall_brc"
7309 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7310 (match_operand 1 "const_int_operand" "n"))]
7311 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7313 [(set_attr "op_type" "RI")
7314 (set_attr "type" "branch")])
7316 (define_insn "*sibcall_brcl"
7317 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7318 (match_operand 1 "const_int_operand" "n"))]
7319 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7321 [(set_attr "op_type" "RIL")
7322 (set_attr "type" "branch")])
7325 ; sibcall_value patterns
7328 (define_expand "sibcall_value"
7329 [(set (match_operand 0 "" "")
7330 (call (match_operand 1 "" "")
7331 (match_operand 2 "" "")))]
7334 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7338 (define_insn "*sibcall_value_br"
7339 [(set (match_operand 0 "" "")
7340 (call (mem:QI (reg 1))
7341 (match_operand 1 "const_int_operand" "n")))]
7342 "SIBLING_CALL_P (insn)
7343 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7345 [(set_attr "op_type" "RR")
7346 (set_attr "type" "branch")
7347 (set_attr "atype" "agen")])
7349 (define_insn "*sibcall_value_brc"
7350 [(set (match_operand 0 "" "")
7351 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7352 (match_operand 2 "const_int_operand" "n")))]
7353 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7355 [(set_attr "op_type" "RI")
7356 (set_attr "type" "branch")])
7358 (define_insn "*sibcall_value_brcl"
7359 [(set (match_operand 0 "" "")
7360 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7361 (match_operand 2 "const_int_operand" "n")))]
7362 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7364 [(set_attr "op_type" "RIL")
7365 (set_attr "type" "branch")])
7369 ; call instruction pattern(s).
7372 (define_expand "call"
7373 [(call (match_operand 0 "" "")
7374 (match_operand 1 "" ""))
7375 (use (match_operand 2 "" ""))]
7378 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7379 gen_rtx_REG (Pmode, RETURN_REGNUM));
7383 (define_insn "*bras"
7384 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7385 (match_operand 1 "const_int_operand" "n"))
7386 (clobber (match_operand 2 "register_operand" "=r"))]
7387 "!SIBLING_CALL_P (insn)
7388 && TARGET_SMALL_EXEC
7389 && GET_MODE (operands[2]) == Pmode"
7391 [(set_attr "op_type" "RI")
7392 (set_attr "type" "jsr")])
7394 (define_insn "*brasl"
7395 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7396 (match_operand 1 "const_int_operand" "n"))
7397 (clobber (match_operand 2 "register_operand" "=r"))]
7398 "!SIBLING_CALL_P (insn)
7400 && GET_MODE (operands[2]) == Pmode"
7402 [(set_attr "op_type" "RIL")
7403 (set_attr "type" "jsr")])
7405 (define_insn "*basr"
7406 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7407 (match_operand 1 "const_int_operand" "n"))
7408 (clobber (match_operand 2 "register_operand" "=r"))]
7409 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7411 if (get_attr_op_type (insn) == OP_TYPE_RR)
7412 return "basr\t%2,%0";
7414 return "bas\t%2,%a0";
7416 [(set (attr "op_type")
7417 (if_then_else (match_operand 0 "register_operand" "")
7418 (const_string "RR") (const_string "RX")))
7419 (set_attr "type" "jsr")
7420 (set_attr "atype" "agen")])
7423 ; call_value instruction pattern(s).
7426 (define_expand "call_value"
7427 [(set (match_operand 0 "" "")
7428 (call (match_operand 1 "" "")
7429 (match_operand 2 "" "")))
7430 (use (match_operand 3 "" ""))]
7433 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7434 gen_rtx_REG (Pmode, RETURN_REGNUM));
7438 (define_insn "*bras_r"
7439 [(set (match_operand 0 "" "")
7440 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7441 (match_operand:SI 2 "const_int_operand" "n")))
7442 (clobber (match_operand 3 "register_operand" "=r"))]
7443 "!SIBLING_CALL_P (insn)
7444 && TARGET_SMALL_EXEC
7445 && GET_MODE (operands[3]) == Pmode"
7447 [(set_attr "op_type" "RI")
7448 (set_attr "type" "jsr")])
7450 (define_insn "*brasl_r"
7451 [(set (match_operand 0 "" "")
7452 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7453 (match_operand 2 "const_int_operand" "n")))
7454 (clobber (match_operand 3 "register_operand" "=r"))]
7455 "!SIBLING_CALL_P (insn)
7457 && GET_MODE (operands[3]) == Pmode"
7459 [(set_attr "op_type" "RIL")
7460 (set_attr "type" "jsr")])
7462 (define_insn "*basr_r"
7463 [(set (match_operand 0 "" "")
7464 (call (mem:QI (match_operand 1 "address_operand" "U"))
7465 (match_operand 2 "const_int_operand" "n")))
7466 (clobber (match_operand 3 "register_operand" "=r"))]
7467 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7469 if (get_attr_op_type (insn) == OP_TYPE_RR)
7470 return "basr\t%3,%1";
7472 return "bas\t%3,%a1";
7474 [(set (attr "op_type")
7475 (if_then_else (match_operand 1 "register_operand" "")
7476 (const_string "RR") (const_string "RX")))
7477 (set_attr "type" "jsr")
7478 (set_attr "atype" "agen")])
7481 ;;- Thread-local storage support.
7484 (define_expand "get_tp_64"
7485 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
7489 (define_expand "get_tp_31"
7490 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
7494 (define_expand "set_tp_64"
7495 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
7496 (unspec_volatile [(reg:DI 36)] UNSPECV_SET_TP)]
7500 (define_expand "set_tp_31"
7501 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
7502 (unspec_volatile [(reg:SI 36)] UNSPECV_SET_TP)]
7506 (define_insn "*set_tp"
7507 [(unspec_volatile [(reg 36)] UNSPECV_SET_TP)]
7510 [(set_attr "type" "none")
7511 (set_attr "length" "0")])
7513 (define_insn "*tls_load_64"
7514 [(set (match_operand:DI 0 "register_operand" "=d")
7515 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7516 (match_operand:DI 2 "" "")]
7520 [(set_attr "op_type" "RXE")])
7522 (define_insn "*tls_load_31"
7523 [(set (match_operand:SI 0 "register_operand" "=d,d")
7524 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7525 (match_operand:SI 2 "" "")]
7531 [(set_attr "op_type" "RX,RXY")])
7533 (define_insn "*bras_tls"
7534 [(set (match_operand 0 "" "")
7535 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7536 (match_operand 2 "const_int_operand" "n")))
7537 (clobber (match_operand 3 "register_operand" "=r"))
7538 (use (match_operand 4 "" ""))]
7539 "!SIBLING_CALL_P (insn)
7540 && TARGET_SMALL_EXEC
7541 && GET_MODE (operands[3]) == Pmode"
7543 [(set_attr "op_type" "RI")
7544 (set_attr "type" "jsr")])
7546 (define_insn "*brasl_tls"
7547 [(set (match_operand 0 "" "")
7548 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7549 (match_operand 2 "const_int_operand" "n")))
7550 (clobber (match_operand 3 "register_operand" "=r"))
7551 (use (match_operand 4 "" ""))]
7552 "!SIBLING_CALL_P (insn)
7554 && GET_MODE (operands[3]) == Pmode"
7556 [(set_attr "op_type" "RIL")
7557 (set_attr "type" "jsr")])
7559 (define_insn "*basr_tls"
7560 [(set (match_operand 0 "" "")
7561 (call (mem:QI (match_operand 1 "address_operand" "U"))
7562 (match_operand 2 "const_int_operand" "n")))
7563 (clobber (match_operand 3 "register_operand" "=r"))
7564 (use (match_operand 4 "" ""))]
7565 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7567 if (get_attr_op_type (insn) == OP_TYPE_RR)
7568 return "basr\t%3,%1%J4";
7570 return "bas\t%3,%a1%J4";
7572 [(set (attr "op_type")
7573 (if_then_else (match_operand 1 "register_operand" "")
7574 (const_string "RR") (const_string "RX")))
7575 (set_attr "type" "jsr")
7576 (set_attr "atype" "agen")])
7579 ;;- Miscellaneous instructions.
7583 ; allocate stack instruction pattern(s).
7586 (define_expand "allocate_stack"
7587 [(match_operand 0 "general_operand" "")
7588 (match_operand 1 "general_operand" "")]
7589 "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
7591 rtx temp = gen_reg_rtx (Pmode);
7593 emit_move_insn (temp, s390_back_chain_rtx ());
7594 anti_adjust_stack (operands[1]);
7595 emit_move_insn (s390_back_chain_rtx (), temp);
7597 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7603 ; setjmp instruction pattern.
7606 (define_expand "builtin_setjmp_receiver"
7607 [(match_operand 0 "" "")]
7610 emit_insn (s390_load_got ());
7611 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7615 ;; These patterns say how to save and restore the stack pointer. We need not
7616 ;; save the stack pointer at function level since we are careful to
7617 ;; preserve the backchain. At block level, we have to restore the backchain
7618 ;; when we restore the stack pointer.
7620 ;; For nonlocal gotos, we must save both the stack pointer and its
7621 ;; backchain and restore both. Note that in the nonlocal case, the
7622 ;; save area is a memory location.
7624 (define_expand "save_stack_function"
7625 [(match_operand 0 "general_operand" "")
7626 (match_operand 1 "general_operand" "")]
7630 (define_expand "restore_stack_function"
7631 [(match_operand 0 "general_operand" "")
7632 (match_operand 1 "general_operand" "")]
7636 (define_expand "restore_stack_block"
7637 [(match_operand 0 "register_operand" "")
7638 (match_operand 1 "register_operand" "")]
7639 "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN"
7641 rtx temp = gen_reg_rtx (Pmode);
7643 emit_move_insn (temp, s390_back_chain_rtx ());
7644 emit_move_insn (operands[0], operands[1]);
7645 emit_move_insn (s390_back_chain_rtx (), temp);
7650 (define_expand "save_stack_nonlocal"
7651 [(match_operand 0 "memory_operand" "")
7652 (match_operand 1 "register_operand" "")]
7655 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7656 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7658 /* Copy the backchain to the first word, sp to the second and the
7659 literal pool base to the third. */
7661 if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
7663 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7664 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7667 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7668 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7673 (define_expand "restore_stack_nonlocal"
7674 [(match_operand 0 "register_operand" "")
7675 (match_operand 1 "memory_operand" "")]
7678 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7679 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7680 rtx temp = NULL_RTX;
7682 /* Restore the backchain from the first word, sp from the second and the
7683 literal pool base from the third. */
7685 if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN)
7686 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7688 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7689 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7692 emit_move_insn (s390_back_chain_rtx (), temp);
7694 emit_insn (gen_rtx_USE (VOIDmode, base));
7700 ; nop instruction pattern(s).
7707 [(set_attr "op_type" "RR")])
7711 ; Special literal pool access instruction pattern(s).
7714 (define_insn "*pool_entry"
7715 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7716 UNSPECV_POOL_ENTRY)]
7719 enum machine_mode mode = GET_MODE (PATTERN (insn));
7720 unsigned int align = GET_MODE_BITSIZE (mode);
7721 s390_output_pool_entry (operands[0], mode, align);
7724 [(set_attr "op_type" "NN")
7725 (set (attr "length")
7726 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7728 (define_insn "pool_align"
7729 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7730 UNSPECV_POOL_ALIGN)]
7733 [(set_attr "op_type" "NN")
7734 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7736 (define_insn "pool_section_start"
7737 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7740 [(set_attr "op_type" "NN")
7741 (set_attr "length" "0")])
7743 (define_insn "pool_section_end"
7744 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7747 [(set_attr "op_type" "NN")
7748 (set_attr "length" "0")])
7750 (define_insn "main_base_31_small"
7751 [(set (match_operand 0 "register_operand" "=a")
7752 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7753 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7755 [(set_attr "op_type" "RR")
7756 (set_attr "type" "la")])
7758 (define_insn "main_base_31_large"
7759 [(set (match_operand 0 "register_operand" "=a")
7760 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7761 (set (pc) (label_ref (match_operand 2 "" "")))]
7762 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7764 [(set_attr "op_type" "RI")])
7766 (define_insn "main_base_64"
7767 [(set (match_operand 0 "register_operand" "=a")
7768 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7769 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7771 [(set_attr "op_type" "RIL")
7772 (set_attr "type" "larl")])
7774 (define_insn "main_pool"
7775 [(set (match_operand 0 "register_operand" "=a")
7776 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7777 "GET_MODE (operands[0]) == Pmode"
7779 [(set_attr "op_type" "NN")
7781 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7782 (const_string "larl") (const_string "la")))])
7784 (define_insn "reload_base_31"
7785 [(set (match_operand 0 "register_operand" "=a")
7786 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7787 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7788 "basr\t%0,0\;la\t%0,%1-.(%0)"
7789 [(set_attr "op_type" "NN")
7790 (set_attr "type" "la")
7791 (set_attr "length" "6")])
7793 (define_insn "reload_base_64"
7794 [(set (match_operand 0 "register_operand" "=a")
7795 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7796 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7798 [(set_attr "op_type" "RIL")
7799 (set_attr "type" "larl")])
7802 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7805 [(set_attr "op_type" "NN")
7806 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7809 ;; Insns related to generating the function prologue and epilogue.
7813 (define_expand "prologue"
7814 [(use (const_int 0))]
7816 "s390_emit_prologue (); DONE;")
7818 (define_insn "prologue_tpf"
7819 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
7820 (clobber (reg:DI 1))]
7821 "TARGET_TPF_PROFILING"
7823 [(set_attr "type" "jsr")
7824 (set_attr "op_type" "RX")])
7826 (define_expand "epilogue"
7827 [(use (const_int 1))]
7829 "s390_emit_epilogue (false); DONE;")
7831 (define_insn "epilogue_tpf"
7832 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
7833 (clobber (reg:DI 1))]
7834 "TARGET_TPF_PROFILING"
7836 [(set_attr "type" "jsr")
7837 (set_attr "op_type" "RX")])
7840 (define_expand "sibcall_epilogue"
7841 [(use (const_int 0))]
7843 "s390_emit_epilogue (true); DONE;")
7845 (define_insn "*return"
7847 (use (match_operand 0 "register_operand" "a"))]
7848 "GET_MODE (operands[0]) == Pmode"
7850 [(set_attr "op_type" "RR")
7851 (set_attr "type" "jsr")
7852 (set_attr "atype" "agen")])
7855 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7856 ;; pointer. This is used for compatibility.
7858 (define_expand "ptr_extend"
7859 [(set (match_operand:DI 0 "register_operand" "=r")
7860 (match_operand:SI 1 "register_operand" "r"))]
7863 emit_insn (gen_anddi3 (operands[0],
7864 gen_lowpart (DImode, operands[1]),
7865 GEN_INT (0x7fffffff)));
7869 ;; Instruction definition to expand eh_return macro to support
7870 ;; swapping in special linkage return addresses.
7872 (define_expand "eh_return"
7873 [(use (match_operand 0 "register_operand" ""))]
7876 s390_emit_tpf_eh_return (operands[0]);