1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Copy sign instructions
109 (UNSPEC_COPYSIGN 800)
111 ; Test Data Class (TDC)
112 (UNSPEC_TDC_INSN 900)
116 ;; UNSPEC_VOLATILE usage
124 (UNSPECV_TPF_PROLOGUE 20)
125 (UNSPECV_TPF_EPILOGUE 21)
129 (UNSPECV_POOL_SECTION 201)
130 (UNSPECV_POOL_ALIGN 202)
131 (UNSPECV_POOL_ENTRY 203)
132 (UNSPECV_MAIN_POOL 300)
145 ; Registers with special meaning
149 ; Sibling call register.
151 ; Literal pool base register.
153 ; Return address register.
155 ; Condition code register.
157 ; Thread local storage pointer register.
161 ; Hardware register names
165 ; General purpose registers
167 ; Floating point registers.
173 ;; PFPO GPR0 argument format
178 ; PFPO operation type
179 (PFPO_CONVERT 0x1000000)
181 (PFPO_OP_TYPE_SF 0x5)
182 (PFPO_OP_TYPE_DF 0x6)
183 (PFPO_OP_TYPE_TF 0x7)
184 (PFPO_OP_TYPE_SD 0x8)
185 (PFPO_OP_TYPE_DD 0x9)
186 (PFPO_OP_TYPE_TD 0xa)
187 ; Bitposition of operand types
188 (PFPO_OP0_TYPE_SHIFT 16)
189 (PFPO_OP1_TYPE_SHIFT 8)
193 ;; Instruction operand type as used in the Principles of Operation.
194 ;; Used to determine defaults for length and other attribute values.
196 (define_attr "op_type"
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
200 ;; Instruction type attribute used for scheduling.
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
203 cs,vs,store,sem,idiv,
204 imulhi,imulsi,imuldi,
205 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
206 floadtf,floaddf,floadsf,fstoredf,fstoresf,
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
210 itoftf, itofdf, itofsf, itofdd, itoftd,
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
214 (cond [(eq_attr "op_type" "NN") (const_string "other")
215 (eq_attr "op_type" "SS") (const_string "cs")]
216 (const_string "integer")))
218 ;; Another attribute used for scheduling purposes:
219 ;; agen: Instruction uses the address generation unit
220 ;; reg: Instruction does not use the agen unit
222 (define_attr "atype" "agen,reg"
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
225 (const_string "agen")))
227 ;; Properties concerning Z10 execution grouping and value forwarding.
228 ;; z10_super: instruction is superscalar.
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
231 ;; target register. It can forward this value to a second instruction that reads
232 ;; the same register if that second instruction is issued in the same group.
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
234 ;; instruction in the S pipe writes to the register, then the T instruction
235 ;; can immediately read the new value.
236 ;; z10_fr: union of Z10_fwd and z10_rec.
237 ;; z10_c: second operand of instruction is a register and read with complemented bits.
239 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
242 (define_attr "z10prop" "none,
243 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
244 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
246 z10_fr, z10_fr_A3, z10_fr_E1,
248 (const_string "none"))
253 (define_attr "length" ""
254 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
255 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
259 ;; Processor type. This attribute must exactly match the processor_type
260 ;; enumeration in s390.h. The current machine description does not
261 ;; distinguish between g5 and g6, but there are differences between the two
262 ;; CPUs could in theory be modeled.
264 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
265 (const (symbol_ref "s390_tune_attr")))
267 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
268 (const_string "standard"))
270 (define_attr "enabled" ""
271 (cond [(eq_attr "cpu_facility" "standard")
274 (and (eq_attr "cpu_facility" "ieee")
275 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
278 (and (eq_attr "cpu_facility" "zarch")
279 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
282 (and (eq_attr "cpu_facility" "longdisp")
283 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
286 (and (eq_attr "cpu_facility" "extimm")
287 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
290 (and (eq_attr "cpu_facility" "dfp")
291 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
294 (and (eq_attr "cpu_facility" "z10")
295 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
299 ;; Pipeline description for z900. For lack of anything better,
300 ;; this description is also used for the g5 and g6.
303 ;; Pipeline description for z990, z9-109 and z9-ec.
306 ;; Pipeline description for z10
310 (include "predicates.md")
312 ;; Constraint definitions
313 (include "constraints.md")
320 ;; These mode iterators allow floating point patterns to be generated from the
322 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
323 (SD "TARGET_HARD_DFP")])
324 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
325 (define_mode_iterator FPALL [TF DF SF TD DD SD])
326 (define_mode_iterator BFP [TF DF SF])
327 (define_mode_iterator DFP [TD DD])
328 (define_mode_iterator DFP_ALL [TD DD SD])
329 (define_mode_iterator DSF [DF SF])
330 (define_mode_iterator SD_SF [SF SD])
331 (define_mode_iterator DD_DF [DF DD])
332 (define_mode_iterator TD_TF [TF TD])
334 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
335 ;; from the same template.
336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
339 ;; from the same template.
340 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
341 (define_mode_iterator DSI [DI SI])
343 ;; These mode iterators allow :P to be used for patterns that operate on
344 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
345 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
347 ;; These macros refer to the actual word_mode of the configuration. This is equal
348 ;; to Pmode except on 31-bit machines in zarch mode.
349 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
350 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
352 ;; This mode iterator allows the QI and HI patterns to be defined from
353 ;; the same template.
354 (define_mode_iterator HQI [HI QI])
356 ;; This mode iterator allows the integer patterns to be defined from the
358 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
359 (define_mode_iterator INTALL [TI DI SI HI QI])
361 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
362 ;; the same template.
363 (define_code_iterator SHIFT [ashift lshiftrt])
365 ;; This iterator and attribute allow to combine most atomic operations.
366 (define_code_iterator ATOMIC [and ior xor plus minus mult])
367 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
368 (plus "add") (minus "sub") (mult "nand")])
370 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
371 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
372 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
374 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
375 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
377 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
379 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
380 ;; Likewise for "<RXe>".
381 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
382 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
384 ;; The decimal floating point variants of add, sub, div and mul support 3
385 ;; fp register operands. The following attributes allow to merge the bfp and
386 ;; dfp variants in a single insn definition.
388 ;; This attribute is used to set op_type accordingly.
389 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
390 (DD "RRR") (SD "RRR")])
392 ;; This attribute is used in the operand constraint list in order to have the
393 ;; first and the second operand match for bfp modes.
394 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
396 ;; This attribute is used in the operand list of the instruction to have an
397 ;; additional operand for the dfp instructions.
398 (define_mode_attr op1 [(TF "") (DF "") (SF "")
399 (TD "%1,") (DD "%1,") (SD "%1,")])
402 ;; This attribute is used in the operand constraint list
403 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
404 ;; TFmode values are represented by a fp register pair. Since the
405 ;; sign bit instructions only handle single source and target fp registers
406 ;; these instructions can only be used for TFmode values if the source and
407 ;; target operand uses the same fp register.
408 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
410 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
411 ;; This is used to disable the memory alternative in TFmode patterns.
412 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
414 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
415 ;; within instruction mnemonics.
416 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
418 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
419 ;; modes and to an empty string for bfp modes.
420 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
422 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
423 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
424 ;; version only operates on one register.
425 (define_mode_attr d0 [(DI "d") (SI "0")])
427 ;; In combination with d0 this allows to combine instructions of which the 31bit
428 ;; version only operates on one register. The DImode version needs an additional
429 ;; register for the assembler output.
430 (define_mode_attr 1 [(DI "%1,") (SI "")])
432 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
433 ;; 'ashift' and "srdl" in 'lshiftrt'.
434 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
436 ;; In SHIFT templates, this attribute holds the correct standard name for the
437 ;; pattern itself and the corresponding function calls.
438 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
440 ;; This attribute handles differences in the instruction 'type' and will result
441 ;; in "RRE" for DImode and "RR" for SImode.
442 (define_mode_attr E [(DI "E") (SI "")])
444 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
445 ;; to result in "RXY" for DImode and "RX" for SImode.
446 (define_mode_attr Y [(DI "Y") (SI "")])
448 ;; This attribute handles differences in the instruction 'type' and will result
449 ;; in "RSE" for TImode and "RS" for DImode.
450 (define_mode_attr TE [(TI "E") (DI "")])
452 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
453 ;; and "lcr" in SImode.
454 (define_mode_attr g [(DI "g") (SI "")])
456 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
457 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
458 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
459 ;; variant for long displacements.
460 (define_mode_attr y [(DI "g") (SI "y")])
462 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
463 ;; and "cds" in DImode.
464 (define_mode_attr tg [(TI "g") (DI "")])
466 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
467 ;; and "cfdbr" in SImode.
468 (define_mode_attr gf [(DI "g") (SI "f")])
470 ;; ICM mask required to load MODE value into the lowest subreg
471 ;; of a SImode register.
472 (define_mode_attr icm_lo [(HI "3") (QI "1")])
474 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
475 ;; HImode and "llgc" in QImode.
476 (define_mode_attr hc [(HI "h") (QI "c")])
478 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
480 (define_mode_attr DBL [(DI "TI") (SI "DI")])
482 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
483 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
484 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
486 ;; Maximum unsigned integer that fits in MODE.
487 (define_mode_attr max_uint [(HI "65535") (QI "255")])
490 ;;- Compare instructions.
493 ; Test-under-Mask instructions
495 (define_insn "*tmqi_mem"
496 [(set (reg CC_REGNUM)
497 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
498 (match_operand:QI 1 "immediate_operand" "n,n"))
499 (match_operand:QI 2 "immediate_operand" "n,n")))]
500 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
504 [(set_attr "op_type" "SI,SIY")
505 (set_attr "z10prop" "z10_super,z10_super")])
507 (define_insn "*tmdi_reg"
508 [(set (reg CC_REGNUM)
509 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
510 (match_operand:DI 1 "immediate_operand"
511 "N0HD0,N1HD0,N2HD0,N3HD0"))
512 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
514 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
515 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
521 [(set_attr "op_type" "RI")
522 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
524 (define_insn "*tmsi_reg"
525 [(set (reg CC_REGNUM)
526 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
527 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
528 (match_operand:SI 2 "immediate_operand" "n,n")))]
529 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
530 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
534 [(set_attr "op_type" "RI")
535 (set_attr "z10prop" "z10_super,z10_super")])
537 (define_insn "*tm<mode>_full"
538 [(set (reg CC_REGNUM)
539 (compare (match_operand:HQI 0 "register_operand" "d")
540 (match_operand:HQI 1 "immediate_operand" "n")))]
541 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
543 [(set_attr "op_type" "RI")
544 (set_attr "z10prop" "z10_super")])
548 ; Load-and-Test instructions
551 ; tst(di|si) instruction pattern(s).
553 (define_insn "*tstdi_sign"
554 [(set (reg CC_REGNUM)
558 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
559 (const_int 32)) (const_int 32))
560 (match_operand:DI 1 "const0_operand" "")))
561 (set (match_operand:DI 2 "register_operand" "=d,d")
562 (sign_extend:DI (match_dup 0)))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
566 [(set_attr "op_type" "RRE,RXY")
567 (set_attr "cpu_facility" "*,z10")
568 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
571 (define_insn "*tst<mode>_extimm"
572 [(set (reg CC_REGNUM)
573 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
574 (match_operand:GPR 1 "const0_operand" "")))
575 (set (match_operand:GPR 2 "register_operand" "=d,d")
577 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
581 [(set_attr "op_type" "RR<E>,RXY")
582 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
585 (define_insn "*tst<mode>_cconly_extimm"
586 [(set (reg CC_REGNUM)
587 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
588 (match_operand:GPR 1 "const0_operand" "")))
589 (clobber (match_scratch:GPR 2 "=X,d"))]
590 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
594 [(set_attr "op_type" "RR<E>,RXY")
595 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
597 (define_insn "*tstdi"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:DI 0 "register_operand" "d")
600 (match_operand:DI 1 "const0_operand" "")))
601 (set (match_operand:DI 2 "register_operand" "=d")
603 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
605 [(set_attr "op_type" "RRE")
606 (set_attr "z10prop" "z10_fr_E1")])
608 (define_insn "*tstsi"
609 [(set (reg CC_REGNUM)
610 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
611 (match_operand:SI 1 "const0_operand" "")))
612 (set (match_operand:SI 2 "register_operand" "=d,d,d")
614 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
619 [(set_attr "op_type" "RR,RS,RSY")
620 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
622 (define_insn "*tstsi_cconly"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
625 (match_operand:SI 1 "const0_operand" "")))
626 (clobber (match_scratch:SI 2 "=X,d,d"))]
627 "s390_match_ccmode(insn, CCSmode)"
632 [(set_attr "op_type" "RR,RS,RSY")
633 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
635 (define_insn "*tstdi_cconly_31"
636 [(set (reg CC_REGNUM)
637 (compare (match_operand:DI 0 "register_operand" "d")
638 (match_operand:DI 1 "const0_operand" "")))]
639 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
641 [(set_attr "op_type" "RS")
642 (set_attr "atype" "reg")])
645 (define_insn "*tst<mode>_cconly2"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:GPR 0 "register_operand" "d")
648 (match_operand:GPR 1 "const0_operand" "")))]
649 "s390_match_ccmode(insn, CCSmode)"
651 [(set_attr "op_type" "RR<E>")
652 (set_attr "z10prop" "z10_fr_E1")])
654 ; tst(hi|qi) instruction pattern(s).
656 (define_insn "*tst<mode>CCT"
657 [(set (reg CC_REGNUM)
658 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
659 (match_operand:HQI 1 "const0_operand" "")))
660 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
662 "s390_match_ccmode(insn, CCTmode)"
665 icmy\t%2,<icm_lo>,%S0
667 [(set_attr "op_type" "RS,RSY,RI")
668 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
670 (define_insn "*tsthiCCT_cconly"
671 [(set (reg CC_REGNUM)
672 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
673 (match_operand:HI 1 "const0_operand" "")))
674 (clobber (match_scratch:HI 2 "=d,d,X"))]
675 "s390_match_ccmode(insn, CCTmode)"
680 [(set_attr "op_type" "RS,RSY,RI")
681 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
683 (define_insn "*tstqiCCT_cconly"
684 [(set (reg CC_REGNUM)
685 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
686 (match_operand:QI 1 "const0_operand" "")))]
687 "s390_match_ccmode(insn, CCTmode)"
692 [(set_attr "op_type" "SI,SIY,RI")
693 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
695 (define_insn "*tst<mode>"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:HQI 0 "s_operand" "Q,S")
698 (match_operand:HQI 1 "const0_operand" "")))
699 (set (match_operand:HQI 2 "register_operand" "=d,d")
701 "s390_match_ccmode(insn, CCSmode)"
704 icmy\t%2,<icm_lo>,%S0"
705 [(set_attr "op_type" "RS,RSY")
706 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
708 (define_insn "*tst<mode>_cconly"
709 [(set (reg CC_REGNUM)
710 (compare (match_operand:HQI 0 "s_operand" "Q,S")
711 (match_operand:HQI 1 "const0_operand" "")))
712 (clobber (match_scratch:HQI 2 "=d,d"))]
713 "s390_match_ccmode(insn, CCSmode)"
716 icmy\t%2,<icm_lo>,%S0"
717 [(set_attr "op_type" "RS,RSY")
718 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
721 ; Compare (equality) instructions
723 (define_insn "*cmpdi_cct"
724 [(set (reg CC_REGNUM)
725 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
726 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
727 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
734 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
735 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
737 (define_insn "*cmpsi_cct"
738 [(set (reg CC_REGNUM)
739 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
740 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
741 "s390_match_ccmode (insn, CCTmode)"
749 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
750 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
752 ; Compare (signed) instructions
754 (define_insn "*cmpdi_ccs_sign"
755 [(set (reg CC_REGNUM)
756 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
758 (match_operand:DI 0 "register_operand" "d, d,d")))]
759 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
764 [(set_attr "op_type" "RRE,RXY,RIL")
765 (set_attr "z10prop" "z10_c,*,*")
766 (set_attr "type" "*,*,larl")])
770 (define_insn "*cmpsi_ccs_sign"
771 [(set (reg CC_REGNUM)
772 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
773 (match_operand:SI 0 "register_operand" "d,d,d")))]
774 "s390_match_ccmode(insn, CCSRmode)"
779 [(set_attr "op_type" "RX,RXY,RIL")
780 (set_attr "cpu_facility" "*,*,z10")
781 (set_attr "type" "*,*,larl")])
783 (define_insn "*cmphi_ccs_z10"
784 [(set (reg CC_REGNUM)
785 (compare (match_operand:HI 0 "s_operand" "Q")
786 (match_operand:HI 1 "immediate_operand" "K")))]
787 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
789 [(set_attr "op_type" "SIL")])
791 (define_insn "*cmpdi_ccs_signhi_rl"
792 [(set (reg CC_REGNUM)
793 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
794 (match_operand:GPR 0 "register_operand" "d,d")))]
795 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
799 [(set_attr "op_type" "RXY,RIL")
800 (set_attr "type" "*,larl")])
802 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
803 (define_insn "*cmp<mode>_ccs"
804 [(set (reg CC_REGNUM)
805 (compare (match_operand:GPR 0 "nonimmediate_operand"
807 (match_operand:GPR 1 "general_operand"
809 "s390_match_ccmode(insn, CCSmode)"
818 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
819 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
820 (set_attr "type" "*,*,*,*,*,*,larl")
821 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
824 ; Compare (unsigned) instructions
826 (define_insn "*cmpsi_ccu_zerohi_rlsi"
827 [(set (reg CC_REGNUM)
828 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
829 "larl_operand" "X")))
830 (match_operand:SI 0 "register_operand" "d")))]
831 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
833 [(set_attr "op_type" "RIL")
834 (set_attr "type" "larl")
835 (set_attr "z10prop" "z10_super")])
838 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
839 [(set (reg CC_REGNUM)
840 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
841 "larl_operand" "X")))
842 (match_operand:GPR 0 "register_operand" "d")))]
843 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
845 [(set_attr "op_type" "RIL")
846 (set_attr "type" "larl")
847 (set_attr "z10prop" "z10_super")])
849 (define_insn "*cmpdi_ccu_zero"
850 [(set (reg CC_REGNUM)
851 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
853 (match_operand:DI 0 "register_operand" "d, d,d")))]
854 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
859 [(set_attr "op_type" "RRE,RXY,RIL")
860 (set_attr "cpu_facility" "*,*,z10")
861 (set_attr "type" "*,*,larl")
862 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
864 (define_insn "*cmpdi_ccu"
865 [(set (reg CC_REGNUM)
866 (compare (match_operand:DI 0 "nonimmediate_operand"
868 (match_operand:DI 1 "general_operand"
869 "d,Op,b,D,RT,BQ,Q")))]
870 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
879 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
880 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
881 (set_attr "type" "*,*,larl,*,*,*,*")
882 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
884 (define_insn "*cmpsi_ccu"
885 [(set (reg CC_REGNUM)
886 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
887 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
888 "s390_match_ccmode (insn, CCUmode)"
898 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
899 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
900 (set_attr "type" "*,*,larl,*,*,*,*,*")
901 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
903 (define_insn "*cmphi_ccu"
904 [(set (reg CC_REGNUM)
905 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
906 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
907 "s390_match_ccmode (insn, CCUmode)
908 && !register_operand (operands[1], HImode)"
915 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
916 (set_attr "cpu_facility" "*,*,z10,*,*")
917 (set_attr "z10prop" "*,*,z10_super,*,*")])
919 (define_insn "*cmpqi_ccu"
920 [(set (reg CC_REGNUM)
921 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
922 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
923 "s390_match_ccmode (insn, CCUmode)
924 && !register_operand (operands[1], QImode)"
932 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
933 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
936 ; Block compare (CLC) instruction patterns.
939 [(set (reg CC_REGNUM)
940 (compare (match_operand:BLK 0 "memory_operand" "Q")
941 (match_operand:BLK 1 "memory_operand" "Q")))
942 (use (match_operand 2 "const_int_operand" "n"))]
943 "s390_match_ccmode (insn, CCUmode)
944 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
945 "clc\t%O0(%2,%R0),%S1"
946 [(set_attr "op_type" "SS")])
949 [(set (reg CC_REGNUM)
950 (compare (match_operand 0 "memory_operand" "")
951 (match_operand 1 "memory_operand" "")))]
953 && s390_match_ccmode (insn, CCUmode)
954 && GET_MODE (operands[0]) == GET_MODE (operands[1])
955 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
957 [(set (match_dup 0) (match_dup 1))
958 (use (match_dup 2))])]
960 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
961 operands[0] = adjust_address (operands[0], BLKmode, 0);
962 operands[1] = adjust_address (operands[1], BLKmode, 0);
964 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
965 operands[0], operands[1]);
966 operands[0] = SET_DEST (PATTERN (curr_insn));
970 ; (TF|DF|SF|TD|DD|SD) instructions
972 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
973 (define_insn "*cmp<mode>_ccs_0"
974 [(set (reg CC_REGNUM)
975 (compare (match_operand:FP 0 "register_operand" "f")
976 (match_operand:FP 1 "const0_operand" "")))]
977 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
978 "lt<xde><bt>r\t%0,%0"
979 [(set_attr "op_type" "RRE")
980 (set_attr "type" "fsimp<mode>")])
982 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
983 (define_insn "*cmp<mode>_ccs"
984 [(set (reg CC_REGNUM)
985 (compare (match_operand:FP 0 "register_operand" "f,f")
986 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
987 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
991 [(set_attr "op_type" "RRE,RXE")
992 (set_attr "type" "fsimp<mode>")])
995 ; Compare and Branch instructions
997 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
998 ; The following instructions do a complementary access of their second
999 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1000 (define_insn "*cmp_and_br_signed_<mode>"
1002 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1003 [(match_operand:GPR 1 "register_operand" "d,d")
1004 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1005 (label_ref (match_operand 3 "" ""))
1007 (clobber (reg:CC CC_REGNUM))]
1010 if (get_attr_length (insn) == 6)
1011 return which_alternative ?
1012 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1014 return which_alternative ?
1015 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1017 [(set_attr "op_type" "RIE")
1018 (set_attr "type" "branch")
1019 (set_attr "z10prop" "z10_super_c,z10_super")
1020 (set (attr "length")
1021 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1022 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1023 ; 10 byte for cgr/jg
1025 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1026 ; The following instructions do a complementary access of their second
1027 ; operand (z10 only): clrj, clgrj, clr, clgr
1028 (define_insn "*cmp_and_br_unsigned_<mode>"
1030 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1031 [(match_operand:GPR 1 "register_operand" "d,d")
1032 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1033 (label_ref (match_operand 3 "" ""))
1035 (clobber (reg:CC CC_REGNUM))]
1038 if (get_attr_length (insn) == 6)
1039 return which_alternative ?
1040 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1042 return which_alternative ?
1043 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1045 [(set_attr "op_type" "RIE")
1046 (set_attr "type" "branch")
1047 (set_attr "z10prop" "z10_super_c,z10_super")
1048 (set (attr "length")
1049 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1050 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1051 ; 10 byte for clgr/jg
1053 ; And now the same two patterns as above but with a negated CC mask.
1055 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1056 ; The following instructions do a complementary access of their second
1057 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1058 (define_insn "*icmp_and_br_signed_<mode>"
1060 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1061 [(match_operand:GPR 1 "register_operand" "d,d")
1062 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1064 (label_ref (match_operand 3 "" ""))))
1065 (clobber (reg:CC CC_REGNUM))]
1068 if (get_attr_length (insn) == 6)
1069 return which_alternative ?
1070 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1072 return which_alternative ?
1073 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1075 [(set_attr "op_type" "RIE")
1076 (set_attr "type" "branch")
1077 (set_attr "z10prop" "z10_super_c,z10_super")
1078 (set (attr "length")
1079 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1080 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1081 ; 10 byte for cgr/jg
1083 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1084 ; The following instructions do a complementary access of their second
1085 ; operand (z10 only): clrj, clgrj, clr, clgr
1086 (define_insn "*icmp_and_br_unsigned_<mode>"
1088 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1089 [(match_operand:GPR 1 "register_operand" "d,d")
1090 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1092 (label_ref (match_operand 3 "" ""))))
1093 (clobber (reg:CC CC_REGNUM))]
1096 if (get_attr_length (insn) == 6)
1097 return which_alternative ?
1098 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1100 return which_alternative ?
1101 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1103 [(set_attr "op_type" "RIE")
1104 (set_attr "type" "branch")
1105 (set_attr "z10prop" "z10_super_c,z10_super")
1106 (set (attr "length")
1107 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1108 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1109 ; 10 byte for clgr/jg
1112 ;;- Move instructions.
1116 ; movti instruction pattern(s).
1119 (define_insn "movti"
1120 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1121 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1128 [(set_attr "op_type" "RSY,RSY,*,*")
1129 (set_attr "type" "lm,stm,*,*")])
1132 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1133 (match_operand:TI 1 "general_operand" ""))]
1134 "TARGET_ZARCH && reload_completed
1135 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1136 [(set (match_dup 2) (match_dup 4))
1137 (set (match_dup 3) (match_dup 5))]
1139 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1140 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1141 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1142 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1146 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1147 (match_operand:TI 1 "general_operand" ""))]
1148 "TARGET_ZARCH && reload_completed
1149 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1150 [(set (match_dup 2) (match_dup 4))
1151 (set (match_dup 3) (match_dup 5))]
1153 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1154 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1155 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1156 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1160 [(set (match_operand:TI 0 "register_operand" "")
1161 (match_operand:TI 1 "memory_operand" ""))]
1162 "TARGET_ZARCH && reload_completed
1163 && !s_operand (operands[1], VOIDmode)"
1164 [(set (match_dup 0) (match_dup 1))]
1166 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1167 addr = gen_lowpart (Pmode, addr);
1168 s390_load_address (addr, XEXP (operands[1], 0));
1169 operands[1] = replace_equiv_address (operands[1], addr);
1174 ; Patterns used for secondary reloads
1177 ; z10 provides move instructions accepting larl memory operands.
1178 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1179 ; These patterns are also used for unaligned SI and DI accesses.
1181 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1182 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1183 (match_operand:INTALL 1 "register_operand" "=d")
1184 (match_operand:P 2 "register_operand" "=&a")])]
1187 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1191 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1192 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1193 (match_operand:INTALL 1 "memory_operand" "")
1194 (match_operand:P 2 "register_operand" "=a")])]
1197 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1201 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1202 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1203 (match_operand:FPALL 1 "register_operand" "=d")
1204 (match_operand:P 2 "register_operand" "=&a")])]
1207 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1211 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1212 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1213 (match_operand:FPALL 1 "memory_operand" "")
1214 (match_operand:P 2 "register_operand" "=a")])]
1217 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1221 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1222 [(parallel [(match_operand:P 0 "register_operand" "=d")
1223 (match_operand:P 1 "larl_operand" "")
1224 (match_operand:P 2 "register_operand" "=a")])]
1227 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1231 ; Handles loading a PLUS (load address) expression
1233 (define_expand "reload<mode>_plus"
1234 [(parallel [(match_operand:P 0 "register_operand" "=a")
1235 (match_operand:P 1 "s390_plus_operand" "")
1236 (match_operand:P 2 "register_operand" "=&a")])]
1239 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1243 ; Handles assessing a non-offsetable memory address
1245 (define_expand "reload<mode>_nonoffmem_in"
1246 [(parallel [(match_operand 0 "register_operand" "")
1247 (match_operand 1 "" "")
1248 (match_operand:P 2 "register_operand" "=&a")])]
1251 gcc_assert (MEM_P (operands[1]));
1252 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1253 operands[1] = replace_equiv_address (operands[1], operands[2]);
1254 emit_move_insn (operands[0], operands[1]);
1258 (define_expand "reload<mode>_nonoffmem_out"
1259 [(parallel [(match_operand 0 "" "")
1260 (match_operand 1 "register_operand" "")
1261 (match_operand:P 2 "register_operand" "=&a")])]
1264 gcc_assert (MEM_P (operands[0]));
1265 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1266 operands[0] = replace_equiv_address (operands[0], operands[2]);
1267 emit_move_insn (operands[0], operands[1]);
1271 (define_expand "reload<mode>_PIC_addr"
1272 [(parallel [(match_operand 0 "register_operand" "=d")
1273 (match_operand 1 "larl_operand" "")
1274 (match_operand:P 2 "register_operand" "=a")])]
1277 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1278 emit_move_insn (operands[0], new_rtx);
1282 ; movdi instruction pattern(s).
1285 (define_expand "movdi"
1286 [(set (match_operand:DI 0 "general_operand" "")
1287 (match_operand:DI 1 "general_operand" ""))]
1290 /* Handle symbolic constants. */
1292 && (SYMBOLIC_CONST (operands[1])
1293 || (GET_CODE (operands[1]) == PLUS
1294 && XEXP (operands[1], 0) == pic_offset_table_rtx
1295 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1296 emit_symbolic_move (operands);
1299 (define_insn "*movdi_larl"
1300 [(set (match_operand:DI 0 "register_operand" "=d")
1301 (match_operand:DI 1 "larl_operand" "X"))]
1303 && !FP_REG_P (operands[0])"
1305 [(set_attr "op_type" "RIL")
1306 (set_attr "type" "larl")
1307 (set_attr "z10prop" "z10_super_A1")])
1309 (define_insn "*movdi_64"
1310 [(set (match_operand:DI 0 "nonimmediate_operand"
1311 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1312 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1313 (match_operand:DI 1 "general_operand"
1314 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1315 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1344 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1345 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1346 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1347 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1349 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1350 z10,*,*,*,*,*,longdisp,*,longdisp,
1352 (set_attr "z10prop" "z10_fwd_A1,
1381 [(set (match_operand:DI 0 "register_operand" "")
1382 (match_operand:DI 1 "register_operand" ""))]
1383 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1384 [(set (match_dup 2) (match_dup 3))
1385 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1386 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1387 "operands[2] = gen_lowpart (SImode, operands[0]);
1388 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1391 [(set (match_operand:DI 0 "register_operand" "")
1392 (match_operand:DI 1 "register_operand" ""))]
1393 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1394 && dead_or_set_p (insn, operands[1])"
1395 [(set (match_dup 3) (match_dup 2))
1396 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1397 (set (match_dup 4) (match_dup 2))]
1398 "operands[2] = gen_lowpart (SImode, operands[1]);
1399 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1402 [(set (match_operand:DI 0 "register_operand" "")
1403 (match_operand:DI 1 "register_operand" ""))]
1404 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1405 && !dead_or_set_p (insn, operands[1])"
1406 [(set (match_dup 3) (match_dup 2))
1407 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1408 (set (match_dup 4) (match_dup 2))
1409 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1410 "operands[2] = gen_lowpart (SImode, operands[1]);
1411 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1413 (define_insn "*movdi_31"
1414 [(set (match_operand:DI 0 "nonimmediate_operand"
1415 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1416 (match_operand:DI 1 "general_operand"
1417 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1432 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1433 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1434 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1436 ; For a load from a symbol ref we can use one of the target registers
1437 ; together with larl to load the address.
1439 [(set (match_operand:DI 0 "register_operand" "")
1440 (match_operand:DI 1 "memory_operand" ""))]
1441 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1442 && larl_operand (XEXP (operands[1], 0), SImode)"
1443 [(set (match_dup 2) (match_dup 3))
1444 (set (match_dup 0) (match_dup 1))]
1446 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1447 operands[3] = XEXP (operands[1], 0);
1448 operands[1] = replace_equiv_address (operands[1], operands[2]);
1452 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1453 (match_operand:DI 1 "general_operand" ""))]
1454 "!TARGET_ZARCH && reload_completed
1455 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1456 [(set (match_dup 2) (match_dup 4))
1457 (set (match_dup 3) (match_dup 5))]
1459 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1460 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1461 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1462 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1466 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1467 (match_operand:DI 1 "general_operand" ""))]
1468 "!TARGET_ZARCH && reload_completed
1469 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1470 [(set (match_dup 2) (match_dup 4))
1471 (set (match_dup 3) (match_dup 5))]
1473 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1474 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1475 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1476 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1480 [(set (match_operand:DI 0 "register_operand" "")
1481 (match_operand:DI 1 "memory_operand" ""))]
1482 "!TARGET_ZARCH && reload_completed
1483 && !FP_REG_P (operands[0])
1484 && !s_operand (operands[1], VOIDmode)"
1485 [(set (match_dup 0) (match_dup 1))]
1487 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1488 s390_load_address (addr, XEXP (operands[1], 0));
1489 operands[1] = replace_equiv_address (operands[1], addr);
1493 [(set (match_operand:DI 0 "register_operand" "")
1494 (mem:DI (match_operand 1 "address_operand" "")))]
1496 && !FP_REG_P (operands[0])
1497 && GET_CODE (operands[1]) == SYMBOL_REF
1498 && CONSTANT_POOL_ADDRESS_P (operands[1])
1499 && get_pool_mode (operands[1]) == DImode
1500 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1501 [(set (match_dup 0) (match_dup 2))]
1502 "operands[2] = get_pool_constant (operands[1]);")
1504 (define_insn "*la_64"
1505 [(set (match_operand:DI 0 "register_operand" "=d,d")
1506 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1511 [(set_attr "op_type" "RX,RXY")
1512 (set_attr "type" "la")
1513 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1517 [(set (match_operand:DI 0 "register_operand" "")
1518 (match_operand:QI 1 "address_operand" ""))
1519 (clobber (reg:CC CC_REGNUM))])]
1521 && preferred_la_operand_p (operands[1], const0_rtx)"
1522 [(set (match_dup 0) (match_dup 1))]
1526 [(set (match_operand:DI 0 "register_operand" "")
1527 (match_operand:DI 1 "register_operand" ""))
1530 (plus:DI (match_dup 0)
1531 (match_operand:DI 2 "nonmemory_operand" "")))
1532 (clobber (reg:CC CC_REGNUM))])]
1534 && !reg_overlap_mentioned_p (operands[0], operands[2])
1535 && preferred_la_operand_p (operands[1], operands[2])"
1536 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1540 ; movsi instruction pattern(s).
1543 (define_expand "movsi"
1544 [(set (match_operand:SI 0 "general_operand" "")
1545 (match_operand:SI 1 "general_operand" ""))]
1548 /* Handle symbolic constants. */
1550 && (SYMBOLIC_CONST (operands[1])
1551 || (GET_CODE (operands[1]) == PLUS
1552 && XEXP (operands[1], 0) == pic_offset_table_rtx
1553 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1554 emit_symbolic_move (operands);
1557 (define_insn "*movsi_larl"
1558 [(set (match_operand:SI 0 "register_operand" "=d")
1559 (match_operand:SI 1 "larl_operand" "X"))]
1560 "!TARGET_64BIT && TARGET_CPU_ZARCH
1561 && !FP_REG_P (operands[0])"
1563 [(set_attr "op_type" "RIL")
1564 (set_attr "type" "larl")
1565 (set_attr "z10prop" "z10_fwd_A1")])
1567 (define_insn "*movsi_zarch"
1568 [(set (match_operand:SI 0 "nonimmediate_operand"
1569 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1570 (match_operand:SI 1 "general_operand"
1571 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1596 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1597 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1598 (set_attr "type" "*,
1620 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1621 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1622 (set_attr "z10prop" "z10_fwd_A1,
1645 (define_insn "*movsi_esa"
1646 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1647 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1661 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1662 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1663 (set_attr "z10prop" "z10_fwd_A1,
1677 [(set (match_operand:SI 0 "register_operand" "")
1678 (mem:SI (match_operand 1 "address_operand" "")))]
1679 "!FP_REG_P (operands[0])
1680 && GET_CODE (operands[1]) == SYMBOL_REF
1681 && CONSTANT_POOL_ADDRESS_P (operands[1])
1682 && get_pool_mode (operands[1]) == SImode
1683 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1684 [(set (match_dup 0) (match_dup 2))]
1685 "operands[2] = get_pool_constant (operands[1]);")
1687 (define_insn "*la_31"
1688 [(set (match_operand:SI 0 "register_operand" "=d,d")
1689 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1690 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1694 [(set_attr "op_type" "RX,RXY")
1695 (set_attr "type" "la")
1696 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1700 [(set (match_operand:SI 0 "register_operand" "")
1701 (match_operand:QI 1 "address_operand" ""))
1702 (clobber (reg:CC CC_REGNUM))])]
1704 && preferred_la_operand_p (operands[1], const0_rtx)"
1705 [(set (match_dup 0) (match_dup 1))]
1709 [(set (match_operand:SI 0 "register_operand" "")
1710 (match_operand:SI 1 "register_operand" ""))
1713 (plus:SI (match_dup 0)
1714 (match_operand:SI 2 "nonmemory_operand" "")))
1715 (clobber (reg:CC CC_REGNUM))])]
1717 && !reg_overlap_mentioned_p (operands[0], operands[2])
1718 && preferred_la_operand_p (operands[1], operands[2])"
1719 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1722 (define_insn "*la_31_and"
1723 [(set (match_operand:SI 0 "register_operand" "=d,d")
1724 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1725 (const_int 2147483647)))]
1730 [(set_attr "op_type" "RX,RXY")
1731 (set_attr "type" "la")
1732 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1734 (define_insn_and_split "*la_31_and_cc"
1735 [(set (match_operand:SI 0 "register_operand" "=d")
1736 (and:SI (match_operand:QI 1 "address_operand" "p")
1737 (const_int 2147483647)))
1738 (clobber (reg:CC CC_REGNUM))]
1741 "&& reload_completed"
1743 (and:SI (match_dup 1) (const_int 2147483647)))]
1745 [(set_attr "op_type" "RX")
1746 (set_attr "type" "la")])
1748 (define_insn "force_la_31"
1749 [(set (match_operand:SI 0 "register_operand" "=d,d")
1750 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1751 (use (const_int 0))]
1756 [(set_attr "op_type" "RX")
1757 (set_attr "type" "la")
1758 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1761 ; movhi instruction pattern(s).
1764 (define_expand "movhi"
1765 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1766 (match_operand:HI 1 "general_operand" ""))]
1769 /* Make it explicit that loading a register from memory
1770 always sign-extends (at least) to SImode. */
1771 if (optimize && can_create_pseudo_p ()
1772 && register_operand (operands[0], VOIDmode)
1773 && GET_CODE (operands[1]) == MEM)
1775 rtx tmp = gen_reg_rtx (SImode);
1776 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1777 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1778 operands[1] = gen_lowpart (HImode, tmp);
1782 (define_insn "*movhi"
1783 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1784 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1796 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1797 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1798 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1799 (set_attr "z10prop" "z10_fr_E1,
1810 [(set (match_operand:HI 0 "register_operand" "")
1811 (mem:HI (match_operand 1 "address_operand" "")))]
1812 "GET_CODE (operands[1]) == SYMBOL_REF
1813 && CONSTANT_POOL_ADDRESS_P (operands[1])
1814 && get_pool_mode (operands[1]) == HImode
1815 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1816 [(set (match_dup 0) (match_dup 2))]
1817 "operands[2] = get_pool_constant (operands[1]);")
1820 ; movqi instruction pattern(s).
1823 (define_expand "movqi"
1824 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1825 (match_operand:QI 1 "general_operand" ""))]
1828 /* On z/Architecture, zero-extending from memory to register
1829 is just as fast as a QImode load. */
1830 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1831 && register_operand (operands[0], VOIDmode)
1832 && GET_CODE (operands[1]) == MEM)
1834 rtx tmp = gen_reg_rtx (DImode);
1835 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1836 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1837 operands[1] = gen_lowpart (QImode, tmp);
1841 (define_insn "*movqi"
1842 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1843 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1855 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1856 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1857 (set_attr "z10prop" "z10_fr_E1,
1868 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1869 (mem:QI (match_operand 1 "address_operand" "")))]
1870 "GET_CODE (operands[1]) == SYMBOL_REF
1871 && CONSTANT_POOL_ADDRESS_P (operands[1])
1872 && get_pool_mode (operands[1]) == QImode
1873 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1874 [(set (match_dup 0) (match_dup 2))]
1875 "operands[2] = get_pool_constant (operands[1]);")
1878 ; movstrictqi instruction pattern(s).
1881 (define_insn "*movstrictqi"
1882 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1883 (match_operand:QI 1 "memory_operand" "R,T"))]
1888 [(set_attr "op_type" "RX,RXY")
1889 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1892 ; movstricthi instruction pattern(s).
1895 (define_insn "*movstricthi"
1896 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1897 (match_operand:HI 1 "memory_operand" "Q,S"))
1898 (clobber (reg:CC CC_REGNUM))]
1903 [(set_attr "op_type" "RS,RSY")
1904 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1907 ; movstrictsi instruction pattern(s).
1910 (define_insn "movstrictsi"
1911 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1912 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1919 [(set_attr "op_type" "RR,RX,RXY,RRE")
1920 (set_attr "type" "lr,load,load,*")
1921 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1924 ; mov(tf|td) instruction pattern(s).
1927 (define_expand "mov<mode>"
1928 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1929 (match_operand:TD_TF 1 "general_operand" ""))]
1933 (define_insn "*mov<mode>_64"
1934 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1935 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1946 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1947 (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
1949 (define_insn "*mov<mode>_31"
1950 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1951 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1958 [(set_attr "op_type" "RRE,RRE,*,*")
1959 (set_attr "type" "fhex,fsimptf,*,*")])
1961 ; TFmode in GPRs splitters
1964 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1965 (match_operand:TD_TF 1 "general_operand" ""))]
1966 "TARGET_ZARCH && reload_completed
1967 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1968 [(set (match_dup 2) (match_dup 4))
1969 (set (match_dup 3) (match_dup 5))]
1971 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1972 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1973 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1974 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1978 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1979 (match_operand:TD_TF 1 "general_operand" ""))]
1980 "TARGET_ZARCH && reload_completed
1981 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1982 [(set (match_dup 2) (match_dup 4))
1983 (set (match_dup 3) (match_dup 5))]
1985 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1986 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1987 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1988 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1992 [(set (match_operand:TD_TF 0 "register_operand" "")
1993 (match_operand:TD_TF 1 "memory_operand" ""))]
1994 "TARGET_ZARCH && reload_completed
1995 && !FP_REG_P (operands[0])
1996 && !s_operand (operands[1], VOIDmode)"
1997 [(set (match_dup 0) (match_dup 1))]
1999 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2000 s390_load_address (addr, XEXP (operands[1], 0));
2001 operands[1] = replace_equiv_address (operands[1], addr);
2004 ; TFmode in BFPs splitters
2007 [(set (match_operand:TD_TF 0 "register_operand" "")
2008 (match_operand:TD_TF 1 "memory_operand" ""))]
2009 "reload_completed && offsettable_memref_p (operands[1])
2010 && FP_REG_P (operands[0])"
2011 [(set (match_dup 2) (match_dup 4))
2012 (set (match_dup 3) (match_dup 5))]
2014 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2016 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2018 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2019 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2023 [(set (match_operand:TD_TF 0 "memory_operand" "")
2024 (match_operand:TD_TF 1 "register_operand" ""))]
2025 "reload_completed && offsettable_memref_p (operands[0])
2026 && FP_REG_P (operands[1])"
2027 [(set (match_dup 2) (match_dup 4))
2028 (set (match_dup 3) (match_dup 5))]
2030 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2031 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2032 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2034 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2039 ; mov(df|dd) instruction pattern(s).
2042 (define_expand "mov<mode>"
2043 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2044 (match_operand:DD_DF 1 "general_operand" ""))]
2048 (define_insn "*mov<mode>_64dfp"
2049 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2050 "=f,f,f,d,f,f,R,T,d, d,RT")
2051 (match_operand:DD_DF 1 "general_operand"
2052 " G,f,d,f,R,T,f,f,d,RT, d"))]
2066 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2067 (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
2068 fstoredf,fstoredf,lr,load,store")
2069 (set_attr "z10prop" "*,
2082 (define_insn "*mov<mode>_64"
2083 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2084 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2096 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2097 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2098 fstore<mode>,fstore<mode>,lr,load,store")
2099 (set_attr "z10prop" "*,
2109 (define_insn "*mov<mode>_31"
2110 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2111 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2112 (match_operand:DD_DF 1 "general_operand"
2113 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2128 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2129 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2130 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2133 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2134 (match_operand:DD_DF 1 "general_operand" ""))]
2135 "!TARGET_ZARCH && reload_completed
2136 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2137 [(set (match_dup 2) (match_dup 4))
2138 (set (match_dup 3) (match_dup 5))]
2140 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2141 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2142 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2143 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2147 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2148 (match_operand:DD_DF 1 "general_operand" ""))]
2149 "!TARGET_ZARCH && reload_completed
2150 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2151 [(set (match_dup 2) (match_dup 4))
2152 (set (match_dup 3) (match_dup 5))]
2154 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2155 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2156 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2157 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2161 [(set (match_operand:DD_DF 0 "register_operand" "")
2162 (match_operand:DD_DF 1 "memory_operand" ""))]
2163 "!TARGET_ZARCH && reload_completed
2164 && !FP_REG_P (operands[0])
2165 && !s_operand (operands[1], VOIDmode)"
2166 [(set (match_dup 0) (match_dup 1))]
2168 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2169 s390_load_address (addr, XEXP (operands[1], 0));
2170 operands[1] = replace_equiv_address (operands[1], addr);
2174 ; mov(sf|sd) instruction pattern(s).
2177 (define_insn "mov<mode>"
2178 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2179 "=f,f,f,f,R,T,d,d,d,R,T")
2180 (match_operand:SD_SF 1 "general_operand"
2181 " G,f,R,T,f,f,d,R,T,d,d"))]
2195 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2196 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2197 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2198 (set_attr "z10prop" "*,
2211 ; movcc instruction pattern
2214 (define_insn "movcc"
2215 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2216 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2226 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2227 (set_attr "type" "lr,*,*,store,store,load,load")
2228 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2231 ; Block move (MVC) patterns.
2235 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2236 (match_operand:BLK 1 "memory_operand" "Q"))
2237 (use (match_operand 2 "const_int_operand" "n"))]
2238 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2239 "mvc\t%O0(%2,%R0),%S1"
2240 [(set_attr "op_type" "SS")])
2242 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2243 ; order to have it implemented with mvc.
2246 [(set (match_operand:QI 0 "memory_operand" "")
2247 (match_operand:QI 1 "memory_operand" ""))]
2250 [(set (match_dup 0) (match_dup 1))
2251 (use (const_int 1))])]
2253 operands[0] = adjust_address (operands[0], BLKmode, 0);
2254 operands[1] = adjust_address (operands[1], BLKmode, 0);
2260 [(set (match_operand:BLK 0 "memory_operand" "")
2261 (match_operand:BLK 1 "memory_operand" ""))
2262 (use (match_operand 2 "const_int_operand" ""))])
2264 [(set (match_operand:BLK 3 "memory_operand" "")
2265 (match_operand:BLK 4 "memory_operand" ""))
2266 (use (match_operand 5 "const_int_operand" ""))])]
2267 "s390_offset_p (operands[0], operands[3], operands[2])
2268 && s390_offset_p (operands[1], operands[4], operands[2])
2269 && !s390_overlap_p (operands[0], operands[1],
2270 INTVAL (operands[2]) + INTVAL (operands[5]))
2271 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2273 [(set (match_dup 6) (match_dup 7))
2274 (use (match_dup 8))])]
2275 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2276 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2277 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2281 ; load_multiple pattern(s).
2283 ; ??? Due to reload problems with replacing registers inside match_parallel
2284 ; we currently support load_multiple/store_multiple only after reload.
2287 (define_expand "load_multiple"
2288 [(match_par_dup 3 [(set (match_operand 0 "" "")
2289 (match_operand 1 "" ""))
2290 (use (match_operand 2 "" ""))])]
2293 enum machine_mode mode;
2299 /* Support only loading a constant number of fixed-point registers from
2300 memory and only bother with this if more than two */
2301 if (GET_CODE (operands[2]) != CONST_INT
2302 || INTVAL (operands[2]) < 2
2303 || INTVAL (operands[2]) > 16
2304 || GET_CODE (operands[1]) != MEM
2305 || GET_CODE (operands[0]) != REG
2306 || REGNO (operands[0]) >= 16)
2309 count = INTVAL (operands[2]);
2310 regno = REGNO (operands[0]);
2311 mode = GET_MODE (operands[0]);
2312 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2315 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2316 if (!can_create_pseudo_p ())
2318 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2320 from = XEXP (operands[1], 0);
2323 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2324 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2325 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2327 from = XEXP (XEXP (operands[1], 0), 0);
2328 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2335 from = force_reg (Pmode, XEXP (operands[1], 0));
2339 for (i = 0; i < count; i++)
2340 XVECEXP (operands[3], 0, i)
2341 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2342 change_address (operands[1], mode,
2343 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2346 (define_insn "*load_multiple_di"
2347 [(match_parallel 0 "load_multiple_operation"
2348 [(set (match_operand:DI 1 "register_operand" "=r")
2349 (match_operand:DI 2 "s_operand" "QS"))])]
2350 "reload_completed && TARGET_ZARCH"
2352 int words = XVECLEN (operands[0], 0);
2353 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2354 return "lmg\t%1,%0,%S2";
2356 [(set_attr "op_type" "RSY")
2357 (set_attr "type" "lm")])
2359 (define_insn "*load_multiple_si"
2360 [(match_parallel 0 "load_multiple_operation"
2361 [(set (match_operand:SI 1 "register_operand" "=r,r")
2362 (match_operand:SI 2 "s_operand" "Q,S"))])]
2365 int words = XVECLEN (operands[0], 0);
2366 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2367 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2369 [(set_attr "op_type" "RS,RSY")
2370 (set_attr "type" "lm")])
2373 ; store multiple pattern(s).
2376 (define_expand "store_multiple"
2377 [(match_par_dup 3 [(set (match_operand 0 "" "")
2378 (match_operand 1 "" ""))
2379 (use (match_operand 2 "" ""))])]
2382 enum machine_mode mode;
2388 /* Support only storing a constant number of fixed-point registers to
2389 memory and only bother with this if more than two. */
2390 if (GET_CODE (operands[2]) != CONST_INT
2391 || INTVAL (operands[2]) < 2
2392 || INTVAL (operands[2]) > 16
2393 || GET_CODE (operands[0]) != MEM
2394 || GET_CODE (operands[1]) != REG
2395 || REGNO (operands[1]) >= 16)
2398 count = INTVAL (operands[2]);
2399 regno = REGNO (operands[1]);
2400 mode = GET_MODE (operands[1]);
2401 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2404 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2406 if (!can_create_pseudo_p ())
2408 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2410 to = XEXP (operands[0], 0);
2413 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2414 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2415 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2417 to = XEXP (XEXP (operands[0], 0), 0);
2418 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2425 to = force_reg (Pmode, XEXP (operands[0], 0));
2429 for (i = 0; i < count; i++)
2430 XVECEXP (operands[3], 0, i)
2431 = gen_rtx_SET (VOIDmode,
2432 change_address (operands[0], mode,
2433 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2434 gen_rtx_REG (mode, regno + i));
2437 (define_insn "*store_multiple_di"
2438 [(match_parallel 0 "store_multiple_operation"
2439 [(set (match_operand:DI 1 "s_operand" "=QS")
2440 (match_operand:DI 2 "register_operand" "r"))])]
2441 "reload_completed && TARGET_ZARCH"
2443 int words = XVECLEN (operands[0], 0);
2444 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2445 return "stmg\t%2,%0,%S1";
2447 [(set_attr "op_type" "RSY")
2448 (set_attr "type" "stm")])
2451 (define_insn "*store_multiple_si"
2452 [(match_parallel 0 "store_multiple_operation"
2453 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2454 (match_operand:SI 2 "register_operand" "r,r"))])]
2457 int words = XVECLEN (operands[0], 0);
2458 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2459 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2461 [(set_attr "op_type" "RS,RSY")
2462 (set_attr "type" "stm")])
2465 ;; String instructions.
2468 (define_insn "*execute_rl"
2469 [(match_parallel 0 ""
2470 [(unspec [(match_operand 1 "register_operand" "a")
2471 (match_operand 2 "" "")
2472 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2473 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2474 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2476 [(set_attr "op_type" "RIL")
2477 (set_attr "type" "cs")])
2479 (define_insn "*execute"
2480 [(match_parallel 0 ""
2481 [(unspec [(match_operand 1 "register_operand" "a")
2482 (match_operand:BLK 2 "memory_operand" "R")
2483 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2484 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2485 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2487 [(set_attr "op_type" "RX")
2488 (set_attr "type" "cs")])
2492 ; strlenM instruction pattern(s).
2495 (define_expand "strlen<mode>"
2496 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2499 (unspec:P [(const_int 0)
2500 (match_operand:BLK 1 "memory_operand" "")
2502 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2503 (clobber (scratch:P))
2504 (clobber (reg:CC CC_REGNUM))])
2506 [(set (match_operand:P 0 "register_operand" "")
2507 (minus:P (match_dup 4) (match_dup 5)))
2508 (clobber (reg:CC CC_REGNUM))])]
2511 operands[4] = gen_reg_rtx (Pmode);
2512 operands[5] = gen_reg_rtx (Pmode);
2513 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2514 operands[1] = replace_equiv_address (operands[1], operands[5]);
2517 (define_insn "*strlen<mode>"
2518 [(set (match_operand:P 0 "register_operand" "=a")
2519 (unspec:P [(match_operand:P 2 "general_operand" "0")
2520 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2522 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2523 (clobber (match_scratch:P 1 "=a"))
2524 (clobber (reg:CC CC_REGNUM))]
2526 "srst\t%0,%1\;jo\t.-4"
2527 [(set_attr "length" "8")
2528 (set_attr "type" "vs")])
2531 ; cmpstrM instruction pattern(s).
2534 (define_expand "cmpstrsi"
2535 [(set (reg:SI 0) (const_int 0))
2537 [(clobber (match_operand 3 "" ""))
2538 (clobber (match_dup 4))
2539 (set (reg:CCU CC_REGNUM)
2540 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2541 (match_operand:BLK 2 "memory_operand" "")))
2544 [(set (match_operand:SI 0 "register_operand" "=d")
2545 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2546 (clobber (reg:CC CC_REGNUM))])]
2549 /* As the result of CMPINT is inverted compared to what we need,
2550 we have to swap the operands. */
2551 rtx op1 = operands[2];
2552 rtx op2 = operands[1];
2553 rtx addr1 = gen_reg_rtx (Pmode);
2554 rtx addr2 = gen_reg_rtx (Pmode);
2556 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2557 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2558 operands[1] = replace_equiv_address_nv (op1, addr1);
2559 operands[2] = replace_equiv_address_nv (op2, addr2);
2560 operands[3] = addr1;
2561 operands[4] = addr2;
2564 (define_insn "*cmpstr<mode>"
2565 [(clobber (match_operand:P 0 "register_operand" "=d"))
2566 (clobber (match_operand:P 1 "register_operand" "=d"))
2567 (set (reg:CCU CC_REGNUM)
2568 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2569 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2572 "clst\t%0,%1\;jo\t.-4"
2573 [(set_attr "length" "8")
2574 (set_attr "type" "vs")])
2577 ; movstr instruction pattern.
2580 (define_expand "movstr"
2581 [(set (reg:SI 0) (const_int 0))
2583 [(clobber (match_dup 3))
2584 (set (match_operand:BLK 1 "memory_operand" "")
2585 (match_operand:BLK 2 "memory_operand" ""))
2586 (set (match_operand 0 "register_operand" "")
2587 (unspec [(match_dup 1)
2589 (reg:SI 0)] UNSPEC_MVST))
2590 (clobber (reg:CC CC_REGNUM))])]
2593 rtx addr1 = gen_reg_rtx (Pmode);
2594 rtx addr2 = gen_reg_rtx (Pmode);
2596 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2597 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2598 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2599 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2600 operands[3] = addr2;
2603 (define_insn "*movstr"
2604 [(clobber (match_operand:P 2 "register_operand" "=d"))
2605 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2606 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2607 (set (match_operand:P 0 "register_operand" "=d")
2608 (unspec [(mem:BLK (match_dup 1))
2609 (mem:BLK (match_dup 3))
2610 (reg:SI 0)] UNSPEC_MVST))
2611 (clobber (reg:CC CC_REGNUM))]
2613 "mvst\t%1,%2\;jo\t.-4"
2614 [(set_attr "length" "8")
2615 (set_attr "type" "vs")])
2619 ; movmemM instruction pattern(s).
2622 (define_expand "movmem<mode>"
2623 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2624 (match_operand:BLK 1 "memory_operand" "")) ; source
2625 (use (match_operand:GPR 2 "general_operand" "")) ; count
2626 (match_operand 3 "" "")]
2628 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2630 ; Move a block that is up to 256 bytes in length.
2631 ; The block length is taken as (operands[2] % 256) + 1.
2633 (define_expand "movmem_short"
2635 [(set (match_operand:BLK 0 "memory_operand" "")
2636 (match_operand:BLK 1 "memory_operand" ""))
2637 (use (match_operand 2 "nonmemory_operand" ""))
2638 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2639 (clobber (match_dup 3))])]
2641 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2643 (define_insn "*movmem_short"
2644 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2645 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2646 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2647 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2648 (clobber (match_scratch 4 "=X,X,X,&a"))]
2649 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2650 && GET_MODE (operands[4]) == Pmode"
2652 [(set_attr "type" "cs")
2653 (set_attr "cpu_facility" "*,*,z10,*")])
2656 [(set (match_operand:BLK 0 "memory_operand" "")
2657 (match_operand:BLK 1 "memory_operand" ""))
2658 (use (match_operand 2 "const_int_operand" ""))
2659 (use (match_operand 3 "immediate_operand" ""))
2660 (clobber (scratch))]
2663 [(set (match_dup 0) (match_dup 1))
2664 (use (match_dup 2))])]
2665 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2668 [(set (match_operand:BLK 0 "memory_operand" "")
2669 (match_operand:BLK 1 "memory_operand" ""))
2670 (use (match_operand 2 "register_operand" ""))
2671 (use (match_operand 3 "memory_operand" ""))
2672 (clobber (scratch))]
2675 [(unspec [(match_dup 2) (match_dup 3)
2676 (const_int 0)] UNSPEC_EXECUTE)
2677 (set (match_dup 0) (match_dup 1))
2678 (use (const_int 1))])]
2682 [(set (match_operand:BLK 0 "memory_operand" "")
2683 (match_operand:BLK 1 "memory_operand" ""))
2684 (use (match_operand 2 "register_operand" ""))
2685 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2686 (clobber (scratch))]
2687 "TARGET_Z10 && reload_completed"
2689 [(unspec [(match_dup 2) (const_int 0)
2690 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2691 (set (match_dup 0) (match_dup 1))
2692 (use (const_int 1))])]
2693 "operands[3] = gen_label_rtx ();")
2696 [(set (match_operand:BLK 0 "memory_operand" "")
2697 (match_operand:BLK 1 "memory_operand" ""))
2698 (use (match_operand 2 "register_operand" ""))
2699 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2700 (clobber (match_operand 3 "register_operand" ""))]
2701 "reload_completed && TARGET_CPU_ZARCH"
2702 [(set (match_dup 3) (label_ref (match_dup 4)))
2704 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2705 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2706 (set (match_dup 0) (match_dup 1))
2707 (use (const_int 1))])]
2708 "operands[4] = gen_label_rtx ();")
2710 ; Move a block of arbitrary length.
2712 (define_expand "movmem_long"
2714 [(clobber (match_dup 2))
2715 (clobber (match_dup 3))
2716 (set (match_operand:BLK 0 "memory_operand" "")
2717 (match_operand:BLK 1 "memory_operand" ""))
2718 (use (match_operand 2 "general_operand" ""))
2720 (clobber (reg:CC CC_REGNUM))])]
2723 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2724 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2725 rtx reg0 = gen_reg_rtx (dreg_mode);
2726 rtx reg1 = gen_reg_rtx (dreg_mode);
2727 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2728 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2729 rtx len0 = gen_lowpart (Pmode, reg0);
2730 rtx len1 = gen_lowpart (Pmode, reg1);
2732 emit_clobber (reg0);
2733 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2734 emit_move_insn (len0, operands[2]);
2736 emit_clobber (reg1);
2737 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2738 emit_move_insn (len1, operands[2]);
2740 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2741 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2746 (define_insn "*movmem_long"
2747 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2748 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2749 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2750 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2753 (clobber (reg:CC CC_REGNUM))]
2754 "TARGET_64BIT || !TARGET_ZARCH"
2755 "mvcle\t%0,%1,0\;jo\t.-4"
2756 [(set_attr "length" "8")
2757 (set_attr "type" "vs")])
2759 (define_insn "*movmem_long_31z"
2760 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2761 (clobber (match_operand:TI 1 "register_operand" "=d"))
2762 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2763 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2766 (clobber (reg:CC CC_REGNUM))]
2767 "!TARGET_64BIT && TARGET_ZARCH"
2768 "mvcle\t%0,%1,0\;jo\t.-4"
2769 [(set_attr "length" "8")
2770 (set_attr "type" "vs")])
2777 (define_expand "signbit<mode>2"
2778 [(set (reg:CCZ CC_REGNUM)
2779 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2782 (set (match_operand:SI 0 "register_operand" "=d")
2783 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2786 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2789 (define_expand "isinf<mode>2"
2790 [(set (reg:CCZ CC_REGNUM)
2791 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2794 (set (match_operand:SI 0 "register_operand" "=d")
2795 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2798 operands[2] = GEN_INT (S390_TDC_INFINITY);
2801 ; This insn is used to generate all variants of the Test Data Class
2802 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2803 ; is the register to be tested and the second one is the bit mask
2804 ; specifying the required test(s).
2806 (define_insn "*TDC_insn_<mode>"
2807 [(set (reg:CCZ CC_REGNUM)
2808 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2809 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2811 "t<_d>c<xde><bt>\t%0,%1"
2812 [(set_attr "op_type" "RXE")
2813 (set_attr "type" "fsimp<mode>")])
2815 (define_insn_and_split "*ccz_to_int"
2816 [(set (match_operand:SI 0 "register_operand" "=d")
2817 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2818 UNSPEC_CCZ_TO_INT))]
2822 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2826 ; setmemM instruction pattern(s).
2829 (define_expand "setmem<mode>"
2830 [(set (match_operand:BLK 0 "memory_operand" "")
2831 (match_operand:QI 2 "general_operand" ""))
2832 (use (match_operand:GPR 1 "general_operand" ""))
2833 (match_operand 3 "" "")]
2835 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2837 ; Clear a block that is up to 256 bytes in length.
2838 ; The block length is taken as (operands[1] % 256) + 1.
2840 (define_expand "clrmem_short"
2842 [(set (match_operand:BLK 0 "memory_operand" "")
2844 (use (match_operand 1 "nonmemory_operand" ""))
2845 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2846 (clobber (match_dup 2))
2847 (clobber (reg:CC CC_REGNUM))])]
2849 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2851 (define_insn "*clrmem_short"
2852 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2854 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2855 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2856 (clobber (match_scratch 3 "=X,X,X,&a"))
2857 (clobber (reg:CC CC_REGNUM))]
2858 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2859 && GET_MODE (operands[3]) == Pmode"
2861 [(set_attr "type" "cs")
2862 (set_attr "cpu_facility" "*,*,z10,*")])
2865 [(set (match_operand:BLK 0 "memory_operand" "")
2867 (use (match_operand 1 "const_int_operand" ""))
2868 (use (match_operand 2 "immediate_operand" ""))
2870 (clobber (reg:CC CC_REGNUM))]
2873 [(set (match_dup 0) (const_int 0))
2875 (clobber (reg:CC CC_REGNUM))])]
2876 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2879 [(set (match_operand:BLK 0 "memory_operand" "")
2881 (use (match_operand 1 "register_operand" ""))
2882 (use (match_operand 2 "memory_operand" ""))
2884 (clobber (reg:CC CC_REGNUM))]
2887 [(unspec [(match_dup 1) (match_dup 2)
2888 (const_int 0)] UNSPEC_EXECUTE)
2889 (set (match_dup 0) (const_int 0))
2891 (clobber (reg:CC CC_REGNUM))])]
2895 [(set (match_operand:BLK 0 "memory_operand" "")
2897 (use (match_operand 1 "register_operand" ""))
2898 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2900 (clobber (reg:CC CC_REGNUM))]
2901 "TARGET_Z10 && reload_completed"
2903 [(unspec [(match_dup 1) (const_int 0)
2904 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2905 (set (match_dup 0) (const_int 0))
2907 (clobber (reg:CC CC_REGNUM))])]
2908 "operands[3] = gen_label_rtx ();")
2911 [(set (match_operand:BLK 0 "memory_operand" "")
2913 (use (match_operand 1 "register_operand" ""))
2914 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2915 (clobber (match_operand 2 "register_operand" ""))
2916 (clobber (reg:CC CC_REGNUM))]
2917 "reload_completed && TARGET_CPU_ZARCH"
2918 [(set (match_dup 2) (label_ref (match_dup 3)))
2920 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2921 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2922 (set (match_dup 0) (const_int 0))
2924 (clobber (reg:CC CC_REGNUM))])]
2925 "operands[3] = gen_label_rtx ();")
2927 ; Initialize a block of arbitrary length with (operands[2] % 256).
2929 (define_expand "setmem_long"
2931 [(clobber (match_dup 1))
2932 (set (match_operand:BLK 0 "memory_operand" "")
2933 (match_operand 2 "shift_count_or_setmem_operand" ""))
2934 (use (match_operand 1 "general_operand" ""))
2936 (clobber (reg:CC CC_REGNUM))])]
2939 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2940 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2941 rtx reg0 = gen_reg_rtx (dreg_mode);
2942 rtx reg1 = gen_reg_rtx (dreg_mode);
2943 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2944 rtx len0 = gen_lowpart (Pmode, reg0);
2946 emit_clobber (reg0);
2947 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2948 emit_move_insn (len0, operands[1]);
2950 emit_move_insn (reg1, const0_rtx);
2952 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2957 (define_insn "*setmem_long"
2958 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2959 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2960 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2962 (use (match_operand:<DBL> 1 "register_operand" "d"))
2963 (clobber (reg:CC CC_REGNUM))]
2964 "TARGET_64BIT || !TARGET_ZARCH"
2965 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2966 [(set_attr "length" "8")
2967 (set_attr "type" "vs")])
2969 (define_insn "*setmem_long_and"
2970 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2971 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2972 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2973 (match_operand 4 "const_int_operand" "n")))
2975 (use (match_operand:<DBL> 1 "register_operand" "d"))
2976 (clobber (reg:CC CC_REGNUM))]
2977 "(TARGET_64BIT || !TARGET_ZARCH) &&
2978 (INTVAL (operands[4]) & 255) == 255"
2979 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2980 [(set_attr "length" "8")
2981 (set_attr "type" "vs")])
2983 (define_insn "*setmem_long_31z"
2984 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2985 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
2986 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2988 (use (match_operand:TI 1 "register_operand" "d"))
2989 (clobber (reg:CC CC_REGNUM))]
2990 "!TARGET_64BIT && TARGET_ZARCH"
2991 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2992 [(set_attr "length" "8")
2993 (set_attr "type" "vs")])
2996 ; cmpmemM instruction pattern(s).
2999 (define_expand "cmpmemsi"
3000 [(set (match_operand:SI 0 "register_operand" "")
3001 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3002 (match_operand:BLK 2 "memory_operand" "") ) )
3003 (use (match_operand:SI 3 "general_operand" ""))
3004 (use (match_operand:SI 4 "" ""))]
3006 "s390_expand_cmpmem (operands[0], operands[1],
3007 operands[2], operands[3]); DONE;")
3009 ; Compare a block that is up to 256 bytes in length.
3010 ; The block length is taken as (operands[2] % 256) + 1.
3012 (define_expand "cmpmem_short"
3014 [(set (reg:CCU CC_REGNUM)
3015 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3016 (match_operand:BLK 1 "memory_operand" "")))
3017 (use (match_operand 2 "nonmemory_operand" ""))
3018 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3019 (clobber (match_dup 3))])]
3021 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3023 (define_insn "*cmpmem_short"
3024 [(set (reg:CCU CC_REGNUM)
3025 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3026 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3027 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3028 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3029 (clobber (match_scratch 4 "=X,X,X,&a"))]
3030 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
3031 && GET_MODE (operands[4]) == Pmode"
3033 [(set_attr "type" "cs")
3034 (set_attr "cpu_facility" "*,*,z10,*")])
3037 [(set (reg:CCU CC_REGNUM)
3038 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3039 (match_operand:BLK 1 "memory_operand" "")))
3040 (use (match_operand 2 "const_int_operand" ""))
3041 (use (match_operand 3 "immediate_operand" ""))
3042 (clobber (scratch))]
3045 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3046 (use (match_dup 2))])]
3047 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3050 [(set (reg:CCU CC_REGNUM)
3051 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3052 (match_operand:BLK 1 "memory_operand" "")))
3053 (use (match_operand 2 "register_operand" ""))
3054 (use (match_operand 3 "memory_operand" ""))
3055 (clobber (scratch))]
3058 [(unspec [(match_dup 2) (match_dup 3)
3059 (const_int 0)] UNSPEC_EXECUTE)
3060 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3061 (use (const_int 1))])]
3065 [(set (reg:CCU CC_REGNUM)
3066 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3067 (match_operand:BLK 1 "memory_operand" "")))
3068 (use (match_operand 2 "register_operand" ""))
3069 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3070 (clobber (scratch))]
3071 "TARGET_Z10 && reload_completed"
3073 [(unspec [(match_dup 2) (const_int 0)
3074 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3075 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3076 (use (const_int 1))])]
3077 "operands[4] = gen_label_rtx ();")
3080 [(set (reg:CCU CC_REGNUM)
3081 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3082 (match_operand:BLK 1 "memory_operand" "")))
3083 (use (match_operand 2 "register_operand" ""))
3084 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3085 (clobber (match_operand 3 "register_operand" ""))]
3086 "reload_completed && TARGET_CPU_ZARCH"
3087 [(set (match_dup 3) (label_ref (match_dup 4)))
3089 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3090 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3091 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3092 (use (const_int 1))])]
3093 "operands[4] = gen_label_rtx ();")
3095 ; Compare a block of arbitrary length.
3097 (define_expand "cmpmem_long"
3099 [(clobber (match_dup 2))
3100 (clobber (match_dup 3))
3101 (set (reg:CCU CC_REGNUM)
3102 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3103 (match_operand:BLK 1 "memory_operand" "")))
3104 (use (match_operand 2 "general_operand" ""))
3105 (use (match_dup 3))])]
3108 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3109 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3110 rtx reg0 = gen_reg_rtx (dreg_mode);
3111 rtx reg1 = gen_reg_rtx (dreg_mode);
3112 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3113 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3114 rtx len0 = gen_lowpart (Pmode, reg0);
3115 rtx len1 = gen_lowpart (Pmode, reg1);
3117 emit_clobber (reg0);
3118 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3119 emit_move_insn (len0, operands[2]);
3121 emit_clobber (reg1);
3122 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3123 emit_move_insn (len1, operands[2]);
3125 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3126 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3131 (define_insn "*cmpmem_long"
3132 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3133 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3134 (set (reg:CCU CC_REGNUM)
3135 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3136 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3138 (use (match_dup 3))]
3139 "TARGET_64BIT || !TARGET_ZARCH"
3140 "clcle\t%0,%1,0\;jo\t.-4"
3141 [(set_attr "length" "8")
3142 (set_attr "type" "vs")])
3144 (define_insn "*cmpmem_long_31z"
3145 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3146 (clobber (match_operand:TI 1 "register_operand" "=d"))
3147 (set (reg:CCU CC_REGNUM)
3148 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3149 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3151 (use (match_dup 3))]
3152 "!TARGET_64BIT && TARGET_ZARCH"
3153 "clcle\t%0,%1,0\;jo\t.-4"
3154 [(set_attr "op_type" "NN")
3155 (set_attr "type" "vs")
3156 (set_attr "length" "8")])
3158 ; Convert CCUmode condition code to integer.
3159 ; Result is zero if EQ, positive if LTU, negative if GTU.
3161 (define_insn_and_split "cmpint"
3162 [(set (match_operand:SI 0 "register_operand" "=d")
3163 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3165 (clobber (reg:CC CC_REGNUM))]
3169 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3171 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3172 (clobber (reg:CC CC_REGNUM))])])
3174 (define_insn_and_split "*cmpint_cc"
3175 [(set (reg CC_REGNUM)
3176 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3179 (set (match_operand:SI 0 "register_operand" "=d")
3180 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3181 "s390_match_ccmode (insn, CCSmode)"
3183 "&& reload_completed"
3184 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3186 [(set (match_dup 2) (match_dup 3))
3187 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3189 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3190 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3191 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3194 (define_insn_and_split "*cmpint_sign"
3195 [(set (match_operand:DI 0 "register_operand" "=d")
3196 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3197 UNSPEC_CCU_TO_INT)))
3198 (clobber (reg:CC CC_REGNUM))]
3201 "&& reload_completed"
3202 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3204 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3205 (clobber (reg:CC CC_REGNUM))])])
3207 (define_insn_and_split "*cmpint_sign_cc"
3208 [(set (reg CC_REGNUM)
3209 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3210 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3211 UNSPEC_CCU_TO_INT) 0)
3212 (const_int 32)) (const_int 32))
3214 (set (match_operand:DI 0 "register_operand" "=d")
3215 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3216 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3218 "&& reload_completed"
3219 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3221 [(set (match_dup 2) (match_dup 3))
3222 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3224 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3225 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3226 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3231 ;;- Conversion instructions.
3234 (define_insn "*sethighpartsi"
3235 [(set (match_operand:SI 0 "register_operand" "=d,d")
3236 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3237 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3238 (clobber (reg:CC CC_REGNUM))]
3243 [(set_attr "op_type" "RS,RSY")
3244 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3246 (define_insn "*sethighpartdi_64"
3247 [(set (match_operand:DI 0 "register_operand" "=d")
3248 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3249 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3250 (clobber (reg:CC CC_REGNUM))]
3253 [(set_attr "op_type" "RSY")
3254 (set_attr "z10prop" "z10_super")])
3256 (define_insn "*sethighpartdi_31"
3257 [(set (match_operand:DI 0 "register_operand" "=d,d")
3258 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3259 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3260 (clobber (reg:CC CC_REGNUM))]
3265 [(set_attr "op_type" "RS,RSY")
3266 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3269 (define_insn_and_split "*extzv<mode>"
3270 [(set (match_operand:GPR 0 "register_operand" "=d")
3271 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3272 (match_operand 2 "const_int_operand" "n")
3274 (clobber (reg:CC CC_REGNUM))]
3275 "INTVAL (operands[2]) > 0
3276 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3278 "&& reload_completed"
3280 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3281 (clobber (reg:CC CC_REGNUM))])
3282 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3284 int bitsize = INTVAL (operands[2]);
3285 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3286 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3288 operands[1] = adjust_address (operands[1], BLKmode, 0);
3289 set_mem_size (operands[1], GEN_INT (size));
3290 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3291 operands[3] = GEN_INT (mask);
3294 (define_insn_and_split "*extv<mode>"
3295 [(set (match_operand:GPR 0 "register_operand" "=d")
3296 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3297 (match_operand 2 "const_int_operand" "n")
3299 (clobber (reg:CC CC_REGNUM))]
3300 "INTVAL (operands[2]) > 0
3301 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3303 "&& reload_completed"
3305 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3306 (clobber (reg:CC CC_REGNUM))])
3308 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3309 (clobber (reg:CC CC_REGNUM))])]
3311 int bitsize = INTVAL (operands[2]);
3312 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3313 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3315 operands[1] = adjust_address (operands[1], BLKmode, 0);
3316 set_mem_size (operands[1], GEN_INT (size));
3317 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3318 operands[3] = GEN_INT (mask);
3322 ; insv instruction patterns
3325 (define_expand "insv"
3326 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3327 (match_operand 1 "const_int_operand" "")
3328 (match_operand 2 "const_int_operand" ""))
3329 (match_operand 3 "general_operand" ""))]
3332 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3337 (define_insn "*insv<mode>_z10"
3338 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3339 (match_operand 1 "const_int_operand" "I")
3340 (match_operand 2 "const_int_operand" "I"))
3341 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3342 (clobber (reg:CC CC_REGNUM))]
3344 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3345 GET_MODE_BITSIZE (<MODE>mode)"
3347 int start = INTVAL (operands[2]);
3348 int size = INTVAL (operands[1]);
3349 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3351 operands[2] = GEN_INT (offset + start); /* start bit position */
3352 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3353 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3354 start - size); /* left shift count */
3356 return "risbg\t%0,%3,%b2,%b1,%b4";
3358 [(set_attr "op_type" "RIE")
3359 (set_attr "z10prop" "z10_super_E1")])
3361 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3362 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3363 (define_insn "*insv<mode>_z10_noshift"
3364 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3365 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3366 (match_operand 2 "const_int_operand" "n"))
3367 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3368 (match_operand 4 "const_int_operand" "n"))))
3369 (clobber (reg:CC CC_REGNUM))]
3371 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3372 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3373 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3379 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3380 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3382 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3383 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3384 operands[7] = const0_rtx; /* left shift count */
3386 return "risbg\t%0,%1,%b5,%b6,%b7";
3388 [(set_attr "op_type" "RIE")
3389 (set_attr "z10prop" "z10_super_E1")])
3391 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3392 (define_insn "*insv<mode>_or_z10_noshift"
3393 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3394 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3395 (match_operand 2 "const_int_operand" "n"))
3396 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3397 (clobber (reg:CC CC_REGNUM))]
3399 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3400 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3405 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3406 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3408 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3409 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3410 operands[6] = const0_rtx; /* left shift count */
3412 return "rosbg\t%0,%1,%b4,%b5,%b6";
3414 [(set_attr "op_type" "RIE")])
3416 (define_insn "*insv<mode>_mem_reg"
3417 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3418 (match_operand 1 "const_int_operand" "n,n")
3420 (match_operand:W 2 "register_operand" "d,d"))]
3421 "INTVAL (operands[1]) > 0
3422 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3423 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3425 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3427 operands[1] = GEN_INT ((1ul << size) - 1);
3428 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3429 : "stcmy\t%2,%1,%S0";
3431 [(set_attr "op_type" "RS,RSY")
3432 (set_attr "z10prop" "z10_super,z10_super")])
3434 (define_insn "*insvdi_mem_reghigh"
3435 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3436 (match_operand 1 "const_int_operand" "n")
3438 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3441 && INTVAL (operands[1]) > 0
3442 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3443 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3445 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3447 operands[1] = GEN_INT ((1ul << size) - 1);
3448 return "stcmh\t%2,%1,%S0";
3450 [(set_attr "op_type" "RSY")
3451 (set_attr "z10prop" "z10_super")])
3453 (define_insn "*insvdi_reg_imm"
3454 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3456 (match_operand 1 "const_int_operand" "n"))
3457 (match_operand:DI 2 "const_int_operand" "n"))]
3459 && INTVAL (operands[1]) >= 0
3460 && INTVAL (operands[1]) < BITS_PER_WORD
3461 && INTVAL (operands[1]) % 16 == 0"
3463 switch (BITS_PER_WORD - INTVAL (operands[1]))
3465 case 64: return "iihh\t%0,%x2"; break;
3466 case 48: return "iihl\t%0,%x2"; break;
3467 case 32: return "iilh\t%0,%x2"; break;
3468 case 16: return "iill\t%0,%x2"; break;
3469 default: gcc_unreachable();
3472 [(set_attr "op_type" "RI")
3473 (set_attr "z10prop" "z10_super_E1")])
3475 ; Update the left-most 32 bit of a DI.
3476 (define_insn "*insv_h_di_reg_extimm"
3477 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3480 (match_operand:DI 1 "const_int_operand" "n"))]
3483 [(set_attr "op_type" "RIL")
3484 (set_attr "z10prop" "z10_fwd_E1")])
3486 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3487 (define_insn "*insv_l<mode>_reg_extimm"
3488 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3490 (match_operand 1 "const_int_operand" "n"))
3491 (match_operand:P 2 "const_int_operand" "n"))]
3493 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3495 [(set_attr "op_type" "RIL")
3496 (set_attr "z10prop" "z10_fwd_A1")])
3499 ; extendsidi2 instruction pattern(s).
3502 (define_expand "extendsidi2"
3503 [(set (match_operand:DI 0 "register_operand" "")
3504 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3509 emit_clobber (operands[0]);
3510 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3511 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3512 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3517 (define_insn "*extendsidi2"
3518 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3519 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3525 [(set_attr "op_type" "RRE,RXY,RIL")
3526 (set_attr "type" "*,*,larl")
3527 (set_attr "cpu_facility" "*,*,z10")
3528 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3531 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3534 (define_expand "extend<HQI:mode><DSI:mode>2"
3535 [(set (match_operand:DSI 0 "register_operand" "")
3536 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3539 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3541 rtx tmp = gen_reg_rtx (SImode);
3542 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3543 emit_insn (gen_extendsidi2 (operands[0], tmp));
3546 else if (!TARGET_EXTIMM)
3548 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3549 GET_MODE_BITSIZE (<HQI:MODE>mode));
3551 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3552 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3553 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3559 ; extendhidi2 instruction pattern(s).
3562 (define_insn "*extendhidi2_extimm"
3563 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3564 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3565 "TARGET_ZARCH && TARGET_EXTIMM"
3570 [(set_attr "op_type" "RRE,RXY,RIL")
3571 (set_attr "type" "*,*,larl")
3572 (set_attr "cpu_facility" "extimm,extimm,z10")
3573 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3575 (define_insn "*extendhidi2"
3576 [(set (match_operand:DI 0 "register_operand" "=d")
3577 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3580 [(set_attr "op_type" "RXY")
3581 (set_attr "z10prop" "z10_super_E1")])
3584 ; extendhisi2 instruction pattern(s).
3587 (define_insn "*extendhisi2_extimm"
3588 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3589 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3596 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3597 (set_attr "type" "*,*,*,larl")
3598 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3599 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3601 (define_insn "*extendhisi2"
3602 [(set (match_operand:SI 0 "register_operand" "=d,d")
3603 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3608 [(set_attr "op_type" "RX,RXY")
3609 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3612 ; extendqi(si|di)2 instruction pattern(s).
3615 ; lbr, lgbr, lb, lgb
3616 (define_insn "*extendqi<mode>2_extimm"
3617 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3618 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3623 [(set_attr "op_type" "RRE,RXY")
3624 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3627 (define_insn "*extendqi<mode>2"
3628 [(set (match_operand:GPR 0 "register_operand" "=d")
3629 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3630 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3632 [(set_attr "op_type" "RXY")
3633 (set_attr "z10prop" "z10_super_E1")])
3635 (define_insn_and_split "*extendqi<mode>2_short_displ"
3636 [(set (match_operand:GPR 0 "register_operand" "=d")
3637 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3638 (clobber (reg:CC CC_REGNUM))]
3639 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3641 "&& reload_completed"
3643 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3644 (clobber (reg:CC CC_REGNUM))])
3646 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3647 (clobber (reg:CC CC_REGNUM))])]
3649 operands[1] = adjust_address (operands[1], BLKmode, 0);
3650 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3651 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3652 - GET_MODE_BITSIZE (QImode));
3656 ; zero_extendsidi2 instruction pattern(s).
3659 (define_expand "zero_extendsidi2"
3660 [(set (match_operand:DI 0 "register_operand" "")
3661 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3666 emit_clobber (operands[0]);
3667 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3668 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3673 (define_insn "*zero_extendsidi2"
3674 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3675 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3681 [(set_attr "op_type" "RRE,RXY,RIL")
3682 (set_attr "type" "*,*,larl")
3683 (set_attr "cpu_facility" "*,*,z10")
3684 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3687 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3690 (define_insn "*llgt_sidi"
3691 [(set (match_operand:DI 0 "register_operand" "=d")
3692 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3693 (const_int 2147483647)))]
3696 [(set_attr "op_type" "RXE")
3697 (set_attr "z10prop" "z10_super_E1")])
3699 (define_insn_and_split "*llgt_sidi_split"
3700 [(set (match_operand:DI 0 "register_operand" "=d")
3701 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3702 (const_int 2147483647)))
3703 (clobber (reg:CC CC_REGNUM))]
3706 "&& reload_completed"
3708 (and:DI (subreg:DI (match_dup 1) 0)
3709 (const_int 2147483647)))]
3712 (define_insn "*llgt_sisi"
3713 [(set (match_operand:SI 0 "register_operand" "=d,d")
3714 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3715 (const_int 2147483647)))]
3720 [(set_attr "op_type" "RRE,RXE")
3721 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3723 (define_insn "*llgt_didi"
3724 [(set (match_operand:DI 0 "register_operand" "=d,d")
3725 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3726 (const_int 2147483647)))]
3731 [(set_attr "op_type" "RRE,RXE")
3732 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3735 [(set (match_operand:DSI 0 "register_operand" "")
3736 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3737 (const_int 2147483647)))
3738 (clobber (reg:CC CC_REGNUM))]
3739 "TARGET_ZARCH && reload_completed"
3741 (and:DSI (match_dup 1)
3742 (const_int 2147483647)))]
3746 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3749 (define_expand "zero_extend<mode>di2"
3750 [(set (match_operand:DI 0 "register_operand" "")
3751 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3756 rtx tmp = gen_reg_rtx (SImode);
3757 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3758 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3761 else if (!TARGET_EXTIMM)
3763 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3764 GET_MODE_BITSIZE(<MODE>mode));
3765 operands[1] = gen_lowpart (DImode, operands[1]);
3766 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3767 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3772 (define_expand "zero_extend<mode>si2"
3773 [(set (match_operand:SI 0 "register_operand" "")
3774 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3779 operands[1] = gen_lowpart (SImode, operands[1]);
3780 emit_insn (gen_andsi3 (operands[0], operands[1],
3781 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3787 (define_insn "*zero_extendhi<mode>2_z10"
3788 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3789 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3795 [(set_attr "op_type" "RXY,RRE,RIL")
3796 (set_attr "type" "*,*,larl")
3797 (set_attr "cpu_facility" "*,*,z10")
3798 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3800 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3801 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3802 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3803 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3808 [(set_attr "op_type" "RRE,RXY")
3809 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3812 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3813 [(set (match_operand:GPR 0 "register_operand" "=d")
3814 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3815 "TARGET_ZARCH && !TARGET_EXTIMM"
3817 [(set_attr "op_type" "RXY")
3818 (set_attr "z10prop" "z10_fwd_A3")])
3820 (define_insn_and_split "*zero_extendhisi2_31"
3821 [(set (match_operand:SI 0 "register_operand" "=&d")
3822 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3823 (clobber (reg:CC CC_REGNUM))]
3826 "&& reload_completed"
3827 [(set (match_dup 0) (const_int 0))
3829 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3830 (clobber (reg:CC CC_REGNUM))])]
3831 "operands[2] = gen_lowpart (HImode, operands[0]);")
3833 (define_insn_and_split "*zero_extendqisi2_31"
3834 [(set (match_operand:SI 0 "register_operand" "=&d")
3835 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3838 "&& reload_completed"
3839 [(set (match_dup 0) (const_int 0))
3840 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3841 "operands[2] = gen_lowpart (QImode, operands[0]);")
3844 ; zero_extendqihi2 instruction pattern(s).
3847 (define_expand "zero_extendqihi2"
3848 [(set (match_operand:HI 0 "register_operand" "")
3849 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3850 "TARGET_ZARCH && !TARGET_EXTIMM"
3852 operands[1] = gen_lowpart (HImode, operands[1]);
3853 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3857 (define_insn "*zero_extendqihi2_64"
3858 [(set (match_operand:HI 0 "register_operand" "=d")
3859 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3860 "TARGET_ZARCH && !TARGET_EXTIMM"
3862 [(set_attr "op_type" "RXY")
3863 (set_attr "z10prop" "z10_fwd_A3")])
3865 (define_insn_and_split "*zero_extendqihi2_31"
3866 [(set (match_operand:HI 0 "register_operand" "=&d")
3867 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3870 "&& reload_completed"
3871 [(set (match_dup 0) (const_int 0))
3872 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3873 "operands[2] = gen_lowpart (QImode, operands[0]);")
3876 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3879 (define_expand "fixuns_truncdddi2"
3881 [(set (match_operand:DI 0 "register_operand" "")
3882 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3883 (clobber (match_scratch:TD 2 "=f"))])]
3887 rtx label1 = gen_label_rtx ();
3888 rtx label2 = gen_label_rtx ();
3889 rtx temp = gen_reg_rtx (TDmode);
3890 REAL_VALUE_TYPE cmp, sub;
3892 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3893 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3895 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3896 solution is doing the check and the subtraction in TD mode and using a
3897 TD -> DI convert afterwards. */
3898 emit_insn (gen_extendddtd2 (temp, operands[1]));
3899 temp = force_reg (TDmode, temp);
3900 emit_cmp_and_jump_insns (temp,
3901 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3902 LT, NULL_RTX, VOIDmode, 0, label1);
3903 emit_insn (gen_subtd3 (temp, temp,
3904 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3905 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3908 emit_label (label1);
3909 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3910 emit_label (label2);
3914 (define_expand "fixuns_trunctddi2"
3915 [(set (match_operand:DI 0 "register_operand" "")
3916 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3919 rtx label1 = gen_label_rtx ();
3920 rtx label2 = gen_label_rtx ();
3921 rtx temp = gen_reg_rtx (TDmode);
3922 REAL_VALUE_TYPE cmp, sub;
3924 operands[1] = force_reg (TDmode, operands[1]);
3925 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3926 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3928 emit_cmp_and_jump_insns (operands[1],
3929 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3930 LT, NULL_RTX, VOIDmode, 0, label1);
3931 emit_insn (gen_subtd3 (temp, operands[1],
3932 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3933 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3936 emit_label (label1);
3937 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3938 emit_label (label2);
3943 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3944 ; instruction pattern(s).
3947 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3948 [(set (match_operand:GPR 0 "register_operand" "")
3949 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3952 rtx label1 = gen_label_rtx ();
3953 rtx label2 = gen_label_rtx ();
3954 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3955 REAL_VALUE_TYPE cmp, sub;
3957 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3958 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3959 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3961 emit_cmp_and_jump_insns (operands[1],
3962 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3963 LT, NULL_RTX, VOIDmode, 0, label1);
3964 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3965 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3966 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3970 emit_label (label1);
3971 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3972 operands[1], GEN_INT (5)));
3973 emit_label (label2);
3977 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3978 [(set (match_operand:GPR 0 "register_operand" "")
3979 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3982 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3987 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3988 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3989 [(set (match_operand:GPR 0 "register_operand" "=d")
3990 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3991 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3992 (clobber (reg:CC CC_REGNUM))]
3994 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3995 [(set_attr "op_type" "RRE")
3996 (set_attr "type" "ftoi")])
4000 ; fix_trunc(td|dd)di2 instruction pattern(s).
4003 (define_expand "fix_trunc<mode>di2"
4004 [(set (match_operand:DI 0 "register_operand" "")
4005 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4006 "TARGET_ZARCH && TARGET_HARD_DFP"
4008 operands[1] = force_reg (<MODE>mode, operands[1]);
4009 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4015 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4016 [(set (match_operand:DI 0 "register_operand" "=d")
4017 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4018 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4019 (clobber (reg:CC CC_REGNUM))]
4020 "TARGET_ZARCH && TARGET_HARD_DFP"
4021 "cg<DFP:xde>tr\t%0,%h2,%1"
4022 [(set_attr "op_type" "RRF")
4023 (set_attr "type" "ftoidfp")])
4027 ; fix_trunctf(si|di)2 instruction pattern(s).
4030 (define_expand "fix_trunctf<mode>2"
4031 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4032 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4033 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4034 (clobber (reg:CC CC_REGNUM))])]
4040 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4043 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4044 (define_insn "floatdi<mode>2"
4045 [(set (match_operand:FP 0 "register_operand" "=f")
4046 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4047 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4048 "c<xde>g<bt>r\t%0,%1"
4049 [(set_attr "op_type" "RRE")
4050 (set_attr "type" "itof<mode>" )])
4052 ; cxfbr, cdfbr, cefbr
4053 (define_insn "floatsi<mode>2"
4054 [(set (match_operand:BFP 0 "register_operand" "=f")
4055 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4058 [(set_attr "op_type" "RRE")
4059 (set_attr "type" "itof<mode>" )])
4063 ; truncdfsf2 instruction pattern(s).
4066 (define_insn "truncdfsf2"
4067 [(set (match_operand:SF 0 "register_operand" "=f")
4068 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4071 [(set_attr "op_type" "RRE")
4072 (set_attr "type" "ftruncdf")])
4075 ; trunctf(df|sf)2 instruction pattern(s).
4079 (define_insn "trunctf<mode>2"
4080 [(set (match_operand:DSF 0 "register_operand" "=f")
4081 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4082 (clobber (match_scratch:TF 2 "=f"))]
4084 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4085 [(set_attr "length" "6")
4086 (set_attr "type" "ftrunctf")])
4089 ; trunctddd2 and truncddsd2 instruction pattern(s).
4092 (define_insn "trunctddd2"
4093 [(set (match_operand:DD 0 "register_operand" "=f")
4094 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4095 (clobber (match_scratch:TD 2 "=f"))]
4097 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4098 [(set_attr "length" "6")
4099 (set_attr "type" "ftruncdd")])
4101 (define_insn "truncddsd2"
4102 [(set (match_operand:SD 0 "register_operand" "=f")
4103 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4106 [(set_attr "op_type" "RRF")
4107 (set_attr "type" "ftruncsd")])
4110 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4113 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4114 (define_insn "extend<DSF:mode><BFP:mode>2"
4115 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4116 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4118 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4120 l<BFP:xde><DSF:xde>br\t%0,%1
4121 l<BFP:xde><DSF:xde>b\t%0,%1"
4122 [(set_attr "op_type" "RRE,RXE")
4123 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4126 ; extendddtd2 and extendsddd2 instruction pattern(s).
4129 (define_insn "extendddtd2"
4130 [(set (match_operand:TD 0 "register_operand" "=f")
4131 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4134 [(set_attr "op_type" "RRF")
4135 (set_attr "type" "fsimptf")])
4137 (define_insn "extendsddd2"
4138 [(set (match_operand:DD 0 "register_operand" "=f")
4139 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4142 [(set_attr "op_type" "RRF")
4143 (set_attr "type" "fsimptf")])
4145 ; Binary <-> Decimal floating point trunc patterns
4148 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4149 [(set (reg:DFP_ALL FPR0_REGNUM)
4150 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4151 (use (reg:SI GPR0_REGNUM))
4152 (clobber (reg:CC CC_REGNUM))]
4156 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4157 [(set (reg:BFP FPR0_REGNUM)
4158 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4159 (use (reg:SI GPR0_REGNUM))
4160 (clobber (reg:CC CC_REGNUM))]
4164 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4165 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4166 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4168 [(set (reg:DFP_ALL FPR0_REGNUM)
4169 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4170 (use (reg:SI GPR0_REGNUM))
4171 (clobber (reg:CC CC_REGNUM))])
4172 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4173 (reg:DFP_ALL FPR0_REGNUM))]
4175 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4177 HOST_WIDE_INT flags;
4179 flags = (PFPO_CONVERT |
4180 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4181 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4183 operands[2] = GEN_INT (flags);
4186 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4187 [(set (reg:DFP_ALL FPR2_REGNUM)
4188 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4189 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4191 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4192 (use (reg:SI GPR0_REGNUM))
4193 (clobber (reg:CC CC_REGNUM))])
4194 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4196 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4198 HOST_WIDE_INT flags;
4200 flags = (PFPO_CONVERT |
4201 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4202 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4204 operands[2] = GEN_INT (flags);
4208 ; Binary <-> Decimal floating point extend patterns
4211 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4212 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4213 (use (reg:SI GPR0_REGNUM))
4214 (clobber (reg:CC CC_REGNUM))]
4218 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4219 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4220 (use (reg:SI GPR0_REGNUM))
4221 (clobber (reg:CC CC_REGNUM))]
4225 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4226 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4227 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4229 [(set (reg:DFP_ALL FPR0_REGNUM)
4230 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4231 (use (reg:SI GPR0_REGNUM))
4232 (clobber (reg:CC CC_REGNUM))])
4233 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4234 (reg:DFP_ALL FPR0_REGNUM))]
4236 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4238 HOST_WIDE_INT flags;
4240 flags = (PFPO_CONVERT |
4241 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4242 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4244 operands[2] = GEN_INT (flags);
4247 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4248 [(set (reg:DFP_ALL FPR2_REGNUM)
4249 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4250 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4252 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4253 (use (reg:SI GPR0_REGNUM))
4254 (clobber (reg:CC CC_REGNUM))])
4255 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4257 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4259 HOST_WIDE_INT flags;
4261 flags = (PFPO_CONVERT |
4262 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4263 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4265 operands[2] = GEN_INT (flags);
4270 ;; ARITHMETIC OPERATIONS
4272 ; arithmetic operations set the ConditionCode,
4273 ; because of unpredictable Bits in Register for Halfword and Byte
4274 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4277 ;;- Add instructions.
4281 ; addti3 instruction pattern(s).
4284 (define_insn_and_split "addti3"
4285 [(set (match_operand:TI 0 "register_operand" "=&d")
4286 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4287 (match_operand:TI 2 "general_operand" "do") ) )
4288 (clobber (reg:CC CC_REGNUM))]
4291 "&& reload_completed"
4293 [(set (reg:CCL1 CC_REGNUM)
4294 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4296 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4298 [(set (match_dup 3) (plus:DI
4299 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4300 (match_dup 4)) (match_dup 5)))
4301 (clobber (reg:CC CC_REGNUM))])]
4302 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4303 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4304 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4305 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4306 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4307 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4310 ; adddi3 instruction pattern(s).
4313 (define_expand "adddi3"
4315 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4316 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4317 (match_operand:DI 2 "general_operand" "")))
4318 (clobber (reg:CC CC_REGNUM))])]
4322 (define_insn "*adddi3_sign"
4323 [(set (match_operand:DI 0 "register_operand" "=d,d")
4324 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4325 (match_operand:DI 1 "register_operand" "0,0")))
4326 (clobber (reg:CC CC_REGNUM))]
4331 [(set_attr "op_type" "RRE,RXY")])
4333 (define_insn "*adddi3_zero_cc"
4334 [(set (reg CC_REGNUM)
4335 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4336 (match_operand:DI 1 "register_operand" "0,0"))
4338 (set (match_operand:DI 0 "register_operand" "=d,d")
4339 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4340 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4344 [(set_attr "op_type" "RRE,RXY")
4345 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4347 (define_insn "*adddi3_zero_cconly"
4348 [(set (reg CC_REGNUM)
4349 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4350 (match_operand:DI 1 "register_operand" "0,0"))
4352 (clobber (match_scratch:DI 0 "=d,d"))]
4353 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4357 [(set_attr "op_type" "RRE,RXY")
4358 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4360 (define_insn "*adddi3_zero"
4361 [(set (match_operand:DI 0 "register_operand" "=d,d")
4362 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4363 (match_operand:DI 1 "register_operand" "0,0")))
4364 (clobber (reg:CC CC_REGNUM))]
4369 [(set_attr "op_type" "RRE,RXY")
4370 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4372 (define_insn_and_split "*adddi3_31z"
4373 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4374 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4375 (match_operand:DI 2 "general_operand" "do") ) )
4376 (clobber (reg:CC CC_REGNUM))]
4377 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4379 "&& reload_completed"
4381 [(set (reg:CCL1 CC_REGNUM)
4382 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4384 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4386 [(set (match_dup 3) (plus:SI
4387 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4388 (match_dup 4)) (match_dup 5)))
4389 (clobber (reg:CC CC_REGNUM))])]
4390 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4391 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4392 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4393 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4394 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4395 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4397 (define_insn_and_split "*adddi3_31"
4398 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4399 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4400 (match_operand:DI 2 "general_operand" "do") ) )
4401 (clobber (reg:CC CC_REGNUM))]
4404 "&& reload_completed"
4406 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4407 (clobber (reg:CC CC_REGNUM))])
4409 [(set (reg:CCL1 CC_REGNUM)
4410 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4412 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4414 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4416 (label_ref (match_dup 9))))
4418 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4419 (clobber (reg:CC CC_REGNUM))])
4421 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4422 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4423 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4424 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4425 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4426 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4427 operands[9] = gen_label_rtx ();")
4430 ; addsi3 instruction pattern(s).
4433 (define_expand "addsi3"
4435 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4436 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4437 (match_operand:SI 2 "general_operand" "")))
4438 (clobber (reg:CC CC_REGNUM))])]
4442 (define_insn "*addsi3_sign"
4443 [(set (match_operand:SI 0 "register_operand" "=d,d")
4444 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4445 (match_operand:SI 1 "register_operand" "0,0")))
4446 (clobber (reg:CC CC_REGNUM))]
4451 [(set_attr "op_type" "RX,RXY")])
4454 ; add(di|si)3 instruction pattern(s).
4457 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4458 (define_insn "*add<mode>3"
4459 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4460 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4461 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4462 (clobber (reg:CC CC_REGNUM))]
4472 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4473 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4474 (set_attr "z10prop" "z10_super_E1,
4482 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4483 (define_insn "*add<mode>3_carry1_cc"
4484 [(set (reg CC_REGNUM)
4485 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4486 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4488 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4489 (plus:GPR (match_dup 1) (match_dup 2)))]
4490 "s390_match_ccmode (insn, CCL1mode)"
4498 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4499 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4500 (set_attr "z10prop" "z10_super_E1,
4507 ; alr, al, aly, algr, alg
4508 (define_insn "*add<mode>3_carry1_cconly"
4509 [(set (reg CC_REGNUM)
4510 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4511 (match_operand:GPR 2 "general_operand" "d,R,T"))
4513 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4514 "s390_match_ccmode (insn, CCL1mode)"
4519 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4520 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4522 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4523 (define_insn "*add<mode>3_carry2_cc"
4524 [(set (reg CC_REGNUM)
4525 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4526 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4528 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4529 (plus:GPR (match_dup 1) (match_dup 2)))]
4530 "s390_match_ccmode (insn, CCL1mode)"
4538 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4539 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4540 (set_attr "z10prop" "z10_super_E1,
4547 ; alr, al, aly, algr, alg
4548 (define_insn "*add<mode>3_carry2_cconly"
4549 [(set (reg CC_REGNUM)
4550 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4551 (match_operand:GPR 2 "general_operand" "d,R,T"))
4553 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4554 "s390_match_ccmode (insn, CCL1mode)"
4559 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4560 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4562 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4563 (define_insn "*add<mode>3_cc"
4564 [(set (reg CC_REGNUM)
4565 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4566 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4568 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4569 (plus:GPR (match_dup 1) (match_dup 2)))]
4570 "s390_match_ccmode (insn, CCLmode)"
4578 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4579 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4580 (set_attr "z10prop" "z10_super_E1,
4587 ; alr, al, aly, algr, alg
4588 (define_insn "*add<mode>3_cconly"
4589 [(set (reg CC_REGNUM)
4590 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4591 (match_operand:GPR 2 "general_operand" "d,R,T"))
4593 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4594 "s390_match_ccmode (insn, CCLmode)"
4599 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4600 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4602 ; alr, al, aly, algr, alg
4603 (define_insn "*add<mode>3_cconly2"
4604 [(set (reg CC_REGNUM)
4605 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4606 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4607 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4608 "s390_match_ccmode(insn, CCLmode)"
4613 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4614 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4616 ; ahi, afi, aghi, agfi, asi, agsi
4617 (define_insn "*add<mode>3_imm_cc"
4618 [(set (reg CC_REGNUM)
4619 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4620 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4622 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4623 (plus:GPR (match_dup 1) (match_dup 2)))]
4624 "s390_match_ccmode (insn, CCAmode)
4625 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4626 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4627 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4628 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4633 [(set_attr "op_type" "RI,RIL,SIY")
4634 (set_attr "cpu_facility" "*,extimm,z10")
4635 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4638 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4641 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4642 (define_insn "add<mode>3"
4643 [(set (match_operand:FP 0 "register_operand" "=f, f")
4644 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4645 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4646 (clobber (reg:CC CC_REGNUM))]
4649 a<xde><bt>r\t%0,<op1>%2
4651 [(set_attr "op_type" "<RRer>,RXE")
4652 (set_attr "type" "fsimp<mode>")])
4654 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4655 (define_insn "*add<mode>3_cc"
4656 [(set (reg CC_REGNUM)
4657 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4658 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4659 (match_operand:FP 3 "const0_operand" "")))
4660 (set (match_operand:FP 0 "register_operand" "=f,f")
4661 (plus:FP (match_dup 1) (match_dup 2)))]
4662 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4664 a<xde><bt>r\t%0,<op1>%2
4666 [(set_attr "op_type" "<RRer>,RXE")
4667 (set_attr "type" "fsimp<mode>")])
4669 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4670 (define_insn "*add<mode>3_cconly"
4671 [(set (reg CC_REGNUM)
4672 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4673 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4674 (match_operand:FP 3 "const0_operand" "")))
4675 (clobber (match_scratch:FP 0 "=f,f"))]
4676 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4678 a<xde><bt>r\t%0,<op1>%2
4680 [(set_attr "op_type" "<RRer>,RXE")
4681 (set_attr "type" "fsimp<mode>")])
4685 ;;- Subtract instructions.
4689 ; subti3 instruction pattern(s).
4692 (define_insn_and_split "subti3"
4693 [(set (match_operand:TI 0 "register_operand" "=&d")
4694 (minus:TI (match_operand:TI 1 "register_operand" "0")
4695 (match_operand:TI 2 "general_operand" "do") ) )
4696 (clobber (reg:CC CC_REGNUM))]
4699 "&& reload_completed"
4701 [(set (reg:CCL2 CC_REGNUM)
4702 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4704 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4706 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4707 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4708 (clobber (reg:CC CC_REGNUM))])]
4709 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4710 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4711 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4712 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4713 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4714 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4717 ; subdi3 instruction pattern(s).
4720 (define_expand "subdi3"
4722 [(set (match_operand:DI 0 "register_operand" "")
4723 (minus:DI (match_operand:DI 1 "register_operand" "")
4724 (match_operand:DI 2 "general_operand" "")))
4725 (clobber (reg:CC CC_REGNUM))])]
4729 (define_insn "*subdi3_sign"
4730 [(set (match_operand:DI 0 "register_operand" "=d,d")
4731 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4732 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4733 (clobber (reg:CC CC_REGNUM))]
4738 [(set_attr "op_type" "RRE,RXY")
4739 (set_attr "z10prop" "z10_c,*")])
4741 (define_insn "*subdi3_zero_cc"
4742 [(set (reg CC_REGNUM)
4743 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4744 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4746 (set (match_operand:DI 0 "register_operand" "=d,d")
4747 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4748 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4752 [(set_attr "op_type" "RRE,RXY")
4753 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4755 (define_insn "*subdi3_zero_cconly"
4756 [(set (reg CC_REGNUM)
4757 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4758 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4760 (clobber (match_scratch:DI 0 "=d,d"))]
4761 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4765 [(set_attr "op_type" "RRE,RXY")
4766 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4768 (define_insn "*subdi3_zero"
4769 [(set (match_operand:DI 0 "register_operand" "=d,d")
4770 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4771 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4772 (clobber (reg:CC CC_REGNUM))]
4777 [(set_attr "op_type" "RRE,RXY")
4778 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4780 (define_insn_and_split "*subdi3_31z"
4781 [(set (match_operand:DI 0 "register_operand" "=&d")
4782 (minus:DI (match_operand:DI 1 "register_operand" "0")
4783 (match_operand:DI 2 "general_operand" "do") ) )
4784 (clobber (reg:CC CC_REGNUM))]
4785 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4787 "&& reload_completed"
4789 [(set (reg:CCL2 CC_REGNUM)
4790 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4792 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4794 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4795 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4796 (clobber (reg:CC CC_REGNUM))])]
4797 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4798 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4799 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4800 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4801 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4802 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4804 (define_insn_and_split "*subdi3_31"
4805 [(set (match_operand:DI 0 "register_operand" "=&d")
4806 (minus:DI (match_operand:DI 1 "register_operand" "0")
4807 (match_operand:DI 2 "general_operand" "do") ) )
4808 (clobber (reg:CC CC_REGNUM))]
4811 "&& reload_completed"
4813 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4814 (clobber (reg:CC CC_REGNUM))])
4816 [(set (reg:CCL2 CC_REGNUM)
4817 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4819 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4821 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4823 (label_ref (match_dup 9))))
4825 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4826 (clobber (reg:CC CC_REGNUM))])
4828 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4829 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4830 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4831 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4832 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4833 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4834 operands[9] = gen_label_rtx ();")
4837 ; subsi3 instruction pattern(s).
4840 (define_expand "subsi3"
4842 [(set (match_operand:SI 0 "register_operand" "")
4843 (minus:SI (match_operand:SI 1 "register_operand" "")
4844 (match_operand:SI 2 "general_operand" "")))
4845 (clobber (reg:CC CC_REGNUM))])]
4849 (define_insn "*subsi3_sign"
4850 [(set (match_operand:SI 0 "register_operand" "=d,d")
4851 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4852 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4853 (clobber (reg:CC CC_REGNUM))]
4858 [(set_attr "op_type" "RX,RXY")])
4861 ; sub(di|si)3 instruction pattern(s).
4864 ; sr, s, sy, sgr, sg
4865 (define_insn "*sub<mode>3"
4866 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4867 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4868 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4869 (clobber (reg:CC CC_REGNUM))]
4875 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4876 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4878 ; slr, sl, sly, slgr, slg
4879 (define_insn "*sub<mode>3_borrow_cc"
4880 [(set (reg CC_REGNUM)
4881 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4882 (match_operand:GPR 2 "general_operand" "d,R,T"))
4884 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4885 (minus:GPR (match_dup 1) (match_dup 2)))]
4886 "s390_match_ccmode (insn, CCL2mode)"
4891 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4892 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4894 ; slr, sl, sly, slgr, slg
4895 (define_insn "*sub<mode>3_borrow_cconly"
4896 [(set (reg CC_REGNUM)
4897 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4898 (match_operand:GPR 2 "general_operand" "d,R,T"))
4900 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4901 "s390_match_ccmode (insn, CCL2mode)"
4906 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4907 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4909 ; slr, sl, sly, slgr, slg
4910 (define_insn "*sub<mode>3_cc"
4911 [(set (reg CC_REGNUM)
4912 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4913 (match_operand:GPR 2 "general_operand" "d,R,T"))
4915 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4916 (minus:GPR (match_dup 1) (match_dup 2)))]
4917 "s390_match_ccmode (insn, CCLmode)"
4922 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4923 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4925 ; slr, sl, sly, slgr, slg
4926 (define_insn "*sub<mode>3_cc2"
4927 [(set (reg CC_REGNUM)
4928 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4929 (match_operand:GPR 2 "general_operand" "d,R,T")))
4930 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4931 (minus:GPR (match_dup 1) (match_dup 2)))]
4932 "s390_match_ccmode (insn, CCL3mode)"
4937 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4938 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4940 ; slr, sl, sly, slgr, slg
4941 (define_insn "*sub<mode>3_cconly"
4942 [(set (reg CC_REGNUM)
4943 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4944 (match_operand:GPR 2 "general_operand" "d,R,T"))
4946 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4947 "s390_match_ccmode (insn, CCLmode)"
4952 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4953 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4956 ; slr, sl, sly, slgr, slg
4957 (define_insn "*sub<mode>3_cconly2"
4958 [(set (reg CC_REGNUM)
4959 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4960 (match_operand:GPR 2 "general_operand" "d,R,T")))
4961 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4962 "s390_match_ccmode (insn, CCL3mode)"
4967 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4968 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4972 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4975 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4976 (define_insn "sub<mode>3"
4977 [(set (match_operand:FP 0 "register_operand" "=f, f")
4978 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4979 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4980 (clobber (reg:CC CC_REGNUM))]
4983 s<xde><bt>r\t%0,<op1>%2
4985 [(set_attr "op_type" "<RRer>,RXE")
4986 (set_attr "type" "fsimp<mode>")])
4988 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4989 (define_insn "*sub<mode>3_cc"
4990 [(set (reg CC_REGNUM)
4991 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4992 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4993 (match_operand:FP 3 "const0_operand" "")))
4994 (set (match_operand:FP 0 "register_operand" "=f,f")
4995 (minus:FP (match_dup 1) (match_dup 2)))]
4996 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4998 s<xde><bt>r\t%0,<op1>%2
5000 [(set_attr "op_type" "<RRer>,RXE")
5001 (set_attr "type" "fsimp<mode>")])
5003 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5004 (define_insn "*sub<mode>3_cconly"
5005 [(set (reg CC_REGNUM)
5006 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5007 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5008 (match_operand:FP 3 "const0_operand" "")))
5009 (clobber (match_scratch:FP 0 "=f,f"))]
5010 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5012 s<xde><bt>r\t%0,<op1>%2
5014 [(set_attr "op_type" "<RRer>,RXE")
5015 (set_attr "type" "fsimp<mode>")])
5019 ;;- Conditional add/subtract instructions.
5023 ; add(di|si)cc instruction pattern(s).
5026 ; the following 4 patterns are used when the result of an add with
5027 ; carry is checked for an overflow condition
5029 ; op1 + op2 + c < op1
5031 ; alcr, alc, alcgr, alcg
5032 (define_insn "*add<mode>3_alc_carry1_cc"
5033 [(set (reg CC_REGNUM)
5035 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5036 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5037 (match_operand:GPR 2 "general_operand" "d,RT"))
5039 (set (match_operand:GPR 0 "register_operand" "=d,d")
5040 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5041 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5045 [(set_attr "op_type" "RRE,RXY")])
5047 ; alcr, alc, alcgr, alcg
5048 (define_insn "*add<mode>3_alc_carry1_cconly"
5049 [(set (reg CC_REGNUM)
5051 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5052 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5053 (match_operand:GPR 2 "general_operand" "d,RT"))
5055 (clobber (match_scratch:GPR 0 "=d,d"))]
5056 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5060 [(set_attr "op_type" "RRE,RXY")])
5062 ; op1 + op2 + c < op2
5064 ; alcr, alc, alcgr, alcg
5065 (define_insn "*add<mode>3_alc_carry2_cc"
5066 [(set (reg CC_REGNUM)
5068 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5069 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5070 (match_operand:GPR 2 "general_operand" "d,RT"))
5072 (set (match_operand:GPR 0 "register_operand" "=d,d")
5073 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5074 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5078 [(set_attr "op_type" "RRE,RXY")])
5080 ; alcr, alc, alcgr, alcg
5081 (define_insn "*add<mode>3_alc_carry2_cconly"
5082 [(set (reg CC_REGNUM)
5084 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5085 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5086 (match_operand:GPR 2 "general_operand" "d,RT"))
5088 (clobber (match_scratch:GPR 0 "=d,d"))]
5089 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5093 [(set_attr "op_type" "RRE,RXY")])
5095 ; alcr, alc, alcgr, alcg
5096 (define_insn "*add<mode>3_alc_cc"
5097 [(set (reg CC_REGNUM)
5099 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5100 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5101 (match_operand:GPR 2 "general_operand" "d,RT"))
5103 (set (match_operand:GPR 0 "register_operand" "=d,d")
5104 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5105 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5109 [(set_attr "op_type" "RRE,RXY")])
5111 ; alcr, alc, alcgr, alcg
5112 (define_insn "*add<mode>3_alc"
5113 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5114 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5115 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5116 (match_operand:GPR 2 "general_operand" "d,RT")))
5117 (clobber (reg:CC CC_REGNUM))]
5122 [(set_attr "op_type" "RRE,RXY")])
5124 ; slbr, slb, slbgr, slbg
5125 (define_insn "*sub<mode>3_slb_cc"
5126 [(set (reg CC_REGNUM)
5128 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5129 (match_operand:GPR 2 "general_operand" "d,RT"))
5130 (match_operand:GPR 3 "s390_slb_comparison" ""))
5132 (set (match_operand:GPR 0 "register_operand" "=d,d")
5133 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5134 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5138 [(set_attr "op_type" "RRE,RXY")
5139 (set_attr "z10prop" "z10_c,*")])
5141 ; slbr, slb, slbgr, slbg
5142 (define_insn "*sub<mode>3_slb"
5143 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5144 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5145 (match_operand:GPR 2 "general_operand" "d,RT"))
5146 (match_operand:GPR 3 "s390_slb_comparison" "")))
5147 (clobber (reg:CC CC_REGNUM))]
5152 [(set_attr "op_type" "RRE,RXY")
5153 (set_attr "z10prop" "z10_c,*")])
5155 (define_expand "add<mode>cc"
5156 [(match_operand:GPR 0 "register_operand" "")
5157 (match_operand 1 "comparison_operator" "")
5158 (match_operand:GPR 2 "register_operand" "")
5159 (match_operand:GPR 3 "const_int_operand" "")]
5161 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5162 XEXP (operands[1], 0), XEXP (operands[1], 1),
5163 operands[0], operands[2],
5164 operands[3])) FAIL; DONE;")
5167 ; scond instruction pattern(s).
5170 (define_insn_and_split "*scond<mode>"
5171 [(set (match_operand:GPR 0 "register_operand" "=&d")
5172 (match_operand:GPR 1 "s390_alc_comparison" ""))
5173 (clobber (reg:CC CC_REGNUM))]
5176 "&& reload_completed"
5177 [(set (match_dup 0) (const_int 0))
5179 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5181 (clobber (reg:CC CC_REGNUM))])]
5184 (define_insn_and_split "*scond<mode>_neg"
5185 [(set (match_operand:GPR 0 "register_operand" "=&d")
5186 (match_operand:GPR 1 "s390_slb_comparison" ""))
5187 (clobber (reg:CC CC_REGNUM))]
5190 "&& reload_completed"
5191 [(set (match_dup 0) (const_int 0))
5193 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5195 (clobber (reg:CC CC_REGNUM))])
5197 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5198 (clobber (reg:CC CC_REGNUM))])]
5202 (define_expand "cstore<mode>4"
5203 [(set (match_operand:SI 0 "register_operand" "")
5204 (match_operator:SI 1 "s390_scond_operator"
5205 [(match_operand:GPR 2 "register_operand" "")
5206 (match_operand:GPR 3 "general_operand" "")]))]
5208 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5209 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5211 (define_expand "cstorecc4"
5213 [(set (match_operand:SI 0 "register_operand" "")
5214 (match_operator:SI 1 "s390_eqne_operator"
5215 [(match_operand:CCZ1 2 "register_operand")
5216 (match_operand 3 "const0_operand")]))
5217 (clobber (reg:CC CC_REGNUM))])]
5219 "emit_insn (gen_sne (operands[0], operands[2]));
5220 if (GET_CODE (operands[1]) == EQ)
5221 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5224 (define_insn_and_split "sne"
5225 [(set (match_operand:SI 0 "register_operand" "=d")
5226 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5228 (clobber (reg:CC CC_REGNUM))]
5233 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5234 (clobber (reg:CC CC_REGNUM))])])
5238 ;;- Multiply instructions.
5242 ; muldi3 instruction pattern(s).
5245 (define_insn "*muldi3_sign"
5246 [(set (match_operand:DI 0 "register_operand" "=d,d")
5247 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5248 (match_operand:DI 1 "register_operand" "0,0")))]
5253 [(set_attr "op_type" "RRE,RXY")
5254 (set_attr "type" "imuldi")])
5256 (define_insn "muldi3"
5257 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5258 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5259 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5266 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5267 (set_attr "type" "imuldi")
5268 (set_attr "cpu_facility" "*,*,*,z10")])
5271 ; mulsi3 instruction pattern(s).
5274 (define_insn "*mulsi3_sign"
5275 [(set (match_operand:SI 0 "register_operand" "=d,d")
5276 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5277 (match_operand:SI 1 "register_operand" "0,0")))]
5282 [(set_attr "op_type" "RX,RXY")
5283 (set_attr "type" "imulhi")
5284 (set_attr "cpu_facility" "*,z10")])
5286 (define_insn "mulsi3"
5287 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5288 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5289 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5297 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5298 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5299 (set_attr "cpu_facility" "*,*,*,*,z10")])
5302 ; mulsidi3 instruction pattern(s).
5305 (define_insn "mulsidi3"
5306 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5307 (mult:DI (sign_extend:DI
5308 (match_operand:SI 1 "register_operand" "%0,0,0"))
5310 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5316 [(set_attr "op_type" "RR,RX,RXY")
5317 (set_attr "type" "imulsi")
5318 (set_attr "cpu_facility" "*,*,z10")])
5321 ; umulsidi3 instruction pattern(s).
5324 (define_insn "umulsidi3"
5325 [(set (match_operand:DI 0 "register_operand" "=d,d")
5326 (mult:DI (zero_extend:DI
5327 (match_operand:SI 1 "register_operand" "%0,0"))
5329 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5330 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5334 [(set_attr "op_type" "RRE,RXY")
5335 (set_attr "type" "imulsi")])
5338 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5341 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5342 (define_insn "mul<mode>3"
5343 [(set (match_operand:FP 0 "register_operand" "=f,f")
5344 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5345 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5348 m<xdee><bt>r\t%0,<op1>%2
5350 [(set_attr "op_type" "<RRer>,RXE")
5351 (set_attr "type" "fmul<mode>")])
5353 ; madbr, maebr, maxb, madb, maeb
5354 (define_insn "*fmadd<mode>"
5355 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5356 (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5357 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5358 (match_operand:DSF 3 "register_operand" "0,0")))]
5359 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5363 [(set_attr "op_type" "RRE,RXE")
5364 (set_attr "type" "fmul<mode>")])
5366 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5367 (define_insn "*fmsub<mode>"
5368 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5369 (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f")
5370 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5371 (match_operand:DSF 3 "register_operand" "0,0")))]
5372 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5376 [(set_attr "op_type" "RRE,RXE")
5377 (set_attr "type" "fmul<mode>")])
5380 ;;- Divide and modulo instructions.
5384 ; divmoddi4 instruction pattern(s).
5387 (define_expand "divmoddi4"
5388 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5389 (div:DI (match_operand:DI 1 "register_operand" "")
5390 (match_operand:DI 2 "general_operand" "")))
5391 (set (match_operand:DI 3 "general_operand" "")
5392 (mod:DI (match_dup 1) (match_dup 2)))])
5393 (clobber (match_dup 4))]
5396 rtx insn, div_equal, mod_equal;
5398 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5399 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5401 operands[4] = gen_reg_rtx(TImode);
5402 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5404 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5405 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5407 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5408 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5413 (define_insn "divmodtidi3"
5414 [(set (match_operand:TI 0 "register_operand" "=d,d")
5418 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5419 (match_operand:DI 2 "general_operand" "d,RT")))
5421 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5426 [(set_attr "op_type" "RRE,RXY")
5427 (set_attr "type" "idiv")])
5429 (define_insn "divmodtisi3"
5430 [(set (match_operand:TI 0 "register_operand" "=d,d")
5434 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5436 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5439 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5444 [(set_attr "op_type" "RRE,RXY")
5445 (set_attr "type" "idiv")])
5448 ; udivmoddi4 instruction pattern(s).
5451 (define_expand "udivmoddi4"
5452 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5453 (udiv:DI (match_operand:DI 1 "general_operand" "")
5454 (match_operand:DI 2 "nonimmediate_operand" "")))
5455 (set (match_operand:DI 3 "general_operand" "")
5456 (umod:DI (match_dup 1) (match_dup 2)))])
5457 (clobber (match_dup 4))]
5460 rtx insn, div_equal, mod_equal, equal;
5462 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5463 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5464 equal = gen_rtx_IOR (TImode,
5465 gen_rtx_ASHIFT (TImode,
5466 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5468 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5470 operands[4] = gen_reg_rtx(TImode);
5471 emit_clobber (operands[4]);
5472 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5473 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5475 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5476 set_unique_reg_note (insn, REG_EQUAL, equal);
5478 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5479 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5481 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5482 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5487 (define_insn "udivmodtidi3"
5488 [(set (match_operand:TI 0 "register_operand" "=d,d")
5493 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5495 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5499 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5504 [(set_attr "op_type" "RRE,RXY")
5505 (set_attr "type" "idiv")])
5508 ; divmodsi4 instruction pattern(s).
5511 (define_expand "divmodsi4"
5512 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5513 (div:SI (match_operand:SI 1 "general_operand" "")
5514 (match_operand:SI 2 "nonimmediate_operand" "")))
5515 (set (match_operand:SI 3 "general_operand" "")
5516 (mod:SI (match_dup 1) (match_dup 2)))])
5517 (clobber (match_dup 4))]
5520 rtx insn, div_equal, mod_equal, equal;
5522 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5523 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5524 equal = gen_rtx_IOR (DImode,
5525 gen_rtx_ASHIFT (DImode,
5526 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5528 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5530 operands[4] = gen_reg_rtx(DImode);
5531 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5533 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5534 set_unique_reg_note (insn, REG_EQUAL, equal);
5536 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5537 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5539 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5540 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5545 (define_insn "divmoddisi3"
5546 [(set (match_operand:DI 0 "register_operand" "=d,d")
5551 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5553 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5557 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5562 [(set_attr "op_type" "RR,RX")
5563 (set_attr "type" "idiv")])
5566 ; udivsi3 and umodsi3 instruction pattern(s).
5569 (define_expand "udivmodsi4"
5570 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5571 (udiv:SI (match_operand:SI 1 "general_operand" "")
5572 (match_operand:SI 2 "nonimmediate_operand" "")))
5573 (set (match_operand:SI 3 "general_operand" "")
5574 (umod:SI (match_dup 1) (match_dup 2)))])
5575 (clobber (match_dup 4))]
5576 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5578 rtx insn, div_equal, mod_equal, equal;
5580 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5581 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5582 equal = gen_rtx_IOR (DImode,
5583 gen_rtx_ASHIFT (DImode,
5584 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5586 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5588 operands[4] = gen_reg_rtx(DImode);
5589 emit_clobber (operands[4]);
5590 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5591 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5593 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5594 set_unique_reg_note (insn, REG_EQUAL, equal);
5596 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5597 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5599 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5600 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5605 (define_insn "udivmoddisi3"
5606 [(set (match_operand:DI 0 "register_operand" "=d,d")
5611 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5613 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5617 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5618 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5622 [(set_attr "op_type" "RRE,RXY")
5623 (set_attr "type" "idiv")])
5625 (define_expand "udivsi3"
5626 [(set (match_operand:SI 0 "register_operand" "=d")
5627 (udiv:SI (match_operand:SI 1 "general_operand" "")
5628 (match_operand:SI 2 "general_operand" "")))
5629 (clobber (match_dup 3))]
5630 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5632 rtx insn, udiv_equal, umod_equal, equal;
5634 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5635 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5636 equal = gen_rtx_IOR (DImode,
5637 gen_rtx_ASHIFT (DImode,
5638 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5640 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5642 operands[3] = gen_reg_rtx (DImode);
5644 if (CONSTANT_P (operands[2]))
5646 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5648 rtx label1 = gen_label_rtx ();
5650 operands[1] = make_safe_from (operands[1], operands[0]);
5651 emit_move_insn (operands[0], const0_rtx);
5652 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5654 emit_move_insn (operands[0], const1_rtx);
5655 emit_label (label1);
5659 operands[2] = force_reg (SImode, operands[2]);
5660 operands[2] = make_safe_from (operands[2], operands[0]);
5662 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5663 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5665 set_unique_reg_note (insn, REG_EQUAL, equal);
5667 insn = emit_move_insn (operands[0],
5668 gen_lowpart (SImode, operands[3]));
5669 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5674 rtx label1 = gen_label_rtx ();
5675 rtx label2 = gen_label_rtx ();
5676 rtx label3 = gen_label_rtx ();
5678 operands[1] = force_reg (SImode, operands[1]);
5679 operands[1] = make_safe_from (operands[1], operands[0]);
5680 operands[2] = force_reg (SImode, operands[2]);
5681 operands[2] = make_safe_from (operands[2], operands[0]);
5683 emit_move_insn (operands[0], const0_rtx);
5684 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5686 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5688 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5690 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5691 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5693 set_unique_reg_note (insn, REG_EQUAL, equal);
5695 insn = emit_move_insn (operands[0],
5696 gen_lowpart (SImode, operands[3]));
5697 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5700 emit_label (label1);
5701 emit_move_insn (operands[0], operands[1]);
5703 emit_label (label2);
5704 emit_move_insn (operands[0], const1_rtx);
5705 emit_label (label3);
5707 emit_move_insn (operands[0], operands[0]);
5711 (define_expand "umodsi3"
5712 [(set (match_operand:SI 0 "register_operand" "=d")
5713 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5714 (match_operand:SI 2 "nonimmediate_operand" "")))
5715 (clobber (match_dup 3))]
5716 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5718 rtx insn, udiv_equal, umod_equal, equal;
5720 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5721 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5722 equal = gen_rtx_IOR (DImode,
5723 gen_rtx_ASHIFT (DImode,
5724 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5726 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5728 operands[3] = gen_reg_rtx (DImode);
5730 if (CONSTANT_P (operands[2]))
5732 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5734 rtx label1 = gen_label_rtx ();
5736 operands[1] = make_safe_from (operands[1], operands[0]);
5737 emit_move_insn (operands[0], operands[1]);
5738 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5740 emit_insn (gen_abssi2 (operands[0], operands[2]));
5741 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5742 emit_label (label1);
5746 operands[2] = force_reg (SImode, operands[2]);
5747 operands[2] = make_safe_from (operands[2], operands[0]);
5749 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5750 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5752 set_unique_reg_note (insn, REG_EQUAL, equal);
5754 insn = emit_move_insn (operands[0],
5755 gen_highpart (SImode, operands[3]));
5756 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5761 rtx label1 = gen_label_rtx ();
5762 rtx label2 = gen_label_rtx ();
5763 rtx label3 = gen_label_rtx ();
5765 operands[1] = force_reg (SImode, operands[1]);
5766 operands[1] = make_safe_from (operands[1], operands[0]);
5767 operands[2] = force_reg (SImode, operands[2]);
5768 operands[2] = make_safe_from (operands[2], operands[0]);
5770 emit_move_insn(operands[0], operands[1]);
5771 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5773 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5775 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5777 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5778 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5780 set_unique_reg_note (insn, REG_EQUAL, equal);
5782 insn = emit_move_insn (operands[0],
5783 gen_highpart (SImode, operands[3]));
5784 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5787 emit_label (label1);
5788 emit_move_insn (operands[0], const0_rtx);
5790 emit_label (label2);
5791 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5792 emit_label (label3);
5798 ; div(df|sf)3 instruction pattern(s).
5801 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5802 (define_insn "div<mode>3"
5803 [(set (match_operand:FP 0 "register_operand" "=f,f")
5804 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5805 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5808 d<xde><bt>r\t%0,<op1>%2
5810 [(set_attr "op_type" "<RRer>,RXE")
5811 (set_attr "type" "fdiv<mode>")])
5815 ;;- And instructions.
5818 (define_expand "and<mode>3"
5819 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5820 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5821 (match_operand:INT 2 "general_operand" "")))
5822 (clobber (reg:CC CC_REGNUM))]
5824 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5827 ; anddi3 instruction pattern(s).
5830 (define_insn "*anddi3_cc"
5831 [(set (reg CC_REGNUM)
5832 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5833 (match_operand:DI 2 "general_operand" "d,RT"))
5835 (set (match_operand:DI 0 "register_operand" "=d,d")
5836 (and:DI (match_dup 1) (match_dup 2)))]
5837 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5841 [(set_attr "op_type" "RRE,RXY")
5842 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5844 (define_insn "*anddi3_cconly"
5845 [(set (reg CC_REGNUM)
5846 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5847 (match_operand:DI 2 "general_operand" "d,RT"))
5849 (clobber (match_scratch:DI 0 "=d,d"))]
5850 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
5851 /* Do not steal TM patterns. */
5852 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5856 [(set_attr "op_type" "RRE,RXY")
5857 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5859 (define_insn "*anddi3"
5860 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5861 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5862 "%d,o,0,0,0,0,0,0,0,0,0,0")
5863 (match_operand:DI 2 "general_operand"
5864 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5865 (clobber (reg:CC CC_REGNUM))]
5866 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5880 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5881 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5882 (set_attr "z10prop" "*,
5896 [(set (match_operand:DI 0 "s_operand" "")
5897 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5898 (clobber (reg:CC CC_REGNUM))]
5901 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5902 (clobber (reg:CC CC_REGNUM))])]
5903 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5907 ; andsi3 instruction pattern(s).
5910 (define_insn "*andsi3_cc"
5911 [(set (reg CC_REGNUM)
5912 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5913 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5915 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5916 (and:SI (match_dup 1) (match_dup 2)))]
5917 "s390_match_ccmode(insn, CCTmode)"
5923 [(set_attr "op_type" "RIL,RR,RX,RXY")
5924 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5926 (define_insn "*andsi3_cconly"
5927 [(set (reg CC_REGNUM)
5928 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5929 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5931 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5932 "s390_match_ccmode(insn, CCTmode)
5933 /* Do not steal TM patterns. */
5934 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5940 [(set_attr "op_type" "RIL,RR,RX,RXY")
5941 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5943 (define_insn "*andsi3_zarch"
5944 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5945 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5946 "%d,o,0,0,0,0,0,0,0,0")
5947 (match_operand:SI 2 "general_operand"
5948 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5949 (clobber (reg:CC CC_REGNUM))]
5950 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5962 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5963 (set_attr "z10prop" "*,
5974 (define_insn "*andsi3_esa"
5975 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5976 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5977 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5978 (clobber (reg:CC CC_REGNUM))]
5979 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5985 [(set_attr "op_type" "RR,RX,SI,SS")
5986 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5990 [(set (match_operand:SI 0 "s_operand" "")
5991 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5992 (clobber (reg:CC CC_REGNUM))]
5995 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5996 (clobber (reg:CC CC_REGNUM))])]
5997 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6000 ; andhi3 instruction pattern(s).
6003 (define_insn "*andhi3_zarch"
6004 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6005 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6006 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
6007 (clobber (reg:CC CC_REGNUM))]
6008 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6014 [(set_attr "op_type" "RR,RI,SI,SS")
6015 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
6018 (define_insn "*andhi3_esa"
6019 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6020 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6021 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6022 (clobber (reg:CC CC_REGNUM))]
6023 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6028 [(set_attr "op_type" "RR,SI,SS")
6029 (set_attr "z10prop" "z10_super_E1,*,*")
6033 [(set (match_operand:HI 0 "s_operand" "")
6034 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6035 (clobber (reg:CC CC_REGNUM))]
6038 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6039 (clobber (reg:CC CC_REGNUM))])]
6040 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6043 ; andqi3 instruction pattern(s).
6046 (define_insn "*andqi3_zarch"
6047 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6048 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6049 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6050 (clobber (reg:CC CC_REGNUM))]
6051 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6058 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6059 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6061 (define_insn "*andqi3_esa"
6062 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6063 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6064 (match_operand:QI 2 "general_operand" "d,n,Q")))
6065 (clobber (reg:CC CC_REGNUM))]
6066 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6071 [(set_attr "op_type" "RR,SI,SS")
6072 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6075 ; Block and (NC) patterns.
6079 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6080 (and:BLK (match_dup 0)
6081 (match_operand:BLK 1 "memory_operand" "Q")))
6082 (use (match_operand 2 "const_int_operand" "n"))
6083 (clobber (reg:CC CC_REGNUM))]
6084 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6085 "nc\t%O0(%2,%R0),%S1"
6086 [(set_attr "op_type" "SS")])
6089 [(set (match_operand 0 "memory_operand" "")
6091 (match_operand 1 "memory_operand" "")))
6092 (clobber (reg:CC CC_REGNUM))]
6094 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6095 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6097 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6099 (clobber (reg:CC CC_REGNUM))])]
6101 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6102 operands[0] = adjust_address (operands[0], BLKmode, 0);
6103 operands[1] = adjust_address (operands[1], BLKmode, 0);
6108 [(set (match_operand:BLK 0 "memory_operand" "")
6109 (and:BLK (match_dup 0)
6110 (match_operand:BLK 1 "memory_operand" "")))
6111 (use (match_operand 2 "const_int_operand" ""))
6112 (clobber (reg:CC CC_REGNUM))])
6114 [(set (match_operand:BLK 3 "memory_operand" "")
6115 (and:BLK (match_dup 3)
6116 (match_operand:BLK 4 "memory_operand" "")))
6117 (use (match_operand 5 "const_int_operand" ""))
6118 (clobber (reg:CC CC_REGNUM))])]
6119 "s390_offset_p (operands[0], operands[3], operands[2])
6120 && s390_offset_p (operands[1], operands[4], operands[2])
6121 && !s390_overlap_p (operands[0], operands[1],
6122 INTVAL (operands[2]) + INTVAL (operands[5]))
6123 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6125 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6127 (clobber (reg:CC CC_REGNUM))])]
6128 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6129 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6130 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6134 ;;- Bit set (inclusive or) instructions.
6137 (define_expand "ior<mode>3"
6138 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6139 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6140 (match_operand:INT 2 "general_operand" "")))
6141 (clobber (reg:CC CC_REGNUM))]
6143 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6146 ; iordi3 instruction pattern(s).
6149 (define_insn "*iordi3_cc"
6150 [(set (reg CC_REGNUM)
6151 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6152 (match_operand:DI 2 "general_operand" "d,RT"))
6154 (set (match_operand:DI 0 "register_operand" "=d,d")
6155 (ior:DI (match_dup 1) (match_dup 2)))]
6156 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6160 [(set_attr "op_type" "RRE,RXY")
6161 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6163 (define_insn "*iordi3_cconly"
6164 [(set (reg CC_REGNUM)
6165 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6166 (match_operand:DI 2 "general_operand" "d,RT"))
6168 (clobber (match_scratch:DI 0 "=d,d"))]
6169 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6173 [(set_attr "op_type" "RRE,RXY")
6174 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6176 (define_insn "*iordi3"
6177 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6178 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6179 (match_operand:DI 2 "general_operand"
6180 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6181 (clobber (reg:CC CC_REGNUM))]
6182 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6194 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6195 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6196 (set_attr "z10prop" "z10_super_E1,
6208 [(set (match_operand:DI 0 "s_operand" "")
6209 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6210 (clobber (reg:CC CC_REGNUM))]
6213 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6214 (clobber (reg:CC CC_REGNUM))])]
6215 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6218 ; iorsi3 instruction pattern(s).
6221 (define_insn "*iorsi3_cc"
6222 [(set (reg CC_REGNUM)
6223 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6224 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6226 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6227 (ior:SI (match_dup 1) (match_dup 2)))]
6228 "s390_match_ccmode(insn, CCTmode)"
6234 [(set_attr "op_type" "RIL,RR,RX,RXY")
6235 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6237 (define_insn "*iorsi3_cconly"
6238 [(set (reg CC_REGNUM)
6239 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6240 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6242 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6243 "s390_match_ccmode(insn, CCTmode)"
6249 [(set_attr "op_type" "RIL,RR,RX,RXY")
6250 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6252 (define_insn "*iorsi3_zarch"
6253 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6254 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6255 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6256 (clobber (reg:CC CC_REGNUM))]
6257 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6267 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6268 (set_attr "z10prop" "z10_super_E1,
6277 (define_insn "*iorsi3_esa"
6278 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6279 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6280 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6281 (clobber (reg:CC CC_REGNUM))]
6282 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6288 [(set_attr "op_type" "RR,RX,SI,SS")
6289 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6292 [(set (match_operand:SI 0 "s_operand" "")
6293 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6294 (clobber (reg:CC CC_REGNUM))]
6297 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6298 (clobber (reg:CC CC_REGNUM))])]
6299 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6302 ; iorhi3 instruction pattern(s).
6305 (define_insn "*iorhi3_zarch"
6306 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6307 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6308 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6309 (clobber (reg:CC CC_REGNUM))]
6310 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6316 [(set_attr "op_type" "RR,RI,SI,SS")
6317 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6319 (define_insn "*iorhi3_esa"
6320 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6321 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6322 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6323 (clobber (reg:CC CC_REGNUM))]
6324 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6329 [(set_attr "op_type" "RR,SI,SS")
6330 (set_attr "z10prop" "z10_super_E1,*,*")])
6333 [(set (match_operand:HI 0 "s_operand" "")
6334 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6335 (clobber (reg:CC CC_REGNUM))]
6338 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6339 (clobber (reg:CC CC_REGNUM))])]
6340 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6343 ; iorqi3 instruction pattern(s).
6346 (define_insn "*iorqi3_zarch"
6347 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6348 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6349 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6350 (clobber (reg:CC CC_REGNUM))]
6351 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6358 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6359 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6361 (define_insn "*iorqi3_esa"
6362 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6363 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6364 (match_operand:QI 2 "general_operand" "d,n,Q")))
6365 (clobber (reg:CC CC_REGNUM))]
6366 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6371 [(set_attr "op_type" "RR,SI,SS")
6372 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6375 ; Block inclusive or (OC) patterns.
6379 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6380 (ior:BLK (match_dup 0)
6381 (match_operand:BLK 1 "memory_operand" "Q")))
6382 (use (match_operand 2 "const_int_operand" "n"))
6383 (clobber (reg:CC CC_REGNUM))]
6384 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6385 "oc\t%O0(%2,%R0),%S1"
6386 [(set_attr "op_type" "SS")])
6389 [(set (match_operand 0 "memory_operand" "")
6391 (match_operand 1 "memory_operand" "")))
6392 (clobber (reg:CC CC_REGNUM))]
6394 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6395 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6397 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6399 (clobber (reg:CC CC_REGNUM))])]
6401 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6402 operands[0] = adjust_address (operands[0], BLKmode, 0);
6403 operands[1] = adjust_address (operands[1], BLKmode, 0);
6408 [(set (match_operand:BLK 0 "memory_operand" "")
6409 (ior:BLK (match_dup 0)
6410 (match_operand:BLK 1 "memory_operand" "")))
6411 (use (match_operand 2 "const_int_operand" ""))
6412 (clobber (reg:CC CC_REGNUM))])
6414 [(set (match_operand:BLK 3 "memory_operand" "")
6415 (ior:BLK (match_dup 3)
6416 (match_operand:BLK 4 "memory_operand" "")))
6417 (use (match_operand 5 "const_int_operand" ""))
6418 (clobber (reg:CC CC_REGNUM))])]
6419 "s390_offset_p (operands[0], operands[3], operands[2])
6420 && s390_offset_p (operands[1], operands[4], operands[2])
6421 && !s390_overlap_p (operands[0], operands[1],
6422 INTVAL (operands[2]) + INTVAL (operands[5]))
6423 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6425 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6427 (clobber (reg:CC CC_REGNUM))])]
6428 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6429 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6430 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6434 ;;- Xor instructions.
6437 (define_expand "xor<mode>3"
6438 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6439 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6440 (match_operand:INT 2 "general_operand" "")))
6441 (clobber (reg:CC CC_REGNUM))]
6443 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6446 ; xordi3 instruction pattern(s).
6449 (define_insn "*xordi3_cc"
6450 [(set (reg CC_REGNUM)
6451 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6452 (match_operand:DI 2 "general_operand" "d,RT"))
6454 (set (match_operand:DI 0 "register_operand" "=d,d")
6455 (xor:DI (match_dup 1) (match_dup 2)))]
6456 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6460 [(set_attr "op_type" "RRE,RXY")
6461 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6463 (define_insn "*xordi3_cconly"
6464 [(set (reg CC_REGNUM)
6465 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6466 (match_operand:DI 2 "general_operand" "d,RT"))
6468 (clobber (match_scratch:DI 0 "=d,d"))]
6469 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6473 [(set_attr "op_type" "RRE,RXY")
6474 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6476 (define_insn "*xordi3"
6477 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6478 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6479 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6480 (clobber (reg:CC CC_REGNUM))]
6481 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6489 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6490 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6491 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6494 [(set (match_operand:DI 0 "s_operand" "")
6495 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6496 (clobber (reg:CC CC_REGNUM))]
6499 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6500 (clobber (reg:CC CC_REGNUM))])]
6501 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6504 ; xorsi3 instruction pattern(s).
6507 (define_insn "*xorsi3_cc"
6508 [(set (reg CC_REGNUM)
6509 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6510 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6512 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6513 (xor:SI (match_dup 1) (match_dup 2)))]
6514 "s390_match_ccmode(insn, CCTmode)"
6520 [(set_attr "op_type" "RIL,RR,RX,RXY")
6521 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6523 (define_insn "*xorsi3_cconly"
6524 [(set (reg CC_REGNUM)
6525 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6526 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6528 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6529 "s390_match_ccmode(insn, CCTmode)"
6535 [(set_attr "op_type" "RIL,RR,RX,RXY")
6536 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6538 (define_insn "*xorsi3"
6539 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6540 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6541 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6542 (clobber (reg:CC CC_REGNUM))]
6543 "s390_logical_operator_ok_p (operands)"
6551 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6552 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6555 [(set (match_operand:SI 0 "s_operand" "")
6556 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6557 (clobber (reg:CC CC_REGNUM))]
6560 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6561 (clobber (reg:CC CC_REGNUM))])]
6562 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6565 ; xorhi3 instruction pattern(s).
6568 (define_insn "*xorhi3"
6569 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6570 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6571 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6572 (clobber (reg:CC CC_REGNUM))]
6573 "s390_logical_operator_ok_p (operands)"
6579 [(set_attr "op_type" "RIL,RR,SI,SS")
6580 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6583 [(set (match_operand:HI 0 "s_operand" "")
6584 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6585 (clobber (reg:CC CC_REGNUM))]
6588 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6589 (clobber (reg:CC CC_REGNUM))])]
6590 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6593 ; xorqi3 instruction pattern(s).
6596 (define_insn "*xorqi3"
6597 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6598 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6599 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6600 (clobber (reg:CC CC_REGNUM))]
6601 "s390_logical_operator_ok_p (operands)"
6608 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6609 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6613 ; Block exclusive or (XC) patterns.
6617 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6618 (xor:BLK (match_dup 0)
6619 (match_operand:BLK 1 "memory_operand" "Q")))
6620 (use (match_operand 2 "const_int_operand" "n"))
6621 (clobber (reg:CC CC_REGNUM))]
6622 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6623 "xc\t%O0(%2,%R0),%S1"
6624 [(set_attr "op_type" "SS")])
6627 [(set (match_operand 0 "memory_operand" "")
6629 (match_operand 1 "memory_operand" "")))
6630 (clobber (reg:CC CC_REGNUM))]
6632 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6633 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6635 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6637 (clobber (reg:CC CC_REGNUM))])]
6639 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6640 operands[0] = adjust_address (operands[0], BLKmode, 0);
6641 operands[1] = adjust_address (operands[1], BLKmode, 0);
6646 [(set (match_operand:BLK 0 "memory_operand" "")
6647 (xor:BLK (match_dup 0)
6648 (match_operand:BLK 1 "memory_operand" "")))
6649 (use (match_operand 2 "const_int_operand" ""))
6650 (clobber (reg:CC CC_REGNUM))])
6652 [(set (match_operand:BLK 3 "memory_operand" "")
6653 (xor:BLK (match_dup 3)
6654 (match_operand:BLK 4 "memory_operand" "")))
6655 (use (match_operand 5 "const_int_operand" ""))
6656 (clobber (reg:CC CC_REGNUM))])]
6657 "s390_offset_p (operands[0], operands[3], operands[2])
6658 && s390_offset_p (operands[1], operands[4], operands[2])
6659 && !s390_overlap_p (operands[0], operands[1],
6660 INTVAL (operands[2]) + INTVAL (operands[5]))
6661 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6663 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6665 (clobber (reg:CC CC_REGNUM))])]
6666 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6667 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6668 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6671 ; Block xor (XC) patterns with src == dest.
6674 (define_insn "*xc_zero"
6675 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6677 (use (match_operand 1 "const_int_operand" "n"))
6678 (clobber (reg:CC CC_REGNUM))]
6679 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6680 "xc\t%O0(%1,%R0),%S0"
6681 [(set_attr "op_type" "SS")])
6685 [(set (match_operand:BLK 0 "memory_operand" "")
6687 (use (match_operand 1 "const_int_operand" ""))
6688 (clobber (reg:CC CC_REGNUM))])
6690 [(set (match_operand:BLK 2 "memory_operand" "")
6692 (use (match_operand 3 "const_int_operand" ""))
6693 (clobber (reg:CC CC_REGNUM))])]
6694 "s390_offset_p (operands[0], operands[2], operands[1])
6695 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6697 [(set (match_dup 4) (const_int 0))
6699 (clobber (reg:CC CC_REGNUM))])]
6700 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6701 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6705 ;;- Negate instructions.
6709 ; neg(di|si)2 instruction pattern(s).
6712 (define_expand "neg<mode>2"
6714 [(set (match_operand:DSI 0 "register_operand" "=d")
6715 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6716 (clobber (reg:CC CC_REGNUM))])]
6720 (define_insn "*negdi2_sign_cc"
6721 [(set (reg CC_REGNUM)
6722 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6723 (match_operand:SI 1 "register_operand" "d") 0)
6724 (const_int 32)) (const_int 32)))
6726 (set (match_operand:DI 0 "register_operand" "=d")
6727 (neg:DI (sign_extend:DI (match_dup 1))))]
6728 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6730 [(set_attr "op_type" "RRE")
6731 (set_attr "z10prop" "z10_c")])
6733 (define_insn "*negdi2_sign"
6734 [(set (match_operand:DI 0 "register_operand" "=d")
6735 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6736 (clobber (reg:CC CC_REGNUM))]
6739 [(set_attr "op_type" "RRE")
6740 (set_attr "z10prop" "z10_c")])
6743 (define_insn "*neg<mode>2_cc"
6744 [(set (reg CC_REGNUM)
6745 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6747 (set (match_operand:GPR 0 "register_operand" "=d")
6748 (neg:GPR (match_dup 1)))]
6749 "s390_match_ccmode (insn, CCAmode)"
6751 [(set_attr "op_type" "RR<E>")
6752 (set_attr "z10prop" "z10_super_c_E1")])
6755 (define_insn "*neg<mode>2_cconly"
6756 [(set (reg CC_REGNUM)
6757 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6759 (clobber (match_scratch:GPR 0 "=d"))]
6760 "s390_match_ccmode (insn, CCAmode)"
6762 [(set_attr "op_type" "RR<E>")
6763 (set_attr "z10prop" "z10_super_c_E1")])
6766 (define_insn "*neg<mode>2"
6767 [(set (match_operand:GPR 0 "register_operand" "=d")
6768 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6769 (clobber (reg:CC CC_REGNUM))]
6772 [(set_attr "op_type" "RR<E>")
6773 (set_attr "z10prop" "z10_super_c_E1")])
6775 (define_insn_and_split "*negdi2_31"
6776 [(set (match_operand:DI 0 "register_operand" "=d")
6777 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6778 (clobber (reg:CC CC_REGNUM))]
6781 "&& reload_completed"
6783 [(set (match_dup 2) (neg:SI (match_dup 3)))
6784 (clobber (reg:CC CC_REGNUM))])
6786 [(set (reg:CCAP CC_REGNUM)
6787 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6788 (set (match_dup 4) (neg:SI (match_dup 5)))])
6790 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6792 (label_ref (match_dup 6))))
6794 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6795 (clobber (reg:CC CC_REGNUM))])
6797 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6798 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6799 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6800 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6801 operands[6] = gen_label_rtx ();")
6804 ; neg(df|sf)2 instruction pattern(s).
6807 (define_expand "neg<mode>2"
6809 [(set (match_operand:BFP 0 "register_operand" "=f")
6810 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6811 (clobber (reg:CC CC_REGNUM))])]
6815 ; lcxbr, lcdbr, lcebr
6816 (define_insn "*neg<mode>2_cc"
6817 [(set (reg CC_REGNUM)
6818 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6819 (match_operand:BFP 2 "const0_operand" "")))
6820 (set (match_operand:BFP 0 "register_operand" "=f")
6821 (neg:BFP (match_dup 1)))]
6822 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6824 [(set_attr "op_type" "RRE")
6825 (set_attr "type" "fsimp<mode>")])
6827 ; lcxbr, lcdbr, lcebr
6828 (define_insn "*neg<mode>2_cconly"
6829 [(set (reg CC_REGNUM)
6830 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6831 (match_operand:BFP 2 "const0_operand" "")))
6832 (clobber (match_scratch:BFP 0 "=f"))]
6833 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6835 [(set_attr "op_type" "RRE")
6836 (set_attr "type" "fsimp<mode>")])
6839 (define_insn "*neg<mode>2_nocc"
6840 [(set (match_operand:FP 0 "register_operand" "=f")
6841 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6844 [(set_attr "op_type" "RRE")
6845 (set_attr "type" "fsimp<mode>")])
6847 ; lcxbr, lcdbr, lcebr
6848 (define_insn "*neg<mode>2"
6849 [(set (match_operand:BFP 0 "register_operand" "=f")
6850 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6851 (clobber (reg:CC CC_REGNUM))]
6854 [(set_attr "op_type" "RRE")
6855 (set_attr "type" "fsimp<mode>")])
6859 ;;- Absolute value instructions.
6863 ; abs(di|si)2 instruction pattern(s).
6866 (define_insn "*absdi2_sign_cc"
6867 [(set (reg CC_REGNUM)
6868 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6869 (match_operand:SI 1 "register_operand" "d") 0)
6870 (const_int 32)) (const_int 32)))
6872 (set (match_operand:DI 0 "register_operand" "=d")
6873 (abs:DI (sign_extend:DI (match_dup 1))))]
6874 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6876 [(set_attr "op_type" "RRE")
6877 (set_attr "z10prop" "z10_c")])
6879 (define_insn "*absdi2_sign"
6880 [(set (match_operand:DI 0 "register_operand" "=d")
6881 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6882 (clobber (reg:CC CC_REGNUM))]
6885 [(set_attr "op_type" "RRE")
6886 (set_attr "z10prop" "z10_c")])
6889 (define_insn "*abs<mode>2_cc"
6890 [(set (reg CC_REGNUM)
6891 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6893 (set (match_operand:GPR 0 "register_operand" "=d")
6894 (abs:GPR (match_dup 1)))]
6895 "s390_match_ccmode (insn, CCAmode)"
6897 [(set_attr "op_type" "RR<E>")
6898 (set_attr "z10prop" "z10_c")])
6901 (define_insn "*abs<mode>2_cconly"
6902 [(set (reg CC_REGNUM)
6903 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6905 (clobber (match_scratch:GPR 0 "=d"))]
6906 "s390_match_ccmode (insn, CCAmode)"
6908 [(set_attr "op_type" "RR<E>")
6909 (set_attr "z10prop" "z10_c")])
6912 (define_insn "abs<mode>2"
6913 [(set (match_operand:GPR 0 "register_operand" "=d")
6914 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6915 (clobber (reg:CC CC_REGNUM))]
6918 [(set_attr "op_type" "RR<E>")
6919 (set_attr "z10prop" "z10_c")])
6922 ; abs(df|sf)2 instruction pattern(s).
6925 (define_expand "abs<mode>2"
6927 [(set (match_operand:BFP 0 "register_operand" "=f")
6928 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6929 (clobber (reg:CC CC_REGNUM))])]
6933 ; lpxbr, lpdbr, lpebr
6934 (define_insn "*abs<mode>2_cc"
6935 [(set (reg CC_REGNUM)
6936 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6937 (match_operand:BFP 2 "const0_operand" "")))
6938 (set (match_operand:BFP 0 "register_operand" "=f")
6939 (abs:BFP (match_dup 1)))]
6940 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6942 [(set_attr "op_type" "RRE")
6943 (set_attr "type" "fsimp<mode>")])
6945 ; lpxbr, lpdbr, lpebr
6946 (define_insn "*abs<mode>2_cconly"
6947 [(set (reg CC_REGNUM)
6948 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6949 (match_operand:BFP 2 "const0_operand" "")))
6950 (clobber (match_scratch:BFP 0 "=f"))]
6951 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6953 [(set_attr "op_type" "RRE")
6954 (set_attr "type" "fsimp<mode>")])
6957 (define_insn "*abs<mode>2_nocc"
6958 [(set (match_operand:FP 0 "register_operand" "=f")
6959 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6962 [(set_attr "op_type" "RRE")
6963 (set_attr "type" "fsimp<mode>")])
6965 ; lpxbr, lpdbr, lpebr
6966 (define_insn "*abs<mode>2"
6967 [(set (match_operand:BFP 0 "register_operand" "=f")
6968 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6969 (clobber (reg:CC CC_REGNUM))]
6972 [(set_attr "op_type" "RRE")
6973 (set_attr "type" "fsimp<mode>")])
6977 ;;- Negated absolute value instructions
6984 (define_insn "*negabsdi2_sign_cc"
6985 [(set (reg CC_REGNUM)
6986 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6987 (match_operand:SI 1 "register_operand" "d") 0)
6988 (const_int 32)) (const_int 32))))
6990 (set (match_operand:DI 0 "register_operand" "=d")
6991 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6992 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6994 [(set_attr "op_type" "RRE")
6995 (set_attr "z10prop" "z10_c")])
6997 (define_insn "*negabsdi2_sign"
6998 [(set (match_operand:DI 0 "register_operand" "=d")
6999 (neg:DI (abs:DI (sign_extend:DI
7000 (match_operand:SI 1 "register_operand" "d")))))
7001 (clobber (reg:CC CC_REGNUM))]
7004 [(set_attr "op_type" "RRE")
7005 (set_attr "z10prop" "z10_c")])
7008 (define_insn "*negabs<mode>2_cc"
7009 [(set (reg CC_REGNUM)
7010 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7012 (set (match_operand:GPR 0 "register_operand" "=d")
7013 (neg:GPR (abs:GPR (match_dup 1))))]
7014 "s390_match_ccmode (insn, CCAmode)"
7016 [(set_attr "op_type" "RR<E>")
7017 (set_attr "z10prop" "z10_c")])
7020 (define_insn "*negabs<mode>2_cconly"
7021 [(set (reg CC_REGNUM)
7022 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7024 (clobber (match_scratch:GPR 0 "=d"))]
7025 "s390_match_ccmode (insn, CCAmode)"
7027 [(set_attr "op_type" "RR<E>")
7028 (set_attr "z10prop" "z10_c")])
7031 (define_insn "*negabs<mode>2"
7032 [(set (match_operand:GPR 0 "register_operand" "=d")
7033 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7034 (clobber (reg:CC CC_REGNUM))]
7037 [(set_attr "op_type" "RR<E>")
7038 (set_attr "z10prop" "z10_c")])
7044 ; lnxbr, lndbr, lnebr
7045 (define_insn "*negabs<mode>2_cc"
7046 [(set (reg CC_REGNUM)
7047 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7048 (match_operand:BFP 2 "const0_operand" "")))
7049 (set (match_operand:BFP 0 "register_operand" "=f")
7050 (neg:BFP (abs:BFP (match_dup 1))))]
7051 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7053 [(set_attr "op_type" "RRE")
7054 (set_attr "type" "fsimp<mode>")])
7056 ; lnxbr, lndbr, lnebr
7057 (define_insn "*negabs<mode>2_cconly"
7058 [(set (reg CC_REGNUM)
7059 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7060 (match_operand:BFP 2 "const0_operand" "")))
7061 (clobber (match_scratch:BFP 0 "=f"))]
7062 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7064 [(set_attr "op_type" "RRE")
7065 (set_attr "type" "fsimp<mode>")])
7068 (define_insn "*negabs<mode>2_nocc"
7069 [(set (match_operand:FP 0 "register_operand" "=f")
7070 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7073 [(set_attr "op_type" "RRE")
7074 (set_attr "type" "fsimp<mode>")])
7076 ; lnxbr, lndbr, lnebr
7077 (define_insn "*negabs<mode>2"
7078 [(set (match_operand:BFP 0 "register_operand" "=f")
7079 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7080 (clobber (reg:CC CC_REGNUM))]
7083 [(set_attr "op_type" "RRE")
7084 (set_attr "type" "fsimp<mode>")])
7087 ;;- Square root instructions.
7091 ; sqrt(df|sf)2 instruction pattern(s).
7094 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7095 (define_insn "sqrt<mode>2"
7096 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7097 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7102 [(set_attr "op_type" "RRE,RXE")
7103 (set_attr "type" "fsqrt<mode>")])
7107 ;;- One complement instructions.
7111 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7114 (define_expand "one_cmpl<mode>2"
7116 [(set (match_operand:INT 0 "register_operand" "")
7117 (xor:INT (match_operand:INT 1 "register_operand" "")
7119 (clobber (reg:CC CC_REGNUM))])]
7125 ;; Find leftmost bit instructions.
7128 (define_expand "clzdi2"
7129 [(set (match_operand:DI 0 "register_operand" "=d")
7130 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7131 "TARGET_EXTIMM && TARGET_ZARCH"
7133 rtx insn, clz_equal;
7134 rtx wide_reg = gen_reg_rtx (TImode);
7135 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7137 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7139 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7141 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7142 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7147 (define_insn "clztidi2"
7148 [(set (match_operand:TI 0 "register_operand" "=d")
7152 (xor:DI (match_operand:DI 1 "register_operand" "d")
7153 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7154 (subreg:SI (clz:DI (match_dup 1)) 4))))
7157 (zero_extend:TI (clz:DI (match_dup 1)))))
7158 (clobber (reg:CC CC_REGNUM))]
7159 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7160 == (unsigned HOST_WIDE_INT) 1 << 63
7161 && TARGET_EXTIMM && TARGET_ZARCH"
7163 [(set_attr "op_type" "RRE")])
7167 ;;- Rotate instructions.
7171 ; rotl(di|si)3 instruction pattern(s).
7175 (define_insn "rotl<mode>3"
7176 [(set (match_operand:GPR 0 "register_operand" "=d")
7177 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7178 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7181 [(set_attr "op_type" "RSE")
7182 (set_attr "atype" "reg")
7183 (set_attr "z10prop" "z10_super_E1")])
7186 (define_insn "*rotl<mode>3_and"
7187 [(set (match_operand:GPR 0 "register_operand" "=d")
7188 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7189 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7190 (match_operand:SI 3 "const_int_operand" "n"))))]
7191 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7193 [(set_attr "op_type" "RSE")
7194 (set_attr "atype" "reg")
7195 (set_attr "z10prop" "z10_super_E1")])
7199 ;;- Shift instructions.
7203 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7206 (define_expand "<shift><mode>3"
7207 [(set (match_operand:DSI 0 "register_operand" "")
7208 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7209 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7214 (define_insn "*<shift>di3_31"
7215 [(set (match_operand:DI 0 "register_operand" "=d")
7216 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7217 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7220 [(set_attr "op_type" "RS")
7221 (set_attr "atype" "reg")])
7223 ; sll, srl, sllg, srlg
7224 (define_insn "*<shift><mode>3"
7225 [(set (match_operand:GPR 0 "register_operand" "=d")
7226 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7227 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7229 "s<lr>l<g>\t%0,<1>%Y2"
7230 [(set_attr "op_type" "RS<E>")
7231 (set_attr "atype" "reg")
7232 (set_attr "z10prop" "z10_super_E1")])
7235 (define_insn "*<shift>di3_31_and"
7236 [(set (match_operand:DI 0 "register_operand" "=d")
7237 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7238 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7239 (match_operand:SI 3 "const_int_operand" "n"))))]
7240 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7242 [(set_attr "op_type" "RS")
7243 (set_attr "atype" "reg")])
7245 ; sll, srl, sllg, srlg
7246 (define_insn "*<shift><mode>3_and"
7247 [(set (match_operand:GPR 0 "register_operand" "=d")
7248 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7249 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7250 (match_operand:SI 3 "const_int_operand" "n"))))]
7251 "(INTVAL (operands[3]) & 63) == 63"
7252 "s<lr>l<g>\t%0,<1>%Y2"
7253 [(set_attr "op_type" "RS<E>")
7254 (set_attr "atype" "reg")
7255 (set_attr "z10prop" "z10_super_E1")])
7258 ; ashr(di|si)3 instruction pattern(s).
7261 (define_expand "ashr<mode>3"
7263 [(set (match_operand:DSI 0 "register_operand" "")
7264 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7265 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7266 (clobber (reg:CC CC_REGNUM))])]
7270 (define_insn "*ashrdi3_cc_31"
7271 [(set (reg CC_REGNUM)
7272 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7273 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7275 (set (match_operand:DI 0 "register_operand" "=d")
7276 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7277 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7279 [(set_attr "op_type" "RS")
7280 (set_attr "atype" "reg")])
7282 (define_insn "*ashrdi3_cconly_31"
7283 [(set (reg CC_REGNUM)
7284 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7285 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7287 (clobber (match_scratch:DI 0 "=d"))]
7288 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7290 [(set_attr "op_type" "RS")
7291 (set_attr "atype" "reg")])
7293 (define_insn "*ashrdi3_31"
7294 [(set (match_operand:DI 0 "register_operand" "=d")
7295 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7296 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7297 (clobber (reg:CC CC_REGNUM))]
7300 [(set_attr "op_type" "RS")
7301 (set_attr "atype" "reg")])
7304 (define_insn "*ashr<mode>3_cc"
7305 [(set (reg CC_REGNUM)
7306 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7307 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7309 (set (match_operand:GPR 0 "register_operand" "=d")
7310 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7311 "s390_match_ccmode(insn, CCSmode)"
7313 [(set_attr "op_type" "RS<E>")
7314 (set_attr "atype" "reg")
7315 (set_attr "z10prop" "z10_super_E1")])
7318 (define_insn "*ashr<mode>3_cconly"
7319 [(set (reg CC_REGNUM)
7320 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7321 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7323 (clobber (match_scratch:GPR 0 "=d"))]
7324 "s390_match_ccmode(insn, CCSmode)"
7326 [(set_attr "op_type" "RS<E>")
7327 (set_attr "atype" "reg")
7328 (set_attr "z10prop" "z10_super_E1")])
7331 (define_insn "*ashr<mode>3"
7332 [(set (match_operand:GPR 0 "register_operand" "=d")
7333 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7334 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7335 (clobber (reg:CC CC_REGNUM))]
7338 [(set_attr "op_type" "RS<E>")
7339 (set_attr "atype" "reg")
7340 (set_attr "z10prop" "z10_super_E1")])
7343 ; shift pattern with implicit ANDs
7345 (define_insn "*ashrdi3_cc_31_and"
7346 [(set (reg CC_REGNUM)
7347 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7348 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7349 (match_operand:SI 3 "const_int_operand" "n")))
7351 (set (match_operand:DI 0 "register_operand" "=d")
7352 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7353 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7354 && (INTVAL (operands[3]) & 63) == 63"
7356 [(set_attr "op_type" "RS")
7357 (set_attr "atype" "reg")])
7359 (define_insn "*ashrdi3_cconly_31_and"
7360 [(set (reg CC_REGNUM)
7361 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7362 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7363 (match_operand:SI 3 "const_int_operand" "n")))
7365 (clobber (match_scratch:DI 0 "=d"))]
7366 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7367 && (INTVAL (operands[3]) & 63) == 63"
7369 [(set_attr "op_type" "RS")
7370 (set_attr "atype" "reg")])
7372 (define_insn "*ashrdi3_31_and"
7373 [(set (match_operand:DI 0 "register_operand" "=d")
7374 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7375 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7376 (match_operand:SI 3 "const_int_operand" "n"))))
7377 (clobber (reg:CC CC_REGNUM))]
7378 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7380 [(set_attr "op_type" "RS")
7381 (set_attr "atype" "reg")])
7384 (define_insn "*ashr<mode>3_cc_and"
7385 [(set (reg CC_REGNUM)
7386 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7387 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7388 (match_operand:SI 3 "const_int_operand" "n")))
7390 (set (match_operand:GPR 0 "register_operand" "=d")
7391 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7392 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7394 [(set_attr "op_type" "RS<E>")
7395 (set_attr "atype" "reg")
7396 (set_attr "z10prop" "z10_super_E1")])
7399 (define_insn "*ashr<mode>3_cconly_and"
7400 [(set (reg CC_REGNUM)
7401 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7402 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7403 (match_operand:SI 3 "const_int_operand" "n")))
7405 (clobber (match_scratch:GPR 0 "=d"))]
7406 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7408 [(set_attr "op_type" "RS<E>")
7409 (set_attr "atype" "reg")
7410 (set_attr "z10prop" "z10_super_E1")])
7413 (define_insn "*ashr<mode>3_and"
7414 [(set (match_operand:GPR 0 "register_operand" "=d")
7415 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7416 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7417 (match_operand:SI 3 "const_int_operand" "n"))))
7418 (clobber (reg:CC CC_REGNUM))]
7419 "(INTVAL (operands[3]) & 63) == 63"
7421 [(set_attr "op_type" "RS<E>")
7422 (set_attr "atype" "reg")
7423 (set_attr "z10prop" "z10_super_E1")])
7427 ;; Branch instruction patterns.
7430 (define_expand "cbranch<mode>4"
7432 (if_then_else (match_operator 0 "comparison_operator"
7433 [(match_operand:GPR 1 "register_operand" "")
7434 (match_operand:GPR 2 "general_operand" "")])
7435 (label_ref (match_operand 3 "" ""))
7438 "s390_emit_jump (operands[3],
7439 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7442 (define_expand "cbranch<mode>4"
7444 (if_then_else (match_operator 0 "comparison_operator"
7445 [(match_operand:FP 1 "register_operand" "")
7446 (match_operand:FP 2 "general_operand" "")])
7447 (label_ref (match_operand 3 "" ""))
7450 "s390_emit_jump (operands[3],
7451 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7454 (define_expand "cbranchcc4"
7456 (if_then_else (match_operator 0 "s390_eqne_operator"
7457 [(match_operand 1 "cc_reg_operand" "")
7458 (match_operand 2 "const0_operand" "")])
7459 (label_ref (match_operand 3 "" ""))
7462 "s390_emit_jump (operands[3],
7463 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7469 ;;- Conditional jump instructions.
7472 (define_insn "*cjump_64"
7475 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7476 (label_ref (match_operand 0 "" ""))
7480 if (get_attr_length (insn) == 4)
7483 return "jg%C1\t%l0";
7485 [(set_attr "op_type" "RI")
7486 (set_attr "type" "branch")
7487 (set (attr "length")
7488 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7489 (const_int 4) (const_int 6)))])
7491 (define_insn "*cjump_31"
7494 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7495 (label_ref (match_operand 0 "" ""))
7499 gcc_assert (get_attr_length (insn) == 4);
7502 [(set_attr "op_type" "RI")
7503 (set_attr "type" "branch")
7504 (set (attr "length")
7505 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7506 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7507 (const_int 4) (const_int 6))
7508 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7509 (const_int 4) (const_int 8))))])
7511 (define_insn "*cjump_long"
7514 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7515 (match_operand 0 "address_operand" "ZQZR")
7519 if (get_attr_op_type (insn) == OP_TYPE_RR)
7524 [(set (attr "op_type")
7525 (if_then_else (match_operand 0 "register_operand" "")
7526 (const_string "RR") (const_string "RX")))
7527 (set_attr "type" "branch")
7528 (set_attr "atype" "agen")])
7532 ;;- Negated conditional jump instructions.
7535 (define_insn "*icjump_64"
7538 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7540 (label_ref (match_operand 0 "" ""))))]
7543 if (get_attr_length (insn) == 4)
7546 return "jg%D1\t%l0";
7548 [(set_attr "op_type" "RI")
7549 (set_attr "type" "branch")
7550 (set (attr "length")
7551 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7552 (const_int 4) (const_int 6)))])
7554 (define_insn "*icjump_31"
7557 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7559 (label_ref (match_operand 0 "" ""))))]
7562 gcc_assert (get_attr_length (insn) == 4);
7565 [(set_attr "op_type" "RI")
7566 (set_attr "type" "branch")
7567 (set (attr "length")
7568 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7569 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7570 (const_int 4) (const_int 6))
7571 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7572 (const_int 4) (const_int 8))))])
7574 (define_insn "*icjump_long"
7577 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7579 (match_operand 0 "address_operand" "ZQZR")))]
7582 if (get_attr_op_type (insn) == OP_TYPE_RR)
7587 [(set (attr "op_type")
7588 (if_then_else (match_operand 0 "register_operand" "")
7589 (const_string "RR") (const_string "RX")))
7590 (set_attr "type" "branch")
7591 (set_attr "atype" "agen")])
7594 ;;- Trap instructions.
7598 [(trap_if (const_int 1) (const_int 0))]
7601 [(set_attr "op_type" "RI")
7602 (set_attr "type" "branch")])
7604 (define_expand "ctrap<mode>4"
7605 [(trap_if (match_operator 0 "comparison_operator"
7606 [(match_operand:GPR 1 "register_operand" "")
7607 (match_operand:GPR 2 "general_operand" "")])
7608 (match_operand 3 "const0_operand" ""))]
7611 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7612 operands[1], operands[2]);
7613 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7617 (define_expand "ctrap<mode>4"
7618 [(trap_if (match_operator 0 "comparison_operator"
7619 [(match_operand:FP 1 "register_operand" "")
7620 (match_operand:FP 2 "general_operand" "")])
7621 (match_operand 3 "const0_operand" ""))]
7624 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7625 operands[1], operands[2]);
7626 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7630 (define_insn "condtrap"
7631 [(trap_if (match_operator 0 "s390_comparison"
7632 [(match_operand 1 "cc_reg_operand" "c")
7637 [(set_attr "op_type" "RI")
7638 (set_attr "type" "branch")])
7640 ; crt, cgrt, cit, cgit
7641 (define_insn "*cmp_and_trap_signed_int<mode>"
7642 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7643 [(match_operand:GPR 1 "register_operand" "d,d")
7644 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7650 [(set_attr "op_type" "RRF,RIE")
7651 (set_attr "type" "branch")
7652 (set_attr "z10prop" "z10_super_c,z10_super")])
7654 ; clrt, clgrt, clfit, clgit
7655 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7656 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7657 [(match_operand:GPR 1 "register_operand" "d,d")
7658 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7663 cl<gf>it%C0\t%1,%x2"
7664 [(set_attr "op_type" "RRF,RIE")
7665 (set_attr "type" "branch")
7666 (set_attr "z10prop" "z10_super_c,z10_super")])
7669 ;;- Loop instructions.
7671 ;; This is all complicated by the fact that since this is a jump insn
7672 ;; we must handle our own output reloads.
7676 ; This splitter will be matched by combine and has to add the 2 moves
7677 ; necessary to load the compare and the increment values into a
7678 ; register pair as needed by brxle.
7680 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7683 (match_operator 6 "s390_brx_operator"
7684 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7685 (match_operand:GPR 2 "general_operand" ""))
7686 (match_operand:GPR 3 "register_operand" "")])
7687 (label_ref (match_operand 0 "" ""))
7689 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7690 (plus:GPR (match_dup 1) (match_dup 2)))
7691 (clobber (match_scratch:GPR 5 ""))]
7694 "!reload_completed && !reload_in_progress"
7695 [(set (match_dup 7) (match_dup 2)) ; the increment
7696 (set (match_dup 8) (match_dup 3)) ; the comparison value
7697 (parallel [(set (pc)
7700 [(plus:GPR (match_dup 1) (match_dup 7))
7702 (label_ref (match_dup 0))
7705 (plus:GPR (match_dup 1) (match_dup 7)))
7706 (clobber (match_dup 5))
7707 (clobber (reg:CC CC_REGNUM))])]
7709 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7710 operands[7] = gen_lowpart (<GPR:MODE>mode,
7711 gen_highpart (word_mode, dreg));
7712 operands[8] = gen_lowpart (<GPR:MODE>mode,
7713 gen_lowpart (word_mode, dreg));
7718 (define_insn_and_split "*brxg_64bit"
7721 (match_operator 5 "s390_brx_operator"
7722 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7723 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7724 (subreg:DI (match_dup 2) 8)])
7725 (label_ref (match_operand 0 "" ""))
7727 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7728 (plus:DI (match_dup 1)
7729 (subreg:DI (match_dup 2) 0)))
7730 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7731 (clobber (reg:CC CC_REGNUM))]
7734 if (which_alternative != 0)
7736 else if (get_attr_length (insn) == 6)
7737 return "brx%E5g\t%1,%2,%l0";
7739 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7741 "&& reload_completed
7742 && (!REG_P (operands[3])
7743 || !rtx_equal_p (operands[1], operands[3]))"
7744 [(set (match_dup 4) (match_dup 1))
7745 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7746 (clobber (reg:CC CC_REGNUM))])
7747 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7748 (set (match_dup 3) (match_dup 4))
7749 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7750 (label_ref (match_dup 0))
7753 [(set_attr "op_type" "RIE")
7754 (set_attr "type" "branch")
7755 (set (attr "length")
7756 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7757 (const_int 6) (const_int 16)))])
7761 (define_insn_and_split "*brx_64bit"
7764 (match_operator 5 "s390_brx_operator"
7765 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7766 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
7767 (subreg:SI (match_dup 2) 12)])
7768 (label_ref (match_operand 0 "" ""))
7770 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7771 (plus:SI (match_dup 1)
7772 (subreg:SI (match_dup 2) 4)))
7773 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7774 (clobber (reg:CC CC_REGNUM))]
7777 if (which_alternative != 0)
7779 else if (get_attr_length (insn) == 6)
7780 return "brx%C5\t%1,%2,%l0";
7782 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7784 "&& reload_completed
7785 && (!REG_P (operands[3])
7786 || !rtx_equal_p (operands[1], operands[3]))"
7787 [(set (match_dup 4) (match_dup 1))
7788 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
7789 (clobber (reg:CC CC_REGNUM))])
7790 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
7791 (set (match_dup 3) (match_dup 4))
7792 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7793 (label_ref (match_dup 0))
7796 [(set_attr "op_type" "RSI")
7797 (set_attr "type" "branch")
7798 (set (attr "length")
7799 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7800 (const_int 6) (const_int 14)))])
7804 (define_insn_and_split "*brx_31bit"
7807 (match_operator 5 "s390_brx_operator"
7808 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7809 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
7810 (subreg:SI (match_dup 2) 4)])
7811 (label_ref (match_operand 0 "" ""))
7813 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7814 (plus:SI (match_dup 1)
7815 (subreg:SI (match_dup 2) 0)))
7816 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7817 (clobber (reg:CC CC_REGNUM))]
7818 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7820 if (which_alternative != 0)
7822 else if (get_attr_length (insn) == 6)
7823 return "brx%C5\t%1,%2,%l0";
7825 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7827 "&& reload_completed
7828 && (!REG_P (operands[3])
7829 || !rtx_equal_p (operands[1], operands[3]))"
7830 [(set (match_dup 4) (match_dup 1))
7831 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
7832 (clobber (reg:CC CC_REGNUM))])
7833 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
7834 (set (match_dup 3) (match_dup 4))
7835 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7836 (label_ref (match_dup 0))
7839 [(set_attr "op_type" "RSI")
7840 (set_attr "type" "branch")
7841 (set (attr "length")
7842 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7843 (const_int 6) (const_int 14)))])
7848 (define_expand "doloop_end"
7849 [(use (match_operand 0 "" "")) ; loop pseudo
7850 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7851 (use (match_operand 2 "" "")) ; max iterations
7852 (use (match_operand 3 "" "")) ; loop level
7853 (use (match_operand 4 "" ""))] ; label
7856 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7857 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7858 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7859 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7860 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
7861 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7868 (define_insn_and_split "doloop_si64"
7871 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7873 (label_ref (match_operand 0 "" ""))
7875 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7876 (plus:SI (match_dup 1) (const_int -1)))
7877 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7878 (clobber (reg:CC CC_REGNUM))]
7881 if (which_alternative != 0)
7883 else if (get_attr_length (insn) == 4)
7884 return "brct\t%1,%l0";
7886 return "ahi\t%1,-1\;jgne\t%l0";
7888 "&& reload_completed
7889 && (! REG_P (operands[2])
7890 || ! rtx_equal_p (operands[1], operands[2]))"
7891 [(set (match_dup 3) (match_dup 1))
7892 (parallel [(set (reg:CCAN CC_REGNUM)
7893 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7895 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7896 (set (match_dup 2) (match_dup 3))
7897 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7898 (label_ref (match_dup 0))
7901 [(set_attr "op_type" "RI")
7902 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7903 ; hurt us in the (rare) case of ahi.
7904 (set_attr "z10prop" "z10_super_E1")
7905 (set_attr "type" "branch")
7906 (set (attr "length")
7907 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7908 (const_int 4) (const_int 10)))])
7910 (define_insn_and_split "doloop_si31"
7913 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7915 (label_ref (match_operand 0 "" ""))
7917 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7918 (plus:SI (match_dup 1) (const_int -1)))
7919 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7920 (clobber (reg:CC CC_REGNUM))]
7923 if (which_alternative != 0)
7925 else if (get_attr_length (insn) == 4)
7926 return "brct\t%1,%l0";
7930 "&& reload_completed
7931 && (! REG_P (operands[2])
7932 || ! rtx_equal_p (operands[1], operands[2]))"
7933 [(set (match_dup 3) (match_dup 1))
7934 (parallel [(set (reg:CCAN CC_REGNUM)
7935 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7937 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7938 (set (match_dup 2) (match_dup 3))
7939 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7940 (label_ref (match_dup 0))
7943 [(set_attr "op_type" "RI")
7944 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7945 ; hurt us in the (rare) case of ahi.
7946 (set_attr "z10prop" "z10_super_E1")
7947 (set_attr "type" "branch")
7948 (set (attr "length")
7949 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7950 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7951 (const_int 4) (const_int 6))
7952 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7953 (const_int 4) (const_int 8))))])
7955 (define_insn "*doloop_si_long"
7958 (ne (match_operand:SI 1 "register_operand" "d")
7960 (match_operand 0 "address_operand" "ZQZR")
7962 (set (match_operand:SI 2 "register_operand" "=1")
7963 (plus:SI (match_dup 1) (const_int -1)))
7964 (clobber (match_scratch:SI 3 "=X"))
7965 (clobber (reg:CC CC_REGNUM))]
7968 if (get_attr_op_type (insn) == OP_TYPE_RR)
7969 return "bctr\t%1,%0";
7971 return "bct\t%1,%a0";
7973 [(set (attr "op_type")
7974 (if_then_else (match_operand 0 "register_operand" "")
7975 (const_string "RR") (const_string "RX")))
7976 (set_attr "type" "branch")
7977 (set_attr "atype" "agen")
7978 (set_attr "z10prop" "z10_c")])
7980 (define_insn_and_split "doloop_di"
7983 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7985 (label_ref (match_operand 0 "" ""))
7987 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7988 (plus:DI (match_dup 1) (const_int -1)))
7989 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7990 (clobber (reg:CC CC_REGNUM))]
7993 if (which_alternative != 0)
7995 else if (get_attr_length (insn) == 4)
7996 return "brctg\t%1,%l0";
7998 return "aghi\t%1,-1\;jgne\t%l0";
8000 "&& reload_completed
8001 && (! REG_P (operands[2])
8002 || ! rtx_equal_p (operands[1], operands[2]))"
8003 [(set (match_dup 3) (match_dup 1))
8004 (parallel [(set (reg:CCAN CC_REGNUM)
8005 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8007 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8008 (set (match_dup 2) (match_dup 3))
8009 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8010 (label_ref (match_dup 0))
8013 [(set_attr "op_type" "RI")
8014 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8015 ; hurt us in the (rare) case of ahi.
8016 (set_attr "z10prop" "z10_super_E1")
8017 (set_attr "type" "branch")
8018 (set (attr "length")
8019 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8020 (const_int 4) (const_int 10)))])
8023 ;;- Unconditional jump instructions.
8027 ; jump instruction pattern(s).
8030 (define_expand "jump"
8031 [(match_operand 0 "" "")]
8033 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8035 (define_insn "*jump64"
8036 [(set (pc) (label_ref (match_operand 0 "" "")))]
8039 if (get_attr_length (insn) == 4)
8044 [(set_attr "op_type" "RI")
8045 (set_attr "type" "branch")
8046 (set (attr "length")
8047 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8048 (const_int 4) (const_int 6)))])
8050 (define_insn "*jump31"
8051 [(set (pc) (label_ref (match_operand 0 "" "")))]
8054 gcc_assert (get_attr_length (insn) == 4);
8057 [(set_attr "op_type" "RI")
8058 (set_attr "type" "branch")
8059 (set (attr "length")
8060 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8061 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8062 (const_int 4) (const_int 6))
8063 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8064 (const_int 4) (const_int 8))))])
8067 ; indirect-jump instruction pattern(s).
8070 (define_insn "indirect_jump"
8071 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8074 if (get_attr_op_type (insn) == OP_TYPE_RR)
8079 [(set (attr "op_type")
8080 (if_then_else (match_operand 0 "register_operand" "")
8081 (const_string "RR") (const_string "RX")))
8082 (set_attr "type" "branch")
8083 (set_attr "atype" "agen")])
8086 ; casesi instruction pattern(s).
8089 (define_insn "casesi_jump"
8090 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8091 (use (label_ref (match_operand 1 "" "")))]
8094 if (get_attr_op_type (insn) == OP_TYPE_RR)
8099 [(set (attr "op_type")
8100 (if_then_else (match_operand 0 "register_operand" "")
8101 (const_string "RR") (const_string "RX")))
8102 (set_attr "type" "branch")
8103 (set_attr "atype" "agen")])
8105 (define_expand "casesi"
8106 [(match_operand:SI 0 "general_operand" "")
8107 (match_operand:SI 1 "general_operand" "")
8108 (match_operand:SI 2 "general_operand" "")
8109 (label_ref (match_operand 3 "" ""))
8110 (label_ref (match_operand 4 "" ""))]
8113 rtx index = gen_reg_rtx (SImode);
8114 rtx base = gen_reg_rtx (Pmode);
8115 rtx target = gen_reg_rtx (Pmode);
8117 emit_move_insn (index, operands[0]);
8118 emit_insn (gen_subsi3 (index, index, operands[1]));
8119 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8122 if (Pmode != SImode)
8123 index = convert_to_mode (Pmode, index, 1);
8124 if (GET_CODE (index) != REG)
8125 index = copy_to_mode_reg (Pmode, index);
8128 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8130 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8132 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8134 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8135 emit_move_insn (target, index);
8138 target = gen_rtx_PLUS (Pmode, base, target);
8139 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8146 ;;- Jump to subroutine.
8151 ; untyped call instruction pattern(s).
8154 ;; Call subroutine returning any type.
8155 (define_expand "untyped_call"
8156 [(parallel [(call (match_operand 0 "" "")
8158 (match_operand 1 "" "")
8159 (match_operand 2 "" "")])]
8164 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8166 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8168 rtx set = XVECEXP (operands[2], 0, i);
8169 emit_move_insn (SET_DEST (set), SET_SRC (set));
8172 /* The optimizer does not know that the call sets the function value
8173 registers we stored in the result block. We avoid problems by
8174 claiming that all hard registers are used and clobbered at this
8176 emit_insn (gen_blockage ());
8181 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8182 ;; all of memory. This blocks insns from being moved across this point.
8184 (define_insn "blockage"
8185 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8188 [(set_attr "type" "none")
8189 (set_attr "length" "0")])
8195 (define_expand "sibcall"
8196 [(call (match_operand 0 "" "")
8197 (match_operand 1 "" ""))]
8200 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8204 (define_insn "*sibcall_br"
8205 [(call (mem:QI (reg SIBCALL_REGNUM))
8206 (match_operand 0 "const_int_operand" "n"))]
8207 "SIBLING_CALL_P (insn)
8208 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8210 [(set_attr "op_type" "RR")
8211 (set_attr "type" "branch")
8212 (set_attr "atype" "agen")])
8214 (define_insn "*sibcall_brc"
8215 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8216 (match_operand 1 "const_int_operand" "n"))]
8217 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8219 [(set_attr "op_type" "RI")
8220 (set_attr "type" "branch")])
8222 (define_insn "*sibcall_brcl"
8223 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8224 (match_operand 1 "const_int_operand" "n"))]
8225 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8227 [(set_attr "op_type" "RIL")
8228 (set_attr "type" "branch")])
8231 ; sibcall_value patterns
8234 (define_expand "sibcall_value"
8235 [(set (match_operand 0 "" "")
8236 (call (match_operand 1 "" "")
8237 (match_operand 2 "" "")))]
8240 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8244 (define_insn "*sibcall_value_br"
8245 [(set (match_operand 0 "" "")
8246 (call (mem:QI (reg SIBCALL_REGNUM))
8247 (match_operand 1 "const_int_operand" "n")))]
8248 "SIBLING_CALL_P (insn)
8249 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8251 [(set_attr "op_type" "RR")
8252 (set_attr "type" "branch")
8253 (set_attr "atype" "agen")])
8255 (define_insn "*sibcall_value_brc"
8256 [(set (match_operand 0 "" "")
8257 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8258 (match_operand 2 "const_int_operand" "n")))]
8259 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8261 [(set_attr "op_type" "RI")
8262 (set_attr "type" "branch")])
8264 (define_insn "*sibcall_value_brcl"
8265 [(set (match_operand 0 "" "")
8266 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8267 (match_operand 2 "const_int_operand" "n")))]
8268 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8270 [(set_attr "op_type" "RIL")
8271 (set_attr "type" "branch")])
8275 ; call instruction pattern(s).
8278 (define_expand "call"
8279 [(call (match_operand 0 "" "")
8280 (match_operand 1 "" ""))
8281 (use (match_operand 2 "" ""))]
8284 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8285 gen_rtx_REG (Pmode, RETURN_REGNUM));
8289 (define_insn "*bras"
8290 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8291 (match_operand 1 "const_int_operand" "n"))
8292 (clobber (match_operand 2 "register_operand" "=r"))]
8293 "!SIBLING_CALL_P (insn)
8294 && TARGET_SMALL_EXEC
8295 && GET_MODE (operands[2]) == Pmode"
8297 [(set_attr "op_type" "RI")
8298 (set_attr "type" "jsr")])
8300 (define_insn "*brasl"
8301 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8302 (match_operand 1 "const_int_operand" "n"))
8303 (clobber (match_operand 2 "register_operand" "=r"))]
8304 "!SIBLING_CALL_P (insn)
8306 && GET_MODE (operands[2]) == Pmode"
8308 [(set_attr "op_type" "RIL")
8309 (set_attr "type" "jsr")])
8311 (define_insn "*basr"
8312 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8313 (match_operand 1 "const_int_operand" "n"))
8314 (clobber (match_operand 2 "register_operand" "=r"))]
8315 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8317 if (get_attr_op_type (insn) == OP_TYPE_RR)
8318 return "basr\t%2,%0";
8320 return "bas\t%2,%a0";
8322 [(set (attr "op_type")
8323 (if_then_else (match_operand 0 "register_operand" "")
8324 (const_string "RR") (const_string "RX")))
8325 (set_attr "type" "jsr")
8326 (set_attr "atype" "agen")])
8329 ; call_value instruction pattern(s).
8332 (define_expand "call_value"
8333 [(set (match_operand 0 "" "")
8334 (call (match_operand 1 "" "")
8335 (match_operand 2 "" "")))
8336 (use (match_operand 3 "" ""))]
8339 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8340 gen_rtx_REG (Pmode, RETURN_REGNUM));
8344 (define_insn "*bras_r"
8345 [(set (match_operand 0 "" "")
8346 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8347 (match_operand:SI 2 "const_int_operand" "n")))
8348 (clobber (match_operand 3 "register_operand" "=r"))]
8349 "!SIBLING_CALL_P (insn)
8350 && TARGET_SMALL_EXEC
8351 && GET_MODE (operands[3]) == Pmode"
8353 [(set_attr "op_type" "RI")
8354 (set_attr "type" "jsr")])
8356 (define_insn "*brasl_r"
8357 [(set (match_operand 0 "" "")
8358 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8359 (match_operand 2 "const_int_operand" "n")))
8360 (clobber (match_operand 3 "register_operand" "=r"))]
8361 "!SIBLING_CALL_P (insn)
8363 && GET_MODE (operands[3]) == Pmode"
8365 [(set_attr "op_type" "RIL")
8366 (set_attr "type" "jsr")])
8368 (define_insn "*basr_r"
8369 [(set (match_operand 0 "" "")
8370 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8371 (match_operand 2 "const_int_operand" "n")))
8372 (clobber (match_operand 3 "register_operand" "=r"))]
8373 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8375 if (get_attr_op_type (insn) == OP_TYPE_RR)
8376 return "basr\t%3,%1";
8378 return "bas\t%3,%a1";
8380 [(set (attr "op_type")
8381 (if_then_else (match_operand 1 "register_operand" "")
8382 (const_string "RR") (const_string "RX")))
8383 (set_attr "type" "jsr")
8384 (set_attr "atype" "agen")])
8387 ;;- Thread-local storage support.
8390 (define_expand "get_tp_64"
8391 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8395 (define_expand "get_tp_31"
8396 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8400 (define_expand "set_tp_64"
8401 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8402 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8406 (define_expand "set_tp_31"
8407 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8408 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8412 (define_insn "*set_tp"
8413 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8416 [(set_attr "type" "none")
8417 (set_attr "length" "0")])
8419 (define_insn "*tls_load_64"
8420 [(set (match_operand:DI 0 "register_operand" "=d")
8421 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8422 (match_operand:DI 2 "" "")]
8426 [(set_attr "op_type" "RXE")
8427 (set_attr "z10prop" "z10_fwd_A3")])
8429 (define_insn "*tls_load_31"
8430 [(set (match_operand:SI 0 "register_operand" "=d,d")
8431 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8432 (match_operand:SI 2 "" "")]
8438 [(set_attr "op_type" "RX,RXY")
8439 (set_attr "type" "load")
8440 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8442 (define_insn "*bras_tls"
8443 [(set (match_operand 0 "" "")
8444 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8445 (match_operand 2 "const_int_operand" "n")))
8446 (clobber (match_operand 3 "register_operand" "=r"))
8447 (use (match_operand 4 "" ""))]
8448 "!SIBLING_CALL_P (insn)
8449 && TARGET_SMALL_EXEC
8450 && GET_MODE (operands[3]) == Pmode"
8452 [(set_attr "op_type" "RI")
8453 (set_attr "type" "jsr")])
8455 (define_insn "*brasl_tls"
8456 [(set (match_operand 0 "" "")
8457 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8458 (match_operand 2 "const_int_operand" "n")))
8459 (clobber (match_operand 3 "register_operand" "=r"))
8460 (use (match_operand 4 "" ""))]
8461 "!SIBLING_CALL_P (insn)
8463 && GET_MODE (operands[3]) == Pmode"
8465 [(set_attr "op_type" "RIL")
8466 (set_attr "type" "jsr")])
8468 (define_insn "*basr_tls"
8469 [(set (match_operand 0 "" "")
8470 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8471 (match_operand 2 "const_int_operand" "n")))
8472 (clobber (match_operand 3 "register_operand" "=r"))
8473 (use (match_operand 4 "" ""))]
8474 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8476 if (get_attr_op_type (insn) == OP_TYPE_RR)
8477 return "basr\t%3,%1%J4";
8479 return "bas\t%3,%a1%J4";
8481 [(set (attr "op_type")
8482 (if_then_else (match_operand 1 "register_operand" "")
8483 (const_string "RR") (const_string "RX")))
8484 (set_attr "type" "jsr")
8485 (set_attr "atype" "agen")])
8488 ;;- Atomic operations
8492 ; memory barrier pattern.
8495 (define_expand "memory_barrier"
8497 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8500 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8501 MEM_VOLATILE_P (operands[0]) = 1;
8504 (define_insn "*memory_barrier"
8505 [(set (match_operand:BLK 0 "" "")
8506 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8509 [(set_attr "op_type" "RR")])
8511 ; Although bcr is superscalar on Z10, this variant will never become part of
8512 ; an execution group.
8515 ; compare and swap patterns.
8518 (define_expand "sync_compare_and_swap<mode>"
8520 [(set (match_operand:TDSI 0 "register_operand" "")
8521 (match_operand:TDSI 1 "memory_operand" ""))
8523 (unspec_volatile:TDSI
8525 (match_operand:TDSI 2 "register_operand" "")
8526 (match_operand:TDSI 3 "register_operand" "")]
8528 (set (reg:CCZ1 CC_REGNUM)
8529 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8532 (define_expand "sync_compare_and_swap<mode>"
8534 [(set (match_operand:HQI 0 "register_operand" "")
8535 (match_operand:HQI 1 "memory_operand" ""))
8537 (unspec_volatile:HQI
8539 (match_operand:HQI 2 "general_operand" "")
8540 (match_operand:HQI 3 "general_operand" "")]
8542 (clobber (reg:CC CC_REGNUM))])]
8544 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8545 operands[2], operands[3]); DONE;")
8548 (define_insn "*sync_compare_and_swap<mode>"
8549 [(set (match_operand:DW 0 "register_operand" "=r")
8550 (match_operand:DW 1 "memory_operand" "+Q"))
8554 (match_operand:DW 2 "register_operand" "0")
8555 (match_operand:DW 3 "register_operand" "r")]
8557 (set (reg:CCZ1 CC_REGNUM)
8558 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8560 "cds<tg>\t%0,%3,%S1"
8561 [(set_attr "op_type" "RS<TE>")
8562 (set_attr "type" "sem")])
8565 (define_insn "*sync_compare_and_swap<mode>"
8566 [(set (match_operand:GPR 0 "register_operand" "=r")
8567 (match_operand:GPR 1 "memory_operand" "+Q"))
8569 (unspec_volatile:GPR
8571 (match_operand:GPR 2 "register_operand" "0")
8572 (match_operand:GPR 3 "register_operand" "r")]
8574 (set (reg:CCZ1 CC_REGNUM)
8575 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8578 [(set_attr "op_type" "RS<E>")
8579 (set_attr "type" "sem")])
8583 ; Other atomic instruction patterns.
8586 (define_expand "sync_lock_test_and_set<mode>"
8587 [(match_operand:HQI 0 "register_operand")
8588 (match_operand:HQI 1 "memory_operand")
8589 (match_operand:HQI 2 "general_operand")]
8591 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8592 operands[2], false); DONE;")
8594 (define_expand "sync_<atomic><mode>"
8595 [(set (match_operand:HQI 0 "memory_operand")
8596 (ATOMIC:HQI (match_dup 0)
8597 (match_operand:HQI 1 "general_operand")))]
8599 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8600 operands[1], false); DONE;")
8602 (define_expand "sync_old_<atomic><mode>"
8603 [(set (match_operand:HQI 0 "register_operand")
8604 (match_operand:HQI 1 "memory_operand"))
8606 (ATOMIC:HQI (match_dup 1)
8607 (match_operand:HQI 2 "general_operand")))]
8609 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8610 operands[2], false); DONE;")
8612 (define_expand "sync_new_<atomic><mode>"
8613 [(set (match_operand:HQI 0 "register_operand")
8614 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8615 (match_operand:HQI 2 "general_operand")))
8616 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8618 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8619 operands[2], true); DONE;")
8622 ;;- Miscellaneous instructions.
8626 ; allocate stack instruction pattern(s).
8629 (define_expand "allocate_stack"
8630 [(match_operand 0 "general_operand" "")
8631 (match_operand 1 "general_operand" "")]
8634 rtx temp = gen_reg_rtx (Pmode);
8636 emit_move_insn (temp, s390_back_chain_rtx ());
8637 anti_adjust_stack (operands[1]);
8638 emit_move_insn (s390_back_chain_rtx (), temp);
8640 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8646 ; setjmp instruction pattern.
8649 (define_expand "builtin_setjmp_receiver"
8650 [(match_operand 0 "" "")]
8653 emit_insn (s390_load_got ());
8654 emit_use (pic_offset_table_rtx);
8658 ;; These patterns say how to save and restore the stack pointer. We need not
8659 ;; save the stack pointer at function level since we are careful to
8660 ;; preserve the backchain. At block level, we have to restore the backchain
8661 ;; when we restore the stack pointer.
8663 ;; For nonlocal gotos, we must save both the stack pointer and its
8664 ;; backchain and restore both. Note that in the nonlocal case, the
8665 ;; save area is a memory location.
8667 (define_expand "save_stack_function"
8668 [(match_operand 0 "general_operand" "")
8669 (match_operand 1 "general_operand" "")]
8673 (define_expand "restore_stack_function"
8674 [(match_operand 0 "general_operand" "")
8675 (match_operand 1 "general_operand" "")]
8679 (define_expand "restore_stack_block"
8680 [(match_operand 0 "register_operand" "")
8681 (match_operand 1 "register_operand" "")]
8684 rtx temp = gen_reg_rtx (Pmode);
8686 emit_move_insn (temp, s390_back_chain_rtx ());
8687 emit_move_insn (operands[0], operands[1]);
8688 emit_move_insn (s390_back_chain_rtx (), temp);
8693 (define_expand "save_stack_nonlocal"
8694 [(match_operand 0 "memory_operand" "")
8695 (match_operand 1 "register_operand" "")]
8698 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8700 /* Copy the backchain to the first word, sp to the second and the
8701 literal pool base to the third. */
8703 rtx save_bc = adjust_address (operands[0], Pmode, 0);
8704 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
8705 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
8707 if (TARGET_BACKCHAIN)
8708 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
8710 emit_move_insn (save_sp, operands[1]);
8711 emit_move_insn (save_bp, base);
8716 (define_expand "restore_stack_nonlocal"
8717 [(match_operand 0 "register_operand" "")
8718 (match_operand 1 "memory_operand" "")]
8721 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8722 rtx temp = NULL_RTX;
8724 /* Restore the backchain from the first word, sp from the second and the
8725 literal pool base from the third. */
8727 rtx save_bc = adjust_address (operands[1], Pmode, 0);
8728 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
8729 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
8731 if (TARGET_BACKCHAIN)
8732 temp = force_reg (Pmode, save_bc);
8734 emit_move_insn (base, save_bp);
8735 emit_move_insn (operands[0], save_sp);
8738 emit_move_insn (s390_back_chain_rtx (), temp);
8744 (define_expand "exception_receiver"
8748 s390_set_has_landing_pad_p (true);
8753 ; nop instruction pattern(s).
8760 [(set_attr "op_type" "RR")
8761 (set_attr "z10prop" "z10_fr_E1")])
8767 [(set_attr "op_type" "RR")])
8771 ; Special literal pool access instruction pattern(s).
8774 (define_insn "*pool_entry"
8775 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8776 UNSPECV_POOL_ENTRY)]
8779 enum machine_mode mode = GET_MODE (PATTERN (insn));
8780 unsigned int align = GET_MODE_BITSIZE (mode);
8781 s390_output_pool_entry (operands[0], mode, align);
8784 [(set (attr "length")
8785 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8787 (define_insn "pool_align"
8788 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8789 UNSPECV_POOL_ALIGN)]
8792 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8794 (define_insn "pool_section_start"
8795 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8798 [(set_attr "length" "0")])
8800 (define_insn "pool_section_end"
8801 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8804 [(set_attr "length" "0")])
8806 (define_insn "main_base_31_small"
8807 [(set (match_operand 0 "register_operand" "=a")
8808 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8809 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8811 [(set_attr "op_type" "RR")
8812 (set_attr "type" "la")])
8814 (define_insn "main_base_31_large"
8815 [(set (match_operand 0 "register_operand" "=a")
8816 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8817 (set (pc) (label_ref (match_operand 2 "" "")))]
8818 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8820 [(set_attr "op_type" "RI")])
8822 (define_insn "main_base_64"
8823 [(set (match_operand 0 "register_operand" "=a")
8824 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8825 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8827 [(set_attr "op_type" "RIL")
8828 (set_attr "type" "larl")
8829 (set_attr "z10prop" "z10_fwd_A1")])
8831 (define_insn "main_pool"
8832 [(set (match_operand 0 "register_operand" "=a")
8833 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8834 "GET_MODE (operands[0]) == Pmode"
8839 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8840 (const_string "larl") (const_string "la")))])
8842 (define_insn "reload_base_31"
8843 [(set (match_operand 0 "register_operand" "=a")
8844 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8845 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8846 "basr\t%0,0\;la\t%0,%1-.(%0)"
8847 [(set_attr "length" "6")
8848 (set_attr "type" "la")])
8850 (define_insn "reload_base_64"
8851 [(set (match_operand 0 "register_operand" "=a")
8852 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8853 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8855 [(set_attr "op_type" "RIL")
8856 (set_attr "type" "larl")
8857 (set_attr "z10prop" "z10_fwd_A1")])
8860 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8865 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8868 ;; Insns related to generating the function prologue and epilogue.
8872 (define_expand "prologue"
8873 [(use (const_int 0))]
8875 "s390_emit_prologue (); DONE;")
8877 (define_expand "epilogue"
8878 [(use (const_int 1))]
8880 "s390_emit_epilogue (false); DONE;")
8882 (define_expand "sibcall_epilogue"
8883 [(use (const_int 0))]
8885 "s390_emit_epilogue (true); DONE;")
8887 (define_insn "*return"
8889 (use (match_operand 0 "register_operand" "a"))]
8890 "GET_MODE (operands[0]) == Pmode"
8892 [(set_attr "op_type" "RR")
8893 (set_attr "type" "jsr")
8894 (set_attr "atype" "agen")])
8897 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8898 ;; pointer. This is used for compatibility.
8900 (define_expand "ptr_extend"
8901 [(set (match_operand:DI 0 "register_operand" "=r")
8902 (match_operand:SI 1 "register_operand" "r"))]
8905 emit_insn (gen_anddi3 (operands[0],
8906 gen_lowpart (DImode, operands[1]),
8907 GEN_INT (0x7fffffff)));
8911 ;; Instruction definition to expand eh_return macro to support
8912 ;; swapping in special linkage return addresses.
8914 (define_expand "eh_return"
8915 [(use (match_operand 0 "register_operand" ""))]
8918 s390_emit_tpf_eh_return (operands[0]);
8923 ; Stack Protector Patterns
8926 (define_expand "stack_protect_set"
8927 [(set (match_operand 0 "memory_operand" "")
8928 (match_operand 1 "memory_operand" ""))]
8931 #ifdef TARGET_THREAD_SSP_OFFSET
8933 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8934 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8937 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8939 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8944 (define_insn "stack_protect_set<mode>"
8945 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8946 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8948 "mvc\t%O0(%G0,%R0),%S1"
8949 [(set_attr "op_type" "SS")])
8951 (define_expand "stack_protect_test"
8952 [(set (reg:CC CC_REGNUM)
8953 (compare (match_operand 0 "memory_operand" "")
8954 (match_operand 1 "memory_operand" "")))
8955 (match_operand 2 "" "")]
8959 #ifdef TARGET_THREAD_SSP_OFFSET
8961 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8962 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8965 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8967 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8969 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
8970 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
8971 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
8975 (define_insn "stack_protect_test<mode>"
8976 [(set (reg:CCZ CC_REGNUM)
8977 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8978 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8980 "clc\t%O0(%G0,%R0),%S1"
8981 [(set_attr "op_type" "SS")])
8983 ; This is used in s390_emit_prologue in order to prevent insns
8984 ; adjusting the stack pointer to be moved over insns writing stack
8985 ; slots using a copy of the stack pointer in a different register.
8986 (define_insn "stack_tie"
8987 [(set (match_operand:BLK 0 "memory_operand" "+m")
8988 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8991 [(set_attr "length" "0")])
8995 ; Data prefetch patterns
8998 (define_insn "prefetch"
8999 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9000 (match_operand:SI 1 "const_int_operand" " n,n")
9001 (match_operand:SI 2 "const_int_operand" " n,n"))]
9004 switch (which_alternative)
9007 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9009 if (larl_operand (operands[0], Pmode))
9010 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9013 /* This might be reached for symbolic operands with an odd
9014 addend. We simply omit the prefetch for such rare cases. */
9019 [(set_attr "type" "load,larl")
9020 (set_attr "op_type" "RXY,RIL")
9021 (set_attr "z10prop" "z10_super")])
9025 ; Byte swap instructions
9028 (define_insn "bswap<mode>2"
9029 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9030 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9035 [(set_attr "type" "*,load")
9036 (set_attr "op_type" "RRE,RXY")
9037 (set_attr "z10prop" "z10_super")])