1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 (define_expand "cmpdf"
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
206 (define_expand "cmpsf"
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
219 ; Test-under-Mask (zero_extract) instructions
221 (define_insn "*tmdi_ext"
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
238 operands[2] = GEN_INT (block << shift);
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
249 [(set_attr "op_type" "RI")])
251 (define_insn "*tmsi_ext"
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
268 operands[2] = GEN_INT (block << shift);
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
277 [(set_attr "op_type" "RI")])
279 (define_insn "*tmqi_ext"
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
299 ; Test-under-Mask instructions
301 (define_insn "*tmdi_mem"
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
321 (define_insn "*tmsi_mem"
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
340 (define_insn "*tmhi_mem"
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
359 (define_insn "*tmqi_mem"
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
369 (define_insn "*tmdi_reg"
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmhi_full"
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
420 [(set_attr "op_type" "RX")])
422 (define_insn "*tmqi_full"
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
428 [(set_attr "op_type" "RI")])
431 ; Load-and-Test instructions
433 (define_insn "*tstdi_sign"
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi"
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly"
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
460 [(set_attr "op_type" "RRE")])
462 (define_insn "*tstdi_cconly_31"
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
468 [(set_attr "op_type" "RS")])
470 (define_insn "*tstsi"
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
476 "s390_match_ccmode(insn, CCSmode)"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
483 (define_insn "*tstsi_cconly"
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
495 (define_insn "*tstsi_cconly2"
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
501 [(set_attr "op_type" "RR")])
503 (define_insn "*tsthiCCT"
505 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d,0")
509 "s390_match_ccmode(insn, CCTmode)"
513 [(set_attr "op_type" "RS,RI")
514 (set_attr "atype" "mem,reg")])
516 (define_insn "*tsthiCCT_cconly"
518 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
519 (match_operand:HI 1 "const0_operand" "")))
520 (clobber (match_scratch:HI 2 "=d,X"))]
521 "s390_match_ccmode(insn, CCTmode)"
525 [(set_attr "op_type" "RS,RI")
526 (set_attr "atype" "mem,reg")])
528 (define_insn "*tsthi"
530 (compare (match_operand:HI 0 "s_operand" "Q")
531 (match_operand:HI 1 "const0_operand" "")))
532 (set (match_operand:HI 2 "register_operand" "=d")
534 "s390_match_ccmode(insn, CCSmode)"
536 [(set_attr "op_type" "RS")
537 (set_attr "atype" "mem")])
539 (define_insn "*tsthi_cconly"
541 (compare (match_operand:HI 0 "s_operand" "Q")
542 (match_operand:HI 1 "const0_operand" "")))
543 (clobber (match_scratch:HI 2 "=d"))]
544 "s390_match_ccmode(insn, CCSmode)"
546 [(set_attr "op_type" "RS")
547 (set_attr "atype" "mem")])
549 (define_insn "*tstqiCCT"
551 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
552 (match_operand:QI 1 "const0_operand" "")))
553 (set (match_operand:QI 2 "register_operand" "=d,0")
555 "s390_match_ccmode(insn, CCTmode)"
559 [(set_attr "op_type" "RS,RI")
560 (set_attr "atype" "mem,reg")])
562 (define_insn "*tstqiCCT_cconly"
564 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
565 (match_operand:QI 1 "const0_operand" "")))]
566 "s390_match_ccmode(insn, CCTmode)"
570 [(set_attr "op_type" "SI,RI")
571 (set_attr "atype" "mem,reg")])
573 (define_insn "*tstqi"
575 (compare (match_operand:QI 0 "s_operand" "Q")
576 (match_operand:QI 1 "const0_operand" "")))
577 (set (match_operand:QI 2 "register_operand" "=d")
579 "s390_match_ccmode(insn, CCSmode)"
581 [(set_attr "op_type" "RS")
582 (set_attr "atype" "mem")])
584 (define_insn "*tstqi_cconly"
586 (compare (match_operand:QI 0 "s_operand" "Q")
587 (match_operand:QI 1 "const0_operand" "")))
588 (clobber (match_scratch:QI 2 "=d"))]
589 "s390_match_ccmode(insn, CCSmode)"
591 [(set_attr "op_type" "RS")
592 (set_attr "atype" "mem")])
595 ; Compare (signed) instructions
597 (define_insn "*cmpdi_ccs_sign"
599 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
600 (match_operand:DI 0 "register_operand" "d,d")))]
601 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
605 [(set_attr "op_type" "RRE,RXE")
606 (set_attr "atype" "reg,mem")])
608 (define_insn "*cmpdi_ccs"
610 (compare (match_operand:DI 0 "register_operand" "d,d,d")
611 (match_operand:DI 1 "general_operand" "d,K,m")))]
612 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
617 [(set_attr "op_type" "RRE,RI,RXE")
618 (set_attr "atype" "reg,reg,mem")])
620 (define_insn "*cmpsi_ccs_sign"
622 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
623 (match_operand:SI 0 "register_operand" "d")))]
624 "s390_match_ccmode(insn, CCSRmode)"
626 [(set_attr "op_type" "RX")
627 (set_attr "atype" "mem")])
629 (define_insn "*cmpsi_ccs"
631 (compare (match_operand:SI 0 "register_operand" "d,d,d")
632 (match_operand:SI 1 "general_operand" "d,K,m")))]
633 "s390_match_ccmode(insn, CCSmode)"
638 [(set_attr "op_type" "RR,RI,RX")
639 (set_attr "atype" "reg,reg,mem")])
642 ; Compare (unsigned) instructions
644 (define_insn "*cmpdi_ccu_zero"
646 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
647 (match_operand:DI 0 "register_operand" "d,d")))]
648 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
652 [(set_attr "op_type" "RRE,RXE")
653 (set_attr "atype" "reg,mem")])
655 (define_insn "*cmpdi_ccu"
657 (compare (match_operand:DI 0 "register_operand" "d,d")
658 (match_operand:DI 1 "general_operand" "d,m")))]
659 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
663 [(set_attr "op_type" "RRE,RXE")
664 (set_attr "atype" "reg,mem")])
666 (define_insn "*cmpsi_ccu"
668 (compare (match_operand:SI 0 "register_operand" "d,d")
669 (match_operand:SI 1 "general_operand" "d,m")))]
670 "s390_match_ccmode(insn, CCUmode)"
674 [(set_attr "op_type" "RR,RX")
675 (set_attr "atype" "reg,mem")])
677 (define_insn "*cmphi_ccu"
679 (compare (match_operand:HI 0 "register_operand" "d")
680 (match_operand:HI 1 "s_imm_operand" "Q")))]
681 "s390_match_ccmode(insn, CCUmode)"
683 [(set_attr "op_type" "RS")
684 (set_attr "atype" "mem")])
686 (define_insn "*cmpqi_ccu"
688 (compare (match_operand:QI 0 "register_operand" "d")
689 (match_operand:QI 1 "s_imm_operand" "Q")))]
690 "s390_match_ccmode(insn, CCUmode)"
692 [(set_attr "op_type" "RS")
693 (set_attr "atype" "mem")])
697 (compare (match_operand:QI 0 "memory_operand" "Q")
698 (match_operand:QI 1 "immediate_operand" "n")))]
699 "s390_match_ccmode (insn, CCUmode)"
701 [(set_attr "op_type" "SI")
702 (set_attr "atype" "mem")])
704 (define_insn "*cmpdi_ccu_mem"
706 (compare (match_operand:DI 0 "s_operand" "Q")
707 (match_operand:DI 1 "s_imm_operand" "Q")))]
708 "s390_match_ccmode(insn, CCUmode)"
709 "clc\\t%O0(8,%R0),%1"
710 [(set_attr "op_type" "SS")
711 (set_attr "atype" "mem")])
713 (define_insn "*cmpsi_ccu_mem"
715 (compare (match_operand:SI 0 "s_operand" "Q")
716 (match_operand:SI 1 "s_imm_operand" "Q")))]
717 "s390_match_ccmode(insn, CCUmode)"
718 "clc\\t%O0(4,%R0),%1"
719 [(set_attr "op_type" "SS")
720 (set_attr "atype" "mem")])
722 (define_insn "*cmphi_ccu_mem"
724 (compare (match_operand:HI 0 "s_operand" "Q")
725 (match_operand:HI 1 "s_imm_operand" "Q")))]
726 "s390_match_ccmode(insn, CCUmode)"
727 "clc\\t%O0(2,%R0),%1"
728 [(set_attr "op_type" "SS")
729 (set_attr "atype" "mem")])
731 (define_insn "*cmpqi_ccu_mem"
733 (compare (match_operand:QI 0 "s_operand" "Q")
734 (match_operand:QI 1 "s_imm_operand" "Q")))]
735 "s390_match_ccmode(insn, CCUmode)"
736 "clc\\t%O0(1,%R0),%1"
737 [(set_attr "op_type" "SS")
738 (set_attr "atype" "mem")])
743 (define_insn "*cmpdf_ccs_0"
745 (compare (match_operand:DF 0 "register_operand" "f")
746 (match_operand:DF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
749 [(set_attr "op_type" "RRE")])
751 (define_insn "*cmpdf_ccs_0_ibm"
753 (compare (match_operand:DF 0 "register_operand" "f")
754 (match_operand:DF 1 "const0_operand" "")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
757 [(set_attr "op_type" "RR")])
759 (define_insn "*cmpdf_ccs"
761 (compare (match_operand:DF 0 "register_operand" "f,f")
762 (match_operand:DF 1 "general_operand" "f,m")))]
763 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
767 [(set_attr "op_type" "RRE,RXE")
768 (set_attr "atype" "reg,mem")])
770 (define_insn "*cmpdf_ccs_ibm"
772 (compare (match_operand:DF 0 "register_operand" "f,f")
773 (match_operand:DF 1 "general_operand" "f,m")))]
774 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
778 [(set_attr "op_type" "RR,RX")
779 (set_attr "atype" "reg,mem")])
784 (define_insn "*cmpsf_ccs_0"
786 (compare (match_operand:SF 0 "register_operand" "f")
787 (match_operand:SF 1 "const0_operand" "")))]
788 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
790 [(set_attr "op_type" "RRE")])
792 (define_insn "*cmpsf_ccs_0_ibm"
794 (compare (match_operand:SF 0 "register_operand" "f")
795 (match_operand:SF 1 "const0_operand" "")))]
796 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
798 [(set_attr "op_type" "RR")])
800 (define_insn "*cmpsf_ccs"
802 (compare (match_operand:SF 0 "register_operand" "f,f")
803 (match_operand:SF 1 "general_operand" "f,m")))]
804 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
808 [(set_attr "op_type" "RRE,RXE")
809 (set_attr "atype" "reg,mem")])
811 (define_insn "*cmpsf_ccs"
813 (compare (match_operand:SF 0 "register_operand" "f,f")
814 (match_operand:SF 1 "general_operand" "f,m")))]
815 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
819 [(set_attr "op_type" "RR,RX")
820 (set_attr "atype" "reg,mem")])
824 ;;- Move instructions.
828 ; movti instruction pattern(s).
832 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
833 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
840 mvc\\t%O0(16,%R0),%1"
841 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
842 (set_attr "atype" "mem")])
845 [(set (match_operand:TI 0 "nonimmediate_operand" "")
846 (match_operand:TI 1 "general_operand" ""))]
847 "TARGET_64BIT && reload_completed
848 && !s_operand (operands[0], VOIDmode)
849 && !s_operand (operands[1], VOIDmode)
850 && (register_operand (operands[0], VOIDmode)
851 || register_operand (operands[1], VOIDmode))
852 && (!register_operand (operands[0], VOIDmode)
853 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
855 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
857 [(set (match_dup 2) (match_dup 4))
858 (set (match_dup 3) (match_dup 5))]
861 if (!register_operand (operands[0], VOIDmode)
862 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
865 operands[2] = operand_subword (operands[0], 0, 0, TImode);
866 operands[3] = operand_subword (operands[0], 1, 0, TImode);
867 operands[4] = operand_subword (operands[1], 0, 0, TImode);
868 operands[5] = operand_subword (operands[1], 1, 0, TImode);
872 operands[2] = operand_subword (operands[0], 1, 0, TImode);
873 operands[3] = operand_subword (operands[0], 0, 0, TImode);
874 operands[4] = operand_subword (operands[1], 1, 0, TImode);
875 operands[5] = operand_subword (operands[1], 0, 0, TImode);
880 [(set (match_operand:TI 0 "register_operand" "")
881 (match_operand:TI 1 "memory_operand" ""))]
882 "TARGET_64BIT && reload_completed
883 && !s_operand (operands[1], VOIDmode)"
884 [(set (match_dup 0) (match_dup 1))]
887 rtx addr = operand_subword (operands[0], 1, 0, TImode);
888 s390_load_address (addr, XEXP (operands[1], 0));
889 operands[1] = replace_equiv_address (operands[1], addr);
893 ; movdi instruction pattern(s).
896 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
897 ;; move to get the address of the symbolic object from the GOT.
899 (define_expand "movdi"
900 [(set (match_operand:DI 0 "general_operand" "")
901 (match_operand:DI 1 "general_operand" ""))]
905 /* Handle PIC symbolic constants. */
906 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
907 emit_pic_move (operands, DImode);
909 /* During and after reload, we need to force constants
910 to the literal pool ourselves, if necessary. */
911 if ((reload_in_progress || reload_completed)
912 && CONSTANT_P (operands[1])
913 && (!legitimate_reload_constant_p (operands[1])
914 || FP_REG_P (operands[0])))
915 operands[1] = force_const_mem (DImode, operands[1]);
918 (define_insn "*movdi_lhi"
919 [(set (match_operand:DI 0 "register_operand" "=d")
920 (match_operand:DI 1 "immediate_operand" "K"))]
922 && GET_CODE (operands[1]) == CONST_INT
923 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
924 && !FP_REG_P (operands[0])"
926 [(set_attr "op_type" "RI")
927 (set_attr "atype" "reg")])
929 (define_insn "*movdi_lli"
930 [(set (match_operand:DI 0 "register_operand" "=d")
931 (match_operand:DI 1 "immediate_operand" "n"))]
932 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
933 && !FP_REG_P (operands[0])"
936 int part = s390_single_hi (operands[1], DImode, 0);
937 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
941 case 0: return \"llihh\\t%0,%x1\";
942 case 1: return \"llihl\\t%0,%x1\";
943 case 2: return \"llilh\\t%0,%x1\";
944 case 3: return \"llill\\t%0,%x1\";
948 [(set_attr "op_type" "RI")
949 (set_attr "atype" "reg")])
951 (define_insn "*movdi_larl"
952 [(set (match_operand:DI 0 "register_operand" "=d")
953 (match_operand:DI 1 "larl_operand" "X"))]
955 && !FP_REG_P (operands[0])"
957 [(set_attr "op_type" "RIL")
958 (set_attr "atype" "reg")
959 (set_attr "type" "la")])
961 (define_insn "*movdi_64"
962 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
963 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
973 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
974 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
976 (define_insn "*movdi_31"
977 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
978 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
989 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
990 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
993 [(set (match_operand:DI 0 "nonimmediate_operand" "")
994 (match_operand:DI 1 "general_operand" ""))]
995 "!TARGET_64BIT && reload_completed
996 && !FP_REG_P (operands[0])
997 && !FP_REG_P (operands[1])
998 && !s_operand (operands[0], VOIDmode)
999 && !s_operand (operands[1], VOIDmode)
1000 && (register_operand (operands[0], VOIDmode)
1001 || register_operand (operands[1], VOIDmode))
1002 && (!register_operand (operands[0], VOIDmode)
1003 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1005 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
1007 [(set (match_dup 2) (match_dup 4))
1008 (set (match_dup 3) (match_dup 5))]
1011 if (!register_operand (operands[0], VOIDmode)
1012 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1015 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1016 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1017 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1018 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1022 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1023 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1024 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1025 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1030 [(set (match_operand:DI 0 "register_operand" "")
1031 (match_operand:DI 1 "memory_operand" ""))]
1032 "!TARGET_64BIT && reload_completed
1033 && !FP_REG_P (operands[0])
1034 && !FP_REG_P (operands[1])
1035 && !s_operand (operands[1], VOIDmode)"
1036 [(set (match_dup 0) (match_dup 1))]
1039 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1040 s390_load_address (addr, XEXP (operands[1], 0));
1041 operands[1] = replace_equiv_address (operands[1], addr);
1045 [(set (match_operand:DI 0 "register_operand" "")
1046 (mem:DI (match_operand 1 "address_operand" "")))]
1048 && !FP_REG_P (operands[0])
1049 && GET_CODE (operands[1]) == SYMBOL_REF
1050 && CONSTANT_POOL_ADDRESS_P (operands[1])
1051 && get_pool_mode (operands[1]) == DImode
1052 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1053 [(set (match_dup 0) (match_dup 2))]
1054 "operands[2] = get_pool_constant (operands[1]);")
1057 ; movsi instruction pattern(s).
1060 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1061 ;; move to get the address of the symbolic object from the GOT.
1063 (define_expand "movsi"
1064 [(set (match_operand:SI 0 "general_operand" "")
1065 (match_operand:SI 1 "general_operand" ""))]
1069 /* Handle PIC symbolic constants. */
1070 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1071 emit_pic_move (operands, SImode);
1073 /* expr.c tries to load an effective address using
1074 force_reg. This fails because we don't have a
1075 generic load_address pattern. Convert the move
1076 to a proper arithmetic operation instead, unless
1077 it is guaranteed to be OK. */
1078 if (GET_CODE (operands[1]) == PLUS
1079 && !legitimate_la_operand_p (operands[1]))
1081 operands[1] = force_operand (operands[1], operands[0]);
1082 if (operands[1] == operands[0])
1086 /* During and after reload, we need to force constants
1087 to the literal pool ourselves, if necessary. */
1088 if ((reload_in_progress || reload_completed)
1089 && CONSTANT_P (operands[1])
1090 && (!legitimate_reload_constant_p (operands[1])
1091 || FP_REG_P (operands[0])))
1092 operands[1] = force_const_mem (SImode, operands[1]);
1095 (define_insn "*movsi_lhi"
1096 [(set (match_operand:SI 0 "register_operand" "=d")
1097 (match_operand:SI 1 "immediate_operand" "K"))]
1098 "GET_CODE (operands[1]) == CONST_INT
1099 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1100 && !FP_REG_P (operands[0])"
1102 [(set_attr "op_type" "RI")])
1104 (define_insn "*movsi_lli"
1105 [(set (match_operand:SI 0 "register_operand" "=d")
1106 (match_operand:SI 1 "immediate_operand" "n"))]
1107 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1108 && !FP_REG_P (operands[0])"
1111 int part = s390_single_hi (operands[1], SImode, 0);
1112 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1116 case 0: return \"llilh\\t%0,%x1\";
1117 case 1: return \"llill\\t%0,%x1\";
1121 [(set_attr "op_type" "RI")])
1123 (define_insn "*movsi"
1124 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1125 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1134 mvc\\t%O0(4,%R0),%1"
1135 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1136 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1139 [(set (match_operand:SI 0 "register_operand" "")
1140 (mem:SI (match_operand 1 "address_operand" "")))]
1141 "!FP_REG_P (operands[0])
1142 && GET_CODE (operands[1]) == SYMBOL_REF
1143 && CONSTANT_POOL_ADDRESS_P (operands[1])
1144 && get_pool_mode (operands[1]) == SImode
1145 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1146 [(set (match_dup 0) (match_dup 2))]
1147 "operands[2] = get_pool_constant (operands[1]);")
1150 ; movhi instruction pattern(s).
1153 (define_insn "movhi"
1154 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1155 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1162 mvc\\t%O0(2,%R0),%1"
1163 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1164 (set_attr "atype" "reg,reg,mem,mem,mem")])
1167 [(set (match_operand:HI 0 "register_operand" "")
1168 (mem:HI (match_operand 1 "address_operand" "")))]
1169 "GET_CODE (operands[1]) == SYMBOL_REF
1170 && CONSTANT_POOL_ADDRESS_P (operands[1])
1171 && get_pool_mode (operands[1]) == HImode
1172 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1173 [(set (match_dup 0) (match_dup 2))]
1174 "operands[2] = get_pool_constant (operands[1]);")
1177 ; movqi instruction pattern(s).
1180 (define_insn "movqi_64"
1181 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1182 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1190 mvc\\t%O0(1,%R0),%1"
1191 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1192 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1195 (define_insn "movqi"
1196 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1197 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1205 mvc\\t%O0(1,%R0),%1"
1206 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1207 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1210 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1211 (mem:QI (match_operand 1 "address_operand" "")))]
1212 "GET_CODE (operands[1]) == SYMBOL_REF
1213 && CONSTANT_POOL_ADDRESS_P (operands[1])
1214 && get_pool_mode (operands[1]) == QImode
1215 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1216 [(set (match_dup 0) (match_dup 2))]
1217 "operands[2] = get_pool_constant (operands[1]);")
1220 ; movstrictqi instruction pattern(s).
1223 (define_insn "*movstrictqi"
1224 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1225 (match_operand:QI 1 "memory_operand" "m"))]
1228 [(set_attr "op_type" "RX")
1229 (set_attr "atype" "mem")])
1232 ; movstricthi instruction pattern(s).
1235 (define_insn "*movstricthi"
1236 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1237 (match_operand:HI 1 "s_imm_operand" "Q"))
1238 (clobber (reg:CC 33))]
1241 [(set_attr "op_type" "RS")
1242 (set_attr "atype" "mem")])
1246 ; movstrictsi instruction pattern(s).
1249 (define_insn "movstrictsi"
1250 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1251 (match_operand:SI 1 "general_operand" "d,m"))]
1256 [(set_attr "op_type" "RR,RS")
1257 (set_attr "atype" "reg,mem")])
1261 ; movdf instruction pattern(s).
1264 (define_expand "movdf"
1265 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1266 (match_operand:DF 1 "general_operand" ""))]
1270 /* During and after reload, we need to force constants
1271 to the literal pool ourselves, if necessary. */
1272 if ((reload_in_progress || reload_completed)
1273 && CONSTANT_P (operands[1]))
1274 operands[1] = force_const_mem (DFmode, operands[1]);
1277 (define_insn "*movdf_64"
1278 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1279 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1288 mvc\\t%O0(8,%R0),%1"
1289 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1290 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1292 (define_insn "*movdf_31"
1293 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1294 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1304 mvc\\t%O0(8,%R0),%1"
1305 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1306 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1309 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1310 (match_operand:DF 1 "general_operand" ""))]
1311 "!TARGET_64BIT && reload_completed
1312 && !FP_REG_P (operands[0])
1313 && !FP_REG_P (operands[1])
1314 && !s_operand (operands[0], VOIDmode)
1315 && !s_operand (operands[1], VOIDmode)
1316 && (register_operand (operands[0], VOIDmode)
1317 || register_operand (operands[1], VOIDmode))
1318 && (!register_operand (operands[0], VOIDmode)
1319 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1321 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1323 [(set (match_dup 2) (match_dup 4))
1324 (set (match_dup 3) (match_dup 5))]
1327 if (!register_operand (operands[0], VOIDmode)
1328 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1331 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1332 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1333 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1334 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1338 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1339 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1340 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1341 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1346 [(set (match_operand:DF 0 "register_operand" "")
1347 (match_operand:DF 1 "memory_operand" ""))]
1348 "!TARGET_64BIT && reload_completed
1349 && !FP_REG_P (operands[0])
1350 && !FP_REG_P (operands[1])
1351 && !s_operand (operands[1], VOIDmode)"
1352 [(set (match_dup 0) (match_dup 1))]
1355 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1356 s390_load_address (addr, XEXP (operands[1], 0));
1357 operands[1] = replace_equiv_address (operands[1], addr);
1361 ; movsf instruction pattern(s).
1364 (define_expand "movsf"
1365 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1366 (match_operand:SF 1 "general_operand" ""))]
1370 /* During and after reload, we need to force constants
1371 to the literal pool ourselves, if necessary. */
1372 if ((reload_in_progress || reload_completed)
1373 && CONSTANT_P (operands[1]))
1374 operands[1] = force_const_mem (SFmode, operands[1]);
1377 (define_insn "*movsf"
1378 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1379 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1388 mvc\\t%O0(4,%R0),%1"
1389 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1390 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1393 ; load_multiple pattern(s).
1396 (define_expand "load_multiple"
1397 [(match_par_dup 3 [(set (match_operand 0 "" "")
1398 (match_operand 1 "" ""))
1399 (use (match_operand 2 "" ""))])]
1408 /* Support only loading a constant number of fixed-point registers from
1409 memory and only bother with this if more than two */
1410 if (GET_CODE (operands[2]) != CONST_INT
1411 || INTVAL (operands[2]) < 2
1412 || INTVAL (operands[2]) > 16
1413 || GET_CODE (operands[1]) != MEM
1414 || GET_CODE (operands[0]) != REG
1415 || REGNO (operands[0]) >= 16)
1418 count = INTVAL (operands[2]);
1419 regno = REGNO (operands[0]);
1421 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1424 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1426 from = XEXP (operands[1], 0);
1429 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1430 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1431 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1433 from = XEXP (XEXP (operands[1], 0), 0);
1434 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1439 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1444 from = force_reg (Pmode, XEXP (operands[1], 0));
1448 for (i = 0; i < count; i++)
1449 XVECEXP (operands[3], 0, i)
1450 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1451 change_address (operands[1], Pmode,
1452 plus_constant (from,
1453 off + i * UNITS_PER_WORD)));
1456 (define_insn "*load_multiple_di"
1457 [(match_parallel 0 "load_multiple_operation"
1458 [(set (match_operand:DI 1 "register_operand" "=r")
1459 (match_operand:DI 2 "s_operand" "Q"))])]
1463 int words = XVECLEN (operands[0], 0);
1465 if (XVECLEN (operands[0], 0) == 1)
1466 return \"lg\\t%1,0(%2)\";
1468 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1469 return \"lmg\\t%1,%0,%2\";
1471 [(set_attr "op_type" "RXE")
1472 (set_attr "atype" "mem")
1473 (set_attr "type" "lm")])
1475 (define_insn "*load_multiple_si"
1476 [(match_parallel 0 "load_multiple_operation"
1477 [(set (match_operand:SI 1 "register_operand" "=r")
1478 (match_operand:SI 2 "s_operand" "Q"))])]
1482 int words = XVECLEN (operands[0], 0);
1484 if (XVECLEN (operands[0], 0) == 1)
1485 return \"l\\t%1,0(%2)\";
1487 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1488 return \"lm\\t%1,%0,%2\";
1490 [(set_attr "op_type" "RXE")
1491 (set_attr "atype" "mem")
1492 (set_attr "type" "lm")])
1495 ; store multiple pattern(s).
1498 (define_expand "store_multiple"
1499 [(match_par_dup 3 [(set (match_operand 0 "" "")
1500 (match_operand 1 "" ""))
1501 (use (match_operand 2 "" ""))])]
1510 /* Support only storing a constant number of fixed-point registers to
1511 memory and only bother with this if more than two. */
1512 if (GET_CODE (operands[2]) != CONST_INT
1513 || INTVAL (operands[2]) < 2
1514 || INTVAL (operands[2]) > 16
1515 || GET_CODE (operands[0]) != MEM
1516 || GET_CODE (operands[1]) != REG
1517 || REGNO (operands[1]) >= 16)
1520 count = INTVAL (operands[2]);
1521 regno = REGNO (operands[1]);
1523 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1527 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1529 to = XEXP (operands[0], 0);
1532 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1533 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1534 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1536 to = XEXP (XEXP (operands[0], 0), 0);
1537 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1542 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1547 to = force_reg (Pmode, XEXP (operands[0], 0));
1551 for (i = 0; i < count; i++)
1552 XVECEXP (operands[3], 0, i)
1553 = gen_rtx_SET (VOIDmode,
1554 change_address (operands[0], Pmode,
1556 off + i * UNITS_PER_WORD)),
1557 gen_rtx_REG (Pmode, regno + i));
1560 (define_insn "*store_multiple_di"
1561 [(match_parallel 0 "store_multiple_operation"
1562 [(set (match_operand:DI 1 "s_operand" "=Q")
1563 (match_operand:DI 2 "register_operand" "r"))])]
1567 int words = XVECLEN (operands[0], 0);
1569 if (XVECLEN (operands[0], 0) == 1)
1570 return \"stg\\t%1,0(%2)\";
1572 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1573 return \"stmg\\t%2,%0,%1\";
1575 [(set_attr "op_type" "RXE")
1576 (set_attr "atype" "mem")
1577 (set_attr "type" "stm")])
1580 (define_insn "*store_multiple_si"
1581 [(match_parallel 0 "store_multiple_operation"
1582 [(set (match_operand:SI 1 "s_operand" "=Q")
1583 (match_operand:SI 2 "register_operand" "r"))])]
1587 int words = XVECLEN (operands[0], 0);
1589 if (XVECLEN (operands[0], 0) == 1)
1590 return \"st\\t%1,0(%2)\";
1592 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1593 return \"stm\\t%2,%0,%1\";
1595 [(set_attr "op_type" "RXE")
1596 (set_attr "atype" "mem")
1597 (set_attr "type" "stm")])
1600 ;; String instructions.
1604 ; movstrM instruction pattern(s).
1607 (define_expand "movstrdi"
1608 [(set (match_operand:BLK 0 "memory_operand" "")
1609 (match_operand:BLK 1 "memory_operand" ""))
1610 (use (match_operand:DI 2 "general_operand" ""))
1611 (match_operand 3 "" "")]
1613 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1615 (define_expand "movstrsi"
1616 [(set (match_operand:BLK 0 "memory_operand" "")
1617 (match_operand:BLK 1 "memory_operand" ""))
1618 (use (match_operand:SI 2 "general_operand" ""))
1619 (match_operand 3 "" "")]
1621 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1623 ; Move a block that is up to 256 bytes in length.
1624 ; The block length is taken as (operands[2] % 256) + 1.
1626 (define_insn "movstr_short_64"
1627 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1628 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1629 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1630 (clobber (match_scratch:DI 3 "=X,&a"))]
1634 switch (which_alternative)
1637 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1640 output_asm_insn (\"bras\\t%3,.+10\", operands);
1641 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1642 return \"ex\\t%2,0(%3)\";
1648 [(set_attr "op_type" "SS,NN")
1649 (set_attr "type" "cs,cs")
1650 (set_attr "atype" "mem,mem")
1651 (set_attr "length" "*,14")])
1653 (define_insn "movstr_short_31"
1654 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1655 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1656 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1657 (clobber (match_scratch:SI 3 "=X,&a"))]
1661 switch (which_alternative)
1664 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1667 output_asm_insn (\"bras\\t%3,.+10\", operands);
1668 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1669 return \"ex\\t%2,0(%3)\";
1675 [(set_attr "op_type" "SS,NN")
1676 (set_attr "type" "cs,cs")
1677 (set_attr "atype" "mem,mem")
1678 (set_attr "length" "*,14")])
1680 ; Move a block of arbitrary length.
1682 (define_insn "movstr_long_64"
1683 [(set (match_operand:TI 0 "register_operand" "=d")
1684 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1685 (lshiftrt:TI (match_dup 2) (const_int 64)))
1687 (set (match_operand:TI 1 "register_operand" "=d")
1688 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1689 (lshiftrt:TI (match_dup 3) (const_int 64)))
1691 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1692 (mem:BLK (subreg:DI (match_dup 3) 0)))
1693 (clobber (reg:CC 33))]
1695 "mvcle\\t%0,%1,0\;jo\\t.-4"
1696 [(set_attr "op_type" "NN")
1697 (set_attr "type" "vs")
1698 (set_attr "atype" "mem")
1699 (set_attr "length" "8")])
1701 (define_insn "movstr_long_31"
1702 [(set (match_operand:DI 0 "register_operand" "=d")
1703 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1704 (lshiftrt:DI (match_dup 2) (const_int 32)))
1706 (set (match_operand:DI 1 "register_operand" "=d")
1707 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1708 (lshiftrt:DI (match_dup 3) (const_int 32)))
1710 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1711 (mem:BLK (subreg:SI (match_dup 3) 0)))
1712 (clobber (reg:CC 33))]
1714 "mvcle\\t%0,%1,0\;jo\\t.-4"
1715 [(set_attr "op_type" "NN")
1716 (set_attr "type" "vs")
1717 (set_attr "atype" "mem")
1718 (set_attr "length" "8")])
1721 ; clrstrM instruction pattern(s).
1724 (define_expand "clrstrdi"
1725 [(set (match_operand:BLK 0 "memory_operand" "")
1727 (use (match_operand:DI 1 "general_operand" ""))
1728 (match_operand 2 "" "")]
1730 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1732 (define_expand "clrstrsi"
1733 [(set (match_operand:BLK 0 "memory_operand" "")
1735 (use (match_operand:SI 1 "general_operand" ""))
1736 (match_operand 2 "" "")]
1738 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1740 ; Clear a block that is up to 256 bytes in length.
1741 ; The block length is taken as (operands[2] % 256) + 1.
1743 (define_insn "clrstr_short_64"
1744 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1746 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1747 (clobber (match_scratch:DI 2 "=X,&a"))
1748 (clobber (reg:CC 33))]
1752 switch (which_alternative)
1755 return \"xc\\t%O0(%b1+1,%R0),%0\";
1758 output_asm_insn (\"bras\\t%2,.+10\", operands);
1759 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1760 return \"ex\\t%1,0(%2)\";
1766 [(set_attr "op_type" "SS,NN")
1767 (set_attr "type" "cs,cs")
1768 (set_attr "atype" "mem,mem")
1769 (set_attr "length" "*,14")])
1771 (define_insn "clrstr_short_31"
1772 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1774 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1775 (clobber (match_scratch:SI 2 "=X,&a"))
1776 (clobber (reg:CC 33))]
1780 switch (which_alternative)
1783 return \"xc\\t%O0(%b1+1,%R0),%0\";
1786 output_asm_insn (\"bras\\t%2,.+10\", operands);
1787 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1788 return \"ex\\t%1,0(%2)\";
1794 [(set_attr "op_type" "SS,NN")
1795 (set_attr "type" "cs,cs")
1796 (set_attr "atype" "mem,mem")
1797 (set_attr "length" "*,14")])
1799 ; Clear a block of arbitrary length.
1801 (define_insn "clrstr_long_64"
1802 [(set (match_operand:TI 0 "register_operand" "=d")
1803 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1804 (lshiftrt:TI (match_dup 2) (const_int 64)))
1806 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1808 (use (match_operand:TI 1 "register_operand" "d"))
1809 (clobber (reg:CC 33))]
1811 "mvcle\\t%0,%1,0\;jo\\t.-4"
1812 [(set_attr "op_type" "NN")
1813 (set_attr "atype" "mem")
1814 (set_attr "type" "vs")
1815 (set_attr "length" "8")])
1817 (define_insn "clrstr_long_31"
1818 [(set (match_operand:DI 0 "register_operand" "=d")
1819 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1820 (lshiftrt:DI (match_dup 2) (const_int 32)))
1822 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1824 (use (match_operand:DI 1 "register_operand" "d"))
1825 (clobber (reg:CC 33))]
1827 "mvcle\\t%0,%1,0\;jo\\t.-4"
1828 [(set_attr "op_type" "NN")
1829 (set_attr "atype" "mem")
1830 (set_attr "type" "vs")
1831 (set_attr "length" "8")])
1834 ; cmpstrM instruction pattern(s).
1837 (define_expand "cmpstrdi"
1838 [(set (match_operand:DI 0 "register_operand" "")
1839 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1840 (match_operand:BLK 2 "memory_operand" "") ) )
1841 (use (match_operand:DI 3 "general_operand" ""))
1842 (use (match_operand:DI 4 "" ""))]
1844 "s390_expand_cmpstr (operands[0], operands[1],
1845 operands[2], operands[3]); DONE;")
1847 (define_expand "cmpstrsi"
1848 [(set (match_operand:SI 0 "register_operand" "")
1849 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1850 (match_operand:BLK 2 "memory_operand" "") ) )
1851 (use (match_operand:SI 3 "general_operand" ""))
1852 (use (match_operand:SI 4 "" ""))]
1854 "s390_expand_cmpstr (operands[0], operands[1],
1855 operands[2], operands[3]); DONE;")
1857 ; Compare a block that is up to 256 bytes in length.
1858 ; The block length is taken as (operands[2] % 256) + 1.
1860 (define_insn "cmpstr_short_64"
1862 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1863 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1864 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1865 (clobber (match_scratch:DI 3 "=X,&a"))]
1869 switch (which_alternative)
1872 return \"clc\\t%O0(%b2+1,%R0),%1\";
1875 output_asm_insn (\"bras\\t%3,.+10\", operands);
1876 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1877 return \"ex\\t%2,0(%3)\";
1883 [(set_attr "op_type" "SS,NN")
1884 (set_attr "type" "cs,cs")
1885 (set_attr "atype" "mem,mem")
1886 (set_attr "length" "*,14")])
1888 (define_insn "cmpstr_short_31"
1890 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1891 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1892 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1893 (clobber (match_scratch:SI 3 "=X,&a"))]
1897 switch (which_alternative)
1900 return \"clc\\t%O0(%b2+1,%R0),%1\";
1903 output_asm_insn (\"bras\\t%3,.+10\", operands);
1904 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1905 return \"ex\\t%2,0(%3)\";
1911 [(set_attr "op_type" "SS,NN")
1912 (set_attr "type" "cs,cs")
1913 (set_attr "atype" "mem,mem")
1914 (set_attr "length" "*,14")])
1916 ; Compare a block of arbitrary length.
1918 (define_insn "cmpstr_long_64"
1919 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1920 (clobber (match_operand:TI 1 "register_operand" "=d"))
1922 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1923 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1925 (use (match_dup 3))]
1928 [(set_attr "op_type" "RR")
1929 (set_attr "atype" "mem")
1930 (set_attr "type" "vs")])
1932 (define_insn "cmpstr_long_31"
1933 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1934 (clobber (match_operand:DI 1 "register_operand" "=d"))
1936 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1937 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1939 (use (match_dup 3))]
1942 [(set_attr "op_type" "RR")
1943 (set_attr "atype" "mem")
1944 (set_attr "type" "vs")])
1946 ; Convert condition code to integer in range (-1, 0, 1)
1948 (define_insn "cmpint_si"
1949 [(set (match_operand:SI 0 "register_operand" "=d")
1950 (compare:SI (reg:CCS 33) (const_int 0)))]
1954 output_asm_insn (\"lhi\\t%0,1\", operands);
1955 output_asm_insn (\"jh\\t.+12\", operands);
1956 output_asm_insn (\"jl\\t.+6\", operands);
1957 output_asm_insn (\"sr\\t%0,%0\", operands);
1958 return \"lcr\\t%0,%0\";
1960 [(set_attr "op_type" "NN")
1961 (set_attr "length" "16")
1962 (set_attr "atype" "reg")
1963 (set_attr "type" "other")])
1965 (define_insn "cmpint_di"
1966 [(set (match_operand:DI 0 "register_operand" "=d")
1967 (compare:DI (reg:CCS 33) (const_int 0)))]
1971 output_asm_insn (\"lghi\\t%0,1\", operands);
1972 output_asm_insn (\"jh\\t.+12\", operands);
1973 output_asm_insn (\"jl\\t.+6\", operands);
1974 output_asm_insn (\"sgr\\t%0,%0\", operands);
1975 return \"lcgr\\t%0,%0\";
1977 [(set_attr "op_type" "NN")
1978 (set_attr "length" "22")
1979 (set_attr "atype" "reg")
1980 (set_attr "type" "other")])
1984 ;;- Conversion instructions.
1987 (define_insn "*sethighqisi"
1988 [(set (match_operand:SI 0 "register_operand" "=d")
1989 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1990 (clobber (reg:CC 33))]
1993 [(set_attr "op_type" "RS")
1994 (set_attr "atype" "mem")])
1996 (define_insn "*sethighhisi"
1997 [(set (match_operand:SI 0 "register_operand" "=d")
1998 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1999 (clobber (reg:CC 33))]
2002 [(set_attr "op_type" "RS")
2003 (set_attr "atype" "mem")])
2005 (define_insn "*sethighqidi_64"
2006 [(set (match_operand:DI 0 "register_operand" "=d")
2007 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2008 (clobber (reg:CC 33))]
2011 [(set_attr "op_type" "RSE")
2012 (set_attr "atype" "mem")])
2014 (define_insn "*sethighqidi_31"
2015 [(set (match_operand:DI 0 "register_operand" "=d")
2016 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2017 (clobber (reg:CC 33))]
2020 [(set_attr "op_type" "RS")
2021 (set_attr "atype" "mem")])
2023 (define_insn_and_split "*extractqi"
2024 [(set (match_operand:SI 0 "register_operand" "=d")
2025 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2026 (match_operand 2 "const_int_operand" "n")
2028 (clobber (reg:CC 33))]
2030 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2032 "&& reload_completed"
2034 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2035 (clobber (reg:CC 33))])
2036 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2039 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2040 operands[1] = change_address (operands[1], QImode, 0);
2042 [(set_attr "type" "o2")
2043 (set_attr "atype" "mem")])
2045 (define_insn_and_split "*extracthi"
2046 [(set (match_operand:SI 0 "register_operand" "=d")
2047 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2048 (match_operand 2 "const_int_operand" "n")
2050 (clobber (reg:CC 33))]
2052 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2054 "&& reload_completed"
2056 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2057 (clobber (reg:CC 33))])
2058 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2061 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2062 operands[1] = change_address (operands[1], HImode, 0);
2064 [(set_attr "type" "o2")
2065 (set_attr "atype" "mem")])
2068 ; extendsidi2 instruction pattern(s).
2071 (define_expand "extendsidi2"
2072 [(set (match_operand:DI 0 "register_operand" "")
2073 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2079 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2080 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2081 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2082 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2088 (define_insn "*extendsidi2"
2089 [(set (match_operand:DI 0 "register_operand" "=d,d")
2090 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2095 [(set_attr "op_type" "RRE,RXE")
2096 (set_attr "atype" "reg,mem")])
2099 ; extendhidi2 instruction pattern(s).
2102 (define_expand "extendhidi2"
2103 [(set (match_operand:DI 0 "register_operand" "")
2104 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2110 rtx tmp = gen_reg_rtx (SImode);
2111 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2112 emit_insn (gen_extendsidi2 (operands[0], tmp));
2117 operands[1] = gen_lowpart (DImode, operands[1]);
2118 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2119 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2125 (define_insn "*extendhidi2"
2126 [(set (match_operand:DI 0 "register_operand" "=d")
2127 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2130 [(set_attr "op_type" "RXE")
2131 (set_attr "atype" "mem")])
2134 ; extendqidi2 instruction pattern(s).
2137 (define_expand "extendqidi2"
2138 [(set (match_operand:DI 0 "register_operand" "")
2139 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2145 rtx tmp = gen_reg_rtx (SImode);
2146 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2147 emit_insn (gen_extendsidi2 (operands[0], tmp));
2152 operands[1] = gen_lowpart (DImode, operands[1]);
2153 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2154 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2161 [(set (match_operand:DI 0 "register_operand" "")
2162 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2163 "TARGET_64BIT && !reload_completed"
2165 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2166 (clobber (reg:CC 33))])
2168 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2169 (clobber (reg:CC 33))])]
2173 ; extendhisi2 instruction pattern(s).
2176 (define_expand "extendhisi2"
2177 [(set (match_operand:SI 0 "register_operand" "")
2178 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2182 operands[1] = gen_lowpart (SImode, operands[1]);
2183 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2184 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2189 (define_insn "*extendhisi2"
2190 [(set (match_operand:SI 0 "register_operand" "=d")
2191 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2194 [(set_attr "op_type" "RX")
2195 (set_attr "atype" "mem")])
2198 ; extendqisi2 instruction pattern(s).
2201 (define_expand "extendqisi2"
2202 [(set (match_operand:SI 0 "register_operand" "")
2203 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2207 operands[1] = gen_lowpart (SImode, operands[1]);
2208 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2209 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2215 [(set (match_operand:SI 0 "register_operand" "")
2216 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2219 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2220 (clobber (reg:CC 33))])
2222 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2223 (clobber (reg:CC 33))])]
2227 ; extendqihi2 instruction pattern(s).
2232 ; zero_extendsidi2 instruction pattern(s).
2235 (define_expand "zero_extendsidi2"
2236 [(set (match_operand:DI 0 "register_operand" "")
2237 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2243 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2244 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2245 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2251 (define_insn "*zero_extendsidi2"
2252 [(set (match_operand:DI 0 "register_operand" "=d,d")
2253 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2258 [(set_attr "op_type" "RRE,RXE")
2259 (set_attr "atype" "reg,mem")])
2262 ; zero_extendhidi2 instruction pattern(s).
2265 (define_expand "zero_extendhidi2"
2266 [(set (match_operand:DI 0 "register_operand" "")
2267 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2273 rtx tmp = gen_reg_rtx (SImode);
2274 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2275 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2280 operands[1] = gen_lowpart (DImode, operands[1]);
2281 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2282 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2288 (define_insn "*zero_extendhidi2"
2289 [(set (match_operand:DI 0 "register_operand" "=d")
2290 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2293 [(set_attr "op_type" "RXE")
2294 (set_attr "atype" "mem")])
2297 ; zero_extendqidi2 instruction pattern(s)
2300 (define_expand "zero_extendqidi2"
2301 [(set (match_operand:DI 0 "register_operand" "")
2302 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2308 rtx tmp = gen_reg_rtx (SImode);
2309 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2310 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2315 operands[1] = gen_lowpart (DImode, operands[1]);
2316 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2317 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2323 (define_insn "*zero_extendqidi2"
2324 [(set (match_operand:DI 0 "register_operand" "=d")
2325 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2328 [(set_attr "op_type" "RXE")
2329 (set_attr "atype" "mem")])
2332 ; zero_extendhisi2 instruction pattern(s).
2335 (define_expand "zero_extendhisi2"
2336 [(set (match_operand:SI 0 "register_operand" "")
2337 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2341 operands[1] = gen_lowpart (SImode, operands[1]);
2342 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2347 (define_insn "*zero_extendhisi2_64"
2348 [(set (match_operand:SI 0 "register_operand" "=d")
2349 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2352 [(set_attr "op_type" "RXE")
2353 (set_attr "atype" "mem")])
2355 (define_insn_and_split "*zero_extendhisi2_31"
2356 [(set (match_operand:SI 0 "register_operand" "=&d")
2357 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2358 (clobber (reg:CC 33))]
2361 "&& reload_completed"
2362 [(set (match_dup 0) (const_int 0))
2364 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2365 (clobber (reg:CC 33))])]
2366 "operands[2] = gen_lowpart (HImode, operands[0]);"
2367 [(set_attr "type" "o2")
2368 (set_attr "atype" "mem")])
2371 ; zero_extendqisi2 instruction pattern(s).
2374 (define_expand "zero_extendqisi2"
2375 [(set (match_operand:SI 0 "register_operand" "")
2376 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2380 operands[1] = gen_lowpart (SImode, operands[1]);
2381 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2386 (define_insn "*zero_extendqisi2_64"
2387 [(set (match_operand:SI 0 "register_operand" "=d")
2388 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2391 [(set_attr "op_type" "RXE")
2392 (set_attr "atype" "mem")])
2394 (define_insn_and_split "*zero_extendqisi2_31"
2395 [(set (match_operand:SI 0 "register_operand" "=&d")
2396 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2399 "&& reload_completed"
2400 [(set (match_dup 0) (const_int 0))
2401 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2402 "operands[2] = gen_lowpart (QImode, operands[0]);"
2403 [(set_attr "type" "o2")
2404 (set_attr "atype" "mem")])
2407 ; zero_extendqihi2 instruction pattern(s).
2410 (define_expand "zero_extendqihi2"
2411 [(set (match_operand:HI 0 "register_operand" "")
2412 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2416 operands[1] = gen_lowpart (HImode, operands[1]);
2417 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2422 (define_insn "*zero_extendqihi2_64"
2423 [(set (match_operand:HI 0 "register_operand" "=d")
2424 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2427 [(set_attr "op_type" "RXE")
2428 (set_attr "atype" "mem")])
2430 (define_insn_and_split "*zero_extendqihi2_31"
2431 [(set (match_operand:HI 0 "register_operand" "=&d")
2432 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2435 "&& reload_completed"
2436 [(set (match_dup 0) (const_int 0))
2437 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2438 "operands[2] = gen_lowpart (QImode, operands[0]);"
2439 [(set_attr "type" "o2")
2440 (set_attr "atype" "mem")])
2444 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2447 (define_expand "fixuns_truncdfdi2"
2448 [(set (match_operand:DI 0 "register_operand" "")
2449 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2450 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2453 rtx label1 = gen_label_rtx ();
2454 rtx label2 = gen_label_rtx ();
2455 rtx temp = gen_reg_rtx (DFmode);
2456 operands[1] = force_reg (DFmode, operands[1]);
2458 emit_insn (gen_cmpdf (operands[1],
2459 CONST_DOUBLE_FROM_REAL_VALUE (
2460 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2461 emit_jump_insn (gen_blt (label1));
2462 emit_insn (gen_subdf3 (temp, operands[1],
2463 CONST_DOUBLE_FROM_REAL_VALUE (
2464 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2465 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2468 emit_label (label1);
2469 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2470 emit_label (label2);
2474 (define_expand "fix_truncdfdi2"
2475 [(set (match_operand:DI 0 "register_operand" "")
2476 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2477 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2480 operands[1] = force_reg (DFmode, operands[1]);
2481 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2485 (define_insn "fix_truncdfdi2_ieee"
2486 [(set (match_operand:DI 0 "register_operand" "=d")
2487 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2488 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2489 (clobber (reg:CC 33))]
2490 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2492 [(set_attr "op_type" "RRE")
2493 (set_attr "type" "other")])
2496 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2499 (define_expand "fixuns_truncdfsi2"
2500 [(set (match_operand:SI 0 "register_operand" "")
2501 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2502 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2505 rtx label1 = gen_label_rtx ();
2506 rtx label2 = gen_label_rtx ();
2507 rtx temp = gen_reg_rtx (DFmode);
2509 operands[1] = force_reg (DFmode,operands[1]);
2510 emit_insn (gen_cmpdf (operands[1],
2511 CONST_DOUBLE_FROM_REAL_VALUE (
2512 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2513 emit_jump_insn (gen_blt (label1));
2514 emit_insn (gen_subdf3 (temp, operands[1],
2515 CONST_DOUBLE_FROM_REAL_VALUE (
2516 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2517 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2520 emit_label (label1);
2521 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2522 emit_label (label2);
2526 (define_expand "fix_truncdfsi2"
2527 [(set (match_operand:SI 0 "register_operand" "")
2528 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2532 if (TARGET_IBM_FLOAT)
2534 /* This is the algorithm from POP chapter A.5.7.2. */
2536 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2537 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2538 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2540 operands[1] = force_reg (DFmode, operands[1]);
2541 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2542 two31r, two32, temp));
2546 operands[1] = force_reg (DFmode, operands[1]);
2547 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2553 (define_insn "fix_truncdfsi2_ieee"
2554 [(set (match_operand:SI 0 "register_operand" "=d")
2555 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2556 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2557 (clobber (reg:CC 33))]
2558 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2560 [(set_attr "op_type" "RRE")
2561 (set_attr "type" "other" )])
2563 (define_insn "fix_truncdfsi2_ibm"
2564 [(set (match_operand:SI 0 "register_operand" "=d")
2565 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2566 (use (match_operand:DI 2 "immediate_operand" "m"))
2567 (use (match_operand:DI 3 "immediate_operand" "m"))
2568 (use (match_operand:BLK 4 "memory_operand" "m"))
2569 (clobber (reg:CC 33))]
2570 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2573 output_asm_insn (\"sd\\t%1,%2\", operands);
2574 output_asm_insn (\"aw\\t%1,%3\", operands);
2575 output_asm_insn (\"std\\t%1,%4\", operands);
2576 output_asm_insn (\"xi\\t%N4,128\", operands);
2577 return \"l\\t%0,%N4\";
2579 [(set_attr "op_type" "NN")
2580 (set_attr "type" "other")
2581 (set_attr "length" "20")])
2584 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2587 (define_expand "fixuns_truncsfdi2"
2588 [(set (match_operand:DI 0 "register_operand" "")
2589 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2590 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2593 rtx label1 = gen_label_rtx ();
2594 rtx label2 = gen_label_rtx ();
2595 rtx temp = gen_reg_rtx (SFmode);
2597 operands[1] = force_reg (SFmode, operands[1]);
2598 emit_insn (gen_cmpsf (operands[1],
2599 CONST_DOUBLE_FROM_REAL_VALUE (
2600 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2601 emit_jump_insn (gen_blt (label1));
2603 emit_insn (gen_subsf3 (temp, operands[1],
2604 CONST_DOUBLE_FROM_REAL_VALUE (
2605 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2606 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2609 emit_label (label1);
2610 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2611 emit_label (label2);
2615 (define_expand "fix_truncsfdi2"
2616 [(set (match_operand:DI 0 "register_operand" "")
2617 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2618 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2621 operands[1] = force_reg (SFmode, operands[1]);
2622 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2626 (define_insn "fix_truncsfdi2_ieee"
2627 [(set (match_operand:DI 0 "register_operand" "=d")
2628 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2629 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2630 (clobber (reg:CC 33))]
2631 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2633 [(set_attr "op_type" "RRE")
2634 (set_attr "type" "other")])
2637 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2640 (define_expand "fixuns_truncsfsi2"
2641 [(set (match_operand:SI 0 "register_operand" "")
2642 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2643 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2646 rtx label1 = gen_label_rtx ();
2647 rtx label2 = gen_label_rtx ();
2648 rtx temp = gen_reg_rtx (SFmode);
2650 operands[1] = force_reg (SFmode, operands[1]);
2651 emit_insn (gen_cmpsf (operands[1],
2652 CONST_DOUBLE_FROM_REAL_VALUE (
2653 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2654 emit_jump_insn (gen_blt (label1));
2655 emit_insn (gen_subsf3 (temp, operands[1],
2656 CONST_DOUBLE_FROM_REAL_VALUE (
2657 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2658 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2661 emit_label (label1);
2662 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2663 emit_label (label2);
2667 (define_expand "fix_truncsfsi2"
2668 [(set (match_operand:SI 0 "register_operand" "")
2669 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2673 if (TARGET_IBM_FLOAT)
2675 /* Convert to DFmode and then use the POP algorithm. */
2676 rtx temp = gen_reg_rtx (DFmode);
2677 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2678 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2682 operands[1] = force_reg (SFmode, operands[1]);
2683 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2689 (define_insn "fix_truncsfsi2_ieee"
2690 [(set (match_operand:SI 0 "register_operand" "=d")
2691 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2692 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2693 (clobber (reg:CC 33))]
2694 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2696 [(set_attr "op_type" "RRE")
2697 (set_attr "type" "other")])
2700 ; floatdidf2 instruction pattern(s).
2703 (define_insn "floatdidf2"
2704 [(set (match_operand:DF 0 "register_operand" "=f")
2705 (float:DF (match_operand:DI 1 "register_operand" "d")))
2706 (clobber (reg:CC 33))]
2707 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2709 [(set_attr "op_type" "RRE")
2710 (set_attr "type" "other" )])
2713 ; floatdisf2 instruction pattern(s).
2716 (define_insn "floatdisf2"
2717 [(set (match_operand:SF 0 "register_operand" "=f")
2718 (float:SF (match_operand:DI 1 "register_operand" "d")))
2719 (clobber (reg:CC 33))]
2720 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2722 [(set_attr "op_type" "RRE")
2723 (set_attr "type" "other" )])
2726 ; floatsidf2 instruction pattern(s).
2729 (define_expand "floatsidf2"
2731 [(set (match_operand:DF 0 "register_operand" "")
2732 (float:DF (match_operand:SI 1 "register_operand" "")))
2733 (clobber (reg:CC 33))])]
2737 if (TARGET_IBM_FLOAT)
2739 /* This is the algorithm from POP chapter A.5.7.1. */
2741 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2742 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2744 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2749 (define_insn "floatsidf2_ieee"
2750 [(set (match_operand:DF 0 "register_operand" "=f")
2751 (float:DF (match_operand:SI 1 "register_operand" "d")))
2752 (clobber (reg:CC 33))]
2753 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2755 [(set_attr "op_type" "RRE")
2756 (set_attr "type" "other" )])
2758 (define_insn "floatsidf2_ibm"
2759 [(set (match_operand:DF 0 "register_operand" "=f")
2760 (float:DF (match_operand:SI 1 "register_operand" "d")))
2761 (use (match_operand:DI 2 "immediate_operand" "m"))
2762 (use (match_operand:BLK 3 "memory_operand" "m"))
2763 (clobber (reg:CC 33))]
2764 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2767 output_asm_insn (\"st\\t%1,%N3\", operands);
2768 output_asm_insn (\"xi\\t%N3,128\", operands);
2769 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2770 output_asm_insn (\"ld\\t%0,%3\", operands);
2771 return \"sd\\t%0,%2\";
2773 [(set_attr "op_type" "NN")
2774 (set_attr "type" "other" )
2775 (set_attr "length" "20")])
2778 ; floatsisf2 instruction pattern(s).
2781 (define_expand "floatsisf2"
2783 [(set (match_operand:SF 0 "register_operand" "")
2784 (float:SF (match_operand:SI 1 "register_operand" "")))
2785 (clobber (reg:CC 33))])]
2789 if (TARGET_IBM_FLOAT)
2791 /* Use the POP algorithm to convert to DFmode and then truncate. */
2792 rtx temp = gen_reg_rtx (DFmode);
2793 emit_insn (gen_floatsidf2 (temp, operands[1]));
2794 emit_insn (gen_truncdfsf2 (operands[0], temp));
2799 (define_insn "floatsisf2_ieee"
2800 [(set (match_operand:SF 0 "register_operand" "=f")
2801 (float:SF (match_operand:SI 1 "register_operand" "d")))
2802 (clobber (reg:CC 33))]
2803 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2805 [(set_attr "op_type" "RRE")
2806 (set_attr "type" "other" )])
2809 ; truncdfsf2 instruction pattern(s).
2812 (define_expand "truncdfsf2"
2813 [(set (match_operand:SF 0 "register_operand" "")
2814 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2818 (define_insn "truncdfsf2_ieee"
2819 [(set (match_operand:SF 0 "register_operand" "=f")
2820 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2821 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2823 [(set_attr "op_type" "RRE")])
2825 (define_insn "truncdfsf2_ibm"
2826 [(set (match_operand:SF 0 "register_operand" "=f,f")
2827 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2828 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2832 [(set_attr "op_type" "RR,RX")
2833 (set_attr "atype" "reg,mem")])
2836 ; extendsfdf2 instruction pattern(s).
2839 (define_expand "extendsfdf2"
2840 [(set (match_operand:DF 0 "register_operand" "")
2841 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2845 if (TARGET_IBM_FLOAT)
2847 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2852 (define_insn "extendsfdf2_ieee"
2853 [(set (match_operand:DF 0 "register_operand" "=f,f")
2854 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2855 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2859 [(set_attr "op_type" "RRE,RXE")])
2861 (define_insn "extendsfdf2_ibm"
2862 [(set (match_operand:DF 0 "register_operand" "=f,f")
2863 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2864 (clobber (reg:CC 33))]
2865 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2867 sdr\\t%0,%0\;ler\\t%0,%1
2868 sdr\\t%0,%0\;le\\t%0,%1"
2869 [(set_attr "op_type" "RRE,RXE")
2870 (set_attr "atype" "reg,mem")
2871 (set_attr "type" "o2,o2")])
2875 ;; ARITHMETRIC OPERATIONS
2877 ; arithmetric operations set the ConditionCode,
2878 ; because of unpredictable Bits in Register for Halfword and Byte
2879 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2882 ;;- Add instructions.
2886 ; adddi3 instruction pattern(s).
2889 (define_insn "*la_64_cc"
2890 [(set (match_operand:DI 0 "register_operand" "=d")
2891 (match_operand:QI 1 "address_operand" "p"))
2892 (clobber (reg:CC 33))]
2894 && preferred_la_operand_p (operands[1], 1)"
2896 [(set_attr "op_type" "RX")
2897 (set_attr "atype" "mem")
2898 (set_attr "type" "la")])
2901 [(set (match_operand:DI 0 "register_operand" "")
2902 (match_operand:QI 1 "address_operand" ""))
2903 (clobber (reg:CC 33))]
2904 "TARGET_64BIT && reload_completed
2905 && preferred_la_operand_p (operands[1], 0)"
2906 [(set (match_dup 0) (match_dup 1))])
2908 (define_insn "*adddi3_sign"
2909 [(set (match_operand:DI 0 "register_operand" "=d,d")
2910 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2911 (match_operand:DI 1 "register_operand" "0,0")))
2912 (clobber (reg:CC 33))]
2917 [(set_attr "op_type" "RRE,RXE")
2918 (set_attr "atype" "reg,mem")])
2920 (define_insn "*adddi3_zero_cc"
2922 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2923 (match_operand:DI 1 "register_operand" "0,0"))
2925 (set (match_operand:DI 0 "register_operand" "=d,d")
2926 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2927 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2931 [(set_attr "op_type" "RRE,RXE")
2932 (set_attr "atype" "reg,mem")])
2934 (define_insn "*adddi3_zero_cconly"
2936 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2937 (match_operand:DI 1 "register_operand" "0,0"))
2939 (clobber (match_scratch:DI 0 "=d,d"))]
2940 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2944 [(set_attr "op_type" "RRE,RXE")
2945 (set_attr "atype" "reg,mem")])
2947 (define_insn "*adddi3_zero"
2948 [(set (match_operand:DI 0 "register_operand" "=d,d")
2949 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2950 (match_operand:DI 1 "register_operand" "0,0")))
2951 (clobber (reg:CC 33))]
2956 [(set_attr "op_type" "RRE,RXE")
2957 (set_attr "atype" "reg,mem")])
2959 (define_insn "*adddi3_imm_cc"
2961 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2962 (match_operand:DI 2 "const_int_operand" "K"))
2964 (set (match_operand:DI 0 "register_operand" "=d")
2965 (plus:DI (match_dup 1) (match_dup 2)))]
2967 && s390_match_ccmode (insn, CCAmode)
2968 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2970 [(set_attr "op_type" "RI")
2971 (set_attr "atype" "reg")])
2973 (define_insn "*adddi3_cc"
2975 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2976 (match_operand:DI 2 "general_operand" "d,m"))
2978 (set (match_operand:DI 0 "register_operand" "=d,d")
2979 (plus:DI (match_dup 1) (match_dup 2)))]
2980 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2984 [(set_attr "op_type" "RRE,RXE")
2985 (set_attr "atype" "reg,mem")])
2987 (define_insn "*adddi3_cconly"
2989 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2990 (match_operand:DI 2 "general_operand" "d,m"))
2992 (clobber (match_scratch:DI 0 "=d,d"))]
2993 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2997 [(set_attr "op_type" "RRE,RXE")
2998 (set_attr "atype" "reg,mem")])
3000 (define_insn "*adddi3_cconly2"
3002 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3003 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3004 (clobber (match_scratch:DI 0 "=d,d"))]
3005 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3009 [(set_attr "op_type" "RRE,RXE")
3010 (set_attr "atype" "reg,mem")])
3012 (define_insn "*adddi3_64"
3013 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3014 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3015 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3016 (clobber (reg:CC 33))]
3022 [(set_attr "op_type" "RRE,RI,RXE")
3023 (set_attr "atype" "reg,reg,mem")])
3025 (define_insn_and_split "*adddi3_31"
3026 [(set (match_operand:DI 0 "register_operand" "=&d")
3027 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3028 (match_operand:DI 2 "general_operand" "dm") ) )
3029 (clobber (reg:CC 33))]
3032 "&& reload_completed"
3034 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3035 (clobber (reg:CC 33))])
3038 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3040 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3042 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3044 (label_ref (match_dup 9))))
3046 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3047 (clobber (reg:CC 33))])
3049 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3050 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3051 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3052 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3053 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3054 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3055 operands[9] = gen_label_rtx ();"
3056 [(set_attr "op_type" "NN")
3057 (set_attr "type" "o3")])
3059 (define_expand "adddi3"
3061 [(set (match_operand:DI 0 "register_operand" "")
3062 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3063 (match_operand:DI 2 "general_operand" "")))
3064 (clobber (reg:CC 33))])]
3068 (define_insn "*la_64"
3069 [(set (match_operand:DI 0 "register_operand" "=d")
3070 (match_operand:QI 1 "address_operand" "p"))]
3073 [(set_attr "op_type" "RX")
3074 (set_attr "atype" "mem")
3075 (set_attr "type" "la")])
3077 (define_expand "reload_indi"
3078 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3079 (match_operand:DI 1 "s390_plus_operand" "")
3080 (match_operand:DI 2 "register_operand" "=&a")])]
3084 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3090 ; addsi3 instruction pattern(s).
3093 (define_insn "*la_31_cc"
3094 [(set (match_operand:SI 0 "register_operand" "=d")
3095 (match_operand:QI 1 "address_operand" "p"))
3096 (clobber (reg:CC 33))]
3098 && preferred_la_operand_p (operands[1], 1)"
3100 [(set_attr "op_type" "RX")
3101 (set_attr "atype" "mem")
3102 (set_attr "type" "la")])
3105 [(set (match_operand:SI 0 "register_operand" "")
3106 (match_operand:QI 1 "address_operand" ""))
3107 (clobber (reg:CC 33))]
3108 "!TARGET_64BIT && reload_completed
3109 && preferred_la_operand_p (operands[1], 0)"
3110 [(set (match_dup 0) (match_dup 1))])
3112 (define_insn "*addsi3_imm_cc"
3114 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3115 (match_operand:SI 2 "const_int_operand" "K"))
3117 (set (match_operand:SI 0 "register_operand" "=d")
3118 (plus:SI (match_dup 1) (match_dup 2)))]
3119 "s390_match_ccmode (insn, CCAmode)
3120 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3122 [(set_attr "op_type" "RI")
3123 (set_attr "atype" "reg")])
3125 (define_insn "*addsi3_carry1_cc"
3127 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3128 (match_operand:SI 2 "general_operand" "d,m"))
3130 (set (match_operand:SI 0 "register_operand" "=d,d")
3131 (plus:SI (match_dup 1) (match_dup 2)))]
3132 "s390_match_ccmode (insn, CCL1mode)"
3136 [(set_attr "op_type" "RR,RX")
3137 (set_attr "atype" "reg,mem")])
3139 (define_insn "*addsi3_carry1_cconly"
3141 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3142 (match_operand:SI 2 "general_operand" "d,m"))
3144 (clobber (match_scratch:SI 0 "=d,d"))]
3145 "s390_match_ccmode (insn, CCL1mode)"
3149 [(set_attr "op_type" "RR,RX")
3150 (set_attr "atype" "reg,mem")])
3152 (define_insn "*addsi3_carry2_cc"
3154 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3155 (match_operand:SI 2 "general_operand" "d,m"))
3157 (set (match_operand:SI 0 "register_operand" "=d,d")
3158 (plus:SI (match_dup 1) (match_dup 2)))]
3159 "s390_match_ccmode (insn, CCL1mode)"
3163 [(set_attr "op_type" "RR,RX")
3164 (set_attr "atype" "reg,mem")])
3166 (define_insn "*addsi3_carry2_cconly"
3168 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3169 (match_operand:SI 2 "general_operand" "d,m"))
3171 (clobber (match_scratch:SI 0 "=d,d"))]
3172 "s390_match_ccmode (insn, CCL1mode)"
3176 [(set_attr "op_type" "RR,RX")
3177 (set_attr "atype" "reg,mem")])
3179 (define_insn "*addsi3_cc"
3181 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3182 (match_operand:SI 2 "general_operand" "d,m"))
3184 (set (match_operand:SI 0 "register_operand" "=d,d")
3185 (plus:SI (match_dup 1) (match_dup 2)))]
3186 "s390_match_ccmode (insn, CCLmode)"
3190 [(set_attr "op_type" "RR,RX")
3191 (set_attr "atype" "reg,mem")])
3193 (define_insn "*addsi3_cconly"
3195 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3196 (match_operand:SI 2 "general_operand" "d,m"))
3198 (clobber (match_scratch:SI 0 "=d,d"))]
3199 "s390_match_ccmode (insn, CCLmode)"
3203 [(set_attr "op_type" "RR,RX")
3204 (set_attr "atype" "reg,mem")])
3206 (define_insn "*addsi3_cconly2"
3208 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3209 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3210 (clobber (match_scratch:SI 0 "=d,d"))]
3211 "s390_match_ccmode(insn, CCLmode)"
3215 [(set_attr "op_type" "RR,RX")
3216 (set_attr "atype" "reg,mem")])
3218 (define_insn "*addsi3_sign"
3219 [(set (match_operand:SI 0 "register_operand" "=d")
3220 (plus:SI (match_operand:SI 1 "register_operand" "0")
3221 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3222 (clobber (reg:CC 33))]
3225 [(set_attr "op_type" "RX")
3226 (set_attr "atype" "mem")])
3228 (define_insn "*addsi3_sub"
3229 [(set (match_operand:SI 0 "register_operand" "=d")
3230 (plus:SI (match_operand:SI 1 "register_operand" "0")
3231 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3232 (clobber (reg:CC 33))]
3235 [(set_attr "op_type" "RX")
3236 (set_attr "atype" "mem")])
3238 (define_insn "addsi3"
3239 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3240 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3241 (match_operand:SI 2 "general_operand" "d,K,m")))
3242 (clobber (reg:CC 33))]
3248 [(set_attr "op_type" "RR,RI,RX")
3249 (set_attr "atype" "reg,reg,mem")])
3251 (define_insn "*la_31"
3252 [(set (match_operand:SI 0 "register_operand" "=d")
3253 (match_operand:QI 1 "address_operand" "p"))]
3254 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3256 [(set_attr "op_type" "RX")
3257 (set_attr "atype" "mem")
3258 (set_attr "type" "la")])
3260 (define_insn "*la_31_and"
3261 [(set (match_operand:SI 0 "register_operand" "=d")
3262 (and:SI (match_operand:QI 1 "address_operand" "p")
3263 (const_int 2147483647)))]
3266 [(set_attr "op_type" "RX")
3267 (set_attr "atype" "mem")
3268 (set_attr "type" "la")])
3270 (define_insn_and_split "*la_31_and_cc"
3271 [(set (match_operand:SI 0 "register_operand" "=d")
3272 (and:SI (match_operand:QI 1 "address_operand" "p")
3273 (const_int 2147483647)))
3274 (clobber (reg:CC 33))]
3277 "&& reload_completed"
3279 (and:SI (match_dup 1) (const_int 2147483647)))]
3281 [(set_attr "op_type" "RX")
3282 (set_attr "atype" "mem")
3283 (set_attr "type" "la")])
3285 (define_insn "force_la_31"
3286 [(set (match_operand:SI 0 "register_operand" "=d")
3287 (match_operand:QI 1 "address_operand" "p"))
3288 (use (const_int 0))]
3291 [(set_attr "op_type" "RX")
3292 (set_attr "atype" "mem")
3293 (set_attr "type" "la")])
3295 (define_expand "reload_insi"
3296 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3297 (match_operand:SI 1 "s390_plus_operand" "")
3298 (match_operand:SI 2 "register_operand" "=&a")])]
3302 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3308 ; adddf3 instruction pattern(s).
3311 (define_expand "adddf3"
3313 [(set (match_operand:DF 0 "register_operand" "=f,f")
3314 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3315 (match_operand:DF 2 "general_operand" "f,m")))
3316 (clobber (reg:CC 33))])]
3320 (define_insn "*adddf3"
3321 [(set (match_operand:DF 0 "register_operand" "=f,f")
3322 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3323 (match_operand:DF 2 "general_operand" "f,m")))
3324 (clobber (reg:CC 33))]
3325 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3329 [(set_attr "op_type" "RRE,RXE")
3330 (set_attr "atype" "reg,mem")])
3332 (define_insn "*adddf3_ibm"
3333 [(set (match_operand:DF 0 "register_operand" "=f,f")
3334 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3335 (match_operand:DF 2 "general_operand" "f,m")))
3336 (clobber (reg:CC 33))]
3337 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3341 [(set_attr "op_type" "RR,RX")
3342 (set_attr "atype" "reg,mem")])
3345 ; addsf3 instruction pattern(s).
3348 (define_expand "addsf3"
3350 [(set (match_operand:SF 0 "register_operand" "=f,f")
3351 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3352 (match_operand:SF 2 "general_operand" "f,m")))
3353 (clobber (reg:CC 33))])]
3357 (define_insn "*addsf3"
3358 [(set (match_operand:SF 0 "register_operand" "=f,f")
3359 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3360 (match_operand:SF 2 "general_operand" "f,m")))
3361 (clobber (reg:CC 33))]
3362 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3366 [(set_attr "op_type" "RRE,RXE")
3367 (set_attr "atype" "reg,mem")])
3369 (define_insn "*addsf3"
3370 [(set (match_operand:SF 0 "register_operand" "=f,f")
3371 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3372 (match_operand:SF 2 "general_operand" "f,m")))
3373 (clobber (reg:CC 33))]
3374 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3378 [(set_attr "op_type" "RR,RX")
3379 (set_attr "atype" "reg,mem")])
3383 ;;- Subtract instructions.
3387 ; subdi3 instruction pattern(s).
3390 (define_insn "*subdi3_sign"
3391 [(set (match_operand:DI 0 "register_operand" "=d,d")
3392 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3393 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3394 (clobber (reg:CC 33))]
3399 [(set_attr "op_type" "RRE,RXE")
3400 (set_attr "atype" "reg,mem")])
3402 (define_insn "*subdi3_zero_cc"
3404 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3405 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3407 (set (match_operand:DI 0 "register_operand" "=d,d")
3408 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3409 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3413 [(set_attr "op_type" "RRE,RXE")
3414 (set_attr "atype" "reg,mem")])
3416 (define_insn "*subdi3_zero_cconly"
3418 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3419 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3421 (clobber (match_scratch:DI 0 "=d,d"))]
3422 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3426 [(set_attr "op_type" "RRE,RXE")
3427 (set_attr "atype" "reg,mem")])
3429 (define_insn "*subdi3_zero"
3430 [(set (match_operand:DI 0 "register_operand" "=d,d")
3431 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3432 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3433 (clobber (reg:CC 33))]
3438 [(set_attr "op_type" "RRE,RXE")
3439 (set_attr "atype" "reg,mem")])
3441 (define_insn "*subdi3_cc"
3443 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3444 (match_operand:DI 2 "general_operand" "d,m"))
3446 (set (match_operand:DI 0 "register_operand" "=d,d")
3447 (minus:DI (match_dup 1) (match_dup 2)))]
3448 "s390_match_ccmode (insn, CCLmode)"
3452 [(set_attr "op_type" "RRE,RXE")
3453 (set_attr "atype" "reg,mem")])
3455 (define_insn "*subdi3_cconly"
3457 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3458 (match_operand:DI 2 "general_operand" "d,m"))
3460 (clobber (match_scratch:DI 0 "=d,d"))]
3461 "s390_match_ccmode (insn, CCLmode)"
3465 [(set_attr "op_type" "RRE,RXE")
3466 (set_attr "atype" "reg,mem")])
3468 (define_insn "*subdi3_64"
3469 [(set (match_operand:DI 0 "register_operand" "=d,d")
3470 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3471 (match_operand:DI 2 "general_operand" "d,m") ) )
3472 (clobber (reg:CC 33))]
3477 [(set_attr "op_type" "RRE,RRE")
3478 (set_attr "atype" "reg,mem")])
3480 (define_insn_and_split "*subdi3_31"
3481 [(set (match_operand:DI 0 "register_operand" "=&d")
3482 (minus:DI (match_operand:DI 1 "register_operand" "0")
3483 (match_operand:DI 2 "general_operand" "dm") ) )
3484 (clobber (reg:CC 33))]
3487 "&& reload_completed"
3489 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3490 (clobber (reg:CC 33))])
3493 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3495 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3497 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3499 (label_ref (match_dup 9))))
3501 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3502 (clobber (reg:CC 33))])
3504 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3505 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3506 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3507 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3508 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3509 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3510 operands[9] = gen_label_rtx ();"
3511 [(set_attr "op_type" "NN")
3512 (set_attr "type" "o3")])
3514 (define_expand "subdi3"
3516 [(set (match_operand:DI 0 "register_operand" "")
3517 (minus:DI (match_operand:DI 1 "register_operand" "")
3518 (match_operand:DI 2 "general_operand" "")))
3519 (clobber (reg:CC 33))])]
3524 ; subsi3 instruction pattern(s).
3527 (define_insn "*subsi3_borrow_cc"
3529 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3530 (match_operand:SI 2 "general_operand" "d,m"))
3532 (set (match_operand:SI 0 "register_operand" "=d,d")
3533 (minus:SI (match_dup 1) (match_dup 2)))]
3534 "s390_match_ccmode(insn, CCL2mode)"
3538 [(set_attr "op_type" "RR,RX")
3539 (set_attr "atype" "reg,mem")])
3541 (define_insn "*subsi3_borrow_cconly"
3543 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3544 (match_operand:SI 2 "general_operand" "d,m"))
3546 (clobber (match_scratch:SI 0 "=d,d"))]
3547 "s390_match_ccmode(insn, CCL2mode)"
3551 [(set_attr "op_type" "RR,RX")
3552 (set_attr "atype" "reg,mem")])
3554 (define_insn "*subsi3_cc"
3556 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3557 (match_operand:SI 2 "general_operand" "d,m"))
3559 (set (match_operand:SI 0 "register_operand" "=d,d")
3560 (minus:SI (match_dup 1) (match_dup 2)))]
3561 "s390_match_ccmode(insn, CCLmode)"
3565 [(set_attr "op_type" "RR,RX")
3566 (set_attr "atype" "reg,mem")])
3568 (define_insn "*subsi3_cconly"
3570 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3571 (match_operand:SI 2 "general_operand" "d,m"))
3573 (clobber (match_scratch:SI 0 "=d,d"))]
3574 "s390_match_ccmode(insn, CCLmode)"
3578 [(set_attr "op_type" "RR,RX")
3579 (set_attr "atype" "reg,mem")])
3581 (define_insn "*subsi3_sign"
3582 [(set (match_operand:SI 0 "register_operand" "=d")
3583 (minus:SI (match_operand:SI 1 "register_operand" "0")
3584 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3585 (clobber (reg:CC 33))]
3588 [(set_attr "op_type" "RX")
3589 (set_attr "atype" "mem")])
3591 (define_insn "*subsi3_sub"
3592 [(set (match_operand:SI 0 "register_operand" "=d")
3593 (minus:SI (match_operand:SI 1 "register_operand" "0")
3594 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3595 (clobber (reg:CC 33))]
3598 [(set_attr "op_type" "RX")
3599 (set_attr "atype" "mem")])
3601 (define_insn "subsi3"
3602 [(set (match_operand:SI 0 "register_operand" "=d,d")
3603 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3604 (match_operand:SI 2 "general_operand" "d,m")))
3605 (clobber (reg:CC 33))]
3610 [(set_attr "op_type" "RR,RX")
3611 (set_attr "atype" "reg,mem")])
3615 ; subdf3 instruction pattern(s).
3618 (define_expand "subdf3"
3620 [(set (match_operand:DF 0 "register_operand" "=f,f")
3621 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3622 (match_operand:DF 2 "general_operand" "f,m")))
3623 (clobber (reg:CC 33))])]
3627 (define_insn "*subdf3"
3628 [(set (match_operand:DF 0 "register_operand" "=f,f")
3629 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3630 (match_operand:DF 2 "general_operand" "f,m")))
3631 (clobber (reg:CC 33))]
3632 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3636 [(set_attr "op_type" "RRE,RXE")
3637 (set_attr "atype" "reg,mem")])
3639 (define_insn "*subdf3_ibm"
3640 [(set (match_operand:DF 0 "register_operand" "=f,f")
3641 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3642 (match_operand:DF 2 "general_operand" "f,m")))
3643 (clobber (reg:CC 33))]
3644 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3648 [(set_attr "op_type" "RR,RX")
3649 (set_attr "atype" "reg,mem")])
3652 ; subsf3 instruction pattern(s).
3655 (define_expand "subsf3"
3657 [(set (match_operand:SF 0 "register_operand" "=f,f")
3658 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3659 (match_operand:SF 2 "general_operand" "f,m")))
3660 (clobber (reg:CC 33))])]
3664 (define_insn "*subsf3"
3665 [(set (match_operand:SF 0 "register_operand" "=f,f")
3666 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3667 (match_operand:SF 2 "general_operand" "f,m")))
3668 (clobber (reg:CC 33))]
3669 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3673 [(set_attr "op_type" "RRE,RXE")
3674 (set_attr "atype" "reg,mem")])
3676 (define_insn "*subsf3_ibm"
3677 [(set (match_operand:SF 0 "register_operand" "=f,f")
3678 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3679 (match_operand:SF 2 "general_operand" "f,m")))
3680 (clobber (reg:CC 33))]
3681 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3685 [(set_attr "op_type" "RR,RX")
3686 (set_attr "atype" "reg,mem")])
3690 ;;- Multiply instructions.
3694 ; muldi3 instruction pattern(s).
3697 (define_insn "*muldi3_sign"
3698 [(set (match_operand:DI 0 "register_operand" "=d,d")
3699 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3700 (match_operand:DI 1 "register_operand" "0,0")))]
3705 [(set_attr "op_type" "RRE,RXE")
3706 (set_attr "atype" "reg,mem")
3707 (set_attr "type" "imul")])
3710 (define_insn "muldi3"
3711 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3712 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3713 (match_operand:DI 2 "general_operand" "d,K,m")))]
3719 [(set_attr "op_type" "RRE,RI,RXE")
3720 (set_attr "atype" "reg,reg,mem")
3721 (set_attr "type" "imul")])
3724 ; mulsi3 instruction pattern(s).
3727 (define_insn "mulsi3"
3728 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3729 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3730 (match_operand:SI 2 "general_operand" "d,K,m")))]
3736 [(set_attr "op_type" "RRE,RI,RX")
3737 (set_attr "atype" "reg,reg,mem")
3738 (set_attr "type" "imul")])
3741 ; mulsidi3 instruction pattern(s).
3744 (define_expand "mulsidi3"
3745 [(set (match_operand:DI 0 "register_operand" "")
3746 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3747 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3753 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3754 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3757 gen_rtx_EXPR_LIST (REG_EQUAL,
3758 gen_rtx_MULT (DImode,
3759 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3760 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3765 (define_insn "mulsi_6432"
3766 [(set (match_operand:DI 0 "register_operand" "=d,d")
3767 (mult:DI (sign_extend:DI
3768 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3770 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3775 [(set_attr "op_type" "RR,RX")
3776 (set_attr "atype" "reg,mem")
3777 (set_attr "type" "imul")])
3780 ; muldf3 instruction pattern(s).
3783 (define_expand "muldf3"
3785 [(set (match_operand:DF 0 "register_operand" "=f,f")
3786 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3787 (match_operand:DF 2 "general_operand" "f,m")))
3788 (clobber (reg:CC 33))])]
3792 (define_insn "*muldf3"
3793 [(set (match_operand:DF 0 "register_operand" "=f,f")
3794 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3795 (match_operand:DF 2 "general_operand" "f,m")))
3796 (clobber (reg:CC 33))]
3797 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3801 [(set_attr "op_type" "RRE,RXE")
3802 (set_attr "type" "fmul")
3803 (set_attr "atype" "reg,mem")])
3805 (define_insn "*muldf3_ibm"
3806 [(set (match_operand:DF 0 "register_operand" "=f,f")
3807 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3808 (match_operand:DF 2 "general_operand" "f,m")))
3809 (clobber (reg:CC 33))]
3810 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3814 [(set_attr "op_type" "RR,RX")
3815 (set_attr "type" "fmul")
3816 (set_attr "atype" "reg,mem")])
3819 ; mulsf3 instruction pattern(s).
3822 (define_expand "mulsf3"
3824 [(set (match_operand:SF 0 "register_operand" "=f,f")
3825 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3826 (match_operand:SF 2 "general_operand" "f,m")))
3827 (clobber (reg:CC 33))])]
3831 (define_insn "*mulsf3"
3832 [(set (match_operand:SF 0 "register_operand" "=f,f")
3833 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3834 (match_operand:SF 2 "general_operand" "f,m")))
3835 (clobber (reg:CC 33))]
3836 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3840 [(set_attr "op_type" "RRE,RXE")
3841 (set_attr "type" "fmul")
3842 (set_attr "atype" "reg,mem")])
3844 (define_insn "*mulsf3_ibm"
3845 [(set (match_operand:SF 0 "register_operand" "=f,f")
3846 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3847 (match_operand:SF 2 "general_operand" "f,m")))
3848 (clobber (reg:CC 33))]
3849 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3853 [(set_attr "op_type" "RR,RX")
3854 (set_attr "type" "fmul")
3855 (set_attr "atype" "reg,mem")])
3859 ;;- Divide and modulo instructions.
3863 ; divmoddi4 instruction pattern(s).
3866 (define_expand "divmoddi4"
3867 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3868 (div:DI (match_operand:DI 1 "general_operand" "")
3869 (match_operand:DI 2 "general_operand" "")))
3870 (set (match_operand:DI 3 "general_operand" "")
3871 (mod:DI (match_dup 1) (match_dup 2)))])
3872 (clobber (match_dup 4))]
3876 rtx insn, div_equal, mod_equal, equal;
3878 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3879 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3880 equal = gen_rtx_IOR (TImode,
3881 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3882 gen_rtx_ASHIFT (TImode,
3883 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3886 operands[4] = gen_reg_rtx(TImode);
3887 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3888 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3889 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3890 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3892 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3894 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3896 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3898 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3900 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3905 (define_insn "divmodtidi3"
3906 [(set (match_operand:TI 0 "register_operand" "=d,d")
3909 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3910 (match_operand:DI 2 "general_operand" "d,m")))
3913 (mod:DI (truncate:DI (match_dup 1))
3920 [(set_attr "op_type" "RRE,RXE")
3921 (set_attr "type" "idiv")
3922 (set_attr "atype" "reg,mem")])
3924 (define_insn "divmodtisi3"
3925 [(set (match_operand:TI 0 "register_operand" "=d,d")
3928 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3929 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3932 (mod:DI (truncate:DI (match_dup 1))
3933 (sign_extend:DI (match_dup 2))))
3939 [(set_attr "op_type" "RRE,RXE")
3940 (set_attr "type" "idiv")
3941 (set_attr "atype" "reg,mem")])
3944 ; udivmoddi4 instruction pattern(s).
3947 (define_expand "udivmoddi4"
3948 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3949 (udiv:DI (match_operand:DI 1 "general_operand" "")
3950 (match_operand:DI 2 "nonimmediate_operand" "")))
3951 (set (match_operand:DI 3 "general_operand" "")
3952 (umod:DI (match_dup 1) (match_dup 2)))])
3953 (clobber (match_dup 4))]
3957 rtx insn, div_equal, mod_equal, equal;
3959 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3960 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3961 equal = gen_rtx_IOR (TImode,
3962 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3963 gen_rtx_ASHIFT (TImode,
3964 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3967 operands[4] = gen_reg_rtx(TImode);
3968 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3969 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3970 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3971 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3973 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3975 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3977 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3979 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3981 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3986 (define_insn "udivmodtidi3"
3987 [(set (match_operand:TI 0 "register_operand" "=d,d")
3988 (ior:TI (zero_extend:TI
3990 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3992 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3996 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4002 [(set_attr "op_type" "RRE,RXE")
4003 (set_attr "type" "idiv")
4004 (set_attr "atype" "reg,mem")])
4007 ; divmodsi4 instruction pattern(s).
4010 (define_expand "divmodsi4"
4011 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4012 (div:SI (match_operand:SI 1 "general_operand" "")
4013 (match_operand:SI 2 "nonimmediate_operand" "")))
4014 (set (match_operand:SI 3 "general_operand" "")
4015 (mod:SI (match_dup 1) (match_dup 2)))])
4016 (clobber (match_dup 4))]
4020 rtx insn, div_equal, mod_equal, equal;
4022 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4023 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4024 equal = gen_rtx_IOR (DImode,
4025 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4026 gen_rtx_ASHIFT (DImode,
4027 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4030 operands[4] = gen_reg_rtx(DImode);
4031 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4032 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4034 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4036 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4038 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4040 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4042 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4047 (define_insn "divmoddisi3"
4048 [(set (match_operand:DI 0 "register_operand" "=d,d")
4049 (ior:DI (zero_extend:DI
4051 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4053 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4057 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4063 [(set_attr "op_type" "RR,RX")
4064 (set_attr "type" "idiv")
4065 (set_attr "atype" "reg,mem")])
4068 ; udivsi3 and umodsi3 instruction pattern(s).
4072 (define_expand "udivsi3"
4073 [(set (match_operand:SI 0 "register_operand" "=d")
4074 (udiv:SI (match_operand:SI 1 "general_operand" "")
4075 (match_operand:SI 2 "general_operand" "")))
4076 (clobber (match_dup 3))]
4080 rtx insn, udiv_equal, umod_equal, equal;
4082 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4083 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4084 equal = gen_rtx_IOR (DImode,
4085 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4086 gen_rtx_ASHIFT (DImode,
4087 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4090 operands[3] = gen_reg_rtx (DImode);
4092 if (CONSTANT_P (operands[2]))
4094 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4096 rtx label1 = gen_label_rtx ();
4098 operands[1] = make_safe_from (operands[1], operands[0]);
4099 emit_move_insn (operands[0], const0_rtx);
4100 emit_insn (gen_cmpsi (operands[1], operands[2]));
4101 emit_jump_insn (gen_bltu (label1));
4102 emit_move_insn (operands[0], const1_rtx);
4103 emit_label (label1);
4107 operands[2] = force_reg (SImode, operands[2]);
4108 operands[2] = make_safe_from (operands[2], operands[0]);
4110 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4111 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4114 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4116 insn = emit_move_insn (operands[0],
4117 gen_lowpart (SImode, operands[3]));
4119 gen_rtx_EXPR_LIST (REG_EQUAL,
4120 udiv_equal, REG_NOTES (insn));
4125 rtx label1 = gen_label_rtx ();
4126 rtx label2 = gen_label_rtx ();
4127 rtx label3 = gen_label_rtx ();
4129 operands[1] = force_reg (SImode, operands[1]);
4130 operands[1] = make_safe_from (operands[1], operands[0]);
4131 operands[2] = force_reg (SImode, operands[2]);
4132 operands[2] = make_safe_from (operands[2], operands[0]);
4134 emit_move_insn (operands[0], const0_rtx);
4135 emit_insn (gen_cmpsi (operands[2], operands[1]));
4136 emit_jump_insn (gen_bgtu (label3));
4137 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4138 emit_jump_insn (gen_blt (label2));
4139 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4140 emit_jump_insn (gen_beq (label1));
4141 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4142 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4145 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4147 insn = emit_move_insn (operands[0],
4148 gen_lowpart (SImode, operands[3]));
4150 gen_rtx_EXPR_LIST (REG_EQUAL,
4151 udiv_equal, REG_NOTES (insn));
4153 emit_label (label1);
4154 emit_move_insn (operands[0], operands[1]);
4156 emit_label (label2);
4157 emit_move_insn (operands[0], const1_rtx);
4158 emit_label (label3);
4160 emit_move_insn (operands[0], operands[0]);
4164 (define_expand "umodsi3"
4165 [(set (match_operand:SI 0 "register_operand" "=d")
4166 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4167 (match_operand:SI 2 "nonimmediate_operand" "")))
4168 (clobber (match_dup 3))]
4172 rtx insn, udiv_equal, umod_equal, equal;
4174 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4175 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4176 equal = gen_rtx_IOR (DImode,
4177 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4178 gen_rtx_ASHIFT (DImode,
4179 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4182 operands[3] = gen_reg_rtx (DImode);
4184 if (CONSTANT_P (operands[2]))
4186 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4188 rtx label1 = gen_label_rtx ();
4190 operands[1] = make_safe_from (operands[1], operands[0]);
4191 emit_move_insn (operands[0], operands[1]);
4192 emit_insn (gen_cmpsi (operands[0], operands[2]));
4193 emit_jump_insn (gen_bltu (label1));
4194 emit_insn (gen_abssi2 (operands[0], operands[2]));
4195 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4196 emit_label (label1);
4200 operands[2] = force_reg (SImode, operands[2]);
4201 operands[2] = make_safe_from (operands[2], operands[0]);
4203 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4204 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4207 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4209 insn = emit_move_insn (operands[0],
4210 gen_highpart (SImode, operands[3]));
4212 gen_rtx_EXPR_LIST (REG_EQUAL,
4213 umod_equal, REG_NOTES (insn));
4218 rtx label1 = gen_label_rtx ();
4219 rtx label2 = gen_label_rtx ();
4220 rtx label3 = gen_label_rtx ();
4222 operands[1] = force_reg (SImode, operands[1]);
4223 operands[1] = make_safe_from (operands[1], operands[0]);
4224 operands[2] = force_reg (SImode, operands[2]);
4225 operands[2] = make_safe_from (operands[2], operands[0]);
4227 emit_move_insn(operands[0], operands[1]);
4228 emit_insn (gen_cmpsi (operands[2], operands[1]));
4229 emit_jump_insn (gen_bgtu (label3));
4230 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4231 emit_jump_insn (gen_blt (label2));
4232 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4233 emit_jump_insn (gen_beq (label1));
4234 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4235 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4238 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4240 insn = emit_move_insn (operands[0],
4241 gen_highpart (SImode, operands[3]));
4243 gen_rtx_EXPR_LIST (REG_EQUAL,
4244 umod_equal, REG_NOTES (insn));
4246 emit_label (label1);
4247 emit_move_insn (operands[0], const0_rtx);
4249 emit_label (label2);
4250 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4251 emit_label (label3);
4257 ; divdf3 instruction pattern(s).
4260 (define_expand "divdf3"
4262 [(set (match_operand:DF 0 "register_operand" "=f,f")
4263 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4264 (match_operand:DF 2 "general_operand" "f,m")))
4265 (clobber (reg:CC 33))])]
4269 (define_insn "*divdf3"
4270 [(set (match_operand:DF 0 "register_operand" "=f,f")
4271 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4272 (match_operand:DF 2 "general_operand" "f,m")))
4273 (clobber (reg:CC 33))]
4274 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4278 [(set_attr "op_type" "RRE,RXE")
4279 (set_attr "type" "fdiv")
4280 (set_attr "atype" "reg,mem")])
4282 (define_insn "*divdf3_ibm"
4283 [(set (match_operand:DF 0 "register_operand" "=f,f")
4284 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4285 (match_operand:DF 2 "general_operand" "f,m")))
4286 (clobber (reg:CC 33))]
4287 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4291 [(set_attr "op_type" "RR,RX")
4292 (set_attr "type" "fdiv")
4293 (set_attr "atype" "reg,mem")])
4296 ; divsf3 instruction pattern(s).
4299 (define_expand "divsf3"
4301 [(set (match_operand:SF 0 "register_operand" "=f,f")
4302 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4303 (match_operand:SF 2 "general_operand" "f,m")))
4304 (clobber (reg:CC 33))])]
4308 (define_insn "*divsf3"
4309 [(set (match_operand:SF 0 "register_operand" "=f,f")
4310 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4311 (match_operand:SF 2 "general_operand" "f,m")))
4312 (clobber (reg:CC 33))]
4313 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4317 [(set_attr "op_type" "RRE,RXE")
4318 (set_attr "type" "fdiv")
4319 (set_attr "atype" "reg,mem")])
4321 (define_insn "*divsf3"
4322 [(set (match_operand:SF 0 "register_operand" "=f,f")
4323 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4324 (match_operand:SF 2 "general_operand" "f,m")))
4325 (clobber (reg:CC 33))]
4326 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4330 [(set_attr "op_type" "RR,RX")
4331 (set_attr "type" "fdiv")
4332 (set_attr "atype" "reg,mem")])
4336 ;;- And instructions.
4340 ; anddi3 instruction pattern(s).
4343 (define_insn "*anddi3_cc"
4345 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4346 (match_operand:DI 2 "general_operand" "d,m"))
4348 (set (match_operand:DI 0 "register_operand" "=d,d")
4349 (and:DI (match_dup 1) (match_dup 2)))]
4350 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4354 [(set_attr "op_type" "RRE,RXE")
4355 (set_attr "atype" "reg,mem")])
4357 (define_insn "*anddi3_cconly"
4359 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4360 (match_operand:DI 2 "general_operand" "d,m"))
4362 (clobber (match_scratch:DI 0 "=d,d"))]
4363 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4367 [(set_attr "op_type" "RRE,RXE")
4368 (set_attr "atype" "reg,mem")])
4370 (define_insn "*anddi3_ni"
4371 [(set (match_operand:DI 0 "register_operand" "=d")
4372 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4373 (match_operand:DI 2 "immediate_operand" "n")))
4374 (clobber (reg:CC 33))]
4375 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4378 int part = s390_single_hi (operands[2], DImode, -1);
4379 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4383 case 0: return \"nihh\\t%0,%x2\";
4384 case 1: return \"nihl\\t%0,%x2\";
4385 case 2: return \"nilh\\t%0,%x2\";
4386 case 3: return \"nill\\t%0,%x2\";
4390 [(set_attr "op_type" "RI")
4391 (set_attr "atype" "reg")])
4393 (define_insn "anddi3"
4394 [(set (match_operand:DI 0 "register_operand" "=d,d")
4395 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4396 (match_operand:DI 2 "general_operand" "d,m")))
4397 (clobber (reg:CC 33))]
4402 [(set_attr "op_type" "RRE,RXE")
4403 (set_attr "atype" "reg,mem")])
4405 (define_insn "*anddi3_ss"
4406 [(set (match_operand:DI 0 "s_operand" "=Q")
4407 (and:DI (match_dup 0)
4408 (match_operand:DI 1 "s_imm_operand" "Q")))
4409 (clobber (reg:CC 33))]
4411 "nc\\t%O0(8,%R0),%1"
4412 [(set_attr "op_type" "SS")
4413 (set_attr "atype" "mem")])
4415 (define_insn "*anddi3_ss_inv"
4416 [(set (match_operand:DI 0 "s_operand" "=Q")
4417 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4419 (clobber (reg:CC 33))]
4421 "nc\\t%O0(8,%R0),%1"
4422 [(set_attr "op_type" "SS")
4423 (set_attr "atype" "mem")])
4426 ; andsi3 instruction pattern(s).
4429 (define_insn "*andsi3_cc"
4431 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4432 (match_operand:SI 2 "general_operand" "d,m"))
4434 (set (match_operand:SI 0 "register_operand" "=d,d")
4435 (and:SI (match_dup 1) (match_dup 2)))]
4436 "s390_match_ccmode(insn, CCTmode)"
4440 [(set_attr "op_type" "RR,RX")
4441 (set_attr "atype" "reg,mem")])
4443 (define_insn "*andsi3_cconly"
4445 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4446 (match_operand:SI 2 "general_operand" "d,m"))
4448 (clobber (match_scratch:SI 0 "=d,d"))]
4449 "s390_match_ccmode(insn, CCTmode)"
4453 [(set_attr "op_type" "RR,RX")
4454 (set_attr "atype" "reg,mem")])
4456 (define_insn "*andsi3_ni"
4457 [(set (match_operand:SI 0 "register_operand" "=d")
4458 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4459 (match_operand:SI 2 "immediate_operand" "n")))
4460 (clobber (reg:CC 33))]
4461 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4464 int part = s390_single_hi (operands[2], SImode, -1);
4465 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4469 case 0: return \"nilh\\t%0,%x2\";
4470 case 1: return \"nill\\t%0,%x2\";
4474 [(set_attr "op_type" "RI")
4475 (set_attr "atype" "reg")])
4477 (define_insn "andsi3"
4478 [(set (match_operand:SI 0 "register_operand" "=d,d")
4479 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4480 (match_operand:SI 2 "general_operand" "d,m")))
4481 (clobber (reg:CC 33))]
4486 [(set_attr "op_type" "RR,RX")
4487 (set_attr "atype" "reg,mem")])
4489 (define_insn "*andsi3_ss"
4490 [(set (match_operand:SI 0 "s_operand" "=Q")
4491 (and:SI (match_dup 0)
4492 (match_operand:SI 1 "s_imm_operand" "Q")))
4493 (clobber (reg:CC 33))]
4495 "nc\\t%O0(4,%R0),%1"
4496 [(set_attr "op_type" "SS")
4497 (set_attr "atype" "mem")])
4499 (define_insn "*andsi3_ss_inv"
4500 [(set (match_operand:SI 0 "s_operand" "=Q")
4501 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4503 (clobber (reg:CC 33))]
4505 "nc\\t%O0(4,%R0),%1"
4506 [(set_attr "op_type" "SS")
4507 (set_attr "atype" "mem")])
4510 ; andhi3 instruction pattern(s).
4513 (define_insn "*andhi3_ni"
4514 [(set (match_operand:HI 0 "register_operand" "=d,d")
4515 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4516 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4517 (clobber (reg:CC 33))]
4522 [(set_attr "op_type" "RR,RI")
4523 (set_attr "atype" "reg")])
4525 (define_insn "andhi3"
4526 [(set (match_operand:HI 0 "register_operand" "=d")
4527 (and:HI (match_operand:HI 1 "register_operand" "%0")
4528 (match_operand:HI 2 "nonmemory_operand" "d")))
4529 (clobber (reg:CC 33))]
4532 [(set_attr "op_type" "RR")
4533 (set_attr "atype" "reg")])
4535 (define_insn "*andhi3_ss"
4536 [(set (match_operand:HI 0 "s_operand" "=Q")
4537 (and:HI (match_dup 0)
4538 (match_operand:HI 1 "s_imm_operand" "Q")))
4539 (clobber (reg:CC 33))]
4541 "nc\\t%O0(2,%R0),%1"
4542 [(set_attr "op_type" "SS")
4543 (set_attr "atype" "mem")])
4545 (define_insn "*andhi3_ss_inv"
4546 [(set (match_operand:HI 0 "s_operand" "=Q")
4547 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4549 (clobber (reg:CC 33))]
4551 "nc\\t%O0(2,%R0),%1"
4552 [(set_attr "op_type" "SS")
4553 (set_attr "atype" "mem")])
4556 ; andqi3 instruction pattern(s).
4559 (define_insn "*andqi3_ni"
4560 [(set (match_operand:QI 0 "register_operand" "=d,d")
4561 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4562 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4563 (clobber (reg:CC 33))]
4568 [(set_attr "op_type" "RR,RI")
4569 (set_attr "atype" "reg")])
4571 (define_insn "andqi3"
4572 [(set (match_operand:QI 0 "register_operand" "=d")
4573 (and:QI (match_operand:QI 1 "register_operand" "%0")
4574 (match_operand:QI 2 "nonmemory_operand" "d")))
4575 (clobber (reg:CC 33))]
4578 [(set_attr "op_type" "RR")
4579 (set_attr "atype" "reg")])
4581 (define_insn "*andqi3_ss"
4582 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4583 (and:QI (match_dup 0)
4584 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4585 (clobber (reg:CC 33))]
4590 [(set_attr "op_type" "SI,SS")
4591 (set_attr "atype" "mem")])
4593 (define_insn "*andqi3_ss_inv"
4594 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4595 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4597 (clobber (reg:CC 33))]
4602 [(set_attr "op_type" "SI,SS")
4603 (set_attr "atype" "mem")])
4607 ;;- Bit set (inclusive or) instructions.
4611 ; iordi3 instruction pattern(s).
4614 (define_insn "*iordi3_cc"
4616 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4617 (match_operand:DI 2 "general_operand" "d,m"))
4619 (set (match_operand:DI 0 "register_operand" "=d,d")
4620 (ior:DI (match_dup 1) (match_dup 2)))]
4621 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4625 [(set_attr "op_type" "RRE,RXE")
4626 (set_attr "atype" "reg,mem")])
4628 (define_insn "*iordi3_cconly"
4630 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4631 (match_operand:DI 2 "general_operand" "d,m"))
4633 (clobber (match_scratch:DI 0 "=d,d"))]
4634 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4638 [(set_attr "op_type" "RRE,RXE")
4639 (set_attr "atype" "reg,mem")])
4641 (define_insn "*iordi3_oi"
4642 [(set (match_operand:DI 0 "register_operand" "=d")
4643 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4644 (match_operand:DI 2 "immediate_operand" "n")))
4645 (clobber (reg:CC 33))]
4646 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4649 int part = s390_single_hi (operands[2], DImode, 0);
4650 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4654 case 0: return \"oihh\\t%0,%x2\";
4655 case 1: return \"oihl\\t%0,%x2\";
4656 case 2: return \"oilh\\t%0,%x2\";
4657 case 3: return \"oill\\t%0,%x2\";
4661 [(set_attr "op_type" "RI")
4662 (set_attr "atype" "reg")])
4664 (define_insn "iordi3"
4665 [(set (match_operand:DI 0 "register_operand" "=d,d")
4666 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4667 (match_operand:DI 2 "general_operand" "d,m")))
4668 (clobber (reg:CC 33))]
4673 [(set_attr "op_type" "RRE,RXE")
4674 (set_attr "atype" "reg,mem")])
4676 (define_insn "*iordi3_ss"
4677 [(set (match_operand:DI 0 "s_operand" "=Q")
4678 (ior:DI (match_dup 0)
4679 (match_operand:DI 1 "s_imm_operand" "Q")))
4680 (clobber (reg:CC 33))]
4682 "oc\\t%O0(8,%R0),%1"
4683 [(set_attr "op_type" "SS")
4684 (set_attr "atype" "mem")])
4686 (define_insn "*iordi3_ss_inv"
4687 [(set (match_operand:DI 0 "s_operand" "=Q")
4688 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4690 (clobber (reg:CC 33))]
4692 "oc\\t%O0(8,%R0),%1"
4693 [(set_attr "op_type" "SS")
4694 (set_attr "atype" "mem")])
4697 ; iorsi3 instruction pattern(s).
4700 (define_insn "*iorsi3_cc"
4702 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4703 (match_operand:SI 2 "general_operand" "d,m"))
4705 (set (match_operand:SI 0 "register_operand" "=d,d")
4706 (ior:SI (match_dup 1) (match_dup 2)))]
4707 "s390_match_ccmode(insn, CCTmode)"
4711 [(set_attr "op_type" "RR,RX")
4712 (set_attr "atype" "reg,mem")])
4714 (define_insn "*iorsi3_cconly"
4716 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4717 (match_operand:SI 2 "general_operand" "d,m"))
4719 (clobber (match_scratch:SI 0 "=d,d"))]
4720 "s390_match_ccmode(insn, CCTmode)"
4724 [(set_attr "op_type" "RR,RX")
4725 (set_attr "atype" "reg,mem")])
4727 (define_insn "*iorsi3_oi"
4728 [(set (match_operand:SI 0 "register_operand" "=d")
4729 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4730 (match_operand:SI 2 "immediate_operand" "n")))
4731 (clobber (reg:CC 33))]
4732 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4735 int part = s390_single_hi (operands[2], SImode, 0);
4736 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4740 case 0: return \"oilh\\t%0,%x2\";
4741 case 1: return \"oill\\t%0,%x2\";
4745 [(set_attr "op_type" "RI")
4746 (set_attr "atype" "reg")])
4748 (define_insn "iorsi3"
4749 [(set (match_operand:SI 0 "register_operand" "=d,d")
4750 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4751 (match_operand:SI 2 "general_operand" "d,m")))
4752 (clobber (reg:CC 33))]
4757 [(set_attr "op_type" "RR,RX")
4758 (set_attr "atype" "reg,mem")])
4760 (define_insn "*iorsi3_ss"
4761 [(set (match_operand:SI 0 "s_operand" "=Q")
4762 (ior:SI (match_dup 0)
4763 (match_operand:SI 1 "s_imm_operand" "Q")))
4764 (clobber (reg:CC 33))]
4766 "oc\\t%O0(4,%R0),%1"
4767 [(set_attr "op_type" "SS")
4768 (set_attr "atype" "mem")])
4770 (define_insn "*iorsi3_ss_inv"
4771 [(set (match_operand:SI 0 "s_operand" "=Q")
4772 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4774 (clobber (reg:CC 33))]
4776 "oc\\t%O0(4,%R0),%1"
4777 [(set_attr "op_type" "SS")
4778 (set_attr "atype" "mem")])
4781 ; iorhi3 instruction pattern(s).
4784 (define_insn "*iorhi3_oi"
4785 [(set (match_operand:HI 0 "register_operand" "=d,d")
4786 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4787 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4788 (clobber (reg:CC 33))]
4793 [(set_attr "op_type" "RR,RI")
4794 (set_attr "atype" "reg")])
4796 (define_insn "iorhi3"
4797 [(set (match_operand:HI 0 "register_operand" "=d")
4798 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4799 (match_operand:HI 2 "nonmemory_operand" "d")))
4800 (clobber (reg:CC 33))]
4803 [(set_attr "op_type" "RR")
4804 (set_attr "atype" "reg")])
4806 (define_insn "*iorhi3_ss"
4807 [(set (match_operand:HI 0 "s_operand" "=Q")
4808 (ior:HI (match_dup 0)
4809 (match_operand:HI 1 "s_imm_operand" "Q")))
4810 (clobber (reg:CC 33))]
4812 "oc\\t%O0(2,%R0),%1"
4813 [(set_attr "op_type" "SS")
4814 (set_attr "atype" "mem")])
4816 (define_insn "*iorhi3_ss_inv"
4817 [(set (match_operand:HI 0 "s_operand" "=Q")
4818 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4820 (clobber (reg:CC 33))]
4822 "oc\\t%O0(2,%R0),%1"
4823 [(set_attr "op_type" "SS")
4824 (set_attr "atype" "mem")])
4827 ; iorqi3 instruction pattern(s).
4830 (define_insn "*iorqi3_oi"
4831 [(set (match_operand:QI 0 "register_operand" "=d,d")
4832 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4833 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4834 (clobber (reg:CC 33))]
4839 [(set_attr "op_type" "RR,RI")
4840 (set_attr "atype" "reg")])
4842 (define_insn "iorqi3"
4843 [(set (match_operand:QI 0 "register_operand" "=d")
4844 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4845 (match_operand:QI 2 "nonmemory_operand" "d")))
4846 (clobber (reg:CC 33))]
4849 [(set_attr "op_type" "RR")
4850 (set_attr "atype" "reg")])
4852 (define_insn "*iorqi3_ss"
4853 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4854 (ior:QI (match_dup 0)
4855 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4856 (clobber (reg:CC 33))]
4861 [(set_attr "op_type" "SI,SS")
4862 (set_attr "atype" "reg,mem")])
4864 (define_insn "*iorqi3_ss_inv"
4865 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4866 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4868 (clobber (reg:CC 33))]
4873 [(set_attr "op_type" "SI,SS")
4874 (set_attr "atype" "reg,mem")])
4878 ;;- Xor instructions.
4882 ; xordi3 instruction pattern(s).
4885 (define_insn "*xordi3_cc"
4887 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4888 (match_operand:DI 2 "general_operand" "d,m"))
4890 (set (match_operand:DI 0 "register_operand" "=d,d")
4891 (xor:DI (match_dup 1) (match_dup 2)))]
4892 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4896 [(set_attr "op_type" "RRE,RXE")
4897 (set_attr "atype" "reg,mem")])
4899 (define_insn "*xordi3_cconly"
4901 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4902 (match_operand:DI 2 "general_operand" "d,m"))
4904 (clobber (match_scratch:DI 0 "=d,d"))]
4905 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4909 [(set_attr "op_type" "RRE,RXE")
4910 (set_attr "atype" "reg,mem")])
4912 (define_insn "xordi3"
4913 [(set (match_operand:DI 0 "register_operand" "=d,d")
4914 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4915 (match_operand:DI 2 "general_operand" "d,m")))
4916 (clobber (reg:CC 33))]
4921 [(set_attr "op_type" "RRE,RXE")
4922 (set_attr "atype" "reg,mem")])
4924 (define_insn "*xordi3_ss"
4925 [(set (match_operand:DI 0 "s_operand" "=Q")
4926 (xor:DI (match_dup 0)
4927 (match_operand:DI 1 "s_imm_operand" "Q")))
4928 (clobber (reg:CC 33))]
4930 "xc\\t%O0(8,%R0),%1"
4931 [(set_attr "op_type" "SS")
4932 (set_attr "atype" "mem")])
4934 (define_insn "*xordi3_ss_inv"
4935 [(set (match_operand:DI 0 "s_operand" "=Q")
4936 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4938 (clobber (reg:CC 33))]
4940 "xc\\t%O0(8,%R0),%1"
4941 [(set_attr "op_type" "SS")
4942 (set_attr "atype" "mem")])
4945 ; xorsi3 instruction pattern(s).
4948 (define_insn "*xorsi3_cc"
4950 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4951 (match_operand:SI 2 "general_operand" "d,m"))
4953 (set (match_operand:SI 0 "register_operand" "=d,d")
4954 (xor:SI (match_dup 1) (match_dup 2)))]
4955 "s390_match_ccmode(insn, CCTmode)"
4959 [(set_attr "op_type" "RR,RX")
4960 (set_attr "atype" "reg,mem")])
4962 (define_insn "*xorsi3_cconly"
4964 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4965 (match_operand:SI 2 "general_operand" "d,m"))
4967 (clobber (match_scratch:SI 0 "=d,d"))]
4968 "s390_match_ccmode(insn, CCTmode)"
4972 [(set_attr "op_type" "RR,RX")
4973 (set_attr "atype" "reg,mem")])
4975 (define_insn "xorsi3"
4976 [(set (match_operand:SI 0 "register_operand" "=d,d")
4977 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4978 (match_operand:SI 2 "general_operand" "d,m")))
4979 (clobber (reg:CC 33))]
4984 [(set_attr "op_type" "RR,RX")
4985 (set_attr "atype" "reg,mem")])
4987 (define_insn "*xorsi3_ss"
4988 [(set (match_operand:SI 0 "s_operand" "=Q")
4989 (xor:SI (match_dup 0)
4990 (match_operand:SI 1 "s_imm_operand" "Q")))
4991 (clobber (reg:CC 33))]
4993 "xc\\t%O0(4,%R0),%1"
4994 [(set_attr "op_type" "SS")
4995 (set_attr "atype" "mem")])
4997 (define_insn "*xorsi3_ss_inv"
4998 [(set (match_operand:SI 0 "s_operand" "=Q")
4999 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
5001 (clobber (reg:CC 33))]
5003 "xc\\t%O0(4,%R0),%1"
5004 [(set_attr "op_type" "SS")
5005 (set_attr "atype" "mem")])
5008 ; xorhi3 instruction pattern(s).
5011 (define_insn "xorhi3"
5012 [(set (match_operand:HI 0 "register_operand" "=d")
5013 (xor:HI (match_operand:HI 1 "register_operand" "%0")
5014 (match_operand:HI 2 "nonmemory_operand" "d")))
5015 (clobber (reg:CC 33))]
5018 [(set_attr "op_type" "RR")
5019 (set_attr "atype" "reg")])
5021 (define_insn "*xorhi3_ss"
5022 [(set (match_operand:HI 0 "s_operand" "=Q")
5023 (xor:HI (match_dup 0)
5024 (match_operand:HI 1 "s_imm_operand" "Q")))
5025 (clobber (reg:CC 33))]
5027 "xc\\t%O0(2,%R0),%1"
5028 [(set_attr "op_type" "SS")
5029 (set_attr "atype" "mem")])
5031 (define_insn "*xorhi3_ss_inv"
5032 [(set (match_operand:HI 0 "s_operand" "=Q")
5033 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
5035 (clobber (reg:CC 33))]
5037 "xc\\t%O0(2,%R0),%1"
5038 [(set_attr "op_type" "SS")
5039 (set_attr "atype" "mem")])
5042 ; xorqi3 instruction pattern(s).
5045 (define_insn "xorqi3"
5046 [(set (match_operand:QI 0 "register_operand" "=d")
5047 (xor:QI (match_operand:QI 1 "register_operand" "%0")
5048 (match_operand:QI 2 "nonmemory_operand" "d")))
5049 (clobber (reg:CC 33))]
5052 [(set_attr "op_type" "RR")
5053 (set_attr "atype" "reg")])
5055 (define_insn "*xorqi3_ss"
5056 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5057 (xor:QI (match_dup 0)
5058 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5059 (clobber (reg:CC 33))]
5064 [(set_attr "op_type" "SI,SS")
5065 (set_attr "atype" "mem")])
5067 (define_insn "*xorqi3_ss_inv"
5068 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5069 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5071 (clobber (reg:CC 33))]
5076 [(set_attr "op_type" "SI,SS")
5077 (set_attr "atype" "mem")])
5081 ;;- Negate instructions.
5085 ; negdi2 instruction pattern(s).
5088 (define_expand "negdi2"
5090 [(set (match_operand:DI 0 "register_operand" "=d")
5091 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5092 (clobber (reg:CC 33))])]
5096 (define_insn "*negdi2_64"
5097 [(set (match_operand:DI 0 "register_operand" "=d")
5098 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5099 (clobber (reg:CC 33))]
5102 [(set_attr "op_type" "RR")])
5104 (define_insn "*negdi2_31"
5105 [(set (match_operand:DI 0 "register_operand" "=d")
5106 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5107 (clobber (reg:CC 33))]
5112 xop[0] = gen_label_rtx ();
5113 output_asm_insn (\"lcr\\t%0,%1\", operands);
5114 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5115 output_asm_insn (\"je\\t%l0\", xop);
5116 output_asm_insn (\"bctr\\t%0,0\", operands);
5117 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5118 CODE_LABEL_NUMBER (xop[0]));
5121 [(set_attr "op_type" "NN")
5122 (set_attr "type" "other")
5123 (set_attr "length" "10")])
5126 ; negsi2 instruction pattern(s).
5129 (define_insn "negsi2"
5130 [(set (match_operand:SI 0 "register_operand" "=d")
5131 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5132 (clobber (reg:CC 33))]
5135 [(set_attr "op_type" "RR")])
5138 ; negdf2 instruction pattern(s).
5141 (define_expand "negdf2"
5143 [(set (match_operand:DF 0 "register_operand" "=f")
5144 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5145 (clobber (reg:CC 33))])]
5149 (define_insn "*negdf2"
5150 [(set (match_operand:DF 0 "register_operand" "=f")
5151 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5152 (clobber (reg:CC 33))]
5153 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5155 [(set_attr "op_type" "RRE")])
5157 (define_insn "*negdf2_ibm"
5158 [(set (match_operand:DF 0 "register_operand" "=f")
5159 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5160 (clobber (reg:CC 33))]
5161 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5163 [(set_attr "op_type" "RR")])
5166 ; negsf2 instruction pattern(s).
5169 (define_expand "negsf2"
5171 [(set (match_operand:SF 0 "register_operand" "=f")
5172 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5173 (clobber (reg:CC 33))])]
5177 (define_insn "*negsf2"
5178 [(set (match_operand:SF 0 "register_operand" "=f")
5179 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5180 (clobber (reg:CC 33))]
5181 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5183 [(set_attr "op_type" "RRE")])
5185 (define_insn "*negsf2"
5186 [(set (match_operand:SF 0 "register_operand" "=f")
5187 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5188 (clobber (reg:CC 33))]
5189 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5191 [(set_attr "op_type" "RR")])
5195 ;;- Absolute value instructions.
5199 ; absdi2 instruction pattern(s).
5202 (define_insn "absdi2"
5203 [(set (match_operand:DI 0 "register_operand" "=d")
5204 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5205 (clobber (reg:CC 33))]
5208 [(set_attr "op_type" "RRE")])
5211 ; abssi2 instruction pattern(s).
5214 (define_insn "abssi2"
5215 [(set (match_operand:SI 0 "register_operand" "=d")
5216 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5217 (clobber (reg:CC 33))]
5220 [(set_attr "op_type" "RR")])
5223 ; absdf2 instruction pattern(s).
5226 (define_expand "absdf2"
5228 [(set (match_operand:DF 0 "register_operand" "=f")
5229 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5230 (clobber (reg:CC 33))])]
5234 (define_insn "*absdf2"
5235 [(set (match_operand:DF 0 "register_operand" "=f")
5236 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5237 (clobber (reg:CC 33))]
5238 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5240 [(set_attr "op_type" "RRE")])
5242 (define_insn "*absdf2_ibm"
5243 [(set (match_operand:DF 0 "register_operand" "=f")
5244 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5245 (clobber (reg:CC 33))]
5246 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5248 [(set_attr "op_type" "RR")])
5251 ; abssf2 instruction pattern(s).
5254 (define_expand "abssf2"
5256 [(set (match_operand:SF 0 "register_operand" "=f")
5257 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5258 (clobber (reg:CC 33))])]
5262 (define_insn "*abssf2"
5263 [(set (match_operand:SF 0 "register_operand" "=f")
5264 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5265 (clobber (reg:CC 33))]
5266 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5268 [(set_attr "op_type" "RRE")])
5270 (define_insn "*abssf2_ibm"
5271 [(set (match_operand:SF 0 "register_operand" "=f")
5272 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5273 (clobber (reg:CC 33))]
5274 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5276 [(set_attr "op_type" "RR")])
5279 ;;- Square root instructions.
5283 ; sqrtdf2 instruction pattern(s).
5286 (define_insn "sqrtdf2"
5287 [(set (match_operand:DF 0 "register_operand" "=f,f")
5288 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5289 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5293 [(set_attr "op_type" "RRE,RSE")])
5296 ; sqrtsf2 instruction pattern(s).
5299 (define_insn "sqrtsf2"
5300 [(set (match_operand:SF 0 "register_operand" "=f,f")
5301 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5302 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5306 [(set_attr "op_type" "RRE,RSE")])
5309 ;;- One complement instructions.
5313 ; one_cmpldi2 instruction pattern(s).
5316 (define_expand "one_cmpldi2"
5318 [(set (match_operand:DI 0 "register_operand" "")
5319 (xor:DI (match_operand:DI 1 "register_operand" "")
5321 (clobber (reg:CC 33))])]
5326 ; one_cmplsi2 instruction pattern(s).
5329 (define_expand "one_cmplsi2"
5331 [(set (match_operand:SI 0 "register_operand" "")
5332 (xor:SI (match_operand:SI 1 "register_operand" "")
5334 (clobber (reg:CC 33))])]
5339 ; one_cmplhi2 instruction pattern(s).
5342 (define_expand "one_cmplhi2"
5344 [(set (match_operand:HI 0 "register_operand" "")
5345 (xor:HI (match_operand:HI 1 "register_operand" "")
5347 (clobber (reg:CC 33))])]
5352 ; one_cmplqi2 instruction pattern(s).
5355 (define_expand "one_cmplqi2"
5357 [(set (match_operand:QI 0 "register_operand" "")
5358 (xor:QI (match_operand:QI 1 "register_operand" "")
5360 (clobber (reg:CC 33))])]
5366 ;;- Rotate instructions.
5370 ; rotldi3 instruction pattern(s).
5373 (define_insn "rotldi3"
5374 [(set (match_operand:DI 0 "register_operand" "=d,d")
5375 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5376 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5381 [(set_attr "op_type" "RSE")])
5384 ; rotlsi3 instruction pattern(s).
5387 (define_insn "rotlsi3"
5388 [(set (match_operand:SI 0 "register_operand" "=d,d")
5389 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5390 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5395 [(set_attr "op_type" "RSE")])
5399 ;;- Arithmetic shift instructions.
5403 ; ashldi3 instruction pattern(s).
5406 (define_expand "ashldi3"
5407 [(set (match_operand:DI 0 "register_operand" "")
5408 (ashift:DI (match_operand:DI 1 "register_operand" "")
5409 (match_operand:SI 2 "nonmemory_operand" "")))]
5413 (define_insn "*ashldi3_31"
5414 [(set (match_operand:DI 0 "register_operand" "=d,d")
5415 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5416 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5421 [(set_attr "op_type" "RS")])
5423 (define_insn "*ashldi3_64"
5424 [(set (match_operand:DI 0 "register_operand" "=d,d")
5425 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5426 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5431 [(set_attr "op_type" "RSE")])
5434 ; ashrdi3 instruction pattern(s).
5437 (define_expand "ashrdi3"
5439 [(set (match_operand:DI 0 "register_operand" "")
5440 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5441 (match_operand:SI 2 "nonmemory_operand" "")))
5442 (clobber (reg:CC 33))])]
5446 (define_insn "*ashrdi3_cc_31"
5448 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5449 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5451 (set (match_operand:DI 0 "register_operand" "=d,d")
5452 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5453 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5457 [(set_attr "op_type" "RS")])
5459 (define_insn "*ashrdi3_cconly_31"
5461 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5462 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5464 (clobber (match_scratch:DI 0 "=d,d"))]
5465 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5469 [(set_attr "op_type" "RS")])
5471 (define_insn "*ashrdi3_31"
5472 [(set (match_operand:DI 0 "register_operand" "=d,d")
5473 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5474 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5475 (clobber (reg:CC 33))]
5480 [(set_attr "op_type" "RS")])
5482 (define_insn "*ashrdi3_cc_64"
5484 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5485 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5487 (set (match_operand:DI 0 "register_operand" "=d,d")
5488 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5489 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5493 [(set_attr "op_type" "RSE")])
5495 (define_insn "*ashrdi3_cconly_64"
5497 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5498 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5500 (clobber (match_scratch:DI 0 "=d,d"))]
5501 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5505 [(set_attr "op_type" "RSE")])
5507 (define_insn "*ashrdi3_64"
5508 [(set (match_operand:DI 0 "register_operand" "=d,d")
5509 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5510 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5511 (clobber (reg:CC 33))]
5516 [(set_attr "op_type" "RSE")])
5519 ; ashlsi3 instruction pattern(s).
5522 (define_insn "ashlsi3"
5523 [(set (match_operand:SI 0 "register_operand" "=d,d")
5524 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5525 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5530 [(set_attr "op_type" "RS")])
5533 ; ashrsi3 instruction pattern(s).
5536 (define_insn "*ashrsi3_cc"
5538 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5539 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5541 (set (match_operand:SI 0 "register_operand" "=d,d")
5542 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5543 "s390_match_ccmode(insn, CCSmode)"
5547 [(set_attr "op_type" "RS")])
5549 (define_insn "*ashrsi3_cconly"
5551 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5552 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5554 (clobber (match_scratch:SI 0 "=d,d"))]
5555 "s390_match_ccmode(insn, CCSmode)"
5559 [(set_attr "op_type" "RS")])
5561 (define_insn "ashrsi3"
5562 [(set (match_operand:SI 0 "register_operand" "=d,d")
5563 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5564 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5565 (clobber (reg:CC 33))]
5570 [(set_attr "op_type" "RS")])
5574 ;;- logical shift instructions.
5578 ; lshrdi3 instruction pattern(s).
5581 (define_expand "lshrdi3"
5582 [(set (match_operand:DI 0 "register_operand" "")
5583 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5584 (match_operand:SI 2 "nonmemory_operand" "")))]
5588 (define_insn "*lshrdi3_31"
5589 [(set (match_operand:DI 0 "register_operand" "=d,d")
5590 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5591 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5596 [(set_attr "op_type" "RS,RS")])
5598 (define_insn "*lshrdi3_64"
5599 [(set (match_operand:DI 0 "register_operand" "=d,d")
5600 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5601 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5606 [(set_attr "op_type" "RSE,RSE")])
5609 ; lshrsi3 instruction pattern(s).
5612 (define_insn "lshrsi3"
5613 [(set (match_operand:SI 0 "register_operand" "=d,d")
5614 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5615 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5620 [(set_attr "op_type" "RS")])
5624 ;; Branch instruction patterns.
5627 (define_expand "beq"
5628 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5630 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5631 (label_ref (match_operand 0 "" ""))
5634 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5636 (define_expand "bne"
5637 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5639 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5640 (label_ref (match_operand 0 "" ""))
5643 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5645 (define_expand "bgt"
5646 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5648 (if_then_else (gt (reg:CCS 33) (const_int 0))
5649 (label_ref (match_operand 0 "" ""))
5652 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5654 (define_expand "bgtu"
5655 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5657 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5658 (label_ref (match_operand 0 "" ""))
5661 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5663 (define_expand "blt"
5664 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5666 (if_then_else (lt (reg:CCS 33) (const_int 0))
5667 (label_ref (match_operand 0 "" ""))
5670 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5672 (define_expand "bltu"
5673 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5675 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5676 (label_ref (match_operand 0 "" ""))
5679 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5681 (define_expand "bge"
5682 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5684 (if_then_else (ge (reg:CCS 33) (const_int 0))
5685 (label_ref (match_operand 0 "" ""))
5688 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5690 (define_expand "bgeu"
5691 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5693 (if_then_else (geu (reg:CCU 33) (const_int 0))
5694 (label_ref (match_operand 0 "" ""))
5697 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5699 (define_expand "ble"
5700 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5702 (if_then_else (le (reg:CCS 33) (const_int 0))
5703 (label_ref (match_operand 0 "" ""))
5706 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5708 (define_expand "bleu"
5709 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5711 (if_then_else (leu (reg:CCU 33) (const_int 0))
5712 (label_ref (match_operand 0 "" ""))
5715 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5717 (define_expand "bunordered"
5718 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5720 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5721 (label_ref (match_operand 0 "" ""))
5724 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5726 (define_expand "bordered"
5727 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5729 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5730 (label_ref (match_operand 0 "" ""))
5733 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5735 (define_expand "buneq"
5736 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5738 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5739 (label_ref (match_operand 0 "" ""))
5742 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5744 (define_expand "bungt"
5745 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5747 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5748 (label_ref (match_operand 0 "" ""))
5751 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5753 (define_expand "bunlt"
5754 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5756 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5757 (label_ref (match_operand 0 "" ""))
5760 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5762 (define_expand "bunge"
5763 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5765 (if_then_else (unge (reg:CCS 33) (const_int 0))
5766 (label_ref (match_operand 0 "" ""))
5769 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5771 (define_expand "bunle"
5772 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5774 (if_then_else (unle (reg:CCS 33) (const_int 0))
5775 (label_ref (match_operand 0 "" ""))
5778 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5780 (define_expand "bltgt"
5781 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5783 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5784 (label_ref (match_operand 0 "" ""))
5787 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5791 ;;- Conditional jump instructions.
5794 (define_insn "cjump"
5797 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5798 (label_ref (match_operand 0 "" ""))
5803 if (get_attr_length (insn) == 4)
5804 return \"j%C1\\t%l0\";
5805 else if (TARGET_64BIT)
5806 return \"jg%C1\\t%l0\";
5810 [(set_attr "op_type" "RI")
5811 (set (attr "length")
5812 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5814 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5816 (eq (symbol_ref "flag_pic") (const_int 0))
5817 (const_int 6)] (const_int 8)))])
5819 (define_insn "*cjump_long"
5822 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5823 (match_operand 0 "address_operand" "p")
5828 if (get_attr_op_type (insn) == OP_TYPE_RR)
5829 return \"b%C1r\\t%0\";
5831 return \"b%C1\\t%a0\";
5833 [(set (attr "op_type")
5834 (if_then_else (match_operand 0 "register_operand" "")
5835 (const_string "RR") (const_string "RX")))
5836 (set_attr "atype" "mem")])
5840 ;;- Negated conditional jump instructions.
5843 (define_insn "icjump"
5846 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5848 (label_ref (match_operand 0 "" ""))))]
5852 if (get_attr_length (insn) == 4)
5853 return \"j%D1\\t%l0\";
5854 else if (TARGET_64BIT)
5855 return \"jg%D1\\t%l0\";
5859 [(set_attr "op_type" "RI")
5860 (set (attr "length")
5861 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5863 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5865 (eq (symbol_ref "flag_pic") (const_int 0))
5866 (const_int 6)] (const_int 8)))])
5868 (define_insn "*icjump_long"
5871 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5873 (match_operand 0 "address_operand" "p")))]
5877 if (get_attr_op_type (insn) == OP_TYPE_RR)
5878 return \"b%D1r\\t%0\";
5880 return \"b%D1\\t%a0\";
5882 [(set (attr "op_type")
5883 (if_then_else (match_operand 0 "register_operand" "")
5884 (const_string "RR") (const_string "RX")))
5885 (set_attr "atype" "mem")])
5888 ;;- Trap instructions.
5892 [(trap_if (const_int 1) (const_int 0))]
5895 [(set_attr "op_type" "RX")])
5897 (define_expand "conditional_trap"
5898 [(set (match_dup 2) (match_dup 3))
5899 (trap_if (match_operator 0 "comparison_operator"
5900 [(match_dup 2) (const_int 0)])
5901 (match_operand:SI 1 "general_operand" ""))]
5905 enum machine_mode ccmode;
5907 if (operands[1] != const0_rtx) FAIL;
5909 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5910 s390_compare_op0, s390_compare_op1);
5911 operands[2] = gen_rtx_REG (ccmode, 33);
5912 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5915 (define_insn "*trap"
5916 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5920 [(set_attr "op_type" "RX")])
5923 ;;- Loop instructions.
5925 ;; This is all complicated by the fact that since this is a jump insn
5926 ;; we must handle our own output reloads.
5928 (define_expand "doloop_end"
5929 [(use (match_operand 0 "" "")) ; loop pseudo
5930 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5931 (use (match_operand 2 "" "")) ; max iterations
5932 (use (match_operand 3 "" "")) ; loop level
5933 (use (match_operand 4 "" ""))] ; label
5937 if (GET_MODE (operands[0]) == SImode)
5938 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5939 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5940 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5947 (define_insn "doloop_si"
5950 (ne (match_operand:SI 1 "register_operand" "d,d")
5952 (label_ref (match_operand 0 "" ""))
5954 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5955 (plus:SI (match_dup 1) (const_int -1)))
5956 (clobber (match_scratch:SI 3 "=X,&d"))
5957 (clobber (reg:CC 33))]
5961 if (which_alternative != 0)
5963 else if (get_attr_length (insn) == 4)
5964 return \"brct\\t%1,%l0\";
5968 [(set_attr "op_type" "RI")
5969 (set (attr "length")
5970 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5972 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5974 (eq (symbol_ref "flag_pic") (const_int 0))
5975 (const_int 6)] (const_int 8)))])
5977 (define_insn "*doloop_si_long"
5980 (ne (match_operand:SI 1 "register_operand" "d,d")
5982 (match_operand 0 "address_operand" "p,p")
5984 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5985 (plus:SI (match_dup 1) (const_int -1)))
5986 (clobber (match_scratch:SI 3 "=X,&d"))
5987 (clobber (reg:CC 33))]
5991 if (get_attr_op_type (insn) == OP_TYPE_RR)
5992 return \"bctr\\t%1,%0\";
5994 return \"bct\\t%1,%a0\";
5996 [(set (attr "op_type")
5997 (if_then_else (match_operand 0 "register_operand" "")
5998 (const_string "RR") (const_string "RX")))
5999 (set_attr "atype" "mem")])
6003 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
6005 (match_operand 0 "" "")
6007 (set (match_operand:SI 2 "nonimmediate_operand" "")
6008 (plus:SI (match_dup 1) (const_int -1)))
6009 (clobber (match_scratch:SI 3 ""))
6010 (clobber (reg:CC 33))]
6012 && (! REG_P (operands[2])
6013 || ! rtx_equal_p (operands[1], operands[2]))"
6014 [(set (match_dup 3) (match_dup 1))
6015 (parallel [(set (reg:CCAN 33)
6016 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6018 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6019 (set (match_dup 2) (match_dup 3))
6020 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6025 (define_insn "doloop_di"
6028 (ne (match_operand:DI 1 "register_operand" "d,d")
6030 (label_ref (match_operand 0 "" ""))
6032 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6033 (plus:DI (match_dup 1) (const_int -1)))
6034 (clobber (match_scratch:DI 3 "=X,&d"))
6035 (clobber (reg:CC 33))]
6039 if (which_alternative != 0)
6041 else if (get_attr_length (insn) == 4)
6042 return \"brctg\\t%1,%l0\";
6046 [(set_attr "op_type" "RI")
6047 (set (attr "length")
6048 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6049 (const_int 4) (const_int 12)))])
6051 (define_insn "*doloop_di_long"
6054 (ne (match_operand:DI 1 "register_operand" "d,d")
6056 (match_operand 0 "address_operand" "p,p")
6058 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6059 (plus:DI (match_dup 1) (const_int -1)))
6060 (clobber (match_scratch:DI 3 "=X,&d"))
6061 (clobber (reg:CC 33))]
6065 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6066 return \"bctgr\\t%1,%0\";
6068 return \"bctg\\t%1,%a0\";
6070 [(set (attr "op_type")
6071 (if_then_else (match_operand 0 "register_operand" "")
6072 (const_string "RRE") (const_string "RXE")))
6073 (set_attr "atype" "mem")])
6077 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6079 (match_operand 0 "" "")
6081 (set (match_operand:DI 2 "nonimmediate_operand" "")
6082 (plus:DI (match_dup 1) (const_int -1)))
6083 (clobber (match_scratch:DI 3 ""))
6084 (clobber (reg:CC 33))]
6086 && (! REG_P (operands[2])
6087 || ! rtx_equal_p (operands[1], operands[2]))"
6088 [(set (match_dup 3) (match_dup 1))
6089 (parallel [(set (reg:CCAN 33)
6090 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6092 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6093 (set (match_dup 2) (match_dup 3))
6094 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6100 ;;- Unconditional jump instructions.
6104 ; jump instruction pattern(s).
6108 [(set (pc) (label_ref (match_operand 0 "" "")))]
6112 if (get_attr_length (insn) == 4)
6114 else if (TARGET_64BIT)
6115 return \"jg\\t%l0\";
6119 [(set_attr "op_type" "RI")
6120 (set (attr "length")
6121 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6123 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6125 (eq (symbol_ref "flag_pic") (const_int 0))
6126 (const_int 6)] (const_int 8)))])
6129 ; indirect-jump instruction pattern(s).
6132 (define_insn "indirect_jump"
6133 [(set (pc) (match_operand 0 "address_operand" "p"))]
6137 if (get_attr_op_type (insn) == OP_TYPE_RR)
6142 [(set (attr "op_type")
6143 (if_then_else (match_operand 0 "register_operand" "")
6144 (const_string "RR") (const_string "RX")))
6145 (set_attr "atype" "mem")])
6148 ; casesi instruction pattern(s).
6151 (define_insn "casesi_jump"
6152 [(set (pc) (match_operand 0 "address_operand" "p"))
6153 (use (label_ref (match_operand 1 "" "")))]
6157 if (get_attr_op_type (insn) == OP_TYPE_RR)
6162 [(set (attr "op_type")
6163 (if_then_else (match_operand 0 "register_operand" "")
6164 (const_string "RR") (const_string "RX")))
6165 (set_attr "atype" "mem")])
6167 (define_expand "casesi"
6168 [(match_operand:SI 0 "general_operand" "")
6169 (match_operand:SI 1 "general_operand" "")
6170 (match_operand:SI 2 "general_operand" "")
6171 (label_ref (match_operand 3 "" ""))
6172 (label_ref (match_operand 4 "" ""))]
6176 rtx index = gen_reg_rtx (SImode);
6177 rtx base = gen_reg_rtx (Pmode);
6178 rtx target = gen_reg_rtx (Pmode);
6180 emit_move_insn (index, operands[0]);
6181 emit_insn (gen_subsi3 (index, index, operands[1]));
6182 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6185 if (Pmode != SImode)
6186 index = convert_to_mode (Pmode, index, 1);
6187 if (GET_CODE (index) != REG)
6188 index = copy_to_mode_reg (Pmode, index);
6191 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6193 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6195 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6197 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6198 emit_move_insn (target, index);
6201 target = gen_rtx_PLUS (Pmode, base, target);
6202 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6209 ;;- Jump to subroutine.
6214 ; untyped call instruction pattern(s).
6217 ;; Call subroutine returning any type.
6218 (define_expand "untyped_call"
6219 [(parallel [(call (match_operand 0 "" "")
6221 (match_operand 1 "" "")
6222 (match_operand 2 "" "")])]
6228 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6230 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6232 rtx set = XVECEXP (operands[2], 0, i);
6233 emit_move_insn (SET_DEST (set), SET_SRC (set));
6236 /* The optimizer does not know that the call sets the function value
6237 registers we stored in the result block. We avoid problems by
6238 claiming that all hard registers are used and clobbered at this
6240 emit_insn (gen_blockage ());
6245 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6246 ;; all of memory. This blocks insns from being moved across this point.
6248 (define_insn "blockage"
6249 [(unspec_volatile [(const_int 0)] 0)]
6252 [(set_attr "type" "none")
6253 (set_attr "length" "0")])
6258 ; call instruction pattern(s).
6261 (define_expand "call"
6262 [(call (match_operand 0 "" "")
6263 (match_operand 1 "" ""))
6264 (use (match_operand 2 "" ""))]
6271 /* Direct function calls need special treatment. */
6272 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6274 rtx sym = XEXP (operands[0], 0);
6276 /* When calling a global routine in PIC mode, we must
6277 replace the symbol itself with the PLT stub. */
6278 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6280 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6281 sym = gen_rtx_CONST (Pmode, sym);
6286 /* Unless we can use the bras(l) insn, force the
6287 routine address into a register. */
6288 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6290 rtx target = gen_reg_rtx (Pmode);
6291 emit_move_insn (target, sym);
6295 operands[0] = gen_rtx_MEM (QImode, sym);
6299 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6300 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6302 /* In 31-bit, we must load the GOT register even if the
6303 compiler doesn't know about it, because the PLT glue
6304 code uses it. In 64-bit, this is not necessary. */
6305 if (plt_call && !TARGET_64BIT)
6306 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6311 (define_expand "call_exp"
6312 [(parallel [(call (match_operand 0 "" "")
6313 (match_operand 1 "" ""))
6314 (clobber (match_operand 2 "" ""))])]
6318 (define_insn "brasl"
6319 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6320 (match_operand:SI 1 "const_int_operand" "n"))
6321 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6324 [(set_attr "op_type" "RIL")
6325 (set_attr "type" "jsr")])
6328 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6329 (match_operand:SI 1 "const_int_operand" "n"))
6330 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6333 [(set_attr "op_type" "RI")
6334 (set_attr "type" "jsr")])
6336 (define_insn "basr_64"
6337 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6338 (match_operand:SI 1 "const_int_operand" "n"))
6339 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6342 [(set_attr "op_type" "RR")
6343 (set_attr "type" "jsr")
6344 (set_attr "atype" "mem")])
6346 (define_insn "basr_31"
6347 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6348 (match_operand:SI 1 "const_int_operand" "n"))
6349 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6352 [(set_attr "op_type" "RR")
6353 (set_attr "type" "jsr")
6354 (set_attr "atype" "mem")])
6356 (define_insn "bas_64"
6357 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6358 (match_operand:SI 1 "const_int_operand" "n"))
6359 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6362 [(set_attr "op_type" "RX")
6363 (set_attr "type" "jsr")
6364 (set_attr "atype" "mem")])
6366 (define_insn "bas_31"
6367 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6368 (match_operand:SI 1 "const_int_operand" "n"))
6369 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6372 [(set_attr "op_type" "RX")
6373 (set_attr "type" "jsr")
6374 (set_attr "atype" "mem")])
6378 ; call_value instruction pattern(s).
6381 (define_expand "call_value"
6382 [(set (match_operand 0 "" "")
6383 (call (match_operand 1 "" "")
6384 (match_operand 2 "" "")))
6385 (use (match_operand 3 "" ""))]
6392 /* Direct function calls need special treatment. */
6393 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6395 rtx sym = XEXP (operands[1], 0);
6397 /* When calling a global routine in PIC mode, we must
6398 replace the symbol itself with the PLT stub. */
6399 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6401 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6402 sym = gen_rtx_CONST (Pmode, sym);
6407 /* Unless we can use the bras(l) insn, force the
6408 routine address into a register. */
6409 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6411 rtx target = gen_reg_rtx (Pmode);
6412 emit_move_insn (target, sym);
6416 operands[1] = gen_rtx_MEM (QImode, sym);
6420 insn = emit_call_insn (
6421 gen_call_value_exp (operands[0], operands[1], operands[2],
6422 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6424 /* In 31-bit, we must load the GOT register even if the
6425 compiler doesn't know about it, because the PLT glue
6426 code uses it. In 64-bit, this is not necessary. */
6427 if (plt_call && !TARGET_64BIT)
6428 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6433 (define_expand "call_value_exp"
6434 [(parallel [(set (match_operand 0 "" "")
6435 (call (match_operand 1 "" "")
6436 (match_operand 2 "" "")))
6437 (clobber (match_operand 3 "" ""))])]
6441 (define_insn "brasl_r"
6442 [(set (match_operand 0 "register_operand" "=df")
6443 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6444 (match_operand:SI 2 "const_int_operand" "n")))
6445 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6448 [(set_attr "op_type" "RIL")
6449 (set_attr "type" "jsr")])
6451 (define_insn "bras_r"
6452 [(set (match_operand 0 "register_operand" "=df")
6453 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6454 (match_operand:SI 2 "const_int_operand" "n")))
6455 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6458 [(set_attr "op_type" "RI")
6459 (set_attr "type" "jsr")])
6461 (define_insn "basr_r_64"
6462 [(set (match_operand 0 "register_operand" "=df")
6463 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6464 (match_operand:SI 2 "const_int_operand" "n")))
6465 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6468 [(set_attr "op_type" "RR")
6469 (set_attr "type" "jsr")])
6471 (define_insn "basr_r_31"
6472 [(set (match_operand 0 "register_operand" "=df")
6473 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6474 (match_operand:SI 2 "const_int_operand" "n")))
6475 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6478 [(set_attr "op_type" "RR")
6479 (set_attr "type" "jsr")
6480 (set_attr "atype" "mem")])
6482 (define_insn "bas_r_64"
6483 [(set (match_operand 0 "register_operand" "=df")
6484 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6485 (match_operand:SI 2 "const_int_operand" "n")))
6486 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6489 [(set_attr "op_type" "RX")
6490 (set_attr "type" "jsr")
6491 (set_attr "atype" "mem")])
6493 (define_insn "bas_r_31"
6494 [(set (match_operand 0 "register_operand" "=df")
6495 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6496 (match_operand:SI 2 "const_int_operand" "n")))
6497 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6500 [(set_attr "op_type" "RX")
6501 (set_attr "type" "jsr")
6502 (set_attr "atype" "mem")])
6506 ;;- Miscellaneous instructions.
6510 ; allocate stack instruction pattern(s).
6513 (define_expand "allocate_stack"
6515 (plus (reg 15) (match_operand 1 "general_operand" "")))
6516 (set (match_operand 0 "general_operand" "")
6521 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6522 rtx chain = gen_rtx (MEM, Pmode, stack);
6523 rtx temp = gen_reg_rtx (Pmode);
6525 emit_move_insn (temp, chain);
6528 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6530 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6532 emit_move_insn (chain, temp);
6534 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6540 ; setjmp/longjmp instruction pattern(s).
6543 (define_expand "builtin_setjmp_setup"
6544 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6548 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6549 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6551 emit_move_insn (base, basereg);
6555 (define_expand "builtin_setjmp_receiver"
6556 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6560 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6561 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6562 SYMBOL_REF_FLAG (got) = 1;
6564 emit_move_insn (gotreg, got);
6565 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6569 (define_expand "builtin_longjmp"
6570 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6574 /* The elements of the buffer are, in order: */
6575 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6576 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6577 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6578 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6579 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6580 rtx jmp = gen_rtx_REG (Pmode, 14);
6582 emit_move_insn (jmp, lab);
6583 emit_move_insn (basereg, base);
6584 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6585 emit_move_insn (hard_frame_pointer_rtx, fp);
6587 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6588 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6589 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6590 emit_indirect_jump (jmp);
6595 ;; These patterns say how to save and restore the stack pointer. We need not
6596 ;; save the stack pointer at function level since we are careful to
6597 ;; preserve the backchain. At block level, we have to restore the backchain
6598 ;; when we restore the stack pointer.
6600 ;; For nonlocal gotos, we must save both the stack pointer and its
6601 ;; backchain and restore both. Note that in the nonlocal case, the
6602 ;; save area is a memory location.
6604 (define_expand "save_stack_function"
6605 [(match_operand 0 "general_operand" "")
6606 (match_operand 1 "general_operand" "")]
6610 (define_expand "restore_stack_function"
6611 [(match_operand 0 "general_operand" "")
6612 (match_operand 1 "general_operand" "")]
6616 (define_expand "restore_stack_block"
6617 [(use (match_operand 0 "register_operand" ""))
6618 (set (match_dup 2) (match_dup 3))
6619 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6620 (set (match_dup 3) (match_dup 2))]
6624 operands[2] = gen_reg_rtx (Pmode);
6625 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6628 (define_expand "save_stack_nonlocal"
6629 [(match_operand 0 "memory_operand" "")
6630 (match_operand 1 "register_operand" "")]
6634 rtx temp = gen_reg_rtx (Pmode);
6636 /* Copy the backchain to the first word, sp to the second. */
6637 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6638 emit_move_insn (operand_subword (operands[0], 0, 0,
6639 TARGET_64BIT ? TImode : DImode),
6641 emit_move_insn (operand_subword (operands[0], 1, 0,
6642 TARGET_64BIT ? TImode : DImode),
6647 (define_expand "restore_stack_nonlocal"
6648 [(match_operand 0 "register_operand" "")
6649 (match_operand 1 "memory_operand" "")]
6653 rtx temp = gen_reg_rtx (Pmode);
6655 /* Restore the backchain from the first word, sp from the second. */
6656 emit_move_insn (temp,
6657 operand_subword (operands[1], 0, 0,
6658 TARGET_64BIT ? TImode : DImode));
6659 emit_move_insn (operands[0],
6660 operand_subword (operands[1], 1, 0,
6661 TARGET_64BIT ? TImode : DImode));
6662 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6668 ; nop instruction pattern(s).
6675 [(set_attr "op_type" "RR")])
6679 ; Special literal pool access instruction pattern(s).
6682 (define_insn "consttable_qi"
6683 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6687 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6690 [(set_attr "op_type" "NN")
6691 (set_attr "length" "1")])
6693 (define_insn "consttable_hi"
6694 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6698 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6701 [(set_attr "op_type" "NN")
6702 (set_attr "length" "2")])
6704 (define_insn "consttable_si"
6705 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6709 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6710 return \".long\\t%0\";
6712 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6715 [(set_attr "op_type" "NN")
6716 (set_attr "length" "4")])
6718 (define_insn "consttable_di"
6719 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6723 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6726 [(set_attr "op_type" "NN")
6727 (set_attr "length" "8")])
6729 (define_insn "consttable_sf"
6730 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6736 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6739 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6740 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6743 [(set_attr "op_type" "NN")
6744 (set_attr "length" "4")])
6746 (define_insn "consttable_df"
6747 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6753 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6756 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6757 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6760 [(set_attr "op_type" "NN")
6761 (set_attr "length" "8")])
6763 (define_insn "pool_start_31"
6764 [(unspec_volatile [(const_int 0)] 206)]
6767 [(set_attr "op_type" "NN")
6768 (set_attr "length" "2")])
6770 (define_insn "pool_end_31"
6771 [(unspec_volatile [(const_int 0)] 207)]
6774 [(set_attr "op_type" "NN")
6775 (set_attr "length" "2")])
6777 (define_insn "pool_start_64"
6778 [(unspec_volatile [(const_int 0)] 206)]
6780 ".section\\t.rodata\;.align\\t8"
6781 [(set_attr "op_type" "NN")
6782 (set_attr "length" "0")])
6784 (define_insn "pool_end_64"
6785 [(unspec_volatile [(const_int 0)] 207)]
6788 [(set_attr "op_type" "NN")
6789 (set_attr "length" "0")])
6791 (define_insn "reload_base_31"
6792 [(set (match_operand:SI 0 "register_operand" "=a")
6793 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6795 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6796 [(set_attr "op_type" "NN")
6797 (set_attr "type" "la")
6798 (set_attr "length" "6")])
6800 (define_insn "reload_base_64"
6801 [(set (match_operand:DI 0 "register_operand" "=a")
6802 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6805 [(set_attr "op_type" "RIL")
6806 (set_attr "type" "la")])
6808 (define_insn "reload_anchor"
6809 [(set (match_operand:SI 0 "register_operand" "=a")
6810 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6812 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6813 [(set_attr "op_type" "NN")
6814 (set_attr "type" "la")
6815 (set_attr "length" "8")])
6818 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6821 [(set_attr "op_type" "NN")
6822 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6825 ;; Insns related to generating the function prologue and epilogue.
6829 (define_expand "prologue"
6830 [(use (const_int 0))]
6834 s390_emit_prologue ();
6838 (define_expand "epilogue"
6839 [(use (const_int 1))]
6843 s390_emit_epilogue ();
6848 (define_insn "*return_si"
6850 (use (match_operand:SI 0 "register_operand" "a"))]
6853 [(set_attr "op_type" "RR")
6854 (set_attr "type" "jsr")
6855 (set_attr "atype" "mem")])
6857 (define_insn "*return_di"
6859 (use (match_operand:DI 0 "register_operand" "a"))]
6862 [(set_attr "op_type" "RR")
6863 (set_attr "type" "jsr")
6864 (set_attr "atype" "mem")])
6866 (define_insn "literal_pool_31"
6867 [(unspec_volatile [(const_int 0)] 300)
6868 (set (match_operand:SI 0 "register_operand" "=a")
6869 (label_ref (match_operand 1 "" "")))
6870 (use (label_ref (match_operand 2 "" "")))]
6874 if (s390_nr_constants) {
6875 output_asm_insn (\"bras\\t%0,%2\", operands);
6876 s390_output_constant_pool (operands[1], operands[2]);
6880 [(set_attr "op_type" "NN")
6881 (set_attr "type" "la")])
6883 (define_insn "literal_pool_64"
6884 [(unspec_volatile [(const_int 0)] 300)
6885 (set (match_operand:DI 0 "register_operand" "=a")
6886 (label_ref (match_operand 1 "" "")))
6887 (use (label_ref (match_operand 2 "" "")))]
6891 if (s390_nr_constants) {
6892 output_asm_insn (\"larl\\t%0,%1\", operands);
6893 s390_output_constant_pool (operands[1], operands[2]);
6897 [(set_attr "op_type" "NN")
6898 (set_attr "type" "la")])