1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %O: print only the displacement of a memory reference.
76 ;; %R: print only the base register of a memory reference.
77 ;; %S: print S-type memory reference (base+displacement).
78 ;; %N: print the second word of a DImode operand.
79 ;; %M: print the second word of a TImode operand.
81 ;; %b: print integer X as if it's an unsigned byte.
82 ;; %x: print integer X as if it's an unsigned word.
83 ;; %h: print integer X as if it's a signed word.
84 ;; %i: print the first nonzero HImode part of X
85 ;; %j: print the first HImode part unequal to 0xffff of X
88 ;; We have a special constraint for pattern matching.
90 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
103 ; GOT/PLT and lt-relative accesses
104 (UNSPEC_LTREL_OFFSET 100)
105 (UNSPEC_LTREL_BASE 101)
113 (UNSPEC_RELOAD_BASE 210)
114 (UNSPEC_MAIN_BASE 211)
119 ; TLS relocation specifiers
124 (UNSPEC_GOTNTPOFF 504)
125 (UNSPEC_INDNTPOFF 505)
128 (UNSPEC_TLSLDM_NTPOFF 511)
129 (UNSPEC_TLS_LOAD 512)
134 ; Stack Smashing Protector
140 ;; UNSPEC_VOLATILE usage
148 (UNSPECV_TPF_PROLOGUE 20)
149 (UNSPECV_TPF_EPILOGUE 21)
153 (UNSPECV_POOL_SECTION 201)
154 (UNSPECV_POOL_ALIGN 202)
155 (UNSPECV_POOL_ENTRY 203)
156 (UNSPECV_MAIN_POOL 300)
172 ; Sibling call register.
174 ; Literal pool base register.
176 ; Return address register.
178 ; Condition code register.
180 ; Thread local storage pointer register.
185 ;; Instruction operand type as used in the Principles of Operation.
186 ;; Used to determine defaults for length and other attribute values.
188 (define_attr "op_type"
189 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
192 ;; Instruction type attribute used for scheduling.
194 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
195 cs,vs,store,sem,idiv,
196 imulhi,imulsi,imuldi,
197 branch,jsr,fsimpdf,fsimpsf,
198 floaddf,floadsf,fstoredf,fstoresf,
199 fmuldf,fmulsf,fdivdf,fdivsf,
200 ftoi,itof,fsqrtdf,fsqrtsf,
202 (cond [(eq_attr "op_type" "NN") (const_string "other")
203 (eq_attr "op_type" "SS") (const_string "cs")]
204 (const_string "integer")))
206 ;; Another attribute used for scheduling purposes:
207 ;; agen: Instruction uses the address generation unit
208 ;; reg: Instruction does not use the agen unit
210 (define_attr "atype" "agen,reg"
211 (cond [(eq_attr "op_type" "E") (const_string "reg")
212 (eq_attr "op_type" "RR") (const_string "reg")
213 (eq_attr "op_type" "RX") (const_string "agen")
214 (eq_attr "op_type" "RI") (const_string "reg")
215 (eq_attr "op_type" "RRE") (const_string "reg")
216 (eq_attr "op_type" "RS") (const_string "agen")
217 (eq_attr "op_type" "RSI") (const_string "agen")
218 (eq_attr "op_type" "S") (const_string "agen")
219 (eq_attr "op_type" "SI") (const_string "agen")
220 (eq_attr "op_type" "SS") (const_string "agen")
221 (eq_attr "op_type" "SSE") (const_string "agen")
222 (eq_attr "op_type" "RXE") (const_string "agen")
223 (eq_attr "op_type" "RSE") (const_string "agen")
224 (eq_attr "op_type" "RIL") (const_string "agen")
225 (eq_attr "op_type" "RXY") (const_string "agen")
226 (eq_attr "op_type" "RSY") (const_string "agen")
227 (eq_attr "op_type" "SIY") (const_string "agen")]
228 (const_string "agen")))
232 (define_attr "length" ""
233 (cond [(eq_attr "op_type" "E") (const_int 2)
234 (eq_attr "op_type" "RR") (const_int 2)
235 (eq_attr "op_type" "RX") (const_int 4)
236 (eq_attr "op_type" "RI") (const_int 4)
237 (eq_attr "op_type" "RRE") (const_int 4)
238 (eq_attr "op_type" "RS") (const_int 4)
239 (eq_attr "op_type" "RSI") (const_int 4)
240 (eq_attr "op_type" "S") (const_int 4)
241 (eq_attr "op_type" "SI") (const_int 4)
242 (eq_attr "op_type" "SS") (const_int 6)
243 (eq_attr "op_type" "SSE") (const_int 6)
244 (eq_attr "op_type" "RXE") (const_int 6)
245 (eq_attr "op_type" "RSE") (const_int 6)
246 (eq_attr "op_type" "RIL") (const_int 6)
247 (eq_attr "op_type" "RXY") (const_int 6)
248 (eq_attr "op_type" "RSY") (const_int 6)
249 (eq_attr "op_type" "SIY") (const_int 6)]
253 ;; Processor type. This attribute must exactly match the processor_type
254 ;; enumeration in s390.h. The current machine description does not
255 ;; distinguish between g5 and g6, but there are differences between the two
256 ;; CPUs could in theory be modeled.
258 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
259 (const (symbol_ref "s390_tune")))
261 ;; Pipeline description for z900. For lack of anything better,
262 ;; this description is also used for the g5 and g6.
265 ;; Pipeline description for z990.
269 (include "predicates.md")
276 ;; This mode macro allows DF and SF patterns to be generated from the
278 (define_mode_macro FPR [DF SF])
280 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
281 ;; from the same template.
282 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
283 (define_mode_macro DSI [DI SI])
285 ;; This mode macro allows :P to be used for patterns that operate on
286 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
287 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
289 ;; This mode macro allows the QI and HI patterns to be defined from
290 ;; the same template.
291 (define_mode_macro HQI [HI QI])
293 ;; This mode macro allows the integer patterns to be defined from the
295 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
297 ;; This macro allows to unify all 'bCOND' expander patterns.
298 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
299 ordered uneq unlt ungt unle unge ltgt])
301 ;; This macro allows to unify all 'sCOND' patterns.
302 (define_code_macro SCOND [ltu gtu leu geu])
304 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
305 ;; the same template.
306 (define_code_macro SHIFT [ashift lshiftrt])
309 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
310 ;; and "ltebr" in SFmode.
311 (define_mode_attr de [(DF "d") (SF "e")])
313 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
314 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
315 (define_mode_attr dee [(DF "d") (SF "ee")])
317 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
318 ;; 'ashift' and "srdl" in 'lshiftrt'.
319 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
321 ;; In SHIFT templates, this attribute holds the correct standard name for the
322 ;; pattern itself and the corresponding function calls.
323 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
325 ;; This attribute handles differences in the instruction 'type' and will result
326 ;; in "RRE" for DImode and "RR" for SImode.
327 (define_mode_attr E [(DI "E") (SI "")])
329 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
330 ;; and "lcr" in SImode.
331 (define_mode_attr g [(DI "g") (SI "")])
333 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
334 ;; and "cfdbr" in SImode.
335 (define_mode_attr gf [(DI "g") (SI "f")])
337 ;; ICM mask required to load MODE value into the highest subreg
338 ;; of a SImode register.
339 (define_mode_attr icm_hi [(HI "12") (QI "8")])
341 ;; ICM mask required to load MODE value into the lowest subreg
342 ;; of a SImode register.
343 (define_mode_attr icm_lo [(HI "3") (QI "1")])
345 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
346 ;; HImode and "llgc" in QImode.
347 (define_mode_attr hc [(HI "h") (QI "c")])
349 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
351 (define_mode_attr DBL [(DI "TI") (SI "DI")])
353 ;; Maximum unsigned integer that fits in MODE.
354 (define_mode_attr max_uint [(HI "65535") (QI "255")])
358 ;;- Compare instructions.
361 (define_expand "cmp<mode>"
362 [(set (reg:CC CC_REGNUM)
363 (compare:CC (match_operand:GPR 0 "register_operand" "")
364 (match_operand:GPR 1 "general_operand" "")))]
367 s390_compare_op0 = operands[0];
368 s390_compare_op1 = operands[1];
372 (define_expand "cmp<mode>"
373 [(set (reg:CC CC_REGNUM)
374 (compare:CC (match_operand:FPR 0 "register_operand" "")
375 (match_operand:FPR 1 "general_operand" "")))]
378 s390_compare_op0 = operands[0];
379 s390_compare_op1 = operands[1];
384 ; Test-under-Mask instructions
386 (define_insn "*tmqi_mem"
387 [(set (reg CC_REGNUM)
388 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
389 (match_operand:QI 1 "immediate_operand" "n,n"))
390 (match_operand:QI 2 "immediate_operand" "n,n")))]
391 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
395 [(set_attr "op_type" "SI,SIY")])
397 (define_insn "*tmdi_reg"
398 [(set (reg CC_REGNUM)
399 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
400 (match_operand:DI 1 "immediate_operand"
401 "N0HD0,N1HD0,N2HD0,N3HD0"))
402 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
404 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
405 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
411 [(set_attr "op_type" "RI")])
413 (define_insn "*tmsi_reg"
414 [(set (reg CC_REGNUM)
415 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
416 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
417 (match_operand:SI 2 "immediate_operand" "n,n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
419 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
423 [(set_attr "op_type" "RI")])
425 (define_insn "*tm<mode>_full"
426 [(set (reg CC_REGNUM)
427 (compare (match_operand:HQI 0 "register_operand" "d")
428 (match_operand:HQI 1 "immediate_operand" "n")))]
429 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
431 [(set_attr "op_type" "RI")])
434 ; Load-and-Test instructions
436 (define_insn "*tstdi_sign"
437 [(set (reg CC_REGNUM)
438 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
439 (const_int 32)) (const_int 32))
440 (match_operand:DI 1 "const0_operand" "")))
441 (set (match_operand:DI 2 "register_operand" "=d")
442 (sign_extend:DI (match_dup 0)))]
443 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
445 [(set_attr "op_type" "RRE")])
447 (define_insn "*tstdi_extimm"
448 [(set (reg CC_REGNUM)
449 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
450 (match_operand:DI 1 "const0_operand" "")))
451 (set (match_operand:DI 2 "register_operand" "=d,d")
453 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
457 [(set_attr "op_type" "RRE,RXY")])
459 (define_insn "*tstdi_cconly_extimm"
460 [(set (reg CC_REGNUM)
461 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
462 (match_operand:DI 1 "const0_operand" "")))
463 (clobber (match_scratch:DI 2 "=X,d"))]
464 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
468 [(set_attr "op_type" "RRE,RXY")])
470 (define_insn "*tstdi"
471 [(set (reg CC_REGNUM)
472 (compare (match_operand:DI 0 "register_operand" "d")
473 (match_operand:DI 1 "const0_operand" "")))
474 (set (match_operand:DI 2 "register_operand" "=d")
476 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
478 [(set_attr "op_type" "RRE")])
480 (define_insn "*tstdi_cconly"
481 [(set (reg CC_REGNUM)
482 (compare (match_operand:DI 0 "register_operand" "d")
483 (match_operand:DI 1 "const0_operand" "")))]
484 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
486 [(set_attr "op_type" "RRE")])
488 (define_insn "*tstdi_cconly_31"
489 [(set (reg CC_REGNUM)
490 (compare (match_operand:DI 0 "register_operand" "d")
491 (match_operand:DI 1 "const0_operand" "")))]
492 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
494 [(set_attr "op_type" "RS")
495 (set_attr "atype" "reg")])
497 (define_insn "*tstsi_extimm"
498 [(set (reg CC_REGNUM)
499 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
500 (match_operand:SI 1 "const0_operand" "")))
501 (set (match_operand:SI 2 "register_operand" "=d,d")
503 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
507 [(set_attr "op_type" "RR,RXY")])
509 (define_insn "*tstsi_cconly_extimm"
510 [(set (reg CC_REGNUM)
511 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
512 (match_operand:SI 1 "const0_operand" "")))
513 (clobber (match_scratch:SI 2 "=X,d"))]
514 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
518 [(set_attr "op_type" "RR,RXY")])
520 (define_insn "*tstsi"
521 [(set (reg CC_REGNUM)
522 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
523 (match_operand:SI 1 "const0_operand" "")))
524 (set (match_operand:SI 2 "register_operand" "=d,d,d")
526 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
531 [(set_attr "op_type" "RR,RS,RSY")])
533 (define_insn "*tstsi_cconly"
534 [(set (reg CC_REGNUM)
535 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
536 (match_operand:SI 1 "const0_operand" "")))
537 (clobber (match_scratch:SI 2 "=X,d,d"))]
538 "s390_match_ccmode(insn, CCSmode)"
543 [(set_attr "op_type" "RR,RS,RSY")])
545 (define_insn "*tstsi_cconly2"
546 [(set (reg CC_REGNUM)
547 (compare (match_operand:SI 0 "register_operand" "d")
548 (match_operand:SI 1 "const0_operand" "")))]
549 "s390_match_ccmode(insn, CCSmode)"
551 [(set_attr "op_type" "RR")])
553 (define_insn "*tst<mode>CCT"
554 [(set (reg CC_REGNUM)
555 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
556 (match_operand:HQI 1 "const0_operand" "")))
557 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
559 "s390_match_ccmode(insn, CCTmode)"
562 icmy\t%2,<icm_lo>,%S0
564 [(set_attr "op_type" "RS,RSY,RI")])
566 (define_insn "*tsthiCCT_cconly"
567 [(set (reg CC_REGNUM)
568 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
569 (match_operand:HI 1 "const0_operand" "")))
570 (clobber (match_scratch:HI 2 "=d,d,X"))]
571 "s390_match_ccmode(insn, CCTmode)"
576 [(set_attr "op_type" "RS,RSY,RI")])
578 (define_insn "*tstqiCCT_cconly"
579 [(set (reg CC_REGNUM)
580 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
581 (match_operand:QI 1 "const0_operand" "")))]
582 "s390_match_ccmode(insn, CCTmode)"
587 [(set_attr "op_type" "SI,SIY,RI")])
589 (define_insn "*tst<mode>"
590 [(set (reg CC_REGNUM)
591 (compare (match_operand:HQI 0 "s_operand" "Q,S")
592 (match_operand:HQI 1 "const0_operand" "")))
593 (set (match_operand:HQI 2 "register_operand" "=d,d")
595 "s390_match_ccmode(insn, CCSmode)"
598 icmy\t%2,<icm_lo>,%S0"
599 [(set_attr "op_type" "RS,RSY")])
601 (define_insn "*tst<mode>_cconly"
602 [(set (reg CC_REGNUM)
603 (compare (match_operand:HQI 0 "s_operand" "Q,S")
604 (match_operand:HQI 1 "const0_operand" "")))
605 (clobber (match_scratch:HQI 2 "=d,d"))]
606 "s390_match_ccmode(insn, CCSmode)"
609 icmy\t%2,<icm_lo>,%S0"
610 [(set_attr "op_type" "RS,RSY")])
613 ; Compare (equality) instructions
615 (define_insn "*cmpdi_cct"
616 [(set (reg CC_REGNUM)
617 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
618 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
619 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
626 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
628 (define_insn "*cmpsi_cct"
629 [(set (reg CC_REGNUM)
630 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
631 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
632 "s390_match_ccmode (insn, CCTmode)"
640 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
643 ; Compare (signed) instructions
645 (define_insn "*cmpdi_ccs_sign"
646 [(set (reg CC_REGNUM)
647 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
648 (match_operand:DI 0 "register_operand" "d,d")))]
649 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
653 [(set_attr "op_type" "RRE,RXY")])
655 (define_insn "*cmpdi_ccs"
656 [(set (reg CC_REGNUM)
657 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
658 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
659 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
665 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
667 (define_insn "*cmpsi_ccs_sign"
668 [(set (reg CC_REGNUM)
669 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
670 (match_operand:SI 0 "register_operand" "d,d")))]
671 "s390_match_ccmode(insn, CCSRmode)"
675 [(set_attr "op_type" "RX,RXY")])
677 (define_insn "*cmpsi_ccs"
678 [(set (reg CC_REGNUM)
679 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
680 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
681 "s390_match_ccmode(insn, CCSmode)"
688 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
691 ; Compare (unsigned) instructions
693 (define_insn "*cmpdi_ccu_zero"
694 [(set (reg CC_REGNUM)
695 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
696 (match_operand:DI 0 "register_operand" "d,d")))]
697 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
701 [(set_attr "op_type" "RRE,RXY")])
703 (define_insn "*cmpdi_ccu"
704 [(set (reg CC_REGNUM)
705 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
706 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
707 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
714 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
716 (define_insn "*cmpsi_ccu"
717 [(set (reg CC_REGNUM)
718 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
719 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
720 "s390_match_ccmode (insn, CCUmode)"
728 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
730 (define_insn "*cmphi_ccu"
731 [(set (reg CC_REGNUM)
732 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
733 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
734 "s390_match_ccmode (insn, CCUmode)
735 && !register_operand (operands[1], HImode)"
741 [(set_attr "op_type" "RS,RSY,SS,SS")])
743 (define_insn "*cmpqi_ccu"
744 [(set (reg CC_REGNUM)
745 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
746 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
747 "s390_match_ccmode (insn, CCUmode)
748 && !register_operand (operands[1], QImode)"
756 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
759 ; Block compare (CLC) instruction patterns.
762 [(set (reg CC_REGNUM)
763 (compare (match_operand:BLK 0 "memory_operand" "Q")
764 (match_operand:BLK 1 "memory_operand" "Q")))
765 (use (match_operand 2 "const_int_operand" "n"))]
766 "s390_match_ccmode (insn, CCUmode)
767 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
768 "clc\t%O0(%2,%R0),%S1"
769 [(set_attr "op_type" "SS")])
772 [(set (reg CC_REGNUM)
773 (compare (match_operand 0 "memory_operand" "")
774 (match_operand 1 "memory_operand" "")))]
776 && s390_match_ccmode (insn, CCUmode)
777 && GET_MODE (operands[0]) == GET_MODE (operands[1])
778 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
780 [(set (match_dup 0) (match_dup 1))
781 (use (match_dup 2))])]
783 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
784 operands[0] = adjust_address (operands[0], BLKmode, 0);
785 operands[1] = adjust_address (operands[1], BLKmode, 0);
787 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
788 operands[0], operands[1]);
789 operands[0] = SET_DEST (PATTERN (curr_insn));
793 ; (DF|SF) instructions
795 (define_insn "*cmp<mode>_ccs_0"
796 [(set (reg CC_REGNUM)
797 (compare (match_operand:FPR 0 "register_operand" "f")
798 (match_operand:FPR 1 "const0_operand" "")))]
799 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
801 [(set_attr "op_type" "RRE")
802 (set_attr "type" "fsimp<mode>")])
804 (define_insn "*cmp<mode>_ccs_0_ibm"
805 [(set (reg CC_REGNUM)
806 (compare (match_operand:FPR 0 "register_operand" "f")
807 (match_operand:FPR 1 "const0_operand" "")))]
808 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
810 [(set_attr "op_type" "RR")
811 (set_attr "type" "fsimp<mode>")])
813 (define_insn "*cmp<mode>_ccs"
814 [(set (reg CC_REGNUM)
815 (compare (match_operand:FPR 0 "register_operand" "f,f")
816 (match_operand:FPR 1 "general_operand" "f,R")))]
817 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
821 [(set_attr "op_type" "RRE,RXE")
822 (set_attr "type" "fsimp<mode>")])
824 (define_insn "*cmp<mode>_ccs_ibm"
825 [(set (reg CC_REGNUM)
826 (compare (match_operand:FPR 0 "register_operand" "f,f")
827 (match_operand:FPR 1 "general_operand" "f,R")))]
828 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
832 [(set_attr "op_type" "RR,RX")
833 (set_attr "type" "fsimp<mode>")])
837 ;;- Move instructions.
841 ; movti instruction pattern(s).
845 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
846 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
854 [(set_attr "op_type" "RSY,RSY,*,*,SS")
855 (set_attr "type" "lm,stm,*,*,*")])
858 [(set (match_operand:TI 0 "nonimmediate_operand" "")
859 (match_operand:TI 1 "general_operand" ""))]
860 "TARGET_64BIT && reload_completed
861 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
862 [(set (match_dup 2) (match_dup 4))
863 (set (match_dup 3) (match_dup 5))]
865 operands[2] = operand_subword (operands[0], 0, 0, TImode);
866 operands[3] = operand_subword (operands[0], 1, 0, TImode);
867 operands[4] = operand_subword (operands[1], 0, 0, TImode);
868 operands[5] = operand_subword (operands[1], 1, 0, TImode);
872 [(set (match_operand:TI 0 "nonimmediate_operand" "")
873 (match_operand:TI 1 "general_operand" ""))]
874 "TARGET_64BIT && reload_completed
875 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
876 [(set (match_dup 2) (match_dup 4))
877 (set (match_dup 3) (match_dup 5))]
879 operands[2] = operand_subword (operands[0], 1, 0, TImode);
880 operands[3] = operand_subword (operands[0], 0, 0, TImode);
881 operands[4] = operand_subword (operands[1], 1, 0, TImode);
882 operands[5] = operand_subword (operands[1], 0, 0, TImode);
886 [(set (match_operand:TI 0 "register_operand" "")
887 (match_operand:TI 1 "memory_operand" ""))]
888 "TARGET_64BIT && reload_completed
889 && !s_operand (operands[1], VOIDmode)"
890 [(set (match_dup 0) (match_dup 1))]
892 rtx addr = operand_subword (operands[0], 1, 0, TImode);
893 s390_load_address (addr, XEXP (operands[1], 0));
894 operands[1] = replace_equiv_address (operands[1], addr);
897 (define_expand "reload_outti"
898 [(parallel [(match_operand:TI 0 "" "")
899 (match_operand:TI 1 "register_operand" "d")
900 (match_operand:DI 2 "register_operand" "=&a")])]
903 gcc_assert (MEM_P (operands[0]));
904 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
905 operands[0] = replace_equiv_address (operands[0], operands[2]);
906 emit_move_insn (operands[0], operands[1]);
911 ; movdi instruction pattern(s).
914 (define_expand "movdi"
915 [(set (match_operand:DI 0 "general_operand" "")
916 (match_operand:DI 1 "general_operand" ""))]
919 /* Handle symbolic constants. */
920 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
921 emit_symbolic_move (operands);
924 (define_insn "*movdi_larl"
925 [(set (match_operand:DI 0 "register_operand" "=d")
926 (match_operand:DI 1 "larl_operand" "X"))]
928 && !FP_REG_P (operands[0])"
930 [(set_attr "op_type" "RIL")
931 (set_attr "type" "larl")])
933 (define_insn "*movdi_64extimm"
934 [(set (match_operand:DI 0 "nonimmediate_operand"
935 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
936 (match_operand:DI 1 "general_operand"
937 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
938 "TARGET_64BIT && TARGET_EXTIMM"
962 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
963 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
964 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
965 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
967 (define_insn "*movdi_64"
968 [(set (match_operand:DI 0 "nonimmediate_operand"
969 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
970 (match_operand:DI 1 "general_operand"
971 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
972 "TARGET_64BIT && !TARGET_EXTIMM"
993 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
994 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
995 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
996 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
999 [(set (match_operand:DI 0 "register_operand" "")
1000 (match_operand:DI 1 "register_operand" ""))]
1001 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1002 [(set (match_dup 2) (match_dup 3))
1003 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1004 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1005 "operands[2] = gen_lowpart (SImode, operands[0]);
1006 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1009 [(set (match_operand:DI 0 "register_operand" "")
1010 (match_operand:DI 1 "register_operand" ""))]
1011 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1012 && dead_or_set_p (insn, operands[1])"
1013 [(set (match_dup 3) (match_dup 2))
1014 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1015 (set (match_dup 4) (match_dup 2))]
1016 "operands[2] = gen_lowpart (SImode, operands[1]);
1017 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1020 [(set (match_operand:DI 0 "register_operand" "")
1021 (match_operand:DI 1 "register_operand" ""))]
1022 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1023 && !dead_or_set_p (insn, operands[1])"
1024 [(set (match_dup 3) (match_dup 2))
1025 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1026 (set (match_dup 4) (match_dup 2))
1027 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1028 "operands[2] = gen_lowpart (SImode, operands[1]);
1029 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1031 (define_insn "*movdi_31"
1032 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1033 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1048 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1049 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1052 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1053 (match_operand:DI 1 "general_operand" ""))]
1054 "!TARGET_64BIT && reload_completed
1055 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1056 [(set (match_dup 2) (match_dup 4))
1057 (set (match_dup 3) (match_dup 5))]
1059 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1060 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1061 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1062 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1066 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1067 (match_operand:DI 1 "general_operand" ""))]
1068 "!TARGET_64BIT && reload_completed
1069 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1070 [(set (match_dup 2) (match_dup 4))
1071 (set (match_dup 3) (match_dup 5))]
1073 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1074 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1075 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1076 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1080 [(set (match_operand:DI 0 "register_operand" "")
1081 (match_operand:DI 1 "memory_operand" ""))]
1082 "!TARGET_64BIT && reload_completed
1083 && !FP_REG_P (operands[0])
1084 && !s_operand (operands[1], VOIDmode)"
1085 [(set (match_dup 0) (match_dup 1))]
1087 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1088 s390_load_address (addr, XEXP (operands[1], 0));
1089 operands[1] = replace_equiv_address (operands[1], addr);
1092 (define_expand "reload_outdi"
1093 [(parallel [(match_operand:DI 0 "" "")
1094 (match_operand:DI 1 "register_operand" "d")
1095 (match_operand:SI 2 "register_operand" "=&a")])]
1098 gcc_assert (MEM_P (operands[0]));
1099 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1100 operands[0] = replace_equiv_address (operands[0], operands[2]);
1101 emit_move_insn (operands[0], operands[1]);
1106 [(set (match_operand:DI 0 "register_operand" "")
1107 (mem:DI (match_operand 1 "address_operand" "")))]
1109 && !FP_REG_P (operands[0])
1110 && GET_CODE (operands[1]) == SYMBOL_REF
1111 && CONSTANT_POOL_ADDRESS_P (operands[1])
1112 && get_pool_mode (operands[1]) == DImode
1113 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1114 [(set (match_dup 0) (match_dup 2))]
1115 "operands[2] = get_pool_constant (operands[1]);")
1117 (define_insn "*la_64"
1118 [(set (match_operand:DI 0 "register_operand" "=d,d")
1119 (match_operand:QI 1 "address_operand" "U,W"))]
1124 [(set_attr "op_type" "RX,RXY")
1125 (set_attr "type" "la")])
1129 [(set (match_operand:DI 0 "register_operand" "")
1130 (match_operand:QI 1 "address_operand" ""))
1131 (clobber (reg:CC CC_REGNUM))])]
1133 && preferred_la_operand_p (operands[1], const0_rtx)"
1134 [(set (match_dup 0) (match_dup 1))]
1138 [(set (match_operand:DI 0 "register_operand" "")
1139 (match_operand:DI 1 "register_operand" ""))
1142 (plus:DI (match_dup 0)
1143 (match_operand:DI 2 "nonmemory_operand" "")))
1144 (clobber (reg:CC CC_REGNUM))])]
1146 && !reg_overlap_mentioned_p (operands[0], operands[2])
1147 && preferred_la_operand_p (operands[1], operands[2])"
1148 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1151 (define_expand "reload_indi"
1152 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1153 (match_operand:DI 1 "s390_plus_operand" "")
1154 (match_operand:DI 2 "register_operand" "=&a")])]
1157 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1162 ; movsi instruction pattern(s).
1165 (define_expand "movsi"
1166 [(set (match_operand:SI 0 "general_operand" "")
1167 (match_operand:SI 1 "general_operand" ""))]
1170 /* Handle symbolic constants. */
1171 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1172 emit_symbolic_move (operands);
1175 (define_insn "*movsi_larl"
1176 [(set (match_operand:SI 0 "register_operand" "=d")
1177 (match_operand:SI 1 "larl_operand" "X"))]
1178 "!TARGET_64BIT && TARGET_CPU_ZARCH
1179 && !FP_REG_P (operands[0])"
1181 [(set_attr "op_type" "RIL")
1182 (set_attr "type" "larl")])
1184 (define_insn "*movsi_zarch"
1185 [(set (match_operand:SI 0 "nonimmediate_operand"
1186 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1187 (match_operand:SI 1 "general_operand"
1188 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1211 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1212 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1213 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1214 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1216 (define_insn "*movsi_esa"
1217 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1218 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1233 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1234 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1237 [(set (match_operand:SI 0 "register_operand" "")
1238 (mem:SI (match_operand 1 "address_operand" "")))]
1239 "!FP_REG_P (operands[0])
1240 && GET_CODE (operands[1]) == SYMBOL_REF
1241 && CONSTANT_POOL_ADDRESS_P (operands[1])
1242 && get_pool_mode (operands[1]) == SImode
1243 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1244 [(set (match_dup 0) (match_dup 2))]
1245 "operands[2] = get_pool_constant (operands[1]);")
1247 (define_insn "*la_31"
1248 [(set (match_operand:SI 0 "register_operand" "=d,d")
1249 (match_operand:QI 1 "address_operand" "U,W"))]
1250 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1254 [(set_attr "op_type" "RX,RXY")
1255 (set_attr "type" "la")])
1259 [(set (match_operand:SI 0 "register_operand" "")
1260 (match_operand:QI 1 "address_operand" ""))
1261 (clobber (reg:CC CC_REGNUM))])]
1263 && preferred_la_operand_p (operands[1], const0_rtx)"
1264 [(set (match_dup 0) (match_dup 1))]
1268 [(set (match_operand:SI 0 "register_operand" "")
1269 (match_operand:SI 1 "register_operand" ""))
1272 (plus:SI (match_dup 0)
1273 (match_operand:SI 2 "nonmemory_operand" "")))
1274 (clobber (reg:CC CC_REGNUM))])]
1276 && !reg_overlap_mentioned_p (operands[0], operands[2])
1277 && preferred_la_operand_p (operands[1], operands[2])"
1278 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1281 (define_insn "*la_31_and"
1282 [(set (match_operand:SI 0 "register_operand" "=d,d")
1283 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1284 (const_int 2147483647)))]
1289 [(set_attr "op_type" "RX,RXY")
1290 (set_attr "type" "la")])
1292 (define_insn_and_split "*la_31_and_cc"
1293 [(set (match_operand:SI 0 "register_operand" "=d")
1294 (and:SI (match_operand:QI 1 "address_operand" "p")
1295 (const_int 2147483647)))
1296 (clobber (reg:CC CC_REGNUM))]
1299 "&& reload_completed"
1301 (and:SI (match_dup 1) (const_int 2147483647)))]
1303 [(set_attr "op_type" "RX")
1304 (set_attr "type" "la")])
1306 (define_insn "force_la_31"
1307 [(set (match_operand:SI 0 "register_operand" "=d,d")
1308 (match_operand:QI 1 "address_operand" "U,W"))
1309 (use (const_int 0))]
1314 [(set_attr "op_type" "RX")
1315 (set_attr "type" "la")])
1317 (define_expand "reload_insi"
1318 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1319 (match_operand:SI 1 "s390_plus_operand" "")
1320 (match_operand:SI 2 "register_operand" "=&a")])]
1323 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1328 ; movhi instruction pattern(s).
1331 (define_expand "movhi"
1332 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1333 (match_operand:HI 1 "general_operand" ""))]
1336 /* Make it explicit that loading a register from memory
1337 always sign-extends (at least) to SImode. */
1338 if (optimize && !no_new_pseudos
1339 && register_operand (operands[0], VOIDmode)
1340 && GET_CODE (operands[1]) == MEM)
1342 rtx tmp = gen_reg_rtx (SImode);
1343 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1344 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1345 operands[1] = gen_lowpart (HImode, tmp);
1349 (define_insn "*movhi"
1350 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1351 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1361 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1362 (set_attr "type" "lr,*,*,*,store,store,*")])
1365 [(set (match_operand:HI 0 "register_operand" "")
1366 (mem:HI (match_operand 1 "address_operand" "")))]
1367 "GET_CODE (operands[1]) == SYMBOL_REF
1368 && CONSTANT_POOL_ADDRESS_P (operands[1])
1369 && get_pool_mode (operands[1]) == HImode
1370 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1371 [(set (match_dup 0) (match_dup 2))]
1372 "operands[2] = get_pool_constant (operands[1]);")
1375 ; movqi instruction pattern(s).
1378 (define_expand "movqi"
1379 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1380 (match_operand:QI 1 "general_operand" ""))]
1383 /* On z/Architecture, zero-extending from memory to register
1384 is just as fast as a QImode load. */
1385 if (TARGET_ZARCH && optimize && !no_new_pseudos
1386 && register_operand (operands[0], VOIDmode)
1387 && GET_CODE (operands[1]) == MEM)
1389 rtx tmp = gen_reg_rtx (word_mode);
1390 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1391 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1392 operands[1] = gen_lowpart (QImode, tmp);
1396 (define_insn "*movqi"
1397 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1398 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1410 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1411 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1414 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1415 (mem:QI (match_operand 1 "address_operand" "")))]
1416 "GET_CODE (operands[1]) == SYMBOL_REF
1417 && CONSTANT_POOL_ADDRESS_P (operands[1])
1418 && get_pool_mode (operands[1]) == QImode
1419 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1420 [(set (match_dup 0) (match_dup 2))]
1421 "operands[2] = get_pool_constant (operands[1]);")
1424 ; movstrictqi instruction pattern(s).
1427 (define_insn "*movstrictqi"
1428 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1429 (match_operand:QI 1 "memory_operand" "R,T"))]
1434 [(set_attr "op_type" "RX,RXY")])
1437 ; movstricthi instruction pattern(s).
1440 (define_insn "*movstricthi"
1441 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1442 (match_operand:HI 1 "memory_operand" "Q,S"))
1443 (clobber (reg:CC CC_REGNUM))]
1448 [(set_attr "op_type" "RS,RSY")])
1451 ; movstrictsi instruction pattern(s).
1454 (define_insn "movstrictsi"
1455 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1456 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1463 [(set_attr "op_type" "RR,RX,RXY,RRE")
1464 (set_attr "type" "lr,load,load,*")])
1467 ; movdf instruction pattern(s).
1470 (define_expand "movdf"
1471 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1472 (match_operand:DF 1 "general_operand" ""))]
1476 (define_insn "*movdf_64"
1477 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1478 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1491 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1492 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1494 (define_insn "*movdf_31"
1495 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1496 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1512 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1513 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1514 lm,lm,stm,stm,*,*,*")])
1517 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1518 (match_operand:DF 1 "general_operand" ""))]
1519 "!TARGET_64BIT && reload_completed
1520 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1521 [(set (match_dup 2) (match_dup 4))
1522 (set (match_dup 3) (match_dup 5))]
1524 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1525 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1526 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1527 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1531 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1532 (match_operand:DF 1 "general_operand" ""))]
1533 "!TARGET_64BIT && reload_completed
1534 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1535 [(set (match_dup 2) (match_dup 4))
1536 (set (match_dup 3) (match_dup 5))]
1538 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1539 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1540 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1541 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1545 [(set (match_operand:DF 0 "register_operand" "")
1546 (match_operand:DF 1 "memory_operand" ""))]
1547 "!TARGET_64BIT && reload_completed
1548 && !FP_REG_P (operands[0])
1549 && !s_operand (operands[1], VOIDmode)"
1550 [(set (match_dup 0) (match_dup 1))]
1552 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1553 s390_load_address (addr, XEXP (operands[1], 0));
1554 operands[1] = replace_equiv_address (operands[1], addr);
1557 (define_expand "reload_outdf"
1558 [(parallel [(match_operand:DF 0 "" "")
1559 (match_operand:DF 1 "register_operand" "d")
1560 (match_operand:SI 2 "register_operand" "=&a")])]
1563 gcc_assert (MEM_P (operands[0]));
1564 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1565 operands[0] = replace_equiv_address (operands[0], operands[2]);
1566 emit_move_insn (operands[0], operands[1]);
1571 ; movsf instruction pattern(s).
1574 (define_insn "movsf"
1575 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1576 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1591 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1592 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1593 lr,load,load,store,store,*")])
1596 ; movcc instruction pattern
1599 (define_insn "movcc"
1600 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1601 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1611 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1612 (set_attr "type" "lr,*,*,store,store,load,load")])
1615 ; Block move (MVC) patterns.
1619 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1620 (match_operand:BLK 1 "memory_operand" "Q"))
1621 (use (match_operand 2 "const_int_operand" "n"))]
1622 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1623 "mvc\t%O0(%2,%R0),%S1"
1624 [(set_attr "op_type" "SS")])
1627 [(set (match_operand 0 "memory_operand" "")
1628 (match_operand 1 "memory_operand" ""))]
1630 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1631 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1633 [(set (match_dup 0) (match_dup 1))
1634 (use (match_dup 2))])]
1636 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1637 operands[0] = adjust_address (operands[0], BLKmode, 0);
1638 operands[1] = adjust_address (operands[1], BLKmode, 0);
1643 [(set (match_operand:BLK 0 "memory_operand" "")
1644 (match_operand:BLK 1 "memory_operand" ""))
1645 (use (match_operand 2 "const_int_operand" ""))])
1647 [(set (match_operand:BLK 3 "memory_operand" "")
1648 (match_operand:BLK 4 "memory_operand" ""))
1649 (use (match_operand 5 "const_int_operand" ""))])]
1650 "s390_offset_p (operands[0], operands[3], operands[2])
1651 && s390_offset_p (operands[1], operands[4], operands[2])
1652 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1654 [(set (match_dup 6) (match_dup 7))
1655 (use (match_dup 8))])]
1656 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1657 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1658 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1662 ; load_multiple pattern(s).
1664 ; ??? Due to reload problems with replacing registers inside match_parallel
1665 ; we currently support load_multiple/store_multiple only after reload.
1668 (define_expand "load_multiple"
1669 [(match_par_dup 3 [(set (match_operand 0 "" "")
1670 (match_operand 1 "" ""))
1671 (use (match_operand 2 "" ""))])]
1674 enum machine_mode mode;
1680 /* Support only loading a constant number of fixed-point registers from
1681 memory and only bother with this if more than two */
1682 if (GET_CODE (operands[2]) != CONST_INT
1683 || INTVAL (operands[2]) < 2
1684 || INTVAL (operands[2]) > 16
1685 || GET_CODE (operands[1]) != MEM
1686 || GET_CODE (operands[0]) != REG
1687 || REGNO (operands[0]) >= 16)
1690 count = INTVAL (operands[2]);
1691 regno = REGNO (operands[0]);
1692 mode = GET_MODE (operands[0]);
1693 if (mode != SImode && mode != word_mode)
1696 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1699 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1701 from = XEXP (operands[1], 0);
1704 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1705 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1706 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1708 from = XEXP (XEXP (operands[1], 0), 0);
1709 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1716 from = force_reg (Pmode, XEXP (operands[1], 0));
1720 for (i = 0; i < count; i++)
1721 XVECEXP (operands[3], 0, i)
1722 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1723 change_address (operands[1], mode,
1724 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1727 (define_insn "*load_multiple_di"
1728 [(match_parallel 0 "load_multiple_operation"
1729 [(set (match_operand:DI 1 "register_operand" "=r")
1730 (match_operand:DI 2 "s_operand" "QS"))])]
1731 "reload_completed && word_mode == DImode"
1733 int words = XVECLEN (operands[0], 0);
1734 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1735 return "lmg\t%1,%0,%S2";
1737 [(set_attr "op_type" "RSY")
1738 (set_attr "type" "lm")])
1740 (define_insn "*load_multiple_si"
1741 [(match_parallel 0 "load_multiple_operation"
1742 [(set (match_operand:SI 1 "register_operand" "=r,r")
1743 (match_operand:SI 2 "s_operand" "Q,S"))])]
1746 int words = XVECLEN (operands[0], 0);
1747 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1748 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1750 [(set_attr "op_type" "RS,RSY")
1751 (set_attr "type" "lm")])
1754 ; store multiple pattern(s).
1757 (define_expand "store_multiple"
1758 [(match_par_dup 3 [(set (match_operand 0 "" "")
1759 (match_operand 1 "" ""))
1760 (use (match_operand 2 "" ""))])]
1763 enum machine_mode mode;
1769 /* Support only storing a constant number of fixed-point registers to
1770 memory and only bother with this if more than two. */
1771 if (GET_CODE (operands[2]) != CONST_INT
1772 || INTVAL (operands[2]) < 2
1773 || INTVAL (operands[2]) > 16
1774 || GET_CODE (operands[0]) != MEM
1775 || GET_CODE (operands[1]) != REG
1776 || REGNO (operands[1]) >= 16)
1779 count = INTVAL (operands[2]);
1780 regno = REGNO (operands[1]);
1781 mode = GET_MODE (operands[1]);
1782 if (mode != SImode && mode != word_mode)
1785 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1789 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1791 to = XEXP (operands[0], 0);
1794 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1795 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1796 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1798 to = XEXP (XEXP (operands[0], 0), 0);
1799 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1806 to = force_reg (Pmode, XEXP (operands[0], 0));
1810 for (i = 0; i < count; i++)
1811 XVECEXP (operands[3], 0, i)
1812 = gen_rtx_SET (VOIDmode,
1813 change_address (operands[0], mode,
1814 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1815 gen_rtx_REG (mode, regno + i));
1818 (define_insn "*store_multiple_di"
1819 [(match_parallel 0 "store_multiple_operation"
1820 [(set (match_operand:DI 1 "s_operand" "=QS")
1821 (match_operand:DI 2 "register_operand" "r"))])]
1822 "reload_completed && word_mode == DImode"
1824 int words = XVECLEN (operands[0], 0);
1825 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1826 return "stmg\t%2,%0,%S1";
1828 [(set_attr "op_type" "RSY")
1829 (set_attr "type" "stm")])
1832 (define_insn "*store_multiple_si"
1833 [(match_parallel 0 "store_multiple_operation"
1834 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1835 (match_operand:SI 2 "register_operand" "r,r"))])]
1838 int words = XVECLEN (operands[0], 0);
1839 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1840 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1842 [(set_attr "op_type" "RS,RSY")
1843 (set_attr "type" "stm")])
1846 ;; String instructions.
1849 (define_insn "*execute"
1850 [(match_parallel 0 ""
1851 [(unspec [(match_operand 1 "register_operand" "a")
1852 (match_operand:BLK 2 "memory_operand" "R")
1853 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1854 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1855 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1857 [(set_attr "op_type" "RX")
1858 (set_attr "type" "cs")])
1862 ; strlenM instruction pattern(s).
1865 (define_expand "strlen<mode>"
1866 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1869 (unspec:P [(const_int 0)
1870 (match_operand:BLK 1 "memory_operand" "")
1872 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1873 (clobber (scratch:P))
1874 (clobber (reg:CC CC_REGNUM))])
1876 [(set (match_operand:P 0 "register_operand" "")
1877 (minus:P (match_dup 4) (match_dup 5)))
1878 (clobber (reg:CC CC_REGNUM))])]
1881 operands[4] = gen_reg_rtx (Pmode);
1882 operands[5] = gen_reg_rtx (Pmode);
1883 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1884 operands[1] = replace_equiv_address (operands[1], operands[5]);
1887 (define_insn "*strlen<mode>"
1888 [(set (match_operand:P 0 "register_operand" "=a")
1889 (unspec:P [(match_operand:P 2 "general_operand" "0")
1890 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1892 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1893 (clobber (match_scratch:P 1 "=a"))
1894 (clobber (reg:CC CC_REGNUM))]
1896 "srst\t%0,%1\;jo\t.-4"
1897 [(set_attr "length" "8")
1898 (set_attr "type" "vs")])
1901 ; cmpstrM instruction pattern(s).
1904 (define_expand "cmpstrsi"
1905 [(set (reg:SI 0) (const_int 0))
1907 [(clobber (match_operand 3 "" ""))
1908 (clobber (match_dup 4))
1909 (set (reg:CCU CC_REGNUM)
1910 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1911 (match_operand:BLK 2 "memory_operand" "")))
1914 [(set (match_operand:SI 0 "register_operand" "=d")
1915 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1916 (clobber (reg:CC CC_REGNUM))])]
1919 /* As the result of CMPINT is inverted compared to what we need,
1920 we have to swap the operands. */
1921 rtx op1 = operands[2];
1922 rtx op2 = operands[1];
1923 rtx addr1 = gen_reg_rtx (Pmode);
1924 rtx addr2 = gen_reg_rtx (Pmode);
1926 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1927 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1928 operands[1] = replace_equiv_address_nv (op1, addr1);
1929 operands[2] = replace_equiv_address_nv (op2, addr2);
1930 operands[3] = addr1;
1931 operands[4] = addr2;
1934 (define_insn "*cmpstr<mode>"
1935 [(clobber (match_operand:P 0 "register_operand" "=d"))
1936 (clobber (match_operand:P 1 "register_operand" "=d"))
1937 (set (reg:CCU CC_REGNUM)
1938 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1939 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1942 "clst\t%0,%1\;jo\t.-4"
1943 [(set_attr "length" "8")
1944 (set_attr "type" "vs")])
1947 ; movmemM instruction pattern(s).
1950 (define_expand "movmem<mode>"
1951 [(set (match_operand:BLK 0 "memory_operand" "")
1952 (match_operand:BLK 1 "memory_operand" ""))
1953 (use (match_operand:GPR 2 "general_operand" ""))
1954 (match_operand 3 "" "")]
1956 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1958 ; Move a block that is up to 256 bytes in length.
1959 ; The block length is taken as (operands[2] % 256) + 1.
1961 (define_expand "movmem_short"
1963 [(set (match_operand:BLK 0 "memory_operand" "")
1964 (match_operand:BLK 1 "memory_operand" ""))
1965 (use (match_operand 2 "nonmemory_operand" ""))
1966 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1967 (clobber (match_dup 3))])]
1969 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1971 (define_insn "*movmem_short"
1972 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1973 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1974 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1975 (use (match_operand 3 "immediate_operand" "X,R,X"))
1976 (clobber (match_scratch 4 "=X,X,&a"))]
1977 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1978 && GET_MODE (operands[4]) == Pmode"
1980 [(set_attr "type" "cs")])
1983 [(set (match_operand:BLK 0 "memory_operand" "")
1984 (match_operand:BLK 1 "memory_operand" ""))
1985 (use (match_operand 2 "const_int_operand" ""))
1986 (use (match_operand 3 "immediate_operand" ""))
1987 (clobber (scratch))]
1990 [(set (match_dup 0) (match_dup 1))
1991 (use (match_dup 2))])]
1992 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1995 [(set (match_operand:BLK 0 "memory_operand" "")
1996 (match_operand:BLK 1 "memory_operand" ""))
1997 (use (match_operand 2 "register_operand" ""))
1998 (use (match_operand 3 "memory_operand" ""))
1999 (clobber (scratch))]
2002 [(unspec [(match_dup 2) (match_dup 3)
2003 (const_int 0)] UNSPEC_EXECUTE)
2004 (set (match_dup 0) (match_dup 1))
2005 (use (const_int 1))])]
2009 [(set (match_operand:BLK 0 "memory_operand" "")
2010 (match_operand:BLK 1 "memory_operand" ""))
2011 (use (match_operand 2 "register_operand" ""))
2012 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2013 (clobber (match_operand 3 "register_operand" ""))]
2014 "reload_completed && TARGET_CPU_ZARCH"
2015 [(set (match_dup 3) (label_ref (match_dup 4)))
2017 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2018 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2019 (set (match_dup 0) (match_dup 1))
2020 (use (const_int 1))])]
2021 "operands[4] = gen_label_rtx ();")
2023 ; Move a block of arbitrary length.
2025 (define_expand "movmem_long"
2027 [(clobber (match_dup 2))
2028 (clobber (match_dup 3))
2029 (set (match_operand:BLK 0 "memory_operand" "")
2030 (match_operand:BLK 1 "memory_operand" ""))
2031 (use (match_operand 2 "general_operand" ""))
2033 (clobber (reg:CC CC_REGNUM))])]
2036 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2037 rtx reg0 = gen_reg_rtx (dword_mode);
2038 rtx reg1 = gen_reg_rtx (dword_mode);
2039 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2040 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2041 rtx len0 = gen_lowpart (Pmode, reg0);
2042 rtx len1 = gen_lowpart (Pmode, reg1);
2044 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2045 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2046 emit_move_insn (len0, operands[2]);
2048 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2049 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2050 emit_move_insn (len1, operands[2]);
2052 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2053 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2058 (define_insn "*movmem_long"
2059 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2060 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2061 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2062 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2065 (clobber (reg:CC CC_REGNUM))]
2067 "mvcle\t%0,%1,0\;jo\t.-4"
2068 [(set_attr "length" "8")
2069 (set_attr "type" "vs")])
2072 ; setmemM instruction pattern(s).
2075 (define_expand "setmem<mode>"
2076 [(set (match_operand:BLK 0 "memory_operand" "")
2077 (match_operand:QI 2 "general_operand" ""))
2078 (use (match_operand:GPR 1 "general_operand" ""))
2079 (match_operand 3 "" "")]
2081 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2083 ; Clear a block that is up to 256 bytes in length.
2084 ; The block length is taken as (operands[1] % 256) + 1.
2086 (define_expand "clrmem_short"
2088 [(set (match_operand:BLK 0 "memory_operand" "")
2090 (use (match_operand 1 "nonmemory_operand" ""))
2091 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2092 (clobber (match_dup 2))
2093 (clobber (reg:CC CC_REGNUM))])]
2095 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2097 (define_insn "*clrmem_short"
2098 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2100 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2101 (use (match_operand 2 "immediate_operand" "X,R,X"))
2102 (clobber (match_scratch 3 "=X,X,&a"))
2103 (clobber (reg:CC CC_REGNUM))]
2104 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2105 && GET_MODE (operands[3]) == Pmode"
2107 [(set_attr "type" "cs")])
2110 [(set (match_operand:BLK 0 "memory_operand" "")
2112 (use (match_operand 1 "const_int_operand" ""))
2113 (use (match_operand 2 "immediate_operand" ""))
2115 (clobber (reg:CC CC_REGNUM))]
2118 [(set (match_dup 0) (const_int 0))
2120 (clobber (reg:CC CC_REGNUM))])]
2121 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2124 [(set (match_operand:BLK 0 "memory_operand" "")
2126 (use (match_operand 1 "register_operand" ""))
2127 (use (match_operand 2 "memory_operand" ""))
2129 (clobber (reg:CC CC_REGNUM))]
2132 [(unspec [(match_dup 1) (match_dup 2)
2133 (const_int 0)] UNSPEC_EXECUTE)
2134 (set (match_dup 0) (const_int 0))
2136 (clobber (reg:CC CC_REGNUM))])]
2140 [(set (match_operand:BLK 0 "memory_operand" "")
2142 (use (match_operand 1 "register_operand" ""))
2143 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2144 (clobber (match_operand 2 "register_operand" ""))
2145 (clobber (reg:CC CC_REGNUM))]
2146 "reload_completed && TARGET_CPU_ZARCH"
2147 [(set (match_dup 2) (label_ref (match_dup 3)))
2149 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2150 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2151 (set (match_dup 0) (const_int 0))
2153 (clobber (reg:CC CC_REGNUM))])]
2154 "operands[3] = gen_label_rtx ();")
2156 ; Initialize a block of arbitrary length with (operands[2] % 256).
2158 (define_expand "setmem_long"
2160 [(clobber (match_dup 1))
2161 (set (match_operand:BLK 0 "memory_operand" "")
2162 (match_operand 2 "setmem_operand" ""))
2163 (use (match_operand 1 "general_operand" ""))
2165 (clobber (reg:CC CC_REGNUM))])]
2168 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2169 rtx reg0 = gen_reg_rtx (dword_mode);
2170 rtx reg1 = gen_reg_rtx (dword_mode);
2171 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2172 rtx len0 = gen_lowpart (Pmode, reg0);
2174 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2175 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2176 emit_move_insn (len0, operands[1]);
2178 emit_move_insn (reg1, const0_rtx);
2180 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2185 (define_insn "*setmem_long"
2186 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2187 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2188 (match_operand 2 "setmem_operand" "Y"))
2190 (use (match_operand:<DBL> 1 "register_operand" "d"))
2191 (clobber (reg:CC CC_REGNUM))]
2193 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2194 [(set_attr "length" "8")
2195 (set_attr "type" "vs")])
2198 ; cmpmemM instruction pattern(s).
2201 (define_expand "cmpmemsi"
2202 [(set (match_operand:SI 0 "register_operand" "")
2203 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2204 (match_operand:BLK 2 "memory_operand" "") ) )
2205 (use (match_operand:SI 3 "general_operand" ""))
2206 (use (match_operand:SI 4 "" ""))]
2208 "s390_expand_cmpmem (operands[0], operands[1],
2209 operands[2], operands[3]); DONE;")
2211 ; Compare a block that is up to 256 bytes in length.
2212 ; The block length is taken as (operands[2] % 256) + 1.
2214 (define_expand "cmpmem_short"
2216 [(set (reg:CCU CC_REGNUM)
2217 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2218 (match_operand:BLK 1 "memory_operand" "")))
2219 (use (match_operand 2 "nonmemory_operand" ""))
2220 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2221 (clobber (match_dup 3))])]
2223 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2225 (define_insn "*cmpmem_short"
2226 [(set (reg:CCU CC_REGNUM)
2227 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2228 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2229 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2230 (use (match_operand 3 "immediate_operand" "X,R,X"))
2231 (clobber (match_scratch 4 "=X,X,&a"))]
2232 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2233 && GET_MODE (operands[4]) == Pmode"
2235 [(set_attr "type" "cs")])
2238 [(set (reg:CCU CC_REGNUM)
2239 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2240 (match_operand:BLK 1 "memory_operand" "")))
2241 (use (match_operand 2 "const_int_operand" ""))
2242 (use (match_operand 3 "immediate_operand" ""))
2243 (clobber (scratch))]
2246 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2247 (use (match_dup 2))])]
2248 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2251 [(set (reg:CCU CC_REGNUM)
2252 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2253 (match_operand:BLK 1 "memory_operand" "")))
2254 (use (match_operand 2 "register_operand" ""))
2255 (use (match_operand 3 "memory_operand" ""))
2256 (clobber (scratch))]
2259 [(unspec [(match_dup 2) (match_dup 3)
2260 (const_int 0)] UNSPEC_EXECUTE)
2261 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2262 (use (const_int 1))])]
2266 [(set (reg:CCU CC_REGNUM)
2267 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2268 (match_operand:BLK 1 "memory_operand" "")))
2269 (use (match_operand 2 "register_operand" ""))
2270 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2271 (clobber (match_operand 3 "register_operand" ""))]
2272 "reload_completed && TARGET_CPU_ZARCH"
2273 [(set (match_dup 3) (label_ref (match_dup 4)))
2275 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2276 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2277 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2278 (use (const_int 1))])]
2279 "operands[4] = gen_label_rtx ();")
2281 ; Compare a block of arbitrary length.
2283 (define_expand "cmpmem_long"
2285 [(clobber (match_dup 2))
2286 (clobber (match_dup 3))
2287 (set (reg:CCU CC_REGNUM)
2288 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2289 (match_operand:BLK 1 "memory_operand" "")))
2290 (use (match_operand 2 "general_operand" ""))
2291 (use (match_dup 3))])]
2294 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2295 rtx reg0 = gen_reg_rtx (dword_mode);
2296 rtx reg1 = gen_reg_rtx (dword_mode);
2297 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2298 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2299 rtx len0 = gen_lowpart (Pmode, reg0);
2300 rtx len1 = gen_lowpart (Pmode, reg1);
2302 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2303 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2304 emit_move_insn (len0, operands[2]);
2306 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2307 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2308 emit_move_insn (len1, operands[2]);
2310 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2311 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2316 (define_insn "*cmpmem_long"
2317 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2318 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2319 (set (reg:CCU CC_REGNUM)
2320 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2321 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2323 (use (match_dup 3))]
2325 "clcle\t%0,%1,0\;jo\t.-4"
2326 [(set_attr "length" "8")
2327 (set_attr "type" "vs")])
2329 ; Convert CCUmode condition code to integer.
2330 ; Result is zero if EQ, positive if LTU, negative if GTU.
2332 (define_insn_and_split "cmpint"
2333 [(set (match_operand:SI 0 "register_operand" "=d")
2334 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2336 (clobber (reg:CC CC_REGNUM))]
2340 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2342 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2343 (clobber (reg:CC CC_REGNUM))])])
2345 (define_insn_and_split "*cmpint_cc"
2346 [(set (reg CC_REGNUM)
2347 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2350 (set (match_operand:SI 0 "register_operand" "=d")
2351 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2352 "s390_match_ccmode (insn, CCSmode)"
2354 "&& reload_completed"
2355 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2357 [(set (match_dup 2) (match_dup 3))
2358 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2360 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2361 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2362 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2365 (define_insn_and_split "*cmpint_sign"
2366 [(set (match_operand:DI 0 "register_operand" "=d")
2367 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2369 (clobber (reg:CC CC_REGNUM))]
2372 "&& reload_completed"
2373 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2375 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2376 (clobber (reg:CC CC_REGNUM))])])
2378 (define_insn_and_split "*cmpint_sign_cc"
2379 [(set (reg CC_REGNUM)
2380 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2381 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2383 (const_int 32)) (const_int 32))
2385 (set (match_operand:DI 0 "register_operand" "=d")
2386 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2387 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2389 "&& reload_completed"
2390 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2392 [(set (match_dup 2) (match_dup 3))
2393 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2395 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2396 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2397 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2402 ;;- Conversion instructions.
2406 (define_insn "*sethigh<mode>si"
2407 [(set (match_operand:SI 0 "register_operand" "=d,d")
2408 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2409 (clobber (reg:CC CC_REGNUM))]
2412 icm\t%0,<icm_hi>,%S1
2413 icmy\t%0,<icm_hi>,%S1"
2414 [(set_attr "op_type" "RS,RSY")])
2416 (define_insn "*sethighqidi_64"
2417 [(set (match_operand:DI 0 "register_operand" "=d")
2418 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2419 (clobber (reg:CC CC_REGNUM))]
2422 [(set_attr "op_type" "RSY")])
2424 (define_insn "*sethighqidi_31"
2425 [(set (match_operand:DI 0 "register_operand" "=d,d")
2426 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2427 (clobber (reg:CC CC_REGNUM))]
2432 [(set_attr "op_type" "RS,RSY")])
2434 (define_insn_and_split "*extractqi"
2435 [(set (match_operand:SI 0 "register_operand" "=d")
2436 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2437 (match_operand 2 "const_int_operand" "n")
2439 (clobber (reg:CC CC_REGNUM))]
2441 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2443 "&& reload_completed"
2445 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2446 (clobber (reg:CC CC_REGNUM))])
2447 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2449 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2450 operands[1] = change_address (operands[1], QImode, 0);
2453 (define_insn_and_split "*extracthi"
2454 [(set (match_operand:SI 0 "register_operand" "=d")
2455 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2456 (match_operand 2 "const_int_operand" "n")
2458 (clobber (reg:CC CC_REGNUM))]
2460 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2462 "&& reload_completed"
2464 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2465 (clobber (reg:CC CC_REGNUM))])
2466 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2468 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2469 operands[1] = change_address (operands[1], HImode, 0);
2473 ; extendsidi2 instruction pattern(s).
2476 (define_expand "extendsidi2"
2477 [(set (match_operand:DI 0 "register_operand" "")
2478 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2483 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2484 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2485 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2486 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2491 (define_insn "*extendsidi2"
2492 [(set (match_operand:DI 0 "register_operand" "=d,d")
2493 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2498 [(set_attr "op_type" "RRE,RXY")])
2501 ; extend(hi|qi)di2 instruction pattern(s).
2504 (define_expand "extend<mode>di2"
2505 [(set (match_operand:DI 0 "register_operand" "")
2506 (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2511 rtx tmp = gen_reg_rtx (SImode);
2512 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2513 emit_insn (gen_extendsidi2 (operands[0], tmp));
2516 else if (!TARGET_EXTIMM)
2518 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2519 GET_MODE_BITSIZE (<MODE>mode));
2520 operands[1] = gen_lowpart (DImode, operands[1]);
2521 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2522 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2527 (define_insn "*extendhidi2_extimm"
2528 [(set (match_operand:DI 0 "register_operand" "=d,d")
2529 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2530 "TARGET_64BIT && TARGET_EXTIMM"
2534 [(set_attr "op_type" "RRE,RXY")])
2536 (define_insn "*extendhidi2"
2537 [(set (match_operand:DI 0 "register_operand" "=d")
2538 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2541 [(set_attr "op_type" "RXY")])
2543 (define_insn "*extendqidi2_extimm"
2544 [(set (match_operand:DI 0 "register_operand" "=d,d")
2545 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2546 "TARGET_64BIT && TARGET_EXTIMM"
2550 [(set_attr "op_type" "RRE,RXY")])
2552 (define_insn "*extendqidi2"
2553 [(set (match_operand:DI 0 "register_operand" "=d")
2554 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2555 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2557 [(set_attr "op_type" "RXY")])
2559 (define_insn_and_split "*extendqidi2_short_displ"
2560 [(set (match_operand:DI 0 "register_operand" "=d")
2561 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2562 (clobber (reg:CC CC_REGNUM))]
2563 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2565 "&& reload_completed"
2567 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2568 (clobber (reg:CC CC_REGNUM))])
2570 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2571 (clobber (reg:CC CC_REGNUM))])]
2575 ; extend(hi|qi)si2 instruction pattern(s).
2578 (define_expand "extend<mode>si2"
2579 [(set (match_operand:SI 0 "register_operand" "")
2580 (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2585 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2586 GET_MODE_BITSIZE(<MODE>mode));
2587 operands[1] = gen_lowpart (SImode, operands[1]);
2588 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2589 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2594 (define_insn "*extendhisi2_extimm"
2595 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2596 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2602 [(set_attr "op_type" "RRE,RX,RXY")])
2604 (define_insn "*extendhisi2"
2605 [(set (match_operand:SI 0 "register_operand" "=d,d")
2606 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2611 [(set_attr "op_type" "RX,RXY")])
2613 (define_insn "*extendqisi2_extimm"
2614 [(set (match_operand:SI 0 "register_operand" "=d,d")
2615 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2620 [(set_attr "op_type" "RRE,RXY")])
2622 (define_insn "*extendqisi2"
2623 [(set (match_operand:SI 0 "register_operand" "=d")
2624 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2625 "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2627 [(set_attr "op_type" "RXY")])
2629 (define_insn_and_split "*extendqisi2_short_displ"
2630 [(set (match_operand:SI 0 "register_operand" "=d")
2631 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2632 (clobber (reg:CC CC_REGNUM))]
2633 "!TARGET_LONG_DISPLACEMENT"
2635 "&& reload_completed"
2637 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2638 (clobber (reg:CC CC_REGNUM))])
2640 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2641 (clobber (reg:CC CC_REGNUM))])]
2645 ; extendqihi2 instruction pattern(s).
2650 ; zero_extendsidi2 instruction pattern(s).
2653 (define_expand "zero_extendsidi2"
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2660 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2661 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2662 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2667 (define_insn "*zero_extendsidi2"
2668 [(set (match_operand:DI 0 "register_operand" "=d,d")
2669 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2674 [(set_attr "op_type" "RRE,RXY")])
2677 ; zero_extend(hi|qi)di2 instruction pattern(s).
2680 (define_expand "zero_extend<mode>di2"
2681 [(set (match_operand:DI 0 "register_operand" "")
2682 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2687 rtx tmp = gen_reg_rtx (SImode);
2688 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2689 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2692 else if (!TARGET_EXTIMM)
2694 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2695 GET_MODE_BITSIZE(<MODE>mode));
2696 operands[1] = gen_lowpart (DImode, operands[1]);
2697 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2698 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2703 (define_insn "*zero_extend<mode>di2_extimm"
2704 [(set (match_operand:DI 0 "register_operand" "=d,d")
2705 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2706 "TARGET_64BIT && TARGET_EXTIMM"
2710 [(set_attr "op_type" "RRE,RXY")])
2712 (define_insn "*zero_extend<mode>di2"
2713 [(set (match_operand:DI 0 "register_operand" "=d")
2714 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2715 "TARGET_64BIT && !TARGET_EXTIMM"
2717 [(set_attr "op_type" "RXY")])
2720 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2723 (define_insn "*llgt_sidi"
2724 [(set (match_operand:DI 0 "register_operand" "=d")
2725 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2726 (const_int 2147483647)))]
2729 [(set_attr "op_type" "RXE")])
2731 (define_insn_and_split "*llgt_sidi_split"
2732 [(set (match_operand:DI 0 "register_operand" "=d")
2733 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2734 (const_int 2147483647)))
2735 (clobber (reg:CC CC_REGNUM))]
2738 "&& reload_completed"
2740 (and:DI (subreg:DI (match_dup 1) 0)
2741 (const_int 2147483647)))]
2744 (define_insn "*llgt_sisi"
2745 [(set (match_operand:SI 0 "register_operand" "=d,d")
2746 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2747 (const_int 2147483647)))]
2752 [(set_attr "op_type" "RRE,RXE")])
2754 (define_insn "*llgt_didi"
2755 [(set (match_operand:DI 0 "register_operand" "=d,d")
2756 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2757 (const_int 2147483647)))]
2762 [(set_attr "op_type" "RRE,RXE")])
2765 [(set (match_operand:GPR 0 "register_operand" "")
2766 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2767 (const_int 2147483647)))
2768 (clobber (reg:CC CC_REGNUM))]
2769 "TARGET_ZARCH && reload_completed"
2771 (and:GPR (match_dup 1)
2772 (const_int 2147483647)))]
2776 ; zero_extend(hi|qi)si2 instruction pattern(s).
2779 (define_expand "zero_extend<mode>si2"
2780 [(set (match_operand:SI 0 "register_operand" "")
2781 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2786 operands[1] = gen_lowpart (SImode, operands[1]);
2787 emit_insn (gen_andsi3 (operands[0], operands[1],
2788 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2793 (define_insn "*zero_extend<mode>si2_extimm"
2794 [(set (match_operand:SI 0 "register_operand" "=d,d")
2795 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2800 [(set_attr "op_type" "RRE,RXY")])
2802 (define_insn "*zero_extend<mode>si2_64"
2803 [(set (match_operand:SI 0 "register_operand" "=d")
2804 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2805 "TARGET_ZARCH && !TARGET_EXTIMM"
2807 [(set_attr "op_type" "RXY")])
2809 (define_insn_and_split "*zero_extendhisi2_31"
2810 [(set (match_operand:SI 0 "register_operand" "=&d")
2811 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2812 (clobber (reg:CC CC_REGNUM))]
2815 "&& reload_completed"
2816 [(set (match_dup 0) (const_int 0))
2818 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2819 (clobber (reg:CC CC_REGNUM))])]
2820 "operands[2] = gen_lowpart (HImode, operands[0]);")
2822 (define_insn_and_split "*zero_extendqisi2_31"
2823 [(set (match_operand:SI 0 "register_operand" "=&d")
2824 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2827 "&& reload_completed"
2828 [(set (match_dup 0) (const_int 0))
2829 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2830 "operands[2] = gen_lowpart (QImode, operands[0]);")
2833 ; zero_extendqihi2 instruction pattern(s).
2836 (define_expand "zero_extendqihi2"
2837 [(set (match_operand:HI 0 "register_operand" "")
2838 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2839 "TARGET_ZARCH && !TARGET_EXTIMM"
2841 operands[1] = gen_lowpart (HImode, operands[1]);
2842 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2846 (define_insn "*zero_extendqihi2_64"
2847 [(set (match_operand:HI 0 "register_operand" "=d")
2848 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2849 "TARGET_ZARCH && !TARGET_EXTIMM"
2851 [(set_attr "op_type" "RXY")])
2853 (define_insn_and_split "*zero_extendqihi2_31"
2854 [(set (match_operand:HI 0 "register_operand" "=&d")
2855 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2858 "&& reload_completed"
2859 [(set (match_dup 0) (const_int 0))
2860 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2861 "operands[2] = gen_lowpart (QImode, operands[0]);")
2865 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2868 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2869 [(set (match_operand:GPR 0 "register_operand" "")
2870 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2871 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2873 rtx label1 = gen_label_rtx ();
2874 rtx label2 = gen_label_rtx ();
2875 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2876 REAL_VALUE_TYPE cmp, sub;
2878 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2879 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2880 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2882 emit_insn (gen_cmp<FPR:mode> (operands[1],
2883 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2884 emit_jump_insn (gen_blt (label1));
2885 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2886 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2887 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2891 emit_label (label1);
2892 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2893 operands[1], GEN_INT(5)));
2894 emit_label (label2);
2898 (define_expand "fix_trunc<FPR:mode>di2"
2899 [(set (match_operand:DI 0 "register_operand" "")
2900 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2901 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2903 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2904 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2909 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2910 [(set (match_operand:GPR 0 "register_operand" "=d")
2911 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2912 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2913 (clobber (reg:CC CC_REGNUM))]
2914 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2915 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2916 [(set_attr "op_type" "RRE")
2917 (set_attr "type" "ftoi")])
2920 ; fix_truncdfsi2 instruction pattern(s).
2923 (define_expand "fix_truncdfsi2"
2924 [(set (match_operand:SI 0 "register_operand" "")
2925 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2928 if (TARGET_IBM_FLOAT)
2930 /* This is the algorithm from POP chapter A.5.7.2. */
2932 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2933 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2934 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2936 operands[1] = force_reg (DFmode, operands[1]);
2937 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2938 two31r, two32, temp));
2942 operands[1] = force_reg (DFmode, operands[1]);
2943 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2949 (define_insn "fix_truncdfsi2_ibm"
2950 [(set (match_operand:SI 0 "register_operand" "=d")
2951 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2952 (use (match_operand:DI 2 "immediate_operand" "m"))
2953 (use (match_operand:DI 3 "immediate_operand" "m"))
2954 (use (match_operand:BLK 4 "memory_operand" "m"))
2955 (clobber (reg:CC CC_REGNUM))]
2956 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2958 output_asm_insn ("sd\t%1,%2", operands);
2959 output_asm_insn ("aw\t%1,%3", operands);
2960 output_asm_insn ("std\t%1,%4", operands);
2961 output_asm_insn ("xi\t%N4,128", operands);
2964 [(set_attr "length" "20")])
2967 ; fix_truncsfsi2 instruction pattern(s).
2970 (define_expand "fix_truncsfsi2"
2971 [(set (match_operand:SI 0 "register_operand" "")
2972 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2975 if (TARGET_IBM_FLOAT)
2977 /* Convert to DFmode and then use the POP algorithm. */
2978 rtx temp = gen_reg_rtx (DFmode);
2979 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2980 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2984 operands[1] = force_reg (SFmode, operands[1]);
2985 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2992 ; floatdi(df|sf)2 instruction pattern(s).
2995 (define_insn "floatdi<mode>2"
2996 [(set (match_operand:FPR 0 "register_operand" "=f")
2997 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2998 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3000 [(set_attr "op_type" "RRE")
3001 (set_attr "type" "itof" )])
3004 ; floatsidf2 instruction pattern(s).
3007 (define_expand "floatsidf2"
3008 [(set (match_operand:DF 0 "register_operand" "")
3009 (float:DF (match_operand:SI 1 "register_operand" "")))]
3012 if (TARGET_IBM_FLOAT)
3014 /* This is the algorithm from POP chapter A.5.7.1. */
3016 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3017 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3019 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3024 (define_insn "floatsidf2_ieee"
3025 [(set (match_operand:DF 0 "register_operand" "=f")
3026 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3027 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3029 [(set_attr "op_type" "RRE")
3030 (set_attr "type" "itof" )])
3032 (define_insn "floatsidf2_ibm"
3033 [(set (match_operand:DF 0 "register_operand" "=f")
3034 (float:DF (match_operand:SI 1 "register_operand" "d")))
3035 (use (match_operand:DI 2 "immediate_operand" "m"))
3036 (use (match_operand:BLK 3 "memory_operand" "m"))
3037 (clobber (reg:CC CC_REGNUM))]
3038 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3040 output_asm_insn ("st\t%1,%N3", operands);
3041 output_asm_insn ("xi\t%N3,128", operands);
3042 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3043 output_asm_insn ("ld\t%0,%3", operands);
3046 [(set_attr "length" "20")])
3049 ; floatsisf2 instruction pattern(s).
3052 (define_expand "floatsisf2"
3053 [(set (match_operand:SF 0 "register_operand" "")
3054 (float:SF (match_operand:SI 1 "register_operand" "")))]
3057 if (TARGET_IBM_FLOAT)
3059 /* Use the POP algorithm to convert to DFmode and then truncate. */
3060 rtx temp = gen_reg_rtx (DFmode);
3061 emit_insn (gen_floatsidf2 (temp, operands[1]));
3062 emit_insn (gen_truncdfsf2 (operands[0], temp));
3067 (define_insn "floatsisf2_ieee"
3068 [(set (match_operand:SF 0 "register_operand" "=f")
3069 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3070 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3072 [(set_attr "op_type" "RRE")
3073 (set_attr "type" "itof" )])
3076 ; truncdfsf2 instruction pattern(s).
3079 (define_expand "truncdfsf2"
3080 [(set (match_operand:SF 0 "register_operand" "")
3081 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3085 (define_insn "truncdfsf2_ieee"
3086 [(set (match_operand:SF 0 "register_operand" "=f")
3087 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3088 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3090 [(set_attr "op_type" "RRE")])
3092 (define_insn "truncdfsf2_ibm"
3093 [(set (match_operand:SF 0 "register_operand" "=f,f")
3094 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3095 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3099 [(set_attr "op_type" "RR,RX")
3100 (set_attr "type" "floadsf")])
3103 ; extendsfdf2 instruction pattern(s).
3106 (define_expand "extendsfdf2"
3107 [(set (match_operand:DF 0 "register_operand" "")
3108 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3111 if (TARGET_IBM_FLOAT)
3113 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3118 (define_insn "extendsfdf2_ieee"
3119 [(set (match_operand:DF 0 "register_operand" "=f,f")
3120 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3121 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3125 [(set_attr "op_type" "RRE,RXE")
3126 (set_attr "type" "floadsf")])
3128 (define_insn "extendsfdf2_ibm"
3129 [(set (match_operand:DF 0 "register_operand" "=f,f")
3130 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3131 (clobber (reg:CC CC_REGNUM))]
3132 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3134 sdr\t%0,%0\;ler\t%0,%1
3135 sdr\t%0,%0\;le\t%0,%1"
3136 [(set_attr "length" "4,6")
3137 (set_attr "type" "floadsf")])
3141 ;; ARITHMETIC OPERATIONS
3143 ; arithmetic operations set the ConditionCode,
3144 ; because of unpredictable Bits in Register for Halfword and Byte
3145 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3148 ;;- Add instructions.
3152 ; addti3 instruction pattern(s).
3155 (define_insn_and_split "addti3"
3156 [(set (match_operand:TI 0 "register_operand" "=&d")
3157 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3158 (match_operand:TI 2 "general_operand" "do") ) )
3159 (clobber (reg:CC CC_REGNUM))]
3162 "&& reload_completed"
3164 [(set (reg:CCL1 CC_REGNUM)
3165 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3167 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3169 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3170 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3171 (clobber (reg:CC CC_REGNUM))])]
3172 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3173 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3174 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3175 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3176 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3177 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3180 ; adddi3 instruction pattern(s).
3183 (define_insn "*adddi3_sign"
3184 [(set (match_operand:DI 0 "register_operand" "=d,d")
3185 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3186 (match_operand:DI 1 "register_operand" "0,0")))
3187 (clobber (reg:CC CC_REGNUM))]
3192 [(set_attr "op_type" "RRE,RXY")])
3194 (define_insn "*adddi3_zero_cc"
3195 [(set (reg CC_REGNUM)
3196 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3197 (match_operand:DI 1 "register_operand" "0,0"))
3199 (set (match_operand:DI 0 "register_operand" "=d,d")
3200 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3201 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3205 [(set_attr "op_type" "RRE,RXY")])
3207 (define_insn "*adddi3_zero_cconly"
3208 [(set (reg CC_REGNUM)
3209 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3210 (match_operand:DI 1 "register_operand" "0,0"))
3212 (clobber (match_scratch:DI 0 "=d,d"))]
3213 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3217 [(set_attr "op_type" "RRE,RXY")])
3219 (define_insn "*adddi3_zero"
3220 [(set (match_operand:DI 0 "register_operand" "=d,d")
3221 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3222 (match_operand:DI 1 "register_operand" "0,0")))
3223 (clobber (reg:CC CC_REGNUM))]
3228 [(set_attr "op_type" "RRE,RXY")])
3230 (define_insn "*adddi3_imm_cc"
3231 [(set (reg CC_REGNUM)
3232 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3233 (match_operand:DI 2 "const_int_operand" "K,Os"))
3235 (set (match_operand:DI 0 "register_operand" "=d,d")
3236 (plus:DI (match_dup 1) (match_dup 2)))]
3238 && s390_match_ccmode (insn, CCAmode)
3239 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3240 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3244 [(set_attr "op_type" "RI,RIL")])
3246 (define_insn "*adddi3_carry1_cc"
3247 [(set (reg CC_REGNUM)
3248 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3249 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3251 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3252 (plus:DI (match_dup 1) (match_dup 2)))]
3253 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3259 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3261 (define_insn "*adddi3_carry1_cconly"
3262 [(set (reg CC_REGNUM)
3263 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3264 (match_operand:DI 2 "general_operand" "d,m"))
3266 (clobber (match_scratch:DI 0 "=d,d"))]
3267 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3271 [(set_attr "op_type" "RRE,RXY")])
3273 (define_insn "*adddi3_carry2_cc"
3274 [(set (reg CC_REGNUM)
3275 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3276 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3278 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3279 (plus:DI (match_dup 1) (match_dup 2)))]
3280 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3286 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3288 (define_insn "*adddi3_carry2_cconly"
3289 [(set (reg CC_REGNUM)
3290 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3291 (match_operand:DI 2 "general_operand" "d,m"))
3293 (clobber (match_scratch:DI 0 "=d,d"))]
3294 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3298 [(set_attr "op_type" "RRE,RXY")])
3300 (define_insn "*adddi3_cc"
3301 [(set (reg CC_REGNUM)
3302 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3303 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3305 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3306 (plus:DI (match_dup 1) (match_dup 2)))]
3307 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3313 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3315 (define_insn "*adddi3_cconly"
3316 [(set (reg CC_REGNUM)
3317 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3318 (match_operand:DI 2 "general_operand" "d,m"))
3320 (clobber (match_scratch:DI 0 "=d,d"))]
3321 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3325 [(set_attr "op_type" "RRE,RXY")])
3327 (define_insn "*adddi3_cconly2"
3328 [(set (reg CC_REGNUM)
3329 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3330 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3331 (clobber (match_scratch:DI 0 "=d,d"))]
3332 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3336 [(set_attr "op_type" "RRE,RXY")])
3338 (define_insn "*adddi3_64"
3339 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3340 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3341 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3342 (clobber (reg:CC CC_REGNUM))]
3350 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3352 (define_insn_and_split "*adddi3_31z"
3353 [(set (match_operand:DI 0 "register_operand" "=&d")
3354 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3355 (match_operand:DI 2 "general_operand" "do") ) )
3356 (clobber (reg:CC CC_REGNUM))]
3357 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3359 "&& reload_completed"
3361 [(set (reg:CCL1 CC_REGNUM)
3362 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3364 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3366 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3367 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3368 (clobber (reg:CC CC_REGNUM))])]
3369 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3370 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3371 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3372 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3373 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3374 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3376 (define_insn_and_split "*adddi3_31"
3377 [(set (match_operand:DI 0 "register_operand" "=&d")
3378 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3379 (match_operand:DI 2 "general_operand" "do") ) )
3380 (clobber (reg:CC CC_REGNUM))]
3383 "&& reload_completed"
3385 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3386 (clobber (reg:CC CC_REGNUM))])
3388 [(set (reg:CCL1 CC_REGNUM)
3389 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3391 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3393 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3395 (label_ref (match_dup 9))))
3397 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3398 (clobber (reg:CC CC_REGNUM))])
3400 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3401 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3402 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3403 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3404 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3405 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3406 operands[9] = gen_label_rtx ();")
3408 (define_expand "adddi3"
3410 [(set (match_operand:DI 0 "register_operand" "")
3411 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3412 (match_operand:DI 2 "general_operand" "")))
3413 (clobber (reg:CC CC_REGNUM))])]
3418 ; addsi3 instruction pattern(s).
3421 (define_insn "*addsi3_imm_cc"
3422 [(set (reg CC_REGNUM)
3423 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3424 (match_operand:SI 2 "const_int_operand" "K,Os"))
3426 (set (match_operand:SI 0 "register_operand" "=d,d")
3427 (plus:SI (match_dup 1) (match_dup 2)))]
3428 "s390_match_ccmode (insn, CCAmode)
3429 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3430 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3431 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3435 [(set_attr "op_type" "RI,RIL")])
3437 (define_insn "*addsi3_carry1_cc"
3438 [(set (reg CC_REGNUM)
3439 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3440 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3442 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3443 (plus:SI (match_dup 1) (match_dup 2)))]
3444 "s390_match_ccmode (insn, CCL1mode)"
3450 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3452 (define_insn "*addsi3_carry1_cconly"
3453 [(set (reg CC_REGNUM)
3454 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3455 (match_operand:SI 2 "general_operand" "d,R,T"))
3457 (clobber (match_scratch:SI 0 "=d,d,d"))]
3458 "s390_match_ccmode (insn, CCL1mode)"
3463 [(set_attr "op_type" "RR,RX,RXY")])
3465 (define_insn "*addsi3_carry2_cc"
3466 [(set (reg CC_REGNUM)
3467 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3468 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3470 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3471 (plus:SI (match_dup 1) (match_dup 2)))]
3472 "s390_match_ccmode (insn, CCL1mode)"
3478 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3480 (define_insn "*addsi3_carry2_cconly"
3481 [(set (reg CC_REGNUM)
3482 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3483 (match_operand:SI 2 "general_operand" "d,R,T"))
3485 (clobber (match_scratch:SI 0 "=d,d,d"))]
3486 "s390_match_ccmode (insn, CCL1mode)"
3491 [(set_attr "op_type" "RR,RX,RXY")])
3493 (define_insn "*addsi3_cc"
3494 [(set (reg CC_REGNUM)
3495 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3496 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3498 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3499 (plus:SI (match_dup 1) (match_dup 2)))]
3500 "s390_match_ccmode (insn, CCLmode)"
3506 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3508 (define_insn "*addsi3_cconly"
3509 [(set (reg CC_REGNUM)
3510 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3511 (match_operand:SI 2 "general_operand" "d,R,T"))
3513 (clobber (match_scratch:SI 0 "=d,d,d"))]
3514 "s390_match_ccmode (insn, CCLmode)"
3519 [(set_attr "op_type" "RR,RX,RXY")])
3521 (define_insn "*addsi3_cconly2"
3522 [(set (reg CC_REGNUM)
3523 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3524 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3525 (clobber (match_scratch:SI 0 "=d,d,d"))]
3526 "s390_match_ccmode (insn, CCLmode)"
3531 [(set_attr "op_type" "RR,RX,RXY")])
3533 (define_insn "*addsi3_sign"
3534 [(set (match_operand:SI 0 "register_operand" "=d,d")
3535 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3536 (match_operand:SI 1 "register_operand" "0,0")))
3537 (clobber (reg:CC CC_REGNUM))]
3542 [(set_attr "op_type" "RX,RXY")])
3544 (define_insn "addsi3"
3545 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3546 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3547 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3548 (clobber (reg:CC CC_REGNUM))]
3556 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3559 ; add(df|sf)3 instruction pattern(s).
3562 (define_expand "add<mode>3"
3564 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3565 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3566 (match_operand:FPR 2 "general_operand" "f,R")))
3567 (clobber (reg:CC CC_REGNUM))])]
3571 (define_insn "*add<mode>3"
3572 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3573 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3574 (match_operand:FPR 2 "general_operand" "f,R")))
3575 (clobber (reg:CC CC_REGNUM))]
3576 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3580 [(set_attr "op_type" "RRE,RXE")
3581 (set_attr "type" "fsimp<mode>")])
3583 (define_insn "*add<mode>3_cc"
3584 [(set (reg CC_REGNUM)
3585 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3586 (match_operand:FPR 2 "general_operand" "f,R"))
3587 (match_operand:FPR 3 "const0_operand" "")))
3588 (set (match_operand:FPR 0 "register_operand" "=f,f")
3589 (plus:FPR (match_dup 1) (match_dup 2)))]
3590 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3594 [(set_attr "op_type" "RRE,RXE")
3595 (set_attr "type" "fsimp<mode>")])
3597 (define_insn "*add<mode>3_cconly"
3598 [(set (reg CC_REGNUM)
3599 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3600 (match_operand:FPR 2 "general_operand" "f,R"))
3601 (match_operand:FPR 3 "const0_operand" "")))
3602 (clobber (match_scratch:FPR 0 "=f,f"))]
3603 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3607 [(set_attr "op_type" "RRE,RXE")
3608 (set_attr "type" "fsimp<mode>")])
3610 (define_insn "*add<mode>3_ibm"
3611 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3612 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3613 (match_operand:FPR 2 "general_operand" "f,R")))
3614 (clobber (reg:CC CC_REGNUM))]
3615 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3619 [(set_attr "op_type" "RR,RX")
3620 (set_attr "type" "fsimp<mode>")])
3624 ;;- Subtract instructions.
3628 ; subti3 instruction pattern(s).
3631 (define_insn_and_split "subti3"
3632 [(set (match_operand:TI 0 "register_operand" "=&d")
3633 (minus:TI (match_operand:TI 1 "register_operand" "0")
3634 (match_operand:TI 2 "general_operand" "do") ) )
3635 (clobber (reg:CC CC_REGNUM))]
3638 "&& reload_completed"
3640 [(set (reg:CCL2 CC_REGNUM)
3641 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3643 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3645 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3646 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3647 (clobber (reg:CC CC_REGNUM))])]
3648 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3649 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3650 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3651 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3652 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3653 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3656 ; subdi3 instruction pattern(s).
3659 (define_insn "*subdi3_sign"
3660 [(set (match_operand:DI 0 "register_operand" "=d,d")
3661 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3662 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3663 (clobber (reg:CC CC_REGNUM))]
3668 [(set_attr "op_type" "RRE,RXY")])
3670 (define_insn "*subdi3_zero_cc"
3671 [(set (reg CC_REGNUM)
3672 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3673 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3675 (set (match_operand:DI 0 "register_operand" "=d,d")
3676 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3677 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3681 [(set_attr "op_type" "RRE,RXY")])
3683 (define_insn "*subdi3_zero_cconly"
3684 [(set (reg CC_REGNUM)
3685 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3686 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3688 (clobber (match_scratch:DI 0 "=d,d"))]
3689 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3693 [(set_attr "op_type" "RRE,RXY")])
3695 (define_insn "*subdi3_zero"
3696 [(set (match_operand:DI 0 "register_operand" "=d,d")
3697 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3698 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3699 (clobber (reg:CC CC_REGNUM))]
3704 [(set_attr "op_type" "RRE,RXY")])
3706 (define_insn "*subdi3_borrow_cc"
3707 [(set (reg CC_REGNUM)
3708 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3709 (match_operand:DI 2 "general_operand" "d,m"))
3711 (set (match_operand:DI 0 "register_operand" "=d,d")
3712 (minus:DI (match_dup 1) (match_dup 2)))]
3713 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3717 [(set_attr "op_type" "RRE,RXY")])
3719 (define_insn "*subdi3_borrow_cconly"
3720 [(set (reg CC_REGNUM)
3721 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3722 (match_operand:DI 2 "general_operand" "d,m"))
3724 (clobber (match_scratch:DI 0 "=d,d"))]
3725 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3729 [(set_attr "op_type" "RRE,RXY")])
3731 (define_insn "*subdi3_cc"
3732 [(set (reg CC_REGNUM)
3733 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3734 (match_operand:DI 2 "general_operand" "d,m"))
3736 (set (match_operand:DI 0 "register_operand" "=d,d")
3737 (minus:DI (match_dup 1) (match_dup 2)))]
3738 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3742 [(set_attr "op_type" "RRE,RXY")])
3744 (define_insn "*subdi3_cc2"
3745 [(set (reg CC_REGNUM)
3746 (compare (match_operand:DI 1 "register_operand" "0,0")
3747 (match_operand:DI 2 "general_operand" "d,m")))
3748 (set (match_operand:DI 0 "register_operand" "=d,d")
3749 (minus:DI (match_dup 1) (match_dup 2)))]
3750 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3754 [(set_attr "op_type" "RRE,RXY")])
3756 (define_insn "*subdi3_cconly"
3757 [(set (reg CC_REGNUM)
3758 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3759 (match_operand:DI 2 "general_operand" "d,m"))
3761 (clobber (match_scratch:DI 0 "=d,d"))]
3762 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3766 [(set_attr "op_type" "RRE,RXY")])
3768 (define_insn "*subdi3_cconly2"
3769 [(set (reg CC_REGNUM)
3770 (compare (match_operand:DI 1 "register_operand" "0,0")
3771 (match_operand:DI 2 "general_operand" "d,m")))
3772 (clobber (match_scratch:DI 0 "=d,d"))]
3773 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3777 [(set_attr "op_type" "RRE,RXY")])
3779 (define_insn "*subdi3_64"
3780 [(set (match_operand:DI 0 "register_operand" "=d,d")
3781 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3782 (match_operand:DI 2 "general_operand" "d,m") ) )
3783 (clobber (reg:CC CC_REGNUM))]
3788 [(set_attr "op_type" "RRE,RRE")])
3790 (define_insn_and_split "*subdi3_31z"
3791 [(set (match_operand:DI 0 "register_operand" "=&d")
3792 (minus:DI (match_operand:DI 1 "register_operand" "0")
3793 (match_operand:DI 2 "general_operand" "do") ) )
3794 (clobber (reg:CC CC_REGNUM))]
3795 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3797 "&& reload_completed"
3799 [(set (reg:CCL2 CC_REGNUM)
3800 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3802 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3804 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3805 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3806 (clobber (reg:CC CC_REGNUM))])]
3807 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3808 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3809 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3810 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3811 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3812 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3814 (define_insn_and_split "*subdi3_31"
3815 [(set (match_operand:DI 0 "register_operand" "=&d")
3816 (minus:DI (match_operand:DI 1 "register_operand" "0")
3817 (match_operand:DI 2 "general_operand" "do") ) )
3818 (clobber (reg:CC CC_REGNUM))]
3821 "&& reload_completed"
3823 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3824 (clobber (reg:CC CC_REGNUM))])
3826 [(set (reg:CCL2 CC_REGNUM)
3827 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3829 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3831 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3833 (label_ref (match_dup 9))))
3835 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3836 (clobber (reg:CC CC_REGNUM))])
3838 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3839 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3840 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3841 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3842 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3843 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3844 operands[9] = gen_label_rtx ();")
3846 (define_expand "subdi3"
3848 [(set (match_operand:DI 0 "register_operand" "")
3849 (minus:DI (match_operand:DI 1 "register_operand" "")
3850 (match_operand:DI 2 "general_operand" "")))
3851 (clobber (reg:CC CC_REGNUM))])]
3856 ; subsi3 instruction pattern(s).
3859 (define_insn "*subsi3_borrow_cc"
3860 [(set (reg CC_REGNUM)
3861 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3862 (match_operand:SI 2 "general_operand" "d,R,T"))
3864 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3865 (minus:SI (match_dup 1) (match_dup 2)))]
3866 "s390_match_ccmode (insn, CCL2mode)"
3871 [(set_attr "op_type" "RR,RX,RXY")])
3873 (define_insn "*subsi3_borrow_cconly"
3874 [(set (reg CC_REGNUM)
3875 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3876 (match_operand:SI 2 "general_operand" "d,R,T"))
3878 (clobber (match_scratch:SI 0 "=d,d,d"))]
3879 "s390_match_ccmode (insn, CCL2mode)"
3884 [(set_attr "op_type" "RR,RX,RXY")])
3886 (define_insn "*subsi3_cc"
3887 [(set (reg CC_REGNUM)
3888 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3889 (match_operand:SI 2 "general_operand" "d,R,T"))
3891 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3892 (minus:SI (match_dup 1) (match_dup 2)))]
3893 "s390_match_ccmode (insn, CCLmode)"
3898 [(set_attr "op_type" "RR,RX,RXY")])
3900 (define_insn "*subsi3_cc2"
3901 [(set (reg CC_REGNUM)
3902 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3903 (match_operand:SI 2 "general_operand" "d,R,T")))
3904 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3905 (minus:SI (match_dup 1) (match_dup 2)))]
3906 "s390_match_ccmode (insn, CCL3mode)"
3911 [(set_attr "op_type" "RR,RX,RXY")])
3913 (define_insn "*subsi3_cconly"
3914 [(set (reg CC_REGNUM)
3915 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3916 (match_operand:SI 2 "general_operand" "d,R,T"))
3918 (clobber (match_scratch:SI 0 "=d,d,d"))]
3919 "s390_match_ccmode (insn, CCLmode)"
3924 [(set_attr "op_type" "RR,RX,RXY")])
3926 (define_insn "*subsi3_cconly2"
3927 [(set (reg CC_REGNUM)
3928 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3929 (match_operand:SI 2 "general_operand" "d,R,T")))
3930 (clobber (match_scratch:SI 0 "=d,d,d"))]
3931 "s390_match_ccmode (insn, CCL3mode)"
3936 [(set_attr "op_type" "RR,RX,RXY")])
3938 (define_insn "*subsi3_sign"
3939 [(set (match_operand:SI 0 "register_operand" "=d,d")
3940 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3941 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3942 (clobber (reg:CC CC_REGNUM))]
3947 [(set_attr "op_type" "RX,RXY")])
3949 (define_insn "subsi3"
3950 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3951 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3952 (match_operand:SI 2 "general_operand" "d,R,T")))
3953 (clobber (reg:CC CC_REGNUM))]
3959 [(set_attr "op_type" "RR,RX,RXY")])
3963 ; sub(df|sf)3 instruction pattern(s).
3966 (define_expand "sub<mode>3"
3968 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3969 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3970 (match_operand:FPR 2 "general_operand" "f,R")))
3971 (clobber (reg:CC CC_REGNUM))])]
3975 (define_insn "*sub<mode>3"
3976 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3977 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3978 (match_operand:FPR 2 "general_operand" "f,R")))
3979 (clobber (reg:CC CC_REGNUM))]
3980 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3984 [(set_attr "op_type" "RRE,RXE")
3985 (set_attr "type" "fsimp<mode>")])
3987 (define_insn "*sub<mode>3_cc"
3988 [(set (reg CC_REGNUM)
3989 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3990 (match_operand:FPR 2 "general_operand" "f,R"))
3991 (match_operand:FPR 3 "const0_operand" "")))
3992 (set (match_operand:FPR 0 "register_operand" "=f,f")
3993 (minus:FPR (match_dup 1) (match_dup 2)))]
3994 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3998 [(set_attr "op_type" "RRE,RXE")
3999 (set_attr "type" "fsimp<mode>")])
4001 (define_insn "*sub<mode>3_cconly"
4002 [(set (reg CC_REGNUM)
4003 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4004 (match_operand:FPR 2 "general_operand" "f,R"))
4005 (match_operand:FPR 3 "const0_operand" "")))
4006 (clobber (match_scratch:FPR 0 "=f,f"))]
4007 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4011 [(set_attr "op_type" "RRE,RXE")
4012 (set_attr "type" "fsimp<mode>")])
4014 (define_insn "*sub<mode>3_ibm"
4015 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4016 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4017 (match_operand:FPR 2 "general_operand" "f,R")))
4018 (clobber (reg:CC CC_REGNUM))]
4019 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4023 [(set_attr "op_type" "RR,RX")
4024 (set_attr "type" "fsimp<mode>")])
4028 ;;- Conditional add/subtract instructions.
4032 ; add(di|si)cc instruction pattern(s).
4035 (define_insn "*add<mode>3_alc_cc"
4036 [(set (reg CC_REGNUM)
4038 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4039 (match_operand:GPR 2 "general_operand" "d,m"))
4040 (match_operand:GPR 3 "s390_alc_comparison" ""))
4042 (set (match_operand:GPR 0 "register_operand" "=d,d")
4043 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4044 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4048 [(set_attr "op_type" "RRE,RXY")])
4050 (define_insn "*add<mode>3_alc"
4051 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4052 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4053 (match_operand:GPR 2 "general_operand" "d,m"))
4054 (match_operand:GPR 3 "s390_alc_comparison" "")))
4055 (clobber (reg:CC CC_REGNUM))]
4060 [(set_attr "op_type" "RRE,RXY")])
4062 (define_insn "*sub<mode>3_slb_cc"
4063 [(set (reg CC_REGNUM)
4065 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4066 (match_operand:GPR 2 "general_operand" "d,m"))
4067 (match_operand:GPR 3 "s390_slb_comparison" ""))
4069 (set (match_operand:GPR 0 "register_operand" "=d,d")
4070 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4071 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4075 [(set_attr "op_type" "RRE,RXY")])
4077 (define_insn "*sub<mode>3_slb"
4078 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4079 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4080 (match_operand:GPR 2 "general_operand" "d,m"))
4081 (match_operand:GPR 3 "s390_slb_comparison" "")))
4082 (clobber (reg:CC CC_REGNUM))]
4087 [(set_attr "op_type" "RRE,RXY")])
4089 (define_expand "add<mode>cc"
4090 [(match_operand:GPR 0 "register_operand" "")
4091 (match_operand 1 "comparison_operator" "")
4092 (match_operand:GPR 2 "register_operand" "")
4093 (match_operand:GPR 3 "const_int_operand" "")]
4095 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4096 s390_compare_op0, s390_compare_op1,
4097 operands[0], operands[2],
4098 operands[3])) FAIL; DONE;")
4101 ; scond instruction pattern(s).
4104 (define_insn_and_split "*scond<mode>"
4105 [(set (match_operand:GPR 0 "register_operand" "=&d")
4106 (match_operand:GPR 1 "s390_alc_comparison" ""))
4107 (clobber (reg:CC CC_REGNUM))]
4110 "&& reload_completed"
4111 [(set (match_dup 0) (const_int 0))
4113 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4115 (clobber (reg:CC CC_REGNUM))])]
4118 (define_insn_and_split "*scond<mode>_neg"
4119 [(set (match_operand:GPR 0 "register_operand" "=&d")
4120 (match_operand:GPR 1 "s390_slb_comparison" ""))
4121 (clobber (reg:CC CC_REGNUM))]
4124 "&& reload_completed"
4125 [(set (match_dup 0) (const_int 0))
4127 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4129 (clobber (reg:CC CC_REGNUM))])
4131 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4132 (clobber (reg:CC CC_REGNUM))])]
4136 (define_expand "s<code>"
4137 [(set (match_operand:SI 0 "register_operand" "")
4138 (SCOND (match_dup 0)
4141 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4142 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4144 (define_expand "seq"
4146 [(set (match_operand:SI 0 "register_operand" "=d")
4148 (clobber (reg:CC CC_REGNUM))])
4150 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4151 (clobber (reg:CC CC_REGNUM))])]
4154 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4156 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4157 PUT_MODE (operands[1], SImode);
4160 (define_insn_and_split "*sne"
4161 [(set (match_operand:SI 0 "register_operand" "=d")
4162 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4164 (clobber (reg:CC CC_REGNUM))]
4169 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4170 (clobber (reg:CC CC_REGNUM))])])
4174 ;;- Multiply instructions.
4178 ; muldi3 instruction pattern(s).
4181 (define_insn "*muldi3_sign"
4182 [(set (match_operand:DI 0 "register_operand" "=d,d")
4183 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4184 (match_operand:DI 1 "register_operand" "0,0")))]
4189 [(set_attr "op_type" "RRE,RXY")
4190 (set_attr "type" "imuldi")])
4192 (define_insn "muldi3"
4193 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4194 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4195 (match_operand:DI 2 "general_operand" "d,K,m")))]
4201 [(set_attr "op_type" "RRE,RI,RXY")
4202 (set_attr "type" "imuldi")])
4205 ; mulsi3 instruction pattern(s).
4208 (define_insn "*mulsi3_sign"
4209 [(set (match_operand:SI 0 "register_operand" "=d")
4210 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4211 (match_operand:SI 1 "register_operand" "0")))]
4214 [(set_attr "op_type" "RX")
4215 (set_attr "type" "imulhi")])
4217 (define_insn "mulsi3"
4218 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4219 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4220 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4227 [(set_attr "op_type" "RRE,RI,RX,RXY")
4228 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4231 ; mulsidi3 instruction pattern(s).
4234 (define_insn "mulsidi3"
4235 [(set (match_operand:DI 0 "register_operand" "=d,d")
4236 (mult:DI (sign_extend:DI
4237 (match_operand:SI 1 "register_operand" "%0,0"))
4239 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4244 [(set_attr "op_type" "RR,RX")
4245 (set_attr "type" "imulsi")])
4248 ; umulsidi3 instruction pattern(s).
4251 (define_insn "umulsidi3"
4252 [(set (match_operand:DI 0 "register_operand" "=d,d")
4253 (mult:DI (zero_extend:DI
4254 (match_operand:SI 1 "register_operand" "%0,0"))
4256 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4257 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4261 [(set_attr "op_type" "RRE,RXY")
4262 (set_attr "type" "imulsi")])
4265 ; mul(df|sf)3 instruction pattern(s).
4268 (define_expand "mul<mode>3"
4269 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4270 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4271 (match_operand:FPR 2 "general_operand" "f,R")))]
4275 (define_insn "*mul<mode>3"
4276 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4277 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4278 (match_operand:FPR 2 "general_operand" "f,R")))]
4279 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4283 [(set_attr "op_type" "RRE,RXE")
4284 (set_attr "type" "fmul<mode>")])
4286 (define_insn "*mul<mode>3_ibm"
4287 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4288 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4289 (match_operand:FPR 2 "general_operand" "f,R")))]
4290 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4294 [(set_attr "op_type" "RR,RX")
4295 (set_attr "type" "fmul<mode>")])
4297 (define_insn "*fmadd<mode>"
4298 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4299 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4300 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4301 (match_operand:FPR 3 "register_operand" "0,0")))]
4302 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4306 [(set_attr "op_type" "RRE,RXE")
4307 (set_attr "type" "fmul<mode>")])
4309 (define_insn "*fmsub<mode>"
4310 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4311 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4312 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4313 (match_operand:FPR 3 "register_operand" "0,0")))]
4314 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4318 [(set_attr "op_type" "RRE,RXE")
4319 (set_attr "type" "fmul<mode>")])
4322 ;;- Divide and modulo instructions.
4326 ; divmoddi4 instruction pattern(s).
4329 (define_expand "divmoddi4"
4330 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4331 (div:DI (match_operand:DI 1 "register_operand" "")
4332 (match_operand:DI 2 "general_operand" "")))
4333 (set (match_operand:DI 3 "general_operand" "")
4334 (mod:DI (match_dup 1) (match_dup 2)))])
4335 (clobber (match_dup 4))]
4338 rtx insn, div_equal, mod_equal;
4340 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4341 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4343 operands[4] = gen_reg_rtx(TImode);
4344 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4346 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4348 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4350 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4352 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4357 (define_insn "divmodtidi3"
4358 [(set (match_operand:TI 0 "register_operand" "=d,d")
4362 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4363 (match_operand:DI 2 "general_operand" "d,m")))
4365 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4370 [(set_attr "op_type" "RRE,RXY")
4371 (set_attr "type" "idiv")])
4373 (define_insn "divmodtisi3"
4374 [(set (match_operand:TI 0 "register_operand" "=d,d")
4378 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4380 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4383 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4388 [(set_attr "op_type" "RRE,RXY")
4389 (set_attr "type" "idiv")])
4392 ; udivmoddi4 instruction pattern(s).
4395 (define_expand "udivmoddi4"
4396 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4397 (udiv:DI (match_operand:DI 1 "general_operand" "")
4398 (match_operand:DI 2 "nonimmediate_operand" "")))
4399 (set (match_operand:DI 3 "general_operand" "")
4400 (umod:DI (match_dup 1) (match_dup 2)))])
4401 (clobber (match_dup 4))]
4404 rtx insn, div_equal, mod_equal, equal;
4406 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4407 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4408 equal = gen_rtx_IOR (TImode,
4409 gen_rtx_ASHIFT (TImode,
4410 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4412 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4414 operands[4] = gen_reg_rtx(TImode);
4415 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4416 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4417 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4418 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4420 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4422 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4424 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4426 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4428 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4433 (define_insn "udivmodtidi3"
4434 [(set (match_operand:TI 0 "register_operand" "=d,d")
4439 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4441 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4445 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4450 [(set_attr "op_type" "RRE,RXY")
4451 (set_attr "type" "idiv")])
4454 ; divmodsi4 instruction pattern(s).
4457 (define_expand "divmodsi4"
4458 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4459 (div:SI (match_operand:SI 1 "general_operand" "")
4460 (match_operand:SI 2 "nonimmediate_operand" "")))
4461 (set (match_operand:SI 3 "general_operand" "")
4462 (mod:SI (match_dup 1) (match_dup 2)))])
4463 (clobber (match_dup 4))]
4466 rtx insn, div_equal, mod_equal, equal;
4468 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4469 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4470 equal = gen_rtx_IOR (DImode,
4471 gen_rtx_ASHIFT (DImode,
4472 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4474 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4476 operands[4] = gen_reg_rtx(DImode);
4477 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4478 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4480 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4482 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4484 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4486 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4488 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4493 (define_insn "divmoddisi3"
4494 [(set (match_operand:DI 0 "register_operand" "=d,d")
4499 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4501 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4505 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4510 [(set_attr "op_type" "RR,RX")
4511 (set_attr "type" "idiv")])
4514 ; udivsi3 and umodsi3 instruction pattern(s).
4517 (define_expand "udivmodsi4"
4518 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4519 (udiv:SI (match_operand:SI 1 "general_operand" "")
4520 (match_operand:SI 2 "nonimmediate_operand" "")))
4521 (set (match_operand:SI 3 "general_operand" "")
4522 (umod:SI (match_dup 1) (match_dup 2)))])
4523 (clobber (match_dup 4))]
4524 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4526 rtx insn, div_equal, mod_equal, equal;
4528 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4529 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4530 equal = gen_rtx_IOR (DImode,
4531 gen_rtx_ASHIFT (DImode,
4532 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4534 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4536 operands[4] = gen_reg_rtx(DImode);
4537 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4538 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4539 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4540 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4542 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4544 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4546 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4548 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4550 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4555 (define_insn "udivmoddisi3"
4556 [(set (match_operand:DI 0 "register_operand" "=d,d")
4561 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4563 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4567 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4568 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4572 [(set_attr "op_type" "RRE,RXY")
4573 (set_attr "type" "idiv")])
4575 (define_expand "udivsi3"
4576 [(set (match_operand:SI 0 "register_operand" "=d")
4577 (udiv:SI (match_operand:SI 1 "general_operand" "")
4578 (match_operand:SI 2 "general_operand" "")))
4579 (clobber (match_dup 3))]
4580 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4582 rtx insn, udiv_equal, umod_equal, equal;
4584 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4585 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4586 equal = gen_rtx_IOR (DImode,
4587 gen_rtx_ASHIFT (DImode,
4588 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4590 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4592 operands[3] = gen_reg_rtx (DImode);
4594 if (CONSTANT_P (operands[2]))
4596 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4598 rtx label1 = gen_label_rtx ();
4600 operands[1] = make_safe_from (operands[1], operands[0]);
4601 emit_move_insn (operands[0], const0_rtx);
4602 emit_insn (gen_cmpsi (operands[1], operands[2]));
4603 emit_jump_insn (gen_bltu (label1));
4604 emit_move_insn (operands[0], const1_rtx);
4605 emit_label (label1);
4609 operands[2] = force_reg (SImode, operands[2]);
4610 operands[2] = make_safe_from (operands[2], operands[0]);
4612 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4613 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4616 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4618 insn = emit_move_insn (operands[0],
4619 gen_lowpart (SImode, operands[3]));
4621 gen_rtx_EXPR_LIST (REG_EQUAL,
4622 udiv_equal, REG_NOTES (insn));
4627 rtx label1 = gen_label_rtx ();
4628 rtx label2 = gen_label_rtx ();
4629 rtx label3 = gen_label_rtx ();
4631 operands[1] = force_reg (SImode, operands[1]);
4632 operands[1] = make_safe_from (operands[1], operands[0]);
4633 operands[2] = force_reg (SImode, operands[2]);
4634 operands[2] = make_safe_from (operands[2], operands[0]);
4636 emit_move_insn (operands[0], const0_rtx);
4637 emit_insn (gen_cmpsi (operands[2], operands[1]));
4638 emit_jump_insn (gen_bgtu (label3));
4639 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4640 emit_jump_insn (gen_blt (label2));
4641 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4642 emit_jump_insn (gen_beq (label1));
4643 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4644 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4647 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4649 insn = emit_move_insn (operands[0],
4650 gen_lowpart (SImode, operands[3]));
4652 gen_rtx_EXPR_LIST (REG_EQUAL,
4653 udiv_equal, REG_NOTES (insn));
4655 emit_label (label1);
4656 emit_move_insn (operands[0], operands[1]);
4658 emit_label (label2);
4659 emit_move_insn (operands[0], const1_rtx);
4660 emit_label (label3);
4662 emit_move_insn (operands[0], operands[0]);
4666 (define_expand "umodsi3"
4667 [(set (match_operand:SI 0 "register_operand" "=d")
4668 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4669 (match_operand:SI 2 "nonimmediate_operand" "")))
4670 (clobber (match_dup 3))]
4671 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4673 rtx insn, udiv_equal, umod_equal, equal;
4675 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4676 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4677 equal = gen_rtx_IOR (DImode,
4678 gen_rtx_ASHIFT (DImode,
4679 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4681 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4683 operands[3] = gen_reg_rtx (DImode);
4685 if (CONSTANT_P (operands[2]))
4687 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4689 rtx label1 = gen_label_rtx ();
4691 operands[1] = make_safe_from (operands[1], operands[0]);
4692 emit_move_insn (operands[0], operands[1]);
4693 emit_insn (gen_cmpsi (operands[0], operands[2]));
4694 emit_jump_insn (gen_bltu (label1));
4695 emit_insn (gen_abssi2 (operands[0], operands[2]));
4696 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4697 emit_label (label1);
4701 operands[2] = force_reg (SImode, operands[2]);
4702 operands[2] = make_safe_from (operands[2], operands[0]);
4704 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4705 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4708 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4710 insn = emit_move_insn (operands[0],
4711 gen_highpart (SImode, operands[3]));
4713 gen_rtx_EXPR_LIST (REG_EQUAL,
4714 umod_equal, REG_NOTES (insn));
4719 rtx label1 = gen_label_rtx ();
4720 rtx label2 = gen_label_rtx ();
4721 rtx label3 = gen_label_rtx ();
4723 operands[1] = force_reg (SImode, operands[1]);
4724 operands[1] = make_safe_from (operands[1], operands[0]);
4725 operands[2] = force_reg (SImode, operands[2]);
4726 operands[2] = make_safe_from (operands[2], operands[0]);
4728 emit_move_insn(operands[0], operands[1]);
4729 emit_insn (gen_cmpsi (operands[2], operands[1]));
4730 emit_jump_insn (gen_bgtu (label3));
4731 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4732 emit_jump_insn (gen_blt (label2));
4733 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4734 emit_jump_insn (gen_beq (label1));
4735 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4736 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4739 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4741 insn = emit_move_insn (operands[0],
4742 gen_highpart (SImode, operands[3]));
4744 gen_rtx_EXPR_LIST (REG_EQUAL,
4745 umod_equal, REG_NOTES (insn));
4747 emit_label (label1);
4748 emit_move_insn (operands[0], const0_rtx);
4750 emit_label (label2);
4751 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4752 emit_label (label3);
4758 ; div(df|sf)3 instruction pattern(s).
4761 (define_expand "div<mode>3"
4762 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4763 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4764 (match_operand:FPR 2 "general_operand" "f,R")))]
4768 (define_insn "*div<mode>3"
4769 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4770 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4771 (match_operand:FPR 2 "general_operand" "f,R")))]
4772 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4776 [(set_attr "op_type" "RRE,RXE")
4777 (set_attr "type" "fdiv<mode>")])
4779 (define_insn "*div<mode>3_ibm"
4780 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4781 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4782 (match_operand:FPR 2 "general_operand" "f,R")))]
4783 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4787 [(set_attr "op_type" "RR,RX")
4788 (set_attr "type" "fdiv<mode>")])
4792 ;;- And instructions.
4795 (define_expand "and<mode>3"
4796 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4797 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4798 (match_operand:INT 2 "general_operand" "")))
4799 (clobber (reg:CC CC_REGNUM))]
4801 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4804 ; anddi3 instruction pattern(s).
4807 (define_insn "*anddi3_cc"
4808 [(set (reg CC_REGNUM)
4809 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4810 (match_operand:DI 2 "general_operand" "d,m"))
4812 (set (match_operand:DI 0 "register_operand" "=d,d")
4813 (and:DI (match_dup 1) (match_dup 2)))]
4814 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4818 [(set_attr "op_type" "RRE,RXY")])
4820 (define_insn "*anddi3_cconly"
4821 [(set (reg CC_REGNUM)
4822 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4823 (match_operand:DI 2 "general_operand" "d,m"))
4825 (clobber (match_scratch:DI 0 "=d,d"))]
4826 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4827 /* Do not steal TM patterns. */
4828 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4832 [(set_attr "op_type" "RRE,RXY")])
4834 (define_insn "*anddi3_extimm"
4835 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
4836 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4837 "%d,o,0,0,0,0,0,0,0,0,0,0")
4838 (match_operand:DI 2 "general_operand"
4839 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
4840 (clobber (reg:CC CC_REGNUM))]
4841 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4855 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
4857 (define_insn "*anddi3"
4858 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4859 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4860 "%d,o,0,0,0,0,0,0,0,0")
4861 (match_operand:DI 2 "general_operand"
4862 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4863 (clobber (reg:CC CC_REGNUM))]
4864 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4876 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4879 [(set (match_operand:DI 0 "s_operand" "")
4880 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4881 (clobber (reg:CC CC_REGNUM))]
4884 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4885 (clobber (reg:CC CC_REGNUM))])]
4886 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4890 ; andsi3 instruction pattern(s).
4893 (define_insn "*andsi3_cc"
4894 [(set (reg CC_REGNUM)
4895 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4896 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4898 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4899 (and:SI (match_dup 1) (match_dup 2)))]
4900 "s390_match_ccmode(insn, CCTmode)"
4906 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4908 (define_insn "*andsi3_cconly"
4909 [(set (reg CC_REGNUM)
4910 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4911 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4913 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
4914 "s390_match_ccmode(insn, CCTmode)
4915 /* Do not steal TM patterns. */
4916 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4922 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4924 (define_insn "*andsi3_zarch"
4925 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4926 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4927 "%d,o,0,0,0,0,0,0,0,0")
4928 (match_operand:SI 2 "general_operand"
4929 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
4930 (clobber (reg:CC CC_REGNUM))]
4931 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4943 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
4945 (define_insn "*andsi3_esa"
4946 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4947 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4948 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4949 (clobber (reg:CC CC_REGNUM))]
4950 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4956 [(set_attr "op_type" "RR,RX,SI,SS")])
4959 [(set (match_operand:SI 0 "s_operand" "")
4960 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4961 (clobber (reg:CC CC_REGNUM))]
4964 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4965 (clobber (reg:CC CC_REGNUM))])]
4966 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4969 ; andhi3 instruction pattern(s).
4972 (define_insn "*andhi3_zarch"
4973 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4974 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4975 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4976 (clobber (reg:CC CC_REGNUM))]
4977 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4983 [(set_attr "op_type" "RR,RI,SI,SS")])
4985 (define_insn "*andhi3_esa"
4986 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4987 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4988 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4989 (clobber (reg:CC CC_REGNUM))]
4990 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4995 [(set_attr "op_type" "RR,SI,SS")])
4998 [(set (match_operand:HI 0 "s_operand" "")
4999 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5000 (clobber (reg:CC CC_REGNUM))]
5003 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5004 (clobber (reg:CC CC_REGNUM))])]
5005 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5008 ; andqi3 instruction pattern(s).
5011 (define_insn "*andqi3_zarch"
5012 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5013 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5014 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5015 (clobber (reg:CC CC_REGNUM))]
5016 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5023 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5025 (define_insn "*andqi3_esa"
5026 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5027 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5028 (match_operand:QI 2 "general_operand" "d,n,Q")))
5029 (clobber (reg:CC CC_REGNUM))]
5030 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5035 [(set_attr "op_type" "RR,SI,SS")])
5038 ; Block and (NC) patterns.
5042 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5043 (and:BLK (match_dup 0)
5044 (match_operand:BLK 1 "memory_operand" "Q")))
5045 (use (match_operand 2 "const_int_operand" "n"))
5046 (clobber (reg:CC CC_REGNUM))]
5047 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5048 "nc\t%O0(%2,%R0),%S1"
5049 [(set_attr "op_type" "SS")])
5052 [(set (match_operand 0 "memory_operand" "")
5054 (match_operand 1 "memory_operand" "")))
5055 (clobber (reg:CC CC_REGNUM))]
5057 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5058 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5060 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5062 (clobber (reg:CC CC_REGNUM))])]
5064 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5065 operands[0] = adjust_address (operands[0], BLKmode, 0);
5066 operands[1] = adjust_address (operands[1], BLKmode, 0);
5071 [(set (match_operand:BLK 0 "memory_operand" "")
5072 (and:BLK (match_dup 0)
5073 (match_operand:BLK 1 "memory_operand" "")))
5074 (use (match_operand 2 "const_int_operand" ""))
5075 (clobber (reg:CC CC_REGNUM))])
5077 [(set (match_operand:BLK 3 "memory_operand" "")
5078 (and:BLK (match_dup 3)
5079 (match_operand:BLK 4 "memory_operand" "")))
5080 (use (match_operand 5 "const_int_operand" ""))
5081 (clobber (reg:CC CC_REGNUM))])]
5082 "s390_offset_p (operands[0], operands[3], operands[2])
5083 && s390_offset_p (operands[1], operands[4], operands[2])
5084 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5086 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5088 (clobber (reg:CC CC_REGNUM))])]
5089 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5090 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5091 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5095 ;;- Bit set (inclusive or) instructions.
5098 (define_expand "ior<mode>3"
5099 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5100 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5101 (match_operand:INT 2 "general_operand" "")))
5102 (clobber (reg:CC CC_REGNUM))]
5104 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5107 ; iordi3 instruction pattern(s).
5110 (define_insn "*iordi3_cc"
5111 [(set (reg CC_REGNUM)
5112 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5113 (match_operand:DI 2 "general_operand" "d,m"))
5115 (set (match_operand:DI 0 "register_operand" "=d,d")
5116 (ior:DI (match_dup 1) (match_dup 2)))]
5117 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5121 [(set_attr "op_type" "RRE,RXY")])
5123 (define_insn "*iordi3_cconly"
5124 [(set (reg CC_REGNUM)
5125 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5126 (match_operand:DI 2 "general_operand" "d,m"))
5128 (clobber (match_scratch:DI 0 "=d,d"))]
5129 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5133 [(set_attr "op_type" "RRE,RXY")])
5135 (define_insn "*iordi3_extimm"
5136 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5137 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5138 (match_operand:DI 2 "general_operand"
5139 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5140 (clobber (reg:CC CC_REGNUM))]
5141 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5153 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5155 (define_insn "*iordi3"
5156 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5157 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5158 (match_operand:DI 2 "general_operand"
5159 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5160 (clobber (reg:CC CC_REGNUM))]
5161 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5171 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5174 [(set (match_operand:DI 0 "s_operand" "")
5175 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5176 (clobber (reg:CC CC_REGNUM))]
5179 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5180 (clobber (reg:CC CC_REGNUM))])]
5181 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5184 ; iorsi3 instruction pattern(s).
5187 (define_insn "*iorsi3_cc"
5188 [(set (reg CC_REGNUM)
5189 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5190 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5192 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5193 (ior:SI (match_dup 1) (match_dup 2)))]
5194 "s390_match_ccmode(insn, CCTmode)"
5200 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5202 (define_insn "*iorsi3_cconly"
5203 [(set (reg CC_REGNUM)
5204 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5205 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5207 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5208 "s390_match_ccmode(insn, CCTmode)"
5214 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5216 (define_insn "*iorsi3_zarch"
5217 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5218 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5219 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5220 (clobber (reg:CC CC_REGNUM))]
5221 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5231 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5233 (define_insn "*iorsi3_esa"
5234 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5235 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5236 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5237 (clobber (reg:CC CC_REGNUM))]
5238 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5244 [(set_attr "op_type" "RR,RX,SI,SS")])
5247 [(set (match_operand:SI 0 "s_operand" "")
5248 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5249 (clobber (reg:CC CC_REGNUM))]
5252 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5253 (clobber (reg:CC CC_REGNUM))])]
5254 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5257 ; iorhi3 instruction pattern(s).
5260 (define_insn "*iorhi3_zarch"
5261 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5262 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5263 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5264 (clobber (reg:CC CC_REGNUM))]
5265 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5271 [(set_attr "op_type" "RR,RI,SI,SS")])
5273 (define_insn "*iorhi3_esa"
5274 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5275 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5276 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5277 (clobber (reg:CC CC_REGNUM))]
5278 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5283 [(set_attr "op_type" "RR,SI,SS")])
5286 [(set (match_operand:HI 0 "s_operand" "")
5287 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5288 (clobber (reg:CC CC_REGNUM))]
5291 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5292 (clobber (reg:CC CC_REGNUM))])]
5293 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5296 ; iorqi3 instruction pattern(s).
5299 (define_insn "*iorqi3_zarch"
5300 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5301 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5302 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5303 (clobber (reg:CC CC_REGNUM))]
5304 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5311 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5313 (define_insn "*iorqi3_esa"
5314 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5315 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5316 (match_operand:QI 2 "general_operand" "d,n,Q")))
5317 (clobber (reg:CC CC_REGNUM))]
5318 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5323 [(set_attr "op_type" "RR,SI,SS")])
5326 ; Block inclusive or (OC) patterns.
5330 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5331 (ior:BLK (match_dup 0)
5332 (match_operand:BLK 1 "memory_operand" "Q")))
5333 (use (match_operand 2 "const_int_operand" "n"))
5334 (clobber (reg:CC CC_REGNUM))]
5335 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5336 "oc\t%O0(%2,%R0),%S1"
5337 [(set_attr "op_type" "SS")])
5340 [(set (match_operand 0 "memory_operand" "")
5342 (match_operand 1 "memory_operand" "")))
5343 (clobber (reg:CC CC_REGNUM))]
5345 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5346 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5348 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5350 (clobber (reg:CC CC_REGNUM))])]
5352 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5353 operands[0] = adjust_address (operands[0], BLKmode, 0);
5354 operands[1] = adjust_address (operands[1], BLKmode, 0);
5359 [(set (match_operand:BLK 0 "memory_operand" "")
5360 (ior:BLK (match_dup 0)
5361 (match_operand:BLK 1 "memory_operand" "")))
5362 (use (match_operand 2 "const_int_operand" ""))
5363 (clobber (reg:CC CC_REGNUM))])
5365 [(set (match_operand:BLK 3 "memory_operand" "")
5366 (ior:BLK (match_dup 3)
5367 (match_operand:BLK 4 "memory_operand" "")))
5368 (use (match_operand 5 "const_int_operand" ""))
5369 (clobber (reg:CC CC_REGNUM))])]
5370 "s390_offset_p (operands[0], operands[3], operands[2])
5371 && s390_offset_p (operands[1], operands[4], operands[2])
5372 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5374 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5376 (clobber (reg:CC CC_REGNUM))])]
5377 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5378 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5379 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5383 ;;- Xor instructions.
5386 (define_expand "xor<mode>3"
5387 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5388 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5389 (match_operand:INT 2 "general_operand" "")))
5390 (clobber (reg:CC CC_REGNUM))]
5392 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5395 ; xordi3 instruction pattern(s).
5398 (define_insn "*xordi3_cc"
5399 [(set (reg CC_REGNUM)
5400 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5401 (match_operand:DI 2 "general_operand" "d,m"))
5403 (set (match_operand:DI 0 "register_operand" "=d,d")
5404 (xor:DI (match_dup 1) (match_dup 2)))]
5405 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5409 [(set_attr "op_type" "RRE,RXY")])
5411 (define_insn "*xordi3_cconly"
5412 [(set (reg CC_REGNUM)
5413 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5414 (match_operand:DI 2 "general_operand" "d,m"))
5416 (clobber (match_scratch:DI 0 "=d,d"))]
5417 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5421 [(set_attr "op_type" "RRE,RXY")])
5423 (define_insn "*xordi3_extimm"
5424 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5425 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5426 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5427 (clobber (reg:CC CC_REGNUM))]
5428 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5436 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5438 (define_insn "*xordi3"
5439 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5440 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5441 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5442 (clobber (reg:CC CC_REGNUM))]
5443 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5449 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5452 [(set (match_operand:DI 0 "s_operand" "")
5453 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5454 (clobber (reg:CC CC_REGNUM))]
5457 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5458 (clobber (reg:CC CC_REGNUM))])]
5459 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5462 ; xorsi3 instruction pattern(s).
5465 (define_insn "*xorsi3_cc"
5466 [(set (reg CC_REGNUM)
5467 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5468 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5470 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5471 (xor:SI (match_dup 1) (match_dup 2)))]
5472 "s390_match_ccmode(insn, CCTmode)"
5478 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5480 (define_insn "*xorsi3_cconly"
5481 [(set (reg CC_REGNUM)
5482 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5483 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5485 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5486 "s390_match_ccmode(insn, CCTmode)"
5492 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5494 (define_insn "*xorsi3"
5495 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5496 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5497 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5498 (clobber (reg:CC CC_REGNUM))]
5499 "s390_logical_operator_ok_p (operands)"
5507 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5510 [(set (match_operand:SI 0 "s_operand" "")
5511 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5512 (clobber (reg:CC CC_REGNUM))]
5515 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5516 (clobber (reg:CC CC_REGNUM))])]
5517 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5520 ; xorhi3 instruction pattern(s).
5523 (define_insn "*xorhi3"
5524 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5525 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5526 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5527 (clobber (reg:CC CC_REGNUM))]
5528 "s390_logical_operator_ok_p (operands)"
5534 [(set_attr "op_type" "RIL,RR,SI,SS")])
5537 [(set (match_operand:HI 0 "s_operand" "")
5538 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5539 (clobber (reg:CC CC_REGNUM))]
5542 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5543 (clobber (reg:CC CC_REGNUM))])]
5544 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5547 ; xorqi3 instruction pattern(s).
5550 (define_insn "*xorqi3"
5551 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5552 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5553 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5554 (clobber (reg:CC CC_REGNUM))]
5555 "s390_logical_operator_ok_p (operands)"
5562 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5565 ; Block exclusive or (XC) patterns.
5569 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5570 (xor:BLK (match_dup 0)
5571 (match_operand:BLK 1 "memory_operand" "Q")))
5572 (use (match_operand 2 "const_int_operand" "n"))
5573 (clobber (reg:CC CC_REGNUM))]
5574 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5575 "xc\t%O0(%2,%R0),%S1"
5576 [(set_attr "op_type" "SS")])
5579 [(set (match_operand 0 "memory_operand" "")
5581 (match_operand 1 "memory_operand" "")))
5582 (clobber (reg:CC CC_REGNUM))]
5584 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5585 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5587 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5589 (clobber (reg:CC CC_REGNUM))])]
5591 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5592 operands[0] = adjust_address (operands[0], BLKmode, 0);
5593 operands[1] = adjust_address (operands[1], BLKmode, 0);
5598 [(set (match_operand:BLK 0 "memory_operand" "")
5599 (xor:BLK (match_dup 0)
5600 (match_operand:BLK 1 "memory_operand" "")))
5601 (use (match_operand 2 "const_int_operand" ""))
5602 (clobber (reg:CC CC_REGNUM))])
5604 [(set (match_operand:BLK 3 "memory_operand" "")
5605 (xor:BLK (match_dup 3)
5606 (match_operand:BLK 4 "memory_operand" "")))
5607 (use (match_operand 5 "const_int_operand" ""))
5608 (clobber (reg:CC CC_REGNUM))])]
5609 "s390_offset_p (operands[0], operands[3], operands[2])
5610 && s390_offset_p (operands[1], operands[4], operands[2])
5611 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5613 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5615 (clobber (reg:CC CC_REGNUM))])]
5616 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5617 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5618 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5621 ; Block xor (XC) patterns with src == dest.
5624 (define_insn "*xc_zero"
5625 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5627 (use (match_operand 1 "const_int_operand" "n"))
5628 (clobber (reg:CC CC_REGNUM))]
5629 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5630 "xc\t%O0(%1,%R0),%S0"
5631 [(set_attr "op_type" "SS")])
5635 [(set (match_operand:BLK 0 "memory_operand" "")
5637 (use (match_operand 1 "const_int_operand" ""))
5638 (clobber (reg:CC CC_REGNUM))])
5640 [(set (match_operand:BLK 2 "memory_operand" "")
5642 (use (match_operand 3 "const_int_operand" ""))
5643 (clobber (reg:CC CC_REGNUM))])]
5644 "s390_offset_p (operands[0], operands[2], operands[1])
5645 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5647 [(set (match_dup 4) (const_int 0))
5649 (clobber (reg:CC CC_REGNUM))])]
5650 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5651 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5655 ;;- Negate instructions.
5659 ; neg(di|si)2 instruction pattern(s).
5662 (define_expand "neg<mode>2"
5664 [(set (match_operand:DSI 0 "register_operand" "=d")
5665 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5666 (clobber (reg:CC CC_REGNUM))])]
5670 (define_insn "*negdi2_sign_cc"
5671 [(set (reg CC_REGNUM)
5672 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5673 (match_operand:SI 1 "register_operand" "d") 0)
5674 (const_int 32)) (const_int 32)))
5676 (set (match_operand:DI 0 "register_operand" "=d")
5677 (neg:DI (sign_extend:DI (match_dup 1))))]
5678 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5680 [(set_attr "op_type" "RRE")])
5682 (define_insn "*negdi2_sign"
5683 [(set (match_operand:DI 0 "register_operand" "=d")
5684 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5685 (clobber (reg:CC CC_REGNUM))]
5688 [(set_attr "op_type" "RRE")])
5690 (define_insn "*neg<mode>2_cc"
5691 [(set (reg CC_REGNUM)
5692 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5694 (set (match_operand:GPR 0 "register_operand" "=d")
5695 (neg:GPR (match_dup 1)))]
5696 "s390_match_ccmode (insn, CCAmode)"
5698 [(set_attr "op_type" "RR<E>")])
5700 (define_insn "*neg<mode>2_cconly"
5701 [(set (reg CC_REGNUM)
5702 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5704 (clobber (match_scratch:GPR 0 "=d"))]
5705 "s390_match_ccmode (insn, CCAmode)"
5707 [(set_attr "op_type" "RR<E>")])
5709 (define_insn "*neg<mode>2"
5710 [(set (match_operand:GPR 0 "register_operand" "=d")
5711 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5712 (clobber (reg:CC CC_REGNUM))]
5715 [(set_attr "op_type" "RR<E>")])
5717 (define_insn_and_split "*negdi2_31"
5718 [(set (match_operand:DI 0 "register_operand" "=d")
5719 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5720 (clobber (reg:CC CC_REGNUM))]
5723 "&& reload_completed"
5725 [(set (match_dup 2) (neg:SI (match_dup 3)))
5726 (clobber (reg:CC CC_REGNUM))])
5728 [(set (reg:CCAP CC_REGNUM)
5729 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5730 (set (match_dup 4) (neg:SI (match_dup 5)))])
5732 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5734 (label_ref (match_dup 6))))
5736 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5737 (clobber (reg:CC CC_REGNUM))])
5739 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5740 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5741 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5742 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5743 operands[6] = gen_label_rtx ();")
5746 ; neg(df|sf)2 instruction pattern(s).
5749 (define_expand "neg<mode>2"
5751 [(set (match_operand:FPR 0 "register_operand" "=f")
5752 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5753 (clobber (reg:CC CC_REGNUM))])]
5757 (define_insn "*neg<mode>2_cc"
5758 [(set (reg CC_REGNUM)
5759 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5760 (match_operand:FPR 2 "const0_operand" "")))
5761 (set (match_operand:FPR 0 "register_operand" "=f")
5762 (neg:FPR (match_dup 1)))]
5763 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5765 [(set_attr "op_type" "RRE")
5766 (set_attr "type" "fsimp<mode>")])
5768 (define_insn "*neg<mode>2_cconly"
5769 [(set (reg CC_REGNUM)
5770 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5771 (match_operand:FPR 2 "const0_operand" "")))
5772 (clobber (match_scratch:FPR 0 "=f"))]
5773 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5775 [(set_attr "op_type" "RRE")
5776 (set_attr "type" "fsimp<mode>")])
5778 (define_insn "*neg<mode>2"
5779 [(set (match_operand:FPR 0 "register_operand" "=f")
5780 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5781 (clobber (reg:CC CC_REGNUM))]
5782 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5784 [(set_attr "op_type" "RRE")
5785 (set_attr "type" "fsimp<mode>")])
5787 (define_insn "*neg<mode>2_ibm"
5788 [(set (match_operand:FPR 0 "register_operand" "=f")
5789 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5790 (clobber (reg:CC CC_REGNUM))]
5791 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5793 [(set_attr "op_type" "RR")
5794 (set_attr "type" "fsimp<mode>")])
5798 ;;- Absolute value instructions.
5802 ; abs(di|si)2 instruction pattern(s).
5805 (define_insn "*absdi2_sign_cc"
5806 [(set (reg CC_REGNUM)
5807 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5808 (match_operand:SI 1 "register_operand" "d") 0)
5809 (const_int 32)) (const_int 32)))
5811 (set (match_operand:DI 0 "register_operand" "=d")
5812 (abs:DI (sign_extend:DI (match_dup 1))))]
5813 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5815 [(set_attr "op_type" "RRE")])
5817 (define_insn "*absdi2_sign"
5818 [(set (match_operand:DI 0 "register_operand" "=d")
5819 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5820 (clobber (reg:CC CC_REGNUM))]
5823 [(set_attr "op_type" "RRE")])
5825 (define_insn "*abs<mode>2_cc"
5826 [(set (reg CC_REGNUM)
5827 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5829 (set (match_operand:GPR 0 "register_operand" "=d")
5830 (abs:GPR (match_dup 1)))]
5831 "s390_match_ccmode (insn, CCAmode)"
5833 [(set_attr "op_type" "RR<E>")])
5835 (define_insn "*abs<mode>2_cconly"
5836 [(set (reg CC_REGNUM)
5837 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5839 (clobber (match_scratch:GPR 0 "=d"))]
5840 "s390_match_ccmode (insn, CCAmode)"
5842 [(set_attr "op_type" "RR<E>")])
5844 (define_insn "abs<mode>2"
5845 [(set (match_operand:GPR 0 "register_operand" "=d")
5846 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5847 (clobber (reg:CC CC_REGNUM))]
5850 [(set_attr "op_type" "RR<E>")])
5853 ; abs(df|sf)2 instruction pattern(s).
5856 (define_expand "abs<mode>2"
5858 [(set (match_operand:FPR 0 "register_operand" "=f")
5859 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5860 (clobber (reg:CC CC_REGNUM))])]
5864 (define_insn "*abs<mode>2_cc"
5865 [(set (reg CC_REGNUM)
5866 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5867 (match_operand:FPR 2 "const0_operand" "")))
5868 (set (match_operand:FPR 0 "register_operand" "=f")
5869 (abs:FPR (match_dup 1)))]
5870 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5872 [(set_attr "op_type" "RRE")
5873 (set_attr "type" "fsimp<mode>")])
5875 (define_insn "*abs<mode>2_cconly"
5876 [(set (reg CC_REGNUM)
5877 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5878 (match_operand:FPR 2 "const0_operand" "")))
5879 (clobber (match_scratch:FPR 0 "=f"))]
5880 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5882 [(set_attr "op_type" "RRE")
5883 (set_attr "type" "fsimp<mode>")])
5885 (define_insn "*abs<mode>2"
5886 [(set (match_operand:FPR 0 "register_operand" "=f")
5887 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5888 (clobber (reg:CC CC_REGNUM))]
5889 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5891 [(set_attr "op_type" "RRE")
5892 (set_attr "type" "fsimp<mode>")])
5894 (define_insn "*abs<mode>2_ibm"
5895 [(set (match_operand:FPR 0 "register_operand" "=f")
5896 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5897 (clobber (reg:CC CC_REGNUM))]
5898 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5900 [(set_attr "op_type" "RR")
5901 (set_attr "type" "fsimp<mode>")])
5904 ;;- Negated absolute value instructions
5911 (define_insn "*negabsdi2_sign_cc"
5912 [(set (reg CC_REGNUM)
5913 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5914 (match_operand:SI 1 "register_operand" "d") 0)
5915 (const_int 32)) (const_int 32))))
5917 (set (match_operand:DI 0 "register_operand" "=d")
5918 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5919 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5921 [(set_attr "op_type" "RRE")])
5923 (define_insn "*negabsdi2_sign"
5924 [(set (match_operand:DI 0 "register_operand" "=d")
5925 (neg:DI (abs:DI (sign_extend:DI
5926 (match_operand:SI 1 "register_operand" "d")))))
5927 (clobber (reg:CC CC_REGNUM))]
5930 [(set_attr "op_type" "RRE")])
5932 (define_insn "*negabs<mode>2_cc"
5933 [(set (reg CC_REGNUM)
5934 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5936 (set (match_operand:GPR 0 "register_operand" "=d")
5937 (neg:GPR (abs:GPR (match_dup 1))))]
5938 "s390_match_ccmode (insn, CCAmode)"
5940 [(set_attr "op_type" "RR<E>")])
5942 (define_insn "*negabs<mode>2_cconly"
5943 [(set (reg CC_REGNUM)
5944 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5946 (clobber (match_scratch:GPR 0 "=d"))]
5947 "s390_match_ccmode (insn, CCAmode)"
5949 [(set_attr "op_type" "RR<E>")])
5951 (define_insn "*negabs<mode>2"
5952 [(set (match_operand:GPR 0 "register_operand" "=d")
5953 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5954 (clobber (reg:CC CC_REGNUM))]
5957 [(set_attr "op_type" "RR<E>")])
5963 (define_insn "*negabs<mode>2_cc"
5964 [(set (reg CC_REGNUM)
5965 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5966 (match_operand:FPR 2 "const0_operand" "")))
5967 (set (match_operand:FPR 0 "register_operand" "=f")
5968 (neg:FPR (abs:FPR (match_dup 1))))]
5969 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5971 [(set_attr "op_type" "RRE")
5972 (set_attr "type" "fsimp<mode>")])
5974 (define_insn "*negabs<mode>2_cconly"
5975 [(set (reg CC_REGNUM)
5976 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5977 (match_operand:FPR 2 "const0_operand" "")))
5978 (clobber (match_scratch:FPR 0 "=f"))]
5979 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5981 [(set_attr "op_type" "RRE")
5982 (set_attr "type" "fsimp<mode>")])
5984 (define_insn "*negabs<mode>2"
5985 [(set (match_operand:FPR 0 "register_operand" "=f")
5986 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5987 (clobber (reg:CC CC_REGNUM))]
5988 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5990 [(set_attr "op_type" "RRE")
5991 (set_attr "type" "fsimp<mode>")])
5994 ;;- Square root instructions.
5998 ; sqrt(df|sf)2 instruction pattern(s).
6001 (define_insn "sqrt<mode>2"
6002 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6003 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6004 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6008 [(set_attr "op_type" "RRE,RXE")
6009 (set_attr "type" "fsqrt<mode>")])
6013 ;;- One complement instructions.
6017 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6020 (define_expand "one_cmpl<mode>2"
6022 [(set (match_operand:INT 0 "register_operand" "")
6023 (xor:INT (match_operand:INT 1 "register_operand" "")
6025 (clobber (reg:CC CC_REGNUM))])]
6031 ;; Find leftmost bit instructions.
6034 (define_expand "clzdi2"
6035 [(set (match_operand:DI 0 "register_operand" "=d")
6036 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6037 "TARGET_EXTIMM && TARGET_64BIT"
6039 rtx insn, clz_equal;
6040 rtx wide_reg = gen_reg_rtx (TImode);
6041 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6043 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6045 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6047 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6049 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6054 (define_insn "clztidi2"
6055 [(set (match_operand:TI 0 "register_operand" "=d")
6059 (xor:DI (match_operand:DI 1 "register_operand" "d")
6060 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6061 (subreg:SI (clz:DI (match_dup 1)) 4))))
6064 (zero_extend:TI (clz:DI (match_dup 1)))))
6065 (clobber (reg:CC CC_REGNUM))]
6066 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6067 == (unsigned HOST_WIDE_INT) 1 << 63
6068 && TARGET_EXTIMM && TARGET_64BIT"
6070 [(set_attr "op_type" "RRE")])
6074 ;;- Rotate instructions.
6078 ; rotl(di|si)3 instruction pattern(s).
6081 (define_insn "rotl<mode>3"
6082 [(set (match_operand:GPR 0 "register_operand" "=d")
6083 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6084 (match_operand:SI 2 "shift_count_operand" "Y")))]
6087 [(set_attr "op_type" "RSE")
6088 (set_attr "atype" "reg")])
6092 ;;- Shift instructions.
6096 ; (ashl|lshr)di3 instruction pattern(s).
6099 (define_expand "<shift>di3"
6100 [(set (match_operand:DI 0 "register_operand" "")
6101 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6102 (match_operand:SI 2 "shift_count_operand" "")))]
6106 (define_insn "*<shift>di3_31"
6107 [(set (match_operand:DI 0 "register_operand" "=d")
6108 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6109 (match_operand:SI 2 "shift_count_operand" "Y")))]
6112 [(set_attr "op_type" "RS")
6113 (set_attr "atype" "reg")])
6115 (define_insn "*<shift>di3_64"
6116 [(set (match_operand:DI 0 "register_operand" "=d")
6117 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6118 (match_operand:SI 2 "shift_count_operand" "Y")))]
6120 "s<lr>lg\t%0,%1,%Y2"
6121 [(set_attr "op_type" "RSE")
6122 (set_attr "atype" "reg")])
6125 ; ashrdi3 instruction pattern(s).
6128 (define_expand "ashrdi3"
6130 [(set (match_operand:DI 0 "register_operand" "")
6131 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6132 (match_operand:SI 2 "shift_count_operand" "")))
6133 (clobber (reg:CC CC_REGNUM))])]
6137 (define_insn "*ashrdi3_cc_31"
6138 [(set (reg CC_REGNUM)
6139 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6140 (match_operand:SI 2 "shift_count_operand" "Y"))
6142 (set (match_operand:DI 0 "register_operand" "=d")
6143 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6144 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6146 [(set_attr "op_type" "RS")
6147 (set_attr "atype" "reg")])
6149 (define_insn "*ashrdi3_cconly_31"
6150 [(set (reg CC_REGNUM)
6151 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6152 (match_operand:SI 2 "shift_count_operand" "Y"))
6154 (clobber (match_scratch:DI 0 "=d"))]
6155 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6157 [(set_attr "op_type" "RS")
6158 (set_attr "atype" "reg")])
6160 (define_insn "*ashrdi3_31"
6161 [(set (match_operand:DI 0 "register_operand" "=d")
6162 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6163 (match_operand:SI 2 "shift_count_operand" "Y")))
6164 (clobber (reg:CC CC_REGNUM))]
6167 [(set_attr "op_type" "RS")
6168 (set_attr "atype" "reg")])
6170 (define_insn "*ashrdi3_cc_64"
6171 [(set (reg CC_REGNUM)
6172 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6173 (match_operand:SI 2 "shift_count_operand" "Y"))
6175 (set (match_operand:DI 0 "register_operand" "=d")
6176 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6177 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6179 [(set_attr "op_type" "RSE")
6180 (set_attr "atype" "reg")])
6182 (define_insn "*ashrdi3_cconly_64"
6183 [(set (reg CC_REGNUM)
6184 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6185 (match_operand:SI 2 "shift_count_operand" "Y"))
6187 (clobber (match_scratch:DI 0 "=d"))]
6188 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6190 [(set_attr "op_type" "RSE")
6191 (set_attr "atype" "reg")])
6193 (define_insn "*ashrdi3_64"
6194 [(set (match_operand:DI 0 "register_operand" "=d")
6195 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6196 (match_operand:SI 2 "shift_count_operand" "Y")))
6197 (clobber (reg:CC CC_REGNUM))]
6200 [(set_attr "op_type" "RSE")
6201 (set_attr "atype" "reg")])
6205 ; (ashl|lshr)si3 instruction pattern(s).
6208 (define_insn "<shift>si3"
6209 [(set (match_operand:SI 0 "register_operand" "=d")
6210 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6211 (match_operand:SI 2 "shift_count_operand" "Y")))]
6214 [(set_attr "op_type" "RS")
6215 (set_attr "atype" "reg")])
6218 ; ashrsi3 instruction pattern(s).
6221 (define_insn "*ashrsi3_cc"
6222 [(set (reg CC_REGNUM)
6223 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6224 (match_operand:SI 2 "shift_count_operand" "Y"))
6226 (set (match_operand:SI 0 "register_operand" "=d")
6227 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6228 "s390_match_ccmode(insn, CCSmode)"
6230 [(set_attr "op_type" "RS")
6231 (set_attr "atype" "reg")])
6234 (define_insn "*ashrsi3_cconly"
6235 [(set (reg CC_REGNUM)
6236 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6237 (match_operand:SI 2 "shift_count_operand" "Y"))
6239 (clobber (match_scratch:SI 0 "=d"))]
6240 "s390_match_ccmode(insn, CCSmode)"
6242 [(set_attr "op_type" "RS")
6243 (set_attr "atype" "reg")])
6245 (define_insn "ashrsi3"
6246 [(set (match_operand:SI 0 "register_operand" "=d")
6247 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6248 (match_operand:SI 2 "shift_count_operand" "Y")))
6249 (clobber (reg:CC CC_REGNUM))]
6252 [(set_attr "op_type" "RS")
6253 (set_attr "atype" "reg")])
6257 ;; Branch instruction patterns.
6260 (define_expand "b<code>"
6262 (if_then_else (COMPARE (match_operand 0 "" "")
6267 "s390_emit_jump (operands[0],
6268 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6272 ;;- Conditional jump instructions.
6275 (define_insn "*cjump_64"
6278 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6279 (label_ref (match_operand 0 "" ""))
6283 if (get_attr_length (insn) == 4)
6286 return "jg%C1\t%l0";
6288 [(set_attr "op_type" "RI")
6289 (set_attr "type" "branch")
6290 (set (attr "length")
6291 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6292 (const_int 4) (const_int 6)))])
6294 (define_insn "*cjump_31"
6297 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6298 (label_ref (match_operand 0 "" ""))
6302 gcc_assert (get_attr_length (insn) == 4);
6305 [(set_attr "op_type" "RI")
6306 (set_attr "type" "branch")
6307 (set (attr "length")
6308 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6309 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6310 (const_int 4) (const_int 6))
6311 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6312 (const_int 4) (const_int 8))))])
6314 (define_insn "*cjump_long"
6317 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6318 (match_operand 0 "address_operand" "U")
6322 if (get_attr_op_type (insn) == OP_TYPE_RR)
6327 [(set (attr "op_type")
6328 (if_then_else (match_operand 0 "register_operand" "")
6329 (const_string "RR") (const_string "RX")))
6330 (set_attr "type" "branch")
6331 (set_attr "atype" "agen")])
6335 ;;- Negated conditional jump instructions.
6338 (define_insn "*icjump_64"
6341 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6343 (label_ref (match_operand 0 "" ""))))]
6346 if (get_attr_length (insn) == 4)
6349 return "jg%D1\t%l0";
6351 [(set_attr "op_type" "RI")
6352 (set_attr "type" "branch")
6353 (set (attr "length")
6354 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6355 (const_int 4) (const_int 6)))])
6357 (define_insn "*icjump_31"
6360 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6362 (label_ref (match_operand 0 "" ""))))]
6365 gcc_assert (get_attr_length (insn) == 4);
6368 [(set_attr "op_type" "RI")
6369 (set_attr "type" "branch")
6370 (set (attr "length")
6371 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6372 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6373 (const_int 4) (const_int 6))
6374 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6375 (const_int 4) (const_int 8))))])
6377 (define_insn "*icjump_long"
6380 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6382 (match_operand 0 "address_operand" "U")))]
6385 if (get_attr_op_type (insn) == OP_TYPE_RR)
6390 [(set (attr "op_type")
6391 (if_then_else (match_operand 0 "register_operand" "")
6392 (const_string "RR") (const_string "RX")))
6393 (set_attr "type" "branch")
6394 (set_attr "atype" "agen")])
6397 ;;- Trap instructions.
6401 [(trap_if (const_int 1) (const_int 0))]
6404 [(set_attr "op_type" "RI")
6405 (set_attr "type" "branch")])
6407 (define_expand "conditional_trap"
6408 [(trap_if (match_operand 0 "comparison_operator" "")
6409 (match_operand 1 "general_operand" ""))]
6412 if (operands[1] != const0_rtx) FAIL;
6413 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6414 s390_compare_op0, s390_compare_op1);
6417 (define_insn "*trap"
6418 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6422 [(set_attr "op_type" "RI")
6423 (set_attr "type" "branch")])
6426 ;;- Loop instructions.
6428 ;; This is all complicated by the fact that since this is a jump insn
6429 ;; we must handle our own output reloads.
6431 (define_expand "doloop_end"
6432 [(use (match_operand 0 "" "")) ; loop pseudo
6433 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6434 (use (match_operand 2 "" "")) ; max iterations
6435 (use (match_operand 3 "" "")) ; loop level
6436 (use (match_operand 4 "" ""))] ; label
6439 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6440 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6441 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6442 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6443 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6444 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6451 (define_insn_and_split "doloop_si64"
6454 (ne (match_operand:SI 1 "register_operand" "d,d")
6456 (label_ref (match_operand 0 "" ""))
6458 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6459 (plus:SI (match_dup 1) (const_int -1)))
6460 (clobber (match_scratch:SI 3 "=X,&1"))
6461 (clobber (reg:CC CC_REGNUM))]
6464 if (which_alternative != 0)
6466 else if (get_attr_length (insn) == 4)
6467 return "brct\t%1,%l0";
6469 return "ahi\t%1,-1\;jgne\t%l0";
6471 "&& reload_completed
6472 && (! REG_P (operands[2])
6473 || ! rtx_equal_p (operands[1], operands[2]))"
6474 [(parallel [(set (reg:CCAN CC_REGNUM)
6475 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6477 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6478 (set (match_dup 2) (match_dup 3))
6479 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6480 (label_ref (match_dup 0))
6483 [(set_attr "op_type" "RI")
6484 (set_attr "type" "branch")
6485 (set (attr "length")
6486 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6487 (const_int 4) (const_int 10)))])
6489 (define_insn_and_split "doloop_si31"
6492 (ne (match_operand:SI 1 "register_operand" "d,d")
6494 (label_ref (match_operand 0 "" ""))
6496 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6497 (plus:SI (match_dup 1) (const_int -1)))
6498 (clobber (match_scratch:SI 3 "=X,&1"))
6499 (clobber (reg:CC CC_REGNUM))]
6502 if (which_alternative != 0)
6504 else if (get_attr_length (insn) == 4)
6505 return "brct\t%1,%l0";
6509 "&& reload_completed
6510 && (! REG_P (operands[2])
6511 || ! rtx_equal_p (operands[1], operands[2]))"
6512 [(parallel [(set (reg:CCAN CC_REGNUM)
6513 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6515 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6516 (set (match_dup 2) (match_dup 3))
6517 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6518 (label_ref (match_dup 0))
6521 [(set_attr "op_type" "RI")
6522 (set_attr "type" "branch")
6523 (set (attr "length")
6524 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6525 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6526 (const_int 4) (const_int 6))
6527 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6528 (const_int 4) (const_int 8))))])
6530 (define_insn "*doloop_si_long"
6533 (ne (match_operand:SI 1 "register_operand" "d,d")
6535 (match_operand 0 "address_operand" "U,U")
6537 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6538 (plus:SI (match_dup 1) (const_int -1)))
6539 (clobber (match_scratch:SI 3 "=X,&1"))
6540 (clobber (reg:CC CC_REGNUM))]
6543 if (get_attr_op_type (insn) == OP_TYPE_RR)
6544 return "bctr\t%1,%0";
6546 return "bct\t%1,%a0";
6548 [(set (attr "op_type")
6549 (if_then_else (match_operand 0 "register_operand" "")
6550 (const_string "RR") (const_string "RX")))
6551 (set_attr "type" "branch")
6552 (set_attr "atype" "agen")])
6554 (define_insn_and_split "doloop_di"
6557 (ne (match_operand:DI 1 "register_operand" "d,d")
6559 (label_ref (match_operand 0 "" ""))
6561 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6562 (plus:DI (match_dup 1) (const_int -1)))
6563 (clobber (match_scratch:DI 3 "=X,&1"))
6564 (clobber (reg:CC CC_REGNUM))]
6567 if (which_alternative != 0)
6569 else if (get_attr_length (insn) == 4)
6570 return "brctg\t%1,%l0";
6572 return "aghi\t%1,-1\;jgne\t%l0";
6574 "&& reload_completed
6575 && (! REG_P (operands[2])
6576 || ! rtx_equal_p (operands[1], operands[2]))"
6577 [(parallel [(set (reg:CCAN CC_REGNUM)
6578 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6580 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6581 (set (match_dup 2) (match_dup 3))
6582 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6583 (label_ref (match_dup 0))
6586 [(set_attr "op_type" "RI")
6587 (set_attr "type" "branch")
6588 (set (attr "length")
6589 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6590 (const_int 4) (const_int 10)))])
6593 ;;- Unconditional jump instructions.
6597 ; jump instruction pattern(s).
6600 (define_expand "jump"
6601 [(match_operand 0 "" "")]
6603 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6605 (define_insn "*jump64"
6606 [(set (pc) (label_ref (match_operand 0 "" "")))]
6609 if (get_attr_length (insn) == 4)
6614 [(set_attr "op_type" "RI")
6615 (set_attr "type" "branch")
6616 (set (attr "length")
6617 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6618 (const_int 4) (const_int 6)))])
6620 (define_insn "*jump31"
6621 [(set (pc) (label_ref (match_operand 0 "" "")))]
6624 gcc_assert (get_attr_length (insn) == 4);
6627 [(set_attr "op_type" "RI")
6628 (set_attr "type" "branch")
6629 (set (attr "length")
6630 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6631 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6632 (const_int 4) (const_int 6))
6633 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6634 (const_int 4) (const_int 8))))])
6637 ; indirect-jump instruction pattern(s).
6640 (define_insn "indirect_jump"
6641 [(set (pc) (match_operand 0 "address_operand" "U"))]
6644 if (get_attr_op_type (insn) == OP_TYPE_RR)
6649 [(set (attr "op_type")
6650 (if_then_else (match_operand 0 "register_operand" "")
6651 (const_string "RR") (const_string "RX")))
6652 (set_attr "type" "branch")
6653 (set_attr "atype" "agen")])
6656 ; casesi instruction pattern(s).
6659 (define_insn "casesi_jump"
6660 [(set (pc) (match_operand 0 "address_operand" "U"))
6661 (use (label_ref (match_operand 1 "" "")))]
6664 if (get_attr_op_type (insn) == OP_TYPE_RR)
6669 [(set (attr "op_type")
6670 (if_then_else (match_operand 0 "register_operand" "")
6671 (const_string "RR") (const_string "RX")))
6672 (set_attr "type" "branch")
6673 (set_attr "atype" "agen")])
6675 (define_expand "casesi"
6676 [(match_operand:SI 0 "general_operand" "")
6677 (match_operand:SI 1 "general_operand" "")
6678 (match_operand:SI 2 "general_operand" "")
6679 (label_ref (match_operand 3 "" ""))
6680 (label_ref (match_operand 4 "" ""))]
6683 rtx index = gen_reg_rtx (SImode);
6684 rtx base = gen_reg_rtx (Pmode);
6685 rtx target = gen_reg_rtx (Pmode);
6687 emit_move_insn (index, operands[0]);
6688 emit_insn (gen_subsi3 (index, index, operands[1]));
6689 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6692 if (Pmode != SImode)
6693 index = convert_to_mode (Pmode, index, 1);
6694 if (GET_CODE (index) != REG)
6695 index = copy_to_mode_reg (Pmode, index);
6698 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6700 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6702 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6704 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6705 emit_move_insn (target, index);
6708 target = gen_rtx_PLUS (Pmode, base, target);
6709 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6716 ;;- Jump to subroutine.
6721 ; untyped call instruction pattern(s).
6724 ;; Call subroutine returning any type.
6725 (define_expand "untyped_call"
6726 [(parallel [(call (match_operand 0 "" "")
6728 (match_operand 1 "" "")
6729 (match_operand 2 "" "")])]
6734 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6736 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6738 rtx set = XVECEXP (operands[2], 0, i);
6739 emit_move_insn (SET_DEST (set), SET_SRC (set));
6742 /* The optimizer does not know that the call sets the function value
6743 registers we stored in the result block. We avoid problems by
6744 claiming that all hard registers are used and clobbered at this
6746 emit_insn (gen_blockage ());
6751 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6752 ;; all of memory. This blocks insns from being moved across this point.
6754 (define_insn "blockage"
6755 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6758 [(set_attr "type" "none")
6759 (set_attr "length" "0")])
6765 (define_expand "sibcall"
6766 [(call (match_operand 0 "" "")
6767 (match_operand 1 "" ""))]
6770 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6774 (define_insn "*sibcall_br"
6775 [(call (mem:QI (reg SIBCALL_REGNUM))
6776 (match_operand 0 "const_int_operand" "n"))]
6777 "SIBLING_CALL_P (insn)
6778 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6780 [(set_attr "op_type" "RR")
6781 (set_attr "type" "branch")
6782 (set_attr "atype" "agen")])
6784 (define_insn "*sibcall_brc"
6785 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6786 (match_operand 1 "const_int_operand" "n"))]
6787 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6789 [(set_attr "op_type" "RI")
6790 (set_attr "type" "branch")])
6792 (define_insn "*sibcall_brcl"
6793 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6794 (match_operand 1 "const_int_operand" "n"))]
6795 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6797 [(set_attr "op_type" "RIL")
6798 (set_attr "type" "branch")])
6801 ; sibcall_value patterns
6804 (define_expand "sibcall_value"
6805 [(set (match_operand 0 "" "")
6806 (call (match_operand 1 "" "")
6807 (match_operand 2 "" "")))]
6810 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6814 (define_insn "*sibcall_value_br"
6815 [(set (match_operand 0 "" "")
6816 (call (mem:QI (reg SIBCALL_REGNUM))
6817 (match_operand 1 "const_int_operand" "n")))]
6818 "SIBLING_CALL_P (insn)
6819 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6821 [(set_attr "op_type" "RR")
6822 (set_attr "type" "branch")
6823 (set_attr "atype" "agen")])
6825 (define_insn "*sibcall_value_brc"
6826 [(set (match_operand 0 "" "")
6827 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6828 (match_operand 2 "const_int_operand" "n")))]
6829 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6831 [(set_attr "op_type" "RI")
6832 (set_attr "type" "branch")])
6834 (define_insn "*sibcall_value_brcl"
6835 [(set (match_operand 0 "" "")
6836 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6837 (match_operand 2 "const_int_operand" "n")))]
6838 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6840 [(set_attr "op_type" "RIL")
6841 (set_attr "type" "branch")])
6845 ; call instruction pattern(s).
6848 (define_expand "call"
6849 [(call (match_operand 0 "" "")
6850 (match_operand 1 "" ""))
6851 (use (match_operand 2 "" ""))]
6854 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6855 gen_rtx_REG (Pmode, RETURN_REGNUM));
6859 (define_insn "*bras"
6860 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6861 (match_operand 1 "const_int_operand" "n"))
6862 (clobber (match_operand 2 "register_operand" "=r"))]
6863 "!SIBLING_CALL_P (insn)
6864 && TARGET_SMALL_EXEC
6865 && GET_MODE (operands[2]) == Pmode"
6867 [(set_attr "op_type" "RI")
6868 (set_attr "type" "jsr")])
6870 (define_insn "*brasl"
6871 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6872 (match_operand 1 "const_int_operand" "n"))
6873 (clobber (match_operand 2 "register_operand" "=r"))]
6874 "!SIBLING_CALL_P (insn)
6876 && GET_MODE (operands[2]) == Pmode"
6878 [(set_attr "op_type" "RIL")
6879 (set_attr "type" "jsr")])
6881 (define_insn "*basr"
6882 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6883 (match_operand 1 "const_int_operand" "n"))
6884 (clobber (match_operand 2 "register_operand" "=r"))]
6885 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6887 if (get_attr_op_type (insn) == OP_TYPE_RR)
6888 return "basr\t%2,%0";
6890 return "bas\t%2,%a0";
6892 [(set (attr "op_type")
6893 (if_then_else (match_operand 0 "register_operand" "")
6894 (const_string "RR") (const_string "RX")))
6895 (set_attr "type" "jsr")
6896 (set_attr "atype" "agen")])
6899 ; call_value instruction pattern(s).
6902 (define_expand "call_value"
6903 [(set (match_operand 0 "" "")
6904 (call (match_operand 1 "" "")
6905 (match_operand 2 "" "")))
6906 (use (match_operand 3 "" ""))]
6909 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6910 gen_rtx_REG (Pmode, RETURN_REGNUM));
6914 (define_insn "*bras_r"
6915 [(set (match_operand 0 "" "")
6916 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6917 (match_operand:SI 2 "const_int_operand" "n")))
6918 (clobber (match_operand 3 "register_operand" "=r"))]
6919 "!SIBLING_CALL_P (insn)
6920 && TARGET_SMALL_EXEC
6921 && GET_MODE (operands[3]) == Pmode"
6923 [(set_attr "op_type" "RI")
6924 (set_attr "type" "jsr")])
6926 (define_insn "*brasl_r"
6927 [(set (match_operand 0 "" "")
6928 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6929 (match_operand 2 "const_int_operand" "n")))
6930 (clobber (match_operand 3 "register_operand" "=r"))]
6931 "!SIBLING_CALL_P (insn)
6933 && GET_MODE (operands[3]) == Pmode"
6935 [(set_attr "op_type" "RIL")
6936 (set_attr "type" "jsr")])
6938 (define_insn "*basr_r"
6939 [(set (match_operand 0 "" "")
6940 (call (mem:QI (match_operand 1 "address_operand" "U"))
6941 (match_operand 2 "const_int_operand" "n")))
6942 (clobber (match_operand 3 "register_operand" "=r"))]
6943 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6945 if (get_attr_op_type (insn) == OP_TYPE_RR)
6946 return "basr\t%3,%1";
6948 return "bas\t%3,%a1";
6950 [(set (attr "op_type")
6951 (if_then_else (match_operand 1 "register_operand" "")
6952 (const_string "RR") (const_string "RX")))
6953 (set_attr "type" "jsr")
6954 (set_attr "atype" "agen")])
6957 ;;- Thread-local storage support.
6960 (define_expand "get_tp_64"
6961 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6965 (define_expand "get_tp_31"
6966 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6970 (define_expand "set_tp_64"
6971 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6972 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6976 (define_expand "set_tp_31"
6977 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6978 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6982 (define_insn "*set_tp"
6983 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6986 [(set_attr "type" "none")
6987 (set_attr "length" "0")])
6989 (define_insn "*tls_load_64"
6990 [(set (match_operand:DI 0 "register_operand" "=d")
6991 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6992 (match_operand:DI 2 "" "")]
6996 [(set_attr "op_type" "RXE")])
6998 (define_insn "*tls_load_31"
6999 [(set (match_operand:SI 0 "register_operand" "=d,d")
7000 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7001 (match_operand:SI 2 "" "")]
7007 [(set_attr "op_type" "RX,RXY")])
7009 (define_insn "*bras_tls"
7010 [(set (match_operand 0 "" "")
7011 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7012 (match_operand 2 "const_int_operand" "n")))
7013 (clobber (match_operand 3 "register_operand" "=r"))
7014 (use (match_operand 4 "" ""))]
7015 "!SIBLING_CALL_P (insn)
7016 && TARGET_SMALL_EXEC
7017 && GET_MODE (operands[3]) == Pmode"
7019 [(set_attr "op_type" "RI")
7020 (set_attr "type" "jsr")])
7022 (define_insn "*brasl_tls"
7023 [(set (match_operand 0 "" "")
7024 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7025 (match_operand 2 "const_int_operand" "n")))
7026 (clobber (match_operand 3 "register_operand" "=r"))
7027 (use (match_operand 4 "" ""))]
7028 "!SIBLING_CALL_P (insn)
7030 && GET_MODE (operands[3]) == Pmode"
7032 [(set_attr "op_type" "RIL")
7033 (set_attr "type" "jsr")])
7035 (define_insn "*basr_tls"
7036 [(set (match_operand 0 "" "")
7037 (call (mem:QI (match_operand 1 "address_operand" "U"))
7038 (match_operand 2 "const_int_operand" "n")))
7039 (clobber (match_operand 3 "register_operand" "=r"))
7040 (use (match_operand 4 "" ""))]
7041 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7043 if (get_attr_op_type (insn) == OP_TYPE_RR)
7044 return "basr\t%3,%1%J4";
7046 return "bas\t%3,%a1%J4";
7048 [(set (attr "op_type")
7049 (if_then_else (match_operand 1 "register_operand" "")
7050 (const_string "RR") (const_string "RX")))
7051 (set_attr "type" "jsr")
7052 (set_attr "atype" "agen")])
7055 ;;- Atomic operations
7059 ; memory barrier pattern.
7062 (define_expand "memory_barrier"
7063 [(set (mem:BLK (match_dup 0))
7064 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7067 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7068 MEM_VOLATILE_P (operands[0]) = 1;
7071 (define_insn "*memory_barrier"
7072 [(set (match_operand:BLK 0 "" "")
7073 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7076 [(set_attr "op_type" "RR")])
7079 ; compare and swap patterns.
7082 (define_insn "sync_compare_and_swap<mode>"
7083 [(set (match_operand:GPR 0 "register_operand" "=r")
7084 (match_operand:GPR 1 "memory_operand" "+Q"))
7086 (unspec_volatile:GPR
7088 (match_operand:GPR 2 "register_operand" "0")
7089 (match_operand:GPR 3 "register_operand" "r")]
7091 (clobber (reg:CC CC_REGNUM))]
7094 [(set_attr "op_type" "RS<E>")
7095 (set_attr "type" "sem")])
7097 (define_expand "sync_compare_and_swap_cc<mode>"
7099 [(set (match_operand:GPR 0 "register_operand" "")
7100 (match_operand:GPR 1 "memory_operand" ""))
7102 (unspec_volatile:GPR
7104 (match_operand:GPR 2 "register_operand" "")
7105 (match_operand:GPR 3 "register_operand" "")]
7108 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7111 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7112 s390_compare_op0 = operands[1];
7113 s390_compare_op1 = operands[2];
7114 s390_compare_emitted = operands[4];
7117 (define_insn "*sync_compare_and_swap_cc<mode>"
7118 [(set (match_operand:GPR 0 "register_operand" "=r")
7119 (match_operand:GPR 1 "memory_operand" "+Q"))
7121 (unspec_volatile:GPR
7123 (match_operand:GPR 2 "register_operand" "0")
7124 (match_operand:GPR 3 "register_operand" "r")]
7126 (set (reg:CCZ1 CC_REGNUM)
7127 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7130 [(set_attr "op_type" "RS<E>")
7131 (set_attr "type" "sem")])
7135 ;;- Miscellaneous instructions.
7139 ; allocate stack instruction pattern(s).
7142 (define_expand "allocate_stack"
7143 [(match_operand 0 "general_operand" "")
7144 (match_operand 1 "general_operand" "")]
7147 rtx temp = gen_reg_rtx (Pmode);
7149 emit_move_insn (temp, s390_back_chain_rtx ());
7150 anti_adjust_stack (operands[1]);
7151 emit_move_insn (s390_back_chain_rtx (), temp);
7153 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7159 ; setjmp instruction pattern.
7162 (define_expand "builtin_setjmp_receiver"
7163 [(match_operand 0 "" "")]
7166 emit_insn (s390_load_got ());
7167 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7171 ;; These patterns say how to save and restore the stack pointer. We need not
7172 ;; save the stack pointer at function level since we are careful to
7173 ;; preserve the backchain. At block level, we have to restore the backchain
7174 ;; when we restore the stack pointer.
7176 ;; For nonlocal gotos, we must save both the stack pointer and its
7177 ;; backchain and restore both. Note that in the nonlocal case, the
7178 ;; save area is a memory location.
7180 (define_expand "save_stack_function"
7181 [(match_operand 0 "general_operand" "")
7182 (match_operand 1 "general_operand" "")]
7186 (define_expand "restore_stack_function"
7187 [(match_operand 0 "general_operand" "")
7188 (match_operand 1 "general_operand" "")]
7192 (define_expand "restore_stack_block"
7193 [(match_operand 0 "register_operand" "")
7194 (match_operand 1 "register_operand" "")]
7197 rtx temp = gen_reg_rtx (Pmode);
7199 emit_move_insn (temp, s390_back_chain_rtx ());
7200 emit_move_insn (operands[0], operands[1]);
7201 emit_move_insn (s390_back_chain_rtx (), temp);
7206 (define_expand "save_stack_nonlocal"
7207 [(match_operand 0 "memory_operand" "")
7208 (match_operand 1 "register_operand" "")]
7211 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7212 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7214 /* Copy the backchain to the first word, sp to the second and the
7215 literal pool base to the third. */
7217 if (TARGET_BACKCHAIN)
7219 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7220 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7223 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7224 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7229 (define_expand "restore_stack_nonlocal"
7230 [(match_operand 0 "register_operand" "")
7231 (match_operand 1 "memory_operand" "")]
7234 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7235 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7236 rtx temp = NULL_RTX;
7238 /* Restore the backchain from the first word, sp from the second and the
7239 literal pool base from the third. */
7241 if (TARGET_BACKCHAIN)
7242 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7244 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7245 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7248 emit_move_insn (s390_back_chain_rtx (), temp);
7250 emit_insn (gen_rtx_USE (VOIDmode, base));
7254 (define_expand "exception_receiver"
7258 s390_set_has_landing_pad_p (true);
7263 ; nop instruction pattern(s).
7270 [(set_attr "op_type" "RR")])
7274 ; Special literal pool access instruction pattern(s).
7277 (define_insn "*pool_entry"
7278 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7279 UNSPECV_POOL_ENTRY)]
7282 enum machine_mode mode = GET_MODE (PATTERN (insn));
7283 unsigned int align = GET_MODE_BITSIZE (mode);
7284 s390_output_pool_entry (operands[0], mode, align);
7287 [(set (attr "length")
7288 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7290 (define_insn "pool_align"
7291 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7292 UNSPECV_POOL_ALIGN)]
7295 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7297 (define_insn "pool_section_start"
7298 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7301 [(set_attr "length" "0")])
7303 (define_insn "pool_section_end"
7304 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7307 [(set_attr "length" "0")])
7309 (define_insn "main_base_31_small"
7310 [(set (match_operand 0 "register_operand" "=a")
7311 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7312 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7314 [(set_attr "op_type" "RR")
7315 (set_attr "type" "la")])
7317 (define_insn "main_base_31_large"
7318 [(set (match_operand 0 "register_operand" "=a")
7319 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7320 (set (pc) (label_ref (match_operand 2 "" "")))]
7321 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7323 [(set_attr "op_type" "RI")])
7325 (define_insn "main_base_64"
7326 [(set (match_operand 0 "register_operand" "=a")
7327 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7328 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7330 [(set_attr "op_type" "RIL")
7331 (set_attr "type" "larl")])
7333 (define_insn "main_pool"
7334 [(set (match_operand 0 "register_operand" "=a")
7335 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7336 "GET_MODE (operands[0]) == Pmode"
7341 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7342 (const_string "larl") (const_string "la")))])
7344 (define_insn "reload_base_31"
7345 [(set (match_operand 0 "register_operand" "=a")
7346 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7347 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7348 "basr\t%0,0\;la\t%0,%1-.(%0)"
7349 [(set_attr "length" "6")
7350 (set_attr "type" "la")])
7352 (define_insn "reload_base_64"
7353 [(set (match_operand 0 "register_operand" "=a")
7354 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7355 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7357 [(set_attr "op_type" "RIL")
7358 (set_attr "type" "larl")])
7361 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7366 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7369 ;; Insns related to generating the function prologue and epilogue.
7373 (define_expand "prologue"
7374 [(use (const_int 0))]
7376 "s390_emit_prologue (); DONE;")
7378 (define_expand "epilogue"
7379 [(use (const_int 1))]
7381 "s390_emit_epilogue (false); DONE;")
7383 (define_expand "sibcall_epilogue"
7384 [(use (const_int 0))]
7386 "s390_emit_epilogue (true); DONE;")
7388 (define_insn "*return"
7390 (use (match_operand 0 "register_operand" "a"))]
7391 "GET_MODE (operands[0]) == Pmode"
7393 [(set_attr "op_type" "RR")
7394 (set_attr "type" "jsr")
7395 (set_attr "atype" "agen")])
7398 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7399 ;; pointer. This is used for compatibility.
7401 (define_expand "ptr_extend"
7402 [(set (match_operand:DI 0 "register_operand" "=r")
7403 (match_operand:SI 1 "register_operand" "r"))]
7406 emit_insn (gen_anddi3 (operands[0],
7407 gen_lowpart (DImode, operands[1]),
7408 GEN_INT (0x7fffffff)));
7412 ;; Instruction definition to expand eh_return macro to support
7413 ;; swapping in special linkage return addresses.
7415 (define_expand "eh_return"
7416 [(use (match_operand 0 "register_operand" ""))]
7419 s390_emit_tpf_eh_return (operands[0]);
7424 ; Stack Protector Patterns
7427 (define_expand "stack_protect_set"
7428 [(set (match_operand 0 "memory_operand" "")
7429 (match_operand 1 "memory_operand" ""))]
7432 #ifdef TARGET_THREAD_SSP_OFFSET
7434 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7435 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7438 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7440 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7445 (define_insn "stack_protect_set<mode>"
7446 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7447 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7449 "mvc\t%O0(%G0,%R0),%S1"
7450 [(set_attr "op_type" "SS")])
7452 (define_expand "stack_protect_test"
7453 [(set (reg:CC CC_REGNUM)
7454 (compare (match_operand 0 "memory_operand" "")
7455 (match_operand 1 "memory_operand" "")))
7456 (match_operand 2 "" "")]
7459 #ifdef TARGET_THREAD_SSP_OFFSET
7461 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7462 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7464 s390_compare_op0 = operands[0];
7465 s390_compare_op1 = operands[1];
7466 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7469 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7471 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7473 emit_jump_insn (gen_beq (operands[2]));
7478 (define_insn "stack_protect_test<mode>"
7479 [(set (reg:CCZ CC_REGNUM)
7480 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7481 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7483 "clc\t%O0(%G0,%R0),%S1"
7484 [(set_attr "op_type" "SS")])