1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it under
9 ;; the terms of the GNU General Public License as published by the Free
10 ;; Software Foundation; either version 2, or (at your option) any later
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the Free
20 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 ;; Special constraints for s/390 machine description:
26 ;; a -- Any address register from 1 to 15.
27 ;; d -- Any register from 0 to 15.
28 ;; I -- An 8-bit constant (0..255).
29 ;; J -- A 12-bit constant (0..4095).
30 ;; K -- A 16-bit constant (-32768..32767).
31 ;; Q -- A memory reference without index-register.
32 ;; S -- Valid operand for the LARL instruction.
34 ;; Special formats used for outputting 390 instructions.
36 ;; %b -- Print a constant byte integer. xy
37 ;; %h -- Print a signed 16-bit. wxyz
38 ;; %N -- Print next register (second word of a DImode reg) or next word.
39 ;; %M -- Print next register (second word of a TImode reg) or next word.
40 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
41 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
43 ;; We have a special constraint for pattern matching.
45 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
57 ; GOT/PLT and lt-relative accesses
58 (UNSPEC_LTREL_OFFSET 100)
59 (UNSPEC_LTREL_BASE 101)
67 (UNSPEC_RELOAD_BASE 210)
69 ; TLS relocation specifiers
74 (UNSPEC_GOTNTPOFF 504)
75 (UNSPEC_INDNTPOFF 505)
79 (UNSPEC_TLSLDM_NTPOFF 511)
84 ;; UNSPEC_VOLATILE usage
93 (UNSPECV_POOL_START 201)
94 (UNSPECV_POOL_END 202)
100 (UNSPECV_POOL_SF 208)
101 (UNSPECV_POOL_DF 209)
102 (UNSPECV_MAIN_POOL 300)
109 ;; Processor type. This attribute must exactly match the processor_type
110 ;; enumeration in s390.h.
112 (define_attr "cpu" "g5,g6,z900,z990"
113 (const (symbol_ref "s390_tune")))
115 ;; Define an insn type attribute. This is used in function unit delay
118 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
119 cs,vs,store,imul,idiv,
120 branch,jsr,fsimpd,fsimps,
121 floadd,floads,fstored, fstores,
122 fmuld,fmuls,fdivd,fdivs,
123 ftoi,itof,fsqrtd,fsqrts,
125 (const_string "integer"))
127 ;; Operand type. Used to default length attribute values
129 (define_attr "op_type"
130 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
133 ;; Insn are devide in two classes:
134 ;; agen: Insn using agen
135 ;; reg: Insn not using agen
137 (define_attr "atype" "agen,reg"
138 (cond [ (eq_attr "op_type" "E") (const_string "reg")
139 (eq_attr "op_type" "RR") (const_string "reg")
140 (eq_attr "op_type" "RX") (const_string "agen")
141 (eq_attr "op_type" "RI") (const_string "reg")
142 (eq_attr "op_type" "RRE") (const_string "reg")
143 (eq_attr "op_type" "RS") (const_string "agen")
144 (eq_attr "op_type" "RSI") (const_string "agen")
145 (eq_attr "op_type" "S") (const_string "agen")
146 (eq_attr "op_type" "SI") (const_string "agen")
147 (eq_attr "op_type" "SS") (const_string "agen")
148 (eq_attr "op_type" "SSE") (const_string "agen")
149 (eq_attr "op_type" "RXE") (const_string "agen")
150 (eq_attr "op_type" "RSE") (const_string "agen")
151 (eq_attr "op_type" "RIL") (const_string "agen")
152 (eq_attr "op_type" "RXY") (const_string "agen")
153 (eq_attr "op_type" "RSY") (const_string "agen")
154 (eq_attr "op_type" "SIY") (const_string "agen")]
155 (const_string "reg")))
157 ;; Generic pipeline function unit.
159 (define_function_unit "integer" 1 0
160 (eq_attr "type" "none") 0 0)
162 (define_function_unit "integer" 1 0
163 (eq_attr "type" "integer") 1 1)
165 (define_function_unit "integer" 1 0
166 (eq_attr "type" "fsimpd") 1 1)
168 (define_function_unit "integer" 1 0
169 (eq_attr "type" "fsimps") 1 1)
171 (define_function_unit "integer" 1 0
172 (eq_attr "type" "load") 1 1)
174 (define_function_unit "integer" 1 0
175 (eq_attr "type" "floadd") 1 1)
177 (define_function_unit "integer" 1 0
178 (eq_attr "type" "floads") 1 1)
180 (define_function_unit "integer" 1 0
181 (eq_attr "type" "la") 1 1)
183 (define_function_unit "integer" 1 0
184 (eq_attr "type" "larl") 1 1)
186 (define_function_unit "integer" 1 0
187 (eq_attr "type" "lr") 1 1)
189 (define_function_unit "integer" 1 0
190 (eq_attr "type" "branch") 1 1)
192 (define_function_unit "integer" 1 0
193 (eq_attr "type" "store") 1 1)
195 (define_function_unit "integer" 1 0
196 (eq_attr "type" "fstored") 1 1)
198 (define_function_unit "integer" 1 0
199 (eq_attr "type" "fstores") 1 1)
201 (define_function_unit "integer" 1 0
202 (eq_attr "type" "lm") 2 2)
204 (define_function_unit "integer" 1 0
205 (eq_attr "type" "stm") 2 2)
207 (define_function_unit "integer" 1 0
208 (eq_attr "type" "cs") 5 5)
210 (define_function_unit "integer" 1 0
211 (eq_attr "type" "vs") 30 30)
213 (define_function_unit "integer" 1 0
214 (eq_attr "type" "jsr") 5 5)
216 (define_function_unit "integer" 1 0
217 (eq_attr "type" "imul") 7 7)
219 (define_function_unit "integer" 1 0
220 (eq_attr "type" "fmuld") 6 6)
222 (define_function_unit "integer" 1 0
223 (eq_attr "type" "fmuls") 6 6)
225 (define_function_unit "integer" 1 0
226 (eq_attr "type" "idiv") 33 33)
228 (define_function_unit "integer" 1 0
229 (eq_attr "type" "fdivd") 33 33)
231 (define_function_unit "integer" 1 0
232 (eq_attr "type" "fdivs") 33 33)
234 (define_function_unit "integer" 1 0
235 (eq_attr "type" "fsqrtd") 30 30)
237 (define_function_unit "integer" 1 0
238 (eq_attr "type" "fsqrts") 30 30)
240 (define_function_unit "integer" 1 0
241 (eq_attr "type" "ftoi") 2 2)
243 (define_function_unit "integer" 1 0
244 (eq_attr "type" "itof") 2 2)
246 (define_function_unit "integer" 1 0
247 (eq_attr "type" "o2") 2 2)
249 (define_function_unit "integer" 1 0
250 (eq_attr "type" "o3") 3 3)
252 (define_function_unit "integer" 1 0
253 (eq_attr "type" "other") 5 5)
255 ;; Pipeline description for z900
262 (define_attr "length" ""
263 (cond [ (eq_attr "op_type" "E") (const_int 2)
264 (eq_attr "op_type" "RR") (const_int 2)
265 (eq_attr "op_type" "RX") (const_int 4)
266 (eq_attr "op_type" "RI") (const_int 4)
267 (eq_attr "op_type" "RRE") (const_int 4)
268 (eq_attr "op_type" "RS") (const_int 4)
269 (eq_attr "op_type" "RSI") (const_int 4)
270 (eq_attr "op_type" "S") (const_int 4)
271 (eq_attr "op_type" "SI") (const_int 4)
272 (eq_attr "op_type" "SS") (const_int 6)
273 (eq_attr "op_type" "SSE") (const_int 6)
274 (eq_attr "op_type" "RXE") (const_int 6)
275 (eq_attr "op_type" "RSE") (const_int 6)
276 (eq_attr "op_type" "RIL") (const_int 6)
277 (eq_attr "op_type" "RXY") (const_int 6)
278 (eq_attr "op_type" "RSY") (const_int 6)
279 (eq_attr "op_type" "SIY") (const_int 6)]
282 ;; Define attributes for `asm' insns.
284 (define_asm_attributes [(set_attr "type" "other")
285 (set_attr "op_type" "NN")])
291 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
292 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
293 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
294 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
295 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
298 ; CCZ1 -> CCA/CCU/CCS/CCT
301 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
302 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
306 ;;- Compare instructions.
309 (define_expand "cmpdi"
311 (compare:CC (match_operand:DI 0 "register_operand" "")
312 (match_operand:DI 1 "general_operand" "")))]
315 s390_compare_op0 = operands[0];
316 s390_compare_op1 = operands[1];
320 (define_expand "cmpsi"
322 (compare:CC (match_operand:SI 0 "register_operand" "")
323 (match_operand:SI 1 "general_operand" "")))]
326 s390_compare_op0 = operands[0];
327 s390_compare_op1 = operands[1];
331 (define_expand "cmpdf"
333 (compare:CC (match_operand:DF 0 "register_operand" "")
334 (match_operand:DF 1 "general_operand" "")))]
337 s390_compare_op0 = operands[0];
338 s390_compare_op1 = operands[1];
342 (define_expand "cmpsf"
344 (compare:CC (match_operand:SF 0 "register_operand" "")
345 (match_operand:SF 1 "general_operand" "")))]
348 s390_compare_op0 = operands[0];
349 s390_compare_op1 = operands[1];
354 ; Test-under-Mask (zero_extract) instructions
356 (define_insn "*tmdi_ext"
358 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
359 (match_operand:DI 1 "const_int_operand" "n")
360 (match_operand:DI 2 "const_int_operand" "n"))
362 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
363 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
364 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
365 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
366 == INTVAL (operands[2]) >> 4"
368 int part = INTVAL (operands[2]) >> 4;
369 int block = (1 << INTVAL (operands[1])) - 1;
370 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
372 operands[2] = GEN_INT (block << shift);
376 case 0: return "tmhh\\t%0,%x2";
377 case 1: return "tmhl\\t%0,%x2";
378 case 2: return "tmlh\\t%0,%x2";
379 case 3: return "tmll\\t%0,%x2";
383 [(set_attr "op_type" "RI")])
385 (define_insn "*tmsi_ext"
387 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
388 (match_operand:SI 1 "const_int_operand" "n")
389 (match_operand:SI 2 "const_int_operand" "n"))
391 "s390_match_ccmode(insn, CCTmode)
392 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
393 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
394 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
395 == INTVAL (operands[2]) >> 4"
397 int part = INTVAL (operands[2]) >> 4;
398 int block = (1 << INTVAL (operands[1])) - 1;
399 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
401 operands[2] = GEN_INT (block << shift);
405 case 0: return "tmh\\t%0,%x2";
406 case 1: return "tml\\t%0,%x2";
410 [(set_attr "op_type" "RI")])
412 (define_insn "*tmqi_ext"
414 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
415 (match_operand:SI 1 "const_int_operand" "n,n")
416 (match_operand:SI 2 "const_int_operand" "n,n"))
418 "s390_match_ccmode(insn, CCTmode)
419 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
420 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
422 int block = (1 << INTVAL (operands[1])) - 1;
423 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
425 operands[2] = GEN_INT (block << shift);
426 return which_alternative == 0 ? "tm\\t%0,%b2" : "tmy\\t%0,%b2";
428 [(set_attr "op_type" "SI,SIY")])
430 ; Test-under-Mask instructions
432 (define_insn "*tmdi_mem"
434 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
435 (match_operand:DI 1 "immediate_operand" "n,n"))
436 (match_operand:DI 2 "immediate_operand" "n,n")))]
438 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
439 && s390_single_qi (operands[1], DImode, 0) >= 0"
441 int part = s390_single_qi (operands[1], DImode, 0);
442 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
444 operands[0] = gen_rtx_MEM (QImode,
445 plus_constant (XEXP (operands[0], 0), part));
446 return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
448 [(set_attr "op_type" "SI,SIY")])
450 (define_insn "*tmsi_mem"
452 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
453 (match_operand:SI 1 "immediate_operand" "n,n"))
454 (match_operand:SI 2 "immediate_operand" "n,n")))]
455 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
456 && s390_single_qi (operands[1], SImode, 0) >= 0"
458 int part = s390_single_qi (operands[1], SImode, 0);
459 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
461 operands[0] = gen_rtx_MEM (QImode,
462 plus_constant (XEXP (operands[0], 0), part));
463 return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
465 [(set_attr "op_type" "SI")])
467 (define_insn "*tmhi_mem"
469 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
470 (match_operand:SI 1 "immediate_operand" "n,n"))
471 (match_operand:SI 2 "immediate_operand" "n,n")))]
472 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
473 && s390_single_qi (operands[1], HImode, 0) >= 0"
475 int part = s390_single_qi (operands[1], HImode, 0);
476 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
478 operands[0] = gen_rtx_MEM (QImode,
479 plus_constant (XEXP (operands[0], 0), part));
480 return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
482 [(set_attr "op_type" "SI")])
484 (define_insn "*tmqi_mem"
486 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
487 (match_operand:SI 1 "immediate_operand" "n,n"))
488 (match_operand:SI 2 "immediate_operand" "n,n")))]
489 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
493 [(set_attr "op_type" "SI,SIY")])
495 (define_insn "*tmdi_reg"
497 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
498 (match_operand:DI 1 "immediate_operand" "n"))
499 (match_operand:DI 2 "immediate_operand" "n")))]
501 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
502 && s390_single_hi (operands[1], DImode, 0) >= 0"
504 int part = s390_single_hi (operands[1], DImode, 0);
505 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
509 case 0: return "tmhh\\t%0,%x1";
510 case 1: return "tmhl\\t%0,%x1";
511 case 2: return "tmlh\\t%0,%x1";
512 case 3: return "tmll\\t%0,%x1";
516 [(set_attr "op_type" "RI")])
518 (define_insn "*tmsi_reg"
520 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
521 (match_operand:SI 1 "immediate_operand" "n"))
522 (match_operand:SI 2 "immediate_operand" "n")))]
523 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
524 && s390_single_hi (operands[1], SImode, 0) >= 0"
526 int part = s390_single_hi (operands[1], SImode, 0);
527 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
531 case 0: return "tmh\\t%0,%x1";
532 case 1: return "tml\\t%0,%x1";
536 [(set_attr "op_type" "RI")])
538 (define_insn "*tmhi_full"
540 (compare (match_operand:HI 0 "register_operand" "d")
541 (match_operand:HI 1 "immediate_operand" "n")))]
542 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
544 [(set_attr "op_type" "RX")])
546 (define_insn "*tmqi_full"
548 (compare (match_operand:QI 0 "register_operand" "d")
549 (match_operand:QI 1 "immediate_operand" "n")))]
550 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
552 [(set_attr "op_type" "RI")])
555 ; Load-and-Test instructions
557 (define_insn "*tstdi_sign"
559 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
560 (const_int 32)) (const_int 32))
561 (match_operand:DI 1 "const0_operand" "")))
562 (set (match_operand:DI 2 "register_operand" "=d")
563 (sign_extend:DI (match_dup 0)))]
564 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
566 [(set_attr "op_type" "RRE")])
568 (define_insn "*tstdi"
570 (compare (match_operand:DI 0 "register_operand" "d")
571 (match_operand:DI 1 "const0_operand" "")))
572 (set (match_operand:DI 2 "register_operand" "=d")
574 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
576 [(set_attr "op_type" "RRE")])
578 (define_insn "*tstdi_cconly"
580 (compare (match_operand:DI 0 "register_operand" "d")
581 (match_operand:DI 1 "const0_operand" "")))]
582 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
584 [(set_attr "op_type" "RRE")])
586 (define_insn "*tstdi_cconly_31"
588 (compare (match_operand:DI 0 "register_operand" "d")
589 (match_operand:DI 1 "const0_operand" "")))]
590 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
592 [(set_attr "op_type" "RS")
593 (set_attr "atype" "reg")])
596 (define_insn "*tstsi"
598 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
599 (match_operand:SI 1 "const0_operand" "")))
600 (set (match_operand:SI 2 "register_operand" "=d,d,d")
602 "s390_match_ccmode(insn, CCSmode)"
607 [(set_attr "op_type" "RR,RS,RSY")])
609 (define_insn "*tstsi_cconly"
611 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
612 (match_operand:SI 1 "const0_operand" "")))
613 (clobber (match_scratch:SI 2 "=X,d,d"))]
614 "s390_match_ccmode(insn, CCSmode)"
619 [(set_attr "op_type" "RR,RS,RSY")])
621 (define_insn "*tstsi_cconly2"
623 (compare (match_operand:SI 0 "register_operand" "d")
624 (match_operand:SI 1 "const0_operand" "")))]
625 "s390_match_ccmode(insn, CCSmode)"
627 [(set_attr "op_type" "RR")])
629 (define_insn "*tsthiCCT"
631 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
632 (match_operand:HI 1 "const0_operand" "")))
633 (set (match_operand:HI 2 "register_operand" "=d,d,0")
635 "s390_match_ccmode(insn, CCTmode)"
640 [(set_attr "op_type" "RS,RSY,RI")])
642 (define_insn "*tsthiCCT_cconly"
644 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
645 (match_operand:HI 1 "const0_operand" "")))
646 (clobber (match_scratch:HI 2 "=d,d,X"))]
647 "s390_match_ccmode(insn, CCTmode)"
652 [(set_attr "op_type" "RS,RSY,RI")])
654 (define_insn "*tsthi"
656 (compare (match_operand:HI 0 "s_operand" "Q,S")
657 (match_operand:HI 1 "const0_operand" "")))
658 (set (match_operand:HI 2 "register_operand" "=d,d")
660 "s390_match_ccmode(insn, CCSmode)"
664 [(set_attr "op_type" "RS,RSY")])
666 (define_insn "*tsthi_cconly"
668 (compare (match_operand:HI 0 "s_operand" "Q,S")
669 (match_operand:HI 1 "const0_operand" "")))
670 (clobber (match_scratch:HI 2 "=d,d"))]
671 "s390_match_ccmode(insn, CCSmode)"
675 [(set_attr "op_type" "RS,RSY")])
677 (define_insn "*tstqiCCT"
679 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
680 (match_operand:QI 1 "const0_operand" "")))
681 (set (match_operand:QI 2 "register_operand" "=d,d,0")
683 "s390_match_ccmode(insn, CCTmode)"
688 [(set_attr "op_type" "RS,RSY,RI")])
690 (define_insn "*tstqiCCT_cconly"
692 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
693 (match_operand:QI 1 "const0_operand" "")))]
694 "s390_match_ccmode(insn, CCTmode)"
699 [(set_attr "op_type" "SI,SIY,RI")])
701 (define_insn "*tstqi"
703 (compare (match_operand:QI 0 "s_operand" "Q,S")
704 (match_operand:QI 1 "const0_operand" "")))
705 (set (match_operand:QI 2 "register_operand" "=d,d")
707 "s390_match_ccmode(insn, CCSmode)"
711 [(set_attr "op_type" "RS,RSY")])
713 (define_insn "*tstqi_cconly"
715 (compare (match_operand:QI 0 "s_operand" "Q,S")
716 (match_operand:QI 1 "const0_operand" "")))
717 (clobber (match_scratch:QI 2 "=d,d"))]
718 "s390_match_ccmode(insn, CCSmode)"
722 [(set_attr "op_type" "RS,RSY")])
725 ; Compare (signed) instructions
727 (define_insn "*cmpdi_ccs_sign"
729 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
730 (match_operand:DI 0 "register_operand" "d,d")))]
731 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
735 [(set_attr "op_type" "RRE,RXY")])
737 (define_insn "*cmpdi_ccs"
739 (compare (match_operand:DI 0 "register_operand" "d,d,d")
740 (match_operand:DI 1 "general_operand" "d,K,m")))]
741 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
746 [(set_attr "op_type" "RRE,RI,RXY")])
748 (define_insn "*cmpsi_ccs_sign"
750 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
751 (match_operand:SI 0 "register_operand" "d,d")))]
752 "s390_match_ccmode(insn, CCSRmode)"
756 [(set_attr "op_type" "RX,RXY")])
758 (define_insn "*cmpsi_ccs"
760 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
761 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
762 "s390_match_ccmode(insn, CCSmode)"
768 [(set_attr "op_type" "RR,RI,RX,RXY")])
771 ; Compare (unsigned) instructions
773 (define_insn "*cmpdi_ccu_zero"
775 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
776 (match_operand:DI 0 "register_operand" "d,d")))]
777 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
781 [(set_attr "op_type" "RRE,RXY")])
783 (define_insn "*cmpdi_ccu"
785 (compare (match_operand:DI 0 "register_operand" "d,d")
786 (match_operand:DI 1 "general_operand" "d,m")))]
787 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
791 [(set_attr "op_type" "RRE,RXY")])
793 (define_insn "*cmpsi_ccu"
795 (compare (match_operand:SI 0 "register_operand" "d,d,d")
796 (match_operand:SI 1 "general_operand" "d,R,T")))]
797 "s390_match_ccmode(insn, CCUmode)"
802 [(set_attr "op_type" "RR,RX,RXY")])
804 (define_insn "*cmphi_ccu"
806 (compare (match_operand:HI 0 "register_operand" "d,d")
807 (match_operand:HI 1 "s_imm_operand" "Q,S")))]
808 "s390_match_ccmode(insn, CCUmode)"
812 [(set_attr "op_type" "RS,RSY")])
814 (define_insn "*cmpqi_ccu"
816 (compare (match_operand:QI 0 "register_operand" "d,d")
817 (match_operand:QI 1 "s_imm_operand" "Q,S")))]
818 "s390_match_ccmode(insn, CCUmode)"
822 [(set_attr "op_type" "RS,RSY")])
826 (compare (match_operand:QI 0 "memory_operand" "Q,S")
827 (match_operand:QI 1 "immediate_operand" "n,n")))]
828 "s390_match_ccmode (insn, CCUmode)"
832 [(set_attr "op_type" "SI,SIY")])
834 (define_insn "*cmpdi_ccu_mem"
836 (compare (match_operand:DI 0 "s_operand" "Q")
837 (match_operand:DI 1 "s_imm_operand" "Q")))]
838 "s390_match_ccmode(insn, CCUmode)"
839 "clc\\t%O0(8,%R0),%1"
840 [(set_attr "op_type" "SS")])
842 (define_insn "*cmpsi_ccu_mem"
844 (compare (match_operand:SI 0 "s_operand" "Q")
845 (match_operand:SI 1 "s_imm_operand" "Q")))]
846 "s390_match_ccmode(insn, CCUmode)"
847 "clc\\t%O0(4,%R0),%1"
848 [(set_attr "op_type" "SS")])
850 (define_insn "*cmphi_ccu_mem"
852 (compare (match_operand:HI 0 "s_operand" "Q")
853 (match_operand:HI 1 "s_imm_operand" "Q")))]
854 "s390_match_ccmode(insn, CCUmode)"
855 "clc\\t%O0(2,%R0),%1"
856 [(set_attr "op_type" "SS")])
858 (define_insn "*cmpqi_ccu_mem"
860 (compare (match_operand:QI 0 "s_operand" "Q")
861 (match_operand:QI 1 "s_imm_operand" "Q")))]
862 "s390_match_ccmode(insn, CCUmode)"
863 "clc\\t%O0(1,%R0),%1"
864 [(set_attr "op_type" "SS")])
869 (define_insn "*cmpdf_ccs_0"
871 (compare (match_operand:DF 0 "register_operand" "f")
872 (match_operand:DF 1 "const0_operand" "")))]
873 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
875 [(set_attr "op_type" "RRE")
876 (set_attr "type" "fsimpd")])
878 (define_insn "*cmpdf_ccs_0_ibm"
880 (compare (match_operand:DF 0 "register_operand" "f")
881 (match_operand:DF 1 "const0_operand" "")))]
882 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
884 [(set_attr "op_type" "RR")
885 (set_attr "type" "fsimpd")])
887 (define_insn "*cmpdf_ccs"
889 (compare (match_operand:DF 0 "register_operand" "f,f")
890 (match_operand:DF 1 "general_operand" "f,R")))]
891 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
895 [(set_attr "op_type" "RRE,RXE")
896 (set_attr "type" "fsimpd")])
898 (define_insn "*cmpdf_ccs_ibm"
900 (compare (match_operand:DF 0 "register_operand" "f,f")
901 (match_operand:DF 1 "general_operand" "f,R")))]
902 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
906 [(set_attr "op_type" "RR,RX")
907 (set_attr "type" "fsimpd")])
912 (define_insn "*cmpsf_ccs_0"
914 (compare (match_operand:SF 0 "register_operand" "f")
915 (match_operand:SF 1 "const0_operand" "")))]
916 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
918 [(set_attr "op_type" "RRE")
919 (set_attr "type" "fsimps")])
921 (define_insn "*cmpsf_ccs_0_ibm"
923 (compare (match_operand:SF 0 "register_operand" "f")
924 (match_operand:SF 1 "const0_operand" "")))]
925 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
927 [(set_attr "op_type" "RR")
928 (set_attr "type" "fsimps")])
930 (define_insn "*cmpsf_ccs"
932 (compare (match_operand:SF 0 "register_operand" "f,f")
933 (match_operand:SF 1 "general_operand" "f,R")))]
934 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
938 [(set_attr "op_type" "RRE,RXE")
939 (set_attr "type" "fsimps")])
941 (define_insn "*cmpsf_ccs"
943 (compare (match_operand:SF 0 "register_operand" "f,f")
944 (match_operand:SF 1 "general_operand" "f,R")))]
945 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
949 [(set_attr "op_type" "RR,RX")
950 (set_attr "type" "fsimps")])
954 ;;- Move instructions.
958 ; movti instruction pattern(s).
962 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
963 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
970 mvc\\t%O0(16,%R0),%1"
971 [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
972 (set_attr "type" "lm,stm,*,*,cs")])
975 [(set (match_operand:TI 0 "nonimmediate_operand" "")
976 (match_operand:TI 1 "general_operand" ""))]
977 "TARGET_64BIT && reload_completed
978 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
979 [(set (match_dup 2) (match_dup 4))
980 (set (match_dup 3) (match_dup 5))]
982 operands[2] = operand_subword (operands[0], 0, 0, TImode);
983 operands[3] = operand_subword (operands[0], 1, 0, TImode);
984 operands[4] = operand_subword (operands[1], 0, 0, TImode);
985 operands[5] = operand_subword (operands[1], 1, 0, TImode);
989 [(set (match_operand:TI 0 "nonimmediate_operand" "")
990 (match_operand:TI 1 "general_operand" ""))]
991 "TARGET_64BIT && reload_completed
992 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
993 [(set (match_dup 2) (match_dup 4))
994 (set (match_dup 3) (match_dup 5))]
996 operands[2] = operand_subword (operands[0], 1, 0, TImode);
997 operands[3] = operand_subword (operands[0], 0, 0, TImode);
998 operands[4] = operand_subword (operands[1], 1, 0, TImode);
999 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1003 [(set (match_operand:TI 0 "register_operand" "")
1004 (match_operand:TI 1 "memory_operand" ""))]
1005 "TARGET_64BIT && reload_completed
1006 && !s_operand (operands[1], VOIDmode)"
1007 [(set (match_dup 0) (match_dup 1))]
1009 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1010 s390_load_address (addr, XEXP (operands[1], 0));
1011 operands[1] = replace_equiv_address (operands[1], addr);
1014 (define_expand "reload_outti"
1015 [(parallel [(match_operand:TI 0 "memory_operand" "")
1016 (match_operand:TI 1 "register_operand" "d")
1017 (match_operand:DI 2 "register_operand" "=&a")])]
1020 s390_load_address (operands[2], XEXP (operands[0], 0));
1021 operands[0] = replace_equiv_address (operands[0], operands[2]);
1022 emit_move_insn (operands[0], operands[1]);
1027 ; movdi instruction pattern(s).
1030 (define_expand "movdi"
1031 [(set (match_operand:DI 0 "general_operand" "")
1032 (match_operand:DI 1 "general_operand" ""))]
1035 /* Handle symbolic constants. */
1036 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1037 emit_symbolic_move (operands);
1039 /* During and after reload, we need to force constants
1040 to the literal pool ourselves, if necessary. */
1041 if ((reload_in_progress || reload_completed)
1042 && CONSTANT_P (operands[1])
1043 && (!legitimate_reload_constant_p (operands[1])
1044 || FP_REG_P (operands[0])))
1045 operands[1] = force_const_mem (DImode, operands[1]);
1048 (define_insn "*movdi_lhi"
1049 [(set (match_operand:DI 0 "register_operand" "=d")
1050 (match_operand:DI 1 "immediate_operand" "K"))]
1052 && GET_CODE (operands[1]) == CONST_INT
1053 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1054 && !FP_REG_P (operands[0])"
1056 [(set_attr "op_type" "RI")])
1058 (define_insn "*movdi_lli"
1059 [(set (match_operand:DI 0 "register_operand" "=d")
1060 (match_operand:DI 1 "immediate_operand" "n"))]
1061 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
1062 && !FP_REG_P (operands[0])"
1064 int part = s390_single_hi (operands[1], DImode, 0);
1065 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
1069 case 0: return "llihh\\t%0,%x1";
1070 case 1: return "llihl\\t%0,%x1";
1071 case 2: return "llilh\\t%0,%x1";
1072 case 3: return "llill\\t%0,%x1";
1076 [(set_attr "op_type" "RI")])
1078 (define_insn "*movdi_lay"
1079 [(set (match_operand:DI 0 "register_operand" "=d")
1080 (match_operand:DI 1 "address_operand" "p"))]
1082 && TARGET_LONG_DISPLACEMENT
1083 && GET_CODE (operands[1]) == CONST_INT
1084 && !FP_REG_P (operands[0])"
1086 [(set_attr "op_type" "RXY")
1087 (set_attr "type" "la")])
1089 (define_insn "*movdi_larl"
1090 [(set (match_operand:DI 0 "register_operand" "=d")
1091 (match_operand:DI 1 "larl_operand" "X"))]
1093 && !FP_REG_P (operands[0])"
1095 [(set_attr "op_type" "RIL")
1096 (set_attr "type" "larl")])
1098 (define_insn "*movdi_64"
1099 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q")
1100 (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
1111 mvc\\t%O0(8,%R0),%1"
1112 [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
1113 (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
1115 (define_insn "*movdi_31"
1116 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
1117 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
1129 mvc\\t%O0(8,%R0),%1"
1130 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
1131 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
1134 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1135 (match_operand:DI 1 "general_operand" ""))]
1136 "!TARGET_64BIT && reload_completed
1137 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1138 [(set (match_dup 2) (match_dup 4))
1139 (set (match_dup 3) (match_dup 5))]
1141 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1142 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1143 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1144 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1148 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1149 (match_operand:DI 1 "general_operand" ""))]
1150 "!TARGET_64BIT && reload_completed
1151 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1152 [(set (match_dup 2) (match_dup 4))
1153 (set (match_dup 3) (match_dup 5))]
1155 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1156 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1157 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1158 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1162 [(set (match_operand:DI 0 "register_operand" "")
1163 (match_operand:DI 1 "memory_operand" ""))]
1164 "!TARGET_64BIT && reload_completed
1165 && !FP_REG_P (operands[0])
1166 && !s_operand (operands[1], VOIDmode)"
1167 [(set (match_dup 0) (match_dup 1))]
1169 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1170 s390_load_address (addr, XEXP (operands[1], 0));
1171 operands[1] = replace_equiv_address (operands[1], addr);
1174 (define_expand "reload_outdi"
1175 [(parallel [(match_operand:DI 0 "memory_operand" "")
1176 (match_operand:DI 1 "register_operand" "d")
1177 (match_operand:SI 2 "register_operand" "=&a")])]
1180 s390_load_address (operands[2], XEXP (operands[0], 0));
1181 operands[0] = replace_equiv_address (operands[0], operands[2]);
1182 emit_move_insn (operands[0], operands[1]);
1187 [(set (match_operand:DI 0 "register_operand" "")
1188 (mem:DI (match_operand 1 "address_operand" "")))]
1190 && !FP_REG_P (operands[0])
1191 && GET_CODE (operands[1]) == SYMBOL_REF
1192 && CONSTANT_POOL_ADDRESS_P (operands[1])
1193 && get_pool_mode (operands[1]) == DImode
1194 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1195 [(set (match_dup 0) (match_dup 2))]
1196 "operands[2] = get_pool_constant (operands[1]);")
1199 ; movsi instruction pattern(s).
1202 (define_expand "movsi"
1203 [(set (match_operand:SI 0 "general_operand" "")
1204 (match_operand:SI 1 "general_operand" ""))]
1207 /* Handle symbolic constants. */
1208 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1209 emit_symbolic_move (operands);
1211 /* expr.c tries to load an effective address using
1212 force_reg. This fails because we don't have a
1213 generic load_address pattern. Convert the move
1214 to a proper arithmetic operation instead, unless
1215 it is guaranteed to be OK. */
1216 if (GET_CODE (operands[1]) == PLUS
1217 && !legitimate_la_operand_p (operands[1]))
1219 operands[1] = force_operand (operands[1], operands[0]);
1220 if (operands[1] == operands[0])
1224 /* During and after reload, we need to force constants
1225 to the literal pool ourselves, if necessary. */
1226 if ((reload_in_progress || reload_completed)
1227 && CONSTANT_P (operands[1])
1228 && (!legitimate_reload_constant_p (operands[1])
1229 || FP_REG_P (operands[0])))
1230 operands[1] = force_const_mem (SImode, operands[1]);
1233 (define_insn "*movsi_lhi"
1234 [(set (match_operand:SI 0 "register_operand" "=d")
1235 (match_operand:SI 1 "immediate_operand" "K"))]
1236 "GET_CODE (operands[1]) == CONST_INT
1237 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1238 && !FP_REG_P (operands[0])"
1240 [(set_attr "op_type" "RI")])
1242 (define_insn "*movsi_lli"
1243 [(set (match_operand:SI 0 "register_operand" "=d")
1244 (match_operand:SI 1 "immediate_operand" "n"))]
1245 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1246 && !FP_REG_P (operands[0])"
1248 int part = s390_single_hi (operands[1], SImode, 0);
1249 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1253 case 0: return "llilh\\t%0,%x1";
1254 case 1: return "llill\\t%0,%x1";
1258 [(set_attr "op_type" "RI")])
1260 (define_insn "*movsi_lay"
1261 [(set (match_operand:SI 0 "register_operand" "=d")
1262 (match_operand:SI 1 "address_operand" "p"))]
1263 "TARGET_LONG_DISPLACEMENT
1264 && GET_CODE (operands[1]) == CONST_INT
1265 && !FP_REG_P (operands[0])"
1267 [(set_attr "op_type" "RXY")
1268 (set_attr "type" "la")])
1270 (define_insn "*movsi"
1271 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
1272 (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
1285 mvc\\t%O0(4,%R0),%1"
1286 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1287 (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
1290 [(set (match_operand:SI 0 "register_operand" "")
1291 (mem:SI (match_operand 1 "address_operand" "")))]
1292 "!FP_REG_P (operands[0])
1293 && GET_CODE (operands[1]) == SYMBOL_REF
1294 && CONSTANT_POOL_ADDRESS_P (operands[1])
1295 && get_pool_mode (operands[1]) == SImode
1296 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1297 [(set (match_dup 0) (match_dup 2))]
1298 "operands[2] = get_pool_constant (operands[1]);")
1301 ; movhi instruction pattern(s).
1304 (define_insn "movhi"
1305 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1306 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1315 mvc\\t%O0(2,%R0),%1"
1316 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1317 (set_attr "type" "lr,*,*,*,store,store,cs")])
1320 [(set (match_operand:HI 0 "register_operand" "")
1321 (mem:HI (match_operand 1 "address_operand" "")))]
1322 "GET_CODE (operands[1]) == SYMBOL_REF
1323 && CONSTANT_POOL_ADDRESS_P (operands[1])
1324 && get_pool_mode (operands[1]) == HImode
1325 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1326 [(set (match_dup 0) (match_dup 2))]
1327 "operands[2] = get_pool_constant (operands[1]);")
1330 ; movqi instruction pattern(s).
1333 (define_insn "movqi_64"
1334 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
1335 (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
1345 mvc\\t%O0(1,%R0),%1"
1346 [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
1347 (set_attr "type" "lr,*,*,store,store,store,store,cs")])
1349 (define_insn "movqi"
1350 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1351 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1362 mvc\\t%O0(1,%R0),%1"
1363 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1364 (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
1367 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1368 (mem:QI (match_operand 1 "address_operand" "")))]
1369 "GET_CODE (operands[1]) == SYMBOL_REF
1370 && CONSTANT_POOL_ADDRESS_P (operands[1])
1371 && get_pool_mode (operands[1]) == QImode
1372 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1373 [(set (match_dup 0) (match_dup 2))]
1374 "operands[2] = get_pool_constant (operands[1]);")
1377 ; movstrictqi instruction pattern(s).
1380 (define_insn "*movstrictqi"
1381 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1382 (match_operand:QI 1 "memory_operand" "R,T"))]
1387 [(set_attr "op_type" "RX,RXY")])
1390 ; movstricthi instruction pattern(s).
1393 (define_insn "*movstricthi"
1394 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1395 (match_operand:HI 1 "s_imm_operand" "Q,S"))
1396 (clobber (reg:CC 33))]
1401 [(set_attr "op_type" "RS,RSY")])
1404 ; movstrictsi instruction pattern(s).
1407 (define_insn "movstrictsi"
1408 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
1409 (match_operand:SI 1 "general_operand" "d,R,T"))]
1415 [(set_attr "op_type" "RR,RX,RXY")
1416 (set_attr "type" "lr,load,load")])
1419 ; movdf instruction pattern(s).
1422 (define_expand "movdf"
1423 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1424 (match_operand:DF 1 "general_operand" ""))]
1427 /* During and after reload, we need to force constants
1428 to the literal pool ourselves, if necessary. */
1429 if ((reload_in_progress || reload_completed)
1430 && CONSTANT_P (operands[1]))
1431 operands[1] = force_const_mem (DFmode, operands[1]);
1434 (define_insn "*movdf_64"
1435 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1436 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1447 mvc\\t%O0(8,%R0),%1"
1448 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1449 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
1451 (define_insn "*movdf_31"
1452 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1453 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1465 mvc\\t%O0(8,%R0),%1"
1466 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
1467 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
1470 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1471 (match_operand:DF 1 "general_operand" ""))]
1472 "!TARGET_64BIT && reload_completed
1473 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1474 [(set (match_dup 2) (match_dup 4))
1475 (set (match_dup 3) (match_dup 5))]
1477 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1478 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1479 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1480 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1484 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1485 (match_operand:DF 1 "general_operand" ""))]
1486 "!TARGET_64BIT && reload_completed
1487 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1488 [(set (match_dup 2) (match_dup 4))
1489 (set (match_dup 3) (match_dup 5))]
1491 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1492 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1493 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1494 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1498 [(set (match_operand:DF 0 "register_operand" "")
1499 (match_operand:DF 1 "memory_operand" ""))]
1500 "!TARGET_64BIT && reload_completed
1501 && !FP_REG_P (operands[0])
1502 && !s_operand (operands[1], VOIDmode)"
1503 [(set (match_dup 0) (match_dup 1))]
1505 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1506 s390_load_address (addr, XEXP (operands[1], 0));
1507 operands[1] = replace_equiv_address (operands[1], addr);
1510 (define_expand "reload_outdf"
1511 [(parallel [(match_operand:DF 0 "memory_operand" "")
1512 (match_operand:DF 1 "register_operand" "d")
1513 (match_operand:SI 2 "register_operand" "=&a")])]
1516 s390_load_address (operands[2], XEXP (operands[0], 0));
1517 operands[0] = replace_equiv_address (operands[0], operands[2]);
1518 emit_move_insn (operands[0], operands[1]);
1523 ; movsf instruction pattern(s).
1526 (define_expand "movsf"
1527 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1528 (match_operand:SF 1 "general_operand" ""))]
1531 /* During and after reload, we need to force constants
1532 to the literal pool ourselves, if necessary. */
1533 if ((reload_in_progress || reload_completed)
1534 && CONSTANT_P (operands[1]))
1535 operands[1] = force_const_mem (SFmode, operands[1]);
1538 (define_insn "*movsf"
1539 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1540 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1553 mvc\\t%O0(4,%R0),%1"
1554 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1555 (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
1558 ; load_multiple pattern(s).
1561 (define_expand "load_multiple"
1562 [(match_par_dup 3 [(set (match_operand 0 "" "")
1563 (match_operand 1 "" ""))
1564 (use (match_operand 2 "" ""))])]
1572 /* Support only loading a constant number of fixed-point registers from
1573 memory and only bother with this if more than two */
1574 if (GET_CODE (operands[2]) != CONST_INT
1575 || INTVAL (operands[2]) < 2
1576 || INTVAL (operands[2]) > 16
1577 || GET_CODE (operands[1]) != MEM
1578 || GET_CODE (operands[0]) != REG
1579 || REGNO (operands[0]) >= 16)
1582 count = INTVAL (operands[2]);
1583 regno = REGNO (operands[0]);
1585 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1588 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1590 from = XEXP (operands[1], 0);
1593 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1594 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1595 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1597 from = XEXP (XEXP (operands[1], 0), 0);
1598 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1603 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1608 from = force_reg (Pmode, XEXP (operands[1], 0));
1612 for (i = 0; i < count; i++)
1613 XVECEXP (operands[3], 0, i)
1614 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1615 change_address (operands[1], Pmode,
1616 plus_constant (from,
1617 off + i * UNITS_PER_WORD)));
1620 (define_insn "*load_multiple_di"
1621 [(match_parallel 0 "load_multiple_operation"
1622 [(set (match_operand:DI 1 "register_operand" "=r")
1623 (match_operand:DI 2 "s_operand" "QS"))])]
1626 int words = XVECLEN (operands[0], 0);
1627 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1628 return "lmg\\t%1,%0,%2";
1630 [(set_attr "op_type" "RSY")
1631 (set_attr "type" "lm")])
1633 (define_insn "*load_multiple_si"
1634 [(match_parallel 0 "load_multiple_operation"
1635 [(set (match_operand:SI 1 "register_operand" "=r,r")
1636 (match_operand:SI 2 "s_operand" "Q,S"))])]
1639 int words = XVECLEN (operands[0], 0);
1640 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1641 return which_alternative == 0 ? "lm\\t%1,%0,%2" : "lmy\\t%1,%0,%2";
1643 [(set_attr "op_type" "RS,RSY")
1644 (set_attr "type" "lm")])
1647 ; store multiple pattern(s).
1650 (define_expand "store_multiple"
1651 [(match_par_dup 3 [(set (match_operand 0 "" "")
1652 (match_operand 1 "" ""))
1653 (use (match_operand 2 "" ""))])]
1661 /* Support only storing a constant number of fixed-point registers to
1662 memory and only bother with this if more than two. */
1663 if (GET_CODE (operands[2]) != CONST_INT
1664 || INTVAL (operands[2]) < 2
1665 || INTVAL (operands[2]) > 16
1666 || GET_CODE (operands[0]) != MEM
1667 || GET_CODE (operands[1]) != REG
1668 || REGNO (operands[1]) >= 16)
1671 count = INTVAL (operands[2]);
1672 regno = REGNO (operands[1]);
1674 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1678 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1680 to = XEXP (operands[0], 0);
1683 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1684 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1685 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1687 to = XEXP (XEXP (operands[0], 0), 0);
1688 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1693 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1698 to = force_reg (Pmode, XEXP (operands[0], 0));
1702 for (i = 0; i < count; i++)
1703 XVECEXP (operands[3], 0, i)
1704 = gen_rtx_SET (VOIDmode,
1705 change_address (operands[0], Pmode,
1707 off + i * UNITS_PER_WORD)),
1708 gen_rtx_REG (Pmode, regno + i));
1711 (define_insn "*store_multiple_di"
1712 [(match_parallel 0 "store_multiple_operation"
1713 [(set (match_operand:DI 1 "s_operand" "=QS")
1714 (match_operand:DI 2 "register_operand" "r"))])]
1717 int words = XVECLEN (operands[0], 0);
1718 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1719 return "stmg\\t%2,%0,%1";
1721 [(set_attr "op_type" "RSY")
1722 (set_attr "type" "stm")])
1725 (define_insn "*store_multiple_si"
1726 [(match_parallel 0 "store_multiple_operation"
1727 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1728 (match_operand:SI 2 "register_operand" "r,r"))])]
1731 int words = XVECLEN (operands[0], 0);
1732 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1733 return which_alternative == 0 ? "stm\\t%2,%0,%1" : "stmy\\t%2,%0,%1";
1735 [(set_attr "op_type" "RS,RSY")
1736 (set_attr "type" "stm")])
1739 ;; String instructions.
1743 ; movstrM instruction pattern(s).
1746 (define_expand "movstrdi"
1747 [(set (match_operand:BLK 0 "memory_operand" "")
1748 (match_operand:BLK 1 "memory_operand" ""))
1749 (use (match_operand:DI 2 "general_operand" ""))
1750 (match_operand 3 "" "")]
1752 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1754 (define_expand "movstrsi"
1755 [(set (match_operand:BLK 0 "memory_operand" "")
1756 (match_operand:BLK 1 "memory_operand" ""))
1757 (use (match_operand:SI 2 "general_operand" ""))
1758 (match_operand 3 "" "")]
1760 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1762 ; Move a block that is up to 256 bytes in length.
1763 ; The block length is taken as (operands[2] % 256) + 1.
1765 (define_insn "movstr_short_64"
1766 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1767 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1768 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1769 (clobber (match_scratch:DI 3 "=X,&a"))]
1772 switch (which_alternative)
1775 return "mvc\\t%O0(%b2+1,%R0),%1";
1778 output_asm_insn ("bras\\t%3,.+10", operands);
1779 output_asm_insn ("mvc\\t%O0(1,%R0),%1", operands);
1780 return "ex\\t%2,0(%3)";
1786 [(set_attr "op_type" "SS,NN")
1787 (set_attr "type" "cs,cs")
1788 (set_attr "atype" "*,agen")
1789 (set_attr "length" "*,14")])
1791 (define_insn "movstr_short_31"
1792 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1793 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1794 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1795 (clobber (match_scratch:SI 3 "=X,&a"))]
1798 switch (which_alternative)
1801 return "mvc\\t%O0(%b2+1,%R0),%1";
1804 output_asm_insn ("bras\\t%3,.+10", operands);
1805 output_asm_insn ("mvc\\t%O0(1,%R0),%1", operands);
1806 return "ex\\t%2,0(%3)";
1812 [(set_attr "op_type" "SS,NN")
1813 (set_attr "type" "cs,cs")
1814 (set_attr "atype" "*,agen")
1815 (set_attr "length" "*,14")])
1817 ; Move a block of arbitrary length.
1819 (define_insn "movstr_long_64"
1820 [(set (match_operand:TI 0 "register_operand" "=d")
1821 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1822 (lshiftrt:TI (match_dup 2) (const_int 64)))
1824 (set (match_operand:TI 1 "register_operand" "=d")
1825 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1826 (lshiftrt:TI (match_dup 3) (const_int 64)))
1828 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1829 (mem:BLK (subreg:DI (match_dup 3) 0)))
1830 (clobber (reg:CC 33))]
1832 "mvcle\\t%0,%1,0\;jo\\t.-4"
1833 [(set_attr "op_type" "NN")
1834 (set_attr "type" "vs")
1835 (set_attr "length" "8")])
1837 (define_insn "movstr_long_31"
1838 [(set (match_operand:DI 0 "register_operand" "=d")
1839 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1840 (lshiftrt:DI (match_dup 2) (const_int 32)))
1842 (set (match_operand:DI 1 "register_operand" "=d")
1843 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1844 (lshiftrt:DI (match_dup 3) (const_int 32)))
1846 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1847 (mem:BLK (subreg:SI (match_dup 3) 0)))
1848 (clobber (reg:CC 33))]
1850 "mvcle\\t%0,%1,0\;jo\\t.-4"
1851 [(set_attr "op_type" "NN")
1852 (set_attr "type" "vs")
1853 (set_attr "length" "8")])
1856 ; clrstrM instruction pattern(s).
1859 (define_expand "clrstrdi"
1860 [(set (match_operand:BLK 0 "memory_operand" "")
1862 (use (match_operand:DI 1 "general_operand" ""))
1863 (match_operand 2 "" "")]
1865 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1867 (define_expand "clrstrsi"
1868 [(set (match_operand:BLK 0 "memory_operand" "")
1870 (use (match_operand:SI 1 "general_operand" ""))
1871 (match_operand 2 "" "")]
1873 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1875 ; Clear a block that is up to 256 bytes in length.
1876 ; The block length is taken as (operands[2] % 256) + 1.
1878 (define_insn "clrstr_short_64"
1879 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1881 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1882 (clobber (match_scratch:DI 2 "=X,&a"))
1883 (clobber (reg:CC 33))]
1886 switch (which_alternative)
1889 return "xc\\t%O0(%b1+1,%R0),%0";
1892 output_asm_insn ("bras\\t%2,.+10", operands);
1893 output_asm_insn ("xc\\t%O0(1,%R0),%0", operands);
1894 return "ex\\t%1,0(%2)";
1900 [(set_attr "op_type" "SS,NN")
1901 (set_attr "type" "cs,cs")
1902 (set_attr "atype" "*,agen")
1903 (set_attr "length" "*,14")])
1905 (define_insn "clrstr_short_31"
1906 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1908 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1909 (clobber (match_scratch:SI 2 "=X,&a"))
1910 (clobber (reg:CC 33))]
1913 switch (which_alternative)
1916 return "xc\\t%O0(%b1+1,%R0),%0";
1919 output_asm_insn ("bras\\t%2,.+10", operands);
1920 output_asm_insn ("xc\\t%O0(1,%R0),%0", operands);
1921 return "ex\\t%1,0(%2)";
1927 [(set_attr "op_type" "SS,NN")
1928 (set_attr "type" "cs,cs")
1929 (set_attr "atype" "*,agen")
1930 (set_attr "length" "*,14")])
1932 ; Clear a block of arbitrary length.
1934 (define_insn "clrstr_long_64"
1935 [(set (match_operand:TI 0 "register_operand" "=d")
1936 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1937 (lshiftrt:TI (match_dup 2) (const_int 64)))
1939 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1941 (use (match_operand:TI 1 "register_operand" "d"))
1942 (clobber (reg:CC 33))]
1944 "mvcle\\t%0,%1,0\;jo\\t.-4"
1945 [(set_attr "op_type" "NN")
1946 (set_attr "type" "vs")
1947 (set_attr "length" "8")])
1949 (define_insn "clrstr_long_31"
1950 [(set (match_operand:DI 0 "register_operand" "=d")
1951 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1952 (lshiftrt:DI (match_dup 2) (const_int 32)))
1954 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1956 (use (match_operand:DI 1 "register_operand" "d"))
1957 (clobber (reg:CC 33))]
1959 "mvcle\\t%0,%1,0\;jo\\t.-4"
1960 [(set_attr "op_type" "NN")
1961 (set_attr "type" "vs")
1962 (set_attr "length" "8")])
1965 ; cmpmemM instruction pattern(s).
1968 (define_expand "cmpmemdi"
1969 [(set (match_operand:DI 0 "register_operand" "")
1970 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1971 (match_operand:BLK 2 "memory_operand" "") ) )
1972 (use (match_operand:DI 3 "general_operand" ""))
1973 (use (match_operand:DI 4 "" ""))]
1975 "s390_expand_cmpmem (operands[0], operands[1],
1976 operands[2], operands[3]); DONE;")
1978 (define_expand "cmpmemsi"
1979 [(set (match_operand:SI 0 "register_operand" "")
1980 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1981 (match_operand:BLK 2 "memory_operand" "") ) )
1982 (use (match_operand:SI 3 "general_operand" ""))
1983 (use (match_operand:SI 4 "" ""))]
1985 "s390_expand_cmpmem (operands[0], operands[1],
1986 operands[2], operands[3]); DONE;")
1988 ; Compare a block that is up to 256 bytes in length.
1989 ; The block length is taken as (operands[2] % 256) + 1.
1991 (define_insn "cmpmem_short_64"
1993 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1994 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1995 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1996 (clobber (match_scratch:DI 3 "=X,&a"))]
1999 switch (which_alternative)
2002 return "clc\\t%O0(%b2+1,%R0),%1";
2005 output_asm_insn ("bras\\t%3,.+10", operands);
2006 output_asm_insn ("clc\\t%O0(1,%R0),%1", operands);
2007 return "ex\\t%2,0(%3)";
2013 [(set_attr "op_type" "SS,NN")
2014 (set_attr "type" "cs,cs")
2015 (set_attr "atype" "*,agen")
2016 (set_attr "length" "*,14")])
2018 (define_insn "cmpmem_short_31"
2020 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
2021 (match_operand:BLK 1 "memory_operand" "Q,Q")))
2022 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
2023 (clobber (match_scratch:SI 3 "=X,&a"))]
2026 switch (which_alternative)
2029 return "clc\\t%O0(%b2+1,%R0),%1";
2032 output_asm_insn ("bras\\t%3,.+10", operands);
2033 output_asm_insn ("clc\\t%O0(1,%R0),%1", operands);
2034 return "ex\\t%2,0(%3)";
2040 [(set_attr "op_type" "SS,NN")
2041 (set_attr "type" "cs,cs")
2042 (set_attr "atype" "*,agen")
2043 (set_attr "length" "*,14")])
2045 ; Compare a block of arbitrary length.
2047 (define_insn "cmpmem_long_64"
2048 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2049 (clobber (match_operand:TI 1 "register_operand" "=d"))
2051 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2052 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2054 (use (match_dup 3))]
2057 [(set_attr "op_type" "RR")
2058 (set_attr "type" "vs")])
2060 (define_insn "cmpmem_long_31"
2061 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2062 (clobber (match_operand:DI 1 "register_operand" "=d"))
2064 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2065 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2067 (use (match_dup 3))]
2070 [(set_attr "op_type" "RR")
2071 (set_attr "type" "vs")])
2073 ; Convert condition code to integer in range (-1, 0, 1)
2075 (define_insn "cmpint_si"
2076 [(set (match_operand:SI 0 "register_operand" "=d")
2077 (compare:SI (reg:CCS 33) (const_int 0)))]
2080 output_asm_insn ("lhi\\t%0,1", operands);
2081 output_asm_insn ("jh\\t.+12", operands);
2082 output_asm_insn ("jl\\t.+6", operands);
2083 output_asm_insn ("sr\\t%0,%0", operands);
2084 return "lcr\\t%0,%0";
2086 [(set_attr "op_type" "NN")
2087 (set_attr "length" "16")
2088 (set_attr "type" "other")])
2090 (define_insn "cmpint_di"
2091 [(set (match_operand:DI 0 "register_operand" "=d")
2092 (compare:DI (reg:CCS 33) (const_int 0)))]
2095 output_asm_insn ("lghi\\t%0,1", operands);
2096 output_asm_insn ("jh\\t.+12", operands);
2097 output_asm_insn ("jl\\t.+6", operands);
2098 output_asm_insn ("sgr\\t%0,%0", operands);
2099 return "lcgr\\t%0,%0";
2101 [(set_attr "op_type" "NN")
2102 (set_attr "length" "22")
2103 (set_attr "type" "other")])
2107 ;;- Conversion instructions.
2110 (define_insn "*sethighqisi"
2111 [(set (match_operand:SI 0 "register_operand" "=d,d")
2112 (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2113 (clobber (reg:CC 33))]
2118 [(set_attr "op_type" "RS,RSY")])
2120 (define_insn "*sethighhisi"
2121 [(set (match_operand:SI 0 "register_operand" "=d,d")
2122 (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2123 (clobber (reg:CC 33))]
2128 [(set_attr "op_type" "RS,RSY")])
2130 (define_insn "*sethighqidi_64"
2131 [(set (match_operand:DI 0 "register_operand" "=d")
2132 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2133 (clobber (reg:CC 33))]
2136 [(set_attr "op_type" "RSY")])
2138 (define_insn "*sethighqidi_31"
2139 [(set (match_operand:DI 0 "register_operand" "=d,d")
2140 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2141 (clobber (reg:CC 33))]
2146 [(set_attr "op_type" "RS,RSY")])
2148 (define_insn_and_split "*extractqi"
2149 [(set (match_operand:SI 0 "register_operand" "=d")
2150 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2151 (match_operand 2 "const_int_operand" "n")
2153 (clobber (reg:CC 33))]
2155 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2157 "&& reload_completed"
2159 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2160 (clobber (reg:CC 33))])
2161 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2163 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2164 operands[1] = change_address (operands[1], QImode, 0);
2166 [(set_attr "atype" "agen")])
2168 (define_insn_and_split "*extracthi"
2169 [(set (match_operand:SI 0 "register_operand" "=d")
2170 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2171 (match_operand 2 "const_int_operand" "n")
2173 (clobber (reg:CC 33))]
2175 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2177 "&& reload_completed"
2179 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2180 (clobber (reg:CC 33))])
2181 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2183 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2184 operands[1] = change_address (operands[1], HImode, 0);
2186 [(set_attr "atype" "agen")])
2189 ; extendsidi2 instruction pattern(s).
2192 (define_expand "extendsidi2"
2193 [(set (match_operand:DI 0 "register_operand" "")
2194 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2200 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2201 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2202 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2203 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2209 (define_insn "*extendsidi2"
2210 [(set (match_operand:DI 0 "register_operand" "=d,d")
2211 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2216 [(set_attr "op_type" "RRE,RXY")])
2219 ; extendhidi2 instruction pattern(s).
2222 (define_expand "extendhidi2"
2223 [(set (match_operand:DI 0 "register_operand" "")
2224 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2230 rtx tmp = gen_reg_rtx (SImode);
2231 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2232 emit_insn (gen_extendsidi2 (operands[0], tmp));
2237 operands[1] = gen_lowpart (DImode, operands[1]);
2238 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2239 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2245 (define_insn "*extendhidi2"
2246 [(set (match_operand:DI 0 "register_operand" "=d")
2247 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2250 [(set_attr "op_type" "RXY")])
2253 ; extendqidi2 instruction pattern(s).
2256 (define_expand "extendqidi2"
2257 [(set (match_operand:DI 0 "register_operand" "")
2258 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2264 rtx tmp = gen_reg_rtx (SImode);
2265 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2266 emit_insn (gen_extendsidi2 (operands[0], tmp));
2271 operands[1] = gen_lowpart (DImode, operands[1]);
2272 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2273 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2279 (define_insn "*extendqidi2"
2280 [(set (match_operand:DI 0 "register_operand" "=d")
2281 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2282 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2284 [(set_attr "op_type" "RXY")])
2287 [(set (match_operand:DI 0 "register_operand" "")
2288 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2289 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
2291 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2292 (clobber (reg:CC 33))])
2294 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2295 (clobber (reg:CC 33))])]
2299 ; extendhisi2 instruction pattern(s).
2302 (define_expand "extendhisi2"
2303 [(set (match_operand:SI 0 "register_operand" "")
2304 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2308 operands[1] = gen_lowpart (SImode, operands[1]);
2309 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2310 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2315 (define_insn "*extendhisi2"
2316 [(set (match_operand:SI 0 "register_operand" "=d,d")
2317 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2322 [(set_attr "op_type" "RX,RXY")])
2325 ; extendqisi2 instruction pattern(s).
2328 (define_expand "extendqisi2"
2329 [(set (match_operand:SI 0 "register_operand" "")
2330 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2334 operands[1] = gen_lowpart (SImode, operands[1]);
2335 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2336 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2341 (define_insn "*extendqisi2"
2342 [(set (match_operand:SI 0 "register_operand" "=d")
2343 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2344 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2346 [(set_attr "op_type" "RXY")])
2349 [(set (match_operand:SI 0 "register_operand" "")
2350 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2351 "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
2353 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2354 (clobber (reg:CC 33))])
2356 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2357 (clobber (reg:CC 33))])]
2361 ; extendqihi2 instruction pattern(s).
2366 ; zero_extendsidi2 instruction pattern(s).
2369 (define_expand "zero_extendsidi2"
2370 [(set (match_operand:DI 0 "register_operand" "")
2371 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2377 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2378 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2379 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2385 (define_insn "*zero_extendsidi2"
2386 [(set (match_operand:DI 0 "register_operand" "=d,d")
2387 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2392 [(set_attr "op_type" "RRE,RXY")])
2395 ; zero_extendhidi2 instruction pattern(s).
2398 (define_expand "zero_extendhidi2"
2399 [(set (match_operand:DI 0 "register_operand" "")
2400 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2406 rtx tmp = gen_reg_rtx (SImode);
2407 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2408 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2413 operands[1] = gen_lowpart (DImode, operands[1]);
2414 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2415 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2421 (define_insn "*zero_extendhidi2"
2422 [(set (match_operand:DI 0 "register_operand" "=d")
2423 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2426 [(set_attr "op_type" "RXY")])
2429 ; zero_extendqidi2 instruction pattern(s)
2432 (define_expand "zero_extendqidi2"
2433 [(set (match_operand:DI 0 "register_operand" "")
2434 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2440 rtx tmp = gen_reg_rtx (SImode);
2441 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2442 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2447 operands[1] = gen_lowpart (DImode, operands[1]);
2448 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2449 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2455 (define_insn "*zero_extendqidi2"
2456 [(set (match_operand:DI 0 "register_operand" "=d")
2457 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2460 [(set_attr "op_type" "RXY")])
2463 ; zero_extendhisi2 instruction pattern(s).
2466 (define_expand "zero_extendhisi2"
2467 [(set (match_operand:SI 0 "register_operand" "")
2468 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2472 operands[1] = gen_lowpart (SImode, operands[1]);
2473 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2478 (define_insn "*zero_extendhisi2_64"
2479 [(set (match_operand:SI 0 "register_operand" "=d")
2480 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2483 [(set_attr "op_type" "RXY")])
2485 (define_insn_and_split "*zero_extendhisi2_31"
2486 [(set (match_operand:SI 0 "register_operand" "=&d")
2487 (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
2488 (clobber (reg:CC 33))]
2491 "&& reload_completed"
2492 [(set (match_dup 0) (const_int 0))
2494 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2495 (clobber (reg:CC 33))])]
2496 "operands[2] = gen_lowpart (HImode, operands[0]);"
2497 [(set_attr "atype" "agen")])
2500 ; zero_extendqisi2 instruction pattern(s).
2503 (define_expand "zero_extendqisi2"
2504 [(set (match_operand:SI 0 "register_operand" "")
2505 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2509 operands[1] = gen_lowpart (SImode, operands[1]);
2510 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2515 (define_insn "*zero_extendqisi2_64"
2516 [(set (match_operand:SI 0 "register_operand" "=d")
2517 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2520 [(set_attr "op_type" "RXY")])
2522 (define_insn_and_split "*zero_extendqisi2_31"
2523 [(set (match_operand:SI 0 "register_operand" "=&d")
2524 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2527 "&& reload_completed"
2528 [(set (match_dup 0) (const_int 0))
2529 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2530 "operands[2] = gen_lowpart (QImode, operands[0]);"
2531 [(set_attr "atype" "agen")])
2534 ; zero_extendqihi2 instruction pattern(s).
2537 (define_expand "zero_extendqihi2"
2538 [(set (match_operand:HI 0 "register_operand" "")
2539 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2543 operands[1] = gen_lowpart (HImode, operands[1]);
2544 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2549 (define_insn "*zero_extendqihi2_64"
2550 [(set (match_operand:HI 0 "register_operand" "=d")
2551 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2554 [(set_attr "op_type" "RXY")])
2556 (define_insn_and_split "*zero_extendqihi2_31"
2557 [(set (match_operand:HI 0 "register_operand" "=&d")
2558 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2561 "&& reload_completed"
2562 [(set (match_dup 0) (const_int 0))
2563 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2564 "operands[2] = gen_lowpart (QImode, operands[0]);"
2565 [(set_attr "atype" "agen")])
2569 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2572 (define_expand "fixuns_truncdfdi2"
2573 [(set (match_operand:DI 0 "register_operand" "")
2574 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2575 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2577 rtx label1 = gen_label_rtx ();
2578 rtx label2 = gen_label_rtx ();
2579 rtx temp = gen_reg_rtx (DFmode);
2580 operands[1] = force_reg (DFmode, operands[1]);
2582 emit_insn (gen_cmpdf (operands[1],
2583 CONST_DOUBLE_FROM_REAL_VALUE (
2584 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2585 emit_jump_insn (gen_blt (label1));
2586 emit_insn (gen_subdf3 (temp, operands[1],
2587 CONST_DOUBLE_FROM_REAL_VALUE (
2588 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2589 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2592 emit_label (label1);
2593 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2594 emit_label (label2);
2598 (define_expand "fix_truncdfdi2"
2599 [(set (match_operand:DI 0 "register_operand" "")
2600 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2601 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2603 operands[1] = force_reg (DFmode, operands[1]);
2604 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2608 (define_insn "fix_truncdfdi2_ieee"
2609 [(set (match_operand:DI 0 "register_operand" "=d")
2610 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2611 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2612 (clobber (reg:CC 33))]
2613 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2615 [(set_attr "op_type" "RRE")
2616 (set_attr "type" "ftoi")])
2619 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2622 (define_expand "fixuns_truncdfsi2"
2623 [(set (match_operand:SI 0 "register_operand" "")
2624 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2625 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2627 rtx label1 = gen_label_rtx ();
2628 rtx label2 = gen_label_rtx ();
2629 rtx temp = gen_reg_rtx (DFmode);
2631 operands[1] = force_reg (DFmode,operands[1]);
2632 emit_insn (gen_cmpdf (operands[1],
2633 CONST_DOUBLE_FROM_REAL_VALUE (
2634 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2635 emit_jump_insn (gen_blt (label1));
2636 emit_insn (gen_subdf3 (temp, operands[1],
2637 CONST_DOUBLE_FROM_REAL_VALUE (
2638 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2639 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2642 emit_label (label1);
2643 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2644 emit_label (label2);
2648 (define_expand "fix_truncdfsi2"
2649 [(set (match_operand:SI 0 "register_operand" "")
2650 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2653 if (TARGET_IBM_FLOAT)
2655 /* This is the algorithm from POP chapter A.5.7.2. */
2657 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2658 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2659 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2661 operands[1] = force_reg (DFmode, operands[1]);
2662 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2663 two31r, two32, temp));
2667 operands[1] = force_reg (DFmode, operands[1]);
2668 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2674 (define_insn "fix_truncdfsi2_ieee"
2675 [(set (match_operand:SI 0 "register_operand" "=d")
2676 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2677 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2678 (clobber (reg:CC 33))]
2679 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2681 [(set_attr "op_type" "RRE")
2682 (set_attr "type" "other" )])
2684 (define_insn "fix_truncdfsi2_ibm"
2685 [(set (match_operand:SI 0 "register_operand" "=d")
2686 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2687 (use (match_operand:DI 2 "immediate_operand" "m"))
2688 (use (match_operand:DI 3 "immediate_operand" "m"))
2689 (use (match_operand:BLK 4 "memory_operand" "m"))
2690 (clobber (reg:CC 33))]
2691 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2693 output_asm_insn ("sd\\t%1,%2", operands);
2694 output_asm_insn ("aw\\t%1,%3", operands);
2695 output_asm_insn ("std\\t%1,%4", operands);
2696 output_asm_insn ("xi\\t%N4,128", operands);
2697 return "l\\t%0,%N4";
2699 [(set_attr "op_type" "NN")
2700 (set_attr "type" "ftoi")
2701 (set_attr "atype" "agen")
2702 (set_attr "length" "20")])
2705 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2708 (define_expand "fixuns_truncsfdi2"
2709 [(set (match_operand:DI 0 "register_operand" "")
2710 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2711 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2713 rtx label1 = gen_label_rtx ();
2714 rtx label2 = gen_label_rtx ();
2715 rtx temp = gen_reg_rtx (SFmode);
2717 operands[1] = force_reg (SFmode, operands[1]);
2718 emit_insn (gen_cmpsf (operands[1],
2719 CONST_DOUBLE_FROM_REAL_VALUE (
2720 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
2721 emit_jump_insn (gen_blt (label1));
2723 emit_insn (gen_subsf3 (temp, operands[1],
2724 CONST_DOUBLE_FROM_REAL_VALUE (
2725 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
2726 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2729 emit_label (label1);
2730 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2731 emit_label (label2);
2735 (define_expand "fix_truncsfdi2"
2736 [(set (match_operand:DI 0 "register_operand" "")
2737 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2738 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2740 operands[1] = force_reg (SFmode, operands[1]);
2741 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2745 (define_insn "fix_truncsfdi2_ieee"
2746 [(set (match_operand:DI 0 "register_operand" "=d")
2747 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2748 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2749 (clobber (reg:CC 33))]
2750 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2752 [(set_attr "op_type" "RRE")
2753 (set_attr "type" "ftoi")])
2756 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2759 (define_expand "fixuns_truncsfsi2"
2760 [(set (match_operand:SI 0 "register_operand" "")
2761 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2762 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2764 rtx label1 = gen_label_rtx ();
2765 rtx label2 = gen_label_rtx ();
2766 rtx temp = gen_reg_rtx (SFmode);
2768 operands[1] = force_reg (SFmode, operands[1]);
2769 emit_insn (gen_cmpsf (operands[1],
2770 CONST_DOUBLE_FROM_REAL_VALUE (
2771 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
2772 emit_jump_insn (gen_blt (label1));
2773 emit_insn (gen_subsf3 (temp, operands[1],
2774 CONST_DOUBLE_FROM_REAL_VALUE (
2775 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
2776 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2779 emit_label (label1);
2780 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2781 emit_label (label2);
2785 (define_expand "fix_truncsfsi2"
2786 [(set (match_operand:SI 0 "register_operand" "")
2787 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2790 if (TARGET_IBM_FLOAT)
2792 /* Convert to DFmode and then use the POP algorithm. */
2793 rtx temp = gen_reg_rtx (DFmode);
2794 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2795 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2799 operands[1] = force_reg (SFmode, operands[1]);
2800 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2806 (define_insn "fix_truncsfsi2_ieee"
2807 [(set (match_operand:SI 0 "register_operand" "=d")
2808 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2809 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2810 (clobber (reg:CC 33))]
2811 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2813 [(set_attr "op_type" "RRE")
2814 (set_attr "type" "ftoi")])
2817 ; floatdidf2 instruction pattern(s).
2820 (define_insn "floatdidf2"
2821 [(set (match_operand:DF 0 "register_operand" "=f")
2822 (float:DF (match_operand:DI 1 "register_operand" "d")))
2823 (clobber (reg:CC 33))]
2824 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2826 [(set_attr "op_type" "RRE")
2827 (set_attr "type" "itof" )])
2830 ; floatdisf2 instruction pattern(s).
2833 (define_insn "floatdisf2"
2834 [(set (match_operand:SF 0 "register_operand" "=f")
2835 (float:SF (match_operand:DI 1 "register_operand" "d")))
2836 (clobber (reg:CC 33))]
2837 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2839 [(set_attr "op_type" "RRE")
2840 (set_attr "type" "itof" )])
2843 ; floatsidf2 instruction pattern(s).
2846 (define_expand "floatsidf2"
2848 [(set (match_operand:DF 0 "register_operand" "")
2849 (float:DF (match_operand:SI 1 "register_operand" "")))
2850 (clobber (reg:CC 33))])]
2853 if (TARGET_IBM_FLOAT)
2855 /* This is the algorithm from POP chapter A.5.7.1. */
2857 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2858 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2860 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2865 (define_insn "floatsidf2_ieee"
2866 [(set (match_operand:DF 0 "register_operand" "=f")
2867 (float:DF (match_operand:SI 1 "register_operand" "d")))
2868 (clobber (reg:CC 33))]
2869 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2871 [(set_attr "op_type" "RRE")
2872 (set_attr "type" "itof" )])
2874 (define_insn "floatsidf2_ibm"
2875 [(set (match_operand:DF 0 "register_operand" "=f")
2876 (float:DF (match_operand:SI 1 "register_operand" "d")))
2877 (use (match_operand:DI 2 "immediate_operand" "m"))
2878 (use (match_operand:BLK 3 "memory_operand" "m"))
2879 (clobber (reg:CC 33))]
2880 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2882 output_asm_insn ("st\\t%1,%N3", operands);
2883 output_asm_insn ("xi\\t%N3,128", operands);
2884 output_asm_insn ("mvc\\t%O3(4,%R3),%2", operands);
2885 output_asm_insn ("ld\\t%0,%3", operands);
2886 return "sd\\t%0,%2";
2888 [(set_attr "op_type" "NN")
2889 (set_attr "type" "other" )
2890 (set_attr "atype" "agen")
2891 (set_attr "length" "20")])
2894 ; floatsisf2 instruction pattern(s).
2897 (define_expand "floatsisf2"
2899 [(set (match_operand:SF 0 "register_operand" "")
2900 (float:SF (match_operand:SI 1 "register_operand" "")))
2901 (clobber (reg:CC 33))])]
2904 if (TARGET_IBM_FLOAT)
2906 /* Use the POP algorithm to convert to DFmode and then truncate. */
2907 rtx temp = gen_reg_rtx (DFmode);
2908 emit_insn (gen_floatsidf2 (temp, operands[1]));
2909 emit_insn (gen_truncdfsf2 (operands[0], temp));
2914 (define_insn "floatsisf2_ieee"
2915 [(set (match_operand:SF 0 "register_operand" "=f")
2916 (float:SF (match_operand:SI 1 "register_operand" "d")))
2917 (clobber (reg:CC 33))]
2918 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2920 [(set_attr "op_type" "RRE")
2921 (set_attr "type" "itof" )])
2924 ; truncdfsf2 instruction pattern(s).
2927 (define_expand "truncdfsf2"
2928 [(set (match_operand:SF 0 "register_operand" "")
2929 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2933 (define_insn "truncdfsf2_ieee"
2934 [(set (match_operand:SF 0 "register_operand" "=f")
2935 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2936 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2938 [(set_attr "op_type" "RRE")])
2940 (define_insn "truncdfsf2_ibm"
2941 [(set (match_operand:SF 0 "register_operand" "=f,f")
2942 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
2943 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2947 [(set_attr "op_type" "RR,RX")
2948 (set_attr "type" "floads,floads")])
2951 ; extendsfdf2 instruction pattern(s).
2954 (define_expand "extendsfdf2"
2955 [(set (match_operand:DF 0 "register_operand" "")
2956 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2959 if (TARGET_IBM_FLOAT)
2961 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2966 (define_insn "extendsfdf2_ieee"
2967 [(set (match_operand:DF 0 "register_operand" "=f,f")
2968 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2969 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2973 [(set_attr "op_type" "RRE,RXE")
2974 (set_attr "type" "floads,floads")])
2976 (define_insn "extendsfdf2_ibm"
2977 [(set (match_operand:DF 0 "register_operand" "=f,f")
2978 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2979 (clobber (reg:CC 33))]
2980 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2982 sdr\\t%0,%0\;ler\\t%0,%1
2983 sdr\\t%0,%0\;le\\t%0,%1"
2984 [(set_attr "op_type" "NN,NN")
2985 (set_attr "atype" "reg,agen")
2986 (set_attr "length" "4,6")
2987 (set_attr "type" "o2,o2")])
2991 ;; ARITHMETIC OPERATIONS
2993 ; arithmetic operations set the ConditionCode,
2994 ; because of unpredictable Bits in Register for Halfword and Byte
2995 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2998 ;;- Add instructions.
3002 ; adddi3 instruction pattern(s).
3005 (define_insn "*adddi3_sign"
3006 [(set (match_operand:DI 0 "register_operand" "=d,d")
3007 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3008 (match_operand:DI 1 "register_operand" "0,0")))
3009 (clobber (reg:CC 33))]
3014 [(set_attr "op_type" "RRE,RXY")])
3016 (define_insn "*adddi3_zero_cc"
3018 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3019 (match_operand:DI 1 "register_operand" "0,0"))
3021 (set (match_operand:DI 0 "register_operand" "=d,d")
3022 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3023 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3027 [(set_attr "op_type" "RRE,RXY")])
3029 (define_insn "*adddi3_zero_cconly"
3031 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3032 (match_operand:DI 1 "register_operand" "0,0"))
3034 (clobber (match_scratch:DI 0 "=d,d"))]
3035 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3039 [(set_attr "op_type" "RRE,RXY")])
3041 (define_insn "*adddi3_zero"
3042 [(set (match_operand:DI 0 "register_operand" "=d,d")
3043 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3044 (match_operand:DI 1 "register_operand" "0,0")))
3045 (clobber (reg:CC 33))]
3050 [(set_attr "op_type" "RRE,RXY")])
3052 (define_insn "*adddi3_imm_cc"
3054 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3055 (match_operand:DI 2 "const_int_operand" "K"))
3057 (set (match_operand:DI 0 "register_operand" "=d")
3058 (plus:DI (match_dup 1) (match_dup 2)))]
3060 && s390_match_ccmode (insn, CCAmode)
3061 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3063 [(set_attr "op_type" "RI")])
3065 (define_insn "*adddi3_cc"
3067 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3068 (match_operand:DI 2 "general_operand" "d,m"))
3070 (set (match_operand:DI 0 "register_operand" "=d,d")
3071 (plus:DI (match_dup 1) (match_dup 2)))]
3072 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3076 [(set_attr "op_type" "RRE,RXY")])
3078 (define_insn "*adddi3_cconly"
3080 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3081 (match_operand:DI 2 "general_operand" "d,m"))
3083 (clobber (match_scratch:DI 0 "=d,d"))]
3084 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3088 [(set_attr "op_type" "RRE,RXY")])
3090 (define_insn "*adddi3_cconly2"
3092 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3093 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3094 (clobber (match_scratch:DI 0 "=d,d"))]
3095 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3099 [(set_attr "op_type" "RRE,RXY")])
3101 (define_insn "*adddi3_64"
3102 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3103 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3104 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3105 (clobber (reg:CC 33))]
3111 [(set_attr "op_type" "RRE,RI,RXY")])
3113 (define_insn_and_split "*adddi3_31"
3114 [(set (match_operand:DI 0 "register_operand" "=&d")
3115 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3116 (match_operand:DI 2 "general_operand" "do") ) )
3117 (clobber (reg:CC 33))]
3120 "&& reload_completed"
3122 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3123 (clobber (reg:CC 33))])
3126 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3128 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3130 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3132 (label_ref (match_dup 9))))
3134 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3135 (clobber (reg:CC 33))])
3137 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3138 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3139 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3140 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3141 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3142 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3143 operands[9] = gen_label_rtx ();"
3144 [(set_attr "op_type" "NN")])
3146 (define_expand "adddi3"
3148 [(set (match_operand:DI 0 "register_operand" "")
3149 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3150 (match_operand:DI 2 "general_operand" "")))
3151 (clobber (reg:CC 33))])]
3155 (define_insn "*la_64"
3156 [(set (match_operand:DI 0 "register_operand" "=d,d")
3157 (match_operand:QI 1 "address_operand" "U,W"))]
3162 [(set_attr "op_type" "RX,RXY")
3163 (set_attr "type" "la")])
3167 [(set (match_operand:DI 0 "register_operand" "")
3168 (match_operand:QI 1 "address_operand" ""))
3169 (clobber (reg:CC 33))])]
3171 && strict_memory_address_p (VOIDmode, operands[1])
3172 && preferred_la_operand_p (operands[1])"
3173 [(set (match_dup 0) (match_dup 1))]
3177 [(set (match_operand:DI 0 "register_operand" "")
3178 (match_operand:DI 1 "register_operand" ""))
3181 (plus:DI (match_dup 0)
3182 (match_operand:DI 2 "nonmemory_operand" "")))
3183 (clobber (reg:CC 33))])]
3185 && !reg_overlap_mentioned_p (operands[0], operands[2])
3186 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2]))
3187 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))"
3188 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3191 (define_expand "reload_indi"
3192 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3193 (match_operand:DI 1 "s390_plus_operand" "")
3194 (match_operand:DI 2 "register_operand" "=&a")])]
3197 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3203 ; addsi3 instruction pattern(s).
3206 (define_insn "*addsi3_imm_cc"
3208 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3209 (match_operand:SI 2 "const_int_operand" "K"))
3211 (set (match_operand:SI 0 "register_operand" "=d")
3212 (plus:SI (match_dup 1) (match_dup 2)))]
3213 "s390_match_ccmode (insn, CCAmode)
3214 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3216 [(set_attr "op_type" "RI")])
3218 (define_insn "*addsi3_carry1_cc"
3220 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3221 (match_operand:SI 2 "general_operand" "d,R,T"))
3223 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3224 (plus:SI (match_dup 1) (match_dup 2)))]
3225 "s390_match_ccmode (insn, CCL1mode)"
3230 [(set_attr "op_type" "RR,RX,RXY")])
3232 (define_insn "*addsi3_carry1_cconly"
3234 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3235 (match_operand:SI 2 "general_operand" "d,R,T"))
3237 (clobber (match_scratch:SI 0 "=d,d,d"))]
3238 "s390_match_ccmode (insn, CCL1mode)"
3243 [(set_attr "op_type" "RR,RX,RXY")])
3245 (define_insn "*addsi3_carry2_cc"
3247 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3248 (match_operand:SI 2 "general_operand" "d,R,T"))
3250 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3251 (plus:SI (match_dup 1) (match_dup 2)))]
3252 "s390_match_ccmode (insn, CCL1mode)"
3257 [(set_attr "op_type" "RR,RX,RXY")])
3259 (define_insn "*addsi3_carry2_cconly"
3261 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3262 (match_operand:SI 2 "general_operand" "d,R,T"))
3264 (clobber (match_scratch:SI 0 "=d,d,d"))]
3265 "s390_match_ccmode (insn, CCL1mode)"
3270 [(set_attr "op_type" "RR,RX,RXY")])
3272 (define_insn "*addsi3_cc"
3274 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3275 (match_operand:SI 2 "general_operand" "d,R,T"))
3277 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3278 (plus:SI (match_dup 1) (match_dup 2)))]
3279 "s390_match_ccmode (insn, CCLmode)"
3284 [(set_attr "op_type" "RR,RX,RXY")])
3286 (define_insn "*addsi3_cconly"
3288 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3289 (match_operand:SI 2 "general_operand" "d,R,T"))
3291 (clobber (match_scratch:SI 0 "=d,d,d"))]
3292 "s390_match_ccmode (insn, CCLmode)"
3297 [(set_attr "op_type" "RR,RX,RXY")])
3299 (define_insn "*addsi3_cconly2"
3301 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3302 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3303 (clobber (match_scratch:SI 0 "=d,d,d"))]
3304 "s390_match_ccmode(insn, CCLmode)"
3309 [(set_attr "op_type" "RR,RX,RXY")])
3311 (define_insn "*addsi3_sign"
3312 [(set (match_operand:SI 0 "register_operand" "=d,d")
3313 (plus:SI (match_operand:SI 1 "register_operand" "0,0")
3314 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3315 (clobber (reg:CC 33))]
3320 [(set_attr "op_type" "RX,RXY")])
3322 (define_insn "*addsi3_sub"
3323 [(set (match_operand:SI 0 "register_operand" "=d,d")
3324 (plus:SI (match_operand:SI 1 "register_operand" "0,0")
3325 (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
3326 (clobber (reg:CC 33))]
3331 [(set_attr "op_type" "RX,RXY")])
3333 (define_insn "addsi3"
3334 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3335 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3336 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3337 (clobber (reg:CC 33))]
3344 [(set_attr "op_type" "RR,RI,RX,RXY")])
3346 (define_insn "*la_31"
3347 [(set (match_operand:SI 0 "register_operand" "=d,d")
3348 (match_operand:QI 1 "address_operand" "U,W"))]
3349 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3353 [(set_attr "op_type" "RX,RXY")
3354 (set_attr "type" "la")])
3358 [(set (match_operand:SI 0 "register_operand" "")
3359 (match_operand:QI 1 "address_operand" ""))
3360 (clobber (reg:CC 33))])]
3362 && strict_memory_address_p (VOIDmode, operands[1])
3363 && preferred_la_operand_p (operands[1])"
3364 [(set (match_dup 0) (match_dup 1))]
3368 [(set (match_operand:SI 0 "register_operand" "")
3369 (match_operand:SI 1 "register_operand" ""))
3372 (plus:SI (match_dup 0)
3373 (match_operand:SI 2 "nonmemory_operand" "")))
3374 (clobber (reg:CC 33))])]
3376 && !reg_overlap_mentioned_p (operands[0], operands[2])
3377 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2]))
3378 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))"
3379 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3382 (define_insn "*la_31_and"
3383 [(set (match_operand:SI 0 "register_operand" "=d,d")
3384 (and:SI (match_operand:QI 1 "address_operand" "U,W")
3385 (const_int 2147483647)))]
3390 [(set_attr "op_type" "RX,RXY")
3391 (set_attr "type" "la")])
3393 (define_insn_and_split "*la_31_and_cc"
3394 [(set (match_operand:SI 0 "register_operand" "=d")
3395 (and:SI (match_operand:QI 1 "address_operand" "p")
3396 (const_int 2147483647)))
3397 (clobber (reg:CC 33))]
3400 "&& reload_completed"
3402 (and:SI (match_dup 1) (const_int 2147483647)))]
3404 [(set_attr "op_type" "RX")
3405 (set_attr "type" "la")])
3407 (define_insn "force_la_31"
3408 [(set (match_operand:SI 0 "register_operand" "=d,d")
3409 (match_operand:QI 1 "address_operand" "U,W"))
3410 (use (const_int 0))]
3415 [(set_attr "op_type" "RX")
3416 (set_attr "type" "la")])
3418 (define_expand "reload_insi"
3419 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3420 (match_operand:SI 1 "s390_plus_operand" "")
3421 (match_operand:SI 2 "register_operand" "=&a")])]
3424 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3430 ; adddf3 instruction pattern(s).
3433 (define_expand "adddf3"
3435 [(set (match_operand:DF 0 "register_operand" "=f,f")
3436 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3437 (match_operand:DF 2 "general_operand" "f,R")))
3438 (clobber (reg:CC 33))])]
3442 (define_insn "*adddf3"
3443 [(set (match_operand:DF 0 "register_operand" "=f,f")
3444 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3445 (match_operand:DF 2 "general_operand" "f,R")))
3446 (clobber (reg:CC 33))]
3447 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3451 [(set_attr "op_type" "RRE,RXE")
3452 (set_attr "type" "fsimpd,fsimpd")])
3454 (define_insn "*adddf3_ibm"
3455 [(set (match_operand:DF 0 "register_operand" "=f,f")
3456 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3457 (match_operand:DF 2 "general_operand" "f,R")))
3458 (clobber (reg:CC 33))]
3459 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3463 [(set_attr "op_type" "RR,RX")
3464 (set_attr "type" "fsimpd,fsimpd")])
3467 ; addsf3 instruction pattern(s).
3470 (define_expand "addsf3"
3472 [(set (match_operand:SF 0 "register_operand" "=f,f")
3473 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3474 (match_operand:SF 2 "general_operand" "f,R")))
3475 (clobber (reg:CC 33))])]
3479 (define_insn "*addsf3"
3480 [(set (match_operand:SF 0 "register_operand" "=f,f")
3481 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3482 (match_operand:SF 2 "general_operand" "f,R")))
3483 (clobber (reg:CC 33))]
3484 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3488 [(set_attr "op_type" "RRE,RXE")
3489 (set_attr "type" "fsimps,fsimps")])
3491 (define_insn "*addsf3"
3492 [(set (match_operand:SF 0 "register_operand" "=f,f")
3493 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3494 (match_operand:SF 2 "general_operand" "f,R")))
3495 (clobber (reg:CC 33))]
3496 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3500 [(set_attr "op_type" "RR,RX")
3501 (set_attr "type" "fsimps,fsimps")])
3505 ;;- Subtract instructions.
3509 ; subdi3 instruction pattern(s).
3512 (define_insn "*subdi3_sign"
3513 [(set (match_operand:DI 0 "register_operand" "=d,d")
3514 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3515 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3516 (clobber (reg:CC 33))]
3521 [(set_attr "op_type" "RRE,RXY")])
3523 (define_insn "*subdi3_zero_cc"
3525 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3526 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3528 (set (match_operand:DI 0 "register_operand" "=d,d")
3529 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3530 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3534 [(set_attr "op_type" "RRE,RXY")])
3536 (define_insn "*subdi3_zero_cconly"
3538 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3539 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3541 (clobber (match_scratch:DI 0 "=d,d"))]
3542 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3546 [(set_attr "op_type" "RRE,RXY")])
3548 (define_insn "*subdi3_zero"
3549 [(set (match_operand:DI 0 "register_operand" "=d,d")
3550 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3551 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3552 (clobber (reg:CC 33))]
3557 [(set_attr "op_type" "RRE,RXY")])
3559 (define_insn "*subdi3_cc"
3561 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3562 (match_operand:DI 2 "general_operand" "d,m"))
3564 (set (match_operand:DI 0 "register_operand" "=d,d")
3565 (minus:DI (match_dup 1) (match_dup 2)))]
3566 "s390_match_ccmode (insn, CCLmode)"
3570 [(set_attr "op_type" "RRE,RXY")])
3572 (define_insn "*subdi3_cconly"
3574 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3575 (match_operand:DI 2 "general_operand" "d,m"))
3577 (clobber (match_scratch:DI 0 "=d,d"))]
3578 "s390_match_ccmode (insn, CCLmode)"
3582 [(set_attr "op_type" "RRE,RXY")])
3584 (define_insn "*subdi3_64"
3585 [(set (match_operand:DI 0 "register_operand" "=d,d")
3586 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3587 (match_operand:DI 2 "general_operand" "d,m") ) )
3588 (clobber (reg:CC 33))]
3593 [(set_attr "op_type" "RRE,RRE")])
3595 (define_insn_and_split "*subdi3_31"
3596 [(set (match_operand:DI 0 "register_operand" "=&d")
3597 (minus:DI (match_operand:DI 1 "register_operand" "0")
3598 (match_operand:DI 2 "general_operand" "do") ) )
3599 (clobber (reg:CC 33))]
3602 "&& reload_completed"
3604 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3605 (clobber (reg:CC 33))])
3608 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3610 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3612 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3614 (label_ref (match_dup 9))))
3616 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3617 (clobber (reg:CC 33))])
3619 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3620 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3621 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3622 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3623 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3624 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3625 operands[9] = gen_label_rtx ();"
3626 [(set_attr "op_type" "NN")])
3628 (define_expand "subdi3"
3630 [(set (match_operand:DI 0 "register_operand" "")
3631 (minus:DI (match_operand:DI 1 "register_operand" "")
3632 (match_operand:DI 2 "general_operand" "")))
3633 (clobber (reg:CC 33))])]
3638 ; subsi3 instruction pattern(s).
3641 (define_insn "*subsi3_borrow_cc"
3643 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3644 (match_operand:SI 2 "general_operand" "d,R,T"))
3646 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3647 (minus:SI (match_dup 1) (match_dup 2)))]
3648 "s390_match_ccmode(insn, CCL2mode)"
3653 [(set_attr "op_type" "RR,RX,RXY")])
3655 (define_insn "*subsi3_borrow_cconly"
3657 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3658 (match_operand:SI 2 "general_operand" "d,R,T"))
3660 (clobber (match_scratch:SI 0 "=d,d,d"))]
3661 "s390_match_ccmode(insn, CCL2mode)"
3666 [(set_attr "op_type" "RR,RX,RXE")])
3668 (define_insn "*subsi3_cc"
3670 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3671 (match_operand:SI 2 "general_operand" "d,R,T"))
3673 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3674 (minus:SI (match_dup 1) (match_dup 2)))]
3675 "s390_match_ccmode(insn, CCLmode)"
3680 [(set_attr "op_type" "RR,RX,RXY")])
3682 (define_insn "*subsi3_cconly"
3684 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3685 (match_operand:SI 2 "general_operand" "d,R,T"))
3687 (clobber (match_scratch:SI 0 "=d,d,d"))]
3688 "s390_match_ccmode(insn, CCLmode)"
3693 [(set_attr "op_type" "RR,RX,RXY")])
3695 (define_insn "*subsi3_sign"
3696 [(set (match_operand:SI 0 "register_operand" "=d,d")
3697 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3698 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3699 (clobber (reg:CC 33))]
3704 [(set_attr "op_type" "RX,RXY")])
3706 (define_insn "*subsi3_sub"
3707 [(set (match_operand:SI 0 "register_operand" "=d,d")
3708 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3709 (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
3710 (clobber (reg:CC 33))]
3715 [(set_attr "op_type" "RX,RXY")])
3717 (define_insn "subsi3"
3718 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3719 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3720 (match_operand:SI 2 "general_operand" "d,R,T")))
3721 (clobber (reg:CC 33))]
3727 [(set_attr "op_type" "RR,RX,RXY")])
3731 ; subdf3 instruction pattern(s).
3734 (define_expand "subdf3"
3736 [(set (match_operand:DF 0 "register_operand" "=f,f")
3737 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3738 (match_operand:DF 2 "general_operand" "f,R")))
3739 (clobber (reg:CC 33))])]
3743 (define_insn "*subdf3"
3744 [(set (match_operand:DF 0 "register_operand" "=f,f")
3745 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3746 (match_operand:DF 2 "general_operand" "f,R")))
3747 (clobber (reg:CC 33))]
3748 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3752 [(set_attr "op_type" "RRE,RXE")
3753 (set_attr "type" "fsimpd,fsimpd")])
3755 (define_insn "*subdf3_ibm"
3756 [(set (match_operand:DF 0 "register_operand" "=f,f")
3757 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3758 (match_operand:DF 2 "general_operand" "f,R")))
3759 (clobber (reg:CC 33))]
3760 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3764 [(set_attr "op_type" "RR,RX")
3765 (set_attr "type" "fsimpd,fsimpd")])
3768 ; subsf3 instruction pattern(s).
3771 (define_expand "subsf3"
3773 [(set (match_operand:SF 0 "register_operand" "=f,f")
3774 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3775 (match_operand:SF 2 "general_operand" "f,R")))
3776 (clobber (reg:CC 33))])]
3780 (define_insn "*subsf3"
3781 [(set (match_operand:SF 0 "register_operand" "=f,f")
3782 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3783 (match_operand:SF 2 "general_operand" "f,R")))
3784 (clobber (reg:CC 33))]
3785 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3789 [(set_attr "op_type" "RRE,RXE")
3790 (set_attr "type" "fsimps,fsimps")])
3792 (define_insn "*subsf3_ibm"
3793 [(set (match_operand:SF 0 "register_operand" "=f,f")
3794 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3795 (match_operand:SF 2 "general_operand" "f,R")))
3796 (clobber (reg:CC 33))]
3797 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3801 [(set_attr "op_type" "RR,RX")
3802 (set_attr "type" "fsimps,fsimps")])
3806 ;;- Multiply instructions.
3810 ; muldi3 instruction pattern(s).
3813 (define_insn "*muldi3_sign"
3814 [(set (match_operand:DI 0 "register_operand" "=d,d")
3815 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3816 (match_operand:DI 1 "register_operand" "0,0")))]
3821 [(set_attr "op_type" "RRE,RXY")
3822 (set_attr "type" "imul")])
3825 (define_insn "muldi3"
3826 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3827 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3828 (match_operand:DI 2 "general_operand" "d,K,m")))]
3834 [(set_attr "op_type" "RRE,RI,RXY")
3835 (set_attr "type" "imul")])
3838 ; mulsi3 instruction pattern(s).
3841 (define_insn "mulsi3"
3842 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3843 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3844 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
3851 [(set_attr "op_type" "RRE,RI,RX,RXY")
3852 (set_attr "type" "imul")])
3855 ; mulsidi3 instruction pattern(s).
3858 (define_expand "mulsidi3"
3859 [(set (match_operand:DI 0 "register_operand" "")
3860 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3861 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3866 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3867 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3870 gen_rtx_EXPR_LIST (REG_EQUAL,
3871 gen_rtx_MULT (DImode,
3872 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3873 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3878 (define_insn "mulsi_6432"
3879 [(set (match_operand:DI 0 "register_operand" "=d,d")
3880 (mult:DI (sign_extend:DI
3881 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3883 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
3888 [(set_attr "op_type" "RR,RX")
3889 (set_attr "type" "imul")])
3892 ; muldf3 instruction pattern(s).
3895 (define_expand "muldf3"
3897 [(set (match_operand:DF 0 "register_operand" "=f,f")
3898 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3899 (match_operand:DF 2 "general_operand" "f,R")))
3900 (clobber (reg:CC 33))])]
3904 (define_insn "*muldf3"
3905 [(set (match_operand:DF 0 "register_operand" "=f,f")
3906 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3907 (match_operand:DF 2 "general_operand" "f,R")))
3908 (clobber (reg:CC 33))]
3909 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3913 [(set_attr "op_type" "RRE,RXE")
3914 (set_attr "type" "fmuld")])
3916 (define_insn "*muldf3_ibm"
3917 [(set (match_operand:DF 0 "register_operand" "=f,f")
3918 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3919 (match_operand:DF 2 "general_operand" "f,R")))
3920 (clobber (reg:CC 33))]
3921 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3925 [(set_attr "op_type" "RR,RX")
3926 (set_attr "type" "fmuld")])
3929 ; mulsf3 instruction pattern(s).
3932 (define_expand "mulsf3"
3934 [(set (match_operand:SF 0 "register_operand" "=f,f")
3935 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3936 (match_operand:SF 2 "general_operand" "f,R")))
3937 (clobber (reg:CC 33))])]
3941 (define_insn "*mulsf3"
3942 [(set (match_operand:SF 0 "register_operand" "=f,f")
3943 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3944 (match_operand:SF 2 "general_operand" "f,R")))
3945 (clobber (reg:CC 33))]
3946 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3950 [(set_attr "op_type" "RRE,RXE")
3951 (set_attr "type" "fmuls")])
3953 (define_insn "*mulsf3_ibm"
3954 [(set (match_operand:SF 0 "register_operand" "=f,f")
3955 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3956 (match_operand:SF 2 "general_operand" "f,R")))
3957 (clobber (reg:CC 33))]
3958 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3962 [(set_attr "op_type" "RR,RX")
3963 (set_attr "type" "fmuls")])
3967 ;;- Divide and modulo instructions.
3971 ; divmoddi4 instruction pattern(s).
3974 (define_expand "divmoddi4"
3975 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3976 (div:DI (match_operand:DI 1 "general_operand" "")
3977 (match_operand:DI 2 "general_operand" "")))
3978 (set (match_operand:DI 3 "general_operand" "")
3979 (mod:DI (match_dup 1) (match_dup 2)))])
3980 (clobber (match_dup 4))]
3983 rtx insn, div_equal, mod_equal, equal;
3985 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3986 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3987 equal = gen_rtx_IOR (TImode,
3988 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3989 gen_rtx_ASHIFT (TImode,
3990 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3993 operands[4] = gen_reg_rtx(TImode);
3994 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3995 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3996 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3997 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3999 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4001 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4003 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4005 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4007 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4012 (define_insn "divmodtidi3"
4013 [(set (match_operand:TI 0 "register_operand" "=d,d")
4016 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
4017 (match_operand:DI 2 "general_operand" "d,m")))
4020 (mod:DI (truncate:DI (match_dup 1))
4027 [(set_attr "op_type" "RRE,RXY")
4028 (set_attr "type" "idiv")])
4030 (define_insn "divmodtisi3"
4031 [(set (match_operand:TI 0 "register_operand" "=d,d")
4034 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
4035 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4038 (mod:DI (truncate:DI (match_dup 1))
4039 (sign_extend:DI (match_dup 2))))
4045 [(set_attr "op_type" "RRE,RXY")
4046 (set_attr "type" "idiv")])
4049 ; udivmoddi4 instruction pattern(s).
4052 (define_expand "udivmoddi4"
4053 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4054 (udiv:DI (match_operand:DI 1 "general_operand" "")
4055 (match_operand:DI 2 "nonimmediate_operand" "")))
4056 (set (match_operand:DI 3 "general_operand" "")
4057 (umod:DI (match_dup 1) (match_dup 2)))])
4058 (clobber (match_dup 4))]
4061 rtx insn, div_equal, mod_equal, equal;
4063 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4064 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4065 equal = gen_rtx_IOR (TImode,
4066 gen_rtx_ZERO_EXTEND (TImode, div_equal),
4067 gen_rtx_ASHIFT (TImode,
4068 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4071 operands[4] = gen_reg_rtx(TImode);
4072 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4073 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4074 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4075 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4077 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4079 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4081 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4083 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4085 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4090 (define_insn "udivmodtidi3"
4091 [(set (match_operand:TI 0 "register_operand" "=d,d")
4092 (ior:TI (zero_extend:TI
4094 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
4096 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4100 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4106 [(set_attr "op_type" "RRE,RXY")
4107 (set_attr "type" "idiv")])
4110 ; divmodsi4 instruction pattern(s).
4113 (define_expand "divmodsi4"
4114 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4115 (div:SI (match_operand:SI 1 "general_operand" "")
4116 (match_operand:SI 2 "nonimmediate_operand" "")))
4117 (set (match_operand:SI 3 "general_operand" "")
4118 (mod:SI (match_dup 1) (match_dup 2)))])
4119 (clobber (match_dup 4))]
4122 rtx insn, div_equal, mod_equal, equal;
4124 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4125 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4126 equal = gen_rtx_IOR (DImode,
4127 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4128 gen_rtx_ASHIFT (DImode,
4129 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4132 operands[4] = gen_reg_rtx(DImode);
4133 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4134 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4136 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4138 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4140 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4142 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4144 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4149 (define_insn "divmoddisi3"
4150 [(set (match_operand:DI 0 "register_operand" "=d,d")
4151 (ior:DI (zero_extend:DI
4153 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4155 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4159 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4165 [(set_attr "op_type" "RR,RX")
4166 (set_attr "type" "idiv")])
4169 ; udivsi3 and umodsi3 instruction pattern(s).
4173 (define_expand "udivsi3"
4174 [(set (match_operand:SI 0 "register_operand" "=d")
4175 (udiv:SI (match_operand:SI 1 "general_operand" "")
4176 (match_operand:SI 2 "general_operand" "")))
4177 (clobber (match_dup 3))]
4180 rtx insn, udiv_equal, umod_equal, equal;
4182 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4183 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4184 equal = gen_rtx_IOR (DImode,
4185 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4186 gen_rtx_ASHIFT (DImode,
4187 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4190 operands[3] = gen_reg_rtx (DImode);
4192 if (CONSTANT_P (operands[2]))
4194 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4196 rtx label1 = gen_label_rtx ();
4198 operands[1] = make_safe_from (operands[1], operands[0]);
4199 emit_move_insn (operands[0], const0_rtx);
4200 emit_insn (gen_cmpsi (operands[1], operands[2]));
4201 emit_jump_insn (gen_bltu (label1));
4202 emit_move_insn (operands[0], const1_rtx);
4203 emit_label (label1);
4207 operands[2] = force_reg (SImode, operands[2]);
4208 operands[2] = make_safe_from (operands[2], operands[0]);
4210 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4211 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4214 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4216 insn = emit_move_insn (operands[0],
4217 gen_lowpart (SImode, operands[3]));
4219 gen_rtx_EXPR_LIST (REG_EQUAL,
4220 udiv_equal, REG_NOTES (insn));
4225 rtx label1 = gen_label_rtx ();
4226 rtx label2 = gen_label_rtx ();
4227 rtx label3 = gen_label_rtx ();
4229 operands[1] = force_reg (SImode, operands[1]);
4230 operands[1] = make_safe_from (operands[1], operands[0]);
4231 operands[2] = force_reg (SImode, operands[2]);
4232 operands[2] = make_safe_from (operands[2], operands[0]);
4234 emit_move_insn (operands[0], const0_rtx);
4235 emit_insn (gen_cmpsi (operands[2], operands[1]));
4236 emit_jump_insn (gen_bgtu (label3));
4237 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4238 emit_jump_insn (gen_blt (label2));
4239 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4240 emit_jump_insn (gen_beq (label1));
4241 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4242 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4245 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4247 insn = emit_move_insn (operands[0],
4248 gen_lowpart (SImode, operands[3]));
4250 gen_rtx_EXPR_LIST (REG_EQUAL,
4251 udiv_equal, REG_NOTES (insn));
4253 emit_label (label1);
4254 emit_move_insn (operands[0], operands[1]);
4256 emit_label (label2);
4257 emit_move_insn (operands[0], const1_rtx);
4258 emit_label (label3);
4260 emit_move_insn (operands[0], operands[0]);
4264 (define_expand "umodsi3"
4265 [(set (match_operand:SI 0 "register_operand" "=d")
4266 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4267 (match_operand:SI 2 "nonimmediate_operand" "")))
4268 (clobber (match_dup 3))]
4271 rtx insn, udiv_equal, umod_equal, equal;
4273 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4274 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4275 equal = gen_rtx_IOR (DImode,
4276 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4277 gen_rtx_ASHIFT (DImode,
4278 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4281 operands[3] = gen_reg_rtx (DImode);
4283 if (CONSTANT_P (operands[2]))
4285 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4287 rtx label1 = gen_label_rtx ();
4289 operands[1] = make_safe_from (operands[1], operands[0]);
4290 emit_move_insn (operands[0], operands[1]);
4291 emit_insn (gen_cmpsi (operands[0], operands[2]));
4292 emit_jump_insn (gen_bltu (label1));
4293 emit_insn (gen_abssi2 (operands[0], operands[2]));
4294 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4295 emit_label (label1);
4299 operands[2] = force_reg (SImode, operands[2]);
4300 operands[2] = make_safe_from (operands[2], operands[0]);
4302 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4303 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4306 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4308 insn = emit_move_insn (operands[0],
4309 gen_highpart (SImode, operands[3]));
4311 gen_rtx_EXPR_LIST (REG_EQUAL,
4312 umod_equal, REG_NOTES (insn));
4317 rtx label1 = gen_label_rtx ();
4318 rtx label2 = gen_label_rtx ();
4319 rtx label3 = gen_label_rtx ();
4321 operands[1] = force_reg (SImode, operands[1]);
4322 operands[1] = make_safe_from (operands[1], operands[0]);
4323 operands[2] = force_reg (SImode, operands[2]);
4324 operands[2] = make_safe_from (operands[2], operands[0]);
4326 emit_move_insn(operands[0], operands[1]);
4327 emit_insn (gen_cmpsi (operands[2], operands[1]));
4328 emit_jump_insn (gen_bgtu (label3));
4329 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4330 emit_jump_insn (gen_blt (label2));
4331 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4332 emit_jump_insn (gen_beq (label1));
4333 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4334 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4337 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4339 insn = emit_move_insn (operands[0],
4340 gen_highpart (SImode, operands[3]));
4342 gen_rtx_EXPR_LIST (REG_EQUAL,
4343 umod_equal, REG_NOTES (insn));
4345 emit_label (label1);
4346 emit_move_insn (operands[0], const0_rtx);
4348 emit_label (label2);
4349 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4350 emit_label (label3);
4356 ; divdf3 instruction pattern(s).
4359 (define_expand "divdf3"
4361 [(set (match_operand:DF 0 "register_operand" "=f,f")
4362 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4363 (match_operand:DF 2 "general_operand" "f,R")))
4364 (clobber (reg:CC 33))])]
4368 (define_insn "*divdf3"
4369 [(set (match_operand:DF 0 "register_operand" "=f,f")
4370 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4371 (match_operand:DF 2 "general_operand" "f,R")))
4372 (clobber (reg:CC 33))]
4373 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4377 [(set_attr "op_type" "RRE,RXE")
4378 (set_attr "type" "fdivd")])
4380 (define_insn "*divdf3_ibm"
4381 [(set (match_operand:DF 0 "register_operand" "=f,f")
4382 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4383 (match_operand:DF 2 "general_operand" "f,R")))
4384 (clobber (reg:CC 33))]
4385 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4389 [(set_attr "op_type" "RR,RX")
4390 (set_attr "type" "fdivd")])
4393 ; divsf3 instruction pattern(s).
4396 (define_expand "divsf3"
4398 [(set (match_operand:SF 0 "register_operand" "=f,f")
4399 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4400 (match_operand:SF 2 "general_operand" "f,R")))
4401 (clobber (reg:CC 33))])]
4405 (define_insn "*divsf3"
4406 [(set (match_operand:SF 0 "register_operand" "=f,f")
4407 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4408 (match_operand:SF 2 "general_operand" "f,R")))
4409 (clobber (reg:CC 33))]
4410 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4414 [(set_attr "op_type" "RRE,RXE")
4415 (set_attr "type" "fdivs")])
4417 (define_insn "*divsf3"
4418 [(set (match_operand:SF 0 "register_operand" "=f,f")
4419 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4420 (match_operand:SF 2 "general_operand" "f,R")))
4421 (clobber (reg:CC 33))]
4422 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4426 [(set_attr "op_type" "RR,RX")
4427 (set_attr "type" "fdivs")])
4431 ;;- And instructions.
4435 ; anddi3 instruction pattern(s).
4438 (define_insn "*anddi3_cc"
4440 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4441 (match_operand:DI 2 "general_operand" "d,m"))
4443 (set (match_operand:DI 0 "register_operand" "=d,d")
4444 (and:DI (match_dup 1) (match_dup 2)))]
4445 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4449 [(set_attr "op_type" "RRE,RXY")])
4451 (define_insn "*anddi3_cconly"
4453 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4454 (match_operand:DI 2 "general_operand" "d,m"))
4456 (clobber (match_scratch:DI 0 "=d,d"))]
4457 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4461 [(set_attr "op_type" "RRE,RXY")])
4463 (define_insn "*anddi3_ni"
4464 [(set (match_operand:DI 0 "register_operand" "=d")
4465 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4466 (match_operand:DI 2 "immediate_operand" "n")))
4467 (clobber (reg:CC 33))]
4468 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4470 int part = s390_single_hi (operands[2], DImode, -1);
4471 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4475 case 0: return "nihh\\t%0,%x2";
4476 case 1: return "nihl\\t%0,%x2";
4477 case 2: return "nilh\\t%0,%x2";
4478 case 3: return "nill\\t%0,%x2";
4482 [(set_attr "op_type" "RI")])
4484 (define_insn "anddi3"
4485 [(set (match_operand:DI 0 "register_operand" "=d,d")
4486 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4487 (match_operand:DI 2 "general_operand" "d,m")))
4488 (clobber (reg:CC 33))]
4493 [(set_attr "op_type" "RRE,RXY")])
4495 (define_insn "*anddi3_ss"
4496 [(set (match_operand:DI 0 "s_operand" "=Q")
4497 (and:DI (match_dup 0)
4498 (match_operand:DI 1 "s_imm_operand" "Q")))
4499 (clobber (reg:CC 33))]
4501 "nc\\t%O0(8,%R0),%1"
4502 [(set_attr "op_type" "SS")])
4504 (define_insn "*anddi3_ss_inv"
4505 [(set (match_operand:DI 0 "s_operand" "=Q")
4506 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4508 (clobber (reg:CC 33))]
4510 "nc\\t%O0(8,%R0),%1"
4511 [(set_attr "op_type" "SS")])
4514 ; andsi3 instruction pattern(s).
4517 (define_insn "*andsi3_cc"
4519 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4520 (match_operand:SI 2 "general_operand" "d,R,T"))
4522 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4523 (and:SI (match_dup 1) (match_dup 2)))]
4524 "s390_match_ccmode(insn, CCTmode)"
4529 [(set_attr "op_type" "RR,RX,RXY")])
4531 (define_insn "*andsi3_cconly"
4533 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4534 (match_operand:SI 2 "general_operand" "d,R,T"))
4536 (clobber (match_scratch:SI 0 "=d,d,d"))]
4537 "s390_match_ccmode(insn, CCTmode)"
4542 [(set_attr "op_type" "RR,RX,RXY")])
4544 (define_insn "*andsi3_ni"
4545 [(set (match_operand:SI 0 "register_operand" "=d")
4546 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4547 (match_operand:SI 2 "immediate_operand" "n")))
4548 (clobber (reg:CC 33))]
4549 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4551 int part = s390_single_hi (operands[2], SImode, -1);
4552 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4556 case 0: return "nilh\\t%0,%x2";
4557 case 1: return "nill\\t%0,%x2";
4561 [(set_attr "op_type" "RI")])
4563 (define_insn "andsi3"
4564 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4565 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4566 (match_operand:SI 2 "general_operand" "d,R,T")))
4567 (clobber (reg:CC 33))]
4573 [(set_attr "op_type" "RR,RX,RXY")])
4575 (define_insn "*andsi3_ss"
4576 [(set (match_operand:SI 0 "s_operand" "=Q")
4577 (and:SI (match_dup 0)
4578 (match_operand:SI 1 "s_imm_operand" "Q")))
4579 (clobber (reg:CC 33))]
4581 "nc\\t%O0(4,%R0),%1"
4582 [(set_attr "op_type" "SS")])
4584 (define_insn "*andsi3_ss_inv"
4585 [(set (match_operand:SI 0 "s_operand" "=Q")
4586 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4588 (clobber (reg:CC 33))]
4590 "nc\\t%O0(4,%R0),%1"
4591 [(set_attr "op_type" "SS")])
4594 ; andhi3 instruction pattern(s).
4597 (define_insn "*andhi3_ni"
4598 [(set (match_operand:HI 0 "register_operand" "=d,d")
4599 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4600 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4601 (clobber (reg:CC 33))]
4606 [(set_attr "op_type" "RR,RI")])
4608 (define_insn "andhi3"
4609 [(set (match_operand:HI 0 "register_operand" "=d")
4610 (and:HI (match_operand:HI 1 "register_operand" "%0")
4611 (match_operand:HI 2 "nonmemory_operand" "d")))
4612 (clobber (reg:CC 33))]
4615 [(set_attr "op_type" "RR")])
4617 (define_insn "*andhi3_ss"
4618 [(set (match_operand:HI 0 "s_operand" "=Q")
4619 (and:HI (match_dup 0)
4620 (match_operand:HI 1 "s_imm_operand" "Q")))
4621 (clobber (reg:CC 33))]
4623 "nc\\t%O0(2,%R0),%1"
4624 [(set_attr "op_type" "SS")])
4626 (define_insn "*andhi3_ss_inv"
4627 [(set (match_operand:HI 0 "s_operand" "=Q")
4628 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4630 (clobber (reg:CC 33))]
4632 "nc\\t%O0(2,%R0),%1"
4633 [(set_attr "op_type" "SS")])
4636 ; andqi3 instruction pattern(s).
4639 (define_insn "*andqi3_ni"
4640 [(set (match_operand:QI 0 "register_operand" "=d,d")
4641 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4642 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4643 (clobber (reg:CC 33))]
4648 [(set_attr "op_type" "RR,RI")])
4650 (define_insn "andqi3"
4651 [(set (match_operand:QI 0 "register_operand" "=d")
4652 (and:QI (match_operand:QI 1 "register_operand" "%0")
4653 (match_operand:QI 2 "nonmemory_operand" "d")))
4654 (clobber (reg:CC 33))]
4657 [(set_attr "op_type" "RR")])
4659 (define_insn "*andqi3_ss"
4660 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
4661 (and:QI (match_dup 0)
4662 (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
4663 (clobber (reg:CC 33))]
4669 [(set_attr "op_type" "SI,SIY,SS")])
4671 (define_insn "*andqi3_ss_inv"
4672 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
4673 (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
4675 (clobber (reg:CC 33))]
4681 [(set_attr "op_type" "SI,SIY,SS")])
4685 ;;- Bit set (inclusive or) instructions.
4689 ; iordi3 instruction pattern(s).
4692 (define_insn "*iordi3_cc"
4694 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4695 (match_operand:DI 2 "general_operand" "d,m"))
4697 (set (match_operand:DI 0 "register_operand" "=d,d")
4698 (ior:DI (match_dup 1) (match_dup 2)))]
4699 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4703 [(set_attr "op_type" "RRE,RXY")])
4705 (define_insn "*iordi3_cconly"
4707 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4708 (match_operand:DI 2 "general_operand" "d,m"))
4710 (clobber (match_scratch:DI 0 "=d,d"))]
4711 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4715 [(set_attr "op_type" "RRE,RXY")])
4717 (define_insn "*iordi3_oi"
4718 [(set (match_operand:DI 0 "register_operand" "=d")
4719 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4720 (match_operand:DI 2 "immediate_operand" "n")))
4721 (clobber (reg:CC 33))]
4722 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4724 int part = s390_single_hi (operands[2], DImode, 0);
4725 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4729 case 0: return "oihh\\t%0,%x2";
4730 case 1: return "oihl\\t%0,%x2";
4731 case 2: return "oilh\\t%0,%x2";
4732 case 3: return "oill\\t%0,%x2";
4736 [(set_attr "op_type" "RI")])
4738 (define_insn "iordi3"
4739 [(set (match_operand:DI 0 "register_operand" "=d,d")
4740 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4741 (match_operand:DI 2 "general_operand" "d,m")))
4742 (clobber (reg:CC 33))]
4747 [(set_attr "op_type" "RRE,RXY")])
4749 (define_insn "*iordi3_ss"
4750 [(set (match_operand:DI 0 "s_operand" "=Q")
4751 (ior:DI (match_dup 0)
4752 (match_operand:DI 1 "s_imm_operand" "Q")))
4753 (clobber (reg:CC 33))]
4755 "oc\\t%O0(8,%R0),%1"
4756 [(set_attr "op_type" "SS")])
4758 (define_insn "*iordi3_ss_inv"
4759 [(set (match_operand:DI 0 "s_operand" "=Q")
4760 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4762 (clobber (reg:CC 33))]
4764 "oc\\t%O0(8,%R0),%1"
4765 [(set_attr "op_type" "SS")])
4768 ; iorsi3 instruction pattern(s).
4771 (define_insn "*iorsi3_cc"
4773 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4774 (match_operand:SI 2 "general_operand" "d,R,T"))
4776 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4777 (ior:SI (match_dup 1) (match_dup 2)))]
4778 "s390_match_ccmode(insn, CCTmode)"
4783 [(set_attr "op_type" "RR,RX,RXY")])
4785 (define_insn "*iorsi3_cconly"
4787 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4788 (match_operand:SI 2 "general_operand" "d,R,T"))
4790 (clobber (match_scratch:SI 0 "=d,d,d"))]
4791 "s390_match_ccmode(insn, CCTmode)"
4796 [(set_attr "op_type" "RR,RX,RXY")])
4798 (define_insn "*iorsi3_oi"
4799 [(set (match_operand:SI 0 "register_operand" "=d")
4800 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4801 (match_operand:SI 2 "immediate_operand" "n")))
4802 (clobber (reg:CC 33))]
4803 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4805 int part = s390_single_hi (operands[2], SImode, 0);
4806 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4810 case 0: return "oilh\\t%0,%x2";
4811 case 1: return "oill\\t%0,%x2";
4815 [(set_attr "op_type" "RI")])
4817 (define_insn "iorsi3"
4818 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4819 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4820 (match_operand:SI 2 "general_operand" "d,R,T")))
4821 (clobber (reg:CC 33))]
4827 [(set_attr "op_type" "RR,RX,RXY")])
4829 (define_insn "*iorsi3_ss"
4830 [(set (match_operand:SI 0 "s_operand" "=Q")
4831 (ior:SI (match_dup 0)
4832 (match_operand:SI 1 "s_imm_operand" "Q")))
4833 (clobber (reg:CC 33))]
4835 "oc\\t%O0(4,%R0),%1"
4836 [(set_attr "op_type" "SS")])
4838 (define_insn "*iorsi3_ss_inv"
4839 [(set (match_operand:SI 0 "s_operand" "=Q")
4840 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4842 (clobber (reg:CC 33))]
4844 "oc\\t%O0(4,%R0),%1"
4845 [(set_attr "op_type" "SS")])
4848 ; iorhi3 instruction pattern(s).
4851 (define_insn "*iorhi3_oi"
4852 [(set (match_operand:HI 0 "register_operand" "=d,d")
4853 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4854 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4855 (clobber (reg:CC 33))]
4860 [(set_attr "op_type" "RR,RI")])
4862 (define_insn "iorhi3"
4863 [(set (match_operand:HI 0 "register_operand" "=d")
4864 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4865 (match_operand:HI 2 "nonmemory_operand" "d")))
4866 (clobber (reg:CC 33))]
4869 [(set_attr "op_type" "RR")])
4871 (define_insn "*iorhi3_ss"
4872 [(set (match_operand:HI 0 "s_operand" "=Q")
4873 (ior:HI (match_dup 0)
4874 (match_operand:HI 1 "s_imm_operand" "Q")))
4875 (clobber (reg:CC 33))]
4877 "oc\\t%O0(2,%R0),%1"
4878 [(set_attr "op_type" "SS")])
4880 (define_insn "*iorhi3_ss_inv"
4881 [(set (match_operand:HI 0 "s_operand" "=Q")
4882 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4884 (clobber (reg:CC 33))]
4886 "oc\\t%O0(2,%R0),%1"
4887 [(set_attr "op_type" "SS")])
4890 ; iorqi3 instruction pattern(s).
4893 (define_insn "*iorqi3_oi"
4894 [(set (match_operand:QI 0 "register_operand" "=d,d")
4895 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4896 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4897 (clobber (reg:CC 33))]
4902 [(set_attr "op_type" "RR,RI")])
4904 (define_insn "iorqi3"
4905 [(set (match_operand:QI 0 "register_operand" "=d")
4906 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4907 (match_operand:QI 2 "nonmemory_operand" "d")))
4908 (clobber (reg:CC 33))]
4911 [(set_attr "op_type" "RR")])
4913 (define_insn "*iorqi3_ss"
4914 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
4915 (ior:QI (match_dup 0)
4916 (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
4917 (clobber (reg:CC 33))]
4923 [(set_attr "op_type" "SI,SIY,SS")])
4925 (define_insn "*iorqi3_ss_inv"
4926 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
4927 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
4929 (clobber (reg:CC 33))]
4935 [(set_attr "op_type" "SI,SIY,SS")])
4939 ;;- Xor instructions.
4943 ; xordi3 instruction pattern(s).
4946 (define_insn "*xordi3_cc"
4948 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4949 (match_operand:DI 2 "general_operand" "d,m"))
4951 (set (match_operand:DI 0 "register_operand" "=d,d")
4952 (xor:DI (match_dup 1) (match_dup 2)))]
4953 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4957 [(set_attr "op_type" "RRE,RXY")])
4959 (define_insn "*xordi3_cconly"
4961 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4962 (match_operand:DI 2 "general_operand" "d,m"))
4964 (clobber (match_scratch:DI 0 "=d,d"))]
4965 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4969 [(set_attr "op_type" "RRE,RXY")])
4971 (define_insn "xordi3"
4972 [(set (match_operand:DI 0 "register_operand" "=d,d")
4973 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4974 (match_operand:DI 2 "general_operand" "d,m")))
4975 (clobber (reg:CC 33))]
4980 [(set_attr "op_type" "RRE,RXY")])
4982 (define_insn "*xordi3_ss"
4983 [(set (match_operand:DI 0 "s_operand" "=Q")
4984 (xor:DI (match_dup 0)
4985 (match_operand:DI 1 "s_imm_operand" "Q")))
4986 (clobber (reg:CC 33))]
4988 "xc\\t%O0(8,%R0),%1"
4989 [(set_attr "op_type" "SS")])
4991 (define_insn "*xordi3_ss_inv"
4992 [(set (match_operand:DI 0 "s_operand" "=Q")
4993 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4995 (clobber (reg:CC 33))]
4997 "xc\\t%O0(8,%R0),%1"
4998 [(set_attr "op_type" "SS")])
5001 ; xorsi3 instruction pattern(s).
5004 (define_insn "*xorsi3_cc"
5006 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5007 (match_operand:SI 2 "general_operand" "d,R,T"))
5009 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5010 (xor:SI (match_dup 1) (match_dup 2)))]
5011 "s390_match_ccmode(insn, CCTmode)"
5016 [(set_attr "op_type" "RR,RX,RXY")])
5018 (define_insn "*xorsi3_cconly"
5020 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5021 (match_operand:SI 2 "general_operand" "d,R,T"))
5023 (clobber (match_scratch:SI 0 "=d,d,d"))]
5024 "s390_match_ccmode(insn, CCTmode)"
5029 [(set_attr "op_type" "RR,RX,RXY")])
5031 (define_insn "xorsi3"
5032 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5033 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5034 (match_operand:SI 2 "general_operand" "d,R,T")))
5035 (clobber (reg:CC 33))]
5041 [(set_attr "op_type" "RR,RX,RXY")])
5043 (define_insn "*xorsi3_ss"
5044 [(set (match_operand:SI 0 "s_operand" "=Q")
5045 (xor:SI (match_dup 0)
5046 (match_operand:SI 1 "s_imm_operand" "Q")))
5047 (clobber (reg:CC 33))]
5049 "xc\\t%O0(4,%R0),%1"
5050 [(set_attr "op_type" "SS")])
5052 (define_insn "*xorsi3_ss_inv"
5053 [(set (match_operand:SI 0 "s_operand" "=Q")
5054 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
5056 (clobber (reg:CC 33))]
5058 "xc\\t%O0(4,%R0),%1"
5059 [(set_attr "op_type" "SS")])
5062 ; xorhi3 instruction pattern(s).
5065 (define_insn "xorhi3"
5066 [(set (match_operand:HI 0 "register_operand" "=d")
5067 (xor:HI (match_operand:HI 1 "register_operand" "%0")
5068 (match_operand:HI 2 "nonmemory_operand" "d")))
5069 (clobber (reg:CC 33))]
5072 [(set_attr "op_type" "RR")])
5074 (define_insn "*xorhi3_ss"
5075 [(set (match_operand:HI 0 "s_operand" "=Q")
5076 (xor:HI (match_dup 0)
5077 (match_operand:HI 1 "s_imm_operand" "Q")))
5078 (clobber (reg:CC 33))]
5080 "xc\\t%O0(2,%R0),%1"
5081 [(set_attr "op_type" "SS")])
5083 (define_insn "*xorhi3_ss_inv"
5084 [(set (match_operand:HI 0 "s_operand" "=Q")
5085 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
5087 (clobber (reg:CC 33))]
5089 "xc\\t%O0(2,%R0),%1"
5090 [(set_attr "op_type" "SS")])
5093 ; xorqi3 instruction pattern(s).
5096 (define_insn "xorqi3"
5097 [(set (match_operand:QI 0 "register_operand" "=d")
5098 (xor:QI (match_operand:QI 1 "register_operand" "%0")
5099 (match_operand:QI 2 "nonmemory_operand" "d")))
5100 (clobber (reg:CC 33))]
5103 [(set_attr "op_type" "RR")])
5105 (define_insn "*xorqi3_ss"
5106 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
5107 (xor:QI (match_dup 0)
5108 (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
5109 (clobber (reg:CC 33))]
5115 [(set_attr "op_type" "SI,SIY,SS")])
5117 (define_insn "*xorqi3_ss_inv"
5118 [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
5119 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
5121 (clobber (reg:CC 33))]
5127 [(set_attr "op_type" "SI,SIY,SS")])
5131 ;;- Negate instructions.
5135 ; negdi2 instruction pattern(s).
5138 (define_expand "negdi2"
5140 [(set (match_operand:DI 0 "register_operand" "=d")
5141 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5142 (clobber (reg:CC 33))])]
5146 (define_insn "*negdi2_64"
5147 [(set (match_operand:DI 0 "register_operand" "=d")
5148 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5149 (clobber (reg:CC 33))]
5152 [(set_attr "op_type" "RR")])
5154 (define_insn "*negdi2_31"
5155 [(set (match_operand:DI 0 "register_operand" "=d")
5156 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5157 (clobber (reg:CC 33))]
5161 xop[0] = gen_label_rtx ();
5162 output_asm_insn ("lcr\\t%0,%1", operands);
5163 output_asm_insn ("lcr\\t%N0,%N1", operands);
5164 output_asm_insn ("je\\t%l0", xop);
5165 output_asm_insn ("bctr\\t%0,0", operands);
5166 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5167 CODE_LABEL_NUMBER (xop[0]));
5170 [(set_attr "op_type" "NN")
5171 (set_attr "type" "other")
5172 (set_attr "length" "10")])
5175 ; negsi2 instruction pattern(s).
5178 (define_insn "negsi2"
5179 [(set (match_operand:SI 0 "register_operand" "=d")
5180 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5181 (clobber (reg:CC 33))]
5184 [(set_attr "op_type" "RR")])
5187 ; negdf2 instruction pattern(s).
5190 (define_expand "negdf2"
5192 [(set (match_operand:DF 0 "register_operand" "=f")
5193 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5194 (clobber (reg:CC 33))])]
5198 (define_insn "*negdf2"
5199 [(set (match_operand:DF 0 "register_operand" "=f")
5200 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5201 (clobber (reg:CC 33))]
5202 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5204 [(set_attr "op_type" "RRE")
5205 (set_attr "type" "fsimpd")])
5207 (define_insn "*negdf2_ibm"
5208 [(set (match_operand:DF 0 "register_operand" "=f")
5209 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5210 (clobber (reg:CC 33))]
5211 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5213 [(set_attr "op_type" "RR")
5214 (set_attr "type" "fsimpd")])
5217 ; negsf2 instruction pattern(s).
5220 (define_expand "negsf2"
5222 [(set (match_operand:SF 0 "register_operand" "=f")
5223 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5224 (clobber (reg:CC 33))])]
5228 (define_insn "*negsf2"
5229 [(set (match_operand:SF 0 "register_operand" "=f")
5230 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5231 (clobber (reg:CC 33))]
5232 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5234 [(set_attr "op_type" "RRE")
5235 (set_attr "type" "fsimps")])
5237 (define_insn "*negsf2"
5238 [(set (match_operand:SF 0 "register_operand" "=f")
5239 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5240 (clobber (reg:CC 33))]
5241 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5243 [(set_attr "op_type" "RR")
5244 (set_attr "type" "fsimps")])
5248 ;;- Absolute value instructions.
5252 ; absdi2 instruction pattern(s).
5255 (define_insn "absdi2"
5256 [(set (match_operand:DI 0 "register_operand" "=d")
5257 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5258 (clobber (reg:CC 33))]
5261 [(set_attr "op_type" "RRE")])
5264 ; abssi2 instruction pattern(s).
5267 (define_insn "abssi2"
5268 [(set (match_operand:SI 0 "register_operand" "=d")
5269 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5270 (clobber (reg:CC 33))]
5273 [(set_attr "op_type" "RR")])
5276 ; absdf2 instruction pattern(s).
5279 (define_expand "absdf2"
5281 [(set (match_operand:DF 0 "register_operand" "=f")
5282 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5283 (clobber (reg:CC 33))])]
5287 (define_insn "*absdf2"
5288 [(set (match_operand:DF 0 "register_operand" "=f")
5289 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5290 (clobber (reg:CC 33))]
5291 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5293 [(set_attr "op_type" "RRE")
5294 (set_attr "type" "fsimpd")])
5296 (define_insn "*absdf2_ibm"
5297 [(set (match_operand:DF 0 "register_operand" "=f")
5298 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5299 (clobber (reg:CC 33))]
5300 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5302 [(set_attr "op_type" "RR")
5303 (set_attr "type" "fsimpd")])
5306 ; abssf2 instruction pattern(s).
5309 (define_expand "abssf2"
5311 [(set (match_operand:SF 0 "register_operand" "=f")
5312 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5313 (clobber (reg:CC 33))])]
5317 (define_insn "*abssf2"
5318 [(set (match_operand:SF 0 "register_operand" "=f")
5319 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5320 (clobber (reg:CC 33))]
5321 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5323 [(set_attr "op_type" "RRE")
5324 (set_attr "type" "fsimps")])
5326 (define_insn "*abssf2_ibm"
5327 [(set (match_operand:SF 0 "register_operand" "=f")
5328 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5329 (clobber (reg:CC 33))]
5330 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5332 [(set_attr "op_type" "RR")
5333 (set_attr "type" "fsimps")])
5336 ;;- Square root instructions.
5340 ; sqrtdf2 instruction pattern(s).
5343 (define_insn "sqrtdf2"
5344 [(set (match_operand:DF 0 "register_operand" "=f,f")
5345 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
5346 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5350 [(set_attr "op_type" "RRE,RXE")])
5353 ; sqrtsf2 instruction pattern(s).
5356 (define_insn "sqrtsf2"
5357 [(set (match_operand:SF 0 "register_operand" "=f,f")
5358 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
5359 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5363 [(set_attr "op_type" "RRE,RXE")])
5366 ;;- One complement instructions.
5370 ; one_cmpldi2 instruction pattern(s).
5373 (define_expand "one_cmpldi2"
5375 [(set (match_operand:DI 0 "register_operand" "")
5376 (xor:DI (match_operand:DI 1 "register_operand" "")
5378 (clobber (reg:CC 33))])]
5383 ; one_cmplsi2 instruction pattern(s).
5386 (define_expand "one_cmplsi2"
5388 [(set (match_operand:SI 0 "register_operand" "")
5389 (xor:SI (match_operand:SI 1 "register_operand" "")
5391 (clobber (reg:CC 33))])]
5396 ; one_cmplhi2 instruction pattern(s).
5399 (define_expand "one_cmplhi2"
5401 [(set (match_operand:HI 0 "register_operand" "")
5402 (xor:HI (match_operand:HI 1 "register_operand" "")
5404 (clobber (reg:CC 33))])]
5409 ; one_cmplqi2 instruction pattern(s).
5412 (define_expand "one_cmplqi2"
5414 [(set (match_operand:QI 0 "register_operand" "")
5415 (xor:QI (match_operand:QI 1 "register_operand" "")
5417 (clobber (reg:CC 33))])]
5423 ;;- Rotate instructions.
5427 ; rotldi3 instruction pattern(s).
5430 (define_insn "rotldi3"
5431 [(set (match_operand:DI 0 "register_operand" "=d,d")
5432 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5433 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5438 [(set_attr "op_type" "RSE")
5439 (set_attr "atype" "reg")])
5442 ; rotlsi3 instruction pattern(s).
5445 (define_insn "rotlsi3"
5446 [(set (match_operand:SI 0 "register_operand" "=d,d")
5447 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5448 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5453 [(set_attr "op_type" "RSE")
5454 (set_attr "atype" "reg")])
5458 ;;- Arithmetic shift instructions.
5462 ; ashldi3 instruction pattern(s).
5465 (define_expand "ashldi3"
5466 [(set (match_operand:DI 0 "register_operand" "")
5467 (ashift:DI (match_operand:DI 1 "register_operand" "")
5468 (match_operand:SI 2 "nonmemory_operand" "")))]
5472 (define_insn "*ashldi3_31"
5473 [(set (match_operand:DI 0 "register_operand" "=d,d")
5474 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5475 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5480 [(set_attr "op_type" "RS")
5481 (set_attr "atype" "reg")])
5483 (define_insn "*ashldi3_64"
5484 [(set (match_operand:DI 0 "register_operand" "=d,d")
5485 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5486 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5491 [(set_attr "op_type" "RSE")
5492 (set_attr "atype" "reg")])
5495 ; ashrdi3 instruction pattern(s).
5498 (define_expand "ashrdi3"
5500 [(set (match_operand:DI 0 "register_operand" "")
5501 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5502 (match_operand:SI 2 "nonmemory_operand" "")))
5503 (clobber (reg:CC 33))])]
5507 (define_insn "*ashrdi3_cc_31"
5509 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5510 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5512 (set (match_operand:DI 0 "register_operand" "=d,d")
5513 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5514 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5518 [(set_attr "op_type" "RS")
5519 (set_attr "atype" "reg")])
5521 (define_insn "*ashrdi3_cconly_31"
5523 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5524 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5526 (clobber (match_scratch:DI 0 "=d,d"))]
5527 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5531 [(set_attr "op_type" "RS")
5532 (set_attr "atype" "reg")])
5534 (define_insn "*ashrdi3_31"
5535 [(set (match_operand:DI 0 "register_operand" "=d,d")
5536 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5537 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5538 (clobber (reg:CC 33))]
5543 [(set_attr "op_type" "RS")
5544 (set_attr "atype" "reg")])
5546 (define_insn "*ashrdi3_cc_64"
5548 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5549 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5551 (set (match_operand:DI 0 "register_operand" "=d,d")
5552 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5553 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5557 [(set_attr "op_type" "RSE")
5558 (set_attr "atype" "reg")])
5560 (define_insn "*ashrdi3_cconly_64"
5562 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5563 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5565 (clobber (match_scratch:DI 0 "=d,d"))]
5566 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5570 [(set_attr "op_type" "RSE")
5571 (set_attr "atype" "reg")])
5573 (define_insn "*ashrdi3_64"
5574 [(set (match_operand:DI 0 "register_operand" "=d,d")
5575 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5576 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5577 (clobber (reg:CC 33))]
5582 [(set_attr "op_type" "RSE")
5583 (set_attr "atype" "reg")])
5587 ; ashlsi3 instruction pattern(s).
5590 (define_insn "ashlsi3"
5591 [(set (match_operand:SI 0 "register_operand" "=d,d")
5592 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5593 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5598 [(set_attr "op_type" "RS")
5599 (set_attr "atype" "reg")])
5602 ; ashrsi3 instruction pattern(s).
5605 (define_insn "*ashrsi3_cc"
5607 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5608 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5610 (set (match_operand:SI 0 "register_operand" "=d,d")
5611 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5612 "s390_match_ccmode(insn, CCSmode)"
5616 [(set_attr "op_type" "RS")
5617 (set_attr "atype" "reg")])
5620 (define_insn "*ashrsi3_cconly"
5622 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5623 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5625 (clobber (match_scratch:SI 0 "=d,d"))]
5626 "s390_match_ccmode(insn, CCSmode)"
5630 [(set_attr "op_type" "RS")
5631 (set_attr "atype" "reg")])
5633 (define_insn "ashrsi3"
5634 [(set (match_operand:SI 0 "register_operand" "=d,d")
5635 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5636 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5637 (clobber (reg:CC 33))]
5642 [(set_attr "op_type" "RS")
5643 (set_attr "atype" "reg")])
5647 ;;- logical shift instructions.
5651 ; lshrdi3 instruction pattern(s).
5654 (define_expand "lshrdi3"
5655 [(set (match_operand:DI 0 "register_operand" "")
5656 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5657 (match_operand:SI 2 "nonmemory_operand" "")))]
5661 (define_insn "*lshrdi3_31"
5662 [(set (match_operand:DI 0 "register_operand" "=d,d")
5663 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5664 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5669 [(set_attr "op_type" "RS,RS")
5670 (set_attr "atype" "reg")])
5672 (define_insn "*lshrdi3_64"
5673 [(set (match_operand:DI 0 "register_operand" "=d,d")
5674 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5675 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5680 [(set_attr "op_type" "RSE,RSE")
5681 (set_attr "atype" "reg")])
5684 ; lshrsi3 instruction pattern(s).
5687 (define_insn "lshrsi3"
5688 [(set (match_operand:SI 0 "register_operand" "=d,d")
5689 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5690 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5695 [(set_attr "op_type" "RS")
5696 (set_attr "atype" "reg")])
5700 ;; Branch instruction patterns.
5703 (define_expand "beq"
5704 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5706 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5707 (label_ref (match_operand 0 "" ""))
5710 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5712 (define_expand "bne"
5713 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5715 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5716 (label_ref (match_operand 0 "" ""))
5719 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5721 (define_expand "bgt"
5722 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5724 (if_then_else (gt (reg:CCS 33) (const_int 0))
5725 (label_ref (match_operand 0 "" ""))
5728 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5730 (define_expand "bgtu"
5731 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5733 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5734 (label_ref (match_operand 0 "" ""))
5737 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5739 (define_expand "blt"
5740 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5742 (if_then_else (lt (reg:CCS 33) (const_int 0))
5743 (label_ref (match_operand 0 "" ""))
5746 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5748 (define_expand "bltu"
5749 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5751 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5752 (label_ref (match_operand 0 "" ""))
5755 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5757 (define_expand "bge"
5758 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5760 (if_then_else (ge (reg:CCS 33) (const_int 0))
5761 (label_ref (match_operand 0 "" ""))
5764 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5766 (define_expand "bgeu"
5767 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5769 (if_then_else (geu (reg:CCU 33) (const_int 0))
5770 (label_ref (match_operand 0 "" ""))
5773 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5775 (define_expand "ble"
5776 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5778 (if_then_else (le (reg:CCS 33) (const_int 0))
5779 (label_ref (match_operand 0 "" ""))
5782 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5784 (define_expand "bleu"
5785 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5787 (if_then_else (leu (reg:CCU 33) (const_int 0))
5788 (label_ref (match_operand 0 "" ""))
5791 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5793 (define_expand "bunordered"
5794 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5796 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5797 (label_ref (match_operand 0 "" ""))
5800 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5802 (define_expand "bordered"
5803 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5805 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5806 (label_ref (match_operand 0 "" ""))
5809 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5811 (define_expand "buneq"
5812 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5814 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5815 (label_ref (match_operand 0 "" ""))
5818 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5820 (define_expand "bungt"
5821 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5823 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5824 (label_ref (match_operand 0 "" ""))
5827 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5829 (define_expand "bunlt"
5830 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5832 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5833 (label_ref (match_operand 0 "" ""))
5836 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5838 (define_expand "bunge"
5839 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5841 (if_then_else (unge (reg:CCS 33) (const_int 0))
5842 (label_ref (match_operand 0 "" ""))
5845 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5847 (define_expand "bunle"
5848 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5850 (if_then_else (unle (reg:CCS 33) (const_int 0))
5851 (label_ref (match_operand 0 "" ""))
5854 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5856 (define_expand "bltgt"
5857 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5859 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5860 (label_ref (match_operand 0 "" ""))
5863 "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
5867 ;;- Conditional jump instructions.
5870 (define_insn "cjump"
5873 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5874 (label_ref (match_operand 0 "" ""))
5878 if (get_attr_length (insn) == 4)
5879 return "j%C1\\t%l0";
5880 else if (TARGET_64BIT)
5881 return "jg%C1\\t%l0";
5885 [(set_attr "op_type" "RI")
5886 (set_attr "type" "branch")
5887 (set (attr "length")
5888 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5890 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5892 (eq (symbol_ref "flag_pic") (const_int 0))
5893 (const_int 6)] (const_int 8)))])
5895 (define_insn "*cjump_long"
5898 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5899 (match_operand 0 "address_operand" "U")
5903 if (get_attr_op_type (insn) == OP_TYPE_RR)
5904 return "b%C1r\\t%0";
5906 return "b%C1\\t%a0";
5908 [(set (attr "op_type")
5909 (if_then_else (match_operand 0 "register_operand" "")
5910 (const_string "RR") (const_string "RX")))
5911 (set_attr "type" "branch")
5912 (set_attr "atype" "agen")])
5916 ;;- Negated conditional jump instructions.
5919 (define_insn "icjump"
5922 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5924 (label_ref (match_operand 0 "" ""))))]
5927 if (get_attr_length (insn) == 4)
5928 return "j%D1\\t%l0";
5929 else if (TARGET_64BIT)
5930 return "jg%D1\\t%l0";
5934 [(set_attr "op_type" "RI")
5935 (set_attr "type" "branch")
5936 (set (attr "length")
5937 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5939 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5941 (eq (symbol_ref "flag_pic") (const_int 0))
5942 (const_int 6)] (const_int 8)))])
5944 (define_insn "*icjump_long"
5947 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5949 (match_operand 0 "address_operand" "U")))]
5952 if (get_attr_op_type (insn) == OP_TYPE_RR)
5953 return "b%D1r\\t%0";
5955 return "b%D1\\t%a0";
5957 [(set (attr "op_type")
5958 (if_then_else (match_operand 0 "register_operand" "")
5959 (const_string "RR") (const_string "RX")))
5960 (set_attr "type" "branch")
5961 (set_attr "atype" "agen")])
5964 ;;- Trap instructions.
5968 [(trap_if (const_int 1) (const_int 0))]
5971 [(set_attr "op_type" "RX")
5972 (set_attr "type" "branch")])
5974 (define_expand "conditional_trap"
5975 [(set (match_dup 2) (match_dup 3))
5976 (trap_if (match_operator 0 "comparison_operator"
5977 [(match_dup 2) (const_int 0)])
5978 (match_operand:SI 1 "general_operand" ""))]
5981 enum machine_mode ccmode;
5983 if (operands[1] != const0_rtx) FAIL;
5985 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5986 s390_compare_op0, s390_compare_op1);
5987 operands[2] = gen_rtx_REG (ccmode, 33);
5988 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5991 (define_insn "*trap"
5992 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5996 [(set_attr "op_type" "RI")
5997 (set_attr "type" "branch")])
6000 ;;- Loop instructions.
6002 ;; This is all complicated by the fact that since this is a jump insn
6003 ;; we must handle our own output reloads.
6005 (define_expand "doloop_end"
6006 [(use (match_operand 0 "" "")) ; loop pseudo
6007 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6008 (use (match_operand 2 "" "")) ; max iterations
6009 (use (match_operand 3 "" "")) ; loop level
6010 (use (match_operand 4 "" ""))] ; label
6013 if (GET_MODE (operands[0]) == SImode)
6014 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
6015 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6016 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6023 (define_insn "doloop_si"
6026 (ne (match_operand:SI 1 "register_operand" "d,d")
6028 (label_ref (match_operand 0 "" ""))
6030 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6031 (plus:SI (match_dup 1) (const_int -1)))
6032 (clobber (match_scratch:SI 3 "=X,&d"))
6033 (clobber (reg:CC 33))]
6036 if (which_alternative != 0)
6038 else if (get_attr_length (insn) == 4)
6039 return "brct\\t%1,%l0";
6043 [(set_attr "op_type" "RI")
6044 (set_attr "type" "branch")
6045 (set (attr "length")
6046 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6048 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6050 (eq (symbol_ref "flag_pic") (const_int 0))
6051 (const_int 6)] (const_int 8)))])
6053 (define_insn "*doloop_si_long"
6056 (ne (match_operand:SI 1 "register_operand" "d,d")
6058 (match_operand 0 "address_operand" "U,U")
6060 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6061 (plus:SI (match_dup 1) (const_int -1)))
6062 (clobber (match_scratch:SI 3 "=X,&d"))
6063 (clobber (reg:CC 33))]
6066 if (get_attr_op_type (insn) == OP_TYPE_RR)
6067 return "bctr\\t%1,%0";
6069 return "bct\\t%1,%a0";
6071 [(set (attr "op_type")
6072 (if_then_else (match_operand 0 "register_operand" "")
6073 (const_string "RR") (const_string "RX")))
6074 (set_attr "type" "branch")
6075 (set_attr "atype" "agen")])
6079 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
6081 (match_operand 0 "" "")
6083 (set (match_operand:SI 2 "nonimmediate_operand" "")
6084 (plus:SI (match_dup 1) (const_int -1)))
6085 (clobber (match_scratch:SI 3 ""))
6086 (clobber (reg:CC 33))]
6088 && (! REG_P (operands[2])
6089 || ! rtx_equal_p (operands[1], operands[2]))"
6090 [(set (match_dup 3) (match_dup 1))
6091 (parallel [(set (reg:CCAN 33)
6092 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6094 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6095 (set (match_dup 2) (match_dup 3))
6096 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6101 (define_insn "doloop_di"
6104 (ne (match_operand:DI 1 "register_operand" "d,d")
6106 (label_ref (match_operand 0 "" ""))
6108 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6109 (plus:DI (match_dup 1) (const_int -1)))
6110 (clobber (match_scratch:DI 3 "=X,&d"))
6111 (clobber (reg:CC 33))]
6114 if (which_alternative != 0)
6116 else if (get_attr_length (insn) == 4)
6117 return "brctg\\t%1,%l0";
6121 [(set_attr "op_type" "RI")
6122 (set_attr "type" "branch")
6123 (set (attr "length")
6124 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6125 (const_int 4) (const_int 12)))])
6127 (define_insn "*doloop_di_long"
6130 (ne (match_operand:DI 1 "register_operand" "d,d")
6132 (match_operand 0 "address_operand" "U,U")
6134 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6135 (plus:DI (match_dup 1) (const_int -1)))
6136 (clobber (match_scratch:DI 3 "=X,&d"))
6137 (clobber (reg:CC 33))]
6140 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6141 return "bctgr\\t%1,%0";
6143 return "bctg\\t%1,%a0";
6145 [(set (attr "op_type")
6146 (if_then_else (match_operand 0 "register_operand" "")
6147 (const_string "RRE") (const_string "RXE")))
6148 (set_attr "type" "branch")
6149 (set_attr "atype" "agen")])
6153 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6155 (match_operand 0 "" "")
6157 (set (match_operand:DI 2 "nonimmediate_operand" "")
6158 (plus:DI (match_dup 1) (const_int -1)))
6159 (clobber (match_scratch:DI 3 ""))
6160 (clobber (reg:CC 33))]
6162 && (! REG_P (operands[2])
6163 || ! rtx_equal_p (operands[1], operands[2]))"
6164 [(set (match_dup 3) (match_dup 1))
6165 (parallel [(set (reg:CCAN 33)
6166 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6168 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6169 (set (match_dup 2) (match_dup 3))
6170 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6176 ;;- Unconditional jump instructions.
6180 ; jump instruction pattern(s).
6184 [(set (pc) (label_ref (match_operand 0 "" "")))]
6187 if (get_attr_length (insn) == 4)
6189 else if (TARGET_64BIT)
6194 [(set_attr "op_type" "RI")
6195 (set_attr "type" "branch")
6196 (set (attr "length")
6197 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6199 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6201 (eq (symbol_ref "flag_pic") (const_int 0))
6202 (const_int 6)] (const_int 8)))])
6205 ; indirect-jump instruction pattern(s).
6208 (define_insn "indirect_jump"
6209 [(set (pc) (match_operand 0 "address_operand" "U"))]
6212 if (get_attr_op_type (insn) == OP_TYPE_RR)
6217 [(set (attr "op_type")
6218 (if_then_else (match_operand 0 "register_operand" "")
6219 (const_string "RR") (const_string "RX")))
6220 (set_attr "type" "branch")
6221 (set_attr "atype" "agen")])
6224 ; casesi instruction pattern(s).
6227 (define_insn "casesi_jump"
6228 [(set (pc) (match_operand 0 "address_operand" "U"))
6229 (use (label_ref (match_operand 1 "" "")))]
6232 if (get_attr_op_type (insn) == OP_TYPE_RR)
6237 [(set (attr "op_type")
6238 (if_then_else (match_operand 0 "register_operand" "")
6239 (const_string "RR") (const_string "RX")))
6240 (set_attr "type" "branch")
6241 (set_attr "atype" "agen")])
6243 (define_expand "casesi"
6244 [(match_operand:SI 0 "general_operand" "")
6245 (match_operand:SI 1 "general_operand" "")
6246 (match_operand:SI 2 "general_operand" "")
6247 (label_ref (match_operand 3 "" ""))
6248 (label_ref (match_operand 4 "" ""))]
6251 rtx index = gen_reg_rtx (SImode);
6252 rtx base = gen_reg_rtx (Pmode);
6253 rtx target = gen_reg_rtx (Pmode);
6255 emit_move_insn (index, operands[0]);
6256 emit_insn (gen_subsi3 (index, index, operands[1]));
6257 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6260 if (Pmode != SImode)
6261 index = convert_to_mode (Pmode, index, 1);
6262 if (GET_CODE (index) != REG)
6263 index = copy_to_mode_reg (Pmode, index);
6266 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6268 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6270 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6272 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6273 emit_move_insn (target, index);
6276 target = gen_rtx_PLUS (Pmode, base, target);
6277 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6284 ;;- Jump to subroutine.
6289 ; untyped call instruction pattern(s).
6292 ;; Call subroutine returning any type.
6293 (define_expand "untyped_call"
6294 [(parallel [(call (match_operand 0 "" "")
6296 (match_operand 1 "" "")
6297 (match_operand 2 "" "")])]
6302 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6304 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6306 rtx set = XVECEXP (operands[2], 0, i);
6307 emit_move_insn (SET_DEST (set), SET_SRC (set));
6310 /* The optimizer does not know that the call sets the function value
6311 registers we stored in the result block. We avoid problems by
6312 claiming that all hard registers are used and clobbered at this
6314 emit_insn (gen_blockage ());
6319 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6320 ;; all of memory. This blocks insns from being moved across this point.
6322 (define_insn "blockage"
6323 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6326 [(set_attr "type" "none")
6327 (set_attr "length" "0")])
6332 ; call instruction pattern(s).
6335 (define_expand "call"
6336 [(call (match_operand 0 "" "")
6337 (match_operand 1 "" ""))
6338 (use (match_operand 2 "" ""))]
6343 /* Direct function calls need special treatment. */
6344 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6346 rtx sym = XEXP (operands[0], 0);
6348 /* When calling a global routine in PIC mode, we must
6349 replace the symbol itself with the PLT stub. */
6350 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
6352 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
6353 sym = gen_rtx_CONST (Pmode, sym);
6356 /* Unless we can use the bras(l) insn, force the
6357 routine address into a register. */
6358 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6361 sym = legitimize_pic_address (sym, 0);
6363 sym = force_reg (Pmode, sym);
6366 operands[0] = gen_rtx_MEM (QImode, sym);
6370 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6371 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6375 (define_expand "call_exp"
6376 [(parallel [(call (match_operand 0 "" "")
6377 (match_operand 1 "" ""))
6378 (clobber (match_operand 2 "" ""))])]
6382 (define_insn "brasl"
6383 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6384 (match_operand:SI 1 "const_int_operand" "n"))
6385 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6388 [(set_attr "op_type" "RIL")
6389 (set_attr "type" "jsr")])
6392 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6393 (match_operand:SI 1 "const_int_operand" "n"))
6394 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6397 [(set_attr "op_type" "RI")
6398 (set_attr "type" "jsr")])
6400 (define_insn "basr_64"
6401 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6402 (match_operand:SI 1 "const_int_operand" "n"))
6403 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6406 [(set_attr "op_type" "RR")
6407 (set_attr "type" "jsr")
6408 (set_attr "atype" "agen")])
6410 (define_insn "basr_31"
6411 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6412 (match_operand:SI 1 "const_int_operand" "n"))
6413 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6416 [(set_attr "op_type" "RR")
6417 (set_attr "type" "jsr")
6418 (set_attr "atype" "agen")])
6420 (define_insn "bas_64"
6421 [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
6422 (match_operand:SI 1 "const_int_operand" "n"))
6423 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6426 [(set_attr "op_type" "RX")
6427 (set_attr "type" "jsr")])
6429 (define_insn "bas_31"
6430 [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
6431 (match_operand:SI 1 "const_int_operand" "n"))
6432 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6435 [(set_attr "op_type" "RX")
6436 (set_attr "type" "jsr")])
6440 ; call_value instruction pattern(s).
6443 (define_expand "call_value"
6444 [(set (match_operand 0 "" "")
6445 (call (match_operand 1 "" "")
6446 (match_operand 2 "" "")))
6447 (use (match_operand 3 "" ""))]
6452 /* Direct function calls need special treatment. */
6453 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6455 rtx sym = XEXP (operands[1], 0);
6457 /* When calling a global routine in PIC mode, we must
6458 replace the symbol itself with the PLT stub. */
6459 if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
6461 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
6462 sym = gen_rtx_CONST (Pmode, sym);
6465 /* Unless we can use the bras(l) insn, force the
6466 routine address into a register. */
6467 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6470 sym = legitimize_pic_address (sym, 0);
6472 sym = force_reg (Pmode, sym);
6475 operands[1] = gen_rtx_MEM (QImode, sym);
6479 insn = emit_call_insn (
6480 gen_call_value_exp (operands[0], operands[1], operands[2],
6481 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6485 (define_expand "call_value_exp"
6486 [(parallel [(set (match_operand 0 "" "")
6487 (call (match_operand 1 "" "")
6488 (match_operand 2 "" "")))
6489 (clobber (match_operand 3 "" ""))])]
6493 (define_insn "brasl_r"
6494 [(set (match_operand 0 "register_operand" "=df")
6495 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6496 (match_operand:SI 2 "const_int_operand" "n")))
6497 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6500 [(set_attr "op_type" "RIL")
6501 (set_attr "type" "jsr")])
6503 (define_insn "bras_r"
6504 [(set (match_operand 0 "register_operand" "=df")
6505 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6506 (match_operand:SI 2 "const_int_operand" "n")))
6507 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6510 [(set_attr "op_type" "RI")
6511 (set_attr "type" "jsr")])
6513 (define_insn "basr_r_64"
6514 [(set (match_operand 0 "register_operand" "=df")
6515 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6516 (match_operand:SI 2 "const_int_operand" "n")))
6517 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6520 [(set_attr "op_type" "RR")
6521 (set_attr "type" "jsr")
6522 (set_attr "atype" "agen")])
6524 (define_insn "basr_r_31"
6525 [(set (match_operand 0 "register_operand" "=df")
6526 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6527 (match_operand:SI 2 "const_int_operand" "n")))
6528 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6531 [(set_attr "op_type" "RR")
6532 (set_attr "type" "jsr")
6533 (set_attr "atype" "agen")])
6535 (define_insn "bas_r_64"
6536 [(set (match_operand 0 "register_operand" "=df")
6537 (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
6538 (match_operand:SI 2 "const_int_operand" "n")))
6539 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6542 [(set_attr "op_type" "RX")
6543 (set_attr "type" "jsr")])
6545 (define_insn "bas_r_31"
6546 [(set (match_operand 0 "register_operand" "=df")
6547 (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
6548 (match_operand:SI 2 "const_int_operand" "n")))
6549 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6552 [(set_attr "op_type" "RX")
6553 (set_attr "type" "jsr")])
6557 ;;- Thread-local storage support.
6560 (define_insn "get_tp_64"
6561 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
6562 (unspec:DI [(const_int 0)] UNSPEC_TP))]
6565 ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
6566 stam\\t%%a0,%%a1,%0"
6567 [(set_attr "op_type" "NN,RS")
6568 (set_attr "atype" "reg,*")
6569 (set_attr "type" "o3,*")
6570 (set_attr "length" "14,*")])
6572 (define_insn "get_tp_31"
6573 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
6574 (unspec:SI [(const_int 0)] UNSPEC_TP))]
6578 stam\\t%%a0,%%a0,%0"
6579 [(set_attr "op_type" "RRE,RS")])
6581 (define_insn "set_tp_64"
6582 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
6583 (clobber (match_scratch:SI 1 "=d,X"))]
6586 sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
6588 [(set_attr "op_type" "NN,RS")
6589 (set_attr "atype" "reg,*")
6590 (set_attr "type" "o3,*")
6591 (set_attr "length" "14,*")])
6593 (define_insn "set_tp_31"
6594 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
6599 [(set_attr "op_type" "RRE,RS")])
6601 (define_insn "*tls_load_64"
6602 [(set (match_operand:DI 0 "register_operand" "=d")
6603 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6604 (match_operand:DI 2 "" "")]
6608 [(set_attr "op_type" "RXE")])
6610 (define_insn "*tls_load_31"
6611 [(set (match_operand:SI 0 "register_operand" "=d,d")
6612 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6613 (match_operand:SI 2 "" "")]
6619 [(set_attr "op_type" "RX,RXY")])
6621 (define_expand "call_value_tls"
6622 [(set (match_operand 0 "" "")
6623 (call (const_int 0) (const_int 0)))
6624 (use (match_operand 1 "" ""))]
6632 sym = s390_tls_get_offset ();
6633 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
6634 sym = gen_rtx_CONST (Pmode, sym);
6636 /* Unless we can use the bras(l) insn, force the
6637 routine address into a register. */
6638 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6641 sym = legitimize_pic_address (sym, 0);
6643 sym = force_reg (Pmode, sym);
6646 sym = gen_rtx_MEM (QImode, sym);
6649 insn = emit_call_insn (
6650 gen_call_value_tls_exp (operands[0], sym, const0_rtx,
6651 gen_rtx_REG (Pmode, RETURN_REGNUM),
6654 /* The calling convention of __tls_get_offset uses the
6655 GOT register implicitly. */
6656 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6657 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]);
6658 CONST_OR_PURE_CALL_P (insn) = 1;
6663 (define_expand "call_value_tls_exp"
6664 [(parallel [(set (match_operand 0 "" "")
6665 (call (match_operand 1 "" "")
6666 (match_operand 2 "" "")))
6667 (clobber (match_operand 3 "" ""))
6668 (use (match_operand 4 "" ""))])]
6672 (define_insn "brasl_tls"
6673 [(set (match_operand 0 "register_operand" "=df")
6674 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6675 (match_operand:SI 2 "const_int_operand" "n")))
6676 (clobber (match_operand:DI 3 "register_operand" "=r"))
6677 (use (match_operand:DI 4 "" ""))]
6680 [(set_attr "op_type" "RIL")
6681 (set_attr "type" "jsr")])
6683 (define_insn "bras_tls"
6684 [(set (match_operand 0 "register_operand" "=df")
6685 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6686 (match_operand:SI 2 "const_int_operand" "n")))
6687 (clobber (match_operand:SI 3 "register_operand" "=r"))
6688 (use (match_operand:SI 4 "" ""))]
6691 [(set_attr "op_type" "RI")
6692 (set_attr "type" "jsr")])
6694 (define_insn "basr_tls_64"
6695 [(set (match_operand 0 "register_operand" "=df")
6696 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6697 (match_operand:SI 2 "const_int_operand" "n")))
6698 (clobber (match_operand:DI 3 "register_operand" "=r"))
6699 (use (match_operand:DI 4 "" ""))]
6702 [(set_attr "op_type" "RR")
6703 (set_attr "type" "jsr")])
6705 (define_insn "basr_tls_31"
6706 [(set (match_operand 0 "register_operand" "=df")
6707 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6708 (match_operand:SI 2 "const_int_operand" "n")))
6709 (clobber (match_operand:SI 3 "register_operand" "=r"))
6710 (use (match_operand:SI 4 "" ""))]
6713 [(set_attr "op_type" "RR")
6714 (set_attr "type" "jsr")
6715 (set_attr "atype" "agen")])
6717 (define_insn "bas_tls_64"
6718 [(set (match_operand 0 "register_operand" "=df")
6719 (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
6720 (match_operand:SI 2 "const_int_operand" "n")))
6721 (clobber (match_operand:DI 3 "register_operand" "=r"))
6722 (use (match_operand:DI 4 "" ""))]
6725 [(set_attr "op_type" "RX")
6726 (set_attr "type" "jsr")
6727 (set_attr "atype" "agen")])
6729 (define_insn "bas_tls_31"
6730 [(set (match_operand 0 "register_operand" "=df")
6731 (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
6732 (match_operand:SI 2 "const_int_operand" "n")))
6733 (clobber (match_operand:SI 3 "register_operand" "=r"))
6734 (use (match_operand:SI 4 "" ""))]
6737 [(set_attr "op_type" "RX")
6738 (set_attr "type" "jsr")
6739 (set_attr "atype" "agen")])
6742 ;;- Miscellaneous instructions.
6746 ; allocate stack instruction pattern(s).
6749 (define_expand "allocate_stack"
6751 (plus (reg 15) (match_operand 1 "general_operand" "")))
6752 (set (match_operand 0 "general_operand" "")
6756 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6757 rtx chain = gen_rtx (MEM, Pmode, stack);
6758 rtx temp = gen_reg_rtx (Pmode);
6760 emit_move_insn (temp, chain);
6763 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6765 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6767 emit_move_insn (chain, temp);
6769 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6775 ; setjmp/longjmp instruction pattern(s).
6778 (define_expand "builtin_setjmp_setup"
6779 [(match_operand 0 "register_operand" "")]
6782 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6783 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6785 emit_move_insn (base, basereg);
6789 (define_expand "builtin_setjmp_receiver"
6790 [(match_operand 0 "" "")]
6793 s390_load_got (false);
6794 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6798 (define_expand "builtin_longjmp"
6799 [(match_operand 0 "register_operand" "")]
6802 /* The elements of the buffer are, in order: */
6803 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6804 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6805 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6806 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6807 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6808 rtx jmp = gen_reg_rtx (Pmode);
6810 emit_move_insn (jmp, lab);
6811 emit_move_insn (basereg, base);
6812 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6813 emit_move_insn (hard_frame_pointer_rtx, fp);
6815 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6816 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6817 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6818 emit_indirect_jump (jmp);
6823 ;; These patterns say how to save and restore the stack pointer. We need not
6824 ;; save the stack pointer at function level since we are careful to
6825 ;; preserve the backchain. At block level, we have to restore the backchain
6826 ;; when we restore the stack pointer.
6828 ;; For nonlocal gotos, we must save both the stack pointer and its
6829 ;; backchain and restore both. Note that in the nonlocal case, the
6830 ;; save area is a memory location.
6832 (define_expand "save_stack_function"
6833 [(match_operand 0 "general_operand" "")
6834 (match_operand 1 "general_operand" "")]
6838 (define_expand "restore_stack_function"
6839 [(match_operand 0 "general_operand" "")
6840 (match_operand 1 "general_operand" "")]
6844 (define_expand "restore_stack_block"
6845 [(use (match_operand 0 "register_operand" ""))
6846 (set (match_dup 2) (match_dup 3))
6847 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6848 (set (match_dup 3) (match_dup 2))]
6851 operands[2] = gen_reg_rtx (Pmode);
6852 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6855 (define_expand "save_stack_nonlocal"
6856 [(match_operand 0 "memory_operand" "")
6857 (match_operand 1 "register_operand" "")]
6860 rtx temp = gen_reg_rtx (Pmode);
6862 /* Copy the backchain to the first word, sp to the second. */
6863 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6864 emit_move_insn (operand_subword (operands[0], 0, 0,
6865 TARGET_64BIT ? TImode : DImode),
6867 emit_move_insn (operand_subword (operands[0], 1, 0,
6868 TARGET_64BIT ? TImode : DImode),
6873 (define_expand "restore_stack_nonlocal"
6874 [(match_operand 0 "register_operand" "")
6875 (match_operand 1 "memory_operand" "")]
6878 rtx temp = gen_reg_rtx (Pmode);
6880 /* Restore the backchain from the first word, sp from the second. */
6881 emit_move_insn (temp,
6882 operand_subword (operands[1], 0, 0,
6883 TARGET_64BIT ? TImode : DImode));
6884 emit_move_insn (operands[0],
6885 operand_subword (operands[1], 1, 0,
6886 TARGET_64BIT ? TImode : DImode));
6887 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6893 ; nop instruction pattern(s).
6900 [(set_attr "op_type" "RR")])
6904 ; Special literal pool access instruction pattern(s).
6907 (define_insn "consttable_qi"
6908 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")]
6912 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6915 [(set_attr "op_type" "NN")
6916 (set_attr "length" "1")])
6918 (define_insn "consttable_hi"
6919 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")]
6923 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6926 [(set_attr "op_type" "NN")
6927 (set_attr "length" "2")])
6929 (define_insn "consttable_si"
6930 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")]
6934 [(set_attr "op_type" "NN")
6935 (set_attr "length" "4")])
6937 (define_insn "consttable_di"
6938 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")]
6942 [(set_attr "op_type" "NN")
6943 (set_attr "length" "8")])
6945 (define_insn "consttable_ti"
6946 [(unspec_volatile [(match_operand:TI 0 "consttable_operand" "X")]
6950 assemble_integer (operands[0], 16, 16*BITS_PER_UNIT, 1);
6953 [(set_attr "op_type" "NN")
6954 (set_attr "length" "16")])
6956 (define_insn "consttable_sf"
6957 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")]
6963 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6966 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6967 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6970 [(set_attr "op_type" "NN")
6971 (set_attr "length" "4")])
6973 (define_insn "consttable_df"
6974 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")]
6980 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6983 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6984 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6987 [(set_attr "op_type" "NN")
6988 (set_attr "length" "8")])
6990 (define_insn "pool_start_31"
6991 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
6994 [(set_attr "op_type" "NN")
6995 (set_attr "length" "2")])
6997 (define_insn "pool_end_31"
6998 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
7001 [(set_attr "op_type" "NN")
7002 (set_attr "length" "2")])
7004 (define_insn "pool_start_64"
7005 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
7007 ".section\\t.rodata\;.align\\t8"
7008 [(set_attr "op_type" "NN")
7009 (set_attr "length" "0")])
7011 (define_insn "pool_end_64"
7012 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
7015 [(set_attr "op_type" "NN")
7016 (set_attr "length" "0")])
7018 (define_insn "reload_base_31"
7019 [(set (match_operand:SI 0 "register_operand" "=a")
7020 (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7022 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
7023 [(set_attr "op_type" "NN")
7024 (set_attr "type" "la")
7025 (set_attr "length" "6")])
7027 (define_insn "reload_base_64"
7028 [(set (match_operand:DI 0 "register_operand" "=a")
7029 (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7032 [(set_attr "op_type" "RIL")
7033 (set_attr "type" "larl")])
7036 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7039 [(set_attr "op_type" "NN")
7040 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7043 ;; Insns related to generating the function prologue and epilogue.
7047 (define_expand "prologue"
7048 [(use (const_int 0))]
7050 "s390_emit_prologue (); DONE;")
7052 (define_expand "epilogue"
7053 [(use (const_int 1))]
7055 "s390_emit_epilogue (); DONE;")
7058 (define_insn "*return_si"
7060 (use (match_operand:SI 0 "register_operand" "a"))]
7063 [(set_attr "op_type" "RR")
7064 (set_attr "type" "jsr")
7065 (set_attr "atype" "agen")])
7067 (define_insn "*return_di"
7069 (use (match_operand:DI 0 "register_operand" "a"))]
7072 [(set_attr "op_type" "RR")
7073 (set_attr "type" "jsr")
7074 (set_attr "atype" "agen")])
7076 (define_insn "literal_pool_31"
7077 [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
7078 (set (match_operand:SI 0 "register_operand" "=a")
7079 (label_ref (match_operand 1 "" "")))
7080 (use (label_ref (match_operand 2 "" "")))]
7083 if (s390_nr_constants)
7085 output_asm_insn ("bras\\t%0,%2", operands);
7086 s390_output_constant_pool (operands[1], operands[2]);
7090 /* We need the anchor label in any case. */
7091 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7092 CODE_LABEL_NUMBER (operands[1]));
7097 [(set_attr "op_type" "NN")
7098 (set_attr "type" "larl")])
7100 (define_insn "literal_pool_64"
7101 [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
7102 (set (match_operand:DI 0 "register_operand" "=a")
7103 (label_ref (match_operand 1 "" "")))
7104 (use (label_ref (match_operand 2 "" "")))]
7107 if (s390_nr_constants)
7109 output_asm_insn ("larl\\t%0,%1", operands);
7110 s390_output_constant_pool (operands[1], operands[2]);
7115 [(set_attr "op_type" "NN")
7116 (set_attr "type" "larl")])
7118 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7119 ;; pointer. This is used for compatability.
7121 (define_expand "ptr_extend"
7122 [(set (match_operand:DI 0 "register_operand" "=r")
7123 (match_operand:SI 1 "register_operand" "r"))]
7126 emit_insn (gen_anddi3 (operands[0],
7127 gen_lowpart (DImode, operands[1]),
7128 GEN_INT (0x7fffffff)));