1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; Q -- Memory reference without index register and with short displacement.
51 ;; R -- Memory reference with index register and short displacement.
52 ;; S -- Memory reference without index register but with long displacement.
53 ;; T -- Memory reference with index register and long displacement.
54 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
55 ;; Offsettable memory reference of type specified by second letter.
56 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
57 ;; Memory reference of the type specified by second letter that
58 ;; does *not* refer to a literal pool entry.
59 ;; U -- Pointer with short displacement.
60 ;; W -- Pointer with long displacement.
61 ;; Y -- Shift count operand.
63 ;; Special formats used for outputting 390 instructions.
65 ;; %C: print opcode suffix for branch condition.
66 ;; %D: print opcode suffix for inverse branch condition.
67 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
68 ;; %O: print only the displacement of a memory reference.
69 ;; %R: print only the base register of a memory reference.
70 ;; %S: print S-type memory reference (base+displacement).
71 ;; %N: print the second word of a DImode operand.
72 ;; %M: print the second word of a TImode operand.
74 ;; %b: print integer X as if it's an unsigned byte.
75 ;; %x: print integer X as if it's an unsigned word.
76 ;; %h: print integer X as if it's a signed word.
77 ;; %i: print the first nonzero HImode part of X
78 ;; %j: print the first HImode part unequal to 0xffff of X
81 ;; We have a special constraint for pattern matching.
83 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
96 ; GOT/PLT and lt-relative accesses
97 (UNSPEC_LTREL_OFFSET 100)
98 (UNSPEC_LTREL_BASE 101)
106 (UNSPEC_RELOAD_BASE 210)
107 (UNSPEC_MAIN_BASE 211)
112 ; TLS relocation specifiers
117 (UNSPEC_GOTNTPOFF 504)
118 (UNSPEC_INDNTPOFF 505)
121 (UNSPEC_TLSLDM_NTPOFF 511)
122 (UNSPEC_TLS_LOAD 512)
129 ;; UNSPEC_VOLATILE usage
137 (UNSPECV_TPF_PROLOGUE 20)
138 (UNSPECV_TPF_EPILOGUE 21)
142 (UNSPECV_POOL_SECTION 201)
143 (UNSPECV_POOL_ALIGN 202)
144 (UNSPECV_POOL_ENTRY 203)
145 (UNSPECV_MAIN_POOL 300)
161 ; Sibling call register.
163 ; Literal pool base register.
165 ; Return address register.
167 ; Condition code register.
169 ; Thread local storage pointer register.
174 ;; Instruction operand type as used in the Principles of Operation.
175 ;; Used to determine defaults for length and other attribute values.
177 (define_attr "op_type"
178 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
181 ;; Instruction type attribute used for scheduling.
183 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
184 cs,vs,store,sem,idiv,
185 imulhi,imulsi,imuldi,
186 branch,jsr,fsimpdf,fsimpsf,
187 floaddf,floadsf,fstoredf,fstoresf,
188 fmuldf,fmulsf,fdivdf,fdivsf,
189 ftoi,itof,fsqrtdf,fsqrtsf,
191 (cond [(eq_attr "op_type" "NN") (const_string "other")
192 (eq_attr "op_type" "SS") (const_string "cs")]
193 (const_string "integer")))
195 ;; Another attribute used for scheduling purposes:
196 ;; agen: Instruction uses the address generation unit
197 ;; reg: Instruction does not use the agen unit
199 (define_attr "atype" "agen,reg"
200 (cond [(eq_attr "op_type" "E") (const_string "reg")
201 (eq_attr "op_type" "RR") (const_string "reg")
202 (eq_attr "op_type" "RX") (const_string "agen")
203 (eq_attr "op_type" "RI") (const_string "reg")
204 (eq_attr "op_type" "RRE") (const_string "reg")
205 (eq_attr "op_type" "RS") (const_string "agen")
206 (eq_attr "op_type" "RSI") (const_string "agen")
207 (eq_attr "op_type" "S") (const_string "agen")
208 (eq_attr "op_type" "SI") (const_string "agen")
209 (eq_attr "op_type" "SS") (const_string "agen")
210 (eq_attr "op_type" "SSE") (const_string "agen")
211 (eq_attr "op_type" "RXE") (const_string "agen")
212 (eq_attr "op_type" "RSE") (const_string "agen")
213 (eq_attr "op_type" "RIL") (const_string "agen")
214 (eq_attr "op_type" "RXY") (const_string "agen")
215 (eq_attr "op_type" "RSY") (const_string "agen")
216 (eq_attr "op_type" "SIY") (const_string "agen")]
217 (const_string "agen")))
221 (define_attr "length" ""
222 (cond [(eq_attr "op_type" "E") (const_int 2)
223 (eq_attr "op_type" "RR") (const_int 2)
224 (eq_attr "op_type" "RX") (const_int 4)
225 (eq_attr "op_type" "RI") (const_int 4)
226 (eq_attr "op_type" "RRE") (const_int 4)
227 (eq_attr "op_type" "RS") (const_int 4)
228 (eq_attr "op_type" "RSI") (const_int 4)
229 (eq_attr "op_type" "S") (const_int 4)
230 (eq_attr "op_type" "SI") (const_int 4)
231 (eq_attr "op_type" "SS") (const_int 6)
232 (eq_attr "op_type" "SSE") (const_int 6)
233 (eq_attr "op_type" "RXE") (const_int 6)
234 (eq_attr "op_type" "RSE") (const_int 6)
235 (eq_attr "op_type" "RIL") (const_int 6)
236 (eq_attr "op_type" "RXY") (const_int 6)
237 (eq_attr "op_type" "RSY") (const_int 6)
238 (eq_attr "op_type" "SIY") (const_int 6)]
242 ;; Processor type. This attribute must exactly match the processor_type
243 ;; enumeration in s390.h. The current machine description does not
244 ;; distinguish between g5 and g6, but there are differences between the two
245 ;; CPUs could in theory be modeled.
247 (define_attr "cpu" "g5,g6,z900,z990"
248 (const (symbol_ref "s390_tune")))
250 ;; Pipeline description for z900. For lack of anything better,
251 ;; this description is also used for the g5 and g6.
254 ;; Pipeline description for z990.
258 (include "predicates.md")
265 ;; This mode macro allows DF and SF patterns to be generated from the
267 (define_mode_macro FPR [DF SF])
269 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
270 ;; from the same template.
271 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
272 (define_mode_macro DSI [DI SI])
274 ;; This mode macro allows :P to be used for patterns that operate on
275 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
276 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
278 ;; This mode macro allows the QI and HI patterns to be defined from
279 ;; the same template.
280 (define_mode_macro HQI [HI QI])
282 ;; This mode macro allows the integer patterns to be defined from the
284 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
286 ;; This macro allows to unify all 'bCOND' expander patterns.
287 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
288 ordered uneq unlt ungt unle unge ltgt])
290 ;; This macro allows to unify all 'sCOND' patterns.
291 (define_code_macro SCOND [ltu gtu leu geu])
293 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
294 ;; the same template.
295 (define_code_macro SHIFT [ashift lshiftrt])
298 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
299 ;; and "ltebr" in SFmode.
300 (define_mode_attr de [(DF "d") (SF "e")])
302 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
303 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
304 (define_mode_attr dee [(DF "d") (SF "ee")])
306 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
307 ;; 'ashift' and "srdl" in 'lshiftrt'.
308 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
310 ;; In SHIFT templates, this attribute holds the correct standard name for the
311 ;; pattern itself and the corresponding function calls.
312 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
314 ;; This attribute handles differences in the instruction 'type' and will result
315 ;; in "RRE" for DImode and "RR" for SImode.
316 (define_mode_attr E [(DI "E") (SI "")])
318 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
319 ;; and "lcr" in SImode.
320 (define_mode_attr g [(DI "g") (SI "")])
322 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
323 ;; and "cfdbr" in SImode.
324 (define_mode_attr gf [(DI "g") (SI "f")])
326 ;; ICM mask required to load MODE value into the highest subreg
327 ;; of a SImode register.
328 (define_mode_attr icm_hi [(HI "12") (QI "8")])
330 ;; ICM mask required to load MODE value into the lowest subreg
331 ;; of a SImode register.
332 (define_mode_attr icm_lo [(HI "3") (QI "1")])
334 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
335 ;; HImode and "llgc" in QImode.
336 (define_mode_attr hc [(HI "h") (QI "c")])
338 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
340 (define_mode_attr DBL [(DI "TI") (SI "DI")])
342 ;; Maximum unsigned integer that fits in MODE.
343 (define_mode_attr max_uint [(HI "65535") (QI "255")])
347 ;;- Compare instructions.
350 (define_expand "cmp<mode>"
351 [(set (reg:CC CC_REGNUM)
352 (compare:CC (match_operand:GPR 0 "register_operand" "")
353 (match_operand:GPR 1 "general_operand" "")))]
356 s390_compare_op0 = operands[0];
357 s390_compare_op1 = operands[1];
361 (define_expand "cmp<mode>"
362 [(set (reg:CC CC_REGNUM)
363 (compare:CC (match_operand:FPR 0 "register_operand" "")
364 (match_operand:FPR 1 "general_operand" "")))]
367 s390_compare_op0 = operands[0];
368 s390_compare_op1 = operands[1];
373 ; Test-under-Mask instructions
375 (define_insn "*tmqi_mem"
376 [(set (reg CC_REGNUM)
377 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
378 (match_operand:QI 1 "immediate_operand" "n,n"))
379 (match_operand:QI 2 "immediate_operand" "n,n")))]
380 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
384 [(set_attr "op_type" "SI,SIY")])
386 (define_insn "*tmdi_reg"
387 [(set (reg CC_REGNUM)
388 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
389 (match_operand:DI 1 "immediate_operand"
390 "N0HD0,N1HD0,N2HD0,N3HD0"))
391 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
393 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
394 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
400 [(set_attr "op_type" "RI")])
402 (define_insn "*tmsi_reg"
403 [(set (reg CC_REGNUM)
404 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
405 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
406 (match_operand:SI 2 "immediate_operand" "n,n")))]
407 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
408 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tm<mode>_full"
415 [(set (reg CC_REGNUM)
416 (compare (match_operand:HQI 0 "register_operand" "d")
417 (match_operand:HQI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
420 [(set_attr "op_type" "RI")])
423 ; Load-and-Test instructions
425 (define_insn "*tstdi_sign"
426 [(set (reg CC_REGNUM)
427 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
428 (const_int 32)) (const_int 32))
429 (match_operand:DI 1 "const0_operand" "")))
430 (set (match_operand:DI 2 "register_operand" "=d")
431 (sign_extend:DI (match_dup 0)))]
432 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
434 [(set_attr "op_type" "RRE")])
436 (define_insn "*tstdi"
437 [(set (reg CC_REGNUM)
438 (compare (match_operand:DI 0 "register_operand" "d")
439 (match_operand:DI 1 "const0_operand" "")))
440 (set (match_operand:DI 2 "register_operand" "=d")
442 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
444 [(set_attr "op_type" "RRE")])
446 (define_insn "*tstdi_cconly"
447 [(set (reg CC_REGNUM)
448 (compare (match_operand:DI 0 "register_operand" "d")
449 (match_operand:DI 1 "const0_operand" "")))]
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly_31"
455 [(set (reg CC_REGNUM)
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
460 [(set_attr "op_type" "RS")
461 (set_attr "atype" "reg")])
464 (define_insn "*tstsi"
465 [(set (reg CC_REGNUM)
466 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
467 (match_operand:SI 1 "const0_operand" "")))
468 (set (match_operand:SI 2 "register_operand" "=d,d,d")
470 "s390_match_ccmode(insn, CCSmode)"
475 [(set_attr "op_type" "RR,RS,RSY")])
477 (define_insn "*tstsi_cconly"
478 [(set (reg CC_REGNUM)
479 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
480 (match_operand:SI 1 "const0_operand" "")))
481 (clobber (match_scratch:SI 2 "=X,d,d"))]
482 "s390_match_ccmode(insn, CCSmode)"
487 [(set_attr "op_type" "RR,RS,RSY")])
489 (define_insn "*tstsi_cconly2"
490 [(set (reg CC_REGNUM)
491 (compare (match_operand:SI 0 "register_operand" "d")
492 (match_operand:SI 1 "const0_operand" "")))]
493 "s390_match_ccmode(insn, CCSmode)"
495 [(set_attr "op_type" "RR")])
497 (define_insn "*tst<mode>CCT"
498 [(set (reg CC_REGNUM)
499 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
500 (match_operand:HQI 1 "const0_operand" "")))
501 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
503 "s390_match_ccmode(insn, CCTmode)"
506 icmy\t%2,<icm_lo>,%S0
508 [(set_attr "op_type" "RS,RSY,RI")])
510 (define_insn "*tsthiCCT_cconly"
511 [(set (reg CC_REGNUM)
512 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
513 (match_operand:HI 1 "const0_operand" "")))
514 (clobber (match_scratch:HI 2 "=d,d,X"))]
515 "s390_match_ccmode(insn, CCTmode)"
520 [(set_attr "op_type" "RS,RSY,RI")])
522 (define_insn "*tstqiCCT_cconly"
523 [(set (reg CC_REGNUM)
524 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
525 (match_operand:QI 1 "const0_operand" "")))]
526 "s390_match_ccmode(insn, CCTmode)"
531 [(set_attr "op_type" "SI,SIY,RI")])
533 (define_insn "*tst<mode>"
534 [(set (reg CC_REGNUM)
535 (compare (match_operand:HQI 0 "s_operand" "Q,S")
536 (match_operand:HQI 1 "const0_operand" "")))
537 (set (match_operand:HQI 2 "register_operand" "=d,d")
539 "s390_match_ccmode(insn, CCSmode)"
542 icmy\t%2,<icm_lo>,%S0"
543 [(set_attr "op_type" "RS,RSY")])
545 (define_insn "*tst<mode>_cconly"
546 [(set (reg CC_REGNUM)
547 (compare (match_operand:HQI 0 "s_operand" "Q,S")
548 (match_operand:HQI 1 "const0_operand" "")))
549 (clobber (match_scratch:HQI 2 "=d,d"))]
550 "s390_match_ccmode(insn, CCSmode)"
553 icmy\t%2,<icm_lo>,%S0"
554 [(set_attr "op_type" "RS,RSY")])
557 ; Compare (equality) instructions
559 (define_insn "*cmpdi_cct"
560 [(set (reg CC_REGNUM)
561 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
562 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
563 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
569 [(set_attr "op_type" "RRE,RI,RXY,SS")])
571 (define_insn "*cmpsi_cct"
572 [(set (reg CC_REGNUM)
573 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
574 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
575 "s390_match_ccmode (insn, CCTmode)"
582 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
585 ; Compare (signed) instructions
587 (define_insn "*cmpdi_ccs_sign"
588 [(set (reg CC_REGNUM)
589 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
590 (match_operand:DI 0 "register_operand" "d,d")))]
591 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
595 [(set_attr "op_type" "RRE,RXY")])
597 (define_insn "*cmpdi_ccs"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:DI 0 "register_operand" "d,d,d")
600 (match_operand:DI 1 "general_operand" "d,K,m")))]
601 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
606 [(set_attr "op_type" "RRE,RI,RXY")])
608 (define_insn "*cmpsi_ccs_sign"
609 [(set (reg CC_REGNUM)
610 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
611 (match_operand:SI 0 "register_operand" "d,d")))]
612 "s390_match_ccmode(insn, CCSRmode)"
616 [(set_attr "op_type" "RX,RXY")])
618 (define_insn "*cmpsi_ccs"
619 [(set (reg CC_REGNUM)
620 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
621 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
622 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RR,RI,RX,RXY")])
631 ; Compare (unsigned) instructions
633 (define_insn "*cmpdi_ccu_zero"
634 [(set (reg CC_REGNUM)
635 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
636 (match_operand:DI 0 "register_operand" "d,d")))]
637 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
641 [(set_attr "op_type" "RRE,RXY")])
643 (define_insn "*cmpdi_ccu"
644 [(set (reg CC_REGNUM)
645 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
646 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
647 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
653 [(set_attr "op_type" "RRE,RXY,SS,SS")])
655 (define_insn "*cmpsi_ccu"
656 [(set (reg CC_REGNUM)
657 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
658 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
659 "s390_match_ccmode (insn, CCUmode)"
666 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
668 (define_insn "*cmphi_ccu"
669 [(set (reg CC_REGNUM)
670 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
671 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
672 "s390_match_ccmode (insn, CCUmode)
673 && !register_operand (operands[1], HImode)"
679 [(set_attr "op_type" "RS,RSY,SS,SS")])
681 (define_insn "*cmpqi_ccu"
682 [(set (reg CC_REGNUM)
683 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
684 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
685 "s390_match_ccmode (insn, CCUmode)
686 && !register_operand (operands[1], QImode)"
694 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
697 ; Block compare (CLC) instruction patterns.
700 [(set (reg CC_REGNUM)
701 (compare (match_operand:BLK 0 "memory_operand" "Q")
702 (match_operand:BLK 1 "memory_operand" "Q")))
703 (use (match_operand 2 "const_int_operand" "n"))]
704 "s390_match_ccmode (insn, CCUmode)
705 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
706 "clc\t%O0(%2,%R0),%S1"
707 [(set_attr "op_type" "SS")])
710 [(set (reg CC_REGNUM)
711 (compare (match_operand 0 "memory_operand" "")
712 (match_operand 1 "memory_operand" "")))]
714 && s390_match_ccmode (insn, CCUmode)
715 && GET_MODE (operands[0]) == GET_MODE (operands[1])
716 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
718 [(set (match_dup 0) (match_dup 1))
719 (use (match_dup 2))])]
721 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
722 operands[0] = adjust_address (operands[0], BLKmode, 0);
723 operands[1] = adjust_address (operands[1], BLKmode, 0);
725 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
726 operands[0], operands[1]);
727 operands[0] = SET_DEST (PATTERN (curr_insn));
731 ; (DF|SF) instructions
733 (define_insn "*cmp<mode>_ccs_0"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:FPR 0 "register_operand" "f")
736 (match_operand:FPR 1 "const0_operand" "")))]
737 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
739 [(set_attr "op_type" "RRE")
740 (set_attr "type" "fsimp<mode>")])
742 (define_insn "*cmp<mode>_ccs_0_ibm"
743 [(set (reg CC_REGNUM)
744 (compare (match_operand:FPR 0 "register_operand" "f")
745 (match_operand:FPR 1 "const0_operand" "")))]
746 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
748 [(set_attr "op_type" "RR")
749 (set_attr "type" "fsimp<mode>")])
751 (define_insn "*cmp<mode>_ccs"
752 [(set (reg CC_REGNUM)
753 (compare (match_operand:FPR 0 "register_operand" "f,f")
754 (match_operand:FPR 1 "general_operand" "f,R")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "type" "fsimp<mode>")])
762 (define_insn "*cmp<mode>_ccs_ibm"
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:FPR 0 "register_operand" "f,f")
765 (match_operand:FPR 1 "general_operand" "f,R")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "type" "fsimp<mode>")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
784 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
792 [(set_attr "op_type" "RSY,RSY,*,*,SS")
793 (set_attr "type" "lm,stm,*,*,*")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
800 [(set (match_dup 2) (match_dup 4))
801 (set (match_dup 3) (match_dup 5))]
803 operands[2] = operand_subword (operands[0], 0, 0, TImode);
804 operands[3] = operand_subword (operands[0], 1, 0, TImode);
805 operands[4] = operand_subword (operands[1], 0, 0, TImode);
806 operands[5] = operand_subword (operands[1], 1, 0, TImode);
810 [(set (match_operand:TI 0 "nonimmediate_operand" "")
811 (match_operand:TI 1 "general_operand" ""))]
812 "TARGET_64BIT && reload_completed
813 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
814 [(set (match_dup 2) (match_dup 4))
815 (set (match_dup 3) (match_dup 5))]
817 operands[2] = operand_subword (operands[0], 1, 0, TImode);
818 operands[3] = operand_subword (operands[0], 0, 0, TImode);
819 operands[4] = operand_subword (operands[1], 1, 0, TImode);
820 operands[5] = operand_subword (operands[1], 0, 0, TImode);
824 [(set (match_operand:TI 0 "register_operand" "")
825 (match_operand:TI 1 "memory_operand" ""))]
826 "TARGET_64BIT && reload_completed
827 && !s_operand (operands[1], VOIDmode)"
828 [(set (match_dup 0) (match_dup 1))]
830 rtx addr = operand_subword (operands[0], 1, 0, TImode);
831 s390_load_address (addr, XEXP (operands[1], 0));
832 operands[1] = replace_equiv_address (operands[1], addr);
835 (define_expand "reload_outti"
836 [(parallel [(match_operand:TI 0 "" "")
837 (match_operand:TI 1 "register_operand" "d")
838 (match_operand:DI 2 "register_operand" "=&a")])]
841 gcc_assert (MEM_P (operands[0]));
842 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
843 operands[0] = replace_equiv_address (operands[0], operands[2]);
844 emit_move_insn (operands[0], operands[1]);
849 ; movdi instruction pattern(s).
852 (define_expand "movdi"
853 [(set (match_operand:DI 0 "general_operand" "")
854 (match_operand:DI 1 "general_operand" ""))]
857 /* Handle symbolic constants. */
858 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
859 emit_symbolic_move (operands);
862 (define_insn "*movdi_larl"
863 [(set (match_operand:DI 0 "register_operand" "=d")
864 (match_operand:DI 1 "larl_operand" "X"))]
866 && !FP_REG_P (operands[0])"
868 [(set_attr "op_type" "RIL")
869 (set_attr "type" "larl")])
871 (define_insn "*movdi_64"
872 [(set (match_operand:DI 0 "nonimmediate_operand"
873 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
874 (match_operand:DI 1 "general_operand"
875 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
897 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
898 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
899 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
900 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
903 [(set (match_operand:DI 0 "register_operand" "")
904 (match_operand:DI 1 "register_operand" ""))]
905 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
906 [(set (match_dup 2) (match_dup 3))
907 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
908 (set (strict_low_part (match_dup 2)) (match_dup 4))]
909 "operands[2] = gen_lowpart (SImode, operands[0]);
910 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
913 [(set (match_operand:DI 0 "register_operand" "")
914 (match_operand:DI 1 "register_operand" ""))]
915 "TARGET_64BIT && ACCESS_REG_P (operands[0])
916 && dead_or_set_p (insn, operands[1])"
917 [(set (match_dup 3) (match_dup 2))
918 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
919 (set (match_dup 4) (match_dup 2))]
920 "operands[2] = gen_lowpart (SImode, operands[1]);
921 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
924 [(set (match_operand:DI 0 "register_operand" "")
925 (match_operand:DI 1 "register_operand" ""))]
926 "TARGET_64BIT && ACCESS_REG_P (operands[0])
927 && !dead_or_set_p (insn, operands[1])"
928 [(set (match_dup 3) (match_dup 2))
929 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
930 (set (match_dup 4) (match_dup 2))
931 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
932 "operands[2] = gen_lowpart (SImode, operands[1]);
933 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
935 (define_insn "*movdi_31"
936 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
937 (match_operand:DI 1 "general_operand" "Q,S,d,d,dKm,d,*f,R,T,*f,*f,Q"))]
952 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
953 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
956 [(set (match_operand:DI 0 "nonimmediate_operand" "")
957 (match_operand:DI 1 "general_operand" ""))]
958 "!TARGET_64BIT && reload_completed
959 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
960 [(set (match_dup 2) (match_dup 4))
961 (set (match_dup 3) (match_dup 5))]
963 operands[2] = operand_subword (operands[0], 0, 0, DImode);
964 operands[3] = operand_subword (operands[0], 1, 0, DImode);
965 operands[4] = operand_subword (operands[1], 0, 0, DImode);
966 operands[5] = operand_subword (operands[1], 1, 0, DImode);
970 [(set (match_operand:DI 0 "nonimmediate_operand" "")
971 (match_operand:DI 1 "general_operand" ""))]
972 "!TARGET_64BIT && reload_completed
973 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
974 [(set (match_dup 2) (match_dup 4))
975 (set (match_dup 3) (match_dup 5))]
977 operands[2] = operand_subword (operands[0], 1, 0, DImode);
978 operands[3] = operand_subword (operands[0], 0, 0, DImode);
979 operands[4] = operand_subword (operands[1], 1, 0, DImode);
980 operands[5] = operand_subword (operands[1], 0, 0, DImode);
984 [(set (match_operand:DI 0 "register_operand" "")
985 (match_operand:DI 1 "memory_operand" ""))]
986 "!TARGET_64BIT && reload_completed
987 && !FP_REG_P (operands[0])
988 && !s_operand (operands[1], VOIDmode)"
989 [(set (match_dup 0) (match_dup 1))]
991 rtx addr = operand_subword (operands[0], 1, 0, DImode);
992 s390_load_address (addr, XEXP (operands[1], 0));
993 operands[1] = replace_equiv_address (operands[1], addr);
996 (define_expand "reload_outdi"
997 [(parallel [(match_operand:DI 0 "" "")
998 (match_operand:DI 1 "register_operand" "d")
999 (match_operand:SI 2 "register_operand" "=&a")])]
1002 gcc_assert (MEM_P (operands[0]));
1003 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1004 operands[0] = replace_equiv_address (operands[0], operands[2]);
1005 emit_move_insn (operands[0], operands[1]);
1010 [(set (match_operand:DI 0 "register_operand" "")
1011 (mem:DI (match_operand 1 "address_operand" "")))]
1013 && !FP_REG_P (operands[0])
1014 && GET_CODE (operands[1]) == SYMBOL_REF
1015 && CONSTANT_POOL_ADDRESS_P (operands[1])
1016 && get_pool_mode (operands[1]) == DImode
1017 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1018 [(set (match_dup 0) (match_dup 2))]
1019 "operands[2] = get_pool_constant (operands[1]);")
1021 (define_insn "*la_64"
1022 [(set (match_operand:DI 0 "register_operand" "=d,d")
1023 (match_operand:QI 1 "address_operand" "U,W"))]
1028 [(set_attr "op_type" "RX,RXY")
1029 (set_attr "type" "la")])
1033 [(set (match_operand:DI 0 "register_operand" "")
1034 (match_operand:QI 1 "address_operand" ""))
1035 (clobber (reg:CC CC_REGNUM))])]
1037 && preferred_la_operand_p (operands[1], const0_rtx)"
1038 [(set (match_dup 0) (match_dup 1))]
1042 [(set (match_operand:DI 0 "register_operand" "")
1043 (match_operand:DI 1 "register_operand" ""))
1046 (plus:DI (match_dup 0)
1047 (match_operand:DI 2 "nonmemory_operand" "")))
1048 (clobber (reg:CC CC_REGNUM))])]
1050 && !reg_overlap_mentioned_p (operands[0], operands[2])
1051 && preferred_la_operand_p (operands[1], operands[2])"
1052 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1055 (define_expand "reload_indi"
1056 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1057 (match_operand:DI 1 "s390_plus_operand" "")
1058 (match_operand:DI 2 "register_operand" "=&a")])]
1061 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1066 ; movsi instruction pattern(s).
1069 (define_expand "movsi"
1070 [(set (match_operand:SI 0 "general_operand" "")
1071 (match_operand:SI 1 "general_operand" ""))]
1074 /* Handle symbolic constants. */
1075 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1076 emit_symbolic_move (operands);
1079 (define_insn "*movsi_larl"
1080 [(set (match_operand:SI 0 "register_operand" "=d")
1081 (match_operand:SI 1 "larl_operand" "X"))]
1082 "!TARGET_64BIT && TARGET_CPU_ZARCH
1083 && !FP_REG_P (operands[0])"
1085 [(set_attr "op_type" "RIL")
1086 (set_attr "type" "larl")])
1088 (define_insn "*movsi_zarch"
1089 [(set (match_operand:SI 0 "nonimmediate_operand"
1090 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1091 (match_operand:SI 1 "general_operand"
1092 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1114 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1115 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1116 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1117 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1119 (define_insn "*movsi_esa"
1120 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1121 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1136 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1137 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1140 [(set (match_operand:SI 0 "register_operand" "")
1141 (mem:SI (match_operand 1 "address_operand" "")))]
1142 "!FP_REG_P (operands[0])
1143 && GET_CODE (operands[1]) == SYMBOL_REF
1144 && CONSTANT_POOL_ADDRESS_P (operands[1])
1145 && get_pool_mode (operands[1]) == SImode
1146 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1147 [(set (match_dup 0) (match_dup 2))]
1148 "operands[2] = get_pool_constant (operands[1]);")
1150 (define_insn "*la_31"
1151 [(set (match_operand:SI 0 "register_operand" "=d,d")
1152 (match_operand:QI 1 "address_operand" "U,W"))]
1153 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1157 [(set_attr "op_type" "RX,RXY")
1158 (set_attr "type" "la")])
1162 [(set (match_operand:SI 0 "register_operand" "")
1163 (match_operand:QI 1 "address_operand" ""))
1164 (clobber (reg:CC CC_REGNUM))])]
1166 && preferred_la_operand_p (operands[1], const0_rtx)"
1167 [(set (match_dup 0) (match_dup 1))]
1171 [(set (match_operand:SI 0 "register_operand" "")
1172 (match_operand:SI 1 "register_operand" ""))
1175 (plus:SI (match_dup 0)
1176 (match_operand:SI 2 "nonmemory_operand" "")))
1177 (clobber (reg:CC CC_REGNUM))])]
1179 && !reg_overlap_mentioned_p (operands[0], operands[2])
1180 && preferred_la_operand_p (operands[1], operands[2])"
1181 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1184 (define_insn "*la_31_and"
1185 [(set (match_operand:SI 0 "register_operand" "=d,d")
1186 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1187 (const_int 2147483647)))]
1192 [(set_attr "op_type" "RX,RXY")
1193 (set_attr "type" "la")])
1195 (define_insn_and_split "*la_31_and_cc"
1196 [(set (match_operand:SI 0 "register_operand" "=d")
1197 (and:SI (match_operand:QI 1 "address_operand" "p")
1198 (const_int 2147483647)))
1199 (clobber (reg:CC CC_REGNUM))]
1202 "&& reload_completed"
1204 (and:SI (match_dup 1) (const_int 2147483647)))]
1206 [(set_attr "op_type" "RX")
1207 (set_attr "type" "la")])
1209 (define_insn "force_la_31"
1210 [(set (match_operand:SI 0 "register_operand" "=d,d")
1211 (match_operand:QI 1 "address_operand" "U,W"))
1212 (use (const_int 0))]
1217 [(set_attr "op_type" "RX")
1218 (set_attr "type" "la")])
1220 (define_expand "reload_insi"
1221 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1222 (match_operand:SI 1 "s390_plus_operand" "")
1223 (match_operand:SI 2 "register_operand" "=&a")])]
1226 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1231 ; movhi instruction pattern(s).
1234 (define_expand "movhi"
1235 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1236 (match_operand:HI 1 "general_operand" ""))]
1239 /* Make it explicit that loading a register from memory
1240 always sign-extends (at least) to SImode. */
1241 if (optimize && !no_new_pseudos
1242 && register_operand (operands[0], VOIDmode)
1243 && GET_CODE (operands[1]) == MEM)
1245 rtx tmp = gen_reg_rtx (SImode);
1246 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1247 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1248 operands[1] = gen_lowpart (HImode, tmp);
1252 (define_insn "*movhi"
1253 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1254 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1264 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1265 (set_attr "type" "lr,*,*,*,store,store,*")])
1268 [(set (match_operand:HI 0 "register_operand" "")
1269 (mem:HI (match_operand 1 "address_operand" "")))]
1270 "GET_CODE (operands[1]) == SYMBOL_REF
1271 && CONSTANT_POOL_ADDRESS_P (operands[1])
1272 && get_pool_mode (operands[1]) == HImode
1273 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1274 [(set (match_dup 0) (match_dup 2))]
1275 "operands[2] = get_pool_constant (operands[1]);")
1278 ; movqi instruction pattern(s).
1281 (define_expand "movqi"
1282 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1283 (match_operand:QI 1 "general_operand" ""))]
1286 /* On z/Architecture, zero-extending from memory to register
1287 is just as fast as a QImode load. */
1288 if (TARGET_ZARCH && optimize && !no_new_pseudos
1289 && register_operand (operands[0], VOIDmode)
1290 && GET_CODE (operands[1]) == MEM)
1292 rtx tmp = gen_reg_rtx (word_mode);
1293 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1294 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1295 operands[1] = gen_lowpart (QImode, tmp);
1299 (define_insn "*movqi"
1300 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1301 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1313 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1314 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1317 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1318 (mem:QI (match_operand 1 "address_operand" "")))]
1319 "GET_CODE (operands[1]) == SYMBOL_REF
1320 && CONSTANT_POOL_ADDRESS_P (operands[1])
1321 && get_pool_mode (operands[1]) == QImode
1322 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1323 [(set (match_dup 0) (match_dup 2))]
1324 "operands[2] = get_pool_constant (operands[1]);")
1327 ; movstrictqi instruction pattern(s).
1330 (define_insn "*movstrictqi"
1331 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1332 (match_operand:QI 1 "memory_operand" "R,T"))]
1337 [(set_attr "op_type" "RX,RXY")])
1340 ; movstricthi instruction pattern(s).
1343 (define_insn "*movstricthi"
1344 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1345 (match_operand:HI 1 "memory_operand" "Q,S"))
1346 (clobber (reg:CC CC_REGNUM))]
1351 [(set_attr "op_type" "RS,RSY")])
1354 ; movstrictsi instruction pattern(s).
1357 (define_insn "movstrictsi"
1358 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1359 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1366 [(set_attr "op_type" "RR,RX,RXY,RRE")
1367 (set_attr "type" "lr,load,load,*")])
1370 ; movdf instruction pattern(s).
1373 (define_expand "movdf"
1374 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1375 (match_operand:DF 1 "general_operand" ""))]
1379 (define_insn "*movdf_64"
1380 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1381 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1394 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1395 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1397 (define_insn "*movdf_31"
1398 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1399 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1415 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1416 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1417 lm,lm,stm,stm,*,*,*")])
1420 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1421 (match_operand:DF 1 "general_operand" ""))]
1422 "!TARGET_64BIT && reload_completed
1423 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1424 [(set (match_dup 2) (match_dup 4))
1425 (set (match_dup 3) (match_dup 5))]
1427 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1428 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1429 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1430 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1434 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1435 (match_operand:DF 1 "general_operand" ""))]
1436 "!TARGET_64BIT && reload_completed
1437 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1438 [(set (match_dup 2) (match_dup 4))
1439 (set (match_dup 3) (match_dup 5))]
1441 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1442 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1443 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1444 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1448 [(set (match_operand:DF 0 "register_operand" "")
1449 (match_operand:DF 1 "memory_operand" ""))]
1450 "!TARGET_64BIT && reload_completed
1451 && !FP_REG_P (operands[0])
1452 && !s_operand (operands[1], VOIDmode)"
1453 [(set (match_dup 0) (match_dup 1))]
1455 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1456 s390_load_address (addr, XEXP (operands[1], 0));
1457 operands[1] = replace_equiv_address (operands[1], addr);
1460 (define_expand "reload_outdf"
1461 [(parallel [(match_operand:DF 0 "" "")
1462 (match_operand:DF 1 "register_operand" "d")
1463 (match_operand:SI 2 "register_operand" "=&a")])]
1466 gcc_assert (MEM_P (operands[0]));
1467 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1468 operands[0] = replace_equiv_address (operands[0], operands[2]);
1469 emit_move_insn (operands[0], operands[1]);
1474 ; movsf instruction pattern(s).
1477 (define_insn "movsf"
1478 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1479 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1494 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1495 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1496 lr,load,load,store,store,*")])
1499 ; movcc instruction pattern
1502 (define_insn "movcc"
1503 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1504 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1514 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1515 (set_attr "type" "lr,*,*,store,store,load,load")])
1518 ; Block move (MVC) patterns.
1522 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1523 (match_operand:BLK 1 "memory_operand" "Q"))
1524 (use (match_operand 2 "const_int_operand" "n"))]
1525 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1526 "mvc\t%O0(%2,%R0),%S1"
1527 [(set_attr "op_type" "SS")])
1530 [(set (match_operand 0 "memory_operand" "")
1531 (match_operand 1 "memory_operand" ""))]
1533 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1534 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1536 [(set (match_dup 0) (match_dup 1))
1537 (use (match_dup 2))])]
1539 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1540 operands[0] = adjust_address (operands[0], BLKmode, 0);
1541 operands[1] = adjust_address (operands[1], BLKmode, 0);
1546 [(set (match_operand:BLK 0 "memory_operand" "")
1547 (match_operand:BLK 1 "memory_operand" ""))
1548 (use (match_operand 2 "const_int_operand" ""))])
1550 [(set (match_operand:BLK 3 "memory_operand" "")
1551 (match_operand:BLK 4 "memory_operand" ""))
1552 (use (match_operand 5 "const_int_operand" ""))])]
1553 "s390_offset_p (operands[0], operands[3], operands[2])
1554 && s390_offset_p (operands[1], operands[4], operands[2])
1555 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1557 [(set (match_dup 6) (match_dup 7))
1558 (use (match_dup 8))])]
1559 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1560 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1561 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1565 ; load_multiple pattern(s).
1567 ; ??? Due to reload problems with replacing registers inside match_parallel
1568 ; we currently support load_multiple/store_multiple only after reload.
1571 (define_expand "load_multiple"
1572 [(match_par_dup 3 [(set (match_operand 0 "" "")
1573 (match_operand 1 "" ""))
1574 (use (match_operand 2 "" ""))])]
1577 enum machine_mode mode;
1583 /* Support only loading a constant number of fixed-point registers from
1584 memory and only bother with this if more than two */
1585 if (GET_CODE (operands[2]) != CONST_INT
1586 || INTVAL (operands[2]) < 2
1587 || INTVAL (operands[2]) > 16
1588 || GET_CODE (operands[1]) != MEM
1589 || GET_CODE (operands[0]) != REG
1590 || REGNO (operands[0]) >= 16)
1593 count = INTVAL (operands[2]);
1594 regno = REGNO (operands[0]);
1595 mode = GET_MODE (operands[0]);
1596 if (mode != SImode && mode != word_mode)
1599 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1602 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1604 from = XEXP (operands[1], 0);
1607 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1608 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1609 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1611 from = XEXP (XEXP (operands[1], 0), 0);
1612 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1619 from = force_reg (Pmode, XEXP (operands[1], 0));
1623 for (i = 0; i < count; i++)
1624 XVECEXP (operands[3], 0, i)
1625 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1626 change_address (operands[1], mode,
1627 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1630 (define_insn "*load_multiple_di"
1631 [(match_parallel 0 "load_multiple_operation"
1632 [(set (match_operand:DI 1 "register_operand" "=r")
1633 (match_operand:DI 2 "s_operand" "QS"))])]
1634 "reload_completed && word_mode == DImode"
1636 int words = XVECLEN (operands[0], 0);
1637 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1638 return "lmg\t%1,%0,%S2";
1640 [(set_attr "op_type" "RSY")
1641 (set_attr "type" "lm")])
1643 (define_insn "*load_multiple_si"
1644 [(match_parallel 0 "load_multiple_operation"
1645 [(set (match_operand:SI 1 "register_operand" "=r,r")
1646 (match_operand:SI 2 "s_operand" "Q,S"))])]
1649 int words = XVECLEN (operands[0], 0);
1650 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1651 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1653 [(set_attr "op_type" "RS,RSY")
1654 (set_attr "type" "lm")])
1657 ; store multiple pattern(s).
1660 (define_expand "store_multiple"
1661 [(match_par_dup 3 [(set (match_operand 0 "" "")
1662 (match_operand 1 "" ""))
1663 (use (match_operand 2 "" ""))])]
1666 enum machine_mode mode;
1672 /* Support only storing a constant number of fixed-point registers to
1673 memory and only bother with this if more than two. */
1674 if (GET_CODE (operands[2]) != CONST_INT
1675 || INTVAL (operands[2]) < 2
1676 || INTVAL (operands[2]) > 16
1677 || GET_CODE (operands[0]) != MEM
1678 || GET_CODE (operands[1]) != REG
1679 || REGNO (operands[1]) >= 16)
1682 count = INTVAL (operands[2]);
1683 regno = REGNO (operands[1]);
1684 mode = GET_MODE (operands[1]);
1685 if (mode != SImode && mode != word_mode)
1688 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1692 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1694 to = XEXP (operands[0], 0);
1697 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1698 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1699 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1701 to = XEXP (XEXP (operands[0], 0), 0);
1702 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1709 to = force_reg (Pmode, XEXP (operands[0], 0));
1713 for (i = 0; i < count; i++)
1714 XVECEXP (operands[3], 0, i)
1715 = gen_rtx_SET (VOIDmode,
1716 change_address (operands[0], mode,
1717 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1718 gen_rtx_REG (mode, regno + i));
1721 (define_insn "*store_multiple_di"
1722 [(match_parallel 0 "store_multiple_operation"
1723 [(set (match_operand:DI 1 "s_operand" "=QS")
1724 (match_operand:DI 2 "register_operand" "r"))])]
1725 "reload_completed && word_mode == DImode"
1727 int words = XVECLEN (operands[0], 0);
1728 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1729 return "stmg\t%2,%0,%S1";
1731 [(set_attr "op_type" "RSY")
1732 (set_attr "type" "stm")])
1735 (define_insn "*store_multiple_si"
1736 [(match_parallel 0 "store_multiple_operation"
1737 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1738 (match_operand:SI 2 "register_operand" "r,r"))])]
1741 int words = XVECLEN (operands[0], 0);
1742 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1743 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1745 [(set_attr "op_type" "RS,RSY")
1746 (set_attr "type" "stm")])
1749 ;; String instructions.
1752 (define_insn "*execute"
1753 [(match_parallel 0 ""
1754 [(unspec [(match_operand 1 "register_operand" "a")
1755 (match_operand:BLK 2 "memory_operand" "R")
1756 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1757 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1758 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1760 [(set_attr "op_type" "RX")
1761 (set_attr "type" "cs")])
1765 ; strlenM instruction pattern(s).
1768 (define_expand "strlen<mode>"
1769 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1772 (unspec:P [(const_int 0)
1773 (match_operand:BLK 1 "memory_operand" "")
1775 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1776 (clobber (scratch:P))
1777 (clobber (reg:CC CC_REGNUM))])
1779 [(set (match_operand:P 0 "register_operand" "")
1780 (minus:P (match_dup 4) (match_dup 5)))
1781 (clobber (reg:CC CC_REGNUM))])]
1784 operands[4] = gen_reg_rtx (Pmode);
1785 operands[5] = gen_reg_rtx (Pmode);
1786 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1787 operands[1] = replace_equiv_address (operands[1], operands[5]);
1790 (define_insn "*strlen<mode>"
1791 [(set (match_operand:P 0 "register_operand" "=a")
1792 (unspec:P [(match_operand:P 2 "general_operand" "0")
1793 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1795 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1796 (clobber (match_scratch:P 1 "=a"))
1797 (clobber (reg:CC CC_REGNUM))]
1799 "srst\t%0,%1\;jo\t.-4"
1800 [(set_attr "length" "8")
1801 (set_attr "type" "vs")])
1804 ; cmpstrM instruction pattern(s).
1807 (define_expand "cmpstrsi"
1808 [(set (reg:SI 0) (const_int 0))
1810 [(clobber (match_operand 3 "" ""))
1811 (clobber (match_dup 4))
1812 (set (reg:CCU CC_REGNUM)
1813 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1814 (match_operand:BLK 2 "memory_operand" "")))
1817 [(set (match_operand:SI 0 "register_operand" "=d")
1818 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1819 (clobber (reg:CC CC_REGNUM))])]
1822 /* As the result of CMPINT is inverted compared to what we need,
1823 we have to swap the operands. */
1824 rtx op1 = operands[2];
1825 rtx op2 = operands[1];
1826 rtx addr1 = gen_reg_rtx (Pmode);
1827 rtx addr2 = gen_reg_rtx (Pmode);
1829 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1830 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1831 operands[1] = replace_equiv_address_nv (op1, addr1);
1832 operands[2] = replace_equiv_address_nv (op2, addr2);
1833 operands[3] = addr1;
1834 operands[4] = addr2;
1837 (define_insn "*cmpstr<mode>"
1838 [(clobber (match_operand:P 0 "register_operand" "=d"))
1839 (clobber (match_operand:P 1 "register_operand" "=d"))
1840 (set (reg:CCU CC_REGNUM)
1841 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1842 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1845 "clst\t%0,%1\;jo\t.-4"
1846 [(set_attr "length" "8")
1847 (set_attr "type" "vs")])
1850 ; movmemM instruction pattern(s).
1853 (define_expand "movmem<mode>"
1854 [(set (match_operand:BLK 0 "memory_operand" "")
1855 (match_operand:BLK 1 "memory_operand" ""))
1856 (use (match_operand:GPR 2 "general_operand" ""))
1857 (match_operand 3 "" "")]
1859 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1861 ; Move a block that is up to 256 bytes in length.
1862 ; The block length is taken as (operands[2] % 256) + 1.
1864 (define_expand "movmem_short"
1866 [(set (match_operand:BLK 0 "memory_operand" "")
1867 (match_operand:BLK 1 "memory_operand" ""))
1868 (use (match_operand 2 "nonmemory_operand" ""))
1869 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1870 (clobber (match_dup 3))])]
1872 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1874 (define_insn "*movmem_short"
1875 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1876 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1877 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1878 (use (match_operand 3 "immediate_operand" "X,R,X"))
1879 (clobber (match_scratch 4 "=X,X,&a"))]
1880 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1881 && GET_MODE (operands[4]) == Pmode"
1883 [(set_attr "type" "cs")])
1886 [(set (match_operand:BLK 0 "memory_operand" "")
1887 (match_operand:BLK 1 "memory_operand" ""))
1888 (use (match_operand 2 "const_int_operand" ""))
1889 (use (match_operand 3 "immediate_operand" ""))
1890 (clobber (scratch))]
1893 [(set (match_dup 0) (match_dup 1))
1894 (use (match_dup 2))])]
1895 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1898 [(set (match_operand:BLK 0 "memory_operand" "")
1899 (match_operand:BLK 1 "memory_operand" ""))
1900 (use (match_operand 2 "register_operand" ""))
1901 (use (match_operand 3 "memory_operand" ""))
1902 (clobber (scratch))]
1905 [(unspec [(match_dup 2) (match_dup 3)
1906 (const_int 0)] UNSPEC_EXECUTE)
1907 (set (match_dup 0) (match_dup 1))
1908 (use (const_int 1))])]
1912 [(set (match_operand:BLK 0 "memory_operand" "")
1913 (match_operand:BLK 1 "memory_operand" ""))
1914 (use (match_operand 2 "register_operand" ""))
1915 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1916 (clobber (match_operand 3 "register_operand" ""))]
1917 "reload_completed && TARGET_CPU_ZARCH"
1918 [(set (match_dup 3) (label_ref (match_dup 4)))
1920 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1921 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1922 (set (match_dup 0) (match_dup 1))
1923 (use (const_int 1))])]
1924 "operands[4] = gen_label_rtx ();")
1926 ; Move a block of arbitrary length.
1928 (define_expand "movmem_long"
1930 [(clobber (match_dup 2))
1931 (clobber (match_dup 3))
1932 (set (match_operand:BLK 0 "memory_operand" "")
1933 (match_operand:BLK 1 "memory_operand" ""))
1934 (use (match_operand 2 "general_operand" ""))
1936 (clobber (reg:CC CC_REGNUM))])]
1939 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1940 rtx reg0 = gen_reg_rtx (dword_mode);
1941 rtx reg1 = gen_reg_rtx (dword_mode);
1942 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1943 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1944 rtx len0 = gen_lowpart (Pmode, reg0);
1945 rtx len1 = gen_lowpart (Pmode, reg1);
1947 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1948 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1949 emit_move_insn (len0, operands[2]);
1951 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1952 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1953 emit_move_insn (len1, operands[2]);
1955 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1956 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1961 (define_insn "*movmem_long"
1962 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
1963 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
1964 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
1965 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
1968 (clobber (reg:CC CC_REGNUM))]
1970 "mvcle\t%0,%1,0\;jo\t.-4"
1971 [(set_attr "length" "8")
1972 (set_attr "type" "vs")])
1975 ; setmemM instruction pattern(s).
1978 (define_expand "setmem<mode>"
1979 [(set (match_operand:BLK 0 "memory_operand" "")
1980 (match_operand:QI 2 "general_operand" ""))
1981 (use (match_operand:GPR 1 "general_operand" ""))
1982 (match_operand 3 "" "")]
1984 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
1986 ; Clear a block that is up to 256 bytes in length.
1987 ; The block length is taken as (operands[1] % 256) + 1.
1989 (define_expand "clrmem_short"
1991 [(set (match_operand:BLK 0 "memory_operand" "")
1993 (use (match_operand 1 "nonmemory_operand" ""))
1994 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1995 (clobber (match_dup 2))
1996 (clobber (reg:CC CC_REGNUM))])]
1998 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2000 (define_insn "*clrmem_short"
2001 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2003 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2004 (use (match_operand 2 "immediate_operand" "X,R,X"))
2005 (clobber (match_scratch 3 "=X,X,&a"))
2006 (clobber (reg:CC CC_REGNUM))]
2007 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2008 && GET_MODE (operands[3]) == Pmode"
2010 [(set_attr "type" "cs")])
2013 [(set (match_operand:BLK 0 "memory_operand" "")
2015 (use (match_operand 1 "const_int_operand" ""))
2016 (use (match_operand 2 "immediate_operand" ""))
2018 (clobber (reg:CC CC_REGNUM))]
2021 [(set (match_dup 0) (const_int 0))
2023 (clobber (reg:CC CC_REGNUM))])]
2024 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2027 [(set (match_operand:BLK 0 "memory_operand" "")
2029 (use (match_operand 1 "register_operand" ""))
2030 (use (match_operand 2 "memory_operand" ""))
2032 (clobber (reg:CC CC_REGNUM))]
2035 [(unspec [(match_dup 1) (match_dup 2)
2036 (const_int 0)] UNSPEC_EXECUTE)
2037 (set (match_dup 0) (const_int 0))
2039 (clobber (reg:CC CC_REGNUM))])]
2043 [(set (match_operand:BLK 0 "memory_operand" "")
2045 (use (match_operand 1 "register_operand" ""))
2046 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2047 (clobber (match_operand 2 "register_operand" ""))
2048 (clobber (reg:CC CC_REGNUM))]
2049 "reload_completed && TARGET_CPU_ZARCH"
2050 [(set (match_dup 2) (label_ref (match_dup 3)))
2052 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2053 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2054 (set (match_dup 0) (const_int 0))
2056 (clobber (reg:CC CC_REGNUM))])]
2057 "operands[3] = gen_label_rtx ();")
2059 ; Initialize a block of arbitrary length with (operands[2] % 256).
2061 (define_expand "setmem_long"
2063 [(clobber (match_dup 1))
2064 (set (match_operand:BLK 0 "memory_operand" "")
2065 (match_operand 2 "setmem_operand" ""))
2066 (use (match_operand 1 "general_operand" ""))
2068 (clobber (reg:CC CC_REGNUM))])]
2071 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2072 rtx reg0 = gen_reg_rtx (dword_mode);
2073 rtx reg1 = gen_reg_rtx (dword_mode);
2074 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2075 rtx len0 = gen_lowpart (Pmode, reg0);
2077 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2078 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2079 emit_move_insn (len0, operands[1]);
2081 emit_move_insn (reg1, const0_rtx);
2083 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2088 (define_insn "*setmem_long"
2089 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2090 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2091 (match_operand 2 "setmem_operand" "Y"))
2093 (use (match_operand:<DBL> 1 "register_operand" "d"))
2094 (clobber (reg:CC CC_REGNUM))]
2096 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2097 [(set_attr "length" "8")
2098 (set_attr "type" "vs")])
2101 ; cmpmemM instruction pattern(s).
2104 (define_expand "cmpmemsi"
2105 [(set (match_operand:SI 0 "register_operand" "")
2106 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2107 (match_operand:BLK 2 "memory_operand" "") ) )
2108 (use (match_operand:SI 3 "general_operand" ""))
2109 (use (match_operand:SI 4 "" ""))]
2111 "s390_expand_cmpmem (operands[0], operands[1],
2112 operands[2], operands[3]); DONE;")
2114 ; Compare a block that is up to 256 bytes in length.
2115 ; The block length is taken as (operands[2] % 256) + 1.
2117 (define_expand "cmpmem_short"
2119 [(set (reg:CCU CC_REGNUM)
2120 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2121 (match_operand:BLK 1 "memory_operand" "")))
2122 (use (match_operand 2 "nonmemory_operand" ""))
2123 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2124 (clobber (match_dup 3))])]
2126 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2128 (define_insn "*cmpmem_short"
2129 [(set (reg:CCU CC_REGNUM)
2130 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2131 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2132 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2133 (use (match_operand 3 "immediate_operand" "X,R,X"))
2134 (clobber (match_scratch 4 "=X,X,&a"))]
2135 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2136 && GET_MODE (operands[4]) == Pmode"
2138 [(set_attr "type" "cs")])
2141 [(set (reg:CCU CC_REGNUM)
2142 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2143 (match_operand:BLK 1 "memory_operand" "")))
2144 (use (match_operand 2 "const_int_operand" ""))
2145 (use (match_operand 3 "immediate_operand" ""))
2146 (clobber (scratch))]
2149 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2150 (use (match_dup 2))])]
2151 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2154 [(set (reg:CCU CC_REGNUM)
2155 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2156 (match_operand:BLK 1 "memory_operand" "")))
2157 (use (match_operand 2 "register_operand" ""))
2158 (use (match_operand 3 "memory_operand" ""))
2159 (clobber (scratch))]
2162 [(unspec [(match_dup 2) (match_dup 3)
2163 (const_int 0)] UNSPEC_EXECUTE)
2164 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2165 (use (const_int 1))])]
2169 [(set (reg:CCU CC_REGNUM)
2170 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2171 (match_operand:BLK 1 "memory_operand" "")))
2172 (use (match_operand 2 "register_operand" ""))
2173 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2174 (clobber (match_operand 3 "register_operand" ""))]
2175 "reload_completed && TARGET_CPU_ZARCH"
2176 [(set (match_dup 3) (label_ref (match_dup 4)))
2178 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2179 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2180 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2181 (use (const_int 1))])]
2182 "operands[4] = gen_label_rtx ();")
2184 ; Compare a block of arbitrary length.
2186 (define_expand "cmpmem_long"
2188 [(clobber (match_dup 2))
2189 (clobber (match_dup 3))
2190 (set (reg:CCU CC_REGNUM)
2191 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2192 (match_operand:BLK 1 "memory_operand" "")))
2193 (use (match_operand 2 "general_operand" ""))
2194 (use (match_dup 3))])]
2197 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2198 rtx reg0 = gen_reg_rtx (dword_mode);
2199 rtx reg1 = gen_reg_rtx (dword_mode);
2200 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2201 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2202 rtx len0 = gen_lowpart (Pmode, reg0);
2203 rtx len1 = gen_lowpart (Pmode, reg1);
2205 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2206 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2207 emit_move_insn (len0, operands[2]);
2209 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2210 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2211 emit_move_insn (len1, operands[2]);
2213 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2214 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2219 (define_insn "*cmpmem_long"
2220 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2221 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2222 (set (reg:CCU CC_REGNUM)
2223 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2224 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2226 (use (match_dup 3))]
2228 "clcle\t%0,%1,0\;jo\t.-4"
2229 [(set_attr "length" "8")
2230 (set_attr "type" "vs")])
2232 ; Convert CCUmode condition code to integer.
2233 ; Result is zero if EQ, positive if LTU, negative if GTU.
2235 (define_insn_and_split "cmpint"
2236 [(set (match_operand:SI 0 "register_operand" "=d")
2237 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2239 (clobber (reg:CC CC_REGNUM))]
2243 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2245 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2246 (clobber (reg:CC CC_REGNUM))])])
2248 (define_insn_and_split "*cmpint_cc"
2249 [(set (reg CC_REGNUM)
2250 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2253 (set (match_operand:SI 0 "register_operand" "=d")
2254 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2255 "s390_match_ccmode (insn, CCSmode)"
2257 "&& reload_completed"
2258 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2260 [(set (match_dup 2) (match_dup 3))
2261 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2263 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2264 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2265 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2268 (define_insn_and_split "*cmpint_sign"
2269 [(set (match_operand:DI 0 "register_operand" "=d")
2270 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2272 (clobber (reg:CC CC_REGNUM))]
2275 "&& reload_completed"
2276 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2278 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2279 (clobber (reg:CC CC_REGNUM))])])
2281 (define_insn_and_split "*cmpint_sign_cc"
2282 [(set (reg CC_REGNUM)
2283 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2284 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2286 (const_int 32)) (const_int 32))
2288 (set (match_operand:DI 0 "register_operand" "=d")
2289 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2290 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2292 "&& reload_completed"
2293 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2295 [(set (match_dup 2) (match_dup 3))
2296 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2298 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2299 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2300 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2305 ;;- Conversion instructions.
2309 (define_insn "*sethigh<mode>si"
2310 [(set (match_operand:SI 0 "register_operand" "=d,d")
2311 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2312 (clobber (reg:CC CC_REGNUM))]
2315 icm\t%0,<icm_hi>,%S1
2316 icmy\t%0,<icm_hi>,%S1"
2317 [(set_attr "op_type" "RS,RSY")])
2319 (define_insn "*sethighqidi_64"
2320 [(set (match_operand:DI 0 "register_operand" "=d")
2321 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2322 (clobber (reg:CC CC_REGNUM))]
2325 [(set_attr "op_type" "RSY")])
2327 (define_insn "*sethighqidi_31"
2328 [(set (match_operand:DI 0 "register_operand" "=d,d")
2329 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2330 (clobber (reg:CC CC_REGNUM))]
2335 [(set_attr "op_type" "RS,RSY")])
2337 (define_insn_and_split "*extractqi"
2338 [(set (match_operand:SI 0 "register_operand" "=d")
2339 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2340 (match_operand 2 "const_int_operand" "n")
2342 (clobber (reg:CC CC_REGNUM))]
2344 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2346 "&& reload_completed"
2348 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2349 (clobber (reg:CC CC_REGNUM))])
2350 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2352 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2353 operands[1] = change_address (operands[1], QImode, 0);
2356 (define_insn_and_split "*extracthi"
2357 [(set (match_operand:SI 0 "register_operand" "=d")
2358 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2359 (match_operand 2 "const_int_operand" "n")
2361 (clobber (reg:CC CC_REGNUM))]
2363 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2365 "&& reload_completed"
2367 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2368 (clobber (reg:CC CC_REGNUM))])
2369 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2371 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2372 operands[1] = change_address (operands[1], HImode, 0);
2376 ; extendsidi2 instruction pattern(s).
2379 (define_expand "extendsidi2"
2380 [(set (match_operand:DI 0 "register_operand" "")
2381 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2387 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2388 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2389 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2390 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2396 (define_insn "*extendsidi2"
2397 [(set (match_operand:DI 0 "register_operand" "=d,d")
2398 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2403 [(set_attr "op_type" "RRE,RXY")])
2406 ; extend(hi|qi)di2 instruction pattern(s).
2409 (define_expand "extend<mode>di2"
2410 [(set (match_operand:DI 0 "register_operand" "")
2411 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2417 rtx tmp = gen_reg_rtx (SImode);
2418 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2419 emit_insn (gen_extendsidi2 (operands[0], tmp));
2424 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2425 GET_MODE_BITSIZE (<MODE>mode));
2426 operands[1] = gen_lowpart (DImode, operands[1]);
2427 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2428 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2434 (define_insn "*extendhidi2"
2435 [(set (match_operand:DI 0 "register_operand" "=d")
2436 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2439 [(set_attr "op_type" "RXY")])
2441 (define_insn "*extendqidi2"
2442 [(set (match_operand:DI 0 "register_operand" "=d")
2443 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2444 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2446 [(set_attr "op_type" "RXY")])
2448 (define_insn_and_split "*extendqidi2_short_displ"
2449 [(set (match_operand:DI 0 "register_operand" "=d")
2450 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2451 (clobber (reg:CC CC_REGNUM))]
2452 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2454 "&& reload_completed"
2456 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2457 (clobber (reg:CC CC_REGNUM))])
2459 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2460 (clobber (reg:CC CC_REGNUM))])]
2464 ; extend(hi|qi)si2 instruction pattern(s).
2467 (define_expand "extend<mode>si2"
2468 [(set (match_operand:SI 0 "register_operand" "")
2469 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2473 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2474 GET_MODE_BITSIZE(<MODE>mode));
2475 operands[1] = gen_lowpart (SImode, operands[1]);
2476 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2477 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2482 (define_insn "*extendhisi2"
2483 [(set (match_operand:SI 0 "register_operand" "=d,d")
2484 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2489 [(set_attr "op_type" "RX,RXY")])
2491 (define_insn "*extendqisi2"
2492 [(set (match_operand:SI 0 "register_operand" "=d")
2493 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2494 "TARGET_LONG_DISPLACEMENT"
2496 [(set_attr "op_type" "RXY")])
2498 (define_insn_and_split "*extendqisi2_short_displ"
2499 [(set (match_operand:SI 0 "register_operand" "=d")
2500 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2501 (clobber (reg:CC CC_REGNUM))]
2502 "!TARGET_LONG_DISPLACEMENT"
2504 "&& reload_completed"
2506 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2507 (clobber (reg:CC CC_REGNUM))])
2509 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2510 (clobber (reg:CC CC_REGNUM))])]
2514 ; extendqihi2 instruction pattern(s).
2519 ; zero_extendsidi2 instruction pattern(s).
2522 (define_expand "zero_extendsidi2"
2523 [(set (match_operand:DI 0 "register_operand" "")
2524 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2530 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2531 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2532 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2538 (define_insn "*zero_extendsidi2"
2539 [(set (match_operand:DI 0 "register_operand" "=d,d")
2540 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2545 [(set_attr "op_type" "RRE,RXY")])
2548 ; zero_extend(hi|qi)di2 instruction pattern(s).
2551 (define_expand "zero_extend<mode>di2"
2552 [(set (match_operand:DI 0 "register_operand" "")
2553 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2559 rtx tmp = gen_reg_rtx (SImode);
2560 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2561 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2566 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2567 GET_MODE_BITSIZE(<MODE>mode));
2568 operands[1] = gen_lowpart (DImode, operands[1]);
2569 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2570 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2576 (define_insn "*zero_extend<mode>di2"
2577 [(set (match_operand:DI 0 "register_operand" "=d")
2578 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2581 [(set_attr "op_type" "RXY")])
2584 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2587 (define_insn "*llgt_sidi"
2588 [(set (match_operand:DI 0 "register_operand" "=d")
2589 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2590 (const_int 2147483647)))]
2593 [(set_attr "op_type" "RXE")])
2595 (define_insn_and_split "*llgt_sidi_split"
2596 [(set (match_operand:DI 0 "register_operand" "=d")
2597 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2598 (const_int 2147483647)))
2599 (clobber (reg:CC CC_REGNUM))]
2602 "&& reload_completed"
2604 (and:DI (subreg:DI (match_dup 1) 0)
2605 (const_int 2147483647)))]
2608 (define_insn "*llgt_sisi"
2609 [(set (match_operand:SI 0 "register_operand" "=d,d")
2610 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2611 (const_int 2147483647)))]
2616 [(set_attr "op_type" "RRE,RXE")])
2618 (define_insn "*llgt_didi"
2619 [(set (match_operand:DI 0 "register_operand" "=d,d")
2620 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2621 (const_int 2147483647)))]
2626 [(set_attr "op_type" "RRE,RXE")])
2629 [(set (match_operand:GPR 0 "register_operand" "")
2630 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2631 (const_int 2147483647)))
2632 (clobber (reg:CC CC_REGNUM))]
2633 "TARGET_ZARCH && reload_completed"
2635 (and:GPR (match_dup 1)
2636 (const_int 2147483647)))]
2640 ; zero_extend(hi|qi)si2 instruction pattern(s).
2643 (define_expand "zero_extend<mode>si2"
2644 [(set (match_operand:SI 0 "register_operand" "")
2645 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2649 operands[1] = gen_lowpart (SImode, operands[1]);
2650 emit_insn (gen_andsi3 (operands[0], operands[1],
2651 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2656 (define_insn "*zero_extend<mode>si2_64"
2657 [(set (match_operand:SI 0 "register_operand" "=d")
2658 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2661 [(set_attr "op_type" "RXY")])
2663 (define_insn_and_split "*zero_extendhisi2_31"
2664 [(set (match_operand:SI 0 "register_operand" "=&d")
2665 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2666 (clobber (reg:CC CC_REGNUM))]
2669 "&& reload_completed"
2670 [(set (match_dup 0) (const_int 0))
2672 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2673 (clobber (reg:CC CC_REGNUM))])]
2674 "operands[2] = gen_lowpart (HImode, operands[0]);")
2676 (define_insn_and_split "*zero_extendqisi2_31"
2677 [(set (match_operand:SI 0 "register_operand" "=&d")
2678 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2681 "&& reload_completed"
2682 [(set (match_dup 0) (const_int 0))
2683 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2684 "operands[2] = gen_lowpart (QImode, operands[0]);")
2687 ; zero_extendqihi2 instruction pattern(s).
2690 (define_expand "zero_extendqihi2"
2691 [(set (match_operand:HI 0 "register_operand" "")
2692 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2696 operands[1] = gen_lowpart (HImode, operands[1]);
2697 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2702 (define_insn "*zero_extendqihi2_64"
2703 [(set (match_operand:HI 0 "register_operand" "=d")
2704 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2707 [(set_attr "op_type" "RXY")])
2709 (define_insn_and_split "*zero_extendqihi2_31"
2710 [(set (match_operand:HI 0 "register_operand" "=&d")
2711 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2714 "&& reload_completed"
2715 [(set (match_dup 0) (const_int 0))
2716 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2717 "operands[2] = gen_lowpart (QImode, operands[0]);")
2721 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2724 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2725 [(set (match_operand:GPR 0 "register_operand" "")
2726 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2727 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2729 rtx label1 = gen_label_rtx ();
2730 rtx label2 = gen_label_rtx ();
2731 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2732 REAL_VALUE_TYPE cmp, sub;
2734 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2735 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2736 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2738 emit_insn (gen_cmp<FPR:mode> (operands[1],
2739 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2740 emit_jump_insn (gen_blt (label1));
2741 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2742 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2743 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2747 emit_label (label1);
2748 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2749 operands[1], GEN_INT(5)));
2750 emit_label (label2);
2754 (define_expand "fix_trunc<FPR:mode>di2"
2755 [(set (match_operand:DI 0 "register_operand" "")
2756 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2757 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2759 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2760 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2765 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2766 [(set (match_operand:GPR 0 "register_operand" "=d")
2767 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2768 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2769 (clobber (reg:CC CC_REGNUM))]
2770 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2771 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2772 [(set_attr "op_type" "RRE")
2773 (set_attr "type" "ftoi")])
2776 ; fix_truncdfsi2 instruction pattern(s).
2779 (define_expand "fix_truncdfsi2"
2780 [(set (match_operand:SI 0 "register_operand" "")
2781 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2784 if (TARGET_IBM_FLOAT)
2786 /* This is the algorithm from POP chapter A.5.7.2. */
2788 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2789 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2790 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2792 operands[1] = force_reg (DFmode, operands[1]);
2793 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2794 two31r, two32, temp));
2798 operands[1] = force_reg (DFmode, operands[1]);
2799 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2805 (define_insn "fix_truncdfsi2_ibm"
2806 [(set (match_operand:SI 0 "register_operand" "=d")
2807 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2808 (use (match_operand:DI 2 "immediate_operand" "m"))
2809 (use (match_operand:DI 3 "immediate_operand" "m"))
2810 (use (match_operand:BLK 4 "memory_operand" "m"))
2811 (clobber (reg:CC CC_REGNUM))]
2812 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2814 output_asm_insn ("sd\t%1,%2", operands);
2815 output_asm_insn ("aw\t%1,%3", operands);
2816 output_asm_insn ("std\t%1,%4", operands);
2817 output_asm_insn ("xi\t%N4,128", operands);
2820 [(set_attr "length" "20")])
2823 ; fix_truncsfsi2 instruction pattern(s).
2826 (define_expand "fix_truncsfsi2"
2827 [(set (match_operand:SI 0 "register_operand" "")
2828 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2831 if (TARGET_IBM_FLOAT)
2833 /* Convert to DFmode and then use the POP algorithm. */
2834 rtx temp = gen_reg_rtx (DFmode);
2835 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2836 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2840 operands[1] = force_reg (SFmode, operands[1]);
2841 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2848 ; floatdi(df|sf)2 instruction pattern(s).
2851 (define_insn "floatdi<mode>2"
2852 [(set (match_operand:FPR 0 "register_operand" "=f")
2853 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2854 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2856 [(set_attr "op_type" "RRE")
2857 (set_attr "type" "itof" )])
2860 ; floatsidf2 instruction pattern(s).
2863 (define_expand "floatsidf2"
2864 [(set (match_operand:DF 0 "register_operand" "")
2865 (float:DF (match_operand:SI 1 "register_operand" "")))]
2868 if (TARGET_IBM_FLOAT)
2870 /* This is the algorithm from POP chapter A.5.7.1. */
2872 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2873 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2875 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2880 (define_insn "floatsidf2_ieee"
2881 [(set (match_operand:DF 0 "register_operand" "=f")
2882 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2883 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2885 [(set_attr "op_type" "RRE")
2886 (set_attr "type" "itof" )])
2888 (define_insn "floatsidf2_ibm"
2889 [(set (match_operand:DF 0 "register_operand" "=f")
2890 (float:DF (match_operand:SI 1 "register_operand" "d")))
2891 (use (match_operand:DI 2 "immediate_operand" "m"))
2892 (use (match_operand:BLK 3 "memory_operand" "m"))
2893 (clobber (reg:CC CC_REGNUM))]
2894 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2896 output_asm_insn ("st\t%1,%N3", operands);
2897 output_asm_insn ("xi\t%N3,128", operands);
2898 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2899 output_asm_insn ("ld\t%0,%3", operands);
2902 [(set_attr "length" "20")])
2905 ; floatsisf2 instruction pattern(s).
2908 (define_expand "floatsisf2"
2909 [(set (match_operand:SF 0 "register_operand" "")
2910 (float:SF (match_operand:SI 1 "register_operand" "")))]
2913 if (TARGET_IBM_FLOAT)
2915 /* Use the POP algorithm to convert to DFmode and then truncate. */
2916 rtx temp = gen_reg_rtx (DFmode);
2917 emit_insn (gen_floatsidf2 (temp, operands[1]));
2918 emit_insn (gen_truncdfsf2 (operands[0], temp));
2923 (define_insn "floatsisf2_ieee"
2924 [(set (match_operand:SF 0 "register_operand" "=f")
2925 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2926 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2928 [(set_attr "op_type" "RRE")
2929 (set_attr "type" "itof" )])
2932 ; truncdfsf2 instruction pattern(s).
2935 (define_expand "truncdfsf2"
2936 [(set (match_operand:SF 0 "register_operand" "")
2937 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2941 (define_insn "truncdfsf2_ieee"
2942 [(set (match_operand:SF 0 "register_operand" "=f")
2943 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2944 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2946 [(set_attr "op_type" "RRE")])
2948 (define_insn "truncdfsf2_ibm"
2949 [(set (match_operand:SF 0 "register_operand" "=f,f")
2950 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2951 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2955 [(set_attr "op_type" "RR,RX")
2956 (set_attr "type" "floadsf")])
2959 ; extendsfdf2 instruction pattern(s).
2962 (define_expand "extendsfdf2"
2963 [(set (match_operand:DF 0 "register_operand" "")
2964 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2967 if (TARGET_IBM_FLOAT)
2969 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2974 (define_insn "extendsfdf2_ieee"
2975 [(set (match_operand:DF 0 "register_operand" "=f,f")
2976 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2977 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2981 [(set_attr "op_type" "RRE,RXE")
2982 (set_attr "type" "floadsf")])
2984 (define_insn "extendsfdf2_ibm"
2985 [(set (match_operand:DF 0 "register_operand" "=f,f")
2986 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2987 (clobber (reg:CC CC_REGNUM))]
2988 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2990 sdr\t%0,%0\;ler\t%0,%1
2991 sdr\t%0,%0\;le\t%0,%1"
2992 [(set_attr "length" "4,6")
2993 (set_attr "type" "floadsf")])
2997 ;; ARITHMETIC OPERATIONS
2999 ; arithmetic operations set the ConditionCode,
3000 ; because of unpredictable Bits in Register for Halfword and Byte
3001 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3004 ;;- Add instructions.
3008 ; addti3 instruction pattern(s).
3011 (define_insn_and_split "addti3"
3012 [(set (match_operand:TI 0 "register_operand" "=&d")
3013 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3014 (match_operand:TI 2 "general_operand" "do") ) )
3015 (clobber (reg:CC CC_REGNUM))]
3018 "&& reload_completed"
3020 [(set (reg:CCL1 CC_REGNUM)
3021 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3023 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3025 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3026 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3027 (clobber (reg:CC CC_REGNUM))])]
3028 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3029 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3030 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3031 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3032 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3033 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3036 ; adddi3 instruction pattern(s).
3039 (define_insn "*adddi3_sign"
3040 [(set (match_operand:DI 0 "register_operand" "=d,d")
3041 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3042 (match_operand:DI 1 "register_operand" "0,0")))
3043 (clobber (reg:CC CC_REGNUM))]
3048 [(set_attr "op_type" "RRE,RXY")])
3050 (define_insn "*adddi3_zero_cc"
3051 [(set (reg CC_REGNUM)
3052 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3053 (match_operand:DI 1 "register_operand" "0,0"))
3055 (set (match_operand:DI 0 "register_operand" "=d,d")
3056 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3057 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3061 [(set_attr "op_type" "RRE,RXY")])
3063 (define_insn "*adddi3_zero_cconly"
3064 [(set (reg CC_REGNUM)
3065 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3066 (match_operand:DI 1 "register_operand" "0,0"))
3068 (clobber (match_scratch:DI 0 "=d,d"))]
3069 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3073 [(set_attr "op_type" "RRE,RXY")])
3075 (define_insn "*adddi3_zero"
3076 [(set (match_operand:DI 0 "register_operand" "=d,d")
3077 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3078 (match_operand:DI 1 "register_operand" "0,0")))
3079 (clobber (reg:CC CC_REGNUM))]
3084 [(set_attr "op_type" "RRE,RXY")])
3086 (define_insn "*adddi3_imm_cc"
3087 [(set (reg CC_REGNUM)
3088 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3089 (match_operand:DI 2 "const_int_operand" "K"))
3091 (set (match_operand:DI 0 "register_operand" "=d")
3092 (plus:DI (match_dup 1) (match_dup 2)))]
3094 && s390_match_ccmode (insn, CCAmode)
3095 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3097 [(set_attr "op_type" "RI")])
3099 (define_insn "*adddi3_carry1_cc"
3100 [(set (reg CC_REGNUM)
3101 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3102 (match_operand:DI 2 "general_operand" "d,m"))
3104 (set (match_operand:DI 0 "register_operand" "=d,d")
3105 (plus:DI (match_dup 1) (match_dup 2)))]
3106 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3110 [(set_attr "op_type" "RRE,RXY")])
3112 (define_insn "*adddi3_carry1_cconly"
3113 [(set (reg CC_REGNUM)
3114 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3115 (match_operand:DI 2 "general_operand" "d,m"))
3117 (clobber (match_scratch:DI 0 "=d,d"))]
3118 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3122 [(set_attr "op_type" "RRE,RXY")])
3124 (define_insn "*adddi3_carry2_cc"
3125 [(set (reg CC_REGNUM)
3126 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3127 (match_operand:DI 2 "general_operand" "d,m"))
3129 (set (match_operand:DI 0 "register_operand" "=d,d")
3130 (plus:DI (match_dup 1) (match_dup 2)))]
3131 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3135 [(set_attr "op_type" "RRE,RXY")])
3137 (define_insn "*adddi3_carry2_cconly"
3138 [(set (reg CC_REGNUM)
3139 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3140 (match_operand:DI 2 "general_operand" "d,m"))
3142 (clobber (match_scratch:DI 0 "=d,d"))]
3143 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3147 [(set_attr "op_type" "RRE,RXY")])
3149 (define_insn "*adddi3_cc"
3150 [(set (reg CC_REGNUM)
3151 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3152 (match_operand:DI 2 "general_operand" "d,m"))
3154 (set (match_operand:DI 0 "register_operand" "=d,d")
3155 (plus:DI (match_dup 1) (match_dup 2)))]
3156 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3160 [(set_attr "op_type" "RRE,RXY")])
3162 (define_insn "*adddi3_cconly"
3163 [(set (reg CC_REGNUM)
3164 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3165 (match_operand:DI 2 "general_operand" "d,m"))
3167 (clobber (match_scratch:DI 0 "=d,d"))]
3168 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3172 [(set_attr "op_type" "RRE,RXY")])
3174 (define_insn "*adddi3_cconly2"
3175 [(set (reg CC_REGNUM)
3176 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3177 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3178 (clobber (match_scratch:DI 0 "=d,d"))]
3179 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3183 [(set_attr "op_type" "RRE,RXY")])
3185 (define_insn "*adddi3_64"
3186 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3187 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3188 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3189 (clobber (reg:CC CC_REGNUM))]
3195 [(set_attr "op_type" "RRE,RI,RXY")])
3197 (define_insn_and_split "*adddi3_31z"
3198 [(set (match_operand:DI 0 "register_operand" "=&d")
3199 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3200 (match_operand:DI 2 "general_operand" "do") ) )
3201 (clobber (reg:CC CC_REGNUM))]
3202 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3204 "&& reload_completed"
3206 [(set (reg:CCL1 CC_REGNUM)
3207 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3209 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3211 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3212 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3213 (clobber (reg:CC CC_REGNUM))])]
3214 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3215 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3216 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3217 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3218 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3219 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3221 (define_insn_and_split "*adddi3_31"
3222 [(set (match_operand:DI 0 "register_operand" "=&d")
3223 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3224 (match_operand:DI 2 "general_operand" "do") ) )
3225 (clobber (reg:CC CC_REGNUM))]
3228 "&& reload_completed"
3230 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3231 (clobber (reg:CC CC_REGNUM))])
3233 [(set (reg:CCL1 CC_REGNUM)
3234 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3236 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3238 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3240 (label_ref (match_dup 9))))
3242 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3243 (clobber (reg:CC CC_REGNUM))])
3245 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3246 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3247 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3248 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3249 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3250 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3251 operands[9] = gen_label_rtx ();")
3253 (define_expand "adddi3"
3255 [(set (match_operand:DI 0 "register_operand" "")
3256 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3257 (match_operand:DI 2 "general_operand" "")))
3258 (clobber (reg:CC CC_REGNUM))])]
3263 ; addsi3 instruction pattern(s).
3266 (define_insn "*addsi3_imm_cc"
3267 [(set (reg CC_REGNUM)
3268 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3269 (match_operand:SI 2 "const_int_operand" "K"))
3271 (set (match_operand:SI 0 "register_operand" "=d")
3272 (plus:SI (match_dup 1) (match_dup 2)))]
3273 "s390_match_ccmode (insn, CCAmode)
3274 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3276 [(set_attr "op_type" "RI")])
3278 (define_insn "*addsi3_carry1_cc"
3279 [(set (reg CC_REGNUM)
3280 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3281 (match_operand:SI 2 "general_operand" "d,R,T"))
3283 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3284 (plus:SI (match_dup 1) (match_dup 2)))]
3285 "s390_match_ccmode (insn, CCL1mode)"
3290 [(set_attr "op_type" "RR,RX,RXY")])
3292 (define_insn "*addsi3_carry1_cconly"
3293 [(set (reg CC_REGNUM)
3294 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3295 (match_operand:SI 2 "general_operand" "d,R,T"))
3297 (clobber (match_scratch:SI 0 "=d,d,d"))]
3298 "s390_match_ccmode (insn, CCL1mode)"
3303 [(set_attr "op_type" "RR,RX,RXY")])
3305 (define_insn "*addsi3_carry2_cc"
3306 [(set (reg CC_REGNUM)
3307 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3308 (match_operand:SI 2 "general_operand" "d,R,T"))
3310 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3311 (plus:SI (match_dup 1) (match_dup 2)))]
3312 "s390_match_ccmode (insn, CCL1mode)"
3317 [(set_attr "op_type" "RR,RX,RXY")])
3319 (define_insn "*addsi3_carry2_cconly"
3320 [(set (reg CC_REGNUM)
3321 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3322 (match_operand:SI 2 "general_operand" "d,R,T"))
3324 (clobber (match_scratch:SI 0 "=d,d,d"))]
3325 "s390_match_ccmode (insn, CCL1mode)"
3330 [(set_attr "op_type" "RR,RX,RXY")])
3332 (define_insn "*addsi3_cc"
3333 [(set (reg CC_REGNUM)
3334 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3335 (match_operand:SI 2 "general_operand" "d,R,T"))
3337 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3338 (plus:SI (match_dup 1) (match_dup 2)))]
3339 "s390_match_ccmode (insn, CCLmode)"
3344 [(set_attr "op_type" "RR,RX,RXY")])
3346 (define_insn "*addsi3_cconly"
3347 [(set (reg CC_REGNUM)
3348 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3349 (match_operand:SI 2 "general_operand" "d,R,T"))
3351 (clobber (match_scratch:SI 0 "=d,d,d"))]
3352 "s390_match_ccmode (insn, CCLmode)"
3357 [(set_attr "op_type" "RR,RX,RXY")])
3359 (define_insn "*addsi3_cconly2"
3360 [(set (reg CC_REGNUM)
3361 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3362 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3363 (clobber (match_scratch:SI 0 "=d,d,d"))]
3364 "s390_match_ccmode (insn, CCLmode)"
3369 [(set_attr "op_type" "RR,RX,RXY")])
3371 (define_insn "*addsi3_sign"
3372 [(set (match_operand:SI 0 "register_operand" "=d,d")
3373 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3374 (match_operand:SI 1 "register_operand" "0,0")))
3375 (clobber (reg:CC CC_REGNUM))]
3380 [(set_attr "op_type" "RX,RXY")])
3382 (define_insn "addsi3"
3383 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3384 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3385 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3386 (clobber (reg:CC CC_REGNUM))]
3393 [(set_attr "op_type" "RR,RI,RX,RXY")])
3396 ; add(df|sf)3 instruction pattern(s).
3399 (define_expand "add<mode>3"
3401 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3402 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3403 (match_operand:FPR 2 "general_operand" "f,R")))
3404 (clobber (reg:CC CC_REGNUM))])]
3408 (define_insn "*add<mode>3"
3409 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3410 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3411 (match_operand:FPR 2 "general_operand" "f,R")))
3412 (clobber (reg:CC CC_REGNUM))]
3413 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3417 [(set_attr "op_type" "RRE,RXE")
3418 (set_attr "type" "fsimp<mode>")])
3420 (define_insn "*add<mode>3_cc"
3421 [(set (reg CC_REGNUM)
3422 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3423 (match_operand:FPR 2 "general_operand" "f,R"))
3424 (match_operand:FPR 3 "const0_operand" "")))
3425 (set (match_operand:FPR 0 "register_operand" "=f,f")
3426 (plus:FPR (match_dup 1) (match_dup 2)))]
3427 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3431 [(set_attr "op_type" "RRE,RXE")
3432 (set_attr "type" "fsimp<mode>")])
3434 (define_insn "*add<mode>3_cconly"
3435 [(set (reg CC_REGNUM)
3436 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3437 (match_operand:FPR 2 "general_operand" "f,R"))
3438 (match_operand:FPR 3 "const0_operand" "")))
3439 (clobber (match_scratch:FPR 0 "=f,f"))]
3440 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3444 [(set_attr "op_type" "RRE,RXE")
3445 (set_attr "type" "fsimp<mode>")])
3447 (define_insn "*add<mode>3_ibm"
3448 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3449 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3450 (match_operand:FPR 2 "general_operand" "f,R")))
3451 (clobber (reg:CC CC_REGNUM))]
3452 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3456 [(set_attr "op_type" "RR,RX")
3457 (set_attr "type" "fsimp<mode>")])
3461 ;;- Subtract instructions.
3465 ; subti3 instruction pattern(s).
3468 (define_insn_and_split "subti3"
3469 [(set (match_operand:TI 0 "register_operand" "=&d")
3470 (minus:TI (match_operand:TI 1 "register_operand" "0")
3471 (match_operand:TI 2 "general_operand" "do") ) )
3472 (clobber (reg:CC CC_REGNUM))]
3475 "&& reload_completed"
3477 [(set (reg:CCL2 CC_REGNUM)
3478 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3480 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3482 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3483 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3484 (clobber (reg:CC CC_REGNUM))])]
3485 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3486 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3487 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3488 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3489 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3490 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3493 ; subdi3 instruction pattern(s).
3496 (define_insn "*subdi3_sign"
3497 [(set (match_operand:DI 0 "register_operand" "=d,d")
3498 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3499 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3500 (clobber (reg:CC CC_REGNUM))]
3505 [(set_attr "op_type" "RRE,RXY")])
3507 (define_insn "*subdi3_zero_cc"
3508 [(set (reg CC_REGNUM)
3509 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3510 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3512 (set (match_operand:DI 0 "register_operand" "=d,d")
3513 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3514 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3518 [(set_attr "op_type" "RRE,RXY")])
3520 (define_insn "*subdi3_zero_cconly"
3521 [(set (reg CC_REGNUM)
3522 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3523 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3525 (clobber (match_scratch:DI 0 "=d,d"))]
3526 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3530 [(set_attr "op_type" "RRE,RXY")])
3532 (define_insn "*subdi3_zero"
3533 [(set (match_operand:DI 0 "register_operand" "=d,d")
3534 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3535 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3536 (clobber (reg:CC CC_REGNUM))]
3541 [(set_attr "op_type" "RRE,RXY")])
3543 (define_insn "*subdi3_borrow_cc"
3544 [(set (reg CC_REGNUM)
3545 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3546 (match_operand:DI 2 "general_operand" "d,m"))
3548 (set (match_operand:DI 0 "register_operand" "=d,d")
3549 (minus:DI (match_dup 1) (match_dup 2)))]
3550 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3554 [(set_attr "op_type" "RRE,RXY")])
3556 (define_insn "*subdi3_borrow_cconly"
3557 [(set (reg CC_REGNUM)
3558 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3559 (match_operand:DI 2 "general_operand" "d,m"))
3561 (clobber (match_scratch:DI 0 "=d,d"))]
3562 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3566 [(set_attr "op_type" "RRE,RXY")])
3568 (define_insn "*subdi3_cc"
3569 [(set (reg CC_REGNUM)
3570 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3571 (match_operand:DI 2 "general_operand" "d,m"))
3573 (set (match_operand:DI 0 "register_operand" "=d,d")
3574 (minus:DI (match_dup 1) (match_dup 2)))]
3575 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3579 [(set_attr "op_type" "RRE,RXY")])
3581 (define_insn "*subdi3_cc2"
3582 [(set (reg CC_REGNUM)
3583 (compare (match_operand:DI 1 "register_operand" "0,0")
3584 (match_operand:DI 2 "general_operand" "d,m")))
3585 (set (match_operand:DI 0 "register_operand" "=d,d")
3586 (minus:DI (match_dup 1) (match_dup 2)))]
3587 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3591 [(set_attr "op_type" "RRE,RXY")])
3593 (define_insn "*subdi3_cconly"
3594 [(set (reg CC_REGNUM)
3595 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3596 (match_operand:DI 2 "general_operand" "d,m"))
3598 (clobber (match_scratch:DI 0 "=d,d"))]
3599 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3603 [(set_attr "op_type" "RRE,RXY")])
3605 (define_insn "*subdi3_cconly2"
3606 [(set (reg CC_REGNUM)
3607 (compare (match_operand:DI 1 "register_operand" "0,0")
3608 (match_operand:DI 2 "general_operand" "d,m")))
3609 (clobber (match_scratch:DI 0 "=d,d"))]
3610 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3614 [(set_attr "op_type" "RRE,RXY")])
3616 (define_insn "*subdi3_64"
3617 [(set (match_operand:DI 0 "register_operand" "=d,d")
3618 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3619 (match_operand:DI 2 "general_operand" "d,m") ) )
3620 (clobber (reg:CC CC_REGNUM))]
3625 [(set_attr "op_type" "RRE,RRE")])
3627 (define_insn_and_split "*subdi3_31z"
3628 [(set (match_operand:DI 0 "register_operand" "=&d")
3629 (minus:DI (match_operand:DI 1 "register_operand" "0")
3630 (match_operand:DI 2 "general_operand" "do") ) )
3631 (clobber (reg:CC CC_REGNUM))]
3632 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3634 "&& reload_completed"
3636 [(set (reg:CCL2 CC_REGNUM)
3637 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3639 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3641 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3642 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3643 (clobber (reg:CC CC_REGNUM))])]
3644 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3645 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3646 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3647 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3648 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3649 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3651 (define_insn_and_split "*subdi3_31"
3652 [(set (match_operand:DI 0 "register_operand" "=&d")
3653 (minus:DI (match_operand:DI 1 "register_operand" "0")
3654 (match_operand:DI 2 "general_operand" "do") ) )
3655 (clobber (reg:CC CC_REGNUM))]
3658 "&& reload_completed"
3660 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3661 (clobber (reg:CC CC_REGNUM))])
3663 [(set (reg:CCL2 CC_REGNUM)
3664 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3666 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3668 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3670 (label_ref (match_dup 9))))
3672 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3673 (clobber (reg:CC CC_REGNUM))])
3675 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3676 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3677 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3678 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3679 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3680 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3681 operands[9] = gen_label_rtx ();")
3683 (define_expand "subdi3"
3685 [(set (match_operand:DI 0 "register_operand" "")
3686 (minus:DI (match_operand:DI 1 "register_operand" "")
3687 (match_operand:DI 2 "general_operand" "")))
3688 (clobber (reg:CC CC_REGNUM))])]
3693 ; subsi3 instruction pattern(s).
3696 (define_insn "*subsi3_borrow_cc"
3697 [(set (reg CC_REGNUM)
3698 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3699 (match_operand:SI 2 "general_operand" "d,R,T"))
3701 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3702 (minus:SI (match_dup 1) (match_dup 2)))]
3703 "s390_match_ccmode (insn, CCL2mode)"
3708 [(set_attr "op_type" "RR,RX,RXY")])
3710 (define_insn "*subsi3_borrow_cconly"
3711 [(set (reg CC_REGNUM)
3712 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3713 (match_operand:SI 2 "general_operand" "d,R,T"))
3715 (clobber (match_scratch:SI 0 "=d,d,d"))]
3716 "s390_match_ccmode (insn, CCL2mode)"
3721 [(set_attr "op_type" "RR,RX,RXY")])
3723 (define_insn "*subsi3_cc"
3724 [(set (reg CC_REGNUM)
3725 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3726 (match_operand:SI 2 "general_operand" "d,R,T"))
3728 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3729 (minus:SI (match_dup 1) (match_dup 2)))]
3730 "s390_match_ccmode (insn, CCLmode)"
3735 [(set_attr "op_type" "RR,RX,RXY")])
3737 (define_insn "*subsi3_cc2"
3738 [(set (reg CC_REGNUM)
3739 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3740 (match_operand:SI 2 "general_operand" "d,R,T")))
3741 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3742 (minus:SI (match_dup 1) (match_dup 2)))]
3743 "s390_match_ccmode (insn, CCL3mode)"
3748 [(set_attr "op_type" "RR,RX,RXY")])
3750 (define_insn "*subsi3_cconly"
3751 [(set (reg CC_REGNUM)
3752 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3753 (match_operand:SI 2 "general_operand" "d,R,T"))
3755 (clobber (match_scratch:SI 0 "=d,d,d"))]
3756 "s390_match_ccmode (insn, CCLmode)"
3761 [(set_attr "op_type" "RR,RX,RXY")])
3763 (define_insn "*subsi3_cconly2"
3764 [(set (reg CC_REGNUM)
3765 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3766 (match_operand:SI 2 "general_operand" "d,R,T")))
3767 (clobber (match_scratch:SI 0 "=d,d,d"))]
3768 "s390_match_ccmode (insn, CCL3mode)"
3773 [(set_attr "op_type" "RR,RX,RXY")])
3775 (define_insn "*subsi3_sign"
3776 [(set (match_operand:SI 0 "register_operand" "=d,d")
3777 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3778 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3779 (clobber (reg:CC CC_REGNUM))]
3784 [(set_attr "op_type" "RX,RXY")])
3786 (define_insn "subsi3"
3787 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3788 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3789 (match_operand:SI 2 "general_operand" "d,R,T")))
3790 (clobber (reg:CC CC_REGNUM))]
3796 [(set_attr "op_type" "RR,RX,RXY")])
3800 ; sub(df|sf)3 instruction pattern(s).
3803 (define_expand "sub<mode>3"
3805 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3806 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3807 (match_operand:FPR 2 "general_operand" "f,R")))
3808 (clobber (reg:CC CC_REGNUM))])]
3812 (define_insn "*sub<mode>3"
3813 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3814 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3815 (match_operand:FPR 2 "general_operand" "f,R")))
3816 (clobber (reg:CC CC_REGNUM))]
3817 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3821 [(set_attr "op_type" "RRE,RXE")
3822 (set_attr "type" "fsimp<mode>")])
3824 (define_insn "*sub<mode>3_cc"
3825 [(set (reg CC_REGNUM)
3826 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3827 (match_operand:FPR 2 "general_operand" "f,R"))
3828 (match_operand:FPR 3 "const0_operand" "")))
3829 (set (match_operand:FPR 0 "register_operand" "=f,f")
3830 (minus:FPR (match_dup 1) (match_dup 2)))]
3831 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3835 [(set_attr "op_type" "RRE,RXE")
3836 (set_attr "type" "fsimp<mode>")])
3838 (define_insn "*sub<mode>3_cconly"
3839 [(set (reg CC_REGNUM)
3840 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3841 (match_operand:FPR 2 "general_operand" "f,R"))
3842 (match_operand:FPR 3 "const0_operand" "")))
3843 (clobber (match_scratch:FPR 0 "=f,f"))]
3844 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3848 [(set_attr "op_type" "RRE,RXE")
3849 (set_attr "type" "fsimp<mode>")])
3851 (define_insn "*sub<mode>3_ibm"
3852 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3853 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3854 (match_operand:FPR 2 "general_operand" "f,R")))
3855 (clobber (reg:CC CC_REGNUM))]
3856 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3860 [(set_attr "op_type" "RR,RX")
3861 (set_attr "type" "fsimp<mode>")])
3865 ;;- Conditional add/subtract instructions.
3869 ; add(di|si)cc instruction pattern(s).
3872 (define_insn "*add<mode>3_alc_cc"
3873 [(set (reg CC_REGNUM)
3875 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3876 (match_operand:GPR 2 "general_operand" "d,m"))
3877 (match_operand:GPR 3 "s390_alc_comparison" ""))
3879 (set (match_operand:GPR 0 "register_operand" "=d,d")
3880 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3881 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3885 [(set_attr "op_type" "RRE,RXY")])
3887 (define_insn "*add<mode>3_alc"
3888 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3889 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3890 (match_operand:GPR 2 "general_operand" "d,m"))
3891 (match_operand:GPR 3 "s390_alc_comparison" "")))
3892 (clobber (reg:CC CC_REGNUM))]
3897 [(set_attr "op_type" "RRE,RXY")])
3899 (define_insn "*sub<mode>3_slb_cc"
3900 [(set (reg CC_REGNUM)
3902 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3903 (match_operand:GPR 2 "general_operand" "d,m"))
3904 (match_operand:GPR 3 "s390_slb_comparison" ""))
3906 (set (match_operand:GPR 0 "register_operand" "=d,d")
3907 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3908 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3912 [(set_attr "op_type" "RRE,RXY")])
3914 (define_insn "*sub<mode>3_slb"
3915 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3916 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3917 (match_operand:GPR 2 "general_operand" "d,m"))
3918 (match_operand:GPR 3 "s390_slb_comparison" "")))
3919 (clobber (reg:CC CC_REGNUM))]
3924 [(set_attr "op_type" "RRE,RXY")])
3926 (define_expand "add<mode>cc"
3927 [(match_operand:GPR 0 "register_operand" "")
3928 (match_operand 1 "comparison_operator" "")
3929 (match_operand:GPR 2 "register_operand" "")
3930 (match_operand:GPR 3 "const_int_operand" "")]
3932 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3933 s390_compare_op0, s390_compare_op1,
3934 operands[0], operands[2],
3935 operands[3])) FAIL; DONE;")
3938 ; scond instruction pattern(s).
3941 (define_insn_and_split "*scond<mode>"
3942 [(set (match_operand:GPR 0 "register_operand" "=&d")
3943 (match_operand:GPR 1 "s390_alc_comparison" ""))
3944 (clobber (reg:CC CC_REGNUM))]
3947 "&& reload_completed"
3948 [(set (match_dup 0) (const_int 0))
3950 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3952 (clobber (reg:CC CC_REGNUM))])]
3955 (define_insn_and_split "*scond<mode>_neg"
3956 [(set (match_operand:GPR 0 "register_operand" "=&d")
3957 (match_operand:GPR 1 "s390_slb_comparison" ""))
3958 (clobber (reg:CC CC_REGNUM))]
3961 "&& reload_completed"
3962 [(set (match_dup 0) (const_int 0))
3964 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3966 (clobber (reg:CC CC_REGNUM))])
3968 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3969 (clobber (reg:CC CC_REGNUM))])]
3973 (define_expand "s<code>"
3974 [(set (match_operand:SI 0 "register_operand" "")
3975 (SCOND (match_dup 0)
3978 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3979 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3981 (define_expand "seq"
3983 [(set (match_operand:SI 0 "register_operand" "=d")
3985 (clobber (reg:CC CC_REGNUM))])
3987 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
3988 (clobber (reg:CC CC_REGNUM))])]
3991 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
3993 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
3994 PUT_MODE (operands[1], SImode);
3997 (define_insn_and_split "*sne"
3998 [(set (match_operand:SI 0 "register_operand" "=d")
3999 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4001 (clobber (reg:CC CC_REGNUM))]
4006 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4007 (clobber (reg:CC CC_REGNUM))])])
4011 ;;- Multiply instructions.
4015 ; muldi3 instruction pattern(s).
4018 (define_insn "*muldi3_sign"
4019 [(set (match_operand:DI 0 "register_operand" "=d,d")
4020 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4021 (match_operand:DI 1 "register_operand" "0,0")))]
4026 [(set_attr "op_type" "RRE,RXY")
4027 (set_attr "type" "imuldi")])
4029 (define_insn "muldi3"
4030 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4031 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4032 (match_operand:DI 2 "general_operand" "d,K,m")))]
4038 [(set_attr "op_type" "RRE,RI,RXY")
4039 (set_attr "type" "imuldi")])
4042 ; mulsi3 instruction pattern(s).
4045 (define_insn "*mulsi3_sign"
4046 [(set (match_operand:SI 0 "register_operand" "=d")
4047 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4048 (match_operand:SI 1 "register_operand" "0")))]
4051 [(set_attr "op_type" "RX")
4052 (set_attr "type" "imulhi")])
4054 (define_insn "mulsi3"
4055 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4056 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4057 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4064 [(set_attr "op_type" "RRE,RI,RX,RXY")
4065 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4068 ; mulsidi3 instruction pattern(s).
4071 (define_insn "mulsidi3"
4072 [(set (match_operand:DI 0 "register_operand" "=d,d")
4073 (mult:DI (sign_extend:DI
4074 (match_operand:SI 1 "register_operand" "%0,0"))
4076 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4081 [(set_attr "op_type" "RR,RX")
4082 (set_attr "type" "imulsi")])
4085 ; umulsidi3 instruction pattern(s).
4088 (define_insn "umulsidi3"
4089 [(set (match_operand:DI 0 "register_operand" "=d,d")
4090 (mult:DI (zero_extend:DI
4091 (match_operand:SI 1 "register_operand" "%0,0"))
4093 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4094 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4098 [(set_attr "op_type" "RRE,RXY")
4099 (set_attr "type" "imulsi")])
4102 ; mul(df|sf)3 instruction pattern(s).
4105 (define_expand "mul<mode>3"
4106 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4107 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4108 (match_operand:FPR 2 "general_operand" "f,R")))]
4112 (define_insn "*mul<mode>3"
4113 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4114 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4115 (match_operand:FPR 2 "general_operand" "f,R")))]
4116 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4120 [(set_attr "op_type" "RRE,RXE")
4121 (set_attr "type" "fmul<mode>")])
4123 (define_insn "*mul<mode>3_ibm"
4124 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4125 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4126 (match_operand:FPR 2 "general_operand" "f,R")))]
4127 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4131 [(set_attr "op_type" "RR,RX")
4132 (set_attr "type" "fmul<mode>")])
4134 (define_insn "*fmadd<mode>"
4135 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4136 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4137 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4138 (match_operand:FPR 3 "register_operand" "0,0")))]
4139 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4143 [(set_attr "op_type" "RRE,RXE")
4144 (set_attr "type" "fmul<mode>")])
4146 (define_insn "*fmsub<mode>"
4147 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4148 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4149 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4150 (match_operand:FPR 3 "register_operand" "0,0")))]
4151 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4155 [(set_attr "op_type" "RRE,RXE")
4156 (set_attr "type" "fmul<mode>")])
4159 ;;- Divide and modulo instructions.
4163 ; divmoddi4 instruction pattern(s).
4166 (define_expand "divmoddi4"
4167 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4168 (div:DI (match_operand:DI 1 "register_operand" "")
4169 (match_operand:DI 2 "general_operand" "")))
4170 (set (match_operand:DI 3 "general_operand" "")
4171 (mod:DI (match_dup 1) (match_dup 2)))])
4172 (clobber (match_dup 4))]
4175 rtx insn, div_equal, mod_equal;
4177 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4178 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4180 operands[4] = gen_reg_rtx(TImode);
4181 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4183 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4185 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4187 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4189 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4194 (define_insn "divmodtidi3"
4195 [(set (match_operand:TI 0 "register_operand" "=d,d")
4199 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4200 (match_operand:DI 2 "general_operand" "d,m")))
4202 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4207 [(set_attr "op_type" "RRE,RXY")
4208 (set_attr "type" "idiv")])
4210 (define_insn "divmodtisi3"
4211 [(set (match_operand:TI 0 "register_operand" "=d,d")
4215 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4217 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4220 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4225 [(set_attr "op_type" "RRE,RXY")
4226 (set_attr "type" "idiv")])
4229 ; udivmoddi4 instruction pattern(s).
4232 (define_expand "udivmoddi4"
4233 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4234 (udiv:DI (match_operand:DI 1 "general_operand" "")
4235 (match_operand:DI 2 "nonimmediate_operand" "")))
4236 (set (match_operand:DI 3 "general_operand" "")
4237 (umod:DI (match_dup 1) (match_dup 2)))])
4238 (clobber (match_dup 4))]
4241 rtx insn, div_equal, mod_equal, equal;
4243 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4244 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4245 equal = gen_rtx_IOR (TImode,
4246 gen_rtx_ASHIFT (TImode,
4247 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4249 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4251 operands[4] = gen_reg_rtx(TImode);
4252 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4253 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4254 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4255 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4257 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4259 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4261 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4263 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4265 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4270 (define_insn "udivmodtidi3"
4271 [(set (match_operand:TI 0 "register_operand" "=d,d")
4276 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4278 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4282 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4287 [(set_attr "op_type" "RRE,RXY")
4288 (set_attr "type" "idiv")])
4291 ; divmodsi4 instruction pattern(s).
4294 (define_expand "divmodsi4"
4295 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4296 (div:SI (match_operand:SI 1 "general_operand" "")
4297 (match_operand:SI 2 "nonimmediate_operand" "")))
4298 (set (match_operand:SI 3 "general_operand" "")
4299 (mod:SI (match_dup 1) (match_dup 2)))])
4300 (clobber (match_dup 4))]
4303 rtx insn, div_equal, mod_equal, equal;
4305 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4306 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4307 equal = gen_rtx_IOR (DImode,
4308 gen_rtx_ASHIFT (DImode,
4309 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4311 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4313 operands[4] = gen_reg_rtx(DImode);
4314 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4315 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4317 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4319 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4321 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4323 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4325 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4330 (define_insn "divmoddisi3"
4331 [(set (match_operand:DI 0 "register_operand" "=d,d")
4336 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4338 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4342 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4347 [(set_attr "op_type" "RR,RX")
4348 (set_attr "type" "idiv")])
4351 ; udivsi3 and umodsi3 instruction pattern(s).
4354 (define_expand "udivmodsi4"
4355 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4356 (udiv:SI (match_operand:SI 1 "general_operand" "")
4357 (match_operand:SI 2 "nonimmediate_operand" "")))
4358 (set (match_operand:SI 3 "general_operand" "")
4359 (umod:SI (match_dup 1) (match_dup 2)))])
4360 (clobber (match_dup 4))]
4361 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4363 rtx insn, div_equal, mod_equal, equal;
4365 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4366 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4367 equal = gen_rtx_IOR (DImode,
4368 gen_rtx_ASHIFT (DImode,
4369 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4371 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4373 operands[4] = gen_reg_rtx(DImode);
4374 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4375 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4376 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4377 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4379 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4381 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4383 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4385 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4387 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4392 (define_insn "udivmoddisi3"
4393 [(set (match_operand:DI 0 "register_operand" "=d,d")
4398 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4400 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4404 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4405 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4409 [(set_attr "op_type" "RRE,RXY")
4410 (set_attr "type" "idiv")])
4412 (define_expand "udivsi3"
4413 [(set (match_operand:SI 0 "register_operand" "=d")
4414 (udiv:SI (match_operand:SI 1 "general_operand" "")
4415 (match_operand:SI 2 "general_operand" "")))
4416 (clobber (match_dup 3))]
4417 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4419 rtx insn, udiv_equal, umod_equal, equal;
4421 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4422 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4423 equal = gen_rtx_IOR (DImode,
4424 gen_rtx_ASHIFT (DImode,
4425 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4427 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4429 operands[3] = gen_reg_rtx (DImode);
4431 if (CONSTANT_P (operands[2]))
4433 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4435 rtx label1 = gen_label_rtx ();
4437 operands[1] = make_safe_from (operands[1], operands[0]);
4438 emit_move_insn (operands[0], const0_rtx);
4439 emit_insn (gen_cmpsi (operands[1], operands[2]));
4440 emit_jump_insn (gen_bltu (label1));
4441 emit_move_insn (operands[0], const1_rtx);
4442 emit_label (label1);
4446 operands[2] = force_reg (SImode, operands[2]);
4447 operands[2] = make_safe_from (operands[2], operands[0]);
4449 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4450 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4453 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4455 insn = emit_move_insn (operands[0],
4456 gen_lowpart (SImode, operands[3]));
4458 gen_rtx_EXPR_LIST (REG_EQUAL,
4459 udiv_equal, REG_NOTES (insn));
4464 rtx label1 = gen_label_rtx ();
4465 rtx label2 = gen_label_rtx ();
4466 rtx label3 = gen_label_rtx ();
4468 operands[1] = force_reg (SImode, operands[1]);
4469 operands[1] = make_safe_from (operands[1], operands[0]);
4470 operands[2] = force_reg (SImode, operands[2]);
4471 operands[2] = make_safe_from (operands[2], operands[0]);
4473 emit_move_insn (operands[0], const0_rtx);
4474 emit_insn (gen_cmpsi (operands[2], operands[1]));
4475 emit_jump_insn (gen_bgtu (label3));
4476 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4477 emit_jump_insn (gen_blt (label2));
4478 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4479 emit_jump_insn (gen_beq (label1));
4480 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4481 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4484 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4486 insn = emit_move_insn (operands[0],
4487 gen_lowpart (SImode, operands[3]));
4489 gen_rtx_EXPR_LIST (REG_EQUAL,
4490 udiv_equal, REG_NOTES (insn));
4492 emit_label (label1);
4493 emit_move_insn (operands[0], operands[1]);
4495 emit_label (label2);
4496 emit_move_insn (operands[0], const1_rtx);
4497 emit_label (label3);
4499 emit_move_insn (operands[0], operands[0]);
4503 (define_expand "umodsi3"
4504 [(set (match_operand:SI 0 "register_operand" "=d")
4505 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4506 (match_operand:SI 2 "nonimmediate_operand" "")))
4507 (clobber (match_dup 3))]
4508 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4510 rtx insn, udiv_equal, umod_equal, equal;
4512 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4513 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4514 equal = gen_rtx_IOR (DImode,
4515 gen_rtx_ASHIFT (DImode,
4516 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4518 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4520 operands[3] = gen_reg_rtx (DImode);
4522 if (CONSTANT_P (operands[2]))
4524 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4526 rtx label1 = gen_label_rtx ();
4528 operands[1] = make_safe_from (operands[1], operands[0]);
4529 emit_move_insn (operands[0], operands[1]);
4530 emit_insn (gen_cmpsi (operands[0], operands[2]));
4531 emit_jump_insn (gen_bltu (label1));
4532 emit_insn (gen_abssi2 (operands[0], operands[2]));
4533 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4534 emit_label (label1);
4538 operands[2] = force_reg (SImode, operands[2]);
4539 operands[2] = make_safe_from (operands[2], operands[0]);
4541 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4542 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4545 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4547 insn = emit_move_insn (operands[0],
4548 gen_highpart (SImode, operands[3]));
4550 gen_rtx_EXPR_LIST (REG_EQUAL,
4551 umod_equal, REG_NOTES (insn));
4556 rtx label1 = gen_label_rtx ();
4557 rtx label2 = gen_label_rtx ();
4558 rtx label3 = gen_label_rtx ();
4560 operands[1] = force_reg (SImode, operands[1]);
4561 operands[1] = make_safe_from (operands[1], operands[0]);
4562 operands[2] = force_reg (SImode, operands[2]);
4563 operands[2] = make_safe_from (operands[2], operands[0]);
4565 emit_move_insn(operands[0], operands[1]);
4566 emit_insn (gen_cmpsi (operands[2], operands[1]));
4567 emit_jump_insn (gen_bgtu (label3));
4568 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4569 emit_jump_insn (gen_blt (label2));
4570 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4571 emit_jump_insn (gen_beq (label1));
4572 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4573 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4576 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4578 insn = emit_move_insn (operands[0],
4579 gen_highpart (SImode, operands[3]));
4581 gen_rtx_EXPR_LIST (REG_EQUAL,
4582 umod_equal, REG_NOTES (insn));
4584 emit_label (label1);
4585 emit_move_insn (operands[0], const0_rtx);
4587 emit_label (label2);
4588 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4589 emit_label (label3);
4595 ; div(df|sf)3 instruction pattern(s).
4598 (define_expand "div<mode>3"
4599 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4600 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4601 (match_operand:FPR 2 "general_operand" "f,R")))]
4605 (define_insn "*div<mode>3"
4606 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4607 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4608 (match_operand:FPR 2 "general_operand" "f,R")))]
4609 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4613 [(set_attr "op_type" "RRE,RXE")
4614 (set_attr "type" "fdiv<mode>")])
4616 (define_insn "*div<mode>3_ibm"
4617 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4618 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4619 (match_operand:FPR 2 "general_operand" "f,R")))]
4620 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4624 [(set_attr "op_type" "RR,RX")
4625 (set_attr "type" "fdiv<mode>")])
4629 ;;- And instructions.
4632 (define_expand "and<mode>3"
4633 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4634 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4635 (match_operand:INT 2 "general_operand" "")))
4636 (clobber (reg:CC CC_REGNUM))]
4638 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4641 ; anddi3 instruction pattern(s).
4644 (define_insn "*anddi3_cc"
4645 [(set (reg CC_REGNUM)
4646 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4647 (match_operand:DI 2 "general_operand" "d,m"))
4649 (set (match_operand:DI 0 "register_operand" "=d,d")
4650 (and:DI (match_dup 1) (match_dup 2)))]
4651 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4655 [(set_attr "op_type" "RRE,RXY")])
4657 (define_insn "*anddi3_cconly"
4658 [(set (reg CC_REGNUM)
4659 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4660 (match_operand:DI 2 "general_operand" "d,m"))
4662 (clobber (match_scratch:DI 0 "=d,d"))]
4663 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4664 /* Do not steal TM patterns. */
4665 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4669 [(set_attr "op_type" "RRE,RXY")])
4671 (define_insn "*anddi3"
4672 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4673 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4674 "%d,o,0,0,0,0,0,0,0,0")
4675 (match_operand:DI 2 "general_operand"
4676 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4677 (clobber (reg:CC CC_REGNUM))]
4678 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4690 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4693 [(set (match_operand:DI 0 "s_operand" "")
4694 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4695 (clobber (reg:CC CC_REGNUM))]
4698 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4699 (clobber (reg:CC CC_REGNUM))])]
4700 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4704 ; andsi3 instruction pattern(s).
4707 (define_insn "*andsi3_cc"
4708 [(set (reg CC_REGNUM)
4709 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4710 (match_operand:SI 2 "general_operand" "d,R,T"))
4712 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4713 (and:SI (match_dup 1) (match_dup 2)))]
4714 "s390_match_ccmode(insn, CCTmode)"
4719 [(set_attr "op_type" "RR,RX,RXY")])
4721 (define_insn "*andsi3_cconly"
4722 [(set (reg CC_REGNUM)
4723 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4724 (match_operand:SI 2 "general_operand" "d,R,T"))
4726 (clobber (match_scratch:SI 0 "=d,d,d"))]
4727 "s390_match_ccmode(insn, CCTmode)
4728 /* Do not steal TM patterns. */
4729 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4734 [(set_attr "op_type" "RR,RX,RXY")])
4736 (define_insn "*andsi3_zarch"
4737 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4738 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4739 "%d,o,0,0,0,0,0,0,0")
4740 (match_operand:SI 2 "general_operand"
4741 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4742 (clobber (reg:CC CC_REGNUM))]
4743 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4754 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4756 (define_insn "*andsi3_esa"
4757 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4758 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4759 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4760 (clobber (reg:CC CC_REGNUM))]
4761 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4767 [(set_attr "op_type" "RR,RX,SI,SS")])
4770 [(set (match_operand:SI 0 "s_operand" "")
4771 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4772 (clobber (reg:CC CC_REGNUM))]
4775 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4776 (clobber (reg:CC CC_REGNUM))])]
4777 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4780 ; andhi3 instruction pattern(s).
4783 (define_insn "*andhi3_zarch"
4784 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4785 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4786 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4787 (clobber (reg:CC CC_REGNUM))]
4788 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4794 [(set_attr "op_type" "RR,RI,SI,SS")])
4796 (define_insn "*andhi3_esa"
4797 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4798 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4799 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4800 (clobber (reg:CC CC_REGNUM))]
4801 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4806 [(set_attr "op_type" "RR,SI,SS")])
4809 [(set (match_operand:HI 0 "s_operand" "")
4810 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4811 (clobber (reg:CC CC_REGNUM))]
4814 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4815 (clobber (reg:CC CC_REGNUM))])]
4816 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4819 ; andqi3 instruction pattern(s).
4822 (define_insn "*andqi3_zarch"
4823 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4824 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4825 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4826 (clobber (reg:CC CC_REGNUM))]
4827 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4834 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4836 (define_insn "*andqi3_esa"
4837 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4838 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4839 (match_operand:QI 2 "general_operand" "d,n,Q")))
4840 (clobber (reg:CC CC_REGNUM))]
4841 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4846 [(set_attr "op_type" "RR,SI,SS")])
4849 ; Block and (NC) patterns.
4853 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4854 (and:BLK (match_dup 0)
4855 (match_operand:BLK 1 "memory_operand" "Q")))
4856 (use (match_operand 2 "const_int_operand" "n"))
4857 (clobber (reg:CC CC_REGNUM))]
4858 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4859 "nc\t%O0(%2,%R0),%S1"
4860 [(set_attr "op_type" "SS")])
4863 [(set (match_operand 0 "memory_operand" "")
4865 (match_operand 1 "memory_operand" "")))
4866 (clobber (reg:CC CC_REGNUM))]
4868 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4869 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4871 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4873 (clobber (reg:CC CC_REGNUM))])]
4875 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4876 operands[0] = adjust_address (operands[0], BLKmode, 0);
4877 operands[1] = adjust_address (operands[1], BLKmode, 0);
4882 [(set (match_operand:BLK 0 "memory_operand" "")
4883 (and:BLK (match_dup 0)
4884 (match_operand:BLK 1 "memory_operand" "")))
4885 (use (match_operand 2 "const_int_operand" ""))
4886 (clobber (reg:CC CC_REGNUM))])
4888 [(set (match_operand:BLK 3 "memory_operand" "")
4889 (and:BLK (match_dup 3)
4890 (match_operand:BLK 4 "memory_operand" "")))
4891 (use (match_operand 5 "const_int_operand" ""))
4892 (clobber (reg:CC CC_REGNUM))])]
4893 "s390_offset_p (operands[0], operands[3], operands[2])
4894 && s390_offset_p (operands[1], operands[4], operands[2])
4895 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4897 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4899 (clobber (reg:CC CC_REGNUM))])]
4900 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4901 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4902 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4906 ;;- Bit set (inclusive or) instructions.
4909 (define_expand "ior<mode>3"
4910 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4911 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4912 (match_operand:INT 2 "general_operand" "")))
4913 (clobber (reg:CC CC_REGNUM))]
4915 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4918 ; iordi3 instruction pattern(s).
4921 (define_insn "*iordi3_cc"
4922 [(set (reg CC_REGNUM)
4923 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4924 (match_operand:DI 2 "general_operand" "d,m"))
4926 (set (match_operand:DI 0 "register_operand" "=d,d")
4927 (ior:DI (match_dup 1) (match_dup 2)))]
4928 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4932 [(set_attr "op_type" "RRE,RXY")])
4934 (define_insn "*iordi3_cconly"
4935 [(set (reg CC_REGNUM)
4936 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4937 (match_operand:DI 2 "general_operand" "d,m"))
4939 (clobber (match_scratch:DI 0 "=d,d"))]
4940 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4944 [(set_attr "op_type" "RRE,RXY")])
4946 (define_insn "*iordi3"
4947 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4948 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4949 (match_operand:DI 2 "general_operand"
4950 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4951 (clobber (reg:CC CC_REGNUM))]
4952 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4962 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4965 [(set (match_operand:DI 0 "s_operand" "")
4966 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4967 (clobber (reg:CC CC_REGNUM))]
4970 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4971 (clobber (reg:CC CC_REGNUM))])]
4972 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4975 ; iorsi3 instruction pattern(s).
4978 (define_insn "*iorsi3_cc"
4979 [(set (reg CC_REGNUM)
4980 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4981 (match_operand:SI 2 "general_operand" "d,R,T"))
4983 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4984 (ior:SI (match_dup 1) (match_dup 2)))]
4985 "s390_match_ccmode(insn, CCTmode)"
4990 [(set_attr "op_type" "RR,RX,RXY")])
4992 (define_insn "*iorsi3_cconly"
4993 [(set (reg CC_REGNUM)
4994 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4995 (match_operand:SI 2 "general_operand" "d,R,T"))
4997 (clobber (match_scratch:SI 0 "=d,d,d"))]
4998 "s390_match_ccmode(insn, CCTmode)"
5003 [(set_attr "op_type" "RR,RX,RXY")])
5005 (define_insn "*iorsi3_zarch"
5006 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5007 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5008 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5009 (clobber (reg:CC CC_REGNUM))]
5010 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5019 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5021 (define_insn "*iorsi3_esa"
5022 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5023 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5024 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5025 (clobber (reg:CC CC_REGNUM))]
5026 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5032 [(set_attr "op_type" "RR,RX,SI,SS")])
5035 [(set (match_operand:SI 0 "s_operand" "")
5036 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5037 (clobber (reg:CC CC_REGNUM))]
5040 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5041 (clobber (reg:CC CC_REGNUM))])]
5042 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5045 ; iorhi3 instruction pattern(s).
5048 (define_insn "*iorhi3_zarch"
5049 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5050 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5051 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5052 (clobber (reg:CC CC_REGNUM))]
5053 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5059 [(set_attr "op_type" "RR,RI,SI,SS")])
5061 (define_insn "*iorhi3_esa"
5062 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5063 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5064 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5065 (clobber (reg:CC CC_REGNUM))]
5066 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5071 [(set_attr "op_type" "RR,SI,SS")])
5074 [(set (match_operand:HI 0 "s_operand" "")
5075 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5076 (clobber (reg:CC CC_REGNUM))]
5079 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5080 (clobber (reg:CC CC_REGNUM))])]
5081 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5084 ; iorqi3 instruction pattern(s).
5087 (define_insn "*iorqi3_zarch"
5088 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5089 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5090 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5091 (clobber (reg:CC CC_REGNUM))]
5092 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5099 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5101 (define_insn "*iorqi3_esa"
5102 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5103 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5104 (match_operand:QI 2 "general_operand" "d,n,Q")))
5105 (clobber (reg:CC CC_REGNUM))]
5106 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5111 [(set_attr "op_type" "RR,SI,SS")])
5114 ; Block inclusive or (OC) patterns.
5118 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5119 (ior:BLK (match_dup 0)
5120 (match_operand:BLK 1 "memory_operand" "Q")))
5121 (use (match_operand 2 "const_int_operand" "n"))
5122 (clobber (reg:CC CC_REGNUM))]
5123 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5124 "oc\t%O0(%2,%R0),%S1"
5125 [(set_attr "op_type" "SS")])
5128 [(set (match_operand 0 "memory_operand" "")
5130 (match_operand 1 "memory_operand" "")))
5131 (clobber (reg:CC CC_REGNUM))]
5133 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5134 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5136 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5138 (clobber (reg:CC CC_REGNUM))])]
5140 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5141 operands[0] = adjust_address (operands[0], BLKmode, 0);
5142 operands[1] = adjust_address (operands[1], BLKmode, 0);
5147 [(set (match_operand:BLK 0 "memory_operand" "")
5148 (ior:BLK (match_dup 0)
5149 (match_operand:BLK 1 "memory_operand" "")))
5150 (use (match_operand 2 "const_int_operand" ""))
5151 (clobber (reg:CC CC_REGNUM))])
5153 [(set (match_operand:BLK 3 "memory_operand" "")
5154 (ior:BLK (match_dup 3)
5155 (match_operand:BLK 4 "memory_operand" "")))
5156 (use (match_operand 5 "const_int_operand" ""))
5157 (clobber (reg:CC CC_REGNUM))])]
5158 "s390_offset_p (operands[0], operands[3], operands[2])
5159 && s390_offset_p (operands[1], operands[4], operands[2])
5160 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5162 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5164 (clobber (reg:CC CC_REGNUM))])]
5165 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5166 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5167 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5171 ;;- Xor instructions.
5174 (define_expand "xor<mode>3"
5175 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5176 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5177 (match_operand:INT 2 "general_operand" "")))
5178 (clobber (reg:CC CC_REGNUM))]
5180 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5183 ; xordi3 instruction pattern(s).
5186 (define_insn "*xordi3_cc"
5187 [(set (reg CC_REGNUM)
5188 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5189 (match_operand:DI 2 "general_operand" "d,m"))
5191 (set (match_operand:DI 0 "register_operand" "=d,d")
5192 (xor:DI (match_dup 1) (match_dup 2)))]
5193 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5197 [(set_attr "op_type" "RRE,RXY")])
5199 (define_insn "*xordi3_cconly"
5200 [(set (reg CC_REGNUM)
5201 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5202 (match_operand:DI 2 "general_operand" "d,m"))
5204 (clobber (match_scratch:DI 0 "=d,d"))]
5205 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5209 [(set_attr "op_type" "RRE,RXY")])
5211 (define_insn "*xordi3"
5212 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5213 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5214 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5215 (clobber (reg:CC CC_REGNUM))]
5216 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5222 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5225 [(set (match_operand:DI 0 "s_operand" "")
5226 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5227 (clobber (reg:CC CC_REGNUM))]
5230 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5231 (clobber (reg:CC CC_REGNUM))])]
5232 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5235 ; xorsi3 instruction pattern(s).
5238 (define_insn "*xorsi3_cc"
5239 [(set (reg CC_REGNUM)
5240 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5241 (match_operand:SI 2 "general_operand" "d,R,T"))
5243 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5244 (xor:SI (match_dup 1) (match_dup 2)))]
5245 "s390_match_ccmode(insn, CCTmode)"
5250 [(set_attr "op_type" "RR,RX,RXY")])
5252 (define_insn "*xorsi3_cconly"
5253 [(set (reg CC_REGNUM)
5254 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5255 (match_operand:SI 2 "general_operand" "d,R,T"))
5257 (clobber (match_scratch:SI 0 "=d,d,d"))]
5258 "s390_match_ccmode(insn, CCTmode)"
5263 [(set_attr "op_type" "RR,RX,RXY")])
5265 (define_insn "*xorsi3"
5266 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5267 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5268 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5269 (clobber (reg:CC CC_REGNUM))]
5270 "s390_logical_operator_ok_p (operands)"
5277 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5280 [(set (match_operand:SI 0 "s_operand" "")
5281 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5282 (clobber (reg:CC CC_REGNUM))]
5285 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5286 (clobber (reg:CC CC_REGNUM))])]
5287 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5290 ; xorhi3 instruction pattern(s).
5293 (define_insn "*xorhi3"
5294 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5295 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5296 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5297 (clobber (reg:CC CC_REGNUM))]
5298 "s390_logical_operator_ok_p (operands)"
5303 [(set_attr "op_type" "RR,SI,SS")])
5306 [(set (match_operand:HI 0 "s_operand" "")
5307 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5308 (clobber (reg:CC CC_REGNUM))]
5311 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5312 (clobber (reg:CC CC_REGNUM))])]
5313 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5316 ; xorqi3 instruction pattern(s).
5319 (define_insn "*xorqi3"
5320 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5321 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5322 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5323 (clobber (reg:CC CC_REGNUM))]
5324 "s390_logical_operator_ok_p (operands)"
5330 [(set_attr "op_type" "RR,SI,SIY,SS")])
5333 ; Block exclusive or (XC) patterns.
5337 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5338 (xor:BLK (match_dup 0)
5339 (match_operand:BLK 1 "memory_operand" "Q")))
5340 (use (match_operand 2 "const_int_operand" "n"))
5341 (clobber (reg:CC CC_REGNUM))]
5342 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5343 "xc\t%O0(%2,%R0),%S1"
5344 [(set_attr "op_type" "SS")])
5347 [(set (match_operand 0 "memory_operand" "")
5349 (match_operand 1 "memory_operand" "")))
5350 (clobber (reg:CC CC_REGNUM))]
5352 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5353 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5355 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5357 (clobber (reg:CC CC_REGNUM))])]
5359 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5360 operands[0] = adjust_address (operands[0], BLKmode, 0);
5361 operands[1] = adjust_address (operands[1], BLKmode, 0);
5366 [(set (match_operand:BLK 0 "memory_operand" "")
5367 (xor:BLK (match_dup 0)
5368 (match_operand:BLK 1 "memory_operand" "")))
5369 (use (match_operand 2 "const_int_operand" ""))
5370 (clobber (reg:CC CC_REGNUM))])
5372 [(set (match_operand:BLK 3 "memory_operand" "")
5373 (xor:BLK (match_dup 3)
5374 (match_operand:BLK 4 "memory_operand" "")))
5375 (use (match_operand 5 "const_int_operand" ""))
5376 (clobber (reg:CC CC_REGNUM))])]
5377 "s390_offset_p (operands[0], operands[3], operands[2])
5378 && s390_offset_p (operands[1], operands[4], operands[2])
5379 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5381 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5383 (clobber (reg:CC CC_REGNUM))])]
5384 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5385 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5386 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5389 ; Block xor (XC) patterns with src == dest.
5392 (define_insn "*xc_zero"
5393 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5395 (use (match_operand 1 "const_int_operand" "n"))
5396 (clobber (reg:CC CC_REGNUM))]
5397 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5398 "xc\t%O0(%1,%R0),%S0"
5399 [(set_attr "op_type" "SS")])
5403 [(set (match_operand:BLK 0 "memory_operand" "")
5405 (use (match_operand 1 "const_int_operand" ""))
5406 (clobber (reg:CC CC_REGNUM))])
5408 [(set (match_operand:BLK 2 "memory_operand" "")
5410 (use (match_operand 3 "const_int_operand" ""))
5411 (clobber (reg:CC CC_REGNUM))])]
5412 "s390_offset_p (operands[0], operands[2], operands[1])
5413 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5415 [(set (match_dup 4) (const_int 0))
5417 (clobber (reg:CC CC_REGNUM))])]
5418 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5419 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5423 ;;- Negate instructions.
5427 ; neg(di|si)2 instruction pattern(s).
5430 (define_expand "neg<mode>2"
5432 [(set (match_operand:DSI 0 "register_operand" "=d")
5433 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5434 (clobber (reg:CC CC_REGNUM))])]
5438 (define_insn "*negdi2_sign_cc"
5439 [(set (reg CC_REGNUM)
5440 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5441 (match_operand:SI 1 "register_operand" "d") 0)
5442 (const_int 32)) (const_int 32)))
5444 (set (match_operand:DI 0 "register_operand" "=d")
5445 (neg:DI (sign_extend:DI (match_dup 1))))]
5446 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5448 [(set_attr "op_type" "RRE")])
5450 (define_insn "*negdi2_sign"
5451 [(set (match_operand:DI 0 "register_operand" "=d")
5452 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5453 (clobber (reg:CC CC_REGNUM))]
5456 [(set_attr "op_type" "RRE")])
5458 (define_insn "*neg<mode>2_cc"
5459 [(set (reg CC_REGNUM)
5460 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5462 (set (match_operand:GPR 0 "register_operand" "=d")
5463 (neg:GPR (match_dup 1)))]
5464 "s390_match_ccmode (insn, CCAmode)"
5466 [(set_attr "op_type" "RR<E>")])
5468 (define_insn "*neg<mode>2_cconly"
5469 [(set (reg CC_REGNUM)
5470 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5472 (clobber (match_scratch:GPR 0 "=d"))]
5473 "s390_match_ccmode (insn, CCAmode)"
5475 [(set_attr "op_type" "RR<E>")])
5477 (define_insn "*neg<mode>2"
5478 [(set (match_operand:GPR 0 "register_operand" "=d")
5479 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5480 (clobber (reg:CC CC_REGNUM))]
5483 [(set_attr "op_type" "RR<E>")])
5485 (define_insn_and_split "*negdi2_31"
5486 [(set (match_operand:DI 0 "register_operand" "=d")
5487 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5488 (clobber (reg:CC CC_REGNUM))]
5491 "&& reload_completed"
5493 [(set (match_dup 2) (neg:SI (match_dup 3)))
5494 (clobber (reg:CC CC_REGNUM))])
5496 [(set (reg:CCAP CC_REGNUM)
5497 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5498 (set (match_dup 4) (neg:SI (match_dup 5)))])
5500 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5502 (label_ref (match_dup 6))))
5504 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5505 (clobber (reg:CC CC_REGNUM))])
5507 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5508 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5509 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5510 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5511 operands[6] = gen_label_rtx ();")
5514 ; neg(df|sf)2 instruction pattern(s).
5517 (define_expand "neg<mode>2"
5519 [(set (match_operand:FPR 0 "register_operand" "=f")
5520 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5521 (clobber (reg:CC CC_REGNUM))])]
5525 (define_insn "*neg<mode>2_cc"
5526 [(set (reg CC_REGNUM)
5527 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5528 (match_operand:FPR 2 "const0_operand" "")))
5529 (set (match_operand:FPR 0 "register_operand" "=f")
5530 (neg:FPR (match_dup 1)))]
5531 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5533 [(set_attr "op_type" "RRE")
5534 (set_attr "type" "fsimp<mode>")])
5536 (define_insn "*neg<mode>2_cconly"
5537 [(set (reg CC_REGNUM)
5538 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5539 (match_operand:FPR 2 "const0_operand" "")))
5540 (clobber (match_scratch:FPR 0 "=f"))]
5541 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5543 [(set_attr "op_type" "RRE")
5544 (set_attr "type" "fsimp<mode>")])
5546 (define_insn "*neg<mode>2"
5547 [(set (match_operand:FPR 0 "register_operand" "=f")
5548 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5549 (clobber (reg:CC CC_REGNUM))]
5550 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5552 [(set_attr "op_type" "RRE")
5553 (set_attr "type" "fsimp<mode>")])
5555 (define_insn "*neg<mode>2_ibm"
5556 [(set (match_operand:FPR 0 "register_operand" "=f")
5557 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5558 (clobber (reg:CC CC_REGNUM))]
5559 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5561 [(set_attr "op_type" "RR")
5562 (set_attr "type" "fsimp<mode>")])
5566 ;;- Absolute value instructions.
5570 ; abs(di|si)2 instruction pattern(s).
5573 (define_insn "*absdi2_sign_cc"
5574 [(set (reg CC_REGNUM)
5575 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5576 (match_operand:SI 1 "register_operand" "d") 0)
5577 (const_int 32)) (const_int 32)))
5579 (set (match_operand:DI 0 "register_operand" "=d")
5580 (abs:DI (sign_extend:DI (match_dup 1))))]
5581 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5583 [(set_attr "op_type" "RRE")])
5585 (define_insn "*absdi2_sign"
5586 [(set (match_operand:DI 0 "register_operand" "=d")
5587 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5588 (clobber (reg:CC CC_REGNUM))]
5591 [(set_attr "op_type" "RRE")])
5593 (define_insn "*abs<mode>2_cc"
5594 [(set (reg CC_REGNUM)
5595 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5597 (set (match_operand:GPR 0 "register_operand" "=d")
5598 (abs:GPR (match_dup 1)))]
5599 "s390_match_ccmode (insn, CCAmode)"
5601 [(set_attr "op_type" "RR<E>")])
5603 (define_insn "*abs<mode>2_cconly"
5604 [(set (reg CC_REGNUM)
5605 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5607 (clobber (match_scratch:GPR 0 "=d"))]
5608 "s390_match_ccmode (insn, CCAmode)"
5610 [(set_attr "op_type" "RR<E>")])
5612 (define_insn "abs<mode>2"
5613 [(set (match_operand:GPR 0 "register_operand" "=d")
5614 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5615 (clobber (reg:CC CC_REGNUM))]
5618 [(set_attr "op_type" "RR<E>")])
5621 ; abs(df|sf)2 instruction pattern(s).
5624 (define_expand "abs<mode>2"
5626 [(set (match_operand:FPR 0 "register_operand" "=f")
5627 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5628 (clobber (reg:CC CC_REGNUM))])]
5632 (define_insn "*abs<mode>2_cc"
5633 [(set (reg CC_REGNUM)
5634 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5635 (match_operand:FPR 2 "const0_operand" "")))
5636 (set (match_operand:FPR 0 "register_operand" "=f")
5637 (abs:FPR (match_dup 1)))]
5638 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5640 [(set_attr "op_type" "RRE")
5641 (set_attr "type" "fsimp<mode>")])
5643 (define_insn "*abs<mode>2_cconly"
5644 [(set (reg CC_REGNUM)
5645 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5646 (match_operand:FPR 2 "const0_operand" "")))
5647 (clobber (match_scratch:FPR 0 "=f"))]
5648 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5650 [(set_attr "op_type" "RRE")
5651 (set_attr "type" "fsimp<mode>")])
5653 (define_insn "*abs<mode>2"
5654 [(set (match_operand:FPR 0 "register_operand" "=f")
5655 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5656 (clobber (reg:CC CC_REGNUM))]
5657 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5659 [(set_attr "op_type" "RRE")
5660 (set_attr "type" "fsimp<mode>")])
5662 (define_insn "*abs<mode>2_ibm"
5663 [(set (match_operand:FPR 0 "register_operand" "=f")
5664 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5665 (clobber (reg:CC CC_REGNUM))]
5666 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5668 [(set_attr "op_type" "RR")
5669 (set_attr "type" "fsimp<mode>")])
5672 ;;- Negated absolute value instructions
5679 (define_insn "*negabsdi2_sign_cc"
5680 [(set (reg CC_REGNUM)
5681 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5682 (match_operand:SI 1 "register_operand" "d") 0)
5683 (const_int 32)) (const_int 32))))
5685 (set (match_operand:DI 0 "register_operand" "=d")
5686 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5687 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5689 [(set_attr "op_type" "RRE")])
5691 (define_insn "*negabsdi2_sign"
5692 [(set (match_operand:DI 0 "register_operand" "=d")
5693 (neg:DI (abs:DI (sign_extend:DI
5694 (match_operand:SI 1 "register_operand" "d")))))
5695 (clobber (reg:CC CC_REGNUM))]
5698 [(set_attr "op_type" "RRE")])
5700 (define_insn "*negabs<mode>2_cc"
5701 [(set (reg CC_REGNUM)
5702 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5704 (set (match_operand:GPR 0 "register_operand" "=d")
5705 (neg:GPR (abs:GPR (match_dup 1))))]
5706 "s390_match_ccmode (insn, CCAmode)"
5708 [(set_attr "op_type" "RR<E>")])
5710 (define_insn "*negabs<mode>2_cconly"
5711 [(set (reg CC_REGNUM)
5712 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5714 (clobber (match_scratch:GPR 0 "=d"))]
5715 "s390_match_ccmode (insn, CCAmode)"
5717 [(set_attr "op_type" "RR<E>")])
5719 (define_insn "*negabs<mode>2"
5720 [(set (match_operand:GPR 0 "register_operand" "=d")
5721 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5722 (clobber (reg:CC CC_REGNUM))]
5725 [(set_attr "op_type" "RR<E>")])
5731 (define_insn "*negabs<mode>2_cc"
5732 [(set (reg CC_REGNUM)
5733 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5734 (match_operand:FPR 2 "const0_operand" "")))
5735 (set (match_operand:FPR 0 "register_operand" "=f")
5736 (neg:FPR (abs:FPR (match_dup 1))))]
5737 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5739 [(set_attr "op_type" "RRE")
5740 (set_attr "type" "fsimp<mode>")])
5742 (define_insn "*negabs<mode>2_cconly"
5743 [(set (reg CC_REGNUM)
5744 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5745 (match_operand:FPR 2 "const0_operand" "")))
5746 (clobber (match_scratch:FPR 0 "=f"))]
5747 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5749 [(set_attr "op_type" "RRE")
5750 (set_attr "type" "fsimp<mode>")])
5752 (define_insn "*negabs<mode>2"
5753 [(set (match_operand:FPR 0 "register_operand" "=f")
5754 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5755 (clobber (reg:CC CC_REGNUM))]
5756 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5758 [(set_attr "op_type" "RRE")
5759 (set_attr "type" "fsimp<mode>")])
5762 ;;- Square root instructions.
5766 ; sqrt(df|sf)2 instruction pattern(s).
5769 (define_insn "sqrt<mode>2"
5770 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5771 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5772 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5776 [(set_attr "op_type" "RRE,RXE")
5777 (set_attr "type" "fsqrt<mode>")])
5781 ;;- One complement instructions.
5785 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5788 (define_expand "one_cmpl<mode>2"
5790 [(set (match_operand:INT 0 "register_operand" "")
5791 (xor:INT (match_operand:INT 1 "register_operand" "")
5793 (clobber (reg:CC CC_REGNUM))])]
5799 ;;- Rotate instructions.
5803 ; rotl(di|si)3 instruction pattern(s).
5806 (define_insn "rotl<mode>3"
5807 [(set (match_operand:GPR 0 "register_operand" "=d")
5808 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5809 (match_operand:SI 2 "shift_count_operand" "Y")))]
5812 [(set_attr "op_type" "RSE")
5813 (set_attr "atype" "reg")])
5817 ;;- Shift instructions.
5821 ; (ashl|lshr)di3 instruction pattern(s).
5824 (define_expand "<shift>di3"
5825 [(set (match_operand:DI 0 "register_operand" "")
5826 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5827 (match_operand:SI 2 "shift_count_operand" "")))]
5831 (define_insn "*<shift>di3_31"
5832 [(set (match_operand:DI 0 "register_operand" "=d")
5833 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5834 (match_operand:SI 2 "shift_count_operand" "Y")))]
5837 [(set_attr "op_type" "RS")
5838 (set_attr "atype" "reg")])
5840 (define_insn "*<shift>di3_64"
5841 [(set (match_operand:DI 0 "register_operand" "=d")
5842 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5843 (match_operand:SI 2 "shift_count_operand" "Y")))]
5845 "s<lr>lg\t%0,%1,%Y2"
5846 [(set_attr "op_type" "RSE")
5847 (set_attr "atype" "reg")])
5850 ; ashrdi3 instruction pattern(s).
5853 (define_expand "ashrdi3"
5855 [(set (match_operand:DI 0 "register_operand" "")
5856 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5857 (match_operand:SI 2 "shift_count_operand" "")))
5858 (clobber (reg:CC CC_REGNUM))])]
5862 (define_insn "*ashrdi3_cc_31"
5863 [(set (reg CC_REGNUM)
5864 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5865 (match_operand:SI 2 "shift_count_operand" "Y"))
5867 (set (match_operand:DI 0 "register_operand" "=d")
5868 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5869 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5871 [(set_attr "op_type" "RS")
5872 (set_attr "atype" "reg")])
5874 (define_insn "*ashrdi3_cconly_31"
5875 [(set (reg CC_REGNUM)
5876 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5877 (match_operand:SI 2 "shift_count_operand" "Y"))
5879 (clobber (match_scratch:DI 0 "=d"))]
5880 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5882 [(set_attr "op_type" "RS")
5883 (set_attr "atype" "reg")])
5885 (define_insn "*ashrdi3_31"
5886 [(set (match_operand:DI 0 "register_operand" "=d")
5887 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5888 (match_operand:SI 2 "shift_count_operand" "Y")))
5889 (clobber (reg:CC CC_REGNUM))]
5892 [(set_attr "op_type" "RS")
5893 (set_attr "atype" "reg")])
5895 (define_insn "*ashrdi3_cc_64"
5896 [(set (reg CC_REGNUM)
5897 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5898 (match_operand:SI 2 "shift_count_operand" "Y"))
5900 (set (match_operand:DI 0 "register_operand" "=d")
5901 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5902 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5904 [(set_attr "op_type" "RSE")
5905 (set_attr "atype" "reg")])
5907 (define_insn "*ashrdi3_cconly_64"
5908 [(set (reg CC_REGNUM)
5909 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5910 (match_operand:SI 2 "shift_count_operand" "Y"))
5912 (clobber (match_scratch:DI 0 "=d"))]
5913 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5915 [(set_attr "op_type" "RSE")
5916 (set_attr "atype" "reg")])
5918 (define_insn "*ashrdi3_64"
5919 [(set (match_operand:DI 0 "register_operand" "=d")
5920 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5921 (match_operand:SI 2 "shift_count_operand" "Y")))
5922 (clobber (reg:CC CC_REGNUM))]
5925 [(set_attr "op_type" "RSE")
5926 (set_attr "atype" "reg")])
5930 ; (ashl|lshr)si3 instruction pattern(s).
5933 (define_insn "<shift>si3"
5934 [(set (match_operand:SI 0 "register_operand" "=d")
5935 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5936 (match_operand:SI 2 "shift_count_operand" "Y")))]
5939 [(set_attr "op_type" "RS")
5940 (set_attr "atype" "reg")])
5943 ; ashrsi3 instruction pattern(s).
5946 (define_insn "*ashrsi3_cc"
5947 [(set (reg CC_REGNUM)
5948 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5949 (match_operand:SI 2 "shift_count_operand" "Y"))
5951 (set (match_operand:SI 0 "register_operand" "=d")
5952 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5953 "s390_match_ccmode(insn, CCSmode)"
5955 [(set_attr "op_type" "RS")
5956 (set_attr "atype" "reg")])
5959 (define_insn "*ashrsi3_cconly"
5960 [(set (reg CC_REGNUM)
5961 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5962 (match_operand:SI 2 "shift_count_operand" "Y"))
5964 (clobber (match_scratch:SI 0 "=d"))]
5965 "s390_match_ccmode(insn, CCSmode)"
5967 [(set_attr "op_type" "RS")
5968 (set_attr "atype" "reg")])
5970 (define_insn "ashrsi3"
5971 [(set (match_operand:SI 0 "register_operand" "=d")
5972 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5973 (match_operand:SI 2 "shift_count_operand" "Y")))
5974 (clobber (reg:CC CC_REGNUM))]
5977 [(set_attr "op_type" "RS")
5978 (set_attr "atype" "reg")])
5982 ;; Branch instruction patterns.
5985 (define_expand "b<code>"
5987 (if_then_else (COMPARE (match_operand 0 "" "")
5992 "s390_emit_jump (operands[0],
5993 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5997 ;;- Conditional jump instructions.
6000 (define_insn "*cjump_64"
6003 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6004 (label_ref (match_operand 0 "" ""))
6008 if (get_attr_length (insn) == 4)
6011 return "jg%C1\t%l0";
6013 [(set_attr "op_type" "RI")
6014 (set_attr "type" "branch")
6015 (set (attr "length")
6016 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6017 (const_int 4) (const_int 6)))])
6019 (define_insn "*cjump_31"
6022 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6023 (label_ref (match_operand 0 "" ""))
6027 gcc_assert (get_attr_length (insn) == 4);
6030 [(set_attr "op_type" "RI")
6031 (set_attr "type" "branch")
6032 (set (attr "length")
6033 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6034 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6035 (const_int 4) (const_int 6))
6036 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6037 (const_int 4) (const_int 8))))])
6039 (define_insn "*cjump_long"
6042 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6043 (match_operand 0 "address_operand" "U")
6047 if (get_attr_op_type (insn) == OP_TYPE_RR)
6052 [(set (attr "op_type")
6053 (if_then_else (match_operand 0 "register_operand" "")
6054 (const_string "RR") (const_string "RX")))
6055 (set_attr "type" "branch")
6056 (set_attr "atype" "agen")])
6060 ;;- Negated conditional jump instructions.
6063 (define_insn "*icjump_64"
6066 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6068 (label_ref (match_operand 0 "" ""))))]
6071 if (get_attr_length (insn) == 4)
6074 return "jg%D1\t%l0";
6076 [(set_attr "op_type" "RI")
6077 (set_attr "type" "branch")
6078 (set (attr "length")
6079 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6080 (const_int 4) (const_int 6)))])
6082 (define_insn "*icjump_31"
6085 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6087 (label_ref (match_operand 0 "" ""))))]
6090 gcc_assert (get_attr_length (insn) == 4);
6093 [(set_attr "op_type" "RI")
6094 (set_attr "type" "branch")
6095 (set (attr "length")
6096 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6097 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6098 (const_int 4) (const_int 6))
6099 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6100 (const_int 4) (const_int 8))))])
6102 (define_insn "*icjump_long"
6105 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6107 (match_operand 0 "address_operand" "U")))]
6110 if (get_attr_op_type (insn) == OP_TYPE_RR)
6115 [(set (attr "op_type")
6116 (if_then_else (match_operand 0 "register_operand" "")
6117 (const_string "RR") (const_string "RX")))
6118 (set_attr "type" "branch")
6119 (set_attr "atype" "agen")])
6122 ;;- Trap instructions.
6126 [(trap_if (const_int 1) (const_int 0))]
6129 [(set_attr "op_type" "RI")
6130 (set_attr "type" "branch")])
6132 (define_expand "conditional_trap"
6133 [(trap_if (match_operand 0 "comparison_operator" "")
6134 (match_operand 1 "general_operand" ""))]
6137 if (operands[1] != const0_rtx) FAIL;
6138 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6139 s390_compare_op0, s390_compare_op1);
6142 (define_insn "*trap"
6143 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6147 [(set_attr "op_type" "RI")
6148 (set_attr "type" "branch")])
6151 ;;- Loop instructions.
6153 ;; This is all complicated by the fact that since this is a jump insn
6154 ;; we must handle our own output reloads.
6156 (define_expand "doloop_end"
6157 [(use (match_operand 0 "" "")) ; loop pseudo
6158 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6159 (use (match_operand 2 "" "")) ; max iterations
6160 (use (match_operand 3 "" "")) ; loop level
6161 (use (match_operand 4 "" ""))] ; label
6164 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6165 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6166 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6167 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6168 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6169 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6176 (define_insn_and_split "doloop_si64"
6179 (ne (match_operand:SI 1 "register_operand" "d,d")
6181 (label_ref (match_operand 0 "" ""))
6183 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6184 (plus:SI (match_dup 1) (const_int -1)))
6185 (clobber (match_scratch:SI 3 "=X,&1"))
6186 (clobber (reg:CC CC_REGNUM))]
6189 if (which_alternative != 0)
6191 else if (get_attr_length (insn) == 4)
6192 return "brct\t%1,%l0";
6194 return "ahi\t%1,-1\;jgne\t%l0";
6196 "&& reload_completed
6197 && (! REG_P (operands[2])
6198 || ! rtx_equal_p (operands[1], operands[2]))"
6199 [(parallel [(set (reg:CCAN CC_REGNUM)
6200 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6202 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6203 (set (match_dup 2) (match_dup 3))
6204 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6205 (label_ref (match_dup 0))
6208 [(set_attr "op_type" "RI")
6209 (set_attr "type" "branch")
6210 (set (attr "length")
6211 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6212 (const_int 4) (const_int 10)))])
6214 (define_insn_and_split "doloop_si31"
6217 (ne (match_operand:SI 1 "register_operand" "d,d")
6219 (label_ref (match_operand 0 "" ""))
6221 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6222 (plus:SI (match_dup 1) (const_int -1)))
6223 (clobber (match_scratch:SI 3 "=X,&1"))
6224 (clobber (reg:CC CC_REGNUM))]
6227 if (which_alternative != 0)
6229 else if (get_attr_length (insn) == 4)
6230 return "brct\t%1,%l0";
6234 "&& reload_completed
6235 && (! REG_P (operands[2])
6236 || ! rtx_equal_p (operands[1], operands[2]))"
6237 [(parallel [(set (reg:CCAN CC_REGNUM)
6238 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6240 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6241 (set (match_dup 2) (match_dup 3))
6242 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6243 (label_ref (match_dup 0))
6246 [(set_attr "op_type" "RI")
6247 (set_attr "type" "branch")
6248 (set (attr "length")
6249 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6250 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6251 (const_int 4) (const_int 6))
6252 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6253 (const_int 4) (const_int 8))))])
6255 (define_insn "*doloop_si_long"
6258 (ne (match_operand:SI 1 "register_operand" "d,d")
6260 (match_operand 0 "address_operand" "U,U")
6262 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6263 (plus:SI (match_dup 1) (const_int -1)))
6264 (clobber (match_scratch:SI 3 "=X,&1"))
6265 (clobber (reg:CC CC_REGNUM))]
6268 if (get_attr_op_type (insn) == OP_TYPE_RR)
6269 return "bctr\t%1,%0";
6271 return "bct\t%1,%a0";
6273 [(set (attr "op_type")
6274 (if_then_else (match_operand 0 "register_operand" "")
6275 (const_string "RR") (const_string "RX")))
6276 (set_attr "type" "branch")
6277 (set_attr "atype" "agen")])
6279 (define_insn_and_split "doloop_di"
6282 (ne (match_operand:DI 1 "register_operand" "d,d")
6284 (label_ref (match_operand 0 "" ""))
6286 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6287 (plus:DI (match_dup 1) (const_int -1)))
6288 (clobber (match_scratch:DI 3 "=X,&1"))
6289 (clobber (reg:CC CC_REGNUM))]
6292 if (which_alternative != 0)
6294 else if (get_attr_length (insn) == 4)
6295 return "brctg\t%1,%l0";
6297 return "aghi\t%1,-1\;jgne\t%l0";
6299 "&& reload_completed
6300 && (! REG_P (operands[2])
6301 || ! rtx_equal_p (operands[1], operands[2]))"
6302 [(parallel [(set (reg:CCAN CC_REGNUM)
6303 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6305 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6306 (set (match_dup 2) (match_dup 3))
6307 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6308 (label_ref (match_dup 0))
6311 [(set_attr "op_type" "RI")
6312 (set_attr "type" "branch")
6313 (set (attr "length")
6314 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6315 (const_int 4) (const_int 10)))])
6318 ;;- Unconditional jump instructions.
6322 ; jump instruction pattern(s).
6325 (define_expand "jump"
6326 [(match_operand 0 "" "")]
6328 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6330 (define_insn "*jump64"
6331 [(set (pc) (label_ref (match_operand 0 "" "")))]
6334 if (get_attr_length (insn) == 4)
6339 [(set_attr "op_type" "RI")
6340 (set_attr "type" "branch")
6341 (set (attr "length")
6342 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6343 (const_int 4) (const_int 6)))])
6345 (define_insn "*jump31"
6346 [(set (pc) (label_ref (match_operand 0 "" "")))]
6349 gcc_assert (get_attr_length (insn) == 4);
6352 [(set_attr "op_type" "RI")
6353 (set_attr "type" "branch")
6354 (set (attr "length")
6355 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6356 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6357 (const_int 4) (const_int 6))
6358 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6359 (const_int 4) (const_int 8))))])
6362 ; indirect-jump instruction pattern(s).
6365 (define_insn "indirect_jump"
6366 [(set (pc) (match_operand 0 "address_operand" "U"))]
6369 if (get_attr_op_type (insn) == OP_TYPE_RR)
6374 [(set (attr "op_type")
6375 (if_then_else (match_operand 0 "register_operand" "")
6376 (const_string "RR") (const_string "RX")))
6377 (set_attr "type" "branch")
6378 (set_attr "atype" "agen")])
6381 ; casesi instruction pattern(s).
6384 (define_insn "casesi_jump"
6385 [(set (pc) (match_operand 0 "address_operand" "U"))
6386 (use (label_ref (match_operand 1 "" "")))]
6389 if (get_attr_op_type (insn) == OP_TYPE_RR)
6394 [(set (attr "op_type")
6395 (if_then_else (match_operand 0 "register_operand" "")
6396 (const_string "RR") (const_string "RX")))
6397 (set_attr "type" "branch")
6398 (set_attr "atype" "agen")])
6400 (define_expand "casesi"
6401 [(match_operand:SI 0 "general_operand" "")
6402 (match_operand:SI 1 "general_operand" "")
6403 (match_operand:SI 2 "general_operand" "")
6404 (label_ref (match_operand 3 "" ""))
6405 (label_ref (match_operand 4 "" ""))]
6408 rtx index = gen_reg_rtx (SImode);
6409 rtx base = gen_reg_rtx (Pmode);
6410 rtx target = gen_reg_rtx (Pmode);
6412 emit_move_insn (index, operands[0]);
6413 emit_insn (gen_subsi3 (index, index, operands[1]));
6414 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6417 if (Pmode != SImode)
6418 index = convert_to_mode (Pmode, index, 1);
6419 if (GET_CODE (index) != REG)
6420 index = copy_to_mode_reg (Pmode, index);
6423 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6425 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6427 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6429 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6430 emit_move_insn (target, index);
6433 target = gen_rtx_PLUS (Pmode, base, target);
6434 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6441 ;;- Jump to subroutine.
6446 ; untyped call instruction pattern(s).
6449 ;; Call subroutine returning any type.
6450 (define_expand "untyped_call"
6451 [(parallel [(call (match_operand 0 "" "")
6453 (match_operand 1 "" "")
6454 (match_operand 2 "" "")])]
6459 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6461 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6463 rtx set = XVECEXP (operands[2], 0, i);
6464 emit_move_insn (SET_DEST (set), SET_SRC (set));
6467 /* The optimizer does not know that the call sets the function value
6468 registers we stored in the result block. We avoid problems by
6469 claiming that all hard registers are used and clobbered at this
6471 emit_insn (gen_blockage ());
6476 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6477 ;; all of memory. This blocks insns from being moved across this point.
6479 (define_insn "blockage"
6480 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6483 [(set_attr "type" "none")
6484 (set_attr "length" "0")])
6490 (define_expand "sibcall"
6491 [(call (match_operand 0 "" "")
6492 (match_operand 1 "" ""))]
6495 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6499 (define_insn "*sibcall_br"
6500 [(call (mem:QI (reg SIBCALL_REGNUM))
6501 (match_operand 0 "const_int_operand" "n"))]
6502 "SIBLING_CALL_P (insn)
6503 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6505 [(set_attr "op_type" "RR")
6506 (set_attr "type" "branch")
6507 (set_attr "atype" "agen")])
6509 (define_insn "*sibcall_brc"
6510 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6511 (match_operand 1 "const_int_operand" "n"))]
6512 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6514 [(set_attr "op_type" "RI")
6515 (set_attr "type" "branch")])
6517 (define_insn "*sibcall_brcl"
6518 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6519 (match_operand 1 "const_int_operand" "n"))]
6520 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6522 [(set_attr "op_type" "RIL")
6523 (set_attr "type" "branch")])
6526 ; sibcall_value patterns
6529 (define_expand "sibcall_value"
6530 [(set (match_operand 0 "" "")
6531 (call (match_operand 1 "" "")
6532 (match_operand 2 "" "")))]
6535 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6539 (define_insn "*sibcall_value_br"
6540 [(set (match_operand 0 "" "")
6541 (call (mem:QI (reg SIBCALL_REGNUM))
6542 (match_operand 1 "const_int_operand" "n")))]
6543 "SIBLING_CALL_P (insn)
6544 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6546 [(set_attr "op_type" "RR")
6547 (set_attr "type" "branch")
6548 (set_attr "atype" "agen")])
6550 (define_insn "*sibcall_value_brc"
6551 [(set (match_operand 0 "" "")
6552 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6553 (match_operand 2 "const_int_operand" "n")))]
6554 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6556 [(set_attr "op_type" "RI")
6557 (set_attr "type" "branch")])
6559 (define_insn "*sibcall_value_brcl"
6560 [(set (match_operand 0 "" "")
6561 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6562 (match_operand 2 "const_int_operand" "n")))]
6563 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6565 [(set_attr "op_type" "RIL")
6566 (set_attr "type" "branch")])
6570 ; call instruction pattern(s).
6573 (define_expand "call"
6574 [(call (match_operand 0 "" "")
6575 (match_operand 1 "" ""))
6576 (use (match_operand 2 "" ""))]
6579 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6580 gen_rtx_REG (Pmode, RETURN_REGNUM));
6584 (define_insn "*bras"
6585 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6586 (match_operand 1 "const_int_operand" "n"))
6587 (clobber (match_operand 2 "register_operand" "=r"))]
6588 "!SIBLING_CALL_P (insn)
6589 && TARGET_SMALL_EXEC
6590 && GET_MODE (operands[2]) == Pmode"
6592 [(set_attr "op_type" "RI")
6593 (set_attr "type" "jsr")])
6595 (define_insn "*brasl"
6596 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6597 (match_operand 1 "const_int_operand" "n"))
6598 (clobber (match_operand 2 "register_operand" "=r"))]
6599 "!SIBLING_CALL_P (insn)
6601 && GET_MODE (operands[2]) == Pmode"
6603 [(set_attr "op_type" "RIL")
6604 (set_attr "type" "jsr")])
6606 (define_insn "*basr"
6607 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6608 (match_operand 1 "const_int_operand" "n"))
6609 (clobber (match_operand 2 "register_operand" "=r"))]
6610 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6612 if (get_attr_op_type (insn) == OP_TYPE_RR)
6613 return "basr\t%2,%0";
6615 return "bas\t%2,%a0";
6617 [(set (attr "op_type")
6618 (if_then_else (match_operand 0 "register_operand" "")
6619 (const_string "RR") (const_string "RX")))
6620 (set_attr "type" "jsr")
6621 (set_attr "atype" "agen")])
6624 ; call_value instruction pattern(s).
6627 (define_expand "call_value"
6628 [(set (match_operand 0 "" "")
6629 (call (match_operand 1 "" "")
6630 (match_operand 2 "" "")))
6631 (use (match_operand 3 "" ""))]
6634 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6635 gen_rtx_REG (Pmode, RETURN_REGNUM));
6639 (define_insn "*bras_r"
6640 [(set (match_operand 0 "" "")
6641 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6642 (match_operand:SI 2 "const_int_operand" "n")))
6643 (clobber (match_operand 3 "register_operand" "=r"))]
6644 "!SIBLING_CALL_P (insn)
6645 && TARGET_SMALL_EXEC
6646 && GET_MODE (operands[3]) == Pmode"
6648 [(set_attr "op_type" "RI")
6649 (set_attr "type" "jsr")])
6651 (define_insn "*brasl_r"
6652 [(set (match_operand 0 "" "")
6653 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6654 (match_operand 2 "const_int_operand" "n")))
6655 (clobber (match_operand 3 "register_operand" "=r"))]
6656 "!SIBLING_CALL_P (insn)
6658 && GET_MODE (operands[3]) == Pmode"
6660 [(set_attr "op_type" "RIL")
6661 (set_attr "type" "jsr")])
6663 (define_insn "*basr_r"
6664 [(set (match_operand 0 "" "")
6665 (call (mem:QI (match_operand 1 "address_operand" "U"))
6666 (match_operand 2 "const_int_operand" "n")))
6667 (clobber (match_operand 3 "register_operand" "=r"))]
6668 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6670 if (get_attr_op_type (insn) == OP_TYPE_RR)
6671 return "basr\t%3,%1";
6673 return "bas\t%3,%a1";
6675 [(set (attr "op_type")
6676 (if_then_else (match_operand 1 "register_operand" "")
6677 (const_string "RR") (const_string "RX")))
6678 (set_attr "type" "jsr")
6679 (set_attr "atype" "agen")])
6682 ;;- Thread-local storage support.
6685 (define_expand "get_tp_64"
6686 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6690 (define_expand "get_tp_31"
6691 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6695 (define_expand "set_tp_64"
6696 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6697 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6701 (define_expand "set_tp_31"
6702 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6703 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6707 (define_insn "*set_tp"
6708 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6711 [(set_attr "type" "none")
6712 (set_attr "length" "0")])
6714 (define_insn "*tls_load_64"
6715 [(set (match_operand:DI 0 "register_operand" "=d")
6716 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6717 (match_operand:DI 2 "" "")]
6721 [(set_attr "op_type" "RXE")])
6723 (define_insn "*tls_load_31"
6724 [(set (match_operand:SI 0 "register_operand" "=d,d")
6725 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6726 (match_operand:SI 2 "" "")]
6732 [(set_attr "op_type" "RX,RXY")])
6734 (define_insn "*bras_tls"
6735 [(set (match_operand 0 "" "")
6736 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6737 (match_operand 2 "const_int_operand" "n")))
6738 (clobber (match_operand 3 "register_operand" "=r"))
6739 (use (match_operand 4 "" ""))]
6740 "!SIBLING_CALL_P (insn)
6741 && TARGET_SMALL_EXEC
6742 && GET_MODE (operands[3]) == Pmode"
6744 [(set_attr "op_type" "RI")
6745 (set_attr "type" "jsr")])
6747 (define_insn "*brasl_tls"
6748 [(set (match_operand 0 "" "")
6749 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6750 (match_operand 2 "const_int_operand" "n")))
6751 (clobber (match_operand 3 "register_operand" "=r"))
6752 (use (match_operand 4 "" ""))]
6753 "!SIBLING_CALL_P (insn)
6755 && GET_MODE (operands[3]) == Pmode"
6757 [(set_attr "op_type" "RIL")
6758 (set_attr "type" "jsr")])
6760 (define_insn "*basr_tls"
6761 [(set (match_operand 0 "" "")
6762 (call (mem:QI (match_operand 1 "address_operand" "U"))
6763 (match_operand 2 "const_int_operand" "n")))
6764 (clobber (match_operand 3 "register_operand" "=r"))
6765 (use (match_operand 4 "" ""))]
6766 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6768 if (get_attr_op_type (insn) == OP_TYPE_RR)
6769 return "basr\t%3,%1%J4";
6771 return "bas\t%3,%a1%J4";
6773 [(set (attr "op_type")
6774 (if_then_else (match_operand 1 "register_operand" "")
6775 (const_string "RR") (const_string "RX")))
6776 (set_attr "type" "jsr")
6777 (set_attr "atype" "agen")])
6780 ;;- Atomic operations
6784 ; memory barrier pattern.
6787 (define_expand "memory_barrier"
6788 [(set (mem:BLK (match_dup 0))
6789 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
6792 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
6793 MEM_VOLATILE_P (operands[0]) = 1;
6796 (define_insn "*memory_barrier"
6797 [(set (match_operand:BLK 0 "" "")
6798 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
6801 [(set_attr "op_type" "RR")])
6804 ; compare and swap patterns.
6807 (define_insn "sync_compare_and_swap<mode>"
6808 [(set (match_operand:GPR 0 "register_operand" "=r")
6809 (match_operand:GPR 1 "memory_operand" "+Q"))
6811 (unspec_volatile:GPR
6813 (match_operand:GPR 2 "register_operand" "0")
6814 (match_operand:GPR 3 "register_operand" "r")]
6816 (clobber (reg:CC CC_REGNUM))]
6819 [(set_attr "op_type" "RS<E>")
6820 (set_attr "type" "sem")])
6822 (define_expand "sync_compare_and_swap_cc<mode>"
6824 [(set (match_operand:GPR 0 "register_operand" "")
6825 (match_operand:GPR 1 "memory_operand" ""))
6827 (unspec_volatile:GPR
6829 (match_operand:GPR 2 "register_operand" "")
6830 (match_operand:GPR 3 "register_operand" "")]
6833 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
6836 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
6837 s390_compare_op0 = operands[1];
6838 s390_compare_op1 = operands[2];
6839 s390_compare_emitted = operands[4];
6842 (define_insn "*sync_compare_and_swap_cc<mode>"
6843 [(set (match_operand:GPR 0 "register_operand" "=r")
6844 (match_operand:GPR 1 "memory_operand" "+Q"))
6846 (unspec_volatile:GPR
6848 (match_operand:GPR 2 "register_operand" "0")
6849 (match_operand:GPR 3 "register_operand" "r")]
6851 (set (reg:CCZ1 CC_REGNUM)
6852 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
6855 [(set_attr "op_type" "RS<E>")
6856 (set_attr "type" "sem")])
6860 ;;- Miscellaneous instructions.
6864 ; allocate stack instruction pattern(s).
6867 (define_expand "allocate_stack"
6868 [(match_operand 0 "general_operand" "")
6869 (match_operand 1 "general_operand" "")]
6872 rtx temp = gen_reg_rtx (Pmode);
6874 emit_move_insn (temp, s390_back_chain_rtx ());
6875 anti_adjust_stack (operands[1]);
6876 emit_move_insn (s390_back_chain_rtx (), temp);
6878 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6884 ; setjmp instruction pattern.
6887 (define_expand "builtin_setjmp_receiver"
6888 [(match_operand 0 "" "")]
6891 emit_insn (s390_load_got ());
6892 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6896 ;; These patterns say how to save and restore the stack pointer. We need not
6897 ;; save the stack pointer at function level since we are careful to
6898 ;; preserve the backchain. At block level, we have to restore the backchain
6899 ;; when we restore the stack pointer.
6901 ;; For nonlocal gotos, we must save both the stack pointer and its
6902 ;; backchain and restore both. Note that in the nonlocal case, the
6903 ;; save area is a memory location.
6905 (define_expand "save_stack_function"
6906 [(match_operand 0 "general_operand" "")
6907 (match_operand 1 "general_operand" "")]
6911 (define_expand "restore_stack_function"
6912 [(match_operand 0 "general_operand" "")
6913 (match_operand 1 "general_operand" "")]
6917 (define_expand "restore_stack_block"
6918 [(match_operand 0 "register_operand" "")
6919 (match_operand 1 "register_operand" "")]
6922 rtx temp = gen_reg_rtx (Pmode);
6924 emit_move_insn (temp, s390_back_chain_rtx ());
6925 emit_move_insn (operands[0], operands[1]);
6926 emit_move_insn (s390_back_chain_rtx (), temp);
6931 (define_expand "save_stack_nonlocal"
6932 [(match_operand 0 "memory_operand" "")
6933 (match_operand 1 "register_operand" "")]
6936 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6937 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6939 /* Copy the backchain to the first word, sp to the second and the
6940 literal pool base to the third. */
6942 if (TARGET_BACKCHAIN)
6944 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6945 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6948 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6949 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6954 (define_expand "restore_stack_nonlocal"
6955 [(match_operand 0 "register_operand" "")
6956 (match_operand 1 "memory_operand" "")]
6959 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6960 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6961 rtx temp = NULL_RTX;
6963 /* Restore the backchain from the first word, sp from the second and the
6964 literal pool base from the third. */
6966 if (TARGET_BACKCHAIN)
6967 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6969 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6970 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6973 emit_move_insn (s390_back_chain_rtx (), temp);
6975 emit_insn (gen_rtx_USE (VOIDmode, base));
6979 (define_expand "exception_receiver"
6983 s390_set_has_landing_pad_p (true);
6988 ; nop instruction pattern(s).
6995 [(set_attr "op_type" "RR")])
6999 ; Special literal pool access instruction pattern(s).
7002 (define_insn "*pool_entry"
7003 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7004 UNSPECV_POOL_ENTRY)]
7007 enum machine_mode mode = GET_MODE (PATTERN (insn));
7008 unsigned int align = GET_MODE_BITSIZE (mode);
7009 s390_output_pool_entry (operands[0], mode, align);
7012 [(set (attr "length")
7013 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7015 (define_insn "pool_align"
7016 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7017 UNSPECV_POOL_ALIGN)]
7020 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7022 (define_insn "pool_section_start"
7023 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7026 [(set_attr "length" "0")])
7028 (define_insn "pool_section_end"
7029 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7032 [(set_attr "length" "0")])
7034 (define_insn "main_base_31_small"
7035 [(set (match_operand 0 "register_operand" "=a")
7036 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7037 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7039 [(set_attr "op_type" "RR")
7040 (set_attr "type" "la")])
7042 (define_insn "main_base_31_large"
7043 [(set (match_operand 0 "register_operand" "=a")
7044 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7045 (set (pc) (label_ref (match_operand 2 "" "")))]
7046 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7048 [(set_attr "op_type" "RI")])
7050 (define_insn "main_base_64"
7051 [(set (match_operand 0 "register_operand" "=a")
7052 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7053 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7055 [(set_attr "op_type" "RIL")
7056 (set_attr "type" "larl")])
7058 (define_insn "main_pool"
7059 [(set (match_operand 0 "register_operand" "=a")
7060 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7061 "GET_MODE (operands[0]) == Pmode"
7066 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7067 (const_string "larl") (const_string "la")))])
7069 (define_insn "reload_base_31"
7070 [(set (match_operand 0 "register_operand" "=a")
7071 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7072 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7073 "basr\t%0,0\;la\t%0,%1-.(%0)"
7074 [(set_attr "length" "6")
7075 (set_attr "type" "la")])
7077 (define_insn "reload_base_64"
7078 [(set (match_operand 0 "register_operand" "=a")
7079 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7080 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7082 [(set_attr "op_type" "RIL")
7083 (set_attr "type" "larl")])
7086 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7091 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7094 ;; Insns related to generating the function prologue and epilogue.
7098 (define_expand "prologue"
7099 [(use (const_int 0))]
7101 "s390_emit_prologue (); DONE;")
7103 (define_expand "epilogue"
7104 [(use (const_int 1))]
7106 "s390_emit_epilogue (false); DONE;")
7108 (define_expand "sibcall_epilogue"
7109 [(use (const_int 0))]
7111 "s390_emit_epilogue (true); DONE;")
7113 (define_insn "*return"
7115 (use (match_operand 0 "register_operand" "a"))]
7116 "GET_MODE (operands[0]) == Pmode"
7118 [(set_attr "op_type" "RR")
7119 (set_attr "type" "jsr")
7120 (set_attr "atype" "agen")])
7123 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7124 ;; pointer. This is used for compatibility.
7126 (define_expand "ptr_extend"
7127 [(set (match_operand:DI 0 "register_operand" "=r")
7128 (match_operand:SI 1 "register_operand" "r"))]
7131 emit_insn (gen_anddi3 (operands[0],
7132 gen_lowpart (DImode, operands[1]),
7133 GEN_INT (0x7fffffff)));
7137 ;; Instruction definition to expand eh_return macro to support
7138 ;; swapping in special linkage return addresses.
7140 (define_expand "eh_return"
7141 [(use (match_operand 0 "register_operand" ""))]
7144 s390_emit_tpf_eh_return (operands[0]);