1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
53 #include "tree-gimple.h"
56 /* Define the specific costs for a given cpu. */
58 struct processor_costs
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
75 const int sqdbr; /* cost of square root in DFmode. */
76 const int sqebr; /* cost of square root in SFmode. */
77 /* multiply and add */
78 const int madbr; /* cost of multiply and add in DFmode. */
79 const int maebr; /* cost of multiply and add in SFmode. */
92 const struct processor_costs *s390_cost;
95 struct processor_costs z900_cost =
97 COSTS_N_INSNS (5), /* M */
98 COSTS_N_INSNS (10), /* MGHI */
99 COSTS_N_INSNS (5), /* MH */
100 COSTS_N_INSNS (4), /* MHI */
101 COSTS_N_INSNS (5), /* ML */
102 COSTS_N_INSNS (5), /* MR */
103 COSTS_N_INSNS (4), /* MS */
104 COSTS_N_INSNS (15), /* MSG */
105 COSTS_N_INSNS (7), /* MSGF */
106 COSTS_N_INSNS (7), /* MSGFR */
107 COSTS_N_INSNS (10), /* MSGR */
108 COSTS_N_INSNS (4), /* MSR */
109 COSTS_N_INSNS (7), /* multiplication in DFmode */
110 COSTS_N_INSNS (44), /* SQDBR */
111 COSTS_N_INSNS (35), /* SQEBR */
112 COSTS_N_INSNS (18), /* MADBR */
113 COSTS_N_INSNS (13), /* MAEBR */
114 COSTS_N_INSNS (30), /* DDBR */
115 COSTS_N_INSNS (30), /* DDR */
116 COSTS_N_INSNS (27), /* DEBR */
117 COSTS_N_INSNS (26), /* DER */
118 COSTS_N_INSNS (220), /* DLGR */
119 COSTS_N_INSNS (34), /* DLR */
120 COSTS_N_INSNS (34), /* DR */
121 COSTS_N_INSNS (32), /* DSGFR */
122 COSTS_N_INSNS (32), /* DSGR */
126 struct processor_costs z990_cost =
128 COSTS_N_INSNS (4), /* M */
129 COSTS_N_INSNS (2), /* MGHI */
130 COSTS_N_INSNS (2), /* MH */
131 COSTS_N_INSNS (2), /* MHI */
132 COSTS_N_INSNS (4), /* ML */
133 COSTS_N_INSNS (4), /* MR */
134 COSTS_N_INSNS (5), /* MS */
135 COSTS_N_INSNS (6), /* MSG */
136 COSTS_N_INSNS (4), /* MSGF */
137 COSTS_N_INSNS (4), /* MSGFR */
138 COSTS_N_INSNS (4), /* MSGR */
139 COSTS_N_INSNS (4), /* MSR */
140 COSTS_N_INSNS (1), /* multiplication in DFmode */
141 COSTS_N_INSNS (66), /* SQDBR */
142 COSTS_N_INSNS (38), /* SQEBR */
143 COSTS_N_INSNS (1), /* MADBR */
144 COSTS_N_INSNS (1), /* MAEBR */
145 COSTS_N_INSNS (40), /* DDBR */
146 COSTS_N_INSNS (44), /* DDR */
147 COSTS_N_INSNS (26), /* DDBR */
148 COSTS_N_INSNS (28), /* DER */
149 COSTS_N_INSNS (176), /* DLGR */
150 COSTS_N_INSNS (31), /* DLR */
151 COSTS_N_INSNS (31), /* DR */
152 COSTS_N_INSNS (31), /* DSGFR */
153 COSTS_N_INSNS (31), /* DSGR */
157 struct processor_costs z9_109_cost =
159 COSTS_N_INSNS (4), /* M */
160 COSTS_N_INSNS (2), /* MGHI */
161 COSTS_N_INSNS (2), /* MH */
162 COSTS_N_INSNS (2), /* MHI */
163 COSTS_N_INSNS (4), /* ML */
164 COSTS_N_INSNS (4), /* MR */
165 COSTS_N_INSNS (5), /* MS */
166 COSTS_N_INSNS (6), /* MSG */
167 COSTS_N_INSNS (4), /* MSGF */
168 COSTS_N_INSNS (4), /* MSGFR */
169 COSTS_N_INSNS (4), /* MSGR */
170 COSTS_N_INSNS (4), /* MSR */
171 COSTS_N_INSNS (1), /* multiplication in DFmode */
172 COSTS_N_INSNS (66), /* SQDBR */
173 COSTS_N_INSNS (38), /* SQEBR */
174 COSTS_N_INSNS (1), /* MADBR */
175 COSTS_N_INSNS (1), /* MAEBR */
176 COSTS_N_INSNS (40), /* DDBR */
177 COSTS_N_INSNS (37), /* DDR */
178 COSTS_N_INSNS (26), /* DDBR */
179 COSTS_N_INSNS (28), /* DER */
180 COSTS_N_INSNS (30), /* DLGR */
181 COSTS_N_INSNS (23), /* DLR */
182 COSTS_N_INSNS (23), /* DR */
183 COSTS_N_INSNS (24), /* DSGFR */
184 COSTS_N_INSNS (24), /* DSGR */
187 extern int reload_completed;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx s390_compare_op0, s390_compare_op1;
193 /* Save the result of a compare_and_swap until the branch or scc is
195 rtx s390_compare_emitted = NULL_RTX;
197 /* Structure used to hold the components of a S/390 memory
198 address. A legitimate address on S/390 is of the general
200 base + index + displacement
201 where any of the components is optional.
203 base and index are registers of the class ADDR_REGS,
204 displacement is an unsigned 12-bit immediate constant. */
214 /* Which cpu are we tuning for. */
215 enum processor_type s390_tune = PROCESSOR_max;
216 enum processor_flags s390_tune_flags;
217 /* Which instruction set architecture to use. */
218 enum processor_type s390_arch;
219 enum processor_flags s390_arch_flags;
221 HOST_WIDE_INT s390_warn_framesize = 0;
222 HOST_WIDE_INT s390_stack_size = 0;
223 HOST_WIDE_INT s390_stack_guard = 0;
225 /* The following structure is embedded in the machine
226 specific part of struct function. */
228 struct s390_frame_layout GTY (())
230 /* Offset within stack frame. */
231 HOST_WIDE_INT gprs_offset;
232 HOST_WIDE_INT f0_offset;
233 HOST_WIDE_INT f4_offset;
234 HOST_WIDE_INT f8_offset;
235 HOST_WIDE_INT backchain_offset;
237 /* Number of first and last gpr to be saved, restored. */
239 int first_restore_gpr;
241 int last_restore_gpr;
243 /* Bits standing for floating point registers. Set, if the
244 respective register has to be saved. Starting with reg 16 (f0)
245 at the rightmost bit.
246 Bit 15 - 8 7 6 5 4 3 2 1 0
247 fpr 15 - 8 7 5 3 1 6 4 2 0
248 reg 31 - 24 23 22 21 20 19 18 17 16 */
249 unsigned int fpr_bitmap;
251 /* Number of floating point registers f8-f15 which must be saved. */
254 /* Set if return address needs to be saved.
255 This flag is set by s390_return_addr_rtx if it could not use
256 the initial value of r14 and therefore depends on r14 saved
258 bool save_return_addr_p;
260 /* Size of stack frame. */
261 HOST_WIDE_INT frame_size;
264 /* Define the structure for the machine field in struct function. */
266 struct machine_function GTY(())
268 struct s390_frame_layout frame_layout;
270 /* Literal pool base register. */
273 /* True if we may need to perform branch splitting. */
274 bool split_branches_pending_p;
276 /* Some local-dynamic TLS symbol name. */
277 const char *some_ld_name;
279 bool has_landing_pad_p;
282 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
284 #define cfun_frame_layout (cfun->machine->frame_layout)
285 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
286 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr - \
287 cfun_frame_layout.first_save_gpr + 1) * UNITS_PER_WORD)
288 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
290 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
293 /* Number of GPRs and FPRs used for argument passing. */
294 #define GP_ARG_NUM_REG 5
295 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
297 /* A couple of shortcuts. */
298 #define CONST_OK_FOR_J(x) \
299 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
300 #define CONST_OK_FOR_K(x) \
301 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
302 #define CONST_OK_FOR_Os(x) \
303 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
304 #define CONST_OK_FOR_Op(x) \
305 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
306 #define CONST_OK_FOR_On(x) \
307 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
309 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
312 s390_set_has_landing_pad_p (bool value)
314 cfun->machine->has_landing_pad_p = value;
317 /* If two condition code modes are compatible, return a condition code
318 mode which is compatible with both. Otherwise, return
321 static enum machine_mode
322 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
330 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
331 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
352 /* Return true if SET either doesn't set the CC register, or else
353 the source and destination have matching CC modes and that
354 CC mode is at least as constrained as REQ_MODE. */
357 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
359 enum machine_mode set_mode;
361 gcc_assert (GET_CODE (set) == SET);
363 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
366 set_mode = GET_MODE (SET_DEST (set));
380 if (req_mode != set_mode)
385 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
386 && req_mode != CCSRmode && req_mode != CCURmode)
392 if (req_mode != CCAmode)
400 return (GET_MODE (SET_SRC (set)) == set_mode);
403 /* Return true if every SET in INSN that sets the CC register
404 has source and destination with matching CC modes and that
405 CC mode is at least as constrained as REQ_MODE.
406 If REQ_MODE is VOIDmode, always return false. */
409 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
413 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
414 if (req_mode == VOIDmode)
417 if (GET_CODE (PATTERN (insn)) == SET)
418 return s390_match_ccmode_set (PATTERN (insn), req_mode);
420 if (GET_CODE (PATTERN (insn)) == PARALLEL)
421 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
423 rtx set = XVECEXP (PATTERN (insn), 0, i);
424 if (GET_CODE (set) == SET)
425 if (!s390_match_ccmode_set (set, req_mode))
432 /* If a test-under-mask instruction can be used to implement
433 (compare (and ... OP1) OP2), return the CC mode required
434 to do that. Otherwise, return VOIDmode.
435 MIXED is true if the instruction can distinguish between
436 CC1 and CC2 for mixed selected bits (TMxx), it is false
437 if the instruction cannot (TM). */
440 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
444 /* ??? Fixme: should work on CONST_DOUBLE as well. */
445 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
448 /* Selected bits all zero: CC0.
449 e.g.: int a; if ((a & (16 + 128)) == 0) */
450 if (INTVAL (op2) == 0)
453 /* Selected bits all one: CC3.
454 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
455 if (INTVAL (op2) == INTVAL (op1))
458 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
460 if ((a & (16 + 128)) == 16) -> CCT1
461 if ((a & (16 + 128)) == 128) -> CCT2 */
464 bit1 = exact_log2 (INTVAL (op2));
465 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
466 if (bit0 != -1 && bit1 != -1)
467 return bit0 > bit1 ? CCT1mode : CCT2mode;
473 /* Given a comparison code OP (EQ, NE, etc.) and the operands
474 OP0 and OP1 of a COMPARE, return the mode to be used for the
478 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
484 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
485 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
487 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
488 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
490 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
491 || GET_CODE (op1) == NEG)
492 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
495 if (GET_CODE (op0) == AND)
497 /* Check whether we can potentially do it via TM. */
498 enum machine_mode ccmode;
499 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
500 if (ccmode != VOIDmode)
502 /* Relax CCTmode to CCZmode to allow fall-back to AND
503 if that turns out to be beneficial. */
504 return ccmode == CCTmode ? CCZmode : ccmode;
508 if (register_operand (op0, HImode)
509 && GET_CODE (op1) == CONST_INT
510 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
512 if (register_operand (op0, QImode)
513 && GET_CODE (op1) == CONST_INT
514 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
523 /* The only overflow condition of NEG and ABS happens when
524 -INT_MAX is used as parameter, which stays negative. So
525 we have an overflow from a positive value to a negative.
526 Using CCAP mode the resulting cc can be used for comparisons. */
527 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
528 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
531 /* If constants are involved in an add instruction it is possible to use
532 the resulting cc for comparisons with zero. Knowing the sign of the
533 constant the overflow behavior gets predictable. e.g.:
534 int a, b; if ((b = a + c) > 0)
535 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
536 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
537 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
539 if (INTVAL (XEXP((op0), 1)) < 0)
553 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
554 && GET_CODE (op1) != CONST_INT)
560 if (GET_CODE (op0) == PLUS
561 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
564 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
565 && GET_CODE (op1) != CONST_INT)
571 if (GET_CODE (op0) == MINUS
572 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
575 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
576 && GET_CODE (op1) != CONST_INT)
585 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
586 that we can implement more efficiently. */
589 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
591 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
592 if ((*code == EQ || *code == NE)
593 && *op1 == const0_rtx
594 && GET_CODE (*op0) == ZERO_EXTRACT
595 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
596 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
597 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
599 rtx inner = XEXP (*op0, 0);
600 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
601 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
602 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
604 if (len > 0 && len < modesize
605 && pos >= 0 && pos + len <= modesize
606 && modesize <= HOST_BITS_PER_WIDE_INT)
608 unsigned HOST_WIDE_INT block;
609 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
610 block <<= modesize - pos - len;
612 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
613 gen_int_mode (block, GET_MODE (inner)));
617 /* Narrow AND of memory against immediate to enable TM. */
618 if ((*code == EQ || *code == NE)
619 && *op1 == const0_rtx
620 && GET_CODE (*op0) == AND
621 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
622 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
624 rtx inner = XEXP (*op0, 0);
625 rtx mask = XEXP (*op0, 1);
627 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
628 if (GET_CODE (inner) == SUBREG
629 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
630 && (GET_MODE_SIZE (GET_MODE (inner))
631 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
633 & GET_MODE_MASK (GET_MODE (inner))
634 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
636 inner = SUBREG_REG (inner);
638 /* Do not change volatile MEMs. */
639 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
641 int part = s390_single_part (XEXP (*op0, 1),
642 GET_MODE (inner), QImode, 0);
645 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
646 inner = adjust_address_nv (inner, QImode, part);
647 *op0 = gen_rtx_AND (QImode, inner, mask);
652 /* Narrow comparisons against 0xffff to HImode if possible. */
653 if ((*code == EQ || *code == NE)
654 && GET_CODE (*op1) == CONST_INT
655 && INTVAL (*op1) == 0xffff
656 && SCALAR_INT_MODE_P (GET_MODE (*op0))
657 && (nonzero_bits (*op0, GET_MODE (*op0))
658 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
660 *op0 = gen_lowpart (HImode, *op0);
665 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
666 if (GET_CODE (*op0) == UNSPEC
667 && XINT (*op0, 1) == UNSPEC_CMPINT
668 && XVECLEN (*op0, 0) == 1
669 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
670 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
671 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
672 && *op1 == const0_rtx)
674 enum rtx_code new_code = UNKNOWN;
677 case EQ: new_code = EQ; break;
678 case NE: new_code = NE; break;
679 case LT: new_code = GTU; break;
680 case GT: new_code = LTU; break;
681 case LE: new_code = GEU; break;
682 case GE: new_code = LEU; break;
686 if (new_code != UNKNOWN)
688 *op0 = XVECEXP (*op0, 0, 0);
693 /* Simplify cascaded EQ, NE with const0_rtx. */
694 if ((*code == NE || *code == EQ)
695 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
696 && GET_MODE (*op0) == SImode
697 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
698 && REG_P (XEXP (*op0, 0))
699 && XEXP (*op0, 1) == const0_rtx
700 && *op1 == const0_rtx)
702 if ((*code == EQ && GET_CODE (*op0) == NE)
703 || (*code == NE && GET_CODE (*op0) == EQ))
707 *op0 = XEXP (*op0, 0);
710 /* Prefer register over memory as first operand. */
711 if (MEM_P (*op0) && REG_P (*op1))
713 rtx tem = *op0; *op0 = *op1; *op1 = tem;
714 *code = swap_condition (*code);
718 /* Emit a compare instruction suitable to implement the comparison
719 OP0 CODE OP1. Return the correct condition RTL to be placed in
720 the IF_THEN_ELSE of the conditional branch testing the result. */
723 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
725 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
728 /* Do not output a redundant compare instruction if a compare_and_swap
729 pattern already computed the result and the machine modes are compatible. */
730 if (s390_compare_emitted
731 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
732 == GET_MODE (s390_compare_emitted)))
733 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
736 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
738 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
739 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
741 s390_compare_emitted = NULL_RTX;
745 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
746 unconditional jump, else a conditional jump under condition COND. */
749 s390_emit_jump (rtx target, rtx cond)
753 target = gen_rtx_LABEL_REF (VOIDmode, target);
755 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
757 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
758 emit_jump_insn (insn);
761 /* Return branch condition mask to implement a branch
762 specified by CODE. Return -1 for invalid comparisons. */
765 s390_branch_condition_mask (rtx code)
767 const int CC0 = 1 << 3;
768 const int CC1 = 1 << 2;
769 const int CC2 = 1 << 1;
770 const int CC3 = 1 << 0;
772 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
773 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
774 gcc_assert (XEXP (code, 1) == const0_rtx);
776 switch (GET_MODE (XEXP (code, 0)))
780 switch (GET_CODE (code))
783 case NE: return CC1 | CC2 | CC3;
789 switch (GET_CODE (code))
792 case NE: return CC0 | CC2 | CC3;
798 switch (GET_CODE (code))
801 case NE: return CC0 | CC1 | CC3;
807 switch (GET_CODE (code))
810 case NE: return CC0 | CC1 | CC2;
816 switch (GET_CODE (code))
818 case EQ: return CC0 | CC2;
819 case NE: return CC1 | CC3;
825 switch (GET_CODE (code))
827 case LTU: return CC2 | CC3; /* carry */
828 case GEU: return CC0 | CC1; /* no carry */
834 switch (GET_CODE (code))
836 case GTU: return CC0 | CC1; /* borrow */
837 case LEU: return CC2 | CC3; /* no borrow */
843 switch (GET_CODE (code))
845 case EQ: return CC0 | CC2;
846 case NE: return CC1 | CC3;
847 case LTU: return CC1;
848 case GTU: return CC3;
849 case LEU: return CC1 | CC2;
850 case GEU: return CC2 | CC3;
855 switch (GET_CODE (code))
858 case NE: return CC1 | CC2 | CC3;
859 case LTU: return CC1;
860 case GTU: return CC2;
861 case LEU: return CC0 | CC1;
862 case GEU: return CC0 | CC2;
868 switch (GET_CODE (code))
871 case NE: return CC2 | CC1 | CC3;
872 case LTU: return CC2;
873 case GTU: return CC1;
874 case LEU: return CC0 | CC2;
875 case GEU: return CC0 | CC1;
881 switch (GET_CODE (code))
884 case NE: return CC1 | CC2 | CC3;
885 case LT: return CC1 | CC3;
887 case LE: return CC0 | CC1 | CC3;
888 case GE: return CC0 | CC2;
894 switch (GET_CODE (code))
897 case NE: return CC1 | CC2 | CC3;
899 case GT: return CC2 | CC3;
900 case LE: return CC0 | CC1;
901 case GE: return CC0 | CC2 | CC3;
907 switch (GET_CODE (code))
910 case NE: return CC1 | CC2 | CC3;
913 case LE: return CC0 | CC1;
914 case GE: return CC0 | CC2;
915 case UNORDERED: return CC3;
916 case ORDERED: return CC0 | CC1 | CC2;
917 case UNEQ: return CC0 | CC3;
918 case UNLT: return CC1 | CC3;
919 case UNGT: return CC2 | CC3;
920 case UNLE: return CC0 | CC1 | CC3;
921 case UNGE: return CC0 | CC2 | CC3;
922 case LTGT: return CC1 | CC2;
928 switch (GET_CODE (code))
931 case NE: return CC2 | CC1 | CC3;
934 case LE: return CC0 | CC2;
935 case GE: return CC0 | CC1;
936 case UNORDERED: return CC3;
937 case ORDERED: return CC0 | CC2 | CC1;
938 case UNEQ: return CC0 | CC3;
939 case UNLT: return CC2 | CC3;
940 case UNGT: return CC1 | CC3;
941 case UNLE: return CC0 | CC2 | CC3;
942 case UNGE: return CC0 | CC1 | CC3;
943 case LTGT: return CC2 | CC1;
953 /* If INV is false, return assembler mnemonic string to implement
954 a branch specified by CODE. If INV is true, return mnemonic
955 for the corresponding inverted branch. */
958 s390_branch_condition_mnemonic (rtx code, int inv)
960 static const char *const mnemonic[16] =
962 NULL, "o", "h", "nle",
963 "l", "nhe", "lh", "ne",
964 "e", "nlh", "he", "nl",
965 "le", "nh", "no", NULL
968 int mask = s390_branch_condition_mask (code);
969 gcc_assert (mask >= 0);
974 gcc_assert (mask >= 1 && mask <= 14);
976 return mnemonic[mask];
979 /* Return the part of op which has a value different from def.
980 The size of the part is determined by mode.
981 Use this function only if you already know that op really
982 contains such a part. */
984 unsigned HOST_WIDE_INT
985 s390_extract_part (rtx op, enum machine_mode mode, int def)
987 unsigned HOST_WIDE_INT value = 0;
988 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
989 int part_bits = GET_MODE_BITSIZE (mode);
990 unsigned HOST_WIDE_INT part_mask
991 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
994 for (i = 0; i < max_parts; i++)
997 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1001 if ((value & part_mask) != (def & part_mask))
1002 return value & part_mask;
1008 /* If OP is an integer constant of mode MODE with exactly one
1009 part of mode PART_MODE unequal to DEF, return the number of that
1010 part. Otherwise, return -1. */
1013 s390_single_part (rtx op,
1014 enum machine_mode mode,
1015 enum machine_mode part_mode,
1018 unsigned HOST_WIDE_INT value = 0;
1019 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1020 unsigned HOST_WIDE_INT part_mask
1021 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1024 if (GET_CODE (op) != CONST_INT)
1027 for (i = 0; i < n_parts; i++)
1030 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1032 value >>= GET_MODE_BITSIZE (part_mode);
1034 if ((value & part_mask) != (def & part_mask))
1042 return part == -1 ? -1 : n_parts - 1 - part;
1045 /* Check whether we can (and want to) split a double-word
1046 move in mode MODE from SRC to DST into two single-word
1047 moves, moving the subword FIRST_SUBWORD first. */
1050 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1052 /* Floating point registers cannot be split. */
1053 if (FP_REG_P (src) || FP_REG_P (dst))
1056 /* We don't need to split if operands are directly accessible. */
1057 if (s_operand (src, mode) || s_operand (dst, mode))
1060 /* Non-offsettable memory references cannot be split. */
1061 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1062 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1065 /* Moving the first subword must not clobber a register
1066 needed to move the second subword. */
1067 if (register_operand (dst, mode))
1069 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1070 if (reg_overlap_mentioned_p (subreg, src))
1077 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1078 and [MEM2, MEM2 + SIZE] do overlap and false
1082 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1084 rtx addr1, addr2, addr_delta;
1085 HOST_WIDE_INT delta;
1087 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1093 addr1 = XEXP (mem1, 0);
1094 addr2 = XEXP (mem2, 0);
1096 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1098 /* This overlapping check is used by peepholes merging memory block operations.
1099 Overlapping operations would otherwise be recognized by the S/390 hardware
1100 and would fall back to a slower implementation. Allowing overlapping
1101 operations would lead to slow code but not to wrong code. Therefore we are
1102 somewhat optimistic if we cannot prove that the memory blocks are
1104 That's why we return false here although this may accept operations on
1105 overlapping memory areas. */
1106 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1109 delta = INTVAL (addr_delta);
1112 || (delta > 0 && delta < size)
1113 || (delta < 0 && -delta < size))
1119 /* Check whether the address of memory reference MEM2 equals exactly
1120 the address of memory reference MEM1 plus DELTA. Return true if
1121 we can prove this to be the case, false otherwise. */
1124 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1126 rtx addr1, addr2, addr_delta;
1128 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1131 addr1 = XEXP (mem1, 0);
1132 addr2 = XEXP (mem2, 0);
1134 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1135 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1141 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1144 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1147 enum machine_mode wmode = mode;
1148 rtx dst = operands[0];
1149 rtx src1 = operands[1];
1150 rtx src2 = operands[2];
1153 /* If we cannot handle the operation directly, use a temp register. */
1154 if (!s390_logical_operator_ok_p (operands))
1155 dst = gen_reg_rtx (mode);
1157 /* QImode and HImode patterns make sense only if we have a destination
1158 in memory. Otherwise perform the operation in SImode. */
1159 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1162 /* Widen operands if required. */
1165 if (GET_CODE (dst) == SUBREG
1166 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1168 else if (REG_P (dst))
1169 dst = gen_rtx_SUBREG (wmode, dst, 0);
1171 dst = gen_reg_rtx (wmode);
1173 if (GET_CODE (src1) == SUBREG
1174 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1176 else if (GET_MODE (src1) != VOIDmode)
1177 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1179 if (GET_CODE (src2) == SUBREG
1180 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1182 else if (GET_MODE (src2) != VOIDmode)
1183 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1186 /* Emit the instruction. */
1187 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1188 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1189 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1191 /* Fix up the destination if needed. */
1192 if (dst != operands[0])
1193 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1196 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1199 s390_logical_operator_ok_p (rtx *operands)
1201 /* If the destination operand is in memory, it needs to coincide
1202 with one of the source operands. After reload, it has to be
1203 the first source operand. */
1204 if (GET_CODE (operands[0]) == MEM)
1205 return rtx_equal_p (operands[0], operands[1])
1206 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1211 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1212 operand IMMOP to switch from SS to SI type instructions. */
1215 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1217 int def = code == AND ? -1 : 0;
1221 gcc_assert (GET_CODE (*memop) == MEM);
1222 gcc_assert (!MEM_VOLATILE_P (*memop));
1224 mask = s390_extract_part (*immop, QImode, def);
1225 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1226 gcc_assert (part >= 0);
1228 *memop = adjust_address (*memop, QImode, part);
1229 *immop = gen_int_mode (mask, QImode);
1233 /* How to allocate a 'struct machine_function'. */
1235 static struct machine_function *
1236 s390_init_machine_status (void)
1238 return ggc_alloc_cleared (sizeof (struct machine_function));
1241 /* Change optimizations to be performed, depending on the
1244 LEVEL is the optimization level specified; 2 if `-O2' is
1245 specified, 1 if `-O' is specified, and 0 if neither is specified.
1247 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1250 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1252 /* ??? There are apparently still problems with -fcaller-saves. */
1253 flag_caller_saves = 0;
1255 /* By default, always emit DWARF-2 unwind info. This allows debugging
1256 without maintaining a stack frame back-chain. */
1257 flag_asynchronous_unwind_tables = 1;
1259 /* Use MVCLE instructions to decrease code size if requested. */
1261 target_flags |= MASK_MVCLE;
1264 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1265 to the associated processor_type and processor_flags if so. */
1268 s390_handle_arch_option (const char *arg,
1269 enum processor_type *type,
1270 enum processor_flags *flags)
1274 const char *const name; /* processor name or nickname. */
1275 const enum processor_type processor;
1276 const enum processor_flags flags;
1278 const processor_alias_table[] =
1280 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1281 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1282 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1283 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1284 | PF_LONG_DISPLACEMENT},
1285 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1286 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1290 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1291 if (strcmp (arg, processor_alias_table[i].name) == 0)
1293 *type = processor_alias_table[i].processor;
1294 *flags = processor_alias_table[i].flags;
1300 /* Implement TARGET_HANDLE_OPTION. */
1303 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1308 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1310 case OPT_mstack_guard_:
1311 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1313 if (exact_log2 (s390_stack_guard) == -1)
1314 error ("stack guard value must be an exact power of 2");
1317 case OPT_mstack_size_:
1318 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1320 if (exact_log2 (s390_stack_size) == -1)
1321 error ("stack size must be an exact power of 2");
1325 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1327 case OPT_mwarn_framesize_:
1328 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1336 override_options (void)
1338 /* Set up function hooks. */
1339 init_machine_status = s390_init_machine_status;
1341 /* Architecture mode defaults according to ABI. */
1342 if (!(target_flags_explicit & MASK_ZARCH))
1345 target_flags |= MASK_ZARCH;
1347 target_flags &= ~MASK_ZARCH;
1350 /* Determine processor architectural level. */
1351 if (!s390_arch_string)
1353 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1354 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1357 /* Determine processor to tune for. */
1358 if (s390_tune == PROCESSOR_max)
1360 s390_tune = s390_arch;
1361 s390_tune_flags = s390_arch_flags;
1364 /* Sanity checks. */
1365 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1366 error ("z/Architecture mode not supported on %s", s390_arch_string);
1367 if (TARGET_64BIT && !TARGET_ZARCH)
1368 error ("64-bit ABI not supported in ESA/390 mode");
1370 /* Set processor cost function. */
1371 if (s390_tune == PROCESSOR_2094_Z9_109)
1372 s390_cost = &z9_109_cost;
1373 else if (s390_tune == PROCESSOR_2084_Z990)
1374 s390_cost = &z990_cost;
1376 s390_cost = &z900_cost;
1378 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1379 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1382 if (s390_stack_size)
1384 if (!s390_stack_guard)
1385 error ("-mstack-size implies use of -mstack-guard");
1386 else if (s390_stack_guard >= s390_stack_size)
1387 error ("stack size must be greater than the stack guard value");
1389 else if (s390_stack_guard)
1390 error ("-mstack-guard implies use of -mstack-size");
1393 /* Map for smallest class containing reg regno. */
1395 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1396 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1397 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1398 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1399 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1400 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1401 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1402 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1403 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1404 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1405 ACCESS_REGS, ACCESS_REGS
1408 /* Return attribute type of insn. */
1410 static enum attr_type
1411 s390_safe_attr_type (rtx insn)
1413 if (recog_memoized (insn) >= 0)
1414 return get_attr_type (insn);
1419 /* Return true if DISP is a valid short displacement. */
1422 s390_short_displacement (rtx disp)
1424 /* No displacement is OK. */
1428 /* Integer displacement in range. */
1429 if (GET_CODE (disp) == CONST_INT)
1430 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1432 /* GOT offset is not OK, the GOT can be large. */
1433 if (GET_CODE (disp) == CONST
1434 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1435 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1436 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1439 /* All other symbolic constants are literal pool references,
1440 which are OK as the literal pool must be small. */
1441 if (GET_CODE (disp) == CONST)
1447 /* Decompose a RTL expression ADDR for a memory address into
1448 its components, returned in OUT.
1450 Returns false if ADDR is not a valid memory address, true
1451 otherwise. If OUT is NULL, don't return the components,
1452 but check for validity only.
1454 Note: Only addresses in canonical form are recognized.
1455 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1456 canonical form so that they will be recognized. */
1459 s390_decompose_address (rtx addr, struct s390_address *out)
1461 HOST_WIDE_INT offset = 0;
1462 rtx base = NULL_RTX;
1463 rtx indx = NULL_RTX;
1464 rtx disp = NULL_RTX;
1466 bool pointer = false;
1467 bool base_ptr = false;
1468 bool indx_ptr = false;
1470 /* Decompose address into base + index + displacement. */
1472 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1475 else if (GET_CODE (addr) == PLUS)
1477 rtx op0 = XEXP (addr, 0);
1478 rtx op1 = XEXP (addr, 1);
1479 enum rtx_code code0 = GET_CODE (op0);
1480 enum rtx_code code1 = GET_CODE (op1);
1482 if (code0 == REG || code0 == UNSPEC)
1484 if (code1 == REG || code1 == UNSPEC)
1486 indx = op0; /* index + base */
1492 base = op0; /* base + displacement */
1497 else if (code0 == PLUS)
1499 indx = XEXP (op0, 0); /* index + base + disp */
1500 base = XEXP (op0, 1);
1511 disp = addr; /* displacement */
1513 /* Extract integer part of displacement. */
1517 if (GET_CODE (disp) == CONST_INT)
1519 offset = INTVAL (disp);
1522 else if (GET_CODE (disp) == CONST
1523 && GET_CODE (XEXP (disp, 0)) == PLUS
1524 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1526 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1527 disp = XEXP (XEXP (disp, 0), 0);
1531 /* Strip off CONST here to avoid special case tests later. */
1532 if (disp && GET_CODE (disp) == CONST)
1533 disp = XEXP (disp, 0);
1535 /* We can convert literal pool addresses to
1536 displacements by basing them off the base register. */
1537 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1539 /* Either base or index must be free to hold the base register. */
1541 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1543 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1547 /* Mark up the displacement. */
1548 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1549 UNSPEC_LTREL_OFFSET);
1552 /* Validate base register. */
1555 if (GET_CODE (base) == UNSPEC)
1556 switch (XINT (base, 1))
1560 disp = gen_rtx_UNSPEC (Pmode,
1561 gen_rtvec (1, XVECEXP (base, 0, 0)),
1562 UNSPEC_LTREL_OFFSET);
1566 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1569 case UNSPEC_LTREL_BASE:
1570 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1577 if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
1580 if (REGNO (base) == BASE_REGNUM
1581 || REGNO (base) == STACK_POINTER_REGNUM
1582 || REGNO (base) == FRAME_POINTER_REGNUM
1583 || ((reload_completed || reload_in_progress)
1584 && frame_pointer_needed
1585 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1586 || REGNO (base) == ARG_POINTER_REGNUM
1588 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1589 pointer = base_ptr = true;
1592 /* Validate index register. */
1595 if (GET_CODE (indx) == UNSPEC)
1596 switch (XINT (indx, 1))
1600 disp = gen_rtx_UNSPEC (Pmode,
1601 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1602 UNSPEC_LTREL_OFFSET);
1606 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1609 case UNSPEC_LTREL_BASE:
1610 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1617 if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
1620 if (REGNO (indx) == BASE_REGNUM
1621 || REGNO (indx) == STACK_POINTER_REGNUM
1622 || REGNO (indx) == FRAME_POINTER_REGNUM
1623 || ((reload_completed || reload_in_progress)
1624 && frame_pointer_needed
1625 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1626 || REGNO (indx) == ARG_POINTER_REGNUM
1628 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1629 pointer = indx_ptr = true;
1632 /* Prefer to use pointer as base, not index. */
1633 if (base && indx && !base_ptr
1634 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1641 /* Validate displacement. */
1644 /* If virtual registers are involved, the displacement will change later
1645 anyway as the virtual registers get eliminated. This could make a
1646 valid displacement invalid, but it is more likely to make an invalid
1647 displacement valid, because we sometimes access the register save area
1648 via negative offsets to one of those registers.
1649 Thus we don't check the displacement for validity here. If after
1650 elimination the displacement turns out to be invalid after all,
1651 this is fixed up by reload in any case. */
1652 if (base != arg_pointer_rtx
1653 && indx != arg_pointer_rtx
1654 && base != return_address_pointer_rtx
1655 && indx != return_address_pointer_rtx
1656 && base != frame_pointer_rtx
1657 && indx != frame_pointer_rtx
1658 && base != virtual_stack_vars_rtx
1659 && indx != virtual_stack_vars_rtx)
1660 if (!DISP_IN_RANGE (offset))
1665 /* All the special cases are pointers. */
1668 /* In the small-PIC case, the linker converts @GOT
1669 and @GOTNTPOFF offsets to possible displacements. */
1670 if (GET_CODE (disp) == UNSPEC
1671 && (XINT (disp, 1) == UNSPEC_GOT
1672 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1679 /* Accept chunkified literal pool symbol references. */
1680 else if (GET_CODE (disp) == MINUS
1681 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1682 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1687 /* Accept literal pool references. */
1688 else if (GET_CODE (disp) == UNSPEC
1689 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1691 orig_disp = gen_rtx_CONST (Pmode, disp);
1694 /* If we have an offset, make sure it does not
1695 exceed the size of the constant pool entry. */
1696 rtx sym = XVECEXP (disp, 0, 0);
1697 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1700 orig_disp = plus_constant (orig_disp, offset);
1715 out->disp = orig_disp;
1716 out->pointer = pointer;
1722 /* Return true if CODE is a valid address without index. */
1725 s390_legitimate_address_without_index_p (rtx op)
1727 struct s390_address addr;
1729 if (!s390_decompose_address (XEXP (op, 0), &addr))
1737 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1740 s390_extra_constraint_str (rtx op, int c, const char * str)
1742 struct s390_address addr;
1744 gcc_assert (c == str[0]);
1746 /* Check for offsettable variants of memory constraints. */
1749 /* Only accept non-volatile MEMs. */
1750 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1753 if ((reload_completed || reload_in_progress)
1754 ? !offsettable_memref_p (op)
1755 : !offsettable_nonstrict_memref_p (op))
1761 /* Check for non-literal-pool variants of memory constraints. */
1764 if (GET_CODE (op) != MEM)
1766 if (!s390_decompose_address (XEXP (op, 0), &addr))
1768 if (addr.base && REG_P (addr.base) && REGNO (addr.base) == BASE_REGNUM)
1770 if (addr.indx && REG_P (addr.indx) && REGNO (addr.indx) == BASE_REGNUM)
1779 if (GET_CODE (op) != MEM)
1781 if (!s390_decompose_address (XEXP (op, 0), &addr))
1786 if (TARGET_LONG_DISPLACEMENT)
1788 if (!s390_short_displacement (addr.disp))
1794 if (GET_CODE (op) != MEM)
1797 if (TARGET_LONG_DISPLACEMENT)
1799 if (!s390_decompose_address (XEXP (op, 0), &addr))
1801 if (!s390_short_displacement (addr.disp))
1807 if (!TARGET_LONG_DISPLACEMENT)
1809 if (GET_CODE (op) != MEM)
1811 if (!s390_decompose_address (XEXP (op, 0), &addr))
1815 if (s390_short_displacement (addr.disp))
1820 if (!TARGET_LONG_DISPLACEMENT)
1822 if (GET_CODE (op) != MEM)
1824 /* Any invalid address here will be fixed up by reload,
1825 so accept it for the most generic constraint. */
1826 if (s390_decompose_address (XEXP (op, 0), &addr)
1827 && s390_short_displacement (addr.disp))
1832 if (TARGET_LONG_DISPLACEMENT)
1834 if (!s390_decompose_address (op, &addr))
1836 if (!s390_short_displacement (addr.disp))
1842 if (!TARGET_LONG_DISPLACEMENT)
1844 /* Any invalid address here will be fixed up by reload,
1845 so accept it for the most generic constraint. */
1846 if (s390_decompose_address (op, &addr)
1847 && s390_short_displacement (addr.disp))
1852 return shift_count_operand (op, VOIDmode);
1861 /* Return true if VALUE matches the constraint STR. */
1864 s390_const_double_ok_for_constraint_p (rtx value,
1868 gcc_assert (c == str[0]);
1873 /* The floating point zero constant. */
1874 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1875 && value == CONST0_RTX (GET_MODE (value)));
1882 /* Return true if VALUE matches the constraint STR. */
1885 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1889 enum machine_mode mode, part_mode;
1891 int part, part_goal;
1893 gcc_assert (c == str[0]);
1898 return (unsigned int)value < 256;
1901 return (unsigned int)value < 4096;
1904 return value >= -32768 && value < 32768;
1907 return (TARGET_LONG_DISPLACEMENT ?
1908 (value >= -524288 && value <= 524287)
1909 : (value >= 0 && value <= 4095));
1911 return value == 2147483647;
1917 part_goal = str[1] - '0';
1921 case 'Q': part_mode = QImode; break;
1922 case 'H': part_mode = HImode; break;
1923 case 'S': part_mode = SImode; break;
1929 case 'H': mode = HImode; break;
1930 case 'S': mode = SImode; break;
1931 case 'D': mode = DImode; break;
1937 case '0': def = 0; break;
1938 case 'F': def = -1; break;
1942 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
1945 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
1948 if (part_goal != -1 && part_goal != part)
1960 return trunc_int_for_mode (value, SImode) == value;
1964 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
1968 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
1976 return legitimate_reload_constant_p (GEN_INT (value));
1985 /* Compute a (partial) cost for rtx X. Return true if the complete
1986 cost has been computed, and false if subexpressions should be
1987 scanned. In either case, *TOTAL contains the cost result.
1988 CODE contains GET_CODE (x), OUTER_CODE contains the code
1989 of the superexpression of x. */
1992 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2015 *total = COSTS_N_INSNS (1);
2020 /* Check for multiply and add. */
2021 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2022 && GET_CODE (XEXP (x, 0)) == MULT
2023 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2025 /* This is the multiply and add case. */
2026 if (GET_MODE (x) == DFmode)
2027 *total = s390_cost->madbr;
2029 *total = s390_cost->maebr;
2030 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2031 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2032 + rtx_cost (XEXP (x, 1), code);
2033 return true; /* Do not do an additional recursive descent. */
2035 *total = COSTS_N_INSNS (1);
2039 switch (GET_MODE (x))
2043 rtx left = XEXP (x, 0);
2044 rtx right = XEXP (x, 1);
2045 if (GET_CODE (right) == CONST_INT
2046 && CONST_OK_FOR_K (INTVAL (right)))
2047 *total = s390_cost->mhi;
2048 else if (GET_CODE (left) == SIGN_EXTEND)
2049 *total = s390_cost->mh;
2051 *total = s390_cost->ms; /* msr, ms, msy */
2056 rtx left = XEXP (x, 0);
2057 rtx right = XEXP (x, 1);
2060 if (GET_CODE (right) == CONST_INT
2061 && CONST_OK_FOR_K (INTVAL (right)))
2062 *total = s390_cost->mghi;
2063 else if (GET_CODE (left) == SIGN_EXTEND)
2064 *total = s390_cost->msgf;
2066 *total = s390_cost->msg; /* msgr, msg */
2068 else /* TARGET_31BIT */
2070 if (GET_CODE (left) == SIGN_EXTEND
2071 && GET_CODE (right) == SIGN_EXTEND)
2072 /* mulsidi case: mr, m */
2073 *total = s390_cost->m;
2074 else if (GET_CODE (left) == ZERO_EXTEND
2075 && GET_CODE (right) == ZERO_EXTEND
2076 && TARGET_CPU_ZARCH)
2077 /* umulsidi case: ml, mlr */
2078 *total = s390_cost->ml;
2080 /* Complex calculation is required. */
2081 *total = COSTS_N_INSNS (40);
2087 *total = s390_cost->mult_df;
2096 if (GET_MODE (x) == TImode) /* 128 bit division */
2097 *total = s390_cost->dlgr;
2098 else if (GET_MODE (x) == DImode)
2100 rtx right = XEXP (x, 1);
2101 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2102 *total = s390_cost->dlr;
2103 else /* 64 by 64 bit division */
2104 *total = s390_cost->dlgr;
2106 else if (GET_MODE (x) == SImode) /* 32 bit division */
2107 *total = s390_cost->dlr;
2112 if (GET_MODE (x) == DImode)
2114 rtx right = XEXP (x, 1);
2115 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2117 *total = s390_cost->dsgfr;
2119 *total = s390_cost->dr;
2120 else /* 64 by 64 bit division */
2121 *total = s390_cost->dsgr;
2123 else if (GET_MODE (x) == SImode) /* 32 bit division */
2124 *total = s390_cost->dlr;
2125 else if (GET_MODE (x) == SFmode)
2127 if (TARGET_IEEE_FLOAT)
2128 *total = s390_cost->debr;
2129 else /* TARGET_IBM_FLOAT */
2130 *total = s390_cost->der;
2132 else if (GET_MODE (x) == DFmode)
2134 if (TARGET_IEEE_FLOAT)
2135 *total = s390_cost->ddbr;
2136 else /* TARGET_IBM_FLOAT */
2137 *total = s390_cost->ddr;
2142 if (GET_MODE (x) == SFmode)
2143 *total = s390_cost->sqebr;
2145 *total = s390_cost->sqdbr;
2150 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2151 || outer_code == PLUS || outer_code == MINUS
2152 || outer_code == COMPARE)
2157 *total = COSTS_N_INSNS (1);
2158 if (GET_CODE (XEXP (x, 0)) == AND
2159 && GET_CODE (XEXP (x, 1)) == CONST_INT
2160 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2162 rtx op0 = XEXP (XEXP (x, 0), 0);
2163 rtx op1 = XEXP (XEXP (x, 0), 1);
2164 rtx op2 = XEXP (x, 1);
2166 if (memory_operand (op0, GET_MODE (op0))
2167 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2169 if (register_operand (op0, GET_MODE (op0))
2170 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2180 /* Return the cost of an address rtx ADDR. */
2183 s390_address_cost (rtx addr)
2185 struct s390_address ad;
2186 if (!s390_decompose_address (addr, &ad))
2189 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2192 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2193 otherwise return 0. */
2196 tls_symbolic_operand (rtx op)
2198 if (GET_CODE (op) != SYMBOL_REF)
2200 return SYMBOL_REF_TLS_MODEL (op);
2203 /* Split DImode access register reference REG (on 64-bit) into its constituent
2204 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2205 gen_highpart cannot be used as they assume all registers are word-sized,
2206 while our access registers have only half that size. */
2209 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2211 gcc_assert (TARGET_64BIT);
2212 gcc_assert (ACCESS_REG_P (reg));
2213 gcc_assert (GET_MODE (reg) == DImode);
2214 gcc_assert (!(REGNO (reg) & 1));
2216 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2217 *hi = gen_rtx_REG (SImode, REGNO (reg));
2220 /* Return true if OP contains a symbol reference */
2223 symbolic_reference_mentioned_p (rtx op)
2228 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2231 fmt = GET_RTX_FORMAT (GET_CODE (op));
2232 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2238 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2239 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2243 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2250 /* Return true if OP contains a reference to a thread-local symbol. */
2253 tls_symbolic_reference_mentioned_p (rtx op)
2258 if (GET_CODE (op) == SYMBOL_REF)
2259 return tls_symbolic_operand (op);
2261 fmt = GET_RTX_FORMAT (GET_CODE (op));
2262 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2268 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2269 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2273 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2281 /* Return true if OP is a legitimate general operand when
2282 generating PIC code. It is given that flag_pic is on
2283 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2286 legitimate_pic_operand_p (rtx op)
2288 /* Accept all non-symbolic constants. */
2289 if (!SYMBOLIC_CONST (op))
2292 /* Reject everything else; must be handled
2293 via emit_symbolic_move. */
2297 /* Returns true if the constant value OP is a legitimate general operand.
2298 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2301 legitimate_constant_p (rtx op)
2303 /* Accept all non-symbolic constants. */
2304 if (!SYMBOLIC_CONST (op))
2307 /* Accept immediate LARL operands. */
2308 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2311 /* Thread-local symbols are never legal constants. This is
2312 so that emit_call knows that computing such addresses
2313 might require a function call. */
2314 if (TLS_SYMBOLIC_CONST (op))
2317 /* In the PIC case, symbolic constants must *not* be
2318 forced into the literal pool. We accept them here,
2319 so that they will be handled by emit_symbolic_move. */
2323 /* All remaining non-PIC symbolic constants are
2324 forced into the literal pool. */
2328 /* Determine if it's legal to put X into the constant pool. This
2329 is not possible if X contains the address of a symbol that is
2330 not constant (TLS) or not known at final link time (PIC). */
2333 s390_cannot_force_const_mem (rtx x)
2335 switch (GET_CODE (x))
2339 /* Accept all non-symbolic constants. */
2343 /* Labels are OK iff we are non-PIC. */
2344 return flag_pic != 0;
2347 /* 'Naked' TLS symbol references are never OK,
2348 non-TLS symbols are OK iff we are non-PIC. */
2349 if (tls_symbolic_operand (x))
2352 return flag_pic != 0;
2355 return s390_cannot_force_const_mem (XEXP (x, 0));
2358 return s390_cannot_force_const_mem (XEXP (x, 0))
2359 || s390_cannot_force_const_mem (XEXP (x, 1));
2362 switch (XINT (x, 1))
2364 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2365 case UNSPEC_LTREL_OFFSET:
2373 case UNSPEC_GOTNTPOFF:
2374 case UNSPEC_INDNTPOFF:
2377 /* If the literal pool shares the code section, be put
2378 execute template placeholders into the pool as well. */
2380 return TARGET_CPU_ZARCH;
2392 /* Returns true if the constant value OP is a legitimate general
2393 operand during and after reload. The difference to
2394 legitimate_constant_p is that this function will not accept
2395 a constant that would need to be forced to the literal pool
2396 before it can be used as operand. */
2399 legitimate_reload_constant_p (rtx op)
2401 /* Accept la(y) operands. */
2402 if (GET_CODE (op) == CONST_INT
2403 && DISP_IN_RANGE (INTVAL (op)))
2406 /* Accept l(g)hi/l(g)fi operands. */
2407 if (GET_CODE (op) == CONST_INT
2408 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2411 /* Accept lliXX operands. */
2413 && GET_CODE (op) == CONST_INT
2414 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2415 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2419 && GET_CODE (op) == CONST_INT
2420 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2421 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2424 /* Accept larl operands. */
2425 if (TARGET_CPU_ZARCH
2426 && larl_operand (op, VOIDmode))
2429 /* Accept lzXX operands. */
2430 if (GET_CODE (op) == CONST_DOUBLE
2431 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2434 /* Accept double-word operands that can be split. */
2435 if (GET_CODE (op) == CONST_INT
2436 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2438 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2439 rtx hi = operand_subword (op, 0, 0, dword_mode);
2440 rtx lo = operand_subword (op, 1, 0, dword_mode);
2441 return legitimate_reload_constant_p (hi)
2442 && legitimate_reload_constant_p (lo);
2445 /* Everything else cannot be handled without reload. */
2449 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2450 return the class of reg to actually use. */
2453 s390_preferred_reload_class (rtx op, enum reg_class class)
2455 switch (GET_CODE (op))
2457 /* Constants we cannot reload must be forced into the
2462 if (legitimate_reload_constant_p (op))
2467 /* If a symbolic constant or a PLUS is reloaded,
2468 it is most likely being used as an address, so
2469 prefer ADDR_REGS. If 'class' is not a superset
2470 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2475 if (reg_class_subset_p (ADDR_REGS, class))
2487 /* Return the register class of a scratch register needed to
2488 load IN into a register of class CLASS in MODE.
2490 We need a temporary when loading a PLUS expression which
2491 is not a legitimate operand of the LOAD ADDRESS instruction. */
2494 s390_secondary_input_reload_class (enum reg_class class,
2495 enum machine_mode mode, rtx in)
2497 if (s390_plus_operand (in, mode))
2500 if (reg_classes_intersect_p (CC_REGS, class))
2501 return GENERAL_REGS;
2506 /* Return the register class of a scratch register needed to
2507 store a register of class CLASS in MODE into OUT:
2509 We need a temporary when storing a double-word to a
2510 non-offsettable memory address. */
2513 s390_secondary_output_reload_class (enum reg_class class,
2514 enum machine_mode mode, rtx out)
2516 if ((TARGET_64BIT ? mode == TImode
2517 : (mode == DImode || mode == DFmode))
2518 && reg_classes_intersect_p (GENERAL_REGS, class)
2519 && GET_CODE (out) == MEM
2520 && GET_CODE (XEXP (out, 0)) == PLUS
2521 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2522 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2523 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2524 + GET_MODE_SIZE (mode) - 1))
2527 if (reg_classes_intersect_p (CC_REGS, class))
2528 return GENERAL_REGS;
2533 /* Generate code to load SRC, which is PLUS that is not a
2534 legitimate operand for the LA instruction, into TARGET.
2535 SCRATCH may be used as scratch register. */
2538 s390_expand_plus_operand (rtx target, rtx src,
2542 struct s390_address ad;
2544 /* src must be a PLUS; get its two operands. */
2545 gcc_assert (GET_CODE (src) == PLUS);
2546 gcc_assert (GET_MODE (src) == Pmode);
2548 /* Check if any of the two operands is already scheduled
2549 for replacement by reload. This can happen e.g. when
2550 float registers occur in an address. */
2551 sum1 = find_replacement (&XEXP (src, 0));
2552 sum2 = find_replacement (&XEXP (src, 1));
2553 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2555 /* If the address is already strictly valid, there's nothing to do. */
2556 if (!s390_decompose_address (src, &ad)
2557 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2558 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
2560 /* Otherwise, one of the operands cannot be an address register;
2561 we reload its value into the scratch register. */
2562 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2564 emit_move_insn (scratch, sum1);
2567 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2569 emit_move_insn (scratch, sum2);
2573 /* According to the way these invalid addresses are generated
2574 in reload.c, it should never happen (at least on s390) that
2575 *neither* of the PLUS components, after find_replacements
2576 was applied, is an address register. */
2577 if (sum1 == scratch && sum2 == scratch)
2583 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2586 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2587 is only ever performed on addresses, so we can mark the
2588 sum as legitimate for LA in any case. */
2589 s390_load_address (target, src);
2593 /* Return true if ADDR is a valid memory address.
2594 STRICT specifies whether strict register checking applies. */
2597 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2598 rtx addr, int strict)
2600 struct s390_address ad;
2601 if (!s390_decompose_address (addr, &ad))
2606 if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2608 if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))
2613 if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base))
2615 if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx))
2622 /* Return true if OP is a valid operand for the LA instruction.
2623 In 31-bit, we need to prove that the result is used as an
2624 address, as LA performs only a 31-bit addition. */
2627 legitimate_la_operand_p (rtx op)
2629 struct s390_address addr;
2630 if (!s390_decompose_address (op, &addr))
2633 return (TARGET_64BIT || addr.pointer);
2636 /* Return true if it is valid *and* preferable to use LA to
2637 compute the sum of OP1 and OP2. */
2640 preferred_la_operand_p (rtx op1, rtx op2)
2642 struct s390_address addr;
2644 if (op2 != const0_rtx)
2645 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2647 if (!s390_decompose_address (op1, &addr))
2649 if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base))
2651 if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx))
2654 if (!TARGET_64BIT && !addr.pointer)
2660 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2661 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2667 /* Emit a forced load-address operation to load SRC into DST.
2668 This will use the LOAD ADDRESS instruction even in situations
2669 where legitimate_la_operand_p (SRC) returns false. */
2672 s390_load_address (rtx dst, rtx src)
2675 emit_move_insn (dst, src);
2677 emit_insn (gen_force_la_31 (dst, src));
2680 /* Return a legitimate reference for ORIG (an address) using the
2681 register REG. If REG is 0, a new pseudo is generated.
2683 There are two types of references that must be handled:
2685 1. Global data references must load the address from the GOT, via
2686 the PIC reg. An insn is emitted to do this load, and the reg is
2689 2. Static data references, constant pool addresses, and code labels
2690 compute the address as an offset from the GOT, whose base is in
2691 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2692 differentiate them from global data objects. The returned
2693 address is the PIC reg + an unspec constant.
2695 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2696 reg also appears in the address. */
2699 legitimize_pic_address (rtx orig, rtx reg)
2705 if (GET_CODE (addr) == LABEL_REF
2706 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2708 /* This is a local symbol. */
2709 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2711 /* Access local symbols PC-relative via LARL.
2712 This is the same as in the non-PIC case, so it is
2713 handled automatically ... */
2717 /* Access local symbols relative to the GOT. */
2719 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2721 if (reload_in_progress || reload_completed)
2722 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2724 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2725 addr = gen_rtx_CONST (Pmode, addr);
2726 addr = force_const_mem (Pmode, addr);
2727 emit_move_insn (temp, addr);
2729 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2732 s390_load_address (reg, new);
2737 else if (GET_CODE (addr) == SYMBOL_REF)
2740 reg = gen_reg_rtx (Pmode);
2744 /* Assume GOT offset < 4k. This is handled the same way
2745 in both 31- and 64-bit code (@GOT). */
2747 if (reload_in_progress || reload_completed)
2748 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2750 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2751 new = gen_rtx_CONST (Pmode, new);
2752 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2753 new = gen_const_mem (Pmode, new);
2754 emit_move_insn (reg, new);
2757 else if (TARGET_CPU_ZARCH)
2759 /* If the GOT offset might be >= 4k, we determine the position
2760 of the GOT entry via a PC-relative LARL (@GOTENT). */
2762 rtx temp = gen_reg_rtx (Pmode);
2764 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2765 new = gen_rtx_CONST (Pmode, new);
2766 emit_move_insn (temp, new);
2768 new = gen_const_mem (Pmode, temp);
2769 emit_move_insn (reg, new);
2774 /* If the GOT offset might be >= 4k, we have to load it
2775 from the literal pool (@GOT). */
2777 rtx temp = gen_reg_rtx (Pmode);
2779 if (reload_in_progress || reload_completed)
2780 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2782 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2783 addr = gen_rtx_CONST (Pmode, addr);
2784 addr = force_const_mem (Pmode, addr);
2785 emit_move_insn (temp, addr);
2787 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2788 new = gen_const_mem (Pmode, new);
2789 emit_move_insn (reg, new);
2795 if (GET_CODE (addr) == CONST)
2797 addr = XEXP (addr, 0);
2798 if (GET_CODE (addr) == UNSPEC)
2800 gcc_assert (XVECLEN (addr, 0) == 1);
2801 switch (XINT (addr, 1))
2803 /* If someone moved a GOT-relative UNSPEC
2804 out of the literal pool, force them back in. */
2807 new = force_const_mem (Pmode, orig);
2810 /* @GOT is OK as is if small. */
2813 new = force_const_mem (Pmode, orig);
2816 /* @GOTENT is OK as is. */
2820 /* @PLT is OK as is on 64-bit, must be converted to
2821 GOT-relative @PLTOFF on 31-bit. */
2823 if (!TARGET_CPU_ZARCH)
2825 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2827 if (reload_in_progress || reload_completed)
2828 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2830 addr = XVECEXP (addr, 0, 0);
2831 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2833 addr = gen_rtx_CONST (Pmode, addr);
2834 addr = force_const_mem (Pmode, addr);
2835 emit_move_insn (temp, addr);
2837 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2840 s390_load_address (reg, new);
2846 /* Everything else cannot happen. */
2852 gcc_assert (GET_CODE (addr) == PLUS);
2854 if (GET_CODE (addr) == PLUS)
2856 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2857 /* Check first to see if this is a constant offset
2858 from a local symbol reference. */
2859 if ((GET_CODE (op0) == LABEL_REF
2860 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
2861 && GET_CODE (op1) == CONST_INT)
2863 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
2865 if (INTVAL (op1) & 1)
2867 /* LARL can't handle odd offsets, so emit a
2868 pair of LARL and LA. */
2869 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2871 if (!DISP_IN_RANGE (INTVAL (op1)))
2873 int even = INTVAL (op1) - 1;
2874 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
2875 op0 = gen_rtx_CONST (Pmode, op0);
2879 emit_move_insn (temp, op0);
2880 new = gen_rtx_PLUS (Pmode, temp, op1);
2884 s390_load_address (reg, new);
2890 /* If the offset is even, we can just use LARL.
2891 This will happen automatically. */
2896 /* Access local symbols relative to the GOT. */
2898 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2900 if (reload_in_progress || reload_completed)
2901 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2903 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
2905 addr = gen_rtx_PLUS (Pmode, addr, op1);
2906 addr = gen_rtx_CONST (Pmode, addr);
2907 addr = force_const_mem (Pmode, addr);
2908 emit_move_insn (temp, addr);
2910 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2913 s390_load_address (reg, new);
2919 /* Now, check whether it is a GOT relative symbol plus offset
2920 that was pulled out of the literal pool. Force it back in. */
2922 else if (GET_CODE (op0) == UNSPEC
2923 && GET_CODE (op1) == CONST_INT
2924 && XINT (op0, 1) == UNSPEC_GOTOFF)
2926 gcc_assert (XVECLEN (op0, 0) == 1);
2928 new = force_const_mem (Pmode, orig);
2931 /* Otherwise, compute the sum. */
2934 base = legitimize_pic_address (XEXP (addr, 0), reg);
2935 new = legitimize_pic_address (XEXP (addr, 1),
2936 base == reg ? NULL_RTX : reg);
2937 if (GET_CODE (new) == CONST_INT)
2938 new = plus_constant (base, INTVAL (new));
2941 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2943 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2944 new = XEXP (new, 1);
2946 new = gen_rtx_PLUS (Pmode, base, new);
2949 if (GET_CODE (new) == CONST)
2950 new = XEXP (new, 0);
2951 new = force_operand (new, 0);
2958 /* Load the thread pointer into a register. */
2961 s390_get_thread_pointer (void)
2963 rtx tp = gen_reg_rtx (Pmode);
2965 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
2966 mark_reg_pointer (tp, BITS_PER_WORD);
2971 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
2972 in s390_tls_symbol which always refers to __tls_get_offset.
2973 The returned offset is written to RESULT_REG and an USE rtx is
2974 generated for TLS_CALL. */
2976 static GTY(()) rtx s390_tls_symbol;
2979 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
2983 gcc_assert (flag_pic);
2985 if (!s390_tls_symbol)
2986 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
2988 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
2989 gen_rtx_REG (Pmode, RETURN_REGNUM));
2991 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
2992 CONST_OR_PURE_CALL_P (insn) = 1;
2995 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2996 this (thread-local) address. REG may be used as temporary. */
2999 legitimize_tls_address (rtx addr, rtx reg)
3001 rtx new, tls_call, temp, base, r2, insn;
3003 if (GET_CODE (addr) == SYMBOL_REF)
3004 switch (tls_symbolic_operand (addr))
3006 case TLS_MODEL_GLOBAL_DYNAMIC:
3008 r2 = gen_rtx_REG (Pmode, 2);
3009 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3010 new = gen_rtx_CONST (Pmode, tls_call);
3011 new = force_const_mem (Pmode, new);
3012 emit_move_insn (r2, new);
3013 s390_emit_tls_call_insn (r2, tls_call);
3014 insn = get_insns ();
3017 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3018 temp = gen_reg_rtx (Pmode);
3019 emit_libcall_block (insn, temp, r2, new);
3021 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3024 s390_load_address (reg, new);
3029 case TLS_MODEL_LOCAL_DYNAMIC:
3031 r2 = gen_rtx_REG (Pmode, 2);
3032 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3033 new = gen_rtx_CONST (Pmode, tls_call);
3034 new = force_const_mem (Pmode, new);
3035 emit_move_insn (r2, new);
3036 s390_emit_tls_call_insn (r2, tls_call);
3037 insn = get_insns ();
3040 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3041 temp = gen_reg_rtx (Pmode);
3042 emit_libcall_block (insn, temp, r2, new);
3044 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3045 base = gen_reg_rtx (Pmode);
3046 s390_load_address (base, new);
3048 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3049 new = gen_rtx_CONST (Pmode, new);
3050 new = force_const_mem (Pmode, new);
3051 temp = gen_reg_rtx (Pmode);
3052 emit_move_insn (temp, new);
3054 new = gen_rtx_PLUS (Pmode, base, temp);
3057 s390_load_address (reg, new);
3062 case TLS_MODEL_INITIAL_EXEC:
3065 /* Assume GOT offset < 4k. This is handled the same way
3066 in both 31- and 64-bit code. */
3068 if (reload_in_progress || reload_completed)
3069 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3071 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3072 new = gen_rtx_CONST (Pmode, new);
3073 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3074 new = gen_const_mem (Pmode, new);
3075 temp = gen_reg_rtx (Pmode);
3076 emit_move_insn (temp, new);
3078 else if (TARGET_CPU_ZARCH)
3080 /* If the GOT offset might be >= 4k, we determine the position
3081 of the GOT entry via a PC-relative LARL. */
3083 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3084 new = gen_rtx_CONST (Pmode, new);
3085 temp = gen_reg_rtx (Pmode);
3086 emit_move_insn (temp, new);
3088 new = gen_const_mem (Pmode, temp);
3089 temp = gen_reg_rtx (Pmode);
3090 emit_move_insn (temp, new);
3094 /* If the GOT offset might be >= 4k, we have to load it
3095 from the literal pool. */
3097 if (reload_in_progress || reload_completed)
3098 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3100 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3101 new = gen_rtx_CONST (Pmode, new);
3102 new = force_const_mem (Pmode, new);
3103 temp = gen_reg_rtx (Pmode);
3104 emit_move_insn (temp, new);
3106 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3107 new = gen_const_mem (Pmode, new);
3109 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3110 temp = gen_reg_rtx (Pmode);
3111 emit_insn (gen_rtx_SET (Pmode, temp, new));
3115 /* In position-dependent code, load the absolute address of
3116 the GOT entry from the literal pool. */
3118 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3119 new = gen_rtx_CONST (Pmode, new);
3120 new = force_const_mem (Pmode, new);
3121 temp = gen_reg_rtx (Pmode);
3122 emit_move_insn (temp, new);
3125 new = gen_const_mem (Pmode, new);
3126 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3127 temp = gen_reg_rtx (Pmode);
3128 emit_insn (gen_rtx_SET (Pmode, temp, new));
3131 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3134 s390_load_address (reg, new);
3139 case TLS_MODEL_LOCAL_EXEC:
3140 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3141 new = gen_rtx_CONST (Pmode, new);
3142 new = force_const_mem (Pmode, new);
3143 temp = gen_reg_rtx (Pmode);
3144 emit_move_insn (temp, new);
3146 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3149 s390_load_address (reg, new);
3158 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3160 switch (XINT (XEXP (addr, 0), 1))
3162 case UNSPEC_INDNTPOFF:
3163 gcc_assert (TARGET_CPU_ZARCH);
3172 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3173 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3175 new = XEXP (XEXP (addr, 0), 0);
3176 if (GET_CODE (new) != SYMBOL_REF)
3177 new = gen_rtx_CONST (Pmode, new);
3179 new = legitimize_tls_address (new, reg);
3180 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3181 new = force_operand (new, 0);
3185 gcc_unreachable (); /* for now ... */
3190 /* Emit insns to move operands[1] into operands[0]. */
3193 emit_symbolic_move (rtx *operands)
3195 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3197 if (GET_CODE (operands[0]) == MEM)
3198 operands[1] = force_reg (Pmode, operands[1]);
3199 else if (TLS_SYMBOLIC_CONST (operands[1]))
3200 operands[1] = legitimize_tls_address (operands[1], temp);
3202 operands[1] = legitimize_pic_address (operands[1], temp);
3205 /* Try machine-dependent ways of modifying an illegitimate address X
3206 to be legitimate. If we find one, return the new, valid address.
3208 OLDX is the address as it was before break_out_memory_refs was called.
3209 In some cases it is useful to look at this to decide what needs to be done.
3211 MODE is the mode of the operand pointed to by X.
3213 When -fpic is used, special handling is needed for symbolic references.
3214 See comments by legitimize_pic_address for details. */
3217 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3218 enum machine_mode mode ATTRIBUTE_UNUSED)
3220 rtx constant_term = const0_rtx;
3222 if (TLS_SYMBOLIC_CONST (x))
3224 x = legitimize_tls_address (x, 0);
3226 if (legitimate_address_p (mode, x, FALSE))
3231 if (SYMBOLIC_CONST (x)
3232 || (GET_CODE (x) == PLUS
3233 && (SYMBOLIC_CONST (XEXP (x, 0))
3234 || SYMBOLIC_CONST (XEXP (x, 1)))))
3235 x = legitimize_pic_address (x, 0);
3237 if (legitimate_address_p (mode, x, FALSE))
3241 x = eliminate_constant_term (x, &constant_term);
3243 /* Optimize loading of large displacements by splitting them
3244 into the multiple of 4K and the rest; this allows the
3245 former to be CSE'd if possible.
3247 Don't do this if the displacement is added to a register
3248 pointing into the stack frame, as the offsets will
3249 change later anyway. */
3251 if (GET_CODE (constant_term) == CONST_INT
3252 && !TARGET_LONG_DISPLACEMENT
3253 && !DISP_IN_RANGE (INTVAL (constant_term))
3254 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3256 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3257 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3259 rtx temp = gen_reg_rtx (Pmode);
3260 rtx val = force_operand (GEN_INT (upper), temp);
3262 emit_move_insn (temp, val);
3264 x = gen_rtx_PLUS (Pmode, x, temp);
3265 constant_term = GEN_INT (lower);
3268 if (GET_CODE (x) == PLUS)
3270 if (GET_CODE (XEXP (x, 0)) == REG)
3272 rtx temp = gen_reg_rtx (Pmode);
3273 rtx val = force_operand (XEXP (x, 1), temp);
3275 emit_move_insn (temp, val);
3277 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3280 else if (GET_CODE (XEXP (x, 1)) == REG)
3282 rtx temp = gen_reg_rtx (Pmode);
3283 rtx val = force_operand (XEXP (x, 0), temp);
3285 emit_move_insn (temp, val);
3287 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3291 if (constant_term != const0_rtx)
3292 x = gen_rtx_PLUS (Pmode, x, constant_term);
3297 /* Try a machine-dependent way of reloading an illegitimate address AD
3298 operand. If we find one, push the reload and and return the new address.
3300 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3301 and TYPE is the reload type of the current reload. */
3304 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3305 int opnum, int type)
3307 if (!optimize || TARGET_LONG_DISPLACEMENT)
3310 if (GET_CODE (ad) == PLUS)
3312 rtx tem = simplify_binary_operation (PLUS, Pmode,
3313 XEXP (ad, 0), XEXP (ad, 1));
3318 if (GET_CODE (ad) == PLUS
3319 && GET_CODE (XEXP (ad, 0)) == REG
3320 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3321 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3323 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3324 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3327 cst = GEN_INT (upper);
3328 if (!legitimate_reload_constant_p (cst))
3329 cst = force_const_mem (Pmode, cst);
3331 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3332 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3334 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3335 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3336 opnum, (enum reload_type) type);
3343 /* Emit code to move LEN bytes from DST to SRC. */
3346 s390_expand_movmem (rtx dst, rtx src, rtx len)
3348 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3350 if (INTVAL (len) > 0)
3351 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3354 else if (TARGET_MVCLE)
3356 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3361 rtx dst_addr, src_addr, count, blocks, temp;
3362 rtx loop_start_label = gen_label_rtx ();
3363 rtx loop_end_label = gen_label_rtx ();
3364 rtx end_label = gen_label_rtx ();
3365 enum machine_mode mode;
3367 mode = GET_MODE (len);
3368 if (mode == VOIDmode)
3371 dst_addr = gen_reg_rtx (Pmode);
3372 src_addr = gen_reg_rtx (Pmode);
3373 count = gen_reg_rtx (mode);
3374 blocks = gen_reg_rtx (mode);
3376 convert_move (count, len, 1);
3377 emit_cmp_and_jump_insns (count, const0_rtx,
3378 EQ, NULL_RTX, mode, 1, end_label);
3380 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3381 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3382 dst = change_address (dst, VOIDmode, dst_addr);
3383 src = change_address (src, VOIDmode, src_addr);
3385 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3387 emit_move_insn (count, temp);
3389 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3391 emit_move_insn (blocks, temp);
3393 emit_cmp_and_jump_insns (blocks, const0_rtx,
3394 EQ, NULL_RTX, mode, 1, loop_end_label);
3396 emit_label (loop_start_label);
3398 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3399 s390_load_address (dst_addr,
3400 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3401 s390_load_address (src_addr,
3402 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3404 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3406 emit_move_insn (blocks, temp);
3408 emit_cmp_and_jump_insns (blocks, const0_rtx,
3409 EQ, NULL_RTX, mode, 1, loop_end_label);
3411 emit_jump (loop_start_label);
3412 emit_label (loop_end_label);
3414 emit_insn (gen_movmem_short (dst, src,
3415 convert_to_mode (Pmode, count, 1)));
3416 emit_label (end_label);
3420 /* Emit code to set LEN bytes at DST to VAL.
3421 Make use of clrmem if VAL is zero. */
3424 s390_expand_setmem (rtx dst, rtx len, rtx val)
3426 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3427 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3429 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3431 if (val == const0_rtx && INTVAL (len) <= 256)
3432 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3435 /* Initialize memory by storing the first byte. */
3436 emit_move_insn (adjust_address (dst, QImode, 0), val);
3438 if (INTVAL (len) > 1)
3440 /* Initiate 1 byte overlap move.
3441 The first byte of DST is propagated through DSTP1.
3442 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3443 DST is set to size 1 so the rest of the memory location
3444 does not count as source operand. */
3445 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3446 set_mem_size (dst, const1_rtx);
3448 emit_insn (gen_movmem_short (dstp1, dst,
3449 GEN_INT (INTVAL (len) - 2)));
3454 else if (TARGET_MVCLE)
3456 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3457 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3462 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3463 rtx loop_start_label = gen_label_rtx ();
3464 rtx loop_end_label = gen_label_rtx ();
3465 rtx end_label = gen_label_rtx ();
3466 enum machine_mode mode;
3468 mode = GET_MODE (len);
3469 if (mode == VOIDmode)
3472 dst_addr = gen_reg_rtx (Pmode);
3473 src_addr = gen_reg_rtx (Pmode);
3474 count = gen_reg_rtx (mode);
3475 blocks = gen_reg_rtx (mode);
3477 convert_move (count, len, 1);
3478 emit_cmp_and_jump_insns (count, const0_rtx,
3479 EQ, NULL_RTX, mode, 1, end_label);
3481 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3482 dst = change_address (dst, VOIDmode, dst_addr);
3484 if (val == const0_rtx)
3485 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3488 dstp1 = adjust_address (dst, VOIDmode, 1);
3489 set_mem_size (dst, const1_rtx);
3491 /* Initialize memory by storing the first byte. */
3492 emit_move_insn (adjust_address (dst, QImode, 0), val);
3494 /* If count is 1 we are done. */
3495 emit_cmp_and_jump_insns (count, const1_rtx,
3496 EQ, NULL_RTX, mode, 1, end_label);
3498 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3501 emit_move_insn (count, temp);
3503 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3505 emit_move_insn (blocks, temp);
3507 emit_cmp_and_jump_insns (blocks, const0_rtx,
3508 EQ, NULL_RTX, mode, 1, loop_end_label);
3510 emit_label (loop_start_label);
3512 if (val == const0_rtx)
3513 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3515 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3516 s390_load_address (dst_addr,
3517 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3519 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3521 emit_move_insn (blocks, temp);
3523 emit_cmp_and_jump_insns (blocks, const0_rtx,
3524 EQ, NULL_RTX, mode, 1, loop_end_label);
3526 emit_jump (loop_start_label);
3527 emit_label (loop_end_label);
3529 if (val == const0_rtx)
3530 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3532 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3533 emit_label (end_label);
3537 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3538 and return the result in TARGET. */
3541 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3543 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3546 /* As the result of CMPINT is inverted compared to what we need,
3547 we have to swap the operands. */
3548 tmp = op0; op0 = op1; op1 = tmp;
3550 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3552 if (INTVAL (len) > 0)
3554 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3555 emit_insn (gen_cmpint (target, ccreg));
3558 emit_move_insn (target, const0_rtx);
3560 else if (TARGET_MVCLE)
3562 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3563 emit_insn (gen_cmpint (target, ccreg));
3567 rtx addr0, addr1, count, blocks, temp;
3568 rtx loop_start_label = gen_label_rtx ();
3569 rtx loop_end_label = gen_label_rtx ();
3570 rtx end_label = gen_label_rtx ();
3571 enum machine_mode mode;
3573 mode = GET_MODE (len);
3574 if (mode == VOIDmode)
3577 addr0 = gen_reg_rtx (Pmode);
3578 addr1 = gen_reg_rtx (Pmode);
3579 count = gen_reg_rtx (mode);
3580 blocks = gen_reg_rtx (mode);
3582 convert_move (count, len, 1);
3583 emit_cmp_and_jump_insns (count, const0_rtx,
3584 EQ, NULL_RTX, mode, 1, end_label);
3586 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3587 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3588 op0 = change_address (op0, VOIDmode, addr0);
3589 op1 = change_address (op1, VOIDmode, addr1);
3591 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3593 emit_move_insn (count, temp);
3595 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3597 emit_move_insn (blocks, temp);
3599 emit_cmp_and_jump_insns (blocks, const0_rtx,
3600 EQ, NULL_RTX, mode, 1, loop_end_label);
3602 emit_label (loop_start_label);
3604 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3605 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3606 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3607 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3608 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3609 emit_jump_insn (temp);
3611 s390_load_address (addr0,
3612 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3613 s390_load_address (addr1,
3614 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3616 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3618 emit_move_insn (blocks, temp);
3620 emit_cmp_and_jump_insns (blocks, const0_rtx,
3621 EQ, NULL_RTX, mode, 1, loop_end_label);
3623 emit_jump (loop_start_label);
3624 emit_label (loop_end_label);
3626 emit_insn (gen_cmpmem_short (op0, op1,
3627 convert_to_mode (Pmode, count, 1)));
3628 emit_label (end_label);
3630 emit_insn (gen_cmpint (target, ccreg));
3635 /* Expand conditional increment or decrement using alc/slb instructions.
3636 Should generate code setting DST to either SRC or SRC + INCREMENT,
3637 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3638 Returns true if successful, false otherwise.
3640 That makes it possible to implement some if-constructs without jumps e.g.:
3641 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3642 unsigned int a, b, c;
3643 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3644 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3645 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3646 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3648 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3649 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3650 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3651 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3652 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3655 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3656 rtx dst, rtx src, rtx increment)
3658 enum machine_mode cmp_mode;
3659 enum machine_mode cc_mode;
3665 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3666 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3668 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3669 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3674 /* Try ADD LOGICAL WITH CARRY. */
3675 if (increment == const1_rtx)
3677 /* Determine CC mode to use. */
3678 if (cmp_code == EQ || cmp_code == NE)
3680 if (cmp_op1 != const0_rtx)
3682 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3683 NULL_RTX, 0, OPTAB_WIDEN);
3684 cmp_op1 = const0_rtx;
3687 cmp_code = cmp_code == EQ ? LEU : GTU;
3690 if (cmp_code == LTU || cmp_code == LEU)
3695 cmp_code = swap_condition (cmp_code);
3712 /* Emit comparison instruction pattern. */
3713 if (!register_operand (cmp_op0, cmp_mode))
3714 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3716 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3717 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3718 /* We use insn_invalid_p here to add clobbers if required. */
3719 ret = insn_invalid_p (emit_insn (insn));
3722 /* Emit ALC instruction pattern. */
3723 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3724 gen_rtx_REG (cc_mode, CC_REGNUM),
3727 if (src != const0_rtx)
3729 if (!register_operand (src, GET_MODE (dst)))
3730 src = force_reg (GET_MODE (dst), src);
3732 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3733 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3736 p = rtvec_alloc (2);
3738 gen_rtx_SET (VOIDmode, dst, op_res);
3740 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3741 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3746 /* Try SUBTRACT LOGICAL WITH BORROW. */
3747 if (increment == constm1_rtx)
3749 /* Determine CC mode to use. */
3750 if (cmp_code == EQ || cmp_code == NE)
3752 if (cmp_op1 != const0_rtx)
3754 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3755 NULL_RTX, 0, OPTAB_WIDEN);
3756 cmp_op1 = const0_rtx;
3759 cmp_code = cmp_code == EQ ? LEU : GTU;
3762 if (cmp_code == GTU || cmp_code == GEU)
3767 cmp_code = swap_condition (cmp_code);
3784 /* Emit comparison instruction pattern. */
3785 if (!register_operand (cmp_op0, cmp_mode))
3786 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3788 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3789 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3790 /* We use insn_invalid_p here to add clobbers if required. */
3791 ret = insn_invalid_p (emit_insn (insn));
3794 /* Emit SLB instruction pattern. */
3795 if (!register_operand (src, GET_MODE (dst)))
3796 src = force_reg (GET_MODE (dst), src);
3798 op_res = gen_rtx_MINUS (GET_MODE (dst),
3799 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3800 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3801 gen_rtx_REG (cc_mode, CC_REGNUM),
3803 p = rtvec_alloc (2);
3805 gen_rtx_SET (VOIDmode, dst, op_res);
3807 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3808 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3817 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3818 We need to emit DTP-relative relocations. */
3820 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
3823 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
3828 fputs ("\t.long\t", file);
3831 fputs ("\t.quad\t", file);
3836 output_addr_const (file, x);
3837 fputs ("@DTPOFF", file);
3840 /* In the name of slightly smaller debug output, and to cater to
3841 general assembler lossage, recognize various UNSPEC sequences
3842 and turn them back into a direct symbol reference. */
3845 s390_delegitimize_address (rtx orig_x)
3849 if (GET_CODE (x) != MEM)
3853 if (GET_CODE (x) == PLUS
3854 && GET_CODE (XEXP (x, 1)) == CONST
3855 && GET_CODE (XEXP (x, 0)) == REG
3856 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
3858 y = XEXP (XEXP (x, 1), 0);
3859 if (GET_CODE (y) == UNSPEC
3860 && XINT (y, 1) == UNSPEC_GOT)
3861 return XVECEXP (y, 0, 0);
3865 if (GET_CODE (x) == CONST)
3868 if (GET_CODE (y) == UNSPEC
3869 && XINT (y, 1) == UNSPEC_GOTENT)
3870 return XVECEXP (y, 0, 0);
3877 /* Output operand OP to stdio stream FILE.
3878 OP is an address (register + offset) which is not used to address data;
3879 instead the rightmost bits are interpreted as the value. */
3882 print_shift_count_operand (FILE *file, rtx op)
3884 HOST_WIDE_INT offset = 0;
3886 /* Shift count operands are always truncated to the 6 least significant bits and
3887 the setmem padding byte to the least 8 significant bits. Hence we can drop
3889 if (GET_CODE (op) == AND && GET_CODE (XEXP (op, 1)) == CONST_INT)
3891 if ((INTVAL (XEXP (op, 1)) & 63) != 63)
3897 /* We can have an integer constant, an address register,
3898 or a sum of the two. */
3899 if (GET_CODE (op) == CONST_INT)
3901 offset = INTVAL (op);
3904 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3906 offset = INTVAL (XEXP (op, 1));
3909 while (op && GET_CODE (op) == SUBREG)
3910 op = SUBREG_REG (op);
3915 gcc_assert (GET_CODE (op) == REG);
3916 gcc_assert (REGNO (op) < FIRST_PSEUDO_REGISTER);
3917 gcc_assert (REGNO_REG_CLASS (REGNO (op)) == ADDR_REGS);
3920 /* Offsets are constricted to twelve bits. */
3921 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
3923 fprintf (file, "(%s)", reg_names[REGNO (op)]);
3926 /* See 'get_some_local_dynamic_name'. */
3929 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
3933 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3935 x = get_pool_constant (x);
3936 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
3939 if (GET_CODE (x) == SYMBOL_REF
3940 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
3942 cfun->machine->some_ld_name = XSTR (x, 0);
3949 /* Locate some local-dynamic symbol still in use by this function
3950 so that we can print its name in local-dynamic base patterns. */
3953 get_some_local_dynamic_name (void)
3957 if (cfun->machine->some_ld_name)
3958 return cfun->machine->some_ld_name;
3960 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
3962 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
3963 return cfun->machine->some_ld_name;
3968 /* Output machine-dependent UNSPECs occurring in address constant X
3969 in assembler syntax to stdio stream FILE. Returns true if the
3970 constant X could be recognized, false otherwise. */
3973 s390_output_addr_const_extra (FILE *file, rtx x)
3975 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
3976 switch (XINT (x, 1))
3979 output_addr_const (file, XVECEXP (x, 0, 0));
3980 fprintf (file, "@GOTENT");
3983 output_addr_const (file, XVECEXP (x, 0, 0));
3984 fprintf (file, "@GOT");
3987 output_addr_const (file, XVECEXP (x, 0, 0));
3988 fprintf (file, "@GOTOFF");
3991 output_addr_const (file, XVECEXP (x, 0, 0));
3992 fprintf (file, "@PLT");
3995 output_addr_const (file, XVECEXP (x, 0, 0));
3996 fprintf (file, "@PLTOFF");
3999 output_addr_const (file, XVECEXP (x, 0, 0));
4000 fprintf (file, "@TLSGD");
4003 assemble_name (file, get_some_local_dynamic_name ());
4004 fprintf (file, "@TLSLDM");
4007 output_addr_const (file, XVECEXP (x, 0, 0));
4008 fprintf (file, "@DTPOFF");
4011 output_addr_const (file, XVECEXP (x, 0, 0));
4012 fprintf (file, "@NTPOFF");
4014 case UNSPEC_GOTNTPOFF:
4015 output_addr_const (file, XVECEXP (x, 0, 0));
4016 fprintf (file, "@GOTNTPOFF");
4018 case UNSPEC_INDNTPOFF:
4019 output_addr_const (file, XVECEXP (x, 0, 0));
4020 fprintf (file, "@INDNTPOFF");
4027 /* Output address operand ADDR in assembler syntax to
4028 stdio stream FILE. */
4031 print_operand_address (FILE *file, rtx addr)
4033 struct s390_address ad;
4035 if (!s390_decompose_address (addr, &ad)
4036 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
4037 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
4038 output_operand_lossage ("cannot decompose address");
4041 output_addr_const (file, ad.disp);
4043 fprintf (file, "0");
4045 if (ad.base && ad.indx)
4046 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4047 reg_names[REGNO (ad.base)]);
4049 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4052 /* Output operand X in assembler syntax to stdio stream FILE.
4053 CODE specified the format flag. The following format flags
4056 'C': print opcode suffix for branch condition.
4057 'D': print opcode suffix for inverse branch condition.
4058 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4059 'G': print the size of the operand in bytes.
4060 'O': print only the displacement of a memory reference.
4061 'R': print only the base register of a memory reference.
4062 'S': print S-type memory reference (base+displacement).
4063 'N': print the second word of a DImode operand.
4064 'M': print the second word of a TImode operand.
4065 'Y': print shift count operand.
4067 'b': print integer X as if it's an unsigned byte.
4068 'x': print integer X as if it's an unsigned word.
4069 'h': print integer X as if it's a signed word.
4070 'i': print the first nonzero HImode part of X.
4071 'j': print the first HImode part unequal to 0xffff of X. */
4074 print_operand (FILE *file, rtx x, int code)
4079 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4083 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4087 if (GET_CODE (x) == SYMBOL_REF)
4089 fprintf (file, "%s", ":tls_load:");
4090 output_addr_const (file, x);
4092 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4094 fprintf (file, "%s", ":tls_gdcall:");
4095 output_addr_const (file, XVECEXP (x, 0, 0));
4097 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4099 fprintf (file, "%s", ":tls_ldcall:");
4100 assemble_name (file, get_some_local_dynamic_name ());
4107 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4112 struct s390_address ad;
4115 gcc_assert (GET_CODE (x) == MEM);
4116 ret = s390_decompose_address (XEXP (x, 0), &ad);
4118 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4119 gcc_assert (!ad.indx);
4122 output_addr_const (file, ad.disp);
4124 fprintf (file, "0");
4130 struct s390_address ad;
4133 gcc_assert (GET_CODE (x) == MEM);
4134 ret = s390_decompose_address (XEXP (x, 0), &ad);
4136 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4137 gcc_assert (!ad.indx);
4140 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4142 fprintf (file, "0");
4148 struct s390_address ad;
4151 gcc_assert (GET_CODE (x) == MEM);
4152 ret = s390_decompose_address (XEXP (x, 0), &ad);
4154 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4155 gcc_assert (!ad.indx);
4158 output_addr_const (file, ad.disp);
4160 fprintf (file, "0");
4163 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4168 if (GET_CODE (x) == REG)
4169 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4170 else if (GET_CODE (x) == MEM)
4171 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4177 if (GET_CODE (x) == REG)
4178 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4179 else if (GET_CODE (x) == MEM)
4180 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4186 print_shift_count_operand (file, x);
4190 switch (GET_CODE (x))
4193 fprintf (file, "%s", reg_names[REGNO (x)]);
4197 output_address (XEXP (x, 0));
4204 output_addr_const (file, x);
4209 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4210 else if (code == 'x')
4211 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4212 else if (code == 'h')
4213 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4214 else if (code == 'i')
4215 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4216 s390_extract_part (x, HImode, 0));
4217 else if (code == 'j')
4218 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4219 s390_extract_part (x, HImode, -1));
4220 else if (code == 'k')
4221 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4222 s390_extract_part (x, SImode, 0));
4223 else if (code == 'm')
4224 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4225 s390_extract_part (x, SImode, -1));
4226 else if (code == 'o')
4227 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4229 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4233 gcc_assert (GET_MODE (x) == VOIDmode);
4235 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4236 else if (code == 'x')
4237 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4238 else if (code == 'h')
4239 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4245 fatal_insn ("UNKNOWN in print_operand !?", x);
4250 /* Target hook for assembling integer objects. We need to define it
4251 here to work a round a bug in some versions of GAS, which couldn't
4252 handle values smaller than INT_MIN when printed in decimal. */
4255 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4257 if (size == 8 && aligned_p
4258 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4260 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4264 return default_assemble_integer (x, size, aligned_p);
4267 /* Returns true if register REGNO is used for forming
4268 a memory address in expression X. */
4271 reg_used_in_mem_p (int regno, rtx x)
4273 enum rtx_code code = GET_CODE (x);
4279 if (refers_to_regno_p (regno, regno+1,
4283 else if (code == SET
4284 && GET_CODE (SET_DEST (x)) == PC)
4286 if (refers_to_regno_p (regno, regno+1,
4291 fmt = GET_RTX_FORMAT (code);
4292 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4295 && reg_used_in_mem_p (regno, XEXP (x, i)))
4298 else if (fmt[i] == 'E')
4299 for (j = 0; j < XVECLEN (x, i); j++)
4300 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4306 /* Returns true if expression DEP_RTX sets an address register
4307 used by instruction INSN to address memory. */
4310 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4314 if (GET_CODE (dep_rtx) == INSN)
4315 dep_rtx = PATTERN (dep_rtx);
4317 if (GET_CODE (dep_rtx) == SET)
4319 target = SET_DEST (dep_rtx);
4320 if (GET_CODE (target) == STRICT_LOW_PART)
4321 target = XEXP (target, 0);
4322 while (GET_CODE (target) == SUBREG)
4323 target = SUBREG_REG (target);
4325 if (GET_CODE (target) == REG)
4327 int regno = REGNO (target);
4329 if (s390_safe_attr_type (insn) == TYPE_LA)
4331 pat = PATTERN (insn);
4332 if (GET_CODE (pat) == PARALLEL)
4334 gcc_assert (XVECLEN (pat, 0) == 2);
4335 pat = XVECEXP (pat, 0, 0);
4337 gcc_assert (GET_CODE (pat) == SET);
4338 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4340 else if (get_attr_atype (insn) == ATYPE_AGEN)
4341 return reg_used_in_mem_p (regno, PATTERN (insn));
4347 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4350 s390_agen_dep_p (rtx dep_insn, rtx insn)
4352 rtx dep_rtx = PATTERN (dep_insn);
4355 if (GET_CODE (dep_rtx) == SET
4356 && addr_generation_dependency_p (dep_rtx, insn))
4358 else if (GET_CODE (dep_rtx) == PARALLEL)
4360 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4362 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4369 /* A C statement (sans semicolon) to update the integer scheduling priority
4370 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4371 reduce the priority to execute INSN later. Do not define this macro if
4372 you do not need to adjust the scheduling priorities of insns.
4374 A STD instruction should be scheduled earlier,
4375 in order to use the bypass. */
4378 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4380 if (! INSN_P (insn))
4383 if (s390_tune != PROCESSOR_2084_Z990
4384 && s390_tune != PROCESSOR_2094_Z9_109)
4387 switch (s390_safe_attr_type (insn))
4391 priority = priority << 3;
4395 priority = priority << 1;
4403 /* The number of instructions that can be issued per cycle. */
4406 s390_issue_rate (void)
4408 if (s390_tune == PROCESSOR_2084_Z990
4409 || s390_tune == PROCESSOR_2094_Z9_109)
4415 s390_first_cycle_multipass_dfa_lookahead (void)
4421 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4422 Fix up MEMs as required. */
4425 annotate_constant_pool_refs (rtx *x)
4430 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4431 || !CONSTANT_POOL_ADDRESS_P (*x));
4433 /* Literal pool references can only occur inside a MEM ... */
4434 if (GET_CODE (*x) == MEM)
4436 rtx memref = XEXP (*x, 0);
4438 if (GET_CODE (memref) == SYMBOL_REF
4439 && CONSTANT_POOL_ADDRESS_P (memref))
4441 rtx base = cfun->machine->base_reg;
4442 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4445 *x = replace_equiv_address (*x, addr);
4449 if (GET_CODE (memref) == CONST
4450 && GET_CODE (XEXP (memref, 0)) == PLUS
4451 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4452 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4453 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4455 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4456 rtx sym = XEXP (XEXP (memref, 0), 0);
4457 rtx base = cfun->machine->base_reg;
4458 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4461 *x = replace_equiv_address (*x, plus_constant (addr, off));
4466 /* ... or a load-address type pattern. */
4467 if (GET_CODE (*x) == SET)
4469 rtx addrref = SET_SRC (*x);
4471 if (GET_CODE (addrref) == SYMBOL_REF
4472 && CONSTANT_POOL_ADDRESS_P (addrref))
4474 rtx base = cfun->machine->base_reg;
4475 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4478 SET_SRC (*x) = addr;
4482 if (GET_CODE (addrref) == CONST
4483 && GET_CODE (XEXP (addrref, 0)) == PLUS
4484 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4485 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4486 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4488 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4489 rtx sym = XEXP (XEXP (addrref, 0), 0);
4490 rtx base = cfun->machine->base_reg;
4491 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4494 SET_SRC (*x) = plus_constant (addr, off);
4499 /* Annotate LTREL_BASE as well. */
4500 if (GET_CODE (*x) == UNSPEC
4501 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4503 rtx base = cfun->machine->base_reg;
4504 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4509 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4510 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4514 annotate_constant_pool_refs (&XEXP (*x, i));
4516 else if (fmt[i] == 'E')
4518 for (j = 0; j < XVECLEN (*x, i); j++)
4519 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
4524 /* Split all branches that exceed the maximum distance.
4525 Returns true if this created a new literal pool entry. */
4528 s390_split_branches (void)
4530 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4531 int new_literal = 0, ret;
4532 rtx insn, pat, tmp, target;
4535 /* We need correct insn addresses. */
4537 shorten_branches (get_insns ());
4539 /* Find all branches that exceed 64KB, and split them. */
4541 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4543 if (GET_CODE (insn) != JUMP_INSN)
4546 pat = PATTERN (insn);
4547 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
4548 pat = XVECEXP (pat, 0, 0);
4549 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
4552 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
4554 label = &SET_SRC (pat);
4556 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
4558 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
4559 label = &XEXP (SET_SRC (pat), 1);
4560 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
4561 label = &XEXP (SET_SRC (pat), 2);
4568 if (get_attr_length (insn) <= 4)
4571 /* We are going to use the return register as scratch register,
4572 make sure it will be saved/restored by the prologue/epilogue. */
4573 cfun_frame_layout.save_return_addr_p = 1;
4578 tmp = force_const_mem (Pmode, *label);
4579 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
4580 INSN_ADDRESSES_NEW (tmp, -1);
4581 annotate_constant_pool_refs (&PATTERN (tmp));
4588 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
4589 UNSPEC_LTREL_OFFSET);
4590 target = gen_rtx_CONST (Pmode, target);
4591 target = force_const_mem (Pmode, target);
4592 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
4593 INSN_ADDRESSES_NEW (tmp, -1);
4594 annotate_constant_pool_refs (&PATTERN (tmp));
4596 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
4597 cfun->machine->base_reg),
4599 target = gen_rtx_PLUS (Pmode, temp_reg, target);
4602 ret = validate_change (insn, label, target, 0);
4610 /* Find an annotated literal pool symbol referenced in RTX X,
4611 and store it at REF. Will abort if X contains references to
4612 more than one such pool symbol; multiple references to the same
4613 symbol are allowed, however.
4615 The rtx pointed to by REF must be initialized to NULL_RTX
4616 by the caller before calling this routine. */
4619 find_constant_pool_ref (rtx x, rtx *ref)
4624 /* Ignore LTREL_BASE references. */
4625 if (GET_CODE (x) == UNSPEC
4626 && XINT (x, 1) == UNSPEC_LTREL_BASE)
4628 /* Likewise POOL_ENTRY insns. */
4629 if (GET_CODE (x) == UNSPEC_VOLATILE
4630 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
4633 gcc_assert (GET_CODE (x) != SYMBOL_REF
4634 || !CONSTANT_POOL_ADDRESS_P (x));
4636 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
4638 rtx sym = XVECEXP (x, 0, 0);
4639 gcc_assert (GET_CODE (sym) == SYMBOL_REF
4640 && CONSTANT_POOL_ADDRESS_P (sym));
4642 if (*ref == NULL_RTX)
4645 gcc_assert (*ref == sym);
4650 fmt = GET_RTX_FORMAT (GET_CODE (x));
4651 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4655 find_constant_pool_ref (XEXP (x, i), ref);
4657 else if (fmt[i] == 'E')
4659 for (j = 0; j < XVECLEN (x, i); j++)
4660 find_constant_pool_ref (XVECEXP (x, i, j), ref);
4665 /* Replace every reference to the annotated literal pool
4666 symbol REF in X by its base plus OFFSET. */
4669 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
4674 gcc_assert (*x != ref);
4676 if (GET_CODE (*x) == UNSPEC
4677 && XINT (*x, 1) == UNSPEC_LTREF
4678 && XVECEXP (*x, 0, 0) == ref)
4680 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
4684 if (GET_CODE (*x) == PLUS
4685 && GET_CODE (XEXP (*x, 1)) == CONST_INT
4686 && GET_CODE (XEXP (*x, 0)) == UNSPEC
4687 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
4688 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
4690 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
4691 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
4695 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4696 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4700 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
4702 else if (fmt[i] == 'E')
4704 for (j = 0; j < XVECLEN (*x, i); j++)
4705 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
4710 /* Check whether X contains an UNSPEC_LTREL_BASE.
4711 Return its constant pool symbol if found, NULL_RTX otherwise. */
4714 find_ltrel_base (rtx x)
4719 if (GET_CODE (x) == UNSPEC
4720 && XINT (x, 1) == UNSPEC_LTREL_BASE)
4721 return XVECEXP (x, 0, 0);
4723 fmt = GET_RTX_FORMAT (GET_CODE (x));
4724 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4728 rtx fnd = find_ltrel_base (XEXP (x, i));
4732 else if (fmt[i] == 'E')
4734 for (j = 0; j < XVECLEN (x, i); j++)
4736 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
4746 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
4749 replace_ltrel_base (rtx *x)
4754 if (GET_CODE (*x) == UNSPEC
4755 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4757 *x = XVECEXP (*x, 0, 1);
4761 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4762 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4766 replace_ltrel_base (&XEXP (*x, i));
4768 else if (fmt[i] == 'E')
4770 for (j = 0; j < XVECLEN (*x, i); j++)
4771 replace_ltrel_base (&XVECEXP (*x, i, j));
4777 /* We keep a list of constants which we have to add to internal
4778 constant tables in the middle of large functions. */
4780 #define NR_C_MODES 7
4781 enum machine_mode constant_modes[NR_C_MODES] =
4792 struct constant *next;
4797 struct constant_pool
4799 struct constant_pool *next;
4804 struct constant *constants[NR_C_MODES];
4805 struct constant *execute;
4810 /* Allocate new constant_pool structure. */
4812 static struct constant_pool *
4813 s390_alloc_pool (void)
4815 struct constant_pool *pool;
4818 pool = (struct constant_pool *) xmalloc (sizeof *pool);
4820 for (i = 0; i < NR_C_MODES; i++)
4821 pool->constants[i] = NULL;
4823 pool->execute = NULL;
4824 pool->label = gen_label_rtx ();
4825 pool->first_insn = NULL_RTX;
4826 pool->pool_insn = NULL_RTX;
4827 pool->insns = BITMAP_ALLOC (NULL);
4833 /* Create new constant pool covering instructions starting at INSN
4834 and chain it to the end of POOL_LIST. */
4836 static struct constant_pool *
4837 s390_start_pool (struct constant_pool **pool_list, rtx insn)
4839 struct constant_pool *pool, **prev;
4841 pool = s390_alloc_pool ();
4842 pool->first_insn = insn;
4844 for (prev = pool_list; *prev; prev = &(*prev)->next)
4851 /* End range of instructions covered by POOL at INSN and emit
4852 placeholder insn representing the pool. */
4855 s390_end_pool (struct constant_pool *pool, rtx insn)
4857 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
4860 insn = get_last_insn ();
4862 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
4863 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
4866 /* Add INSN to the list of insns covered by POOL. */
4869 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
4871 bitmap_set_bit (pool->insns, INSN_UID (insn));
4874 /* Return pool out of POOL_LIST that covers INSN. */
4876 static struct constant_pool *
4877 s390_find_pool (struct constant_pool *pool_list, rtx insn)
4879 struct constant_pool *pool;
4881 for (pool = pool_list; pool; pool = pool->next)
4882 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
4888 /* Add constant VAL of mode MODE to the constant pool POOL. */
4891 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
4896 for (i = 0; i < NR_C_MODES; i++)
4897 if (constant_modes[i] == mode)
4899 gcc_assert (i != NR_C_MODES);
4901 for (c = pool->constants[i]; c != NULL; c = c->next)
4902 if (rtx_equal_p (val, c->value))
4907 c = (struct constant *) xmalloc (sizeof *c);
4909 c->label = gen_label_rtx ();
4910 c->next = pool->constants[i];
4911 pool->constants[i] = c;
4912 pool->size += GET_MODE_SIZE (mode);
4916 /* Find constant VAL of mode MODE in the constant pool POOL.
4917 Return an RTX describing the distance from the start of
4918 the pool to the location of the new constant. */
4921 s390_find_constant (struct constant_pool *pool, rtx val,
4922 enum machine_mode mode)
4928 for (i = 0; i < NR_C_MODES; i++)
4929 if (constant_modes[i] == mode)
4931 gcc_assert (i != NR_C_MODES);
4933 for (c = pool->constants[i]; c != NULL; c = c->next)
4934 if (rtx_equal_p (val, c->value))
4939 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
4940 gen_rtx_LABEL_REF (Pmode, pool->label));
4941 offset = gen_rtx_CONST (Pmode, offset);
4945 /* Check whether INSN is an execute. Return the label_ref to its
4946 execute target template if so, NULL_RTX otherwise. */
4949 s390_execute_label (rtx insn)
4951 if (GET_CODE (insn) == INSN
4952 && GET_CODE (PATTERN (insn)) == PARALLEL
4953 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
4954 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
4955 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
4960 /* Add execute target for INSN to the constant pool POOL. */
4963 s390_add_execute (struct constant_pool *pool, rtx insn)
4967 for (c = pool->execute; c != NULL; c = c->next)
4968 if (INSN_UID (insn) == INSN_UID (c->value))
4973 c = (struct constant *) xmalloc (sizeof *c);
4975 c->label = gen_label_rtx ();
4976 c->next = pool->execute;
4982 /* Find execute target for INSN in the constant pool POOL.
4983 Return an RTX describing the distance from the start of
4984 the pool to the location of the execute target. */
4987 s390_find_execute (struct constant_pool *pool, rtx insn)
4992 for (c = pool->execute; c != NULL; c = c->next)
4993 if (INSN_UID (insn) == INSN_UID (c->value))
4998 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
4999 gen_rtx_LABEL_REF (Pmode, pool->label));
5000 offset = gen_rtx_CONST (Pmode, offset);
5004 /* For an execute INSN, extract the execute target template. */
5007 s390_execute_target (rtx insn)
5009 rtx pattern = PATTERN (insn);
5010 gcc_assert (s390_execute_label (insn));
5012 if (XVECLEN (pattern, 0) == 2)
5014 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5018 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5021 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5022 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5024 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5030 /* Indicate that INSN cannot be duplicated. This is the case for
5031 execute insns that carry a unique label. */
5034 s390_cannot_copy_insn_p (rtx insn)
5036 rtx label = s390_execute_label (insn);
5037 return label && label != const0_rtx;
5040 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5041 do not emit the pool base label. */
5044 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5047 rtx insn = pool->pool_insn;
5050 /* Switch to rodata section. */
5051 if (TARGET_CPU_ZARCH)
5053 insn = emit_insn_after (gen_pool_section_start (), insn);
5054 INSN_ADDRESSES_NEW (insn, -1);
5057 /* Ensure minimum pool alignment. */
5058 if (TARGET_CPU_ZARCH)
5059 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5061 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5062 INSN_ADDRESSES_NEW (insn, -1);
5064 /* Emit pool base label. */
5067 insn = emit_label_after (pool->label, insn);
5068 INSN_ADDRESSES_NEW (insn, -1);
5071 /* Dump constants in descending alignment requirement order,
5072 ensuring proper alignment for every constant. */
5073 for (i = 0; i < NR_C_MODES; i++)
5074 for (c = pool->constants[i]; c; c = c->next)
5076 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5077 rtx value = c->value;
5078 if (GET_CODE (value) == CONST
5079 && GET_CODE (XEXP (value, 0)) == UNSPEC
5080 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5081 && XVECLEN (XEXP (value, 0), 0) == 1)
5083 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5084 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5085 value = gen_rtx_CONST (VOIDmode, value);
5088 insn = emit_label_after (c->label, insn);
5089 INSN_ADDRESSES_NEW (insn, -1);
5091 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5092 gen_rtvec (1, value),
5093 UNSPECV_POOL_ENTRY);
5094 insn = emit_insn_after (value, insn);
5095 INSN_ADDRESSES_NEW (insn, -1);
5098 /* Ensure minimum alignment for instructions. */
5099 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5100 INSN_ADDRESSES_NEW (insn, -1);
5102 /* Output in-pool execute template insns. */
5103 for (c = pool->execute; c; c = c->next)
5105 insn = emit_label_after (c->label, insn);
5106 INSN_ADDRESSES_NEW (insn, -1);
5108 insn = emit_insn_after (s390_execute_target (c->value), insn);
5109 INSN_ADDRESSES_NEW (insn, -1);
5112 /* Switch back to previous section. */
5113 if (TARGET_CPU_ZARCH)
5115 insn = emit_insn_after (gen_pool_section_end (), insn);
5116 INSN_ADDRESSES_NEW (insn, -1);
5119 insn = emit_barrier_after (insn);
5120 INSN_ADDRESSES_NEW (insn, -1);
5122 /* Remove placeholder insn. */
5123 remove_insn (pool->pool_insn);
5126 /* Free all memory used by POOL. */
5129 s390_free_pool (struct constant_pool *pool)
5131 struct constant *c, *next;
5134 for (i = 0; i < NR_C_MODES; i++)
5135 for (c = pool->constants[i]; c; c = next)
5141 for (c = pool->execute; c; c = next)
5147 BITMAP_FREE (pool->insns);
5152 /* Collect main literal pool. Return NULL on overflow. */
5154 static struct constant_pool *
5155 s390_mainpool_start (void)
5157 struct constant_pool *pool;
5160 pool = s390_alloc_pool ();
5162 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5164 if (GET_CODE (insn) == INSN
5165 && GET_CODE (PATTERN (insn)) == SET
5166 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5167 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5169 gcc_assert (!pool->pool_insn);
5170 pool->pool_insn = insn;
5173 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5175 s390_add_execute (pool, insn);
5177 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5179 rtx pool_ref = NULL_RTX;
5180 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5183 rtx constant = get_pool_constant (pool_ref);
5184 enum machine_mode mode = get_pool_mode (pool_ref);
5185 s390_add_constant (pool, constant, mode);
5190 gcc_assert (pool->pool_insn || pool->size == 0);
5192 if (pool->size >= 4096)
5194 /* We're going to chunkify the pool, so remove the main
5195 pool placeholder insn. */
5196 remove_insn (pool->pool_insn);
5198 s390_free_pool (pool);
5205 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5206 Modify the current function to output the pool constants as well as
5207 the pool register setup instruction. */
5210 s390_mainpool_finish (struct constant_pool *pool)
5212 rtx base_reg = cfun->machine->base_reg;
5215 /* If the pool is empty, we're done. */
5216 if (pool->size == 0)
5218 /* We don't actually need a base register after all. */
5219 cfun->machine->base_reg = NULL_RTX;
5221 if (pool->pool_insn)
5222 remove_insn (pool->pool_insn);
5223 s390_free_pool (pool);
5227 /* We need correct insn addresses. */
5228 shorten_branches (get_insns ());
5230 /* On zSeries, we use a LARL to load the pool register. The pool is
5231 located in the .rodata section, so we emit it after the function. */
5232 if (TARGET_CPU_ZARCH)
5234 insn = gen_main_base_64 (base_reg, pool->label);
5235 insn = emit_insn_after (insn, pool->pool_insn);
5236 INSN_ADDRESSES_NEW (insn, -1);
5237 remove_insn (pool->pool_insn);
5239 insn = get_last_insn ();
5240 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5241 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5243 s390_dump_pool (pool, 0);
5246 /* On S/390, if the total size of the function's code plus literal pool
5247 does not exceed 4096 bytes, we use BASR to set up a function base
5248 pointer, and emit the literal pool at the end of the function. */
5249 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5250 + pool->size + 8 /* alignment slop */ < 4096)
5252 insn = gen_main_base_31_small (base_reg, pool->label);
5253 insn = emit_insn_after (insn, pool->pool_insn);
5254 INSN_ADDRESSES_NEW (insn, -1);
5255 remove_insn (pool->pool_insn);
5257 insn = emit_label_after (pool->label, insn);
5258 INSN_ADDRESSES_NEW (insn, -1);
5260 insn = get_last_insn ();
5261 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5262 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5264 s390_dump_pool (pool, 1);
5267 /* Otherwise, we emit an inline literal pool and use BASR to branch
5268 over it, setting up the pool register at the same time. */
5271 rtx pool_end = gen_label_rtx ();
5273 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5274 insn = emit_insn_after (insn, pool->pool_insn);
5275 INSN_ADDRESSES_NEW (insn, -1);
5276 remove_insn (pool->pool_insn);
5278 insn = emit_label_after (pool->label, insn);
5279 INSN_ADDRESSES_NEW (insn, -1);
5281 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5282 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5284 insn = emit_label_after (pool_end, pool->pool_insn);
5285 INSN_ADDRESSES_NEW (insn, -1);
5287 s390_dump_pool (pool, 1);
5291 /* Replace all literal pool references. */
5293 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5296 replace_ltrel_base (&PATTERN (insn));
5298 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5300 rtx addr, pool_ref = NULL_RTX;
5301 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5304 if (s390_execute_label (insn))
5305 addr = s390_find_execute (pool, insn);
5307 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5308 get_pool_mode (pool_ref));
5310 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5311 INSN_CODE (insn) = -1;
5317 /* Free the pool. */
5318 s390_free_pool (pool);
5321 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5322 We have decided we cannot use this pool, so revert all changes
5323 to the current function that were done by s390_mainpool_start. */
5325 s390_mainpool_cancel (struct constant_pool *pool)
5327 /* We didn't actually change the instruction stream, so simply
5328 free the pool memory. */
5329 s390_free_pool (pool);
5333 /* Chunkify the literal pool. */
5335 #define S390_POOL_CHUNK_MIN 0xc00
5336 #define S390_POOL_CHUNK_MAX 0xe00
5338 static struct constant_pool *
5339 s390_chunkify_start (void)
5341 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5344 rtx pending_ltrel = NULL_RTX;
5347 rtx (*gen_reload_base) (rtx, rtx) =
5348 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5351 /* We need correct insn addresses. */
5353 shorten_branches (get_insns ());
5355 /* Scan all insns and move literals to pool chunks. */
5357 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5359 /* Check for pending LTREL_BASE. */
5362 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5365 gcc_assert (ltrel_base == pending_ltrel);
5366 pending_ltrel = NULL_RTX;
5370 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5373 curr_pool = s390_start_pool (&pool_list, insn);
5375 s390_add_execute (curr_pool, insn);
5376 s390_add_pool_insn (curr_pool, insn);
5378 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5380 rtx pool_ref = NULL_RTX;
5381 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5384 rtx constant = get_pool_constant (pool_ref);
5385 enum machine_mode mode = get_pool_mode (pool_ref);
5388 curr_pool = s390_start_pool (&pool_list, insn);
5390 s390_add_constant (curr_pool, constant, mode);
5391 s390_add_pool_insn (curr_pool, insn);
5393 /* Don't split the pool chunk between a LTREL_OFFSET load
5394 and the corresponding LTREL_BASE. */
5395 if (GET_CODE (constant) == CONST
5396 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5397 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5399 gcc_assert (!pending_ltrel);
5400 pending_ltrel = pool_ref;
5405 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5408 s390_add_pool_insn (curr_pool, insn);
5409 /* An LTREL_BASE must follow within the same basic block. */
5410 gcc_assert (!pending_ltrel);
5414 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5415 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5418 if (TARGET_CPU_ZARCH)
5420 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5423 s390_end_pool (curr_pool, NULL_RTX);
5428 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5429 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5432 /* We will later have to insert base register reload insns.
5433 Those will have an effect on code size, which we need to
5434 consider here. This calculation makes rather pessimistic
5435 worst-case assumptions. */
5436 if (GET_CODE (insn) == CODE_LABEL)
5439 if (chunk_size < S390_POOL_CHUNK_MIN
5440 && curr_pool->size < S390_POOL_CHUNK_MIN)
5443 /* Pool chunks can only be inserted after BARRIERs ... */
5444 if (GET_CODE (insn) == BARRIER)
5446 s390_end_pool (curr_pool, insn);
5451 /* ... so if we don't find one in time, create one. */
5452 else if ((chunk_size > S390_POOL_CHUNK_MAX
5453 || curr_pool->size > S390_POOL_CHUNK_MAX))
5455 rtx label, jump, barrier;
5457 /* We can insert the barrier only after a 'real' insn. */
5458 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5460 if (get_attr_length (insn) == 0)
5463 /* Don't separate LTREL_BASE from the corresponding
5464 LTREL_OFFSET load. */
5468 label = gen_label_rtx ();
5469 jump = emit_jump_insn_after (gen_jump (label), insn);
5470 barrier = emit_barrier_after (jump);
5471 insn = emit_label_after (label, barrier);
5472 JUMP_LABEL (jump) = label;
5473 LABEL_NUSES (label) = 1;
5475 INSN_ADDRESSES_NEW (jump, -1);
5476 INSN_ADDRESSES_NEW (barrier, -1);
5477 INSN_ADDRESSES_NEW (insn, -1);
5479 s390_end_pool (curr_pool, barrier);
5487 s390_end_pool (curr_pool, NULL_RTX);
5488 gcc_assert (!pending_ltrel);
5490 /* Find all labels that are branched into
5491 from an insn belonging to a different chunk. */
5493 far_labels = BITMAP_ALLOC (NULL);
5495 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5497 /* Labels marked with LABEL_PRESERVE_P can be target
5498 of non-local jumps, so we have to mark them.
5499 The same holds for named labels.
5501 Don't do that, however, if it is the label before
5504 if (GET_CODE (insn) == CODE_LABEL
5505 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5507 rtx vec_insn = next_real_insn (insn);
5508 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5509 PATTERN (vec_insn) : NULL_RTX;
5511 || !(GET_CODE (vec_pat) == ADDR_VEC
5512 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5513 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5516 /* If we have a direct jump (conditional or unconditional)
5517 or a casesi jump, check all potential targets. */
5518 else if (GET_CODE (insn) == JUMP_INSN)
5520 rtx pat = PATTERN (insn);
5521 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5522 pat = XVECEXP (pat, 0, 0);
5524 if (GET_CODE (pat) == SET)
5526 rtx label = JUMP_LABEL (insn);
5529 if (s390_find_pool (pool_list, label)
5530 != s390_find_pool (pool_list, insn))
5531 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5534 else if (GET_CODE (pat) == PARALLEL
5535 && XVECLEN (pat, 0) == 2
5536 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5537 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
5538 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
5540 /* Find the jump table used by this casesi jump. */
5541 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
5542 rtx vec_insn = next_real_insn (vec_label);
5543 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5544 PATTERN (vec_insn) : NULL_RTX;
5546 && (GET_CODE (vec_pat) == ADDR_VEC
5547 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5549 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
5551 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
5553 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
5555 if (s390_find_pool (pool_list, label)
5556 != s390_find_pool (pool_list, insn))
5557 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5564 /* Insert base register reload insns before every pool. */
5566 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5568 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5570 rtx insn = curr_pool->first_insn;
5571 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
5574 /* Insert base register reload insns at every far label. */
5576 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5577 if (GET_CODE (insn) == CODE_LABEL
5578 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
5580 struct constant_pool *pool = s390_find_pool (pool_list, insn);
5583 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5585 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
5590 BITMAP_FREE (far_labels);
5593 /* Recompute insn addresses. */
5595 init_insn_lengths ();
5596 shorten_branches (get_insns ());
5601 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
5602 After we have decided to use this list, finish implementing
5603 all changes to the current function as required. */
5606 s390_chunkify_finish (struct constant_pool *pool_list)
5608 struct constant_pool *curr_pool = NULL;
5612 /* Replace all literal pool references. */
5614 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5617 replace_ltrel_base (&PATTERN (insn));
5619 curr_pool = s390_find_pool (pool_list, insn);
5623 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5625 rtx addr, pool_ref = NULL_RTX;
5626 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5629 if (s390_execute_label (insn))
5630 addr = s390_find_execute (curr_pool, insn);
5632 addr = s390_find_constant (curr_pool,
5633 get_pool_constant (pool_ref),
5634 get_pool_mode (pool_ref));
5636 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5637 INSN_CODE (insn) = -1;
5642 /* Dump out all literal pools. */
5644 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5645 s390_dump_pool (curr_pool, 0);
5647 /* Free pool list. */
5651 struct constant_pool *next = pool_list->next;
5652 s390_free_pool (pool_list);
5657 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
5658 We have decided we cannot use this list, so revert all changes
5659 to the current function that were done by s390_chunkify_start. */
5662 s390_chunkify_cancel (struct constant_pool *pool_list)
5664 struct constant_pool *curr_pool = NULL;
5667 /* Remove all pool placeholder insns. */
5669 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5671 /* Did we insert an extra barrier? Remove it. */
5672 rtx barrier = PREV_INSN (curr_pool->pool_insn);
5673 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
5674 rtx label = NEXT_INSN (curr_pool->pool_insn);
5676 if (jump && GET_CODE (jump) == JUMP_INSN
5677 && barrier && GET_CODE (barrier) == BARRIER
5678 && label && GET_CODE (label) == CODE_LABEL
5679 && GET_CODE (PATTERN (jump)) == SET
5680 && SET_DEST (PATTERN (jump)) == pc_rtx
5681 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
5682 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
5685 remove_insn (barrier);
5686 remove_insn (label);
5689 remove_insn (curr_pool->pool_insn);
5692 /* Remove all base register reload insns. */
5694 for (insn = get_insns (); insn; )
5696 rtx next_insn = NEXT_INSN (insn);
5698 if (GET_CODE (insn) == INSN
5699 && GET_CODE (PATTERN (insn)) == SET
5700 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
5701 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
5707 /* Free pool list. */
5711 struct constant_pool *next = pool_list->next;
5712 s390_free_pool (pool_list);
5718 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
5721 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
5725 switch (GET_MODE_CLASS (mode))
5728 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
5730 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
5731 assemble_real (r, mode, align);
5735 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
5744 /* Return an RTL expression representing the value of the return address
5745 for the frame COUNT steps up from the current frame. FRAME is the
5746 frame pointer of that frame. */
5749 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
5754 /* Without backchain, we fail for all but the current frame. */
5756 if (!TARGET_BACKCHAIN && count > 0)
5759 /* For the current frame, we need to make sure the initial
5760 value of RETURN_REGNUM is actually saved. */
5764 /* On non-z architectures branch splitting could overwrite r14. */
5765 if (TARGET_CPU_ZARCH)
5766 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
5769 cfun_frame_layout.save_return_addr_p = true;
5770 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
5774 if (TARGET_PACKED_STACK)
5775 offset = -2 * UNITS_PER_WORD;
5777 offset = RETURN_REGNUM * UNITS_PER_WORD;
5779 addr = plus_constant (frame, offset);
5780 addr = memory_address (Pmode, addr);
5781 return gen_rtx_MEM (Pmode, addr);
5784 /* Return an RTL expression representing the back chain stored in
5785 the current stack frame. */
5788 s390_back_chain_rtx (void)
5792 gcc_assert (TARGET_BACKCHAIN);
5794 if (TARGET_PACKED_STACK)
5795 chain = plus_constant (stack_pointer_rtx,
5796 STACK_POINTER_OFFSET - UNITS_PER_WORD);
5798 chain = stack_pointer_rtx;
5800 chain = gen_rtx_MEM (Pmode, chain);
5804 /* Find first call clobbered register unused in a function.
5805 This could be used as base register in a leaf function
5806 or for holding the return address before epilogue. */
5809 find_unused_clobbered_reg (void)
5812 for (i = 0; i < 6; i++)
5813 if (!regs_ever_live[i])
5819 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
5820 clobbered hard regs in SETREG. */
5823 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
5825 int *regs_ever_clobbered = (int *)data;
5826 unsigned int i, regno;
5827 enum machine_mode mode = GET_MODE (setreg);
5829 if (GET_CODE (setreg) == SUBREG)
5831 rtx inner = SUBREG_REG (setreg);
5832 if (!GENERAL_REG_P (inner))
5834 regno = subreg_regno (setreg);
5836 else if (GENERAL_REG_P (setreg))
5837 regno = REGNO (setreg);
5842 i < regno + HARD_REGNO_NREGS (regno, mode);
5844 regs_ever_clobbered[i] = 1;
5847 /* Walks through all basic blocks of the current function looking
5848 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
5849 of the passed integer array REGS_EVER_CLOBBERED are set to one for
5850 each of those regs. */
5853 s390_regs_ever_clobbered (int *regs_ever_clobbered)
5859 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
5861 /* For non-leaf functions we have to consider all call clobbered regs to be
5863 if (!current_function_is_leaf)
5865 for (i = 0; i < 16; i++)
5866 regs_ever_clobbered[i] = call_really_used_regs[i];
5869 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
5870 this work is done by liveness analysis (mark_regs_live_at_end).
5871 Special care is needed for functions containing landing pads. Landing pads
5872 may use the eh registers, but the code which sets these registers is not
5873 contained in that function. Hence s390_regs_ever_clobbered is not able to
5874 deal with this automatically. */
5875 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
5876 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
5877 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
5879 /* For nonlocal gotos all call-saved registers have to be saved.
5880 This flag is also set for the unwinding code in libgcc.
5881 See expand_builtin_unwind_init. For regs_ever_live this is done by
5883 if (current_function_has_nonlocal_label)
5884 for (i = 0; i < 16; i++)
5885 if (!call_really_used_regs[i])
5886 regs_ever_clobbered[i] = 1;
5888 FOR_EACH_BB (cur_bb)
5890 FOR_BB_INSNS (cur_bb, cur_insn)
5892 if (INSN_P (cur_insn))
5893 note_stores (PATTERN (cur_insn),
5894 s390_reg_clobbered_rtx,
5895 regs_ever_clobbered);
5900 /* Determine the frame area which actually has to be accessed
5901 in the function epilogue. The values are stored at the
5902 given pointers AREA_BOTTOM (address of the lowest used stack
5903 address) and AREA_TOP (address of the first item which does
5904 not belong to the stack frame). */
5907 s390_frame_area (int *area_bottom, int *area_top)
5915 if (cfun_frame_layout.first_restore_gpr != -1)
5917 b = (cfun_frame_layout.gprs_offset
5918 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
5919 t = b + (cfun_frame_layout.last_restore_gpr
5920 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
5923 if (TARGET_64BIT && cfun_save_high_fprs_p)
5925 b = MIN (b, cfun_frame_layout.f8_offset);
5926 t = MAX (t, (cfun_frame_layout.f8_offset
5927 + cfun_frame_layout.high_fprs * 8));
5931 for (i = 2; i < 4; i++)
5932 if (cfun_fpr_bit_p (i))
5934 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
5935 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
5942 /* Fill cfun->machine with info about register usage of current function.
5943 Return in CLOBBERED_REGS which GPRs are currently considered set. */
5946 s390_register_info (int clobbered_regs[])
5950 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
5951 cfun_frame_layout.fpr_bitmap = 0;
5952 cfun_frame_layout.high_fprs = 0;
5954 for (i = 24; i < 32; i++)
5955 if (regs_ever_live[i] && !global_regs[i])
5957 cfun_set_fpr_bit (i - 16);
5958 cfun_frame_layout.high_fprs++;
5961 /* Find first and last gpr to be saved. We trust regs_ever_live
5962 data, except that we don't save and restore global registers.
5964 Also, all registers with special meaning to the compiler need
5965 to be handled extra. */
5967 s390_regs_ever_clobbered (clobbered_regs);
5969 for (i = 0; i < 16; i++)
5970 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
5972 if (frame_pointer_needed)
5973 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
5976 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
5977 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
5979 clobbered_regs[BASE_REGNUM]
5980 |= (cfun->machine->base_reg
5981 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
5983 clobbered_regs[RETURN_REGNUM]
5984 |= (!current_function_is_leaf
5985 || TARGET_TPF_PROFILING
5986 || cfun->machine->split_branches_pending_p
5987 || cfun_frame_layout.save_return_addr_p
5988 || current_function_calls_eh_return
5989 || current_function_stdarg);
5991 clobbered_regs[STACK_POINTER_REGNUM]
5992 |= (!current_function_is_leaf
5993 || TARGET_TPF_PROFILING
5994 || cfun_save_high_fprs_p
5995 || get_frame_size () > 0
5996 || current_function_calls_alloca
5997 || current_function_stdarg);
5999 for (i = 6; i < 16; i++)
6000 if (clobbered_regs[i])
6002 for (j = 15; j > i; j--)
6003 if (clobbered_regs[j])
6008 /* Nothing to save/restore. */
6009 cfun_frame_layout.first_save_gpr = -1;
6010 cfun_frame_layout.first_restore_gpr = -1;
6011 cfun_frame_layout.last_save_gpr = -1;
6012 cfun_frame_layout.last_restore_gpr = -1;
6016 /* Save / Restore from gpr i to j. */
6017 cfun_frame_layout.first_save_gpr = i;
6018 cfun_frame_layout.first_restore_gpr = i;
6019 cfun_frame_layout.last_save_gpr = j;
6020 cfun_frame_layout.last_restore_gpr = j;
6023 if (current_function_stdarg)
6025 /* Varargs functions need to save gprs 2 to 6. */
6026 if (cfun->va_list_gpr_size
6027 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6029 int min_gpr = current_function_args_info.gprs;
6030 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6031 if (max_gpr > GP_ARG_NUM_REG)
6032 max_gpr = GP_ARG_NUM_REG;
6034 if (cfun_frame_layout.first_save_gpr == -1
6035 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6036 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6038 if (cfun_frame_layout.last_save_gpr == -1
6039 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6040 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6043 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6044 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6045 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6047 int min_fpr = current_function_args_info.fprs;
6048 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6049 if (max_fpr > FP_ARG_NUM_REG)
6050 max_fpr = FP_ARG_NUM_REG;
6052 /* ??? This is currently required to ensure proper location
6053 of the fpr save slots within the va_list save area. */
6054 if (TARGET_PACKED_STACK)
6057 for (i = min_fpr; i < max_fpr; i++)
6058 cfun_set_fpr_bit (i);
6063 for (i = 2; i < 4; i++)
6064 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6065 cfun_set_fpr_bit (i);
6068 /* Fill cfun->machine with info about frame of current function. */
6071 s390_frame_info (void)
6075 cfun_frame_layout.frame_size = get_frame_size ();
6076 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6077 fatal_error ("total size of local variables exceeds architecture limit");
6079 if (!TARGET_PACKED_STACK)
6081 cfun_frame_layout.backchain_offset = 0;
6082 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6083 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6084 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6085 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr
6088 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6090 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6092 cfun_frame_layout.gprs_offset
6093 = (cfun_frame_layout.backchain_offset
6094 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr + 1)
6099 cfun_frame_layout.f4_offset
6100 = (cfun_frame_layout.gprs_offset
6101 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6103 cfun_frame_layout.f0_offset
6104 = (cfun_frame_layout.f4_offset
6105 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6109 /* On 31 bit we have to care about alignment of the
6110 floating point regs to provide fastest access. */
6111 cfun_frame_layout.f0_offset
6112 = ((cfun_frame_layout.gprs_offset
6113 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6114 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6116 cfun_frame_layout.f4_offset
6117 = (cfun_frame_layout.f0_offset
6118 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6121 else /* no backchain */
6123 cfun_frame_layout.f4_offset
6124 = (STACK_POINTER_OFFSET
6125 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6127 cfun_frame_layout.f0_offset
6128 = (cfun_frame_layout.f4_offset
6129 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6131 cfun_frame_layout.gprs_offset
6132 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6135 if (current_function_is_leaf
6136 && !TARGET_TPF_PROFILING
6137 && cfun_frame_layout.frame_size == 0
6138 && !cfun_save_high_fprs_p
6139 && !current_function_calls_alloca
6140 && !current_function_stdarg)
6143 if (!TARGET_PACKED_STACK)
6144 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6145 + current_function_outgoing_args_size
6146 + cfun_frame_layout.high_fprs * 8);
6149 if (TARGET_BACKCHAIN)
6150 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6152 /* No alignment trouble here because f8-f15 are only saved under
6154 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6155 cfun_frame_layout.f4_offset),
6156 cfun_frame_layout.gprs_offset)
6157 - cfun_frame_layout.high_fprs * 8);
6159 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6161 for (i = 0; i < 8; i++)
6162 if (cfun_fpr_bit_p (i))
6163 cfun_frame_layout.frame_size += 8;
6165 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6167 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6168 the frame size to sustain 8 byte alignment of stack frames. */
6169 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6170 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6171 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6173 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6177 /* Generate frame layout. Fills in register and frame data for the current
6178 function in cfun->machine. This routine can be called multiple times;
6179 it will re-do the complete frame layout every time. */
6182 s390_init_frame_layout (void)
6184 HOST_WIDE_INT frame_size;
6186 int clobbered_regs[16];
6188 /* On S/390 machines, we may need to perform branch splitting, which
6189 will require both base and return address register. We have no
6190 choice but to assume we're going to need them until right at the
6191 end of the machine dependent reorg phase. */
6192 if (!TARGET_CPU_ZARCH)
6193 cfun->machine->split_branches_pending_p = true;
6197 frame_size = cfun_frame_layout.frame_size;
6199 /* Try to predict whether we'll need the base register. */
6200 base_used = cfun->machine->split_branches_pending_p
6201 || current_function_uses_const_pool
6202 || (!DISP_IN_RANGE (-frame_size)
6203 && !CONST_OK_FOR_K (-frame_size));
6205 /* Decide which register to use as literal pool base. In small
6206 leaf functions, try to use an unused call-clobbered register
6207 as base register to avoid save/restore overhead. */
6209 cfun->machine->base_reg = NULL_RTX;
6210 else if (current_function_is_leaf && !regs_ever_live[5])
6211 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6213 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6215 s390_register_info (clobbered_regs);
6218 while (frame_size != cfun_frame_layout.frame_size);
6221 /* Update frame layout. Recompute actual register save data based on
6222 current info and update regs_ever_live for the special registers.
6223 May be called multiple times, but may never cause *more* registers
6224 to be saved than s390_init_frame_layout allocated room for. */
6227 s390_update_frame_layout (void)
6229 int clobbered_regs[16];
6231 s390_register_info (clobbered_regs);
6233 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6234 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6235 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6237 if (cfun->machine->base_reg)
6238 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6241 /* Return true if register FROM can be eliminated via register TO. */
6244 s390_can_eliminate (int from, int to)
6246 gcc_assert (to == STACK_POINTER_REGNUM
6247 || to == HARD_FRAME_POINTER_REGNUM);
6249 gcc_assert (from == FRAME_POINTER_REGNUM
6250 || from == ARG_POINTER_REGNUM
6251 || from == RETURN_ADDRESS_POINTER_REGNUM);
6253 /* Make sure we actually saved the return address. */
6254 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6255 if (!current_function_calls_eh_return
6256 && !current_function_stdarg
6257 && !cfun_frame_layout.save_return_addr_p)
6263 /* Return offset between register FROM and TO initially after prolog. */
6266 s390_initial_elimination_offset (int from, int to)
6268 HOST_WIDE_INT offset;
6271 /* ??? Why are we called for non-eliminable pairs? */
6272 if (!s390_can_eliminate (from, to))
6277 case FRAME_POINTER_REGNUM:
6278 offset = (get_frame_size()
6279 + STACK_POINTER_OFFSET
6280 + current_function_outgoing_args_size);
6283 case ARG_POINTER_REGNUM:
6284 s390_init_frame_layout ();
6285 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6288 case RETURN_ADDRESS_POINTER_REGNUM:
6289 s390_init_frame_layout ();
6290 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr;
6291 gcc_assert (index >= 0);
6292 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6293 offset += index * UNITS_PER_WORD;
6303 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6304 to register BASE. Return generated insn. */
6307 save_fpr (rtx base, int offset, int regnum)
6310 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6312 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6313 set_mem_alias_set (addr, get_varargs_alias_set ());
6315 set_mem_alias_set (addr, get_frame_alias_set ());
6317 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6320 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6321 to register BASE. Return generated insn. */
6324 restore_fpr (rtx base, int offset, int regnum)
6327 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6328 set_mem_alias_set (addr, get_frame_alias_set ());
6330 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6333 /* Generate insn to save registers FIRST to LAST into
6334 the register save area located at offset OFFSET
6335 relative to register BASE. */
6338 save_gprs (rtx base, int offset, int first, int last)
6340 rtx addr, insn, note;
6343 addr = plus_constant (base, offset);
6344 addr = gen_rtx_MEM (Pmode, addr);
6346 set_mem_alias_set (addr, get_frame_alias_set ());
6348 /* Special-case single register. */
6352 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6354 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6356 RTX_FRAME_RELATED_P (insn) = 1;
6361 insn = gen_store_multiple (addr,
6362 gen_rtx_REG (Pmode, first),
6363 GEN_INT (last - first + 1));
6365 if (first <= 6 && current_function_stdarg)
6366 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6368 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6371 set_mem_alias_set (mem, get_varargs_alias_set ());
6374 /* We need to set the FRAME_RELATED flag on all SETs
6375 inside the store-multiple pattern.
6377 However, we must not emit DWARF records for registers 2..5
6378 if they are stored for use by variable arguments ...
6380 ??? Unfortunately, it is not enough to simply not the
6381 FRAME_RELATED flags for those SETs, because the first SET
6382 of the PARALLEL is always treated as if it had the flag
6383 set, even if it does not. Therefore we emit a new pattern
6384 without those registers as REG_FRAME_RELATED_EXPR note. */
6388 rtx pat = PATTERN (insn);
6390 for (i = 0; i < XVECLEN (pat, 0); i++)
6391 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6392 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6394 RTX_FRAME_RELATED_P (insn) = 1;
6398 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6399 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6400 gen_rtx_REG (Pmode, 6),
6401 GEN_INT (last - 6 + 1));
6402 note = PATTERN (note);
6405 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6406 note, REG_NOTES (insn));
6408 for (i = 0; i < XVECLEN (note, 0); i++)
6409 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6410 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6412 RTX_FRAME_RELATED_P (insn) = 1;
6418 /* Generate insn to restore registers FIRST to LAST from
6419 the register save area located at offset OFFSET
6420 relative to register BASE. */
6423 restore_gprs (rtx base, int offset, int first, int last)
6427 addr = plus_constant (base, offset);
6428 addr = gen_rtx_MEM (Pmode, addr);
6429 set_mem_alias_set (addr, get_frame_alias_set ());
6431 /* Special-case single register. */
6435 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6437 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6442 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6444 GEN_INT (last - first + 1));
6448 /* Return insn sequence to load the GOT register. */
6450 static GTY(()) rtx got_symbol;
6452 s390_load_got (void)
6458 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6459 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
6464 if (TARGET_CPU_ZARCH)
6466 emit_move_insn (pic_offset_table_rtx, got_symbol);
6472 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
6473 UNSPEC_LTREL_OFFSET);
6474 offset = gen_rtx_CONST (Pmode, offset);
6475 offset = force_const_mem (Pmode, offset);
6477 emit_move_insn (pic_offset_table_rtx, offset);
6479 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
6481 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
6483 emit_move_insn (pic_offset_table_rtx, offset);
6486 insns = get_insns ();
6491 /* Expand the prologue into a bunch of separate insns. */
6494 s390_emit_prologue (void)
6502 /* Complete frame layout. */
6504 s390_update_frame_layout ();
6506 /* Annotate all constant pool references to let the scheduler know
6507 they implicitly use the base register. */
6509 push_topmost_sequence ();
6511 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6513 annotate_constant_pool_refs (&PATTERN (insn));
6515 pop_topmost_sequence ();
6517 /* Choose best register to use for temp use within prologue.
6518 See below for why TPF must use the register 1. */
6520 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
6521 && !current_function_is_leaf
6522 && !TARGET_TPF_PROFILING)
6523 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6525 temp_reg = gen_rtx_REG (Pmode, 1);
6527 /* Save call saved gprs. */
6528 if (cfun_frame_layout.first_save_gpr != -1)
6530 insn = save_gprs (stack_pointer_rtx,
6531 cfun_frame_layout.gprs_offset,
6532 cfun_frame_layout.first_save_gpr,
6533 cfun_frame_layout.last_save_gpr);
6537 /* Dummy insn to mark literal pool slot. */
6539 if (cfun->machine->base_reg)
6540 emit_insn (gen_main_pool (cfun->machine->base_reg));
6542 offset = cfun_frame_layout.f0_offset;
6544 /* Save f0 and f2. */
6545 for (i = 0; i < 2; i++)
6547 if (cfun_fpr_bit_p (i))
6549 save_fpr (stack_pointer_rtx, offset, i + 16);
6552 else if (!TARGET_PACKED_STACK)
6556 /* Save f4 and f6. */
6557 offset = cfun_frame_layout.f4_offset;
6558 for (i = 2; i < 4; i++)
6560 if (cfun_fpr_bit_p (i))
6562 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
6565 /* If f4 and f6 are call clobbered they are saved due to stdargs and
6566 therefore are not frame related. */
6567 if (!call_really_used_regs[i + 16])
6568 RTX_FRAME_RELATED_P (insn) = 1;
6570 else if (!TARGET_PACKED_STACK)
6574 if (TARGET_PACKED_STACK
6575 && cfun_save_high_fprs_p
6576 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
6578 offset = (cfun_frame_layout.f8_offset
6579 + (cfun_frame_layout.high_fprs - 1) * 8);
6581 for (i = 15; i > 7 && offset >= 0; i--)
6582 if (cfun_fpr_bit_p (i))
6584 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
6586 RTX_FRAME_RELATED_P (insn) = 1;
6589 if (offset >= cfun_frame_layout.f8_offset)
6593 if (!TARGET_PACKED_STACK)
6594 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
6596 /* Decrement stack pointer. */
6598 if (cfun_frame_layout.frame_size > 0)
6600 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
6602 if (s390_stack_size)
6604 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
6605 & ~(s390_stack_guard - 1));
6606 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
6607 GEN_INT (stack_check_mask));
6610 gen_cmpdi (t, const0_rtx);
6612 gen_cmpsi (t, const0_rtx);
6614 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
6615 gen_rtx_REG (CCmode,
6621 if (s390_warn_framesize > 0
6622 && cfun_frame_layout.frame_size >= s390_warn_framesize)
6623 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
6624 current_function_name (), cfun_frame_layout.frame_size);
6626 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
6627 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
6629 /* Save incoming stack pointer into temp reg. */
6630 if (TARGET_BACKCHAIN || next_fpr)
6631 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
6633 /* Subtract frame size from stack pointer. */
6635 if (DISP_IN_RANGE (INTVAL (frame_off)))
6637 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6638 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6640 insn = emit_insn (insn);
6644 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
6645 frame_off = force_const_mem (Pmode, frame_off);
6647 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
6648 annotate_constant_pool_refs (&PATTERN (insn));
6651 RTX_FRAME_RELATED_P (insn) = 1;
6653 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6654 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6655 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6656 GEN_INT (-cfun_frame_layout.frame_size))),
6659 /* Set backchain. */
6661 if (TARGET_BACKCHAIN)
6663 if (cfun_frame_layout.backchain_offset)
6664 addr = gen_rtx_MEM (Pmode,
6665 plus_constant (stack_pointer_rtx,
6666 cfun_frame_layout.backchain_offset));
6668 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
6669 set_mem_alias_set (addr, get_frame_alias_set ());
6670 insn = emit_insn (gen_move_insn (addr, temp_reg));
6673 /* If we support asynchronous exceptions (e.g. for Java),
6674 we need to make sure the backchain pointer is set up
6675 before any possibly trapping memory access. */
6677 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
6679 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
6680 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
6684 /* Save fprs 8 - 15 (64 bit ABI). */
6686 if (cfun_save_high_fprs_p && next_fpr)
6688 insn = emit_insn (gen_add2_insn (temp_reg,
6689 GEN_INT (cfun_frame_layout.f8_offset)));
6693 for (i = 24; i <= next_fpr; i++)
6694 if (cfun_fpr_bit_p (i - 16))
6696 rtx addr = plus_constant (stack_pointer_rtx,
6697 cfun_frame_layout.frame_size
6698 + cfun_frame_layout.f8_offset
6701 insn = save_fpr (temp_reg, offset, i);
6703 RTX_FRAME_RELATED_P (insn) = 1;
6705 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6706 gen_rtx_SET (VOIDmode,
6707 gen_rtx_MEM (DFmode, addr),
6708 gen_rtx_REG (DFmode, i)),
6713 /* Set frame pointer, if needed. */
6715 if (frame_pointer_needed)
6717 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6718 RTX_FRAME_RELATED_P (insn) = 1;
6721 /* Set up got pointer, if needed. */
6723 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6725 rtx insns = s390_load_got ();
6727 for (insn = insns; insn; insn = NEXT_INSN (insn))
6729 annotate_constant_pool_refs (&PATTERN (insn));
6731 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
6738 if (TARGET_TPF_PROFILING)
6740 /* Generate a BAS instruction to serve as a function
6741 entry intercept to facilitate the use of tracing
6742 algorithms located at the branch target. */
6743 emit_insn (gen_prologue_tpf ());
6745 /* Emit a blockage here so that all code
6746 lies between the profiling mechanisms. */
6747 emit_insn (gen_blockage ());
6751 /* Expand the epilogue into a bunch of separate insns. */
6754 s390_emit_epilogue (bool sibcall)
6756 rtx frame_pointer, return_reg;
6757 int area_bottom, area_top, offset = 0;
6762 if (TARGET_TPF_PROFILING)
6765 /* Generate a BAS instruction to serve as a function
6766 entry intercept to facilitate the use of tracing
6767 algorithms located at the branch target. */
6769 /* Emit a blockage here so that all code
6770 lies between the profiling mechanisms. */
6771 emit_insn (gen_blockage ());
6773 emit_insn (gen_epilogue_tpf ());
6776 /* Check whether to use frame or stack pointer for restore. */
6778 frame_pointer = (frame_pointer_needed
6779 ? hard_frame_pointer_rtx : stack_pointer_rtx);
6781 s390_frame_area (&area_bottom, &area_top);
6783 /* Check whether we can access the register save area.
6784 If not, increment the frame pointer as required. */
6786 if (area_top <= area_bottom)
6788 /* Nothing to restore. */
6790 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
6791 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
6793 /* Area is in range. */
6794 offset = cfun_frame_layout.frame_size;
6798 rtx insn, frame_off;
6800 offset = area_bottom < 0 ? -area_bottom : 0;
6801 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
6803 if (DISP_IN_RANGE (INTVAL (frame_off)))
6805 insn = gen_rtx_SET (VOIDmode, frame_pointer,
6806 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
6807 insn = emit_insn (insn);
6811 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
6812 frame_off = force_const_mem (Pmode, frame_off);
6814 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
6815 annotate_constant_pool_refs (&PATTERN (insn));
6819 /* Restore call saved fprs. */
6823 if (cfun_save_high_fprs_p)
6825 next_offset = cfun_frame_layout.f8_offset;
6826 for (i = 24; i < 32; i++)
6828 if (cfun_fpr_bit_p (i - 16))
6830 restore_fpr (frame_pointer,
6831 offset + next_offset, i);
6840 next_offset = cfun_frame_layout.f4_offset;
6841 for (i = 18; i < 20; i++)
6843 if (cfun_fpr_bit_p (i - 16))
6845 restore_fpr (frame_pointer,
6846 offset + next_offset, i);
6849 else if (!TARGET_PACKED_STACK)
6855 /* Return register. */
6857 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6859 /* Restore call saved gprs. */
6861 if (cfun_frame_layout.first_restore_gpr != -1)
6866 /* Check for global register and save them
6867 to stack location from where they get restored. */
6869 for (i = cfun_frame_layout.first_restore_gpr;
6870 i <= cfun_frame_layout.last_restore_gpr;
6873 /* These registers are special and need to be
6874 restored in any case. */
6875 if (i == STACK_POINTER_REGNUM
6876 || i == RETURN_REGNUM
6878 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
6883 addr = plus_constant (frame_pointer,
6884 offset + cfun_frame_layout.gprs_offset
6885 + (i - cfun_frame_layout.first_save_gpr)
6887 addr = gen_rtx_MEM (Pmode, addr);
6888 set_mem_alias_set (addr, get_frame_alias_set ());
6889 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
6895 /* Fetch return address from stack before load multiple,
6896 this will do good for scheduling. */
6898 if (cfun_frame_layout.save_return_addr_p
6899 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
6900 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
6902 int return_regnum = find_unused_clobbered_reg();
6905 return_reg = gen_rtx_REG (Pmode, return_regnum);
6907 addr = plus_constant (frame_pointer,
6908 offset + cfun_frame_layout.gprs_offset
6910 - cfun_frame_layout.first_save_gpr)
6912 addr = gen_rtx_MEM (Pmode, addr);
6913 set_mem_alias_set (addr, get_frame_alias_set ());
6914 emit_move_insn (return_reg, addr);
6918 insn = restore_gprs (frame_pointer,
6919 offset + cfun_frame_layout.gprs_offset
6920 + (cfun_frame_layout.first_restore_gpr
6921 - cfun_frame_layout.first_save_gpr)
6923 cfun_frame_layout.first_restore_gpr,
6924 cfun_frame_layout.last_restore_gpr);
6931 /* Return to caller. */
6933 p = rtvec_alloc (2);
6935 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
6936 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
6937 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
6942 /* Return the size in bytes of a function argument of
6943 type TYPE and/or mode MODE. At least one of TYPE or
6944 MODE must be specified. */
6947 s390_function_arg_size (enum machine_mode mode, tree type)
6950 return int_size_in_bytes (type);
6952 /* No type info available for some library calls ... */
6953 if (mode != BLKmode)
6954 return GET_MODE_SIZE (mode);
6956 /* If we have neither type nor mode, abort */
6960 /* Return true if a function argument of type TYPE and mode MODE
6961 is to be passed in a floating-point register, if available. */
6964 s390_function_arg_float (enum machine_mode mode, tree type)
6966 int size = s390_function_arg_size (mode, type);
6970 /* Soft-float changes the ABI: no floating-point registers are used. */
6971 if (TARGET_SOFT_FLOAT)
6974 /* No type info available for some library calls ... */
6976 return mode == SFmode || mode == DFmode;
6978 /* The ABI says that record types with a single member are treated
6979 just like that member would be. */
6980 while (TREE_CODE (type) == RECORD_TYPE)
6982 tree field, single = NULL_TREE;
6984 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6986 if (TREE_CODE (field) != FIELD_DECL)
6989 if (single == NULL_TREE)
6990 single = TREE_TYPE (field);
6995 if (single == NULL_TREE)
7001 return TREE_CODE (type) == REAL_TYPE;
7004 /* Return true if a function argument of type TYPE and mode MODE
7005 is to be passed in an integer register, or a pair of integer
7006 registers, if available. */
7009 s390_function_arg_integer (enum machine_mode mode, tree type)
7011 int size = s390_function_arg_size (mode, type);
7015 /* No type info available for some library calls ... */
7017 return GET_MODE_CLASS (mode) == MODE_INT
7018 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7020 /* We accept small integral (and similar) types. */
7021 if (INTEGRAL_TYPE_P (type)
7022 || POINTER_TYPE_P (type)
7023 || TREE_CODE (type) == OFFSET_TYPE
7024 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7027 /* We also accept structs of size 1, 2, 4, 8 that are not
7028 passed in floating-point registers. */
7029 if (AGGREGATE_TYPE_P (type)
7030 && exact_log2 (size) >= 0
7031 && !s390_function_arg_float (mode, type))
7037 /* Return 1 if a function argument of type TYPE and mode MODE
7038 is to be passed by reference. The ABI specifies that only
7039 structures of size 1, 2, 4, or 8 bytes are passed by value,
7040 all other structures (and complex numbers) are passed by
7044 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7045 enum machine_mode mode, tree type,
7046 bool named ATTRIBUTE_UNUSED)
7048 int size = s390_function_arg_size (mode, type);
7054 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7057 if (TREE_CODE (type) == COMPLEX_TYPE
7058 || TREE_CODE (type) == VECTOR_TYPE)
7065 /* Update the data in CUM to advance over an argument of mode MODE and
7066 data type TYPE. (TYPE is null for libcalls where that information
7067 may not be available.). The boolean NAMED specifies whether the
7068 argument is a named argument (as opposed to an unnamed argument
7069 matching an ellipsis). */
7072 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7073 tree type, int named ATTRIBUTE_UNUSED)
7075 if (s390_function_arg_float (mode, type))
7079 else if (s390_function_arg_integer (mode, type))
7081 int size = s390_function_arg_size (mode, type);
7082 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7088 /* Define where to put the arguments to a function.
7089 Value is zero to push the argument on the stack,
7090 or a hard register in which to store the argument.
7092 MODE is the argument's machine mode.
7093 TYPE is the data type of the argument (as a tree).
7094 This is null for libcalls where that information may
7096 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7097 the preceding args and about the function being called.
7098 NAMED is nonzero if this argument is a named parameter
7099 (otherwise it is an extra parameter matching an ellipsis).
7101 On S/390, we use general purpose registers 2 through 6 to
7102 pass integer, pointer, and certain structure arguments, and
7103 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7104 to pass floating point arguments. All remaining arguments
7105 are pushed to the stack. */
7108 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7109 int named ATTRIBUTE_UNUSED)
7111 if (s390_function_arg_float (mode, type))
7113 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7116 return gen_rtx_REG (mode, cum->fprs + 16);
7118 else if (s390_function_arg_integer (mode, type))
7120 int size = s390_function_arg_size (mode, type);
7121 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7123 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7126 return gen_rtx_REG (mode, cum->gprs + 2);
7129 /* After the real arguments, expand_call calls us once again
7130 with a void_type_node type. Whatever we return here is
7131 passed as operand 2 to the call expanders.
7133 We don't need this feature ... */
7134 else if (type == void_type_node)
7140 /* Return true if return values of type TYPE should be returned
7141 in a memory buffer whose address is passed by the caller as
7142 hidden first argument. */
7145 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7147 /* We accept small integral (and similar) types. */
7148 if (INTEGRAL_TYPE_P (type)
7149 || POINTER_TYPE_P (type)
7150 || TREE_CODE (type) == OFFSET_TYPE
7151 || TREE_CODE (type) == REAL_TYPE)
7152 return int_size_in_bytes (type) > 8;
7154 /* Aggregates and similar constructs are always returned
7156 if (AGGREGATE_TYPE_P (type)
7157 || TREE_CODE (type) == COMPLEX_TYPE
7158 || TREE_CODE (type) == VECTOR_TYPE)
7161 /* ??? We get called on all sorts of random stuff from
7162 aggregate_value_p. We can't abort, but it's not clear
7163 what's safe to return. Pretend it's a struct I guess. */
7167 /* Define where to return a (scalar) value of type TYPE.
7168 If TYPE is null, define where to return a (scalar)
7169 value of mode MODE from a libcall. */
7172 s390_function_value (tree type, enum machine_mode mode)
7176 int unsignedp = TYPE_UNSIGNED (type);
7177 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7180 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7181 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7182 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7184 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7185 return gen_rtx_REG (mode, 16);
7187 return gen_rtx_REG (mode, 2);
7191 /* Create and return the va_list datatype.
7193 On S/390, va_list is an array type equivalent to
7195 typedef struct __va_list_tag
7199 void *__overflow_arg_area;
7200 void *__reg_save_area;
7203 where __gpr and __fpr hold the number of general purpose
7204 or floating point arguments used up to now, respectively,
7205 __overflow_arg_area points to the stack location of the
7206 next argument passed on the stack, and __reg_save_area
7207 always points to the start of the register area in the
7208 call frame of the current function. The function prologue
7209 saves all registers used for argument passing into this
7210 area if the function uses variable arguments. */
7213 s390_build_builtin_va_list (void)
7215 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7217 record = lang_hooks.types.make_type (RECORD_TYPE);
7220 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7222 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7223 long_integer_type_node);
7224 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7225 long_integer_type_node);
7226 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7228 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7231 va_list_gpr_counter_field = f_gpr;
7232 va_list_fpr_counter_field = f_fpr;
7234 DECL_FIELD_CONTEXT (f_gpr) = record;
7235 DECL_FIELD_CONTEXT (f_fpr) = record;
7236 DECL_FIELD_CONTEXT (f_ovf) = record;
7237 DECL_FIELD_CONTEXT (f_sav) = record;
7239 TREE_CHAIN (record) = type_decl;
7240 TYPE_NAME (record) = type_decl;
7241 TYPE_FIELDS (record) = f_gpr;
7242 TREE_CHAIN (f_gpr) = f_fpr;
7243 TREE_CHAIN (f_fpr) = f_ovf;
7244 TREE_CHAIN (f_ovf) = f_sav;
7246 layout_type (record);
7248 /* The correct type is an array type of one element. */
7249 return build_array_type (record, build_index_type (size_zero_node));
7252 /* Implement va_start by filling the va_list structure VALIST.
7253 STDARG_P is always true, and ignored.
7254 NEXTARG points to the first anonymous stack argument.
7256 The following global variables are used to initialize
7257 the va_list structure:
7259 current_function_args_info:
7260 holds number of gprs and fprs used for named arguments.
7261 current_function_arg_offset_rtx:
7262 holds the offset of the first anonymous stack argument
7263 (relative to the virtual arg pointer). */
7266 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7268 HOST_WIDE_INT n_gpr, n_fpr;
7270 tree f_gpr, f_fpr, f_ovf, f_sav;
7271 tree gpr, fpr, ovf, sav, t;
7273 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7274 f_fpr = TREE_CHAIN (f_gpr);
7275 f_ovf = TREE_CHAIN (f_fpr);
7276 f_sav = TREE_CHAIN (f_ovf);
7278 valist = build_va_arg_indirect_ref (valist);
7279 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7280 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7281 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7282 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7284 /* Count number of gp and fp argument registers used. */
7286 n_gpr = current_function_args_info.gprs;
7287 n_fpr = current_function_args_info.fprs;
7289 if (cfun->va_list_gpr_size)
7291 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7292 build_int_cst (NULL_TREE, n_gpr));
7293 TREE_SIDE_EFFECTS (t) = 1;
7294 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7297 if (cfun->va_list_fpr_size)
7299 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7300 build_int_cst (NULL_TREE, n_fpr));
7301 TREE_SIDE_EFFECTS (t) = 1;
7302 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7305 /* Find the overflow area. */
7306 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7307 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7309 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7311 off = INTVAL (current_function_arg_offset_rtx);
7312 off = off < 0 ? 0 : off;
7313 if (TARGET_DEBUG_ARG)
7314 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7315 (int)n_gpr, (int)n_fpr, off);
7317 t = build (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7319 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7320 TREE_SIDE_EFFECTS (t) = 1;
7321 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7324 /* Find the register save area. */
7325 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7326 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7328 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7329 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7330 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7332 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7333 TREE_SIDE_EFFECTS (t) = 1;
7334 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7338 /* Implement va_arg by updating the va_list structure
7339 VALIST as required to retrieve an argument of type
7340 TYPE, and returning that argument.
7342 Generates code equivalent to:
7344 if (integral value) {
7345 if (size <= 4 && args.gpr < 5 ||
7346 size > 4 && args.gpr < 4 )
7347 ret = args.reg_save_area[args.gpr+8]
7349 ret = *args.overflow_arg_area++;
7350 } else if (float value) {
7352 ret = args.reg_save_area[args.fpr+64]
7354 ret = *args.overflow_arg_area++;
7355 } else if (aggregate value) {
7357 ret = *args.reg_save_area[args.gpr]
7359 ret = **args.overflow_arg_area++;
7363 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7364 tree *post_p ATTRIBUTE_UNUSED)
7366 tree f_gpr, f_fpr, f_ovf, f_sav;
7367 tree gpr, fpr, ovf, sav, reg, t, u;
7368 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7369 tree lab_false, lab_over, addr;
7371 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7372 f_fpr = TREE_CHAIN (f_gpr);
7373 f_ovf = TREE_CHAIN (f_fpr);
7374 f_sav = TREE_CHAIN (f_ovf);
7376 valist = build_va_arg_indirect_ref (valist);
7377 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7378 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7379 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7380 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7382 size = int_size_in_bytes (type);
7384 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7386 if (TARGET_DEBUG_ARG)
7388 fprintf (stderr, "va_arg: aggregate type");
7392 /* Aggregates are passed by reference. */
7397 /* kernel stack layout on 31 bit: It is assumed here that no padding
7398 will be added by s390_frame_info because for va_args always an even
7399 number of gprs has to be saved r15-r2 = 14 regs. */
7400 sav_ofs = 2 * UNITS_PER_WORD;
7401 sav_scale = UNITS_PER_WORD;
7402 size = UNITS_PER_WORD;
7403 max_reg = GP_ARG_NUM_REG - n_reg;
7405 else if (s390_function_arg_float (TYPE_MODE (type), type))
7407 if (TARGET_DEBUG_ARG)
7409 fprintf (stderr, "va_arg: float type");
7413 /* FP args go in FP registers, if present. */
7417 sav_ofs = 16 * UNITS_PER_WORD;
7419 max_reg = FP_ARG_NUM_REG - n_reg;
7423 if (TARGET_DEBUG_ARG)
7425 fprintf (stderr, "va_arg: other type");
7429 /* Otherwise into GP registers. */
7432 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7434 /* kernel stack layout on 31 bit: It is assumed here that no padding
7435 will be added by s390_frame_info because for va_args always an even
7436 number of gprs has to be saved r15-r2 = 14 regs. */
7437 sav_ofs = 2 * UNITS_PER_WORD;
7439 if (size < UNITS_PER_WORD)
7440 sav_ofs += UNITS_PER_WORD - size;
7442 sav_scale = UNITS_PER_WORD;
7443 max_reg = GP_ARG_NUM_REG - n_reg;
7446 /* Pull the value out of the saved registers ... */
7448 lab_false = create_artificial_label ();
7449 lab_over = create_artificial_label ();
7450 addr = create_tmp_var (ptr_type_node, "addr");
7451 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7453 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
7454 t = build2 (GT_EXPR, boolean_type_node, reg, t);
7455 u = build1 (GOTO_EXPR, void_type_node, lab_false);
7456 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7457 gimplify_and_add (t, pre_p);
7459 t = build2 (PLUS_EXPR, ptr_type_node, sav,
7460 fold_convert (ptr_type_node, size_int (sav_ofs)));
7461 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
7462 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
7463 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
7465 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
7466 gimplify_and_add (t, pre_p);
7468 t = build1 (GOTO_EXPR, void_type_node, lab_over);
7469 gimplify_and_add (t, pre_p);
7471 t = build1 (LABEL_EXPR, void_type_node, lab_false);
7472 append_to_statement_list (t, pre_p);
7475 /* ... Otherwise out of the overflow area. */
7478 if (size < UNITS_PER_WORD)
7479 t = build2 (PLUS_EXPR, ptr_type_node, t,
7480 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
7482 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7484 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
7485 gimplify_and_add (u, pre_p);
7487 t = build2 (PLUS_EXPR, ptr_type_node, t,
7488 fold_convert (ptr_type_node, size_int (size)));
7489 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
7490 gimplify_and_add (t, pre_p);
7492 t = build1 (LABEL_EXPR, void_type_node, lab_over);
7493 append_to_statement_list (t, pre_p);
7496 /* Increment register save count. */
7498 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
7499 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
7500 gimplify_and_add (u, pre_p);
7504 t = build_pointer_type (build_pointer_type (type));
7505 addr = fold_convert (t, addr);
7506 addr = build_va_arg_indirect_ref (addr);
7510 t = build_pointer_type (type);
7511 addr = fold_convert (t, addr);
7514 return build_va_arg_indirect_ref (addr);
7522 S390_BUILTIN_THREAD_POINTER,
7523 S390_BUILTIN_SET_THREAD_POINTER,
7528 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
7533 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
7539 s390_init_builtins (void)
7543 ftype = build_function_type (ptr_type_node, void_list_node);
7544 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
7545 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
7548 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
7549 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
7550 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
7554 /* Expand an expression EXP that calls a built-in function,
7555 with result going to TARGET if that's convenient
7556 (and in mode MODE if that's convenient).
7557 SUBTARGET may be used as the target for computing one of EXP's operands.
7558 IGNORE is nonzero if the value is to be ignored. */
7561 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7562 enum machine_mode mode ATTRIBUTE_UNUSED,
7563 int ignore ATTRIBUTE_UNUSED)
7567 unsigned int const *code_for_builtin =
7568 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
7570 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7571 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7572 tree arglist = TREE_OPERAND (exp, 1);
7573 enum insn_code icode;
7574 rtx op[MAX_ARGS], pat;
7578 if (fcode >= S390_BUILTIN_max)
7579 internal_error ("bad builtin fcode");
7580 icode = code_for_builtin[fcode];
7582 internal_error ("bad builtin fcode");
7584 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
7586 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
7588 arglist = TREE_CHAIN (arglist), arity++)
7590 const struct insn_operand_data *insn_op;
7592 tree arg = TREE_VALUE (arglist);
7593 if (arg == error_mark_node)
7595 if (arity > MAX_ARGS)
7598 insn_op = &insn_data[icode].operand[arity + nonvoid];
7600 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
7602 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
7603 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
7608 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7610 || GET_MODE (target) != tmode
7611 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
7612 target = gen_reg_rtx (tmode);
7618 pat = GEN_FCN (icode) (target);
7622 pat = GEN_FCN (icode) (target, op[0]);
7624 pat = GEN_FCN (icode) (op[0]);
7627 pat = GEN_FCN (icode) (target, op[0], op[1]);
7643 /* Output assembly code for the trampoline template to
7646 On S/390, we use gpr 1 internally in the trampoline code;
7647 gpr 0 is used to hold the static chain. */
7650 s390_trampoline_template (FILE *file)
7653 op[0] = gen_rtx_REG (Pmode, 0);
7654 op[1] = gen_rtx_REG (Pmode, 1);
7658 output_asm_insn ("basr\t%1,0", op);
7659 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
7660 output_asm_insn ("br\t%1", op);
7661 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
7665 output_asm_insn ("basr\t%1,0", op);
7666 output_asm_insn ("lm\t%0,%1,6(%1)", op);
7667 output_asm_insn ("br\t%1", op);
7668 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
7672 /* Emit RTL insns to initialize the variable parts of a trampoline.
7673 FNADDR is an RTX for the address of the function's pure code.
7674 CXT is an RTX for the static chain value for the function. */
7677 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
7679 emit_move_insn (gen_rtx_MEM (Pmode,
7680 memory_address (Pmode,
7681 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
7682 emit_move_insn (gen_rtx_MEM (Pmode,
7683 memory_address (Pmode,
7684 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
7687 /* Return rtx for 64-bit constant formed from the 32-bit subwords
7688 LOW and HIGH, independent of the host word size. */
7691 s390_gen_rtx_const_DI (int high, int low)
7693 #if HOST_BITS_PER_WIDE_INT >= 64
7695 val = (HOST_WIDE_INT)high;
7697 val |= (HOST_WIDE_INT)low;
7699 return GEN_INT (val);
7701 #if HOST_BITS_PER_WIDE_INT >= 32
7702 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
7709 /* Output assembler code to FILE to increment profiler label # LABELNO
7710 for profiling a function entry. */
7713 s390_function_profiler (FILE *file, int labelno)
7718 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
7720 fprintf (file, "# function profiler \n");
7722 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
7723 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
7724 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
7726 op[2] = gen_rtx_REG (Pmode, 1);
7727 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7728 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
7730 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
7733 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
7734 op[4] = gen_rtx_CONST (Pmode, op[4]);
7739 output_asm_insn ("stg\t%0,%1", op);
7740 output_asm_insn ("larl\t%2,%3", op);
7741 output_asm_insn ("brasl\t%0,%4", op);
7742 output_asm_insn ("lg\t%0,%1", op);
7746 op[6] = gen_label_rtx ();
7748 output_asm_insn ("st\t%0,%1", op);
7749 output_asm_insn ("bras\t%2,%l6", op);
7750 output_asm_insn (".long\t%4", op);
7751 output_asm_insn (".long\t%3", op);
7752 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
7753 output_asm_insn ("l\t%0,0(%2)", op);
7754 output_asm_insn ("l\t%2,4(%2)", op);
7755 output_asm_insn ("basr\t%0,%0", op);
7756 output_asm_insn ("l\t%0,%1", op);
7760 op[5] = gen_label_rtx ();
7761 op[6] = gen_label_rtx ();
7763 output_asm_insn ("st\t%0,%1", op);
7764 output_asm_insn ("bras\t%2,%l6", op);
7765 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
7766 output_asm_insn (".long\t%4-%l5", op);
7767 output_asm_insn (".long\t%3-%l5", op);
7768 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
7769 output_asm_insn ("lr\t%0,%2", op);
7770 output_asm_insn ("a\t%0,0(%2)", op);
7771 output_asm_insn ("a\t%2,4(%2)", op);
7772 output_asm_insn ("basr\t%0,%0", op);
7773 output_asm_insn ("l\t%0,%1", op);
7777 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
7778 into its SYMBOL_REF_FLAGS. */
7781 s390_encode_section_info (tree decl, rtx rtl, int first)
7783 default_encode_section_info (decl, rtl, first);
7785 /* If a variable has a forced alignment to < 2 bytes, mark it with
7786 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
7787 if (TREE_CODE (decl) == VAR_DECL
7788 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
7789 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
7792 /* Output thunk to FILE that implements a C++ virtual function call (with
7793 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
7794 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
7795 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
7796 relative to the resulting this pointer. */
7799 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
7800 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7806 /* Operand 0 is the target function. */
7807 op[0] = XEXP (DECL_RTL (function), 0);
7808 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
7811 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
7812 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
7813 op[0] = gen_rtx_CONST (Pmode, op[0]);
7816 /* Operand 1 is the 'this' pointer. */
7817 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7818 op[1] = gen_rtx_REG (Pmode, 3);
7820 op[1] = gen_rtx_REG (Pmode, 2);
7822 /* Operand 2 is the delta. */
7823 op[2] = GEN_INT (delta);
7825 /* Operand 3 is the vcall_offset. */
7826 op[3] = GEN_INT (vcall_offset);
7828 /* Operand 4 is the temporary register. */
7829 op[4] = gen_rtx_REG (Pmode, 1);
7831 /* Operands 5 to 8 can be used as labels. */
7837 /* Operand 9 can be used for temporary register. */
7840 /* Generate code. */
7843 /* Setup literal pool pointer if required. */
7844 if ((!DISP_IN_RANGE (delta)
7845 && !CONST_OK_FOR_K (delta)
7846 && !CONST_OK_FOR_Os (delta))
7847 || (!DISP_IN_RANGE (vcall_offset)
7848 && !CONST_OK_FOR_K (vcall_offset)
7849 && !CONST_OK_FOR_Os (vcall_offset)))
7851 op[5] = gen_label_rtx ();
7852 output_asm_insn ("larl\t%4,%5", op);
7855 /* Add DELTA to this pointer. */
7858 if (CONST_OK_FOR_J (delta))
7859 output_asm_insn ("la\t%1,%2(%1)", op);
7860 else if (DISP_IN_RANGE (delta))
7861 output_asm_insn ("lay\t%1,%2(%1)", op);
7862 else if (CONST_OK_FOR_K (delta))
7863 output_asm_insn ("aghi\t%1,%2", op);
7864 else if (CONST_OK_FOR_Os (delta))
7865 output_asm_insn ("agfi\t%1,%2", op);
7868 op[6] = gen_label_rtx ();
7869 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
7873 /* Perform vcall adjustment. */
7876 if (DISP_IN_RANGE (vcall_offset))
7878 output_asm_insn ("lg\t%4,0(%1)", op);
7879 output_asm_insn ("ag\t%1,%3(%4)", op);
7881 else if (CONST_OK_FOR_K (vcall_offset))
7883 output_asm_insn ("lghi\t%4,%3", op);
7884 output_asm_insn ("ag\t%4,0(%1)", op);
7885 output_asm_insn ("ag\t%1,0(%4)", op);
7887 else if (CONST_OK_FOR_Os (vcall_offset))
7889 output_asm_insn ("lgfi\t%4,%3", op);
7890 output_asm_insn ("ag\t%4,0(%1)", op);
7891 output_asm_insn ("ag\t%1,0(%4)", op);
7895 op[7] = gen_label_rtx ();
7896 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
7897 output_asm_insn ("ag\t%4,0(%1)", op);
7898 output_asm_insn ("ag\t%1,0(%4)", op);
7902 /* Jump to target. */
7903 output_asm_insn ("jg\t%0", op);
7905 /* Output literal pool if required. */
7908 output_asm_insn (".align\t4", op);
7909 targetm.asm_out.internal_label (file, "L",
7910 CODE_LABEL_NUMBER (op[5]));
7914 targetm.asm_out.internal_label (file, "L",
7915 CODE_LABEL_NUMBER (op[6]));
7916 output_asm_insn (".long\t%2", op);
7920 targetm.asm_out.internal_label (file, "L",
7921 CODE_LABEL_NUMBER (op[7]));
7922 output_asm_insn (".long\t%3", op);
7927 /* Setup base pointer if required. */
7929 || (!DISP_IN_RANGE (delta)
7930 && !CONST_OK_FOR_K (delta)
7931 && !CONST_OK_FOR_Os (delta))
7932 || (!DISP_IN_RANGE (delta)
7933 && !CONST_OK_FOR_K (vcall_offset)
7934 && !CONST_OK_FOR_Os (vcall_offset)))
7936 op[5] = gen_label_rtx ();
7937 output_asm_insn ("basr\t%4,0", op);
7938 targetm.asm_out.internal_label (file, "L",
7939 CODE_LABEL_NUMBER (op[5]));
7942 /* Add DELTA to this pointer. */
7945 if (CONST_OK_FOR_J (delta))
7946 output_asm_insn ("la\t%1,%2(%1)", op);
7947 else if (DISP_IN_RANGE (delta))
7948 output_asm_insn ("lay\t%1,%2(%1)", op);
7949 else if (CONST_OK_FOR_K (delta))
7950 output_asm_insn ("ahi\t%1,%2", op);
7951 else if (CONST_OK_FOR_Os (delta))
7952 output_asm_insn ("afi\t%1,%2", op);
7955 op[6] = gen_label_rtx ();
7956 output_asm_insn ("a\t%1,%6-%5(%4)", op);
7960 /* Perform vcall adjustment. */
7963 if (CONST_OK_FOR_J (vcall_offset))
7965 output_asm_insn ("l\t%4,0(%1)", op);
7966 output_asm_insn ("a\t%1,%3(%4)", op);
7968 else if (DISP_IN_RANGE (vcall_offset))
7970 output_asm_insn ("l\t%4,0(%1)", op);
7971 output_asm_insn ("ay\t%1,%3(%4)", op);
7973 else if (CONST_OK_FOR_K (vcall_offset))
7975 output_asm_insn ("lhi\t%4,%3", op);
7976 output_asm_insn ("a\t%4,0(%1)", op);
7977 output_asm_insn ("a\t%1,0(%4)", op);
7979 else if (CONST_OK_FOR_Os (vcall_offset))
7981 output_asm_insn ("iilf\t%4,%3", op);
7982 output_asm_insn ("a\t%4,0(%1)", op);
7983 output_asm_insn ("a\t%1,0(%4)", op);
7987 op[7] = gen_label_rtx ();
7988 output_asm_insn ("l\t%4,%7-%5(%4)", op);
7989 output_asm_insn ("a\t%4,0(%1)", op);
7990 output_asm_insn ("a\t%1,0(%4)", op);
7993 /* We had to clobber the base pointer register.
7994 Re-setup the base pointer (with a different base). */
7995 op[5] = gen_label_rtx ();
7996 output_asm_insn ("basr\t%4,0", op);
7997 targetm.asm_out.internal_label (file, "L",
7998 CODE_LABEL_NUMBER (op[5]));
8001 /* Jump to target. */
8002 op[8] = gen_label_rtx ();
8005 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8007 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8008 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8009 else if (flag_pic == 1)
8011 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8012 output_asm_insn ("l\t%4,%0(%4)", op);
8014 else if (flag_pic == 2)
8016 op[9] = gen_rtx_REG (Pmode, 0);
8017 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8018 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8019 output_asm_insn ("ar\t%4,%9", op);
8020 output_asm_insn ("l\t%4,0(%4)", op);
8023 output_asm_insn ("br\t%4", op);
8025 /* Output literal pool. */
8026 output_asm_insn (".align\t4", op);
8028 if (nonlocal && flag_pic == 2)
8029 output_asm_insn (".long\t%0", op);
8032 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8033 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8036 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8038 output_asm_insn (".long\t%0", op);
8040 output_asm_insn (".long\t%0-%5", op);
8044 targetm.asm_out.internal_label (file, "L",
8045 CODE_LABEL_NUMBER (op[6]));
8046 output_asm_insn (".long\t%2", op);
8050 targetm.asm_out.internal_label (file, "L",
8051 CODE_LABEL_NUMBER (op[7]));
8052 output_asm_insn (".long\t%3", op);
8058 s390_valid_pointer_mode (enum machine_mode mode)
8060 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8063 /* Checks whether the given ARGUMENT_LIST would use a caller
8064 saved register. This is used to decide whether sibling call
8065 optimization could be performed on the respective function
8069 s390_call_saved_register_used (tree argument_list)
8071 CUMULATIVE_ARGS cum;
8073 enum machine_mode mode;
8078 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8080 while (argument_list)
8082 parameter = TREE_VALUE (argument_list);
8083 argument_list = TREE_CHAIN (argument_list);
8085 gcc_assert (parameter);
8087 /* For an undeclared variable passed as parameter we will get
8088 an ERROR_MARK node here. */
8089 if (TREE_CODE (parameter) == ERROR_MARK)
8092 type = TREE_TYPE (parameter);
8095 mode = TYPE_MODE (type);
8098 if (pass_by_reference (&cum, mode, type, true))
8101 type = build_pointer_type (type);
8104 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8106 s390_function_arg_advance (&cum, mode, type, 0);
8108 if (parm_rtx && REG_P (parm_rtx))
8111 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8113 if (! call_used_regs[reg + REGNO (parm_rtx)])
8120 /* Return true if the given call expression can be
8121 turned into a sibling call.
8122 DECL holds the declaration of the function to be called whereas
8123 EXP is the call expression itself. */
8126 s390_function_ok_for_sibcall (tree decl, tree exp)
8128 /* The TPF epilogue uses register 1. */
8129 if (TARGET_TPF_PROFILING)
8132 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8133 which would have to be restored before the sibcall. */
8134 if (!TARGET_64BIT && flag_pic && decl && TREE_PUBLIC (decl))
8137 /* Register 6 on s390 is available as an argument register but unfortunately
8138 "caller saved". This makes functions needing this register for arguments
8139 not suitable for sibcalls. */
8140 if (TREE_OPERAND (exp, 1)
8141 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8147 /* Return the fixed registers used for condition codes. */
8150 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8153 *p2 = INVALID_REGNUM;
8158 /* This function is used by the call expanders of the machine description.
8159 It emits the call insn itself together with the necessary operations
8160 to adjust the target address and returns the emitted insn.
8161 ADDR_LOCATION is the target address rtx
8162 TLS_CALL the location of the thread-local symbol
8163 RESULT_REG the register where the result of the call should be stored
8164 RETADDR_REG the register where the return address should be stored
8165 If this parameter is NULL_RTX the call is considered
8166 to be a sibling call. */
8169 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8172 bool plt_call = false;
8178 /* Direct function calls need special treatment. */
8179 if (GET_CODE (addr_location) == SYMBOL_REF)
8181 /* When calling a global routine in PIC mode, we must
8182 replace the symbol itself with the PLT stub. */
8183 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8185 addr_location = gen_rtx_UNSPEC (Pmode,
8186 gen_rtvec (1, addr_location),
8188 addr_location = gen_rtx_CONST (Pmode, addr_location);
8192 /* Unless we can use the bras(l) insn, force the
8193 routine address into a register. */
8194 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8197 addr_location = legitimize_pic_address (addr_location, 0);
8199 addr_location = force_reg (Pmode, addr_location);
8203 /* If it is already an indirect call or the code above moved the
8204 SYMBOL_REF to somewhere else make sure the address can be found in
8206 if (retaddr_reg == NULL_RTX
8207 && GET_CODE (addr_location) != SYMBOL_REF
8210 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8211 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8214 addr_location = gen_rtx_MEM (QImode, addr_location);
8215 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8217 if (result_reg != NULL_RTX)
8218 call = gen_rtx_SET (VOIDmode, result_reg, call);
8220 if (retaddr_reg != NULL_RTX)
8222 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8224 if (tls_call != NULL_RTX)
8225 vec = gen_rtvec (3, call, clobber,
8226 gen_rtx_USE (VOIDmode, tls_call));
8228 vec = gen_rtvec (2, call, clobber);
8230 call = gen_rtx_PARALLEL (VOIDmode, vec);
8233 insn = emit_call_insn (call);
8235 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8236 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8238 /* s390_function_ok_for_sibcall should
8239 have denied sibcalls in this case. */
8240 gcc_assert (retaddr_reg != NULL_RTX);
8242 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8247 /* Implement CONDITIONAL_REGISTER_USAGE. */
8250 s390_conditional_register_usage (void)
8256 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8257 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8259 if (TARGET_CPU_ZARCH)
8261 fixed_regs[RETURN_REGNUM] = 0;
8262 call_used_regs[RETURN_REGNUM] = 0;
8266 for (i = 24; i < 32; i++)
8267 call_used_regs[i] = call_really_used_regs[i] = 0;
8271 for (i = 18; i < 20; i++)
8272 call_used_regs[i] = call_really_used_regs[i] = 0;
8275 if (TARGET_SOFT_FLOAT)
8277 for (i = 16; i < 32; i++)
8278 call_used_regs[i] = fixed_regs[i] = 1;
8282 /* Corresponding function to eh_return expander. */
8284 static GTY(()) rtx s390_tpf_eh_return_symbol;
8286 s390_emit_tpf_eh_return (rtx target)
8290 if (!s390_tpf_eh_return_symbol)
8291 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8293 reg = gen_rtx_REG (Pmode, 2);
8295 emit_move_insn (reg, target);
8296 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8297 gen_rtx_REG (Pmode, RETURN_REGNUM));
8298 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8300 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8303 /* Rework the prologue/epilogue to avoid saving/restoring
8304 registers unnecessarily. */
8307 s390_optimize_prologue (void)
8309 rtx insn, new_insn, next_insn;
8311 /* Do a final recompute of the frame-related data. */
8313 s390_update_frame_layout ();
8315 /* If all special registers are in fact used, there's nothing we
8316 can do, so no point in walking the insn list. */
8318 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8319 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8320 && (TARGET_CPU_ZARCH
8321 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8322 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8325 /* Search for prologue/epilogue insns and replace them. */
8327 for (insn = get_insns (); insn; insn = next_insn)
8329 int first, last, off;
8330 rtx set, base, offset;
8332 next_insn = NEXT_INSN (insn);
8334 if (GET_CODE (insn) != INSN)
8337 if (GET_CODE (PATTERN (insn)) == PARALLEL
8338 && store_multiple_operation (PATTERN (insn), VOIDmode))
8340 set = XVECEXP (PATTERN (insn), 0, 0);
8341 first = REGNO (SET_SRC (set));
8342 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8343 offset = const0_rtx;
8344 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8345 off = INTVAL (offset);
8347 if (GET_CODE (base) != REG || off < 0)
8349 if (cfun_frame_layout.first_save_gpr != -1
8350 && (cfun_frame_layout.first_save_gpr < first
8351 || cfun_frame_layout.last_save_gpr > last))
8353 if (REGNO (base) != STACK_POINTER_REGNUM
8354 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8356 if (first > BASE_REGNUM || last < BASE_REGNUM)
8359 if (cfun_frame_layout.first_save_gpr != -1)
8361 new_insn = save_gprs (base,
8362 off + (cfun_frame_layout.first_save_gpr
8363 - first) * UNITS_PER_WORD,
8364 cfun_frame_layout.first_save_gpr,
8365 cfun_frame_layout.last_save_gpr);
8366 new_insn = emit_insn_before (new_insn, insn);
8367 INSN_ADDRESSES_NEW (new_insn, -1);
8374 if (cfun_frame_layout.first_save_gpr == -1
8375 && GET_CODE (PATTERN (insn)) == SET
8376 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8377 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8378 || (!TARGET_CPU_ZARCH
8379 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8380 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8382 set = PATTERN (insn);
8383 first = REGNO (SET_SRC (set));
8384 offset = const0_rtx;
8385 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8386 off = INTVAL (offset);
8388 if (GET_CODE (base) != REG || off < 0)
8390 if (REGNO (base) != STACK_POINTER_REGNUM
8391 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8398 if (GET_CODE (PATTERN (insn)) == PARALLEL
8399 && load_multiple_operation (PATTERN (insn), VOIDmode))
8401 set = XVECEXP (PATTERN (insn), 0, 0);
8402 first = REGNO (SET_DEST (set));
8403 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8404 offset = const0_rtx;
8405 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8406 off = INTVAL (offset);
8408 if (GET_CODE (base) != REG || off < 0)
8410 if (cfun_frame_layout.first_restore_gpr != -1
8411 && (cfun_frame_layout.first_restore_gpr < first
8412 || cfun_frame_layout.last_restore_gpr > last))
8414 if (REGNO (base) != STACK_POINTER_REGNUM
8415 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8417 if (first > BASE_REGNUM || last < BASE_REGNUM)
8420 if (cfun_frame_layout.first_restore_gpr != -1)
8422 new_insn = restore_gprs (base,
8423 off + (cfun_frame_layout.first_restore_gpr
8424 - first) * UNITS_PER_WORD,
8425 cfun_frame_layout.first_restore_gpr,
8426 cfun_frame_layout.last_restore_gpr);
8427 new_insn = emit_insn_before (new_insn, insn);
8428 INSN_ADDRESSES_NEW (new_insn, -1);
8435 if (cfun_frame_layout.first_restore_gpr == -1
8436 && GET_CODE (PATTERN (insn)) == SET
8437 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8438 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8439 || (!TARGET_CPU_ZARCH
8440 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8441 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
8443 set = PATTERN (insn);
8444 first = REGNO (SET_DEST (set));
8445 offset = const0_rtx;
8446 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8447 off = INTVAL (offset);
8449 if (GET_CODE (base) != REG || off < 0)
8451 if (REGNO (base) != STACK_POINTER_REGNUM
8452 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8461 /* Perform machine-dependent processing. */
8466 bool pool_overflow = false;
8468 /* Make sure all splits have been performed; splits after
8469 machine_dependent_reorg might confuse insn length counts. */
8470 split_all_insns_noflow ();
8473 /* Install the main literal pool and the associated base
8474 register load insns.
8476 In addition, there are two problematic situations we need
8479 - the literal pool might be > 4096 bytes in size, so that
8480 some of its elements cannot be directly accessed
8482 - a branch target might be > 64K away from the branch, so that
8483 it is not possible to use a PC-relative instruction.
8485 To fix those, we split the single literal pool into multiple
8486 pool chunks, reloading the pool base register at various
8487 points throughout the function to ensure it always points to
8488 the pool chunk the following code expects, and / or replace
8489 PC-relative branches by absolute branches.
8491 However, the two problems are interdependent: splitting the
8492 literal pool can move a branch further away from its target,
8493 causing the 64K limit to overflow, and on the other hand,
8494 replacing a PC-relative branch by an absolute branch means
8495 we need to put the branch target address into the literal
8496 pool, possibly causing it to overflow.
8498 So, we loop trying to fix up both problems until we manage
8499 to satisfy both conditions at the same time. Note that the
8500 loop is guaranteed to terminate as every pass of the loop
8501 strictly decreases the total number of PC-relative branches
8502 in the function. (This is not completely true as there
8503 might be branch-over-pool insns introduced by chunkify_start.
8504 Those never need to be split however.) */
8508 struct constant_pool *pool = NULL;
8510 /* Collect the literal pool. */
8513 pool = s390_mainpool_start ();
8515 pool_overflow = true;
8518 /* If literal pool overflowed, start to chunkify it. */
8520 pool = s390_chunkify_start ();
8522 /* Split out-of-range branches. If this has created new
8523 literal pool entries, cancel current chunk list and
8524 recompute it. zSeries machines have large branch
8525 instructions, so we never need to split a branch. */
8526 if (!TARGET_CPU_ZARCH && s390_split_branches ())
8529 s390_chunkify_cancel (pool);
8531 s390_mainpool_cancel (pool);
8536 /* If we made it up to here, both conditions are satisfied.
8537 Finish up literal pool related changes. */
8539 s390_chunkify_finish (pool);
8541 s390_mainpool_finish (pool);
8543 /* We're done splitting branches. */
8544 cfun->machine->split_branches_pending_p = false;
8548 /* Generate out-of-pool execute target insns. */
8549 if (TARGET_CPU_ZARCH)
8551 rtx insn, label, target;
8553 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8555 label = s390_execute_label (insn);
8559 gcc_assert (label != const0_rtx);
8561 target = emit_label (XEXP (label, 0));
8562 INSN_ADDRESSES_NEW (target, -1);
8564 target = emit_insn (s390_execute_target (insn));
8565 INSN_ADDRESSES_NEW (target, -1);
8569 /* Try to optimize prologue and epilogue further. */
8570 s390_optimize_prologue ();
8574 /* Initialize GCC target structure. */
8576 #undef TARGET_ASM_ALIGNED_HI_OP
8577 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
8578 #undef TARGET_ASM_ALIGNED_DI_OP
8579 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
8580 #undef TARGET_ASM_INTEGER
8581 #define TARGET_ASM_INTEGER s390_assemble_integer
8583 #undef TARGET_ASM_OPEN_PAREN
8584 #define TARGET_ASM_OPEN_PAREN ""
8586 #undef TARGET_ASM_CLOSE_PAREN
8587 #define TARGET_ASM_CLOSE_PAREN ""
8589 #undef TARGET_DEFAULT_TARGET_FLAGS
8590 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
8591 #undef TARGET_HANDLE_OPTION
8592 #define TARGET_HANDLE_OPTION s390_handle_option
8594 #undef TARGET_ENCODE_SECTION_INFO
8595 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
8598 #undef TARGET_HAVE_TLS
8599 #define TARGET_HAVE_TLS true
8601 #undef TARGET_CANNOT_FORCE_CONST_MEM
8602 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
8604 #undef TARGET_DELEGITIMIZE_ADDRESS
8605 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
8607 #undef TARGET_RETURN_IN_MEMORY
8608 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
8610 #undef TARGET_INIT_BUILTINS
8611 #define TARGET_INIT_BUILTINS s390_init_builtins
8612 #undef TARGET_EXPAND_BUILTIN
8613 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
8615 #undef TARGET_ASM_OUTPUT_MI_THUNK
8616 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
8617 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
8618 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
8620 #undef TARGET_SCHED_ADJUST_PRIORITY
8621 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
8622 #undef TARGET_SCHED_ISSUE_RATE
8623 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
8624 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
8625 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
8627 #undef TARGET_CANNOT_COPY_INSN_P
8628 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
8629 #undef TARGET_RTX_COSTS
8630 #define TARGET_RTX_COSTS s390_rtx_costs
8631 #undef TARGET_ADDRESS_COST
8632 #define TARGET_ADDRESS_COST s390_address_cost
8634 #undef TARGET_MACHINE_DEPENDENT_REORG
8635 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
8637 #undef TARGET_VALID_POINTER_MODE
8638 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
8640 #undef TARGET_BUILD_BUILTIN_VA_LIST
8641 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
8642 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
8643 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
8645 #undef TARGET_PROMOTE_FUNCTION_ARGS
8646 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
8647 #undef TARGET_PROMOTE_FUNCTION_RETURN
8648 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
8649 #undef TARGET_PASS_BY_REFERENCE
8650 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
8652 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
8653 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
8655 #undef TARGET_FIXED_CONDITION_CODE_REGS
8656 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
8658 #undef TARGET_CC_MODES_COMPATIBLE
8659 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
8661 #undef TARGET_INVALID_WITHIN_DOLOOP
8662 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
8665 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
8666 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
8669 struct gcc_target targetm = TARGET_INITIALIZER;
8671 #include "gt-s390.h"