1 ;; Scheduling description for IBM RS64 processors.
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 ;; MA 02111-1307, USA.
21 (define_automaton "rs64,rs64fp")
22 (define_cpu_unit "iu_rs64" "rs64")
23 (define_cpu_unit "mciu_rs64" "rs64")
24 (define_cpu_unit "fpu_rs64" "rs64fp")
25 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
27 ;; RS64a 64-bit IU, LSU, FPU, BPU
29 (define_insn_reservation "rs64a-load" 2
30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
31 (eq_attr "cpu" "rs64a"))
34 (define_insn_reservation "rs64a-store" 1
35 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
36 (eq_attr "cpu" "rs64a"))
39 (define_insn_reservation "rs64a-fpload" 3
40 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
41 (eq_attr "cpu" "rs64a"))
44 (define_insn_reservation "rs64a-integer" 1
45 (and (eq_attr "type" "integer,insert_word")
46 (eq_attr "cpu" "rs64a"))
49 (define_insn_reservation "rs64a-imul" 20
50 (and (eq_attr "type" "imul,imul_compare")
51 (eq_attr "cpu" "rs64a"))
54 (define_insn_reservation "rs64a-imul2" 12
55 (and (eq_attr "type" "imul2")
56 (eq_attr "cpu" "rs64a"))
59 (define_insn_reservation "rs64a-imul3" 8
60 (and (eq_attr "type" "imul3")
61 (eq_attr "cpu" "rs64a"))
64 (define_insn_reservation "rs64a-lmul" 34
65 (and (eq_attr "type" "lmul,lmul_compare")
66 (eq_attr "cpu" "rs64a"))
69 (define_insn_reservation "rs64a-idiv" 66
70 (and (eq_attr "type" "idiv")
71 (eq_attr "cpu" "rs64a"))
74 (define_insn_reservation "rs64a-ldiv" 66
75 (and (eq_attr "type" "ldiv")
76 (eq_attr "cpu" "rs64a"))
79 (define_insn_reservation "rs64a-compare" 3
80 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
81 (eq_attr "cpu" "rs64a"))
82 "iu_rs64,nothing,bpu_rs64")
84 (define_insn_reservation "rs64a-fpcompare" 5
85 (and (eq_attr "type" "fpcompare")
86 (eq_attr "cpu" "rs64a"))
87 "mciu_rs64,fpu_rs64,bpu_rs64")
89 (define_insn_reservation "rs64a-fp" 4
90 (and (eq_attr "type" "fp,dmul")
91 (eq_attr "cpu" "rs64a"))
94 (define_insn_reservation "rs64a-sdiv" 31
95 (and (eq_attr "type" "sdiv,ddiv")
96 (eq_attr "cpu" "rs64a"))
97 "mciu_rs64,fpu_rs64*31")
99 (define_insn_reservation "rs64a-sqrt" 49
100 (and (eq_attr "type" "ssqrt,dsqrt")
101 (eq_attr "cpu" "rs64a"))
102 "mciu_rs64,fpu_rs64*49")
104 (define_insn_reservation "rs64a-mfcr" 2
105 (and (eq_attr "type" "mfcr")
106 (eq_attr "cpu" "rs64a"))
109 (define_insn_reservation "rs64a-mtcr" 3
110 (and (eq_attr "type" "mtcr")
111 (eq_attr "cpu" "rs64a"))
114 (define_insn_reservation "rs64a-mtjmpr" 3
115 (and (eq_attr "type" "mtjmpr")
116 (eq_attr "cpu" "rs64a"))
119 (define_insn_reservation "rs64a-mfjmpr" 2
120 (and (eq_attr "type" "mfjmpr")
121 (eq_attr "cpu" "rs64a"))
124 (define_insn_reservation "rs64a-jmpreg" 1
125 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
126 (eq_attr "cpu" "rs64a"))