1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 Target Report RejectNegative Mask(POWER)
24 Use POWER instruction set
27 Target Report RejectNegative
28 Do not use POWER instruction set
31 Target Report Mask(POWER2)
32 Use POWER2 instruction set
35 Target Report RejectNegative Mask(POWERPC)
36 Use PowerPC instruction set
39 Target Report RejectNegative
40 Do not use PowerPC instruction set
43 Target Report Mask(POWERPC64)
44 Use PowerPC-64 instruction set
47 Target Report Mask(PPC_GPOPT)
48 Use PowerPC General Purpose group optional instructions
51 Target Report Mask(PPC_GFXOPT)
52 Use PowerPC Graphics group optional instructions
55 Target Report Mask(MFCRF)
56 Use PowerPC V2.01 single field mfcr instruction
59 Target Report Mask(POPCNTB)
60 Use PowerPC V2.02 popcntb instruction
63 Target Report Mask(FPRND)
64 Use PowerPC V2.02 floating point rounding instructions
67 Target Report Mask(CMPB)
68 Use PowerPC V2.05 compare bytes instruction
71 Target Report Mask(MFPGPR)
72 Use extended PowerPC V2.05 move floating point to/from GPR instructions
75 Target Report Mask(ALTIVEC)
76 Use AltiVec instructions
79 Target Report Mask(DFP)
80 Use decimal floating point instructions
83 Target Report Mask(MULHW)
84 Use 4xx half-word multiply instructions
87 Target Report Mask(DLMZB)
88 Use 4xx string-search dlmzb instruction
91 Target Report Mask(MULTIPLE)
92 Generate load/store multiple instructions
95 Target Report Mask(STRING)
96 Generate string instructions for block moves
99 Target Report RejectNegative Mask(NEW_MNEMONICS)
100 Use new mnemonics for PowerPC architecture
103 Target Report RejectNegative InverseMask(NEW_MNEMONICS)
104 Use old mnemonics for PowerPC architecture
107 Target Report RejectNegative Mask(SOFT_FLOAT)
108 Do not use hardware floating point
111 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
112 Use hardware floating point
115 Target Report Mask(POPCNTD)
116 Use PowerPC V2.06 popcntd instruction
119 Target Report Mask(VSX)
120 Use vector/scalar (VSX) instructions
123 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
124 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
127 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
128 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
131 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
132 ; If -mvsx, set alignment to 128 bits instead of 32/64
135 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
136 ; Allow/disallow the movmisalign in DF/DI vectors
139 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
140 ; Allow/disallow permutation of DF/DI vectors
143 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
144 ; Explicitly set/unset whether rs6000_sched_groups is set
147 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
148 ; Explicitly set/unset whether rs6000_always_hint is set
150 malign-branch-targets
151 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
152 ; Explicitly set/unset whether rs6000_align_branch_targets is set
155 Target Report Var(TARGET_UPDATE) Init(1)
156 Generate load/store with update instructions
158 mavoid-indexed-addresses
159 Target Report Var(TARGET_AVOID_XFORM) Init(-1)
160 Avoid generation of indexed load/store instructions when possible
163 Target Report Var(TARGET_FUSED_MADD) Init(1)
164 Generate fused multiply/add instructions
167 Target Report Var(tls_markers) Init(1)
168 Mark __tls_get_addr calls with argument info
171 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1)
174 Target Report Var(TARGET_SCHED_PROLOG) VarExists
175 Schedule the start and end of the procedure
178 Target Report RejectNegative Var(aix_struct_return)
179 Return all structures in memory (AIX default)
182 Target Report RejectNegative Var(aix_struct_return,0) VarExists
183 Return small structures in registers (SVR4 default)
186 Target Report Var(TARGET_XL_COMPAT)
187 Conform more closely to IBM XLC semantics
190 Target Report Var(TARGET_RECIP)
191 Generate software reciprocal sqrt for better throughput
194 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
195 Do not place floating point constants in TOC
198 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0)
199 Place floating point constants in TOC
202 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
203 Do not place symbol+offset constants in TOC
206 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists
207 Place symbol+offset constants in TOC
209 ; Output only one TOC entry per module. Normally linking fails if
210 ; there are more than 16K unique variables/constants in an executable. With
211 ; this option, linking fails only if there are more than 16K modules, or
212 ; if there are more than 16K unique variables/constant in a single module.
214 ; This is at the cost of having 2 extra loads and one extra store per
215 ; function, and one less allocable register.
217 Target Report Mask(MINIMAL_TOC)
218 Use only one TOC entry per procedure
222 Put everything in the regular TOC
225 Target Report Var(TARGET_ALTIVEC_VRSAVE)
226 Generate VRSAVE instructions when generating AltiVec code
229 Target RejectNegative Joined
230 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
233 Target Report Mask(ISEL)
234 Generate isel instructions
237 Target RejectNegative Joined
238 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead
242 Generate SPE SIMD instructions on E500
245 Target Var(rs6000_paired_float)
246 Generate PPC750CL paired-single instructions
249 Target RejectNegative Joined
250 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
253 Target RejectNegative Joined
254 -mdebug= Enable debug output
257 Target RejectNegative Joined
258 -mabi= Specify ABI to use
261 Target RejectNegative Joined
262 -mcpu= Use features of and schedule code for given CPU
265 Target RejectNegative Joined
266 -mtune= Schedule code for given CPU
269 Target RejectNegative Joined
270 -mtraceback= Select full, part, or no traceback table
273 Target Report Var(rs6000_default_long_calls)
274 Avoid all range limits on call instructions
277 Target Report Var(rs6000_gen_cell_microcode) Init(-1)
278 Generate Cell microcode
281 Target Var(rs6000_warn_cell_microcode) Init(0) Warning
282 Warn when a Cell microcoded instruction is emitted
285 Target Var(rs6000_warn_altivec_long) Init(1)
286 Warn about deprecated 'vector long ...' AltiVec type usage
289 Target RejectNegative Joined
290 -mfloat-gprs= Select GPR floating point method
293 Target RejectNegative Joined UInteger
294 -mlong-double-<n> Specify size of long double (64 or 128 bits)
297 Target RejectNegative Joined
298 Determine which dependences between insns are considered costly
301 Target RejectNegative Joined
302 Specify which post scheduling nop insertion scheme to apply
305 Target RejectNegative Joined
306 Specify alignment of structure fields default/natural
308 mprioritize-restricted-insns=
309 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
310 Specify scheduling priority for dispatch slot restricted insns
313 Target RejectNegative Var(rs6000_single_float)
314 Single-precision floating point unit
317 Target RejectNegative Var(rs6000_double_float)
318 Double-precision floating point unit
321 Target RejectNegative Var(rs6000_simple_fpu)
322 Floating point unit does not support divide & sqrt
325 Target RejectNegative Joined
326 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
329 Target Var(rs6000_xilinx_fpu)