1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
64 ;; UNSPEC_VOLATILE usage
69 (UNSPECV_EH_RR 9) ; eh_reg_restore
72 ;; Define an insn type attribute. This is used in function unit delay
74 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
75 (const_string "integer"))
78 ; '(pc)' in the following doesn't include the instruction itself; it is
79 ; calculated as if the instruction had zero size.
80 (define_attr "length" ""
81 (if_then_else (eq_attr "type" "branch")
82 (if_then_else (and (ge (minus (match_dup 0) (pc))
84 (lt (minus (match_dup 0) (pc))
90 ;; Processor type -- this attribute must exactly match the processor_type
91 ;; enumeration in rs6000.h.
93 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
94 (const (symbol_ref "rs6000_cpu_attr")))
96 (automata_option "ndfa")
109 (include "power4.md")
110 (include "power5.md")
112 (include "predicates.md")
114 (include "darwin.md")
119 ; This mode macro allows :GPR to be used to indicate the allowable size
120 ; of whole values in GPRs.
121 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
123 ; Any supported integer mode.
124 (define_mode_macro INT [QI HI SI DI TI])
126 ; Any supported integer mode that fits in one register.
127 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
129 ; SImode or DImode, even if DImode doesn't fit in GPRs.
130 (define_mode_macro SDI [SI DI])
132 ; The size of a pointer. Also, the size of the value that a record-condition
133 ; (one with a '.') will compare.
134 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
136 ; Various instructions that come in SI and DI forms.
137 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
138 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
139 ; A generic w/d attribute, for things like cmpw/cmpd.
140 (define_mode_attr wd [(SI "w") (DI "d")])
143 ;; Start with fixed-point load and store insns. Here we put only the more
144 ;; complex forms. Basic data transfer is done later.
146 (define_expand "zero_extendqidi2"
147 [(set (match_operand:DI 0 "gpc_reg_operand" "")
148 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
153 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
154 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
159 [(set_attr "type" "load,*")])
162 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
163 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
165 (clobber (match_scratch:DI 2 "=r,r"))]
170 [(set_attr "type" "compare")
171 (set_attr "length" "4,8")])
174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
175 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
177 (clobber (match_scratch:DI 2 ""))]
178 "TARGET_POWERPC64 && reload_completed"
180 (zero_extend:DI (match_dup 1)))
182 (compare:CC (match_dup 2)
187 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
188 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
190 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
191 (zero_extend:DI (match_dup 1)))]
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
200 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
201 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
203 (set (match_operand:DI 0 "gpc_reg_operand" "")
204 (zero_extend:DI (match_dup 1)))]
205 "TARGET_POWERPC64 && reload_completed"
207 (zero_extend:DI (match_dup 1)))
209 (compare:CC (match_dup 0)
213 (define_insn "extendqidi2"
214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
215 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
221 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
223 (clobber (match_scratch:DI 2 "=r,r"))]
228 [(set_attr "type" "compare")
229 (set_attr "length" "4,8")])
232 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
233 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
235 (clobber (match_scratch:DI 2 ""))]
236 "TARGET_POWERPC64 && reload_completed"
238 (sign_extend:DI (match_dup 1)))
240 (compare:CC (match_dup 2)
245 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
246 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
248 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
249 (sign_extend:DI (match_dup 1)))]
254 [(set_attr "type" "compare")
255 (set_attr "length" "4,8")])
258 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
259 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
261 (set (match_operand:DI 0 "gpc_reg_operand" "")
262 (sign_extend:DI (match_dup 1)))]
263 "TARGET_POWERPC64 && reload_completed"
265 (sign_extend:DI (match_dup 1)))
267 (compare:CC (match_dup 0)
271 (define_expand "zero_extendhidi2"
272 [(set (match_operand:DI 0 "gpc_reg_operand" "")
273 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
278 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
279 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
284 [(set_attr "type" "load,*")])
287 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
288 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
290 (clobber (match_scratch:DI 2 "=r,r"))]
295 [(set_attr "type" "compare")
296 (set_attr "length" "4,8")])
299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
300 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
302 (clobber (match_scratch:DI 2 ""))]
303 "TARGET_POWERPC64 && reload_completed"
305 (zero_extend:DI (match_dup 1)))
307 (compare:CC (match_dup 2)
312 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
313 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
315 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
316 (zero_extend:DI (match_dup 1)))]
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
325 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
326 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
328 (set (match_operand:DI 0 "gpc_reg_operand" "")
329 (zero_extend:DI (match_dup 1)))]
330 "TARGET_POWERPC64 && reload_completed"
332 (zero_extend:DI (match_dup 1)))
334 (compare:CC (match_dup 0)
338 (define_expand "extendhidi2"
339 [(set (match_operand:DI 0 "gpc_reg_operand" "")
340 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
345 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
346 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
351 [(set_attr "type" "load_ext,*")])
354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
355 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
357 (clobber (match_scratch:DI 2 "=r,r"))]
362 [(set_attr "type" "compare")
363 (set_attr "length" "4,8")])
366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
367 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
369 (clobber (match_scratch:DI 2 ""))]
370 "TARGET_POWERPC64 && reload_completed"
372 (sign_extend:DI (match_dup 1)))
374 (compare:CC (match_dup 2)
379 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
380 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
383 (sign_extend:DI (match_dup 1)))]
388 [(set_attr "type" "compare")
389 (set_attr "length" "4,8")])
392 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
393 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
395 (set (match_operand:DI 0 "gpc_reg_operand" "")
396 (sign_extend:DI (match_dup 1)))]
397 "TARGET_POWERPC64 && reload_completed"
399 (sign_extend:DI (match_dup 1)))
401 (compare:CC (match_dup 0)
405 (define_expand "zero_extendsidi2"
406 [(set (match_operand:DI 0 "gpc_reg_operand" "")
407 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
418 [(set_attr "type" "load,*")])
421 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
422 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
424 (clobber (match_scratch:DI 2 "=r,r"))]
429 [(set_attr "type" "compare")
430 (set_attr "length" "4,8")])
433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
434 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
436 (clobber (match_scratch:DI 2 ""))]
437 "TARGET_POWERPC64 && reload_completed"
439 (zero_extend:DI (match_dup 1)))
441 (compare:CC (match_dup 2)
446 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
447 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
449 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
450 (zero_extend:DI (match_dup 1)))]
455 [(set_attr "type" "compare")
456 (set_attr "length" "4,8")])
459 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
460 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
462 (set (match_operand:DI 0 "gpc_reg_operand" "")
463 (zero_extend:DI (match_dup 1)))]
464 "TARGET_POWERPC64 && reload_completed"
466 (zero_extend:DI (match_dup 1)))
468 (compare:CC (match_dup 0)
472 (define_expand "extendsidi2"
473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
474 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
479 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
480 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
485 [(set_attr "type" "load_ext,*")])
488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
489 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
491 (clobber (match_scratch:DI 2 "=r,r"))]
496 [(set_attr "type" "compare")
497 (set_attr "length" "4,8")])
500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
501 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
503 (clobber (match_scratch:DI 2 ""))]
504 "TARGET_POWERPC64 && reload_completed"
506 (sign_extend:DI (match_dup 1)))
508 (compare:CC (match_dup 2)
513 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
514 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
516 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
517 (sign_extend:DI (match_dup 1)))]
522 [(set_attr "type" "compare")
523 (set_attr "length" "4,8")])
526 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
527 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
529 (set (match_operand:DI 0 "gpc_reg_operand" "")
530 (sign_extend:DI (match_dup 1)))]
531 "TARGET_POWERPC64 && reload_completed"
533 (sign_extend:DI (match_dup 1)))
535 (compare:CC (match_dup 0)
539 (define_expand "zero_extendqisi2"
540 [(set (match_operand:SI 0 "gpc_reg_operand" "")
541 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
547 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
551 {rlinm|rlwinm} %0,%1,0,0xff"
552 [(set_attr "type" "load,*")])
555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
556 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
558 (clobber (match_scratch:SI 2 "=r,r"))]
561 {andil.|andi.} %2,%1,0xff
563 [(set_attr "type" "compare")
564 (set_attr "length" "4,8")])
567 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
568 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
570 (clobber (match_scratch:SI 2 ""))]
573 (zero_extend:SI (match_dup 1)))
575 (compare:CC (match_dup 2)
580 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
581 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
583 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
584 (zero_extend:SI (match_dup 1)))]
587 {andil.|andi.} %0,%1,0xff
589 [(set_attr "type" "compare")
590 (set_attr "length" "4,8")])
593 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
594 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
596 (set (match_operand:SI 0 "gpc_reg_operand" "")
597 (zero_extend:SI (match_dup 1)))]
600 (zero_extend:SI (match_dup 1)))
602 (compare:CC (match_dup 0)
606 (define_expand "extendqisi2"
607 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
608 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
613 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
614 else if (TARGET_POWER)
615 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
617 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
621 (define_insn "extendqisi2_ppc"
622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
623 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
628 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
629 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
631 (clobber (match_scratch:SI 2 "=r,r"))]
636 [(set_attr "type" "compare")
637 (set_attr "length" "4,8")])
640 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
643 (clobber (match_scratch:SI 2 ""))]
644 "TARGET_POWERPC && reload_completed"
646 (sign_extend:SI (match_dup 1)))
648 (compare:CC (match_dup 2)
653 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
654 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
656 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
657 (sign_extend:SI (match_dup 1)))]
662 [(set_attr "type" "compare")
663 (set_attr "length" "4,8")])
666 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
667 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
669 (set (match_operand:SI 0 "gpc_reg_operand" "")
670 (sign_extend:SI (match_dup 1)))]
671 "TARGET_POWERPC && reload_completed"
673 (sign_extend:SI (match_dup 1)))
675 (compare:CC (match_dup 0)
679 (define_expand "extendqisi2_power"
680 [(parallel [(set (match_dup 2)
681 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
683 (clobber (scratch:SI))])
684 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
685 (ashiftrt:SI (match_dup 2)
687 (clobber (scratch:SI))])]
690 { operands[1] = gen_lowpart (SImode, operands[1]);
691 operands[2] = gen_reg_rtx (SImode); }")
693 (define_expand "extendqisi2_no_power"
695 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
697 (set (match_operand:SI 0 "gpc_reg_operand" "")
698 (ashiftrt:SI (match_dup 2)
700 "! TARGET_POWER && ! TARGET_POWERPC"
702 { operands[1] = gen_lowpart (SImode, operands[1]);
703 operands[2] = gen_reg_rtx (SImode); }")
705 (define_expand "zero_extendqihi2"
706 [(set (match_operand:HI 0 "gpc_reg_operand" "")
707 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
712 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
717 {rlinm|rlwinm} %0,%1,0,0xff"
718 [(set_attr "type" "load,*")])
721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
722 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
724 (clobber (match_scratch:HI 2 "=r,r"))]
727 {andil.|andi.} %2,%1,0xff
729 [(set_attr "type" "compare")
730 (set_attr "length" "4,8")])
733 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
736 (clobber (match_scratch:HI 2 ""))]
739 (zero_extend:HI (match_dup 1)))
741 (compare:CC (match_dup 2)
746 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
747 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
749 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
750 (zero_extend:HI (match_dup 1)))]
753 {andil.|andi.} %0,%1,0xff
755 [(set_attr "type" "compare")
756 (set_attr "length" "4,8")])
759 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
760 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
762 (set (match_operand:HI 0 "gpc_reg_operand" "")
763 (zero_extend:HI (match_dup 1)))]
766 (zero_extend:HI (match_dup 1)))
768 (compare:CC (match_dup 0)
772 (define_expand "extendqihi2"
773 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
774 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
779 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
780 else if (TARGET_POWER)
781 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
783 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
787 (define_insn "extendqihi2_ppc"
788 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
789 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
794 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
797 (clobber (match_scratch:HI 2 "=r,r"))]
802 [(set_attr "type" "compare")
803 (set_attr "length" "4,8")])
806 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
807 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
809 (clobber (match_scratch:HI 2 ""))]
810 "TARGET_POWERPC && reload_completed"
812 (sign_extend:HI (match_dup 1)))
814 (compare:CC (match_dup 2)
819 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
820 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
822 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
823 (sign_extend:HI (match_dup 1)))]
828 [(set_attr "type" "compare")
829 (set_attr "length" "4,8")])
832 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
833 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
835 (set (match_operand:HI 0 "gpc_reg_operand" "")
836 (sign_extend:HI (match_dup 1)))]
837 "TARGET_POWERPC && reload_completed"
839 (sign_extend:HI (match_dup 1)))
841 (compare:CC (match_dup 0)
845 (define_expand "extendqihi2_power"
846 [(parallel [(set (match_dup 2)
847 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
849 (clobber (scratch:SI))])
850 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
851 (ashiftrt:SI (match_dup 2)
853 (clobber (scratch:SI))])]
856 { operands[0] = gen_lowpart (SImode, operands[0]);
857 operands[1] = gen_lowpart (SImode, operands[1]);
858 operands[2] = gen_reg_rtx (SImode); }")
860 (define_expand "extendqihi2_no_power"
862 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
864 (set (match_operand:HI 0 "gpc_reg_operand" "")
865 (ashiftrt:SI (match_dup 2)
867 "! TARGET_POWER && ! TARGET_POWERPC"
869 { operands[0] = gen_lowpart (SImode, operands[0]);
870 operands[1] = gen_lowpart (SImode, operands[1]);
871 operands[2] = gen_reg_rtx (SImode); }")
873 (define_expand "zero_extendhisi2"
874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
875 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
881 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
885 {rlinm|rlwinm} %0,%1,0,0xffff"
886 [(set_attr "type" "load,*")])
889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
892 (clobber (match_scratch:SI 2 "=r,r"))]
895 {andil.|andi.} %2,%1,0xffff
897 [(set_attr "type" "compare")
898 (set_attr "length" "4,8")])
901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
902 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
904 (clobber (match_scratch:SI 2 ""))]
907 (zero_extend:SI (match_dup 1)))
909 (compare:CC (match_dup 2)
914 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
915 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
917 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
918 (zero_extend:SI (match_dup 1)))]
921 {andil.|andi.} %0,%1,0xffff
923 [(set_attr "type" "compare")
924 (set_attr "length" "4,8")])
927 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
928 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
930 (set (match_operand:SI 0 "gpc_reg_operand" "")
931 (zero_extend:SI (match_dup 1)))]
934 (zero_extend:SI (match_dup 1)))
936 (compare:CC (match_dup 0)
940 (define_expand "extendhisi2"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
942 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
953 [(set_attr "type" "load_ext,*")])
956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
957 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
959 (clobber (match_scratch:SI 2 "=r,r"))]
964 [(set_attr "type" "compare")
965 (set_attr "length" "4,8")])
968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
969 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
971 (clobber (match_scratch:SI 2 ""))]
974 (sign_extend:SI (match_dup 1)))
976 (compare:CC (match_dup 2)
981 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
982 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
985 (sign_extend:SI (match_dup 1)))]
990 [(set_attr "type" "compare")
991 (set_attr "length" "4,8")])
994 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
995 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
997 (set (match_operand:SI 0 "gpc_reg_operand" "")
998 (sign_extend:SI (match_dup 1)))]
1001 (sign_extend:SI (match_dup 1)))
1003 (compare:CC (match_dup 0)
1007 ;; Fixed-point arithmetic insns.
1009 (define_expand "add<mode>3"
1010 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1011 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1012 (match_operand:SDI 2 "reg_or_arith_cint_operand" "")))]
1016 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1018 if (non_short_cint_operand (operands[2], DImode))
1021 else if (GET_CODE (operands[2]) == CONST_INT
1022 && ! add_operand (operands[2], <MODE>mode))
1024 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1025 ? operands[0] : gen_reg_rtx (<MODE>mode));
1027 HOST_WIDE_INT val = INTVAL (operands[2]);
1028 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1029 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1031 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1034 /* The ordering here is important for the prolog expander.
1035 When space is allocated from the stack, adding 'low' first may
1036 produce a temporary deallocation (which would be bad). */
1037 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1038 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1043 ;; Discourage ai/addic because of carry but provide it in an alternative
1044 ;; allowing register zero as source.
1045 (define_insn "*add<mode>3_internal1"
1046 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1047 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1048 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1052 {cal %0,%2(%1)|addi %0,%1,%2}
1054 {cau|addis} %0,%1,%v2"
1055 [(set_attr "length" "4,4,4,4")])
1057 (define_insn "addsi3_high"
1058 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1059 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1060 (high:SI (match_operand 2 "" ""))))]
1061 "TARGET_MACHO && !TARGET_64BIT"
1062 "{cau|addis} %0,%1,ha16(%2)"
1063 [(set_attr "length" "4")])
1065 (define_insn "*add<mode>3_internal2"
1066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1067 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1068 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1070 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1073 {cax.|add.} %3,%1,%2
1074 {ai.|addic.} %3,%1,%2
1077 [(set_attr "type" "fast_compare,compare,compare,compare")
1078 (set_attr "length" "4,4,8,8")])
1081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1082 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1083 (match_operand:GPR 2 "reg_or_short_operand" ""))
1085 (clobber (match_scratch:GPR 3 ""))]
1088 (plus:GPR (match_dup 1)
1091 (compare:CC (match_dup 3)
1095 (define_insn "*add<mode>3_internal3"
1096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1097 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1098 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1101 (plus:P (match_dup 1)
1105 {cax.|add.} %0,%1,%2
1106 {ai.|addic.} %0,%1,%2
1109 [(set_attr "type" "fast_compare,compare,compare,compare")
1110 (set_attr "length" "4,4,8,8")])
1113 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1114 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1115 (match_operand:P 2 "reg_or_short_operand" ""))
1117 (set (match_operand:P 0 "gpc_reg_operand" "")
1118 (plus:P (match_dup 1) (match_dup 2)))]
1121 (plus:P (match_dup 1)
1124 (compare:CC (match_dup 0)
1128 ;; Split an add that we can't do in one insn into two insns, each of which
1129 ;; does one 16-bit part. This is used by combine. Note that the low-order
1130 ;; add should be last in case the result gets used in an address.
1133 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1134 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1135 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1137 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1138 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1141 HOST_WIDE_INT val = INTVAL (operands[2]);
1142 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1143 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1145 operands[4] = GEN_INT (low);
1146 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1147 operands[3] = GEN_INT (rest);
1148 else if (! no_new_pseudos)
1150 operands[3] = gen_reg_rtx (DImode);
1151 emit_move_insn (operands[3], operands[2]);
1152 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1159 (define_insn "one_cmpl<mode>2"
1160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1161 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1167 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1169 (clobber (match_scratch:P 2 "=r,r"))]
1174 [(set_attr "type" "compare")
1175 (set_attr "length" "4,8")])
1178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1179 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1181 (clobber (match_scratch:P 2 ""))]
1184 (not:P (match_dup 1)))
1186 (compare:CC (match_dup 2)
1191 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1192 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1194 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1195 (not:P (match_dup 1)))]
1200 [(set_attr "type" "compare")
1201 (set_attr "length" "4,8")])
1204 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1205 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1207 (set (match_operand:P 0 "gpc_reg_operand" "")
1208 (not:P (match_dup 1)))]
1211 (not:P (match_dup 1)))
1213 (compare:CC (match_dup 0)
1218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1219 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1220 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1222 "{sf%I1|subf%I1c} %0,%2,%1")
1225 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1226 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1227 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1235 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1236 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1238 (clobber (match_scratch:SI 3 "=r,r"))]
1241 {sf.|subfc.} %3,%2,%1
1243 [(set_attr "type" "compare")
1244 (set_attr "length" "4,8")])
1247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1248 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1249 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1251 (clobber (match_scratch:P 3 "=r,r"))]
1256 [(set_attr "type" "fast_compare")
1257 (set_attr "length" "4,8")])
1260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1261 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1262 (match_operand:P 2 "gpc_reg_operand" ""))
1264 (clobber (match_scratch:P 3 ""))]
1267 (minus:P (match_dup 1)
1270 (compare:CC (match_dup 3)
1275 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1276 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1277 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1279 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1280 (minus:SI (match_dup 1) (match_dup 2)))]
1283 {sf.|subfc.} %0,%2,%1
1285 [(set_attr "type" "compare")
1286 (set_attr "length" "4,8")])
1289 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1290 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1291 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1293 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1294 (minus:P (match_dup 1)
1300 [(set_attr "type" "fast_compare")
1301 (set_attr "length" "4,8")])
1304 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1305 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1306 (match_operand:P 2 "gpc_reg_operand" ""))
1308 (set (match_operand:P 0 "gpc_reg_operand" "")
1309 (minus:P (match_dup 1)
1313 (minus:P (match_dup 1)
1316 (compare:CC (match_dup 0)
1320 (define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand")
1321 (DI "reg_or_sub_cint64_operand")])
1323 (define_expand "sub<mode>3"
1324 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1325 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1326 (match_operand:SDI 2 "<sub_op2>" "")))]
1330 if (GET_CODE (operands[2]) == CONST_INT)
1332 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1333 negate_rtx (<MODE>mode, operands[2])));
1338 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1339 ;; instruction and some auxiliary computations. Then we just have a single
1340 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1343 (define_expand "sminsi3"
1345 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1346 (match_operand:SI 2 "reg_or_short_operand" ""))
1348 (minus:SI (match_dup 2) (match_dup 1))))
1349 (set (match_operand:SI 0 "gpc_reg_operand" "")
1350 (minus:SI (match_dup 2) (match_dup 3)))]
1351 "TARGET_POWER || TARGET_ISEL"
1356 operands[2] = force_reg (SImode, operands[2]);
1357 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1361 operands[3] = gen_reg_rtx (SImode);
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1366 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1367 (match_operand:SI 2 "reg_or_short_operand" "")))
1368 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1371 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1373 (minus:SI (match_dup 2) (match_dup 1))))
1374 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1377 (define_expand "smaxsi3"
1379 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1380 (match_operand:SI 2 "reg_or_short_operand" ""))
1382 (minus:SI (match_dup 2) (match_dup 1))))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "")
1384 (plus:SI (match_dup 3) (match_dup 1)))]
1385 "TARGET_POWER || TARGET_ISEL"
1390 operands[2] = force_reg (SImode, operands[2]);
1391 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1394 operands[3] = gen_reg_rtx (SImode);
1398 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1399 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1400 (match_operand:SI 2 "reg_or_short_operand" "")))
1401 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1404 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1406 (minus:SI (match_dup 2) (match_dup 1))))
1407 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1410 (define_expand "uminsi3"
1411 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1413 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1415 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1417 (minus:SI (match_dup 4) (match_dup 3))))
1418 (set (match_operand:SI 0 "gpc_reg_operand" "")
1419 (minus:SI (match_dup 2) (match_dup 3)))]
1420 "TARGET_POWER || TARGET_ISEL"
1425 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1428 operands[3] = gen_reg_rtx (SImode);
1429 operands[4] = gen_reg_rtx (SImode);
1430 operands[5] = GEN_INT (-2147483647 - 1);
1433 (define_expand "umaxsi3"
1434 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1436 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1438 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1440 (minus:SI (match_dup 4) (match_dup 3))))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "")
1442 (plus:SI (match_dup 3) (match_dup 1)))]
1443 "TARGET_POWER || TARGET_ISEL"
1448 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1451 operands[3] = gen_reg_rtx (SImode);
1452 operands[4] = gen_reg_rtx (SImode);
1453 operands[5] = GEN_INT (-2147483647 - 1);
1457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1458 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1459 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1461 (minus:SI (match_dup 2) (match_dup 1))))]
1466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1468 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1469 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1471 (minus:SI (match_dup 2) (match_dup 1)))
1473 (clobber (match_scratch:SI 3 "=r,r"))]
1478 [(set_attr "type" "delayed_compare")
1479 (set_attr "length" "4,8")])
1482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1484 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1485 (match_operand:SI 2 "reg_or_short_operand" ""))
1487 (minus:SI (match_dup 2) (match_dup 1)))
1489 (clobber (match_scratch:SI 3 ""))]
1490 "TARGET_POWER && reload_completed"
1492 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1494 (minus:SI (match_dup 2) (match_dup 1))))
1496 (compare:CC (match_dup 3)
1501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1503 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1504 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1506 (minus:SI (match_dup 2) (match_dup 1)))
1508 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1509 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1511 (minus:SI (match_dup 2) (match_dup 1))))]
1516 [(set_attr "type" "delayed_compare")
1517 (set_attr "length" "4,8")])
1520 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1522 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1523 (match_operand:SI 2 "reg_or_short_operand" ""))
1525 (minus:SI (match_dup 2) (match_dup 1)))
1527 (set (match_operand:SI 0 "gpc_reg_operand" "")
1528 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1530 (minus:SI (match_dup 2) (match_dup 1))))]
1531 "TARGET_POWER && reload_completed"
1533 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1535 (minus:SI (match_dup 2) (match_dup 1))))
1537 (compare:CC (match_dup 0)
1541 ;; We don't need abs with condition code because such comparisons should
1543 (define_expand "abssi2"
1544 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1545 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1551 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1554 else if (! TARGET_POWER)
1556 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1561 (define_insn "*abssi2_power"
1562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1563 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1567 (define_insn_and_split "abssi2_isel"
1568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1569 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1570 (clobber (match_scratch:SI 2 "=&b"))
1571 (clobber (match_scratch:CC 3 "=y"))]
1574 "&& reload_completed"
1575 [(set (match_dup 2) (neg:SI (match_dup 1)))
1577 (compare:CC (match_dup 1)
1580 (if_then_else:SI (ge (match_dup 3)
1586 (define_insn_and_split "abssi2_nopower"
1587 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1588 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1589 (clobber (match_scratch:SI 2 "=&r,&r"))]
1590 "! TARGET_POWER && ! TARGET_ISEL"
1592 "&& reload_completed"
1593 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1594 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1595 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1598 (define_insn "*nabs_power"
1599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1600 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1604 (define_insn_and_split "*nabs_nopower"
1605 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1606 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1607 (clobber (match_scratch:SI 2 "=&r,&r"))]
1610 "&& reload_completed"
1611 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1612 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1613 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1616 (define_expand "neg<mode>2"
1617 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1618 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1622 (define_insn "*neg<mode>2_internal"
1623 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1624 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1629 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1630 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1632 (clobber (match_scratch:P 2 "=r,r"))]
1637 [(set_attr "type" "fast_compare")
1638 (set_attr "length" "4,8")])
1641 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1642 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1644 (clobber (match_scratch:P 2 ""))]
1647 (neg:P (match_dup 1)))
1649 (compare:CC (match_dup 2)
1654 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1655 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1657 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1658 (neg:P (match_dup 1)))]
1663 [(set_attr "type" "fast_compare")
1664 (set_attr "length" "4,8")])
1667 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1668 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1670 (set (match_operand:P 0 "gpc_reg_operand" "")
1671 (neg:P (match_dup 1)))]
1672 "TARGET_32BIT && reload_completed"
1674 (neg:P (match_dup 1)))
1676 (compare:CC (match_dup 0)
1680 (define_insn "clz<mode>2"
1681 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1682 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1684 "{cntlz|cntlz<wd>} %0,%1")
1686 (define_expand "ctz<mode>2"
1688 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1689 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1691 (clobber (scratch:CC))])
1692 (set (match_dup 4) (clz:GPR (match_dup 3)))
1693 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1694 (minus:GPR (match_dup 5) (match_dup 4)))]
1697 operands[2] = gen_reg_rtx (<MODE>mode);
1698 operands[3] = gen_reg_rtx (<MODE>mode);
1699 operands[4] = gen_reg_rtx (<MODE>mode);
1700 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1703 (define_expand "ffs<mode>2"
1705 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1706 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1708 (clobber (scratch:CC))])
1709 (set (match_dup 4) (clz:GPR (match_dup 3)))
1710 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1711 (minus:GPR (match_dup 5) (match_dup 4)))]
1714 operands[2] = gen_reg_rtx (<MODE>mode);
1715 operands[3] = gen_reg_rtx (<MODE>mode);
1716 operands[4] = gen_reg_rtx (<MODE>mode);
1717 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1720 (define_expand "popcount<mode>2"
1722 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1725 (mult:GPR (match_dup 2) (match_dup 4)))
1726 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1727 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1730 operands[2] = gen_reg_rtx (<MODE>mode);
1731 operands[3] = gen_reg_rtx (<MODE>mode);
1732 operands[4] = force_reg (<MODE>mode,
1733 <MODE>mode == SImode
1734 ? GEN_INT (0x01010101)
1735 : GEN_INT ((HOST_WIDE_INT)
1736 0x01010101 << 32 | 0x01010101));
1737 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1740 (define_insn "popcntb<mode>2"
1741 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1742 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1747 (define_expand "mulsi3"
1748 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1749 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1750 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1755 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1757 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1761 (define_insn "mulsi3_mq"
1762 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1763 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1765 (clobber (match_scratch:SI 3 "=q,q"))]
1768 {muls|mullw} %0,%1,%2
1769 {muli|mulli} %0,%1,%2"
1771 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1772 (const_string "imul3")
1773 (match_operand:SI 2 "short_cint_operand" "")
1774 (const_string "imul2")]
1775 (const_string "imul")))])
1777 (define_insn "mulsi3_no_mq"
1778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1779 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1780 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1783 {muls|mullw} %0,%1,%2
1784 {muli|mulli} %0,%1,%2"
1786 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1787 (const_string "imul3")
1788 (match_operand:SI 2 "short_cint_operand" "")
1789 (const_string "imul2")]
1790 (const_string "imul")))])
1792 (define_insn "*mulsi3_mq_internal1"
1793 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1794 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1795 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1797 (clobber (match_scratch:SI 3 "=r,r"))
1798 (clobber (match_scratch:SI 4 "=q,q"))]
1801 {muls.|mullw.} %3,%1,%2
1803 [(set_attr "type" "imul_compare")
1804 (set_attr "length" "4,8")])
1807 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1808 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1809 (match_operand:SI 2 "gpc_reg_operand" ""))
1811 (clobber (match_scratch:SI 3 ""))
1812 (clobber (match_scratch:SI 4 ""))]
1813 "TARGET_POWER && reload_completed"
1814 [(parallel [(set (match_dup 3)
1815 (mult:SI (match_dup 1) (match_dup 2)))
1816 (clobber (match_dup 4))])
1818 (compare:CC (match_dup 3)
1822 (define_insn "*mulsi3_no_mq_internal1"
1823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1824 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1825 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1827 (clobber (match_scratch:SI 3 "=r,r"))]
1830 {muls.|mullw.} %3,%1,%2
1832 [(set_attr "type" "imul_compare")
1833 (set_attr "length" "4,8")])
1836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1837 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1838 (match_operand:SI 2 "gpc_reg_operand" ""))
1840 (clobber (match_scratch:SI 3 ""))]
1841 "! TARGET_POWER && reload_completed"
1843 (mult:SI (match_dup 1) (match_dup 2)))
1845 (compare:CC (match_dup 3)
1849 (define_insn "*mulsi3_mq_internal2"
1850 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1851 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1852 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1854 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1855 (mult:SI (match_dup 1) (match_dup 2)))
1856 (clobber (match_scratch:SI 4 "=q,q"))]
1859 {muls.|mullw.} %0,%1,%2
1861 [(set_attr "type" "imul_compare")
1862 (set_attr "length" "4,8")])
1865 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1866 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1867 (match_operand:SI 2 "gpc_reg_operand" ""))
1869 (set (match_operand:SI 0 "gpc_reg_operand" "")
1870 (mult:SI (match_dup 1) (match_dup 2)))
1871 (clobber (match_scratch:SI 4 ""))]
1872 "TARGET_POWER && reload_completed"
1873 [(parallel [(set (match_dup 0)
1874 (mult:SI (match_dup 1) (match_dup 2)))
1875 (clobber (match_dup 4))])
1877 (compare:CC (match_dup 0)
1881 (define_insn "*mulsi3_no_mq_internal2"
1882 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1883 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1884 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1886 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1887 (mult:SI (match_dup 1) (match_dup 2)))]
1890 {muls.|mullw.} %0,%1,%2
1892 [(set_attr "type" "imul_compare")
1893 (set_attr "length" "4,8")])
1896 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1897 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1898 (match_operand:SI 2 "gpc_reg_operand" ""))
1900 (set (match_operand:SI 0 "gpc_reg_operand" "")
1901 (mult:SI (match_dup 1) (match_dup 2)))]
1902 "! TARGET_POWER && reload_completed"
1904 (mult:SI (match_dup 1) (match_dup 2)))
1906 (compare:CC (match_dup 0)
1910 ;; Operand 1 is divided by operand 2; quotient goes to operand
1911 ;; 0 and remainder to operand 3.
1912 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1914 (define_expand "divmodsi4"
1915 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1916 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1917 (match_operand:SI 2 "gpc_reg_operand" "")))
1918 (set (match_operand:SI 3 "register_operand" "")
1919 (mod:SI (match_dup 1) (match_dup 2)))])]
1920 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1923 if (! TARGET_POWER && ! TARGET_POWERPC)
1925 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1926 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1927 emit_insn (gen_divss_call ());
1928 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1929 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1934 (define_insn "*divmodsi4_internal"
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1937 (match_operand:SI 2 "gpc_reg_operand" "r")))
1938 (set (match_operand:SI 3 "register_operand" "=q")
1939 (mod:SI (match_dup 1) (match_dup 2)))]
1942 [(set_attr "type" "idiv")])
1944 (define_expand "udivsi3"
1945 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1946 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1947 (match_operand:SI 2 "gpc_reg_operand" "")))]
1948 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1951 if (! TARGET_POWER && ! TARGET_POWERPC)
1953 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1954 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1955 emit_insn (gen_quous_call ());
1956 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1959 else if (TARGET_POWER)
1961 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1966 (define_insn "udivsi3_mq"
1967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1968 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1969 (match_operand:SI 2 "gpc_reg_operand" "r")))
1970 (clobber (match_scratch:SI 3 "=q"))]
1971 "TARGET_POWERPC && TARGET_POWER"
1973 [(set_attr "type" "idiv")])
1975 (define_insn "*udivsi3_no_mq"
1976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1977 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1978 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1979 "TARGET_POWERPC && ! TARGET_POWER"
1981 [(set_attr "type" "idiv")])
1983 ;; For powers of two we can do srai/aze for divide and then adjust for
1984 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1985 ;; used; for PowerPC, force operands into register and do a normal divide;
1986 ;; for AIX common-mode, use quoss call on register operands.
1987 (define_expand "divsi3"
1988 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1989 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1990 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1994 if (GET_CODE (operands[2]) == CONST_INT
1995 && INTVAL (operands[2]) > 0
1996 && exact_log2 (INTVAL (operands[2])) >= 0)
1998 else if (TARGET_POWERPC)
2000 operands[2] = force_reg (SImode, operands[2]);
2003 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2007 else if (TARGET_POWER)
2011 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2012 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2013 emit_insn (gen_quoss_call ());
2014 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2019 (define_insn "divsi3_mq"
2020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2021 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2022 (match_operand:SI 2 "gpc_reg_operand" "r")))
2023 (clobber (match_scratch:SI 3 "=q"))]
2024 "TARGET_POWERPC && TARGET_POWER"
2026 [(set_attr "type" "idiv")])
2028 (define_insn "*divsi3_no_mq"
2029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2030 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2031 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2032 "TARGET_POWERPC && ! TARGET_POWER"
2034 [(set_attr "type" "idiv")])
2036 (define_expand "modsi3"
2037 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2038 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2039 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2047 if (GET_CODE (operands[2]) != CONST_INT
2048 || INTVAL (operands[2]) <= 0
2049 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2052 temp1 = gen_reg_rtx (SImode);
2053 temp2 = gen_reg_rtx (SImode);
2055 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2056 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2057 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2063 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2064 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2066 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2067 [(set_attr "type" "two")
2068 (set_attr "length" "8")])
2071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2072 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2073 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2075 (clobber (match_scratch:SI 3 "=r,r"))]
2078 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2080 [(set_attr "type" "compare")
2081 (set_attr "length" "8,12")])
2084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2085 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2086 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2088 (clobber (match_scratch:SI 3 ""))]
2091 (div:SI (match_dup 1) (match_dup 2)))
2093 (compare:CC (match_dup 3)
2098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2099 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2100 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2102 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2103 (div:SI (match_dup 1) (match_dup 2)))]
2106 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2108 [(set_attr "type" "compare")
2109 (set_attr "length" "8,12")])
2112 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2113 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2114 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2116 (set (match_operand:SI 0 "gpc_reg_operand" "")
2117 (div:SI (match_dup 1) (match_dup 2)))]
2120 (div:SI (match_dup 1) (match_dup 2)))
2122 (compare:CC (match_dup 0)
2127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2130 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2132 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2133 (match_operand:SI 3 "gpc_reg_operand" "r")))
2134 (set (match_operand:SI 2 "register_operand" "=*q")
2137 (zero_extend:DI (match_dup 1)) (const_int 32))
2138 (zero_extend:DI (match_dup 4)))
2142 [(set_attr "type" "idiv")])
2144 ;; To do unsigned divide we handle the cases of the divisor looking like a
2145 ;; negative number. If it is a constant that is less than 2**31, we don't
2146 ;; have to worry about the branches. So make a few subroutines here.
2148 ;; First comes the normal case.
2149 (define_expand "udivmodsi4_normal"
2150 [(set (match_dup 4) (const_int 0))
2151 (parallel [(set (match_operand:SI 0 "" "")
2152 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2154 (zero_extend:DI (match_operand:SI 1 "" "")))
2155 (match_operand:SI 2 "" "")))
2156 (set (match_operand:SI 3 "" "")
2157 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2159 (zero_extend:DI (match_dup 1)))
2163 { operands[4] = gen_reg_rtx (SImode); }")
2165 ;; This handles the branches.
2166 (define_expand "udivmodsi4_tests"
2167 [(set (match_operand:SI 0 "" "") (const_int 0))
2168 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2169 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2170 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2171 (label_ref (match_operand:SI 4 "" "")) (pc)))
2172 (set (match_dup 0) (const_int 1))
2173 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2174 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2175 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2176 (label_ref (match_dup 4)) (pc)))]
2179 { operands[5] = gen_reg_rtx (CCUNSmode);
2180 operands[6] = gen_reg_rtx (CCmode);
2183 (define_expand "udivmodsi4"
2184 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2185 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2186 (match_operand:SI 2 "reg_or_cint_operand" "")))
2187 (set (match_operand:SI 3 "gpc_reg_operand" "")
2188 (umod:SI (match_dup 1) (match_dup 2)))])]
2196 if (! TARGET_POWERPC)
2198 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2199 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2200 emit_insn (gen_divus_call ());
2201 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2202 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2209 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2211 operands[2] = force_reg (SImode, operands[2]);
2212 label = gen_label_rtx ();
2213 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2214 operands[3], label));
2217 operands[2] = force_reg (SImode, operands[2]);
2219 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2227 ;; AIX architecture-independent common-mode multiply (DImode),
2228 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2229 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2230 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2231 ;; assumed unused if generating common-mode, so ignore.
2232 (define_insn "mulh_call"
2235 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2236 (sign_extend:DI (reg:SI 4)))
2238 (clobber (match_scratch:SI 0 "=l"))]
2239 "! TARGET_POWER && ! TARGET_POWERPC"
2241 [(set_attr "type" "imul")])
2243 (define_insn "mull_call"
2245 (mult:DI (sign_extend:DI (reg:SI 3))
2246 (sign_extend:DI (reg:SI 4))))
2247 (clobber (match_scratch:SI 0 "=l"))
2248 (clobber (reg:SI 0))]
2249 "! TARGET_POWER && ! TARGET_POWERPC"
2251 [(set_attr "type" "imul")])
2253 (define_insn "divss_call"
2255 (div:SI (reg:SI 3) (reg:SI 4)))
2257 (mod:SI (reg:SI 3) (reg:SI 4)))
2258 (clobber (match_scratch:SI 0 "=l"))
2259 (clobber (reg:SI 0))]
2260 "! TARGET_POWER && ! TARGET_POWERPC"
2262 [(set_attr "type" "idiv")])
2264 (define_insn "divus_call"
2266 (udiv:SI (reg:SI 3) (reg:SI 4)))
2268 (umod:SI (reg:SI 3) (reg:SI 4)))
2269 (clobber (match_scratch:SI 0 "=l"))
2270 (clobber (reg:SI 0))
2271 (clobber (match_scratch:CC 1 "=x"))
2272 (clobber (reg:CC 69))]
2273 "! TARGET_POWER && ! TARGET_POWERPC"
2275 [(set_attr "type" "idiv")])
2277 (define_insn "quoss_call"
2279 (div:SI (reg:SI 3) (reg:SI 4)))
2280 (clobber (match_scratch:SI 0 "=l"))]
2281 "! TARGET_POWER && ! TARGET_POWERPC"
2283 [(set_attr "type" "idiv")])
2285 (define_insn "quous_call"
2287 (udiv:SI (reg:SI 3) (reg:SI 4)))
2288 (clobber (match_scratch:SI 0 "=l"))
2289 (clobber (reg:SI 0))
2290 (clobber (match_scratch:CC 1 "=x"))
2291 (clobber (reg:CC 69))]
2292 "! TARGET_POWER && ! TARGET_POWERPC"
2294 [(set_attr "type" "idiv")])
2296 ;; Logical instructions
2297 ;; The logical instructions are mostly combined by using match_operator,
2298 ;; but the plain AND insns are somewhat different because there is no
2299 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2300 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2302 (define_insn "andsi3"
2303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2304 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2305 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2306 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2310 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2311 {andil.|andi.} %0,%1,%b2
2312 {andiu.|andis.} %0,%1,%u2"
2313 [(set_attr "type" "*,*,compare,compare")])
2315 ;; Note to set cr's other than cr0 we do the and immediate and then
2316 ;; the test again -- this avoids a mfcr which on the higher end
2317 ;; machines causes an execution serialization
2319 (define_insn "*andsi3_internal2"
2320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2321 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2322 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2324 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2325 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2329 {andil.|andi.} %3,%1,%b2
2330 {andiu.|andis.} %3,%1,%u2
2331 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2336 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2337 (set_attr "length" "4,4,4,4,8,8,8,8")])
2339 (define_insn "*andsi3_internal3"
2340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2341 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2342 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2344 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2345 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2349 {andil.|andi.} %3,%1,%b2
2350 {andiu.|andis.} %3,%1,%u2
2351 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2356 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2357 (set_attr "length" "8,4,4,4,8,8,8,8")])
2360 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2361 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2362 (match_operand:SI 2 "and_operand" ""))
2364 (clobber (match_scratch:SI 3 ""))
2365 (clobber (match_scratch:CC 4 ""))]
2367 [(parallel [(set (match_dup 3)
2368 (and:SI (match_dup 1)
2370 (clobber (match_dup 4))])
2372 (compare:CC (match_dup 3)
2376 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2377 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2380 [(set (match_operand:CC 0 "cc_reg_operand" "")
2381 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2382 (match_operand:SI 2 "gpc_reg_operand" ""))
2384 (clobber (match_scratch:SI 3 ""))
2385 (clobber (match_scratch:CC 4 ""))]
2386 "TARGET_POWERPC64 && reload_completed"
2387 [(parallel [(set (match_dup 3)
2388 (and:SI (match_dup 1)
2390 (clobber (match_dup 4))])
2392 (compare:CC (match_dup 3)
2396 (define_insn "*andsi3_internal4"
2397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2398 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2399 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2402 (and:SI (match_dup 1)
2404 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2408 {andil.|andi.} %0,%1,%b2
2409 {andiu.|andis.} %0,%1,%u2
2410 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2415 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2416 (set_attr "length" "4,4,4,4,8,8,8,8")])
2418 (define_insn "*andsi3_internal5"
2419 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2420 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2421 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2424 (and:SI (match_dup 1)
2426 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2430 {andil.|andi.} %0,%1,%b2
2431 {andiu.|andis.} %0,%1,%u2
2432 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2437 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2438 (set_attr "length" "8,4,4,4,8,8,8,8")])
2441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2442 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2443 (match_operand:SI 2 "and_operand" ""))
2445 (set (match_operand:SI 0 "gpc_reg_operand" "")
2446 (and:SI (match_dup 1)
2448 (clobber (match_scratch:CC 4 ""))]
2450 [(parallel [(set (match_dup 0)
2451 (and:SI (match_dup 1)
2453 (clobber (match_dup 4))])
2455 (compare:CC (match_dup 0)
2460 [(set (match_operand:CC 3 "cc_reg_operand" "")
2461 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2462 (match_operand:SI 2 "gpc_reg_operand" ""))
2464 (set (match_operand:SI 0 "gpc_reg_operand" "")
2465 (and:SI (match_dup 1)
2467 (clobber (match_scratch:CC 4 ""))]
2468 "TARGET_POWERPC64 && reload_completed"
2469 [(parallel [(set (match_dup 0)
2470 (and:SI (match_dup 1)
2472 (clobber (match_dup 4))])
2474 (compare:CC (match_dup 0)
2478 ;; Handle the PowerPC64 rlwinm corner case
2480 (define_insn_and_split "*andsi3_internal6"
2481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2482 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2483 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2488 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2491 (rotate:SI (match_dup 0) (match_dup 5)))]
2494 int mb = extract_MB (operands[2]);
2495 int me = extract_ME (operands[2]);
2496 operands[3] = GEN_INT (me + 1);
2497 operands[5] = GEN_INT (32 - (me + 1));
2498 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2500 [(set_attr "length" "8")])
2502 (define_expand "iorsi3"
2503 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2504 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2505 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2509 if (GET_CODE (operands[2]) == CONST_INT
2510 && ! logical_operand (operands[2], SImode))
2512 HOST_WIDE_INT value = INTVAL (operands[2]);
2513 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2514 ? operands[0] : gen_reg_rtx (SImode));
2516 emit_insn (gen_iorsi3 (tmp, operands[1],
2517 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2518 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2523 (define_expand "xorsi3"
2524 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2525 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2526 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2530 if (GET_CODE (operands[2]) == CONST_INT
2531 && ! logical_operand (operands[2], SImode))
2533 HOST_WIDE_INT value = INTVAL (operands[2]);
2534 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2535 ? operands[0] : gen_reg_rtx (SImode));
2537 emit_insn (gen_xorsi3 (tmp, operands[1],
2538 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2539 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2544 (define_insn "*boolsi3_internal1"
2545 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2546 (match_operator:SI 3 "boolean_or_operator"
2547 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2548 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2552 {%q3il|%q3i} %0,%1,%b2
2553 {%q3iu|%q3is} %0,%1,%u2")
2555 (define_insn "*boolsi3_internal2"
2556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2557 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2558 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2559 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2561 (clobber (match_scratch:SI 3 "=r,r"))]
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(match_operand:SI 1 "gpc_reg_operand" "")
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2575 (clobber (match_scratch:SI 3 ""))]
2576 "TARGET_32BIT && reload_completed"
2577 [(set (match_dup 3) (match_dup 4))
2579 (compare:CC (match_dup 3)
2583 (define_insn "*boolsi3_internal3"
2584 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2585 (compare:CC (match_operator:SI 4 "boolean_operator"
2586 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2587 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2595 [(set_attr "type" "compare")
2596 (set_attr "length" "4,8")])
2599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2600 (compare:CC (match_operator:SI 4 "boolean_operator"
2601 [(match_operand:SI 1 "gpc_reg_operand" "")
2602 (match_operand:SI 2 "gpc_reg_operand" "")])
2604 (set (match_operand:SI 0 "gpc_reg_operand" "")
2606 "TARGET_32BIT && reload_completed"
2607 [(set (match_dup 0) (match_dup 4))
2609 (compare:CC (match_dup 0)
2613 ;; Split a logical operation that we can't do in one insn into two insns,
2614 ;; each of which does one 16-bit part. This is used by combine.
2617 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2618 (match_operator:SI 3 "boolean_or_operator"
2619 [(match_operand:SI 1 "gpc_reg_operand" "")
2620 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2622 [(set (match_dup 0) (match_dup 4))
2623 (set (match_dup 0) (match_dup 5))]
2627 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2628 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2630 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2631 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2635 (define_insn "*boolcsi3_internal1"
2636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2637 (match_operator:SI 3 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2639 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2643 (define_insn "*boolcsi3_internal2"
2644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2645 (compare:CC (match_operator:SI 4 "boolean_operator"
2646 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2647 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2649 (clobber (match_scratch:SI 3 "=r,r"))]
2654 [(set_attr "type" "compare")
2655 (set_attr "length" "4,8")])
2658 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2659 (compare:CC (match_operator:SI 4 "boolean_operator"
2660 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2661 (match_operand:SI 2 "gpc_reg_operand" "")])
2663 (clobber (match_scratch:SI 3 ""))]
2664 "TARGET_32BIT && reload_completed"
2665 [(set (match_dup 3) (match_dup 4))
2667 (compare:CC (match_dup 3)
2671 (define_insn "*boolcsi3_internal3"
2672 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2673 (compare:CC (match_operator:SI 4 "boolean_operator"
2674 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2675 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2677 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2683 [(set_attr "type" "compare")
2684 (set_attr "length" "4,8")])
2687 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2688 (compare:CC (match_operator:SI 4 "boolean_operator"
2689 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2690 (match_operand:SI 2 "gpc_reg_operand" "")])
2692 (set (match_operand:SI 0 "gpc_reg_operand" "")
2694 "TARGET_32BIT && reload_completed"
2695 [(set (match_dup 0) (match_dup 4))
2697 (compare:CC (match_dup 0)
2701 (define_insn "*boolccsi3_internal1"
2702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2703 (match_operator:SI 3 "boolean_operator"
2704 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2705 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2709 (define_insn "*boolccsi3_internal2"
2710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2711 (compare:CC (match_operator:SI 4 "boolean_operator"
2712 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2713 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2715 (clobber (match_scratch:SI 3 "=r,r"))]
2720 [(set_attr "type" "compare")
2721 (set_attr "length" "4,8")])
2724 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2725 (compare:CC (match_operator:SI 4 "boolean_operator"
2726 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2727 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2729 (clobber (match_scratch:SI 3 ""))]
2730 "TARGET_32BIT && reload_completed"
2731 [(set (match_dup 3) (match_dup 4))
2733 (compare:CC (match_dup 3)
2737 (define_insn "*boolccsi3_internal3"
2738 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2739 (compare:CC (match_operator:SI 4 "boolean_operator"
2740 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2741 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2749 [(set_attr "type" "compare")
2750 (set_attr "length" "4,8")])
2753 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2754 (compare:CC (match_operator:SI 4 "boolean_operator"
2755 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2756 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2758 (set (match_operand:SI 0 "gpc_reg_operand" "")
2760 "TARGET_32BIT && reload_completed"
2761 [(set (match_dup 0) (match_dup 4))
2763 (compare:CC (match_dup 0)
2767 ;; maskir insn. We need four forms because things might be in arbitrary
2768 ;; orders. Don't define forms that only set CR fields because these
2769 ;; would modify an input register.
2771 (define_insn "*maskir_internal1"
2772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2773 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2774 (match_operand:SI 1 "gpc_reg_operand" "0"))
2775 (and:SI (match_dup 2)
2776 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2780 (define_insn "*maskir_internal2"
2781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2782 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2783 (match_operand:SI 1 "gpc_reg_operand" "0"))
2784 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2789 (define_insn "*maskir_internal3"
2790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2791 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2792 (match_operand:SI 3 "gpc_reg_operand" "r"))
2793 (and:SI (not:SI (match_dup 2))
2794 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2798 (define_insn "*maskir_internal4"
2799 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2800 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2801 (match_operand:SI 2 "gpc_reg_operand" "r"))
2802 (and:SI (not:SI (match_dup 2))
2803 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2807 (define_insn "*maskir_internal5"
2808 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2810 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2811 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2812 (and:SI (match_dup 2)
2813 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2815 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2816 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2817 (and:SI (match_dup 2) (match_dup 3))))]
2822 [(set_attr "type" "compare")
2823 (set_attr "length" "4,8")])
2826 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2828 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2829 (match_operand:SI 1 "gpc_reg_operand" ""))
2830 (and:SI (match_dup 2)
2831 (match_operand:SI 3 "gpc_reg_operand" "")))
2833 (set (match_operand:SI 0 "gpc_reg_operand" "")
2834 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2835 (and:SI (match_dup 2) (match_dup 3))))]
2836 "TARGET_POWER && reload_completed"
2838 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2839 (and:SI (match_dup 2) (match_dup 3))))
2841 (compare:CC (match_dup 0)
2845 (define_insn "*maskir_internal6"
2846 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2848 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2849 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2850 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2853 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2854 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2855 (and:SI (match_dup 3) (match_dup 2))))]
2860 [(set_attr "type" "compare")
2861 (set_attr "length" "4,8")])
2864 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2866 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2867 (match_operand:SI 1 "gpc_reg_operand" ""))
2868 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2871 (set (match_operand:SI 0 "gpc_reg_operand" "")
2872 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2873 (and:SI (match_dup 3) (match_dup 2))))]
2874 "TARGET_POWER && reload_completed"
2876 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2877 (and:SI (match_dup 3) (match_dup 2))))
2879 (compare:CC (match_dup 0)
2883 (define_insn "*maskir_internal7"
2884 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2886 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2887 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2888 (and:SI (not:SI (match_dup 2))
2889 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2891 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2892 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2893 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2898 [(set_attr "type" "compare")
2899 (set_attr "length" "4,8")])
2902 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2904 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2905 (match_operand:SI 3 "gpc_reg_operand" ""))
2906 (and:SI (not:SI (match_dup 2))
2907 (match_operand:SI 1 "gpc_reg_operand" "")))
2909 (set (match_operand:SI 0 "gpc_reg_operand" "")
2910 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2911 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2912 "TARGET_POWER && reload_completed"
2914 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2915 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2917 (compare:CC (match_dup 0)
2921 (define_insn "*maskir_internal8"
2922 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2924 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2925 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2926 (and:SI (not:SI (match_dup 2))
2927 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2929 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2930 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2931 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2936 [(set_attr "type" "compare")
2937 (set_attr "length" "4,8")])
2940 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2942 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "gpc_reg_operand" ""))
2944 (and:SI (not:SI (match_dup 2))
2945 (match_operand:SI 1 "gpc_reg_operand" "")))
2947 (set (match_operand:SI 0 "gpc_reg_operand" "")
2948 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2949 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2950 "TARGET_POWER && reload_completed"
2952 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2953 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2955 (compare:CC (match_dup 0)
2959 ;; Rotate and shift insns, in all their variants. These support shifts,
2960 ;; field inserts and extracts, and various combinations thereof.
2961 (define_expand "insv"
2962 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2963 (match_operand:SI 1 "const_int_operand" "")
2964 (match_operand:SI 2 "const_int_operand" ""))
2965 (match_operand 3 "gpc_reg_operand" ""))]
2969 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2970 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2971 compiler if the address of the structure is taken later. */
2972 if (GET_CODE (operands[0]) == SUBREG
2973 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2976 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2977 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2979 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2983 (define_insn "insvsi"
2984 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2985 (match_operand:SI 1 "const_int_operand" "i")
2986 (match_operand:SI 2 "const_int_operand" "i"))
2987 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2991 int start = INTVAL (operands[2]) & 31;
2992 int size = INTVAL (operands[1]) & 31;
2994 operands[4] = GEN_INT (32 - start - size);
2995 operands[1] = GEN_INT (start + size - 1);
2996 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2998 [(set_attr "type" "insert_word")])
3000 (define_insn "*insvsi_internal1"
3001 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3002 (match_operand:SI 1 "const_int_operand" "i")
3003 (match_operand:SI 2 "const_int_operand" "i"))
3004 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3005 (match_operand:SI 4 "const_int_operand" "i")))]
3006 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3009 int shift = INTVAL (operands[4]) & 31;
3010 int start = INTVAL (operands[2]) & 31;
3011 int size = INTVAL (operands[1]) & 31;
3013 operands[4] = GEN_INT (shift - start - size);
3014 operands[1] = GEN_INT (start + size - 1);
3015 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3017 [(set_attr "type" "insert_word")])
3019 (define_insn "*insvsi_internal2"
3020 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3021 (match_operand:SI 1 "const_int_operand" "i")
3022 (match_operand:SI 2 "const_int_operand" "i"))
3023 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3024 (match_operand:SI 4 "const_int_operand" "i")))]
3025 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3028 int shift = INTVAL (operands[4]) & 31;
3029 int start = INTVAL (operands[2]) & 31;
3030 int size = INTVAL (operands[1]) & 31;
3032 operands[4] = GEN_INT (32 - shift - start - size);
3033 operands[1] = GEN_INT (start + size - 1);
3034 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3036 [(set_attr "type" "insert_word")])
3038 (define_insn "*insvsi_internal3"
3039 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3040 (match_operand:SI 1 "const_int_operand" "i")
3041 (match_operand:SI 2 "const_int_operand" "i"))
3042 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3043 (match_operand:SI 4 "const_int_operand" "i")))]
3044 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3047 int shift = INTVAL (operands[4]) & 31;
3048 int start = INTVAL (operands[2]) & 31;
3049 int size = INTVAL (operands[1]) & 31;
3051 operands[4] = GEN_INT (32 - shift - start - size);
3052 operands[1] = GEN_INT (start + size - 1);
3053 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3055 [(set_attr "type" "insert_word")])
3057 (define_insn "*insvsi_internal4"
3058 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3059 (match_operand:SI 1 "const_int_operand" "i")
3060 (match_operand:SI 2 "const_int_operand" "i"))
3061 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3062 (match_operand:SI 4 "const_int_operand" "i")
3063 (match_operand:SI 5 "const_int_operand" "i")))]
3064 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3067 int extract_start = INTVAL (operands[5]) & 31;
3068 int extract_size = INTVAL (operands[4]) & 31;
3069 int insert_start = INTVAL (operands[2]) & 31;
3070 int insert_size = INTVAL (operands[1]) & 31;
3072 /* Align extract field with insert field */
3073 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3074 operands[1] = GEN_INT (insert_start + insert_size - 1);
3075 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3077 [(set_attr "type" "insert_word")])
3079 ;; combine patterns for rlwimi
3080 (define_insn "*insvsi_internal5"
3081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3082 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3083 (match_operand:SI 1 "mask_operand" "i"))
3084 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3085 (match_operand:SI 2 "const_int_operand" "i"))
3086 (match_operand:SI 5 "mask_operand" "i"))))]
3087 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3090 int me = extract_ME(operands[5]);
3091 int mb = extract_MB(operands[5]);
3092 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3093 operands[2] = GEN_INT(mb);
3094 operands[1] = GEN_INT(me);
3095 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3097 [(set_attr "type" "insert_word")])
3099 (define_insn "*insvsi_internal6"
3100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3101 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3102 (match_operand:SI 2 "const_int_operand" "i"))
3103 (match_operand:SI 5 "mask_operand" "i"))
3104 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3105 (match_operand:SI 1 "mask_operand" "i"))))]
3106 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3109 int me = extract_ME(operands[5]);
3110 int mb = extract_MB(operands[5]);
3111 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3112 operands[2] = GEN_INT(mb);
3113 operands[1] = GEN_INT(me);
3114 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3116 [(set_attr "type" "insert_word")])
3118 (define_insn "insvdi"
3119 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3120 (match_operand:SI 1 "const_int_operand" "i")
3121 (match_operand:SI 2 "const_int_operand" "i"))
3122 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3126 int start = INTVAL (operands[2]) & 63;
3127 int size = INTVAL (operands[1]) & 63;
3129 operands[1] = GEN_INT (64 - start - size);
3130 return \"rldimi %0,%3,%H1,%H2\";
3133 (define_insn "*insvdi_internal2"
3134 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3135 (match_operand:SI 1 "const_int_operand" "i")
3136 (match_operand:SI 2 "const_int_operand" "i"))
3137 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3138 (match_operand:SI 4 "const_int_operand" "i")))]
3140 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3143 int shift = INTVAL (operands[4]) & 63;
3144 int start = (INTVAL (operands[2]) & 63) - 32;
3145 int size = INTVAL (operands[1]) & 63;
3147 operands[4] = GEN_INT (64 - shift - start - size);
3148 operands[2] = GEN_INT (start);
3149 operands[1] = GEN_INT (start + size - 1);
3150 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3153 (define_insn "*insvdi_internal3"
3154 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3155 (match_operand:SI 1 "const_int_operand" "i")
3156 (match_operand:SI 2 "const_int_operand" "i"))
3157 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3158 (match_operand:SI 4 "const_int_operand" "i")))]
3160 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3163 int shift = INTVAL (operands[4]) & 63;
3164 int start = (INTVAL (operands[2]) & 63) - 32;
3165 int size = INTVAL (operands[1]) & 63;
3167 operands[4] = GEN_INT (64 - shift - start - size);
3168 operands[2] = GEN_INT (start);
3169 operands[1] = GEN_INT (start + size - 1);
3170 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3173 (define_expand "extzv"
3174 [(set (match_operand 0 "gpc_reg_operand" "")
3175 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3176 (match_operand:SI 2 "const_int_operand" "")
3177 (match_operand:SI 3 "const_int_operand" "")))]
3181 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3182 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3183 compiler if the address of the structure is taken later. */
3184 if (GET_CODE (operands[0]) == SUBREG
3185 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3188 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3189 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3191 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3195 (define_insn "extzvsi"
3196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3197 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3198 (match_operand:SI 2 "const_int_operand" "i")
3199 (match_operand:SI 3 "const_int_operand" "i")))]
3203 int start = INTVAL (operands[3]) & 31;
3204 int size = INTVAL (operands[2]) & 31;
3206 if (start + size >= 32)
3207 operands[3] = const0_rtx;
3209 operands[3] = GEN_INT (start + size);
3210 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3213 (define_insn "*extzvsi_internal1"
3214 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3215 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3216 (match_operand:SI 2 "const_int_operand" "i,i")
3217 (match_operand:SI 3 "const_int_operand" "i,i"))
3219 (clobber (match_scratch:SI 4 "=r,r"))]
3223 int start = INTVAL (operands[3]) & 31;
3224 int size = INTVAL (operands[2]) & 31;
3226 /* Force split for non-cc0 compare. */
3227 if (which_alternative == 1)
3230 /* If the bit-field being tested fits in the upper or lower half of a
3231 word, it is possible to use andiu. or andil. to test it. This is
3232 useful because the condition register set-use delay is smaller for
3233 andi[ul]. than for rlinm. This doesn't work when the starting bit
3234 position is 0 because the LT and GT bits may be set wrong. */
3236 if ((start > 0 && start + size <= 16) || start >= 16)
3238 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3239 - (1 << (16 - (start & 15) - size))));
3241 return \"{andiu.|andis.} %4,%1,%3\";
3243 return \"{andil.|andi.} %4,%1,%3\";
3246 if (start + size >= 32)
3247 operands[3] = const0_rtx;
3249 operands[3] = GEN_INT (start + size);
3250 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3252 [(set_attr "type" "compare")
3253 (set_attr "length" "4,8")])
3256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3257 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3258 (match_operand:SI 2 "const_int_operand" "")
3259 (match_operand:SI 3 "const_int_operand" ""))
3261 (clobber (match_scratch:SI 4 ""))]
3264 (zero_extract:SI (match_dup 1) (match_dup 2)
3267 (compare:CC (match_dup 4)
3271 (define_insn "*extzvsi_internal2"
3272 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3273 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3274 (match_operand:SI 2 "const_int_operand" "i,i")
3275 (match_operand:SI 3 "const_int_operand" "i,i"))
3277 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3278 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3282 int start = INTVAL (operands[3]) & 31;
3283 int size = INTVAL (operands[2]) & 31;
3285 /* Force split for non-cc0 compare. */
3286 if (which_alternative == 1)
3289 /* Since we are using the output value, we can't ignore any need for
3290 a shift. The bit-field must end at the LSB. */
3291 if (start >= 16 && start + size == 32)
3293 operands[3] = GEN_INT ((1 << size) - 1);
3294 return \"{andil.|andi.} %0,%1,%3\";
3297 if (start + size >= 32)
3298 operands[3] = const0_rtx;
3300 operands[3] = GEN_INT (start + size);
3301 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3303 [(set_attr "type" "compare")
3304 (set_attr "length" "4,8")])
3307 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3308 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3309 (match_operand:SI 2 "const_int_operand" "")
3310 (match_operand:SI 3 "const_int_operand" ""))
3312 (set (match_operand:SI 0 "gpc_reg_operand" "")
3313 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3316 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3318 (compare:CC (match_dup 0)
3322 (define_insn "extzvdi"
3323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3324 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3325 (match_operand:SI 2 "const_int_operand" "i")
3326 (match_operand:SI 3 "const_int_operand" "i")))]
3330 int start = INTVAL (operands[3]) & 63;
3331 int size = INTVAL (operands[2]) & 63;
3333 if (start + size >= 64)
3334 operands[3] = const0_rtx;
3336 operands[3] = GEN_INT (start + size);
3337 operands[2] = GEN_INT (64 - size);
3338 return \"rldicl %0,%1,%3,%2\";
3341 (define_insn "*extzvdi_internal1"
3342 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3343 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3344 (match_operand:SI 2 "const_int_operand" "i")
3345 (match_operand:SI 3 "const_int_operand" "i"))
3347 (clobber (match_scratch:DI 4 "=r"))]
3351 int start = INTVAL (operands[3]) & 63;
3352 int size = INTVAL (operands[2]) & 63;
3354 if (start + size >= 64)
3355 operands[3] = const0_rtx;
3357 operands[3] = GEN_INT (start + size);
3358 operands[2] = GEN_INT (64 - size);
3359 return \"rldicl. %4,%1,%3,%2\";
3361 [(set_attr "type" "compare")])
3363 (define_insn "*extzvdi_internal2"
3364 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3365 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3366 (match_operand:SI 2 "const_int_operand" "i")
3367 (match_operand:SI 3 "const_int_operand" "i"))
3369 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3370 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3374 int start = INTVAL (operands[3]) & 63;
3375 int size = INTVAL (operands[2]) & 63;
3377 if (start + size >= 64)
3378 operands[3] = const0_rtx;
3380 operands[3] = GEN_INT (start + size);
3381 operands[2] = GEN_INT (64 - size);
3382 return \"rldicl. %0,%1,%3,%2\";
3384 [(set_attr "type" "compare")])
3386 (define_insn "rotlsi3"
3387 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3388 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3389 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3391 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3393 (define_insn "*rotlsi3_internal2"
3394 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3395 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3396 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3398 (clobber (match_scratch:SI 3 "=r,r"))]
3401 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3403 [(set_attr "type" "delayed_compare")
3404 (set_attr "length" "4,8")])
3407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3408 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3409 (match_operand:SI 2 "reg_or_cint_operand" ""))
3411 (clobber (match_scratch:SI 3 ""))]
3414 (rotate:SI (match_dup 1) (match_dup 2)))
3416 (compare:CC (match_dup 3)
3420 (define_insn "*rotlsi3_internal3"
3421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3422 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3423 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3426 (rotate:SI (match_dup 1) (match_dup 2)))]
3429 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3431 [(set_attr "type" "delayed_compare")
3432 (set_attr "length" "4,8")])
3435 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3436 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3437 (match_operand:SI 2 "reg_or_cint_operand" ""))
3439 (set (match_operand:SI 0 "gpc_reg_operand" "")
3440 (rotate:SI (match_dup 1) (match_dup 2)))]
3443 (rotate:SI (match_dup 1) (match_dup 2)))
3445 (compare:CC (match_dup 0)
3449 (define_insn "*rotlsi3_internal4"
3450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3451 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3452 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3453 (match_operand:SI 3 "mask_operand" "n")))]
3455 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3457 (define_insn "*rotlsi3_internal5"
3458 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3460 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3461 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3462 (match_operand:SI 3 "mask_operand" "n,n"))
3464 (clobber (match_scratch:SI 4 "=r,r"))]
3467 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3469 [(set_attr "type" "delayed_compare")
3470 (set_attr "length" "4,8")])
3473 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3475 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3476 (match_operand:SI 2 "reg_or_cint_operand" ""))
3477 (match_operand:SI 3 "mask_operand" ""))
3479 (clobber (match_scratch:SI 4 ""))]
3482 (and:SI (rotate:SI (match_dup 1)
3486 (compare:CC (match_dup 4)
3490 (define_insn "*rotlsi3_internal6"
3491 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3493 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3494 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3495 (match_operand:SI 3 "mask_operand" "n,n"))
3497 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3498 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3501 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3503 [(set_attr "type" "delayed_compare")
3504 (set_attr "length" "4,8")])
3507 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" ""))
3511 (match_operand:SI 3 "mask_operand" ""))
3513 (set (match_operand:SI 0 "gpc_reg_operand" "")
3514 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3517 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3519 (compare:CC (match_dup 0)
3523 (define_insn "*rotlsi3_internal7"
3524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3530 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3532 (define_insn "*rotlsi3_internal8"
3533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3534 (compare:CC (zero_extend:SI
3536 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3537 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3539 (clobber (match_scratch:SI 3 "=r,r"))]
3542 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3544 [(set_attr "type" "delayed_compare")
3545 (set_attr "length" "4,8")])
3548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3549 (compare:CC (zero_extend:SI
3551 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3552 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3554 (clobber (match_scratch:SI 3 ""))]
3557 (zero_extend:SI (subreg:QI
3558 (rotate:SI (match_dup 1)
3561 (compare:CC (match_dup 3)
3565 (define_insn "*rotlsi3_internal9"
3566 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3567 (compare:CC (zero_extend:SI
3569 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3570 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3573 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3576 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3578 [(set_attr "type" "delayed_compare")
3579 (set_attr "length" "4,8")])
3582 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3583 (compare:CC (zero_extend:SI
3585 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3586 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3588 (set (match_operand:SI 0 "gpc_reg_operand" "")
3589 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3592 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3594 (compare:CC (match_dup 0)
3598 (define_insn "*rotlsi3_internal10"
3599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3602 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3603 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3605 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3607 (define_insn "*rotlsi3_internal11"
3608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3609 (compare:CC (zero_extend:SI
3611 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3612 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3614 (clobber (match_scratch:SI 3 "=r,r"))]
3617 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3619 [(set_attr "type" "delayed_compare")
3620 (set_attr "length" "4,8")])
3623 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3624 (compare:CC (zero_extend:SI
3626 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3627 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3629 (clobber (match_scratch:SI 3 ""))]
3632 (zero_extend:SI (subreg:HI
3633 (rotate:SI (match_dup 1)
3636 (compare:CC (match_dup 3)
3640 (define_insn "*rotlsi3_internal12"
3641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3642 (compare:CC (zero_extend:SI
3644 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3647 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3648 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3651 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3653 [(set_attr "type" "delayed_compare")
3654 (set_attr "length" "4,8")])
3657 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3658 (compare:CC (zero_extend:SI
3660 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3661 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3663 (set (match_operand:SI 0 "gpc_reg_operand" "")
3664 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3667 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3669 (compare:CC (match_dup 0)
3673 ;; Note that we use "sle." instead of "sl." so that we can set
3674 ;; SHIFT_COUNT_TRUNCATED.
3676 (define_expand "ashlsi3"
3677 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3678 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3679 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3684 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3686 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3690 (define_insn "ashlsi3_power"
3691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3692 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3693 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3694 (clobber (match_scratch:SI 3 "=q,X"))]
3698 {sli|slwi} %0,%1,%h2")
3700 (define_insn "ashlsi3_no_power"
3701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3702 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3703 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3705 "{sl|slw}%I2 %0,%1,%h2")
3708 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3709 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3710 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3712 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3713 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3717 {sli.|slwi.} %3,%1,%h2
3720 [(set_attr "type" "delayed_compare")
3721 (set_attr "length" "4,4,8,8")])
3724 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3725 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3726 (match_operand:SI 2 "reg_or_cint_operand" ""))
3728 (clobber (match_scratch:SI 3 ""))
3729 (clobber (match_scratch:SI 4 ""))]
3730 "TARGET_POWER && reload_completed"
3731 [(parallel [(set (match_dup 3)
3732 (ashift:SI (match_dup 1) (match_dup 2)))
3733 (clobber (match_dup 4))])
3735 (compare:CC (match_dup 3)
3740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3741 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3742 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3744 (clobber (match_scratch:SI 3 "=r,r"))]
3745 "! TARGET_POWER && TARGET_32BIT"
3747 {sl|slw}%I2. %3,%1,%h2
3749 [(set_attr "type" "delayed_compare")
3750 (set_attr "length" "4,8")])
3753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3754 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3755 (match_operand:SI 2 "reg_or_cint_operand" ""))
3757 (clobber (match_scratch:SI 3 ""))]
3758 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3760 (ashift:SI (match_dup 1) (match_dup 2)))
3762 (compare:CC (match_dup 3)
3767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3768 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3769 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3771 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3772 (ashift:SI (match_dup 1) (match_dup 2)))
3773 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3777 {sli.|slwi.} %0,%1,%h2
3780 [(set_attr "type" "delayed_compare")
3781 (set_attr "length" "4,4,8,8")])
3784 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3785 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3786 (match_operand:SI 2 "reg_or_cint_operand" ""))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "")
3789 (ashift:SI (match_dup 1) (match_dup 2)))
3790 (clobber (match_scratch:SI 4 ""))]
3791 "TARGET_POWER && reload_completed"
3792 [(parallel [(set (match_dup 0)
3793 (ashift:SI (match_dup 1) (match_dup 2)))
3794 (clobber (match_dup 4))])
3796 (compare:CC (match_dup 0)
3801 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3802 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3803 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3805 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3806 (ashift:SI (match_dup 1) (match_dup 2)))]
3807 "! TARGET_POWER && TARGET_32BIT"
3809 {sl|slw}%I2. %0,%1,%h2
3811 [(set_attr "type" "delayed_compare")
3812 (set_attr "length" "4,8")])
3815 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3816 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3817 (match_operand:SI 2 "reg_or_cint_operand" ""))
3819 (set (match_operand:SI 0 "gpc_reg_operand" "")
3820 (ashift:SI (match_dup 1) (match_dup 2)))]
3821 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3823 (ashift:SI (match_dup 1) (match_dup 2)))
3825 (compare:CC (match_dup 0)
3829 (define_insn "rlwinm"
3830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3831 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3832 (match_operand:SI 2 "const_int_operand" "i"))
3833 (match_operand:SI 3 "mask_operand" "n")))]
3834 "includes_lshift_p (operands[2], operands[3])"
3835 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3840 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3841 (match_operand:SI 2 "const_int_operand" "i,i"))
3842 (match_operand:SI 3 "mask_operand" "n,n"))
3844 (clobber (match_scratch:SI 4 "=r,r"))]
3845 "includes_lshift_p (operands[2], operands[3])"
3847 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3849 [(set_attr "type" "delayed_compare")
3850 (set_attr "length" "4,8")])
3853 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3855 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3856 (match_operand:SI 2 "const_int_operand" ""))
3857 (match_operand:SI 3 "mask_operand" ""))
3859 (clobber (match_scratch:SI 4 ""))]
3860 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3862 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3865 (compare:CC (match_dup 4)
3870 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3872 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3873 (match_operand:SI 2 "const_int_operand" "i,i"))
3874 (match_operand:SI 3 "mask_operand" "n,n"))
3876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3877 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3878 "includes_lshift_p (operands[2], operands[3])"
3880 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3882 [(set_attr "type" "delayed_compare")
3883 (set_attr "length" "4,8")])
3886 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3888 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3889 (match_operand:SI 2 "const_int_operand" ""))
3890 (match_operand:SI 3 "mask_operand" ""))
3892 (set (match_operand:SI 0 "gpc_reg_operand" "")
3893 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3894 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3896 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3898 (compare:CC (match_dup 0)
3902 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3904 (define_expand "lshrsi3"
3905 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3906 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3907 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3912 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3914 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3918 (define_insn "lshrsi3_power"
3919 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3920 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3921 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3922 (clobber (match_scratch:SI 3 "=q,X,X"))]
3927 {s%A2i|s%A2wi} %0,%1,%h2")
3929 (define_insn "lshrsi3_no_power"
3930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3931 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3932 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3936 {sr|srw}%I2 %0,%1,%h2")
3939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3940 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3941 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3943 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3944 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3949 {s%A2i.|s%A2wi.} %3,%1,%h2
3953 [(set_attr "type" "delayed_compare")
3954 (set_attr "length" "4,4,4,8,8,8")])
3957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3958 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3959 (match_operand:SI 2 "reg_or_cint_operand" ""))
3961 (clobber (match_scratch:SI 3 ""))
3962 (clobber (match_scratch:SI 4 ""))]
3963 "TARGET_POWER && reload_completed"
3964 [(parallel [(set (match_dup 3)
3965 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3966 (clobber (match_dup 4))])
3968 (compare:CC (match_dup 3)
3973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3974 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3975 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3977 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3978 "! TARGET_POWER && TARGET_32BIT"
3981 {sr|srw}%I2. %3,%1,%h2
3984 [(set_attr "type" "delayed_compare")
3985 (set_attr "length" "4,4,8,8")])
3988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3989 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3990 (match_operand:SI 2 "reg_or_cint_operand" ""))
3992 (clobber (match_scratch:SI 3 ""))]
3993 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3995 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3997 (compare:CC (match_dup 3)
4002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4003 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4004 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4006 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4007 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4008 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4013 {s%A2i.|s%A2wi.} %0,%1,%h2
4017 [(set_attr "type" "delayed_compare")
4018 (set_attr "length" "4,4,4,8,8,8")])
4021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4022 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4023 (match_operand:SI 2 "reg_or_cint_operand" ""))
4025 (set (match_operand:SI 0 "gpc_reg_operand" "")
4026 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4027 (clobber (match_scratch:SI 4 ""))]
4028 "TARGET_POWER && reload_completed"
4029 [(parallel [(set (match_dup 0)
4030 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4031 (clobber (match_dup 4))])
4033 (compare:CC (match_dup 0)
4038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4039 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4042 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4043 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4044 "! TARGET_POWER && TARGET_32BIT"
4047 {sr|srw}%I2. %0,%1,%h2
4050 [(set_attr "type" "delayed_compare")
4051 (set_attr "length" "4,4,8,8")])
4054 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4055 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4056 (match_operand:SI 2 "reg_or_cint_operand" ""))
4058 (set (match_operand:SI 0 "gpc_reg_operand" "")
4059 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4060 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4062 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4064 (compare:CC (match_dup 0)
4069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4070 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4071 (match_operand:SI 2 "const_int_operand" "i"))
4072 (match_operand:SI 3 "mask_operand" "n")))]
4073 "includes_rshift_p (operands[2], operands[3])"
4074 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4077 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4079 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4080 (match_operand:SI 2 "const_int_operand" "i,i"))
4081 (match_operand:SI 3 "mask_operand" "n,n"))
4083 (clobber (match_scratch:SI 4 "=r,r"))]
4084 "includes_rshift_p (operands[2], operands[3])"
4086 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4088 [(set_attr "type" "delayed_compare")
4089 (set_attr "length" "4,8")])
4092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4094 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4095 (match_operand:SI 2 "const_int_operand" ""))
4096 (match_operand:SI 3 "mask_operand" ""))
4098 (clobber (match_scratch:SI 4 ""))]
4099 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4101 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4104 (compare:CC (match_dup 4)
4109 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4111 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4112 (match_operand:SI 2 "const_int_operand" "i,i"))
4113 (match_operand:SI 3 "mask_operand" "n,n"))
4115 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4116 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4117 "includes_rshift_p (operands[2], operands[3])"
4119 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4121 [(set_attr "type" "delayed_compare")
4122 (set_attr "length" "4,8")])
4125 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4127 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4128 (match_operand:SI 2 "const_int_operand" ""))
4129 (match_operand:SI 3 "mask_operand" ""))
4131 (set (match_operand:SI 0 "gpc_reg_operand" "")
4132 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4133 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4135 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4137 (compare:CC (match_dup 0)
4142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4145 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4146 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4147 "includes_rshift_p (operands[2], GEN_INT (255))"
4148 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4155 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4156 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4158 (clobber (match_scratch:SI 3 "=r,r"))]
4159 "includes_rshift_p (operands[2], GEN_INT (255))"
4161 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4163 [(set_attr "type" "delayed_compare")
4164 (set_attr "length" "4,8")])
4167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4171 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4172 (match_operand:SI 2 "const_int_operand" "")) 0))
4174 (clobber (match_scratch:SI 3 ""))]
4175 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4177 (zero_extend:SI (subreg:QI
4178 (lshiftrt:SI (match_dup 1)
4181 (compare:CC (match_dup 3)
4186 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4190 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4191 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4194 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4195 "includes_rshift_p (operands[2], GEN_INT (255))"
4197 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4199 [(set_attr "type" "delayed_compare")
4200 (set_attr "length" "4,8")])
4203 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4207 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4208 (match_operand:SI 2 "const_int_operand" "")) 0))
4210 (set (match_operand:SI 0 "gpc_reg_operand" "")
4211 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4212 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4214 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4216 (compare:CC (match_dup 0)
4221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4224 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4225 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4226 "includes_rshift_p (operands[2], GEN_INT (65535))"
4227 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4234 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4235 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4237 (clobber (match_scratch:SI 3 "=r,r"))]
4238 "includes_rshift_p (operands[2], GEN_INT (65535))"
4240 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4242 [(set_attr "type" "delayed_compare")
4243 (set_attr "length" "4,8")])
4246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4250 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "const_int_operand" "")) 0))
4253 (clobber (match_scratch:SI 3 ""))]
4254 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4256 (zero_extend:SI (subreg:HI
4257 (lshiftrt:SI (match_dup 1)
4260 (compare:CC (match_dup 3)
4265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4269 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4270 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4272 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4273 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4274 "includes_rshift_p (operands[2], GEN_INT (65535))"
4276 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4278 [(set_attr "type" "delayed_compare")
4279 (set_attr "length" "4,8")])
4282 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4286 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4287 (match_operand:SI 2 "const_int_operand" "")) 0))
4289 (set (match_operand:SI 0 "gpc_reg_operand" "")
4290 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4291 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4293 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4295 (compare:CC (match_dup 0)
4300 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4302 (match_operand:SI 1 "gpc_reg_operand" "r"))
4303 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4309 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4311 (match_operand:SI 1 "gpc_reg_operand" "r"))
4312 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4318 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4320 (match_operand:SI 1 "gpc_reg_operand" "r"))
4321 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4327 (define_expand "ashrsi3"
4328 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4329 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4335 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4337 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4341 (define_insn "ashrsi3_power"
4342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4343 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4344 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4345 (clobber (match_scratch:SI 3 "=q,X"))]
4349 {srai|srawi} %0,%1,%h2")
4351 (define_insn "ashrsi3_no_power"
4352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4353 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4354 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4356 "{sra|sraw}%I2 %0,%1,%h2")
4359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4360 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4361 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4363 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4364 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4368 {srai.|srawi.} %3,%1,%h2
4371 [(set_attr "type" "delayed_compare")
4372 (set_attr "length" "4,4,8,8")])
4375 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4376 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4377 (match_operand:SI 2 "reg_or_cint_operand" ""))
4379 (clobber (match_scratch:SI 3 ""))
4380 (clobber (match_scratch:SI 4 ""))]
4381 "TARGET_POWER && reload_completed"
4382 [(parallel [(set (match_dup 3)
4383 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4384 (clobber (match_dup 4))])
4386 (compare:CC (match_dup 3)
4391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4392 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4393 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4395 (clobber (match_scratch:SI 3 "=r,r"))]
4398 {sra|sraw}%I2. %3,%1,%h2
4400 [(set_attr "type" "delayed_compare")
4401 (set_attr "length" "4,8")])
4404 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4405 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4406 (match_operand:SI 2 "reg_or_cint_operand" ""))
4408 (clobber (match_scratch:SI 3 ""))]
4409 "! TARGET_POWER && reload_completed"
4411 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4413 (compare:CC (match_dup 3)
4418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4419 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4420 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4423 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4424 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4428 {srai.|srawi.} %0,%1,%h2
4431 [(set_attr "type" "delayed_compare")
4432 (set_attr "length" "4,4,8,8")])
4435 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4436 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4437 (match_operand:SI 2 "reg_or_cint_operand" ""))
4439 (set (match_operand:SI 0 "gpc_reg_operand" "")
4440 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4441 (clobber (match_scratch:SI 4 ""))]
4442 "TARGET_POWER && reload_completed"
4443 [(parallel [(set (match_dup 0)
4444 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4445 (clobber (match_dup 4))])
4447 (compare:CC (match_dup 0)
4452 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4453 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4454 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4456 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4457 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4460 {sra|sraw}%I2. %0,%1,%h2
4462 [(set_attr "type" "delayed_compare")
4463 (set_attr "length" "4,8")])
4466 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4467 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4468 (match_operand:SI 2 "reg_or_cint_operand" ""))
4470 (set (match_operand:SI 0 "gpc_reg_operand" "")
4471 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4472 "! TARGET_POWER && reload_completed"
4474 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4476 (compare:CC (match_dup 0)
4480 ;; Floating-point insns, excluding normal data motion.
4482 ;; PowerPC has a full set of single-precision floating point instructions.
4484 ;; For the POWER architecture, we pretend that we have both SFmode and
4485 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4486 ;; The only conversions we will do will be when storing to memory. In that
4487 ;; case, we will use the "frsp" instruction before storing.
4489 ;; Note that when we store into a single-precision memory location, we need to
4490 ;; use the frsp insn first. If the register being stored isn't dead, we
4491 ;; need a scratch register for the frsp. But this is difficult when the store
4492 ;; is done by reload. It is not incorrect to do the frsp on the register in
4493 ;; this case, we just lose precision that we would have otherwise gotten but
4494 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4496 (define_expand "extendsfdf2"
4497 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4498 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4499 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4502 (define_insn_and_split "*extendsfdf2_fpr"
4503 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4504 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4505 "TARGET_HARD_FLOAT && TARGET_FPRS"
4510 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4513 emit_note (NOTE_INSN_DELETED);
4516 [(set_attr "type" "fp,fp,fpload")])
4518 (define_expand "truncdfsf2"
4519 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4520 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4521 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4524 (define_insn "*truncdfsf2_fpr"
4525 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4526 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4527 "TARGET_HARD_FLOAT && TARGET_FPRS"
4529 [(set_attr "type" "fp")])
4531 (define_insn "aux_truncdfsf2"
4532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4533 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4534 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4536 [(set_attr "type" "fp")])
4538 (define_expand "negsf2"
4539 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4540 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4544 (define_insn "*negsf2"
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4547 "TARGET_HARD_FLOAT && TARGET_FPRS"
4549 [(set_attr "type" "fp")])
4551 (define_expand "abssf2"
4552 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4553 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4557 (define_insn "*abssf2"
4558 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4559 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4560 "TARGET_HARD_FLOAT && TARGET_FPRS"
4562 [(set_attr "type" "fp")])
4565 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4566 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4567 "TARGET_HARD_FLOAT && TARGET_FPRS"
4569 [(set_attr "type" "fp")])
4571 (define_expand "addsf3"
4572 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4573 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4574 (match_operand:SF 2 "gpc_reg_operand" "")))]
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4580 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4581 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4582 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4584 [(set_attr "type" "fp")])
4587 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4588 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4589 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4590 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4591 "{fa|fadd} %0,%1,%2"
4592 [(set_attr "type" "fp")])
4594 (define_expand "subsf3"
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4596 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4597 (match_operand:SF 2 "gpc_reg_operand" "")))]
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4605 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4607 [(set_attr "type" "fp")])
4610 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4611 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4612 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4613 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4614 "{fs|fsub} %0,%1,%2"
4615 [(set_attr "type" "fp")])
4617 (define_expand "mulsf3"
4618 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4619 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4620 (match_operand:SF 2 "gpc_reg_operand" "")))]
4625 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4626 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4627 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4628 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4630 [(set_attr "type" "fp")])
4633 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4634 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4635 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4636 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4637 "{fm|fmul} %0,%1,%2"
4638 [(set_attr "type" "dmul")])
4640 (define_expand "divsf3"
4641 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4642 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4643 (match_operand:SF 2 "gpc_reg_operand" "")))]
4648 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4649 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4650 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4651 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4653 [(set_attr "type" "sdiv")])
4656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4657 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4658 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4659 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4660 "{fd|fdiv} %0,%1,%2"
4661 [(set_attr "type" "ddiv")])
4664 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4665 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4666 (match_operand:SF 2 "gpc_reg_operand" "f"))
4667 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4668 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4669 "fmadds %0,%1,%2,%3"
4670 [(set_attr "type" "fp")])
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4674 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4675 (match_operand:SF 2 "gpc_reg_operand" "f"))
4676 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4677 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4678 "{fma|fmadd} %0,%1,%2,%3"
4679 [(set_attr "type" "dmul")])
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4683 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4684 (match_operand:SF 2 "gpc_reg_operand" "f"))
4685 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4686 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4687 "fmsubs %0,%1,%2,%3"
4688 [(set_attr "type" "fp")])
4691 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4692 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4693 (match_operand:SF 2 "gpc_reg_operand" "f"))
4694 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4695 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4696 "{fms|fmsub} %0,%1,%2,%3"
4697 [(set_attr "type" "dmul")])
4700 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4701 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4702 (match_operand:SF 2 "gpc_reg_operand" "f"))
4703 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4704 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4705 && HONOR_SIGNED_ZEROS (SFmode)"
4706 "fnmadds %0,%1,%2,%3"
4707 [(set_attr "type" "fp")])
4710 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4711 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4712 (match_operand:SF 2 "gpc_reg_operand" "f"))
4713 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4714 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4715 && ! HONOR_SIGNED_ZEROS (SFmode)"
4716 "fnmadds %0,%1,%2,%3"
4717 [(set_attr "type" "fp")])
4720 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4721 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4722 (match_operand:SF 2 "gpc_reg_operand" "f"))
4723 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4724 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4725 "{fnma|fnmadd} %0,%1,%2,%3"
4726 [(set_attr "type" "dmul")])
4729 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4730 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4731 (match_operand:SF 2 "gpc_reg_operand" "f"))
4732 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4733 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4734 && ! HONOR_SIGNED_ZEROS (SFmode)"
4735 "{fnma|fnmadd} %0,%1,%2,%3"
4736 [(set_attr "type" "dmul")])
4739 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4740 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4741 (match_operand:SF 2 "gpc_reg_operand" "f"))
4742 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4743 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4744 && HONOR_SIGNED_ZEROS (SFmode)"
4745 "fnmsubs %0,%1,%2,%3"
4746 [(set_attr "type" "fp")])
4749 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4750 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4751 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4752 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4753 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4754 && ! HONOR_SIGNED_ZEROS (SFmode)"
4755 "fnmsubs %0,%1,%2,%3"
4756 [(set_attr "type" "fp")])
4759 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4760 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4761 (match_operand:SF 2 "gpc_reg_operand" "f"))
4762 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4763 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4764 "{fnms|fnmsub} %0,%1,%2,%3"
4765 [(set_attr "type" "dmul")])
4768 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4769 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4770 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4771 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4772 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4773 && ! HONOR_SIGNED_ZEROS (SFmode)"
4774 "{fnms|fnmsub} %0,%1,%2,%3"
4775 [(set_attr "type" "fp")])
4777 (define_expand "sqrtsf2"
4778 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4779 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4780 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4784 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4785 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4786 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4788 [(set_attr "type" "ssqrt")])
4791 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4792 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4793 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4795 [(set_attr "type" "dsqrt")])
4797 (define_expand "copysignsf3"
4799 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4801 (neg:SF (abs:SF (match_dup 1))))
4802 (set (match_operand:SF 0 "gpc_reg_operand" "")
4803 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4807 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4808 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4810 operands[3] = gen_reg_rtx (SFmode);
4811 operands[4] = gen_reg_rtx (SFmode);
4812 operands[5] = CONST0_RTX (SFmode);
4815 (define_expand "copysigndf3"
4817 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4819 (neg:DF (abs:DF (match_dup 1))))
4820 (set (match_operand:DF 0 "gpc_reg_operand" "")
4821 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4825 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4826 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4828 operands[3] = gen_reg_rtx (DFmode);
4829 operands[4] = gen_reg_rtx (DFmode);
4830 operands[5] = CONST0_RTX (DFmode);
4833 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4834 ;; fsel instruction and some auxiliary computations. Then we just have a
4835 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4837 (define_expand "smaxsf3"
4838 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4839 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4840 (match_operand:SF 2 "gpc_reg_operand" ""))
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4844 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4846 (define_expand "sminsf3"
4847 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4848 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4849 (match_operand:SF 2 "gpc_reg_operand" ""))
4852 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4853 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4857 (match_operator:SF 3 "min_max_operator"
4858 [(match_operand:SF 1 "gpc_reg_operand" "")
4859 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4860 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4863 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4864 operands[1], operands[2]);
4868 (define_expand "movsicc"
4869 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4870 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4871 (match_operand:SI 2 "gpc_reg_operand" "")
4872 (match_operand:SI 3 "gpc_reg_operand" "")))]
4876 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4882 ;; We use the BASE_REGS for the isel input operands because, if rA is
4883 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4884 ;; because we may switch the operands and rB may end up being rA.
4886 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4887 ;; leave out the mode in operand 4 and use one pattern, but reload can
4888 ;; change the mode underneath our feet and then gets confused trying
4889 ;; to reload the value.
4890 (define_insn "isel_signed"
4891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4893 (match_operator 1 "comparison_operator"
4894 [(match_operand:CC 4 "cc_reg_operand" "y")
4896 (match_operand:SI 2 "gpc_reg_operand" "b")
4897 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4900 { return output_isel (operands); }"
4901 [(set_attr "length" "4")])
4903 (define_insn "isel_unsigned"
4904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4906 (match_operator 1 "comparison_operator"
4907 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4909 (match_operand:SI 2 "gpc_reg_operand" "b")
4910 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4913 { return output_isel (operands); }"
4914 [(set_attr "length" "4")])
4916 (define_expand "movsfcc"
4917 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4918 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4919 (match_operand:SF 2 "gpc_reg_operand" "")
4920 (match_operand:SF 3 "gpc_reg_operand" "")))]
4921 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4924 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4930 (define_insn "*fselsfsf4"
4931 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4932 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4933 (match_operand:SF 4 "zero_fp_constant" "F"))
4934 (match_operand:SF 2 "gpc_reg_operand" "f")
4935 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4936 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4938 [(set_attr "type" "fp")])
4940 (define_insn "*fseldfsf4"
4941 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4942 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4943 (match_operand:DF 4 "zero_fp_constant" "F"))
4944 (match_operand:SF 2 "gpc_reg_operand" "f")
4945 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4946 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4948 [(set_attr "type" "fp")])
4950 (define_expand "negdf2"
4951 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4952 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4953 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4956 (define_insn "*negdf2_fpr"
4957 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4958 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4959 "TARGET_HARD_FLOAT && TARGET_FPRS"
4961 [(set_attr "type" "fp")])
4963 (define_expand "absdf2"
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4965 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4966 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4969 (define_insn "*absdf2_fpr"
4970 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4971 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4972 "TARGET_HARD_FLOAT && TARGET_FPRS"
4974 [(set_attr "type" "fp")])
4976 (define_insn "*nabsdf2_fpr"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4978 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4979 "TARGET_HARD_FLOAT && TARGET_FPRS"
4981 [(set_attr "type" "fp")])
4983 (define_expand "adddf3"
4984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4985 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4986 (match_operand:DF 2 "gpc_reg_operand" "")))]
4987 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4990 (define_insn "*adddf3_fpr"
4991 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4992 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4993 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4994 "TARGET_HARD_FLOAT && TARGET_FPRS"
4995 "{fa|fadd} %0,%1,%2"
4996 [(set_attr "type" "fp")])
4998 (define_expand "subdf3"
4999 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5000 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5001 (match_operand:DF 2 "gpc_reg_operand" "")))]
5002 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5005 (define_insn "*subdf3_fpr"
5006 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5007 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5008 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5009 "TARGET_HARD_FLOAT && TARGET_FPRS"
5010 "{fs|fsub} %0,%1,%2"
5011 [(set_attr "type" "fp")])
5013 (define_expand "muldf3"
5014 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5015 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5016 (match_operand:DF 2 "gpc_reg_operand" "")))]
5017 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5020 (define_insn "*muldf3_fpr"
5021 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5022 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5023 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5024 "TARGET_HARD_FLOAT && TARGET_FPRS"
5025 "{fm|fmul} %0,%1,%2"
5026 [(set_attr "type" "dmul")])
5028 (define_expand "divdf3"
5029 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5030 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5031 (match_operand:DF 2 "gpc_reg_operand" "")))]
5032 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5035 (define_insn "*divdf3_fpr"
5036 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5037 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5038 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5039 "TARGET_HARD_FLOAT && TARGET_FPRS"
5040 "{fd|fdiv} %0,%1,%2"
5041 [(set_attr "type" "ddiv")])
5044 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5045 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5046 (match_operand:DF 2 "gpc_reg_operand" "f"))
5047 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5048 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5049 "{fma|fmadd} %0,%1,%2,%3"
5050 [(set_attr "type" "dmul")])
5053 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5054 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5055 (match_operand:DF 2 "gpc_reg_operand" "f"))
5056 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5057 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5058 "{fms|fmsub} %0,%1,%2,%3"
5059 [(set_attr "type" "dmul")])
5062 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5063 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5064 (match_operand:DF 2 "gpc_reg_operand" "f"))
5065 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5066 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5067 && HONOR_SIGNED_ZEROS (DFmode)"
5068 "{fnma|fnmadd} %0,%1,%2,%3"
5069 [(set_attr "type" "dmul")])
5072 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5073 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5074 (match_operand:DF 2 "gpc_reg_operand" "f"))
5075 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5076 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5077 && ! HONOR_SIGNED_ZEROS (DFmode)"
5078 "{fnma|fnmadd} %0,%1,%2,%3"
5079 [(set_attr "type" "dmul")])
5082 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5083 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5084 (match_operand:DF 2 "gpc_reg_operand" "f"))
5085 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5086 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5087 && HONOR_SIGNED_ZEROS (DFmode)"
5088 "{fnms|fnmsub} %0,%1,%2,%3"
5089 [(set_attr "type" "dmul")])
5092 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5093 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5094 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5095 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5096 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5097 && ! HONOR_SIGNED_ZEROS (DFmode)"
5098 "{fnms|fnmsub} %0,%1,%2,%3"
5099 [(set_attr "type" "dmul")])
5101 (define_insn "sqrtdf2"
5102 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5103 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5104 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5106 [(set_attr "type" "dsqrt")])
5108 ;; The conditional move instructions allow us to perform max and min
5109 ;; operations even when
5111 (define_expand "smaxdf3"
5112 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5113 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5114 (match_operand:DF 2 "gpc_reg_operand" ""))
5117 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5118 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5120 (define_expand "smindf3"
5121 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5122 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5123 (match_operand:DF 2 "gpc_reg_operand" ""))
5126 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5127 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5130 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5131 (match_operator:DF 3 "min_max_operator"
5132 [(match_operand:DF 1 "gpc_reg_operand" "")
5133 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5134 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5137 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5138 operands[1], operands[2]);
5142 (define_expand "movdfcc"
5143 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5144 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5145 (match_operand:DF 2 "gpc_reg_operand" "")
5146 (match_operand:DF 3 "gpc_reg_operand" "")))]
5147 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5150 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5156 (define_insn "*fseldfdf4"
5157 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5158 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5159 (match_operand:DF 4 "zero_fp_constant" "F"))
5160 (match_operand:DF 2 "gpc_reg_operand" "f")
5161 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5162 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5164 [(set_attr "type" "fp")])
5166 (define_insn "*fselsfdf4"
5167 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5168 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5169 (match_operand:SF 4 "zero_fp_constant" "F"))
5170 (match_operand:DF 2 "gpc_reg_operand" "f")
5171 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5174 [(set_attr "type" "fp")])
5176 ;; Conversions to and from floating-point.
5178 (define_expand "fixuns_truncsfsi2"
5179 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5180 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5181 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5184 (define_expand "fix_truncsfsi2"
5185 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5186 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5187 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5190 ; For each of these conversions, there is a define_expand, a define_insn
5191 ; with a '#' template, and a define_split (with C code). The idea is
5192 ; to allow constant folding with the template of the define_insn,
5193 ; then to have the insns split later (between sched1 and final).
5195 (define_expand "floatsidf2"
5196 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5197 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5200 (clobber (match_dup 4))
5201 (clobber (match_dup 5))
5202 (clobber (match_dup 6))])]
5203 "TARGET_HARD_FLOAT && TARGET_FPRS"
5206 if (TARGET_E500_DOUBLE)
5208 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5211 if (TARGET_POWERPC64)
5213 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5214 rtx t1 = gen_reg_rtx (DImode);
5215 rtx t2 = gen_reg_rtx (DImode);
5216 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5220 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5221 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5222 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5223 operands[5] = gen_reg_rtx (DFmode);
5224 operands[6] = gen_reg_rtx (SImode);
5227 (define_insn_and_split "*floatsidf2_internal"
5228 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5229 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5230 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5231 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5232 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5233 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5234 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5235 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5237 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5241 rtx lowword, highword;
5242 gcc_assert (MEM_P (operands[4]));
5243 highword = adjust_address (operands[4], SImode, 0);
5244 lowword = adjust_address (operands[4], SImode, 4);
5245 if (! WORDS_BIG_ENDIAN)
5248 tmp = highword; highword = lowword; lowword = tmp;
5251 emit_insn (gen_xorsi3 (operands[6], operands[1],
5252 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5253 emit_move_insn (lowword, operands[6]);
5254 emit_move_insn (highword, operands[2]);
5255 emit_move_insn (operands[5], operands[4]);
5256 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5259 [(set_attr "length" "24")])
5261 (define_expand "floatunssisf2"
5262 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5263 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5264 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5267 (define_expand "floatunssidf2"
5268 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5269 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5272 (clobber (match_dup 4))
5273 (clobber (match_dup 5))])]
5274 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5277 if (TARGET_E500_DOUBLE)
5279 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5282 if (TARGET_POWERPC64)
5284 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5285 rtx t1 = gen_reg_rtx (DImode);
5286 rtx t2 = gen_reg_rtx (DImode);
5287 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5292 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5293 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5294 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5295 operands[5] = gen_reg_rtx (DFmode);
5298 (define_insn_and_split "*floatunssidf2_internal"
5299 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5300 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5301 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5302 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5303 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5304 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5305 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5307 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5311 rtx lowword, highword;
5312 gcc_assert (MEM_P (operands[4]));
5313 highword = adjust_address (operands[4], SImode, 0);
5314 lowword = adjust_address (operands[4], SImode, 4);
5315 if (! WORDS_BIG_ENDIAN)
5318 tmp = highword; highword = lowword; lowword = tmp;
5321 emit_move_insn (lowword, operands[1]);
5322 emit_move_insn (highword, operands[2]);
5323 emit_move_insn (operands[5], operands[4]);
5324 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5327 [(set_attr "length" "20")])
5329 ; In the TARGET_PPC_GFXOPT case, this could and probably should
5330 ; take a memory destination; but actually making this work is hard.
5331 (define_expand "fix_truncdfsi2"
5332 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5333 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5334 (clobber (match_dup 2))
5335 (clobber (match_dup 3))])]
5336 "(TARGET_POWER2 || TARGET_POWERPC)
5337 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5340 if (TARGET_E500_DOUBLE)
5342 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5345 operands[2] = gen_reg_rtx (DImode);
5346 if (TARGET_PPC_GFXOPT)
5348 rtx orig_dest = operands[0];
5349 if (GET_CODE (orig_dest) != MEM)
5350 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5351 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5353 if (operands[0] != orig_dest)
5354 emit_move_insn (orig_dest, operands[0]);
5357 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5360 (define_insn_and_split "*fix_truncdfsi2_internal"
5361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5362 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5363 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5364 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5365 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5367 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5372 gcc_assert (MEM_P (operands[3]));
5373 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5375 emit_insn (gen_fctiwz (operands[2], operands[1]));
5376 emit_move_insn (operands[3], operands[2]);
5377 emit_move_insn (operands[0], lowword);
5380 [(set_attr "length" "16")])
5382 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5383 [(set (match_operand:SI 0 "memory_operand" "=Z")
5384 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5385 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5386 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5387 && TARGET_PPC_GFXOPT"
5393 emit_insn (gen_fctiwz (operands[2], operands[1]));
5394 emit_insn (gen_stfiwx (operands[0], operands[2]));
5397 [(set_attr "length" "16")])
5399 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5400 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5401 ; because the first makes it clear that operand 0 is not live
5402 ; before the instruction.
5403 (define_insn "fctiwz"
5404 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5405 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5407 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5408 "{fcirz|fctiwz} %0,%1"
5409 [(set_attr "type" "fp")])
5411 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5412 (define_insn "stfiwx"
5413 [(set (match_operand:SI 0 "memory_operand" "=Z")
5414 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5418 [(set_attr "type" "fpstore")])
5420 (define_expand "floatsisf2"
5421 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5422 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5423 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5426 (define_insn "floatdidf2"
5427 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5428 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5429 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5431 [(set_attr "type" "fp")])
5433 (define_insn_and_split "floatsidf_ppc64"
5434 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5435 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5436 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5437 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5438 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5439 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5442 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5443 (set (match_dup 2) (match_dup 3))
5444 (set (match_dup 4) (match_dup 2))
5445 (set (match_dup 0) (float:DF (match_dup 4)))]
5448 (define_insn_and_split "floatunssidf_ppc64"
5449 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5450 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5451 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5452 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5453 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5454 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5457 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5458 (set (match_dup 2) (match_dup 3))
5459 (set (match_dup 4) (match_dup 2))
5460 (set (match_dup 0) (float:DF (match_dup 4)))]
5463 (define_insn "fix_truncdfdi2"
5464 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5465 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5466 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5468 [(set_attr "type" "fp")])
5470 (define_expand "floatdisf2"
5471 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5472 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5473 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5476 rtx val = operands[1];
5477 if (!flag_unsafe_math_optimizations)
5479 rtx label = gen_label_rtx ();
5480 val = gen_reg_rtx (DImode);
5481 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5484 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5488 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5489 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5490 ;; from double rounding.
5491 (define_insn_and_split "floatdisf2_internal1"
5492 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5493 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5494 (clobber (match_scratch:DF 2 "=f"))]
5495 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5497 "&& reload_completed"
5499 (float:DF (match_dup 1)))
5501 (float_truncate:SF (match_dup 2)))]
5504 ;; Twiddles bits to avoid double rounding.
5505 ;; Bits that might be truncated when converting to DFmode are replaced
5506 ;; by a bit that won't be lost at that stage, but is below the SFmode
5507 ;; rounding position.
5508 (define_expand "floatdisf2_internal2"
5509 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5511 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5513 (clobber (scratch:CC))])
5514 (set (match_dup 3) (plus:DI (match_dup 3)
5516 (set (match_dup 0) (plus:DI (match_dup 0)
5518 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5520 (set (match_dup 0) (ior:DI (match_dup 0)
5522 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5524 (clobber (scratch:CC))])
5525 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5526 (label_ref (match_operand:DI 2 "" ""))
5528 (set (match_dup 0) (match_dup 1))]
5529 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5532 operands[3] = gen_reg_rtx (DImode);
5533 operands[4] = gen_reg_rtx (CCUNSmode);
5536 ;; Define the DImode operations that can be done in a small number
5537 ;; of instructions. The & constraints are to prevent the register
5538 ;; allocator from allocating registers that overlap with the inputs
5539 ;; (for example, having an input in 7,8 and an output in 6,7). We
5540 ;; also allow for the output being the same as one of the inputs.
5542 (define_insn "*adddi3_noppc64"
5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5544 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5545 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5546 "! TARGET_POWERPC64"
5549 if (WORDS_BIG_ENDIAN)
5550 return (GET_CODE (operands[2])) != CONST_INT
5551 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5552 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5554 return (GET_CODE (operands[2])) != CONST_INT
5555 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5556 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5558 [(set_attr "type" "two")
5559 (set_attr "length" "8")])
5561 (define_insn "*subdi3_noppc64"
5562 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5563 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5564 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5565 "! TARGET_POWERPC64"
5568 if (WORDS_BIG_ENDIAN)
5569 return (GET_CODE (operands[1]) != CONST_INT)
5570 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5571 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5573 return (GET_CODE (operands[1]) != CONST_INT)
5574 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5575 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5577 [(set_attr "type" "two")
5578 (set_attr "length" "8")])
5580 (define_insn "*negdi2_noppc64"
5581 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5582 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5583 "! TARGET_POWERPC64"
5586 return (WORDS_BIG_ENDIAN)
5587 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5588 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5590 [(set_attr "type" "two")
5591 (set_attr "length" "8")])
5593 (define_expand "mulsidi3"
5594 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5595 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5596 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5597 "! TARGET_POWERPC64"
5600 if (! TARGET_POWER && ! TARGET_POWERPC)
5602 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5603 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5604 emit_insn (gen_mull_call ());
5605 if (WORDS_BIG_ENDIAN)
5606 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5609 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5610 gen_rtx_REG (SImode, 3));
5611 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5612 gen_rtx_REG (SImode, 4));
5616 else if (TARGET_POWER)
5618 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5623 (define_insn "mulsidi3_mq"
5624 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5625 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5626 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5627 (clobber (match_scratch:SI 3 "=q"))]
5629 "mul %0,%1,%2\;mfmq %L0"
5630 [(set_attr "type" "imul")
5631 (set_attr "length" "8")])
5633 (define_insn "*mulsidi3_no_mq"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5635 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5636 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5637 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5640 return (WORDS_BIG_ENDIAN)
5641 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5642 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5644 [(set_attr "type" "imul")
5645 (set_attr "length" "8")])
5648 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5649 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5650 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5651 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5654 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5655 (sign_extend:DI (match_dup 2)))
5658 (mult:SI (match_dup 1)
5662 int endian = (WORDS_BIG_ENDIAN == 0);
5663 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5664 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5667 (define_expand "umulsidi3"
5668 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5669 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5670 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5671 "TARGET_POWERPC && ! TARGET_POWERPC64"
5676 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5681 (define_insn "umulsidi3_mq"
5682 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5683 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5684 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5685 (clobber (match_scratch:SI 3 "=q"))]
5686 "TARGET_POWERPC && TARGET_POWER"
5689 return (WORDS_BIG_ENDIAN)
5690 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5691 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5693 [(set_attr "type" "imul")
5694 (set_attr "length" "8")])
5696 (define_insn "*umulsidi3_no_mq"
5697 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5698 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5699 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5700 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5703 return (WORDS_BIG_ENDIAN)
5704 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5705 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5707 [(set_attr "type" "imul")
5708 (set_attr "length" "8")])
5711 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5712 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5713 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5714 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5717 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5718 (zero_extend:DI (match_dup 2)))
5721 (mult:SI (match_dup 1)
5725 int endian = (WORDS_BIG_ENDIAN == 0);
5726 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5727 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5730 (define_expand "smulsi3_highpart"
5731 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5733 (lshiftrt:DI (mult:DI (sign_extend:DI
5734 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5736 (match_operand:SI 2 "gpc_reg_operand" "r")))
5741 if (! TARGET_POWER && ! TARGET_POWERPC)
5743 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5744 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5745 emit_insn (gen_mulh_call ());
5746 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5749 else if (TARGET_POWER)
5751 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5756 (define_insn "smulsi3_highpart_mq"
5757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5759 (lshiftrt:DI (mult:DI (sign_extend:DI
5760 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5762 (match_operand:SI 2 "gpc_reg_operand" "r")))
5764 (clobber (match_scratch:SI 3 "=q"))]
5767 [(set_attr "type" "imul")])
5769 (define_insn "*smulsi3_highpart_no_mq"
5770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5772 (lshiftrt:DI (mult:DI (sign_extend:DI
5773 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5775 (match_operand:SI 2 "gpc_reg_operand" "r")))
5777 "TARGET_POWERPC && ! TARGET_POWER"
5779 [(set_attr "type" "imul")])
5781 (define_expand "umulsi3_highpart"
5782 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5784 (lshiftrt:DI (mult:DI (zero_extend:DI
5785 (match_operand:SI 1 "gpc_reg_operand" ""))
5787 (match_operand:SI 2 "gpc_reg_operand" "")))
5794 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5799 (define_insn "umulsi3_highpart_mq"
5800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5802 (lshiftrt:DI (mult:DI (zero_extend:DI
5803 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5805 (match_operand:SI 2 "gpc_reg_operand" "r")))
5807 (clobber (match_scratch:SI 3 "=q"))]
5808 "TARGET_POWERPC && TARGET_POWER"
5810 [(set_attr "type" "imul")])
5812 (define_insn "*umulsi3_highpart_no_mq"
5813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5815 (lshiftrt:DI (mult:DI (zero_extend:DI
5816 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5818 (match_operand:SI 2 "gpc_reg_operand" "r")))
5820 "TARGET_POWERPC && ! TARGET_POWER"
5822 [(set_attr "type" "imul")])
5824 ;; If operands 0 and 2 are in the same register, we have a problem. But
5825 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5826 ;; why we have the strange constraints below.
5827 (define_insn "ashldi3_power"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5829 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5830 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5831 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5834 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5835 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5836 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5837 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5838 [(set_attr "length" "8")])
5840 (define_insn "lshrdi3_power"
5841 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5842 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5843 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5844 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5847 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5848 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5849 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5850 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5851 [(set_attr "length" "8")])
5853 ;; Shift by a variable amount is too complex to be worth open-coding. We
5854 ;; just handle shifts by constants.
5855 (define_insn "ashrdi3_power"
5856 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5857 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5858 (match_operand:SI 2 "const_int_operand" "M,i")))
5859 (clobber (match_scratch:SI 3 "=X,q"))]
5862 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5863 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5864 [(set_attr "length" "8")])
5866 (define_insn "ashrdi3_no_power"
5867 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5868 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5869 (match_operand:SI 2 "const_int_operand" "M,i")))]
5870 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5872 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5873 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5874 [(set_attr "type" "two,three")
5875 (set_attr "length" "8,12")])
5877 (define_insn "*ashrdisi3_noppc64"
5878 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5879 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5880 (const_int 32)) 4))]
5881 "TARGET_32BIT && !TARGET_POWERPC64"
5884 if (REGNO (operands[0]) == REGNO (operands[1]))
5887 return \"mr %0,%1\";
5889 [(set_attr "length" "4")])
5892 ;; PowerPC64 DImode operations.
5894 (define_insn_and_split "absdi2"
5895 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5896 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5897 (clobber (match_scratch:DI 2 "=&r,&r"))]
5900 "&& reload_completed"
5901 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5902 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5903 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5906 (define_insn_and_split "*nabsdi2"
5907 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5908 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5909 (clobber (match_scratch:DI 2 "=&r,&r"))]
5912 "&& reload_completed"
5913 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5914 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5915 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5918 (define_insn "muldi3"
5919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5920 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5921 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5924 [(set_attr "type" "lmul")])
5926 (define_insn "*muldi3_internal1"
5927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5928 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5929 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5931 (clobber (match_scratch:DI 3 "=r,r"))]
5936 [(set_attr "type" "lmul_compare")
5937 (set_attr "length" "4,8")])
5940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5941 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5942 (match_operand:DI 2 "gpc_reg_operand" ""))
5944 (clobber (match_scratch:DI 3 ""))]
5945 "TARGET_POWERPC64 && reload_completed"
5947 (mult:DI (match_dup 1) (match_dup 2)))
5949 (compare:CC (match_dup 3)
5953 (define_insn "*muldi3_internal2"
5954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5955 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5956 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5958 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5959 (mult:DI (match_dup 1) (match_dup 2)))]
5964 [(set_attr "type" "lmul_compare")
5965 (set_attr "length" "4,8")])
5968 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5969 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5970 (match_operand:DI 2 "gpc_reg_operand" ""))
5972 (set (match_operand:DI 0 "gpc_reg_operand" "")
5973 (mult:DI (match_dup 1) (match_dup 2)))]
5974 "TARGET_POWERPC64 && reload_completed"
5976 (mult:DI (match_dup 1) (match_dup 2)))
5978 (compare:CC (match_dup 0)
5982 (define_insn "smuldi3_highpart"
5983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5985 (lshiftrt:TI (mult:TI (sign_extend:TI
5986 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5988 (match_operand:DI 2 "gpc_reg_operand" "r")))
5992 [(set_attr "type" "lmul")])
5994 (define_insn "umuldi3_highpart"
5995 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5997 (lshiftrt:TI (mult:TI (zero_extend:TI
5998 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6000 (match_operand:DI 2 "gpc_reg_operand" "r")))
6004 [(set_attr "type" "lmul")])
6006 (define_expand "divdi3"
6007 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6008 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6009 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6013 if (GET_CODE (operands[2]) == CONST_INT
6014 && INTVAL (operands[2]) > 0
6015 && exact_log2 (INTVAL (operands[2])) >= 0)
6018 operands[2] = force_reg (DImode, operands[2]);
6021 (define_expand "moddi3"
6022 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6023 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6024 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6032 if (GET_CODE (operands[2]) != CONST_INT
6033 || INTVAL (operands[2]) <= 0
6034 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6037 temp1 = gen_reg_rtx (DImode);
6038 temp2 = gen_reg_rtx (DImode);
6040 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6041 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6042 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6047 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6048 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6049 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6051 "sradi %0,%1,%p2\;addze %0,%0"
6052 [(set_attr "type" "two")
6053 (set_attr "length" "8")])
6056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6057 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6058 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6060 (clobber (match_scratch:DI 3 "=r,r"))]
6063 sradi %3,%1,%p2\;addze. %3,%3
6065 [(set_attr "type" "compare")
6066 (set_attr "length" "8,12")])
6069 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6070 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6071 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6073 (clobber (match_scratch:DI 3 ""))]
6074 "TARGET_POWERPC64 && reload_completed"
6076 (div:DI (match_dup 1) (match_dup 2)))
6078 (compare:CC (match_dup 3)
6083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6084 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6085 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6087 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6088 (div:DI (match_dup 1) (match_dup 2)))]
6091 sradi %0,%1,%p2\;addze. %0,%0
6093 [(set_attr "type" "compare")
6094 (set_attr "length" "8,12")])
6097 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6098 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6099 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6101 (set (match_operand:DI 0 "gpc_reg_operand" "")
6102 (div:DI (match_dup 1) (match_dup 2)))]
6103 "TARGET_POWERPC64 && reload_completed"
6105 (div:DI (match_dup 1) (match_dup 2)))
6107 (compare:CC (match_dup 0)
6112 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6113 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6114 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6117 [(set_attr "type" "ldiv")])
6119 (define_insn "udivdi3"
6120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6121 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6122 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6125 [(set_attr "type" "ldiv")])
6127 (define_insn "rotldi3"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6129 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6130 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6132 "rld%I2cl %0,%1,%H2,0")
6134 (define_insn "*rotldi3_internal2"
6135 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6136 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6137 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6139 (clobber (match_scratch:DI 3 "=r,r"))]
6142 rld%I2cl. %3,%1,%H2,0
6144 [(set_attr "type" "delayed_compare")
6145 (set_attr "length" "4,8")])
6148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6149 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6150 (match_operand:DI 2 "reg_or_cint_operand" ""))
6152 (clobber (match_scratch:DI 3 ""))]
6153 "TARGET_POWERPC64 && reload_completed"
6155 (rotate:DI (match_dup 1) (match_dup 2)))
6157 (compare:CC (match_dup 3)
6161 (define_insn "*rotldi3_internal3"
6162 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6163 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6164 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6166 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6167 (rotate:DI (match_dup 1) (match_dup 2)))]
6170 rld%I2cl. %0,%1,%H2,0
6172 [(set_attr "type" "delayed_compare")
6173 (set_attr "length" "4,8")])
6176 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6177 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6178 (match_operand:DI 2 "reg_or_cint_operand" ""))
6180 (set (match_operand:DI 0 "gpc_reg_operand" "")
6181 (rotate:DI (match_dup 1) (match_dup 2)))]
6182 "TARGET_POWERPC64 && reload_completed"
6184 (rotate:DI (match_dup 1) (match_dup 2)))
6186 (compare:CC (match_dup 0)
6190 (define_insn "*rotldi3_internal4"
6191 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6192 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6193 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6194 (match_operand:DI 3 "mask64_operand" "n")))]
6196 "rld%I2c%B3 %0,%1,%H2,%S3")
6198 (define_insn "*rotldi3_internal5"
6199 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6201 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6202 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6203 (match_operand:DI 3 "mask64_operand" "n,n"))
6205 (clobber (match_scratch:DI 4 "=r,r"))]
6208 rld%I2c%B3. %4,%1,%H2,%S3
6210 [(set_attr "type" "delayed_compare")
6211 (set_attr "length" "4,8")])
6214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6216 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6217 (match_operand:DI 2 "reg_or_cint_operand" ""))
6218 (match_operand:DI 3 "mask64_operand" ""))
6220 (clobber (match_scratch:DI 4 ""))]
6221 "TARGET_POWERPC64 && reload_completed"
6223 (and:DI (rotate:DI (match_dup 1)
6227 (compare:CC (match_dup 4)
6231 (define_insn "*rotldi3_internal6"
6232 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6234 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6235 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6236 (match_operand:DI 3 "mask64_operand" "n,n"))
6238 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6239 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6242 rld%I2c%B3. %0,%1,%H2,%S3
6244 [(set_attr "type" "delayed_compare")
6245 (set_attr "length" "4,8")])
6248 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6250 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6251 (match_operand:DI 2 "reg_or_cint_operand" ""))
6252 (match_operand:DI 3 "mask64_operand" ""))
6254 (set (match_operand:DI 0 "gpc_reg_operand" "")
6255 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6256 "TARGET_POWERPC64 && reload_completed"
6258 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6260 (compare:CC (match_dup 0)
6264 (define_insn "*rotldi3_internal7"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6268 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6269 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6271 "rld%I2cl %0,%1,%H2,56")
6273 (define_insn "*rotldi3_internal8"
6274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6275 (compare:CC (zero_extend:DI
6277 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6278 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6280 (clobber (match_scratch:DI 3 "=r,r"))]
6283 rld%I2cl. %3,%1,%H2,56
6285 [(set_attr "type" "delayed_compare")
6286 (set_attr "length" "4,8")])
6289 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6290 (compare:CC (zero_extend:DI
6292 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6295 (clobber (match_scratch:DI 3 ""))]
6296 "TARGET_POWERPC64 && reload_completed"
6298 (zero_extend:DI (subreg:QI
6299 (rotate:DI (match_dup 1)
6302 (compare:CC (match_dup 3)
6306 (define_insn "*rotldi3_internal9"
6307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6308 (compare:CC (zero_extend:DI
6310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6311 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6314 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6317 rld%I2cl. %0,%1,%H2,56
6319 [(set_attr "type" "delayed_compare")
6320 (set_attr "length" "4,8")])
6323 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6324 (compare:CC (zero_extend:DI
6326 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6327 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6329 (set (match_operand:DI 0 "gpc_reg_operand" "")
6330 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6331 "TARGET_POWERPC64 && reload_completed"
6333 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6335 (compare:CC (match_dup 0)
6339 (define_insn "*rotldi3_internal10"
6340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6343 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6344 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6346 "rld%I2cl %0,%1,%H2,48")
6348 (define_insn "*rotldi3_internal11"
6349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6350 (compare:CC (zero_extend:DI
6352 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6353 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6355 (clobber (match_scratch:DI 3 "=r,r"))]
6358 rld%I2cl. %3,%1,%H2,48
6360 [(set_attr "type" "delayed_compare")
6361 (set_attr "length" "4,8")])
6364 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6365 (compare:CC (zero_extend:DI
6367 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6368 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6370 (clobber (match_scratch:DI 3 ""))]
6371 "TARGET_POWERPC64 && reload_completed"
6373 (zero_extend:DI (subreg:HI
6374 (rotate:DI (match_dup 1)
6377 (compare:CC (match_dup 3)
6381 (define_insn "*rotldi3_internal12"
6382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6383 (compare:CC (zero_extend:DI
6385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6386 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6388 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6389 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6392 rld%I2cl. %0,%1,%H2,48
6394 [(set_attr "type" "delayed_compare")
6395 (set_attr "length" "4,8")])
6398 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6399 (compare:CC (zero_extend:DI
6401 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6402 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6404 (set (match_operand:DI 0 "gpc_reg_operand" "")
6405 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6406 "TARGET_POWERPC64 && reload_completed"
6408 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6410 (compare:CC (match_dup 0)
6414 (define_insn "*rotldi3_internal13"
6415 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6418 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6419 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6421 "rld%I2cl %0,%1,%H2,32")
6423 (define_insn "*rotldi3_internal14"
6424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6425 (compare:CC (zero_extend:DI
6427 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6428 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6430 (clobber (match_scratch:DI 3 "=r,r"))]
6433 rld%I2cl. %3,%1,%H2,32
6435 [(set_attr "type" "delayed_compare")
6436 (set_attr "length" "4,8")])
6439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6440 (compare:CC (zero_extend:DI
6442 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6443 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6445 (clobber (match_scratch:DI 3 ""))]
6446 "TARGET_POWERPC64 && reload_completed"
6448 (zero_extend:DI (subreg:SI
6449 (rotate:DI (match_dup 1)
6452 (compare:CC (match_dup 3)
6456 (define_insn "*rotldi3_internal15"
6457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6458 (compare:CC (zero_extend:DI
6460 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6461 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6463 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6464 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6467 rld%I2cl. %0,%1,%H2,32
6469 [(set_attr "type" "delayed_compare")
6470 (set_attr "length" "4,8")])
6473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6474 (compare:CC (zero_extend:DI
6476 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6477 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6479 (set (match_operand:DI 0 "gpc_reg_operand" "")
6480 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6481 "TARGET_POWERPC64 && reload_completed"
6483 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6485 (compare:CC (match_dup 0)
6489 (define_expand "ashldi3"
6490 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6491 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6492 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6493 "TARGET_POWERPC64 || TARGET_POWER"
6496 if (TARGET_POWERPC64)
6498 else if (TARGET_POWER)
6500 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6507 (define_insn "*ashldi3_internal1"
6508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6509 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6510 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6514 (define_insn "*ashldi3_internal2"
6515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6516 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6517 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6519 (clobber (match_scratch:DI 3 "=r,r"))]
6524 [(set_attr "type" "delayed_compare")
6525 (set_attr "length" "4,8")])
6528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6529 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6530 (match_operand:SI 2 "reg_or_cint_operand" ""))
6532 (clobber (match_scratch:DI 3 ""))]
6533 "TARGET_POWERPC64 && reload_completed"
6535 (ashift:DI (match_dup 1) (match_dup 2)))
6537 (compare:CC (match_dup 3)
6541 (define_insn "*ashldi3_internal3"
6542 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6543 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6544 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6546 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6547 (ashift:DI (match_dup 1) (match_dup 2)))]
6552 [(set_attr "type" "delayed_compare")
6553 (set_attr "length" "4,8")])
6556 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6557 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6558 (match_operand:SI 2 "reg_or_cint_operand" ""))
6560 (set (match_operand:DI 0 "gpc_reg_operand" "")
6561 (ashift:DI (match_dup 1) (match_dup 2)))]
6562 "TARGET_POWERPC64 && reload_completed"
6564 (ashift:DI (match_dup 1) (match_dup 2)))
6566 (compare:CC (match_dup 0)
6570 (define_insn "*ashldi3_internal4"
6571 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6572 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6573 (match_operand:SI 2 "const_int_operand" "i"))
6574 (match_operand:DI 3 "const_int_operand" "n")))]
6575 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6576 "rldic %0,%1,%H2,%W3")
6578 (define_insn "ashldi3_internal5"
6579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6581 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6582 (match_operand:SI 2 "const_int_operand" "i,i"))
6583 (match_operand:DI 3 "const_int_operand" "n,n"))
6585 (clobber (match_scratch:DI 4 "=r,r"))]
6586 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6588 rldic. %4,%1,%H2,%W3
6590 [(set_attr "type" "delayed_compare")
6591 (set_attr "length" "4,8")])
6594 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6596 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6597 (match_operand:SI 2 "const_int_operand" ""))
6598 (match_operand:DI 3 "const_int_operand" ""))
6600 (clobber (match_scratch:DI 4 ""))]
6601 "TARGET_POWERPC64 && reload_completed
6602 && includes_rldic_lshift_p (operands[2], operands[3])"
6604 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6607 (compare:CC (match_dup 4)
6611 (define_insn "*ashldi3_internal6"
6612 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6614 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6615 (match_operand:SI 2 "const_int_operand" "i,i"))
6616 (match_operand:DI 3 "const_int_operand" "n,n"))
6618 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6619 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6620 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6622 rldic. %0,%1,%H2,%W3
6624 [(set_attr "type" "delayed_compare")
6625 (set_attr "length" "4,8")])
6628 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6630 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6631 (match_operand:SI 2 "const_int_operand" ""))
6632 (match_operand:DI 3 "const_int_operand" ""))
6634 (set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6636 "TARGET_POWERPC64 && reload_completed
6637 && includes_rldic_lshift_p (operands[2], operands[3])"
6639 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6642 (compare:CC (match_dup 0)
6646 (define_insn "*ashldi3_internal7"
6647 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6648 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6649 (match_operand:SI 2 "const_int_operand" "i"))
6650 (match_operand:DI 3 "mask64_operand" "n")))]
6651 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6652 "rldicr %0,%1,%H2,%S3")
6654 (define_insn "ashldi3_internal8"
6655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6657 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6658 (match_operand:SI 2 "const_int_operand" "i,i"))
6659 (match_operand:DI 3 "mask64_operand" "n,n"))
6661 (clobber (match_scratch:DI 4 "=r,r"))]
6662 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6664 rldicr. %4,%1,%H2,%S3
6666 [(set_attr "type" "delayed_compare")
6667 (set_attr "length" "4,8")])
6670 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6672 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6673 (match_operand:SI 2 "const_int_operand" ""))
6674 (match_operand:DI 3 "mask64_operand" ""))
6676 (clobber (match_scratch:DI 4 ""))]
6677 "TARGET_POWERPC64 && reload_completed
6678 && includes_rldicr_lshift_p (operands[2], operands[3])"
6680 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6683 (compare:CC (match_dup 4)
6687 (define_insn "*ashldi3_internal9"
6688 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6690 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6691 (match_operand:SI 2 "const_int_operand" "i,i"))
6692 (match_operand:DI 3 "mask64_operand" "n,n"))
6694 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6695 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6696 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6698 rldicr. %0,%1,%H2,%S3
6700 [(set_attr "type" "delayed_compare")
6701 (set_attr "length" "4,8")])
6704 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6706 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:SI 2 "const_int_operand" ""))
6708 (match_operand:DI 3 "mask64_operand" ""))
6710 (set (match_operand:DI 0 "gpc_reg_operand" "")
6711 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6712 "TARGET_POWERPC64 && reload_completed
6713 && includes_rldicr_lshift_p (operands[2], operands[3])"
6715 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6718 (compare:CC (match_dup 0)
6722 (define_expand "lshrdi3"
6723 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6724 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6725 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6726 "TARGET_POWERPC64 || TARGET_POWER"
6729 if (TARGET_POWERPC64)
6731 else if (TARGET_POWER)
6733 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6740 (define_insn "*lshrdi3_internal1"
6741 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6742 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6743 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6747 (define_insn "*lshrdi3_internal2"
6748 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6749 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6750 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6752 (clobber (match_scratch:DI 3 "=r,r"))]
6757 [(set_attr "type" "delayed_compare")
6758 (set_attr "length" "4,8")])
6761 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6762 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6763 (match_operand:SI 2 "reg_or_cint_operand" ""))
6765 (clobber (match_scratch:DI 3 ""))]
6766 "TARGET_POWERPC64 && reload_completed"
6768 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6770 (compare:CC (match_dup 3)
6774 (define_insn "*lshrdi3_internal3"
6775 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6776 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6777 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6779 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6780 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6785 [(set_attr "type" "delayed_compare")
6786 (set_attr "length" "4,8")])
6789 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6790 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:SI 2 "reg_or_cint_operand" ""))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6795 "TARGET_POWERPC64 && reload_completed"
6797 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6799 (compare:CC (match_dup 0)
6803 (define_expand "ashrdi3"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6805 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6806 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6810 if (TARGET_POWERPC64)
6812 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6814 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6817 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6818 && WORDS_BIG_ENDIAN)
6820 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6827 (define_insn "*ashrdi3_internal1"
6828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6829 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6830 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6832 "srad%I2 %0,%1,%H2")
6834 (define_insn "*ashrdi3_internal2"
6835 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6836 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6837 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6839 (clobber (match_scratch:DI 3 "=r,r"))]
6844 [(set_attr "type" "delayed_compare")
6845 (set_attr "length" "4,8")])
6848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6849 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6850 (match_operand:SI 2 "reg_or_cint_operand" ""))
6852 (clobber (match_scratch:DI 3 ""))]
6853 "TARGET_POWERPC64 && reload_completed"
6855 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6857 (compare:CC (match_dup 3)
6861 (define_insn "*ashrdi3_internal3"
6862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6863 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6864 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6867 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6872 [(set_attr "type" "delayed_compare")
6873 (set_attr "length" "4,8")])
6876 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6877 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6878 (match_operand:SI 2 "reg_or_cint_operand" ""))
6880 (set (match_operand:DI 0 "gpc_reg_operand" "")
6881 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6882 "TARGET_POWERPC64 && reload_completed"
6884 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6886 (compare:CC (match_dup 0)
6890 (define_insn "anddi3"
6891 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6892 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6893 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6894 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6898 rldic%B2 %0,%1,0,%S2
6899 rlwinm %0,%1,0,%m2,%M2
6903 [(set_attr "type" "*,*,*,compare,compare,*")
6904 (set_attr "length" "4,4,4,4,4,8")])
6907 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6908 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:DI 2 "mask64_2_operand" "")))
6910 (clobber (match_scratch:CC 3 ""))]
6912 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6913 && !mask64_operand (operands[2], DImode)"
6915 (and:DI (rotate:DI (match_dup 1)
6919 (and:DI (rotate:DI (match_dup 0)
6923 build_mask64_2_operands (operands[2], &operands[4]);
6926 (define_insn "*anddi3_internal2"
6927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6928 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6929 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6931 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6932 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6936 rldic%B2. %3,%1,0,%S2
6945 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6946 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6949 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6950 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6951 (match_operand:DI 2 "and64_operand" ""))
6953 (clobber (match_scratch:DI 3 ""))
6954 (clobber (match_scratch:CC 4 ""))]
6955 "TARGET_POWERPC64 && reload_completed"
6956 [(parallel [(set (match_dup 3)
6957 (and:DI (match_dup 1)
6959 (clobber (match_dup 4))])
6961 (compare:CC (match_dup 3)
6966 [(set (match_operand:CC 0 "cc_reg_operand" "")
6967 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6968 (match_operand:DI 2 "mask64_2_operand" ""))
6970 (clobber (match_scratch:DI 3 ""))
6971 (clobber (match_scratch:CC 4 ""))]
6972 "TARGET_POWERPC64 && reload_completed
6973 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6974 && !mask64_operand (operands[2], DImode)"
6976 (and:DI (rotate:DI (match_dup 1)
6979 (parallel [(set (match_dup 0)
6980 (compare:CC (and:DI (rotate:DI (match_dup 3)
6984 (clobber (match_dup 3))])]
6987 build_mask64_2_operands (operands[2], &operands[5]);
6990 (define_insn "*anddi3_internal3"
6991 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6992 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6993 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6995 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6996 (and:DI (match_dup 1) (match_dup 2)))
6997 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7001 rldic%B2. %0,%1,0,%S2
7010 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7011 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7014 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7015 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7016 (match_operand:DI 2 "and64_operand" ""))
7018 (set (match_operand:DI 0 "gpc_reg_operand" "")
7019 (and:DI (match_dup 1) (match_dup 2)))
7020 (clobber (match_scratch:CC 4 ""))]
7021 "TARGET_POWERPC64 && reload_completed"
7022 [(parallel [(set (match_dup 0)
7023 (and:DI (match_dup 1) (match_dup 2)))
7024 (clobber (match_dup 4))])
7026 (compare:CC (match_dup 0)
7031 [(set (match_operand:CC 3 "cc_reg_operand" "")
7032 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7033 (match_operand:DI 2 "mask64_2_operand" ""))
7035 (set (match_operand:DI 0 "gpc_reg_operand" "")
7036 (and:DI (match_dup 1) (match_dup 2)))
7037 (clobber (match_scratch:CC 4 ""))]
7038 "TARGET_POWERPC64 && reload_completed
7039 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7040 && !mask64_operand (operands[2], DImode)"
7042 (and:DI (rotate:DI (match_dup 1)
7045 (parallel [(set (match_dup 3)
7046 (compare:CC (and:DI (rotate:DI (match_dup 0)
7051 (and:DI (rotate:DI (match_dup 0)
7056 build_mask64_2_operands (operands[2], &operands[5]);
7059 (define_expand "iordi3"
7060 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7061 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7062 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7066 if (non_logical_cint_operand (operands[2], DImode))
7068 HOST_WIDE_INT value;
7069 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7070 ? operands[0] : gen_reg_rtx (DImode));
7072 if (GET_CODE (operands[2]) == CONST_INT)
7074 value = INTVAL (operands[2]);
7075 emit_insn (gen_iordi3 (tmp, operands[1],
7076 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7080 value = CONST_DOUBLE_LOW (operands[2]);
7081 emit_insn (gen_iordi3 (tmp, operands[1],
7082 immed_double_const (value
7083 & (~ (HOST_WIDE_INT) 0xffff),
7087 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7092 (define_expand "xordi3"
7093 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7094 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7095 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7099 if (non_logical_cint_operand (operands[2], DImode))
7101 HOST_WIDE_INT value;
7102 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7103 ? operands[0] : gen_reg_rtx (DImode));
7105 if (GET_CODE (operands[2]) == CONST_INT)
7107 value = INTVAL (operands[2]);
7108 emit_insn (gen_xordi3 (tmp, operands[1],
7109 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7113 value = CONST_DOUBLE_LOW (operands[2]);
7114 emit_insn (gen_xordi3 (tmp, operands[1],
7115 immed_double_const (value
7116 & (~ (HOST_WIDE_INT) 0xffff),
7120 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7125 (define_insn "*booldi3_internal1"
7126 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7127 (match_operator:DI 3 "boolean_or_operator"
7128 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7129 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7136 (define_insn "*booldi3_internal2"
7137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7138 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7139 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7140 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7142 (clobber (match_scratch:DI 3 "=r,r"))]
7147 [(set_attr "type" "compare")
7148 (set_attr "length" "4,8")])
7151 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7152 (compare:CC (match_operator:DI 4 "boolean_operator"
7153 [(match_operand:DI 1 "gpc_reg_operand" "")
7154 (match_operand:DI 2 "gpc_reg_operand" "")])
7156 (clobber (match_scratch:DI 3 ""))]
7157 "TARGET_POWERPC64 && reload_completed"
7158 [(set (match_dup 3) (match_dup 4))
7160 (compare:CC (match_dup 3)
7164 (define_insn "*booldi3_internal3"
7165 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7166 (compare:CC (match_operator:DI 4 "boolean_operator"
7167 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7168 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7170 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7176 [(set_attr "type" "compare")
7177 (set_attr "length" "4,8")])
7180 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7181 (compare:CC (match_operator:DI 4 "boolean_operator"
7182 [(match_operand:DI 1 "gpc_reg_operand" "")
7183 (match_operand:DI 2 "gpc_reg_operand" "")])
7185 (set (match_operand:DI 0 "gpc_reg_operand" "")
7187 "TARGET_POWERPC64 && reload_completed"
7188 [(set (match_dup 0) (match_dup 4))
7190 (compare:CC (match_dup 0)
7194 ;; Split a logical operation that we can't do in one insn into two insns,
7195 ;; each of which does one 16-bit part. This is used by combine.
7198 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7199 (match_operator:DI 3 "boolean_or_operator"
7200 [(match_operand:DI 1 "gpc_reg_operand" "")
7201 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7203 [(set (match_dup 0) (match_dup 4))
7204 (set (match_dup 0) (match_dup 5))]
7209 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7211 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7212 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7214 i4 = GEN_INT (value & 0xffff);
7218 i3 = GEN_INT (INTVAL (operands[2])
7219 & (~ (HOST_WIDE_INT) 0xffff));
7220 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7222 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7224 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7228 (define_insn "*boolcdi3_internal1"
7229 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7230 (match_operator:DI 3 "boolean_operator"
7231 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7232 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7236 (define_insn "*boolcdi3_internal2"
7237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7238 (compare:CC (match_operator:DI 4 "boolean_operator"
7239 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7240 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7242 (clobber (match_scratch:DI 3 "=r,r"))]
7247 [(set_attr "type" "compare")
7248 (set_attr "length" "4,8")])
7251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7252 (compare:CC (match_operator:DI 4 "boolean_operator"
7253 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7254 (match_operand:DI 2 "gpc_reg_operand" "")])
7256 (clobber (match_scratch:DI 3 ""))]
7257 "TARGET_POWERPC64 && reload_completed"
7258 [(set (match_dup 3) (match_dup 4))
7260 (compare:CC (match_dup 3)
7264 (define_insn "*boolcdi3_internal3"
7265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7266 (compare:CC (match_operator:DI 4 "boolean_operator"
7267 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7268 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7270 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7276 [(set_attr "type" "compare")
7277 (set_attr "length" "4,8")])
7280 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7281 (compare:CC (match_operator:DI 4 "boolean_operator"
7282 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7283 (match_operand:DI 2 "gpc_reg_operand" "")])
7285 (set (match_operand:DI 0 "gpc_reg_operand" "")
7287 "TARGET_POWERPC64 && reload_completed"
7288 [(set (match_dup 0) (match_dup 4))
7290 (compare:CC (match_dup 0)
7294 (define_insn "*boolccdi3_internal1"
7295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7296 (match_operator:DI 3 "boolean_operator"
7297 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7298 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7302 (define_insn "*boolccdi3_internal2"
7303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7304 (compare:CC (match_operator:DI 4 "boolean_operator"
7305 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7306 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7308 (clobber (match_scratch:DI 3 "=r,r"))]
7313 [(set_attr "type" "compare")
7314 (set_attr "length" "4,8")])
7317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7318 (compare:CC (match_operator:DI 4 "boolean_operator"
7319 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7320 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7322 (clobber (match_scratch:DI 3 ""))]
7323 "TARGET_POWERPC64 && reload_completed"
7324 [(set (match_dup 3) (match_dup 4))
7326 (compare:CC (match_dup 3)
7330 (define_insn "*boolccdi3_internal3"
7331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7332 (compare:CC (match_operator:DI 4 "boolean_operator"
7333 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7334 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7336 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7342 [(set_attr "type" "compare")
7343 (set_attr "length" "4,8")])
7346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7347 (compare:CC (match_operator:DI 4 "boolean_operator"
7348 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7349 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7351 (set (match_operand:DI 0 "gpc_reg_operand" "")
7353 "TARGET_POWERPC64 && reload_completed"
7354 [(set (match_dup 0) (match_dup 4))
7356 (compare:CC (match_dup 0)
7360 ;; Now define ways of moving data around.
7362 ;; Elf specific ways of loading addresses for non-PIC code.
7363 ;; The output of this could be r0, but we make a very strong
7364 ;; preference for a base register because it will usually
7366 (define_insn "elf_high"
7367 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7368 (high:SI (match_operand 1 "" "")))]
7369 "TARGET_ELF && ! TARGET_64BIT"
7370 "{liu|lis} %0,%1@ha")
7372 (define_insn "elf_low"
7373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7374 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7375 (match_operand 2 "" "")))]
7376 "TARGET_ELF && ! TARGET_64BIT"
7378 {cal|la} %0,%2@l(%1)
7379 {ai|addic} %0,%1,%K2")
7382 ;; Set up a register with a value from the GOT table
7384 (define_expand "movsi_got"
7385 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7386 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7387 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7388 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7391 if (GET_CODE (operands[1]) == CONST)
7393 rtx offset = const0_rtx;
7394 HOST_WIDE_INT value;
7396 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7397 value = INTVAL (offset);
7400 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7401 emit_insn (gen_movsi_got (tmp, operands[1]));
7402 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7407 operands[2] = rs6000_got_register (operands[1]);
7410 (define_insn "*movsi_got_internal"
7411 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7412 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7413 (match_operand:SI 2 "gpc_reg_operand" "b")]
7415 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7416 "{l|lwz} %0,%a1@got(%2)"
7417 [(set_attr "type" "load")])
7419 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7420 ;; didn't get allocated to a hard register.
7422 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7423 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7424 (match_operand:SI 2 "memory_operand" "")]
7426 "DEFAULT_ABI == ABI_V4
7428 && (reload_in_progress || reload_completed)"
7429 [(set (match_dup 0) (match_dup 2))
7430 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7434 ;; For SI, we special-case integers that can't be loaded in one insn. We
7435 ;; do the load 16-bits at a time. We could do this by loading from memory,
7436 ;; and this is even supposed to be faster, but it is simpler not to get
7437 ;; integers in the TOC.
7438 (define_expand "movsi"
7439 [(set (match_operand:SI 0 "general_operand" "")
7440 (match_operand:SI 1 "any_operand" ""))]
7442 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7444 (define_insn "movsi_low"
7445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7446 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7447 (match_operand 2 "" ""))))]
7448 "TARGET_MACHO && ! TARGET_64BIT"
7449 "{l|lwz} %0,lo16(%2)(%1)"
7450 [(set_attr "type" "load")
7451 (set_attr "length" "4")])
7453 (define_insn "*movsi_internal1"
7454 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7455 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7456 "gpc_reg_operand (operands[0], SImode)
7457 || gpc_reg_operand (operands[1], SImode)"
7461 {l%U1%X1|lwz%U1%X1} %0,%1
7462 {st%U0%X0|stw%U0%X0} %1,%0
7472 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7473 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7475 ;; Split a load of a large constant into the appropriate two-insn
7479 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7480 (match_operand:SI 1 "const_int_operand" ""))]
7481 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7482 && (INTVAL (operands[1]) & 0xffff) != 0"
7486 (ior:SI (match_dup 0)
7489 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7491 if (tem == operands[0])
7497 (define_insn "*movsi_internal2"
7498 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7499 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7504 {cmpi|cmpwi} %2,%0,0
7507 [(set_attr "type" "cmp,compare,cmp")
7508 (set_attr "length" "4,4,8")])
7511 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7512 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7514 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7515 "TARGET_32BIT && reload_completed"
7516 [(set (match_dup 0) (match_dup 1))
7518 (compare:CC (match_dup 0)
7522 (define_expand "movhi"
7523 [(set (match_operand:HI 0 "general_operand" "")
7524 (match_operand:HI 1 "any_operand" ""))]
7526 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7528 (define_insn "*movhi_internal"
7529 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7530 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7531 "gpc_reg_operand (operands[0], HImode)
7532 || gpc_reg_operand (operands[1], HImode)"
7542 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7544 (define_expand "movqi"
7545 [(set (match_operand:QI 0 "general_operand" "")
7546 (match_operand:QI 1 "any_operand" ""))]
7548 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7550 (define_insn "*movqi_internal"
7551 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7552 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7553 "gpc_reg_operand (operands[0], QImode)
7554 || gpc_reg_operand (operands[1], QImode)"
7564 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7566 ;; Here is how to move condition codes around. When we store CC data in
7567 ;; an integer register or memory, we store just the high-order 4 bits.
7568 ;; This lets us not shift in the most common case of CR0.
7569 (define_expand "movcc"
7570 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7571 (match_operand:CC 1 "nonimmediate_operand" ""))]
7575 (define_insn "*movcc_internal1"
7576 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7577 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7578 "register_operand (operands[0], CCmode)
7579 || register_operand (operands[1], CCmode)"
7583 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7585 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7590 {l%U1%X1|lwz%U1%X1} %0,%1
7591 {st%U0%U1|stw%U0%U1} %1,%0"
7593 (cond [(eq_attr "alternative" "0")
7594 (const_string "cr_logical")
7595 (eq_attr "alternative" "1,2")
7596 (const_string "mtcr")
7597 (eq_attr "alternative" "5,7")
7598 (const_string "integer")
7599 (eq_attr "alternative" "6")
7600 (const_string "mfjmpr")
7601 (eq_attr "alternative" "8")
7602 (const_string "mtjmpr")
7603 (eq_attr "alternative" "9")
7604 (const_string "load")
7605 (eq_attr "alternative" "10")
7606 (const_string "store")
7607 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7608 (const_string "mfcrf")
7610 (const_string "mfcr")))
7611 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7613 ;; For floating-point, we normally deal with the floating-point registers
7614 ;; unless -msoft-float is used. The sole exception is that parameter passing
7615 ;; can produce floating-point values in fixed-point registers. Unless the
7616 ;; value is a simple constant or already in memory, we deal with this by
7617 ;; allocating memory and copying the value explicitly via that memory location.
7618 (define_expand "movsf"
7619 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7620 (match_operand:SF 1 "any_operand" ""))]
7622 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7625 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7626 (match_operand:SF 1 "const_double_operand" ""))]
7628 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7629 || (GET_CODE (operands[0]) == SUBREG
7630 && GET_CODE (SUBREG_REG (operands[0])) == REG
7631 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7632 [(set (match_dup 2) (match_dup 3))]
7638 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7639 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7641 if (! TARGET_POWERPC64)
7642 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7644 operands[2] = gen_lowpart (SImode, operands[0]);
7646 operands[3] = gen_int_mode (l, SImode);
7649 (define_insn "*movsf_hardfloat"
7650 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7651 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7652 "(gpc_reg_operand (operands[0], SFmode)
7653 || gpc_reg_operand (operands[1], SFmode))
7654 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7657 {l%U1%X1|lwz%U1%X1} %0,%1
7658 {st%U0%X0|stw%U0%X0} %1,%0
7668 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7669 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7671 (define_insn "*movsf_softfloat"
7672 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7673 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7674 "(gpc_reg_operand (operands[0], SFmode)
7675 || gpc_reg_operand (operands[1], SFmode))
7676 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7682 {l%U1%X1|lwz%U1%X1} %0,%1
7683 {st%U0%X0|stw%U0%X0} %1,%0
7690 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7691 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7694 (define_expand "movdf"
7695 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7696 (match_operand:DF 1 "any_operand" ""))]
7698 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7701 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7702 (match_operand:DF 1 "const_int_operand" ""))]
7703 "! TARGET_POWERPC64 && reload_completed
7704 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7705 || (GET_CODE (operands[0]) == SUBREG
7706 && GET_CODE (SUBREG_REG (operands[0])) == REG
7707 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7708 [(set (match_dup 2) (match_dup 4))
7709 (set (match_dup 3) (match_dup 1))]
7712 int endian = (WORDS_BIG_ENDIAN == 0);
7713 HOST_WIDE_INT value = INTVAL (operands[1]);
7715 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7716 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7717 #if HOST_BITS_PER_WIDE_INT == 32
7718 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7720 operands[4] = GEN_INT (value >> 32);
7721 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7726 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7727 (match_operand:DF 1 "const_double_operand" ""))]
7728 "! TARGET_POWERPC64 && reload_completed
7729 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7730 || (GET_CODE (operands[0]) == SUBREG
7731 && GET_CODE (SUBREG_REG (operands[0])) == REG
7732 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7733 [(set (match_dup 2) (match_dup 4))
7734 (set (match_dup 3) (match_dup 5))]
7737 int endian = (WORDS_BIG_ENDIAN == 0);
7741 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7742 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7744 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7745 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7746 operands[4] = gen_int_mode (l[endian], SImode);
7747 operands[5] = gen_int_mode (l[1 - endian], SImode);
7751 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7752 (match_operand:DF 1 "easy_fp_constant" ""))]
7753 "TARGET_POWERPC64 && reload_completed
7754 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7755 || (GET_CODE (operands[0]) == SUBREG
7756 && GET_CODE (SUBREG_REG (operands[0])) == REG
7757 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7758 [(set (match_dup 2) (match_dup 3))]
7761 int endian = (WORDS_BIG_ENDIAN == 0);
7764 #if HOST_BITS_PER_WIDE_INT >= 64
7768 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7769 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7771 operands[2] = gen_lowpart (DImode, operands[0]);
7772 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7773 #if HOST_BITS_PER_WIDE_INT >= 64
7774 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7775 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7777 operands[3] = gen_int_mode (val, DImode);
7779 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7783 ;; Don't have reload use general registers to load a constant. First,
7784 ;; it might not work if the output operand is the equivalent of
7785 ;; a non-offsettable memref, but also it is less efficient than loading
7786 ;; the constant into an FP register, since it will probably be used there.
7787 ;; The "??" is a kludge until we can figure out a more reasonable way
7788 ;; of handling these non-offsettable values.
7789 (define_insn "*movdf_hardfloat32"
7790 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7791 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7792 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7793 && (gpc_reg_operand (operands[0], DFmode)
7794 || gpc_reg_operand (operands[1], DFmode))"
7797 switch (which_alternative)
7802 /* We normally copy the low-numbered register first. However, if
7803 the first register operand 0 is the same as the second register
7804 of operand 1, we must copy in the opposite order. */
7805 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7806 return \"mr %L0,%L1\;mr %0,%1\";
7808 return \"mr %0,%1\;mr %L0,%L1\";
7810 if (GET_CODE (operands[1]) == MEM
7811 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7812 reload_completed || reload_in_progress)
7813 || GET_CODE (XEXP (operands[1], 0)) == REG
7814 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7815 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7816 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7818 /* If the low-address word is used in the address, we must load
7819 it last. Otherwise, load it first. Note that we cannot have
7820 auto-increment in that case since the address register is
7821 known to be dead. */
7822 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7824 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7826 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7832 addreg = find_addr_reg (XEXP (operands[1], 0));
7833 if (refers_to_regno_p (REGNO (operands[0]),
7834 REGNO (operands[0]) + 1,
7837 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7838 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7839 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7840 return \"{lx|lwzx} %0,%1\";
7844 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7845 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7846 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7847 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7852 if (GET_CODE (operands[0]) == MEM
7853 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7854 reload_completed || reload_in_progress)
7855 || GET_CODE (XEXP (operands[0], 0)) == REG
7856 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7857 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7858 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7859 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7864 addreg = find_addr_reg (XEXP (operands[0], 0));
7865 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7866 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7867 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7868 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7872 return \"fmr %0,%1\";
7874 return \"lfd%U1%X1 %0,%1\";
7876 return \"stfd%U0%X0 %1,%0\";
7883 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7884 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7886 (define_insn "*movdf_softfloat32"
7887 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7888 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7889 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7890 && (gpc_reg_operand (operands[0], DFmode)
7891 || gpc_reg_operand (operands[1], DFmode))"
7894 switch (which_alternative)
7899 /* We normally copy the low-numbered register first. However, if
7900 the first register operand 0 is the same as the second register of
7901 operand 1, we must copy in the opposite order. */
7902 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7903 return \"mr %L0,%L1\;mr %0,%1\";
7905 return \"mr %0,%1\;mr %L0,%L1\";
7907 /* If the low-address word is used in the address, we must load
7908 it last. Otherwise, load it first. Note that we cannot have
7909 auto-increment in that case since the address register is
7910 known to be dead. */
7911 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7913 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7915 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7917 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7924 [(set_attr "type" "two,load,store,*,*,*")
7925 (set_attr "length" "8,8,8,8,12,16")])
7927 ; ld/std require word-aligned displacements -> 'Y' constraint.
7928 ; List Y->r and r->Y before r->r for reload.
7929 (define_insn "*movdf_hardfloat64"
7930 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7931 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7932 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7933 && (gpc_reg_operand (operands[0], DFmode)
7934 || gpc_reg_operand (operands[1], DFmode))"
7948 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7949 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7951 (define_insn "*movdf_softfloat64"
7952 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7953 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7954 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7955 && (gpc_reg_operand (operands[0], DFmode)
7956 || gpc_reg_operand (operands[1], DFmode))"
7967 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7968 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7970 (define_expand "movtf"
7971 [(set (match_operand:TF 0 "general_operand" "")
7972 (match_operand:TF 1 "any_operand" ""))]
7973 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7974 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7975 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7977 ; It's important to list the o->f and f->o moves before f->f because
7978 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7979 ; which doesn't make progress. Likewise r->Y must be before r->r.
7980 (define_insn_and_split "*movtf_internal"
7981 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7982 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7983 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7984 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7985 && (gpc_reg_operand (operands[0], TFmode)
7986 || gpc_reg_operand (operands[1], TFmode))"
7988 "&& reload_completed"
7990 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7991 [(set_attr "length" "8,8,8,20,20,16")])
7993 (define_expand "extenddftf2"
7994 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7995 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7996 (use (match_dup 2))])]
7997 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7998 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8000 operands[2] = CONST0_RTX (DFmode);
8003 (define_insn_and_split "*extenddftf2_internal"
8004 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8005 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8006 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8007 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8008 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8010 "&& reload_completed"
8013 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8014 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8015 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8017 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8022 (define_expand "extendsftf2"
8023 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8024 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8025 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8026 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8028 rtx tmp = gen_reg_rtx (DFmode);
8029 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8030 emit_insn (gen_extenddftf2 (operands[0], tmp));
8034 (define_expand "trunctfdf2"
8035 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8036 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8037 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8038 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8041 (define_insn_and_split "trunctfdf2_internal1"
8042 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8043 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8044 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8045 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8049 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8052 emit_note (NOTE_INSN_DELETED);
8055 [(set_attr "type" "fp")])
8057 (define_insn "trunctfdf2_internal2"
8058 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8059 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8060 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8061 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8063 [(set_attr "type" "fp")])
8065 (define_insn_and_split "trunctfsf2"
8066 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8067 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8068 (clobber (match_scratch:DF 2 "=f"))]
8069 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8070 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8072 "&& reload_completed"
8074 (float_truncate:DF (match_dup 1)))
8076 (float_truncate:SF (match_dup 2)))]
8079 (define_expand "floatsitf2"
8080 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8081 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8082 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8083 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8085 rtx tmp = gen_reg_rtx (DFmode);
8086 expand_float (tmp, operands[1], false);
8087 emit_insn (gen_extenddftf2 (operands[0], tmp));
8091 ; fadd, but rounding towards zero.
8092 ; This is probably not the optimal code sequence.
8093 (define_insn "fix_trunc_helper"
8094 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8095 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8096 UNSPEC_FIX_TRUNC_TF))
8097 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8098 "TARGET_HARD_FLOAT && TARGET_FPRS"
8099 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8100 [(set_attr "type" "fp")
8101 (set_attr "length" "20")])
8103 (define_expand "fix_trunctfsi2"
8104 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8105 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8106 (clobber (match_dup 2))
8107 (clobber (match_dup 3))
8108 (clobber (match_dup 4))
8109 (clobber (match_dup 5))])]
8110 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8111 && (TARGET_POWER2 || TARGET_POWERPC)
8112 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8114 operands[2] = gen_reg_rtx (DFmode);
8115 operands[3] = gen_reg_rtx (DFmode);
8116 operands[4] = gen_reg_rtx (DImode);
8117 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8120 (define_insn_and_split "*fix_trunctfsi2_internal"
8121 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8122 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8123 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8124 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8125 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8126 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8127 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8128 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8130 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8134 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8136 gcc_assert (MEM_P (operands[5]));
8137 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8139 emit_insn (gen_fctiwz (operands[4], operands[2]));
8140 emit_move_insn (operands[5], operands[4]);
8141 emit_move_insn (operands[0], lowword);
8145 (define_insn "negtf2"
8146 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8147 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8148 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8149 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8152 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8153 return \"fneg %L0,%L1\;fneg %0,%1\";
8155 return \"fneg %0,%1\;fneg %L0,%L1\";
8157 [(set_attr "type" "fp")
8158 (set_attr "length" "8")])
8160 (define_expand "abstf2"
8161 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8162 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8163 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8164 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8167 rtx label = gen_label_rtx ();
8168 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8173 (define_expand "abstf2_internal"
8174 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8175 (match_operand:TF 1 "gpc_reg_operand" "f"))
8176 (set (match_dup 3) (match_dup 5))
8177 (set (match_dup 5) (abs:DF (match_dup 5)))
8178 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8179 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8180 (label_ref (match_operand 2 "" ""))
8182 (set (match_dup 6) (neg:DF (match_dup 6)))]
8183 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8184 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8187 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8188 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8189 operands[3] = gen_reg_rtx (DFmode);
8190 operands[4] = gen_reg_rtx (CCFPmode);
8191 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8192 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8195 ;; Next come the multi-word integer load and store and the load and store
8197 (define_expand "movdi"
8198 [(set (match_operand:DI 0 "general_operand" "")
8199 (match_operand:DI 1 "any_operand" ""))]
8201 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8203 ; List r->r after r->"o<>", otherwise reload will try to reload a
8204 ; non-offsettable address by using r->r which won't make progress.
8205 (define_insn "*movdi_internal32"
8206 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8207 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8209 && (gpc_reg_operand (operands[0], DImode)
8210 || gpc_reg_operand (operands[1], DImode))"
8219 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8222 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8223 (match_operand:DI 1 "const_int_operand" ""))]
8224 "! TARGET_POWERPC64 && reload_completed"
8225 [(set (match_dup 2) (match_dup 4))
8226 (set (match_dup 3) (match_dup 1))]
8229 HOST_WIDE_INT value = INTVAL (operands[1]);
8230 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8232 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8234 #if HOST_BITS_PER_WIDE_INT == 32
8235 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8237 operands[4] = GEN_INT (value >> 32);
8238 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8243 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8244 (match_operand:DI 1 "input_operand" ""))]
8245 "reload_completed && !TARGET_POWERPC64
8246 && gpr_or_gpr_p (operands[0], operands[1])"
8248 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8250 (define_insn "*movdi_internal64"
8251 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8252 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8254 && (gpc_reg_operand (operands[0], DImode)
8255 || gpc_reg_operand (operands[1], DImode))"
8270 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8271 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8273 ;; immediate value valid for a single instruction hiding in a const_double
8275 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8276 (match_operand:DI 1 "const_double_operand" "F"))]
8277 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8278 && GET_CODE (operands[1]) == CONST_DOUBLE
8279 && num_insns_constant (operands[1], DImode) == 1"
8282 return ((unsigned HOST_WIDE_INT)
8283 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8284 ? \"li %0,%1\" : \"lis %0,%v1\";
8287 ;; Generate all one-bits and clear left or right.
8288 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8291 (match_operand:DI 1 "mask64_operand" ""))]
8292 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8293 [(set (match_dup 0) (const_int -1))
8295 (and:DI (rotate:DI (match_dup 0)
8300 ;; Split a load of a large constant into the appropriate five-instruction
8301 ;; sequence. Handle anything in a constant number of insns.
8302 ;; When non-easy constants can go in the TOC, this should use
8303 ;; easy_fp_constant predicate.
8305 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8306 (match_operand:DI 1 "const_int_operand" ""))]
8307 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8308 [(set (match_dup 0) (match_dup 2))
8309 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8311 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8313 if (tem == operands[0])
8320 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8321 (match_operand:DI 1 "const_double_operand" ""))]
8322 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8323 [(set (match_dup 0) (match_dup 2))
8324 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8326 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8328 if (tem == operands[0])
8334 (define_insn "*movdi_internal2"
8335 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8336 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8338 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8344 [(set_attr "type" "cmp,compare,cmp")
8345 (set_attr "length" "4,4,8")])
8348 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8349 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8351 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8352 "TARGET_POWERPC64 && reload_completed"
8353 [(set (match_dup 0) (match_dup 1))
8355 (compare:CC (match_dup 0)
8359 ;; TImode is similar, except that we usually want to compute the address into
8360 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8361 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8362 (define_expand "movti"
8363 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8364 (match_operand:TI 1 "general_operand" ""))
8365 (clobber (scratch:SI))])]
8367 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8369 ;; We say that MQ is clobbered in the last alternative because the first
8370 ;; alternative would never get used otherwise since it would need a reload
8371 ;; while the 2nd alternative would not. We put memory cases first so they
8372 ;; are preferred. Otherwise, we'd try to reload the output instead of
8373 ;; giving the SCRATCH mq.
8375 (define_insn "*movti_power"
8376 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8377 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8378 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8379 "TARGET_POWER && ! TARGET_POWERPC64
8380 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8383 switch (which_alternative)
8390 return \"{stsi|stswi} %1,%P0,16\";
8395 /* If the address is not used in the output, we can use lsi. Otherwise,
8396 fall through to generating four loads. */
8398 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8399 return \"{lsi|lswi} %0,%P1,16\";
8400 /* ... fall through ... */
8406 [(set_attr "type" "store,store,*,load,load,*")])
8408 (define_insn "*movti_string"
8409 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8410 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8411 "! TARGET_POWER && ! TARGET_POWERPC64
8412 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8415 switch (which_alternative)
8421 return \"{stsi|stswi} %1,%P0,16\";
8426 /* If the address is not used in the output, we can use lsi. Otherwise,
8427 fall through to generating four loads. */
8429 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8430 return \"{lsi|lswi} %0,%P1,16\";
8431 /* ... fall through ... */
8437 [(set_attr "type" "store,store,*,load,load,*")])
8439 (define_insn "*movti_ppc64"
8440 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8441 (match_operand:TI 1 "input_operand" "r,r,m"))]
8442 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8443 || gpc_reg_operand (operands[1], TImode))"
8445 [(set_attr "type" "*,load,store")])
8448 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8449 (match_operand:TI 1 "const_double_operand" ""))]
8451 [(set (match_dup 2) (match_dup 4))
8452 (set (match_dup 3) (match_dup 5))]
8455 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8457 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8459 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8461 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8462 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8464 else if (GET_CODE (operands[1]) == CONST_INT)
8466 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8467 operands[5] = operands[1];
8474 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8475 (match_operand:TI 1 "input_operand" ""))]
8477 && gpr_or_gpr_p (operands[0], operands[1])"
8479 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8481 (define_expand "load_multiple"
8482 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8483 (match_operand:SI 1 "" ""))
8484 (use (match_operand:SI 2 "" ""))])]
8485 "TARGET_STRING && !TARGET_POWERPC64"
8493 /* Support only loading a constant number of fixed-point registers from
8494 memory and only bother with this if more than two; the machine
8495 doesn't support more than eight. */
8496 if (GET_CODE (operands[2]) != CONST_INT
8497 || INTVAL (operands[2]) <= 2
8498 || INTVAL (operands[2]) > 8
8499 || GET_CODE (operands[1]) != MEM
8500 || GET_CODE (operands[0]) != REG
8501 || REGNO (operands[0]) >= 32)
8504 count = INTVAL (operands[2]);
8505 regno = REGNO (operands[0]);
8507 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8508 op1 = replace_equiv_address (operands[1],
8509 force_reg (SImode, XEXP (operands[1], 0)));
8511 for (i = 0; i < count; i++)
8512 XVECEXP (operands[3], 0, i)
8513 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8514 adjust_address_nv (op1, SImode, i * 4));
8517 (define_insn "*ldmsi8"
8518 [(match_parallel 0 "load_multiple_operation"
8519 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8520 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8521 (set (match_operand:SI 3 "gpc_reg_operand" "")
8522 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8523 (set (match_operand:SI 4 "gpc_reg_operand" "")
8524 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8525 (set (match_operand:SI 5 "gpc_reg_operand" "")
8526 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8527 (set (match_operand:SI 6 "gpc_reg_operand" "")
8528 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8529 (set (match_operand:SI 7 "gpc_reg_operand" "")
8530 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8531 (set (match_operand:SI 8 "gpc_reg_operand" "")
8532 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8533 (set (match_operand:SI 9 "gpc_reg_operand" "")
8534 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8535 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8537 { return rs6000_output_load_multiple (operands); }"
8538 [(set_attr "type" "load")
8539 (set_attr "length" "32")])
8541 (define_insn "*ldmsi7"
8542 [(match_parallel 0 "load_multiple_operation"
8543 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8544 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8545 (set (match_operand:SI 3 "gpc_reg_operand" "")
8546 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8547 (set (match_operand:SI 4 "gpc_reg_operand" "")
8548 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8549 (set (match_operand:SI 5 "gpc_reg_operand" "")
8550 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8551 (set (match_operand:SI 6 "gpc_reg_operand" "")
8552 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8553 (set (match_operand:SI 7 "gpc_reg_operand" "")
8554 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8555 (set (match_operand:SI 8 "gpc_reg_operand" "")
8556 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8557 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8559 { return rs6000_output_load_multiple (operands); }"
8560 [(set_attr "type" "load")
8561 (set_attr "length" "32")])
8563 (define_insn "*ldmsi6"
8564 [(match_parallel 0 "load_multiple_operation"
8565 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8566 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8567 (set (match_operand:SI 3 "gpc_reg_operand" "")
8568 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8569 (set (match_operand:SI 4 "gpc_reg_operand" "")
8570 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8571 (set (match_operand:SI 5 "gpc_reg_operand" "")
8572 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8573 (set (match_operand:SI 6 "gpc_reg_operand" "")
8574 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8575 (set (match_operand:SI 7 "gpc_reg_operand" "")
8576 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8577 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8579 { return rs6000_output_load_multiple (operands); }"
8580 [(set_attr "type" "load")
8581 (set_attr "length" "32")])
8583 (define_insn "*ldmsi5"
8584 [(match_parallel 0 "load_multiple_operation"
8585 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8586 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8587 (set (match_operand:SI 3 "gpc_reg_operand" "")
8588 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8589 (set (match_operand:SI 4 "gpc_reg_operand" "")
8590 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8591 (set (match_operand:SI 5 "gpc_reg_operand" "")
8592 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8593 (set (match_operand:SI 6 "gpc_reg_operand" "")
8594 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8595 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8597 { return rs6000_output_load_multiple (operands); }"
8598 [(set_attr "type" "load")
8599 (set_attr "length" "32")])
8601 (define_insn "*ldmsi4"
8602 [(match_parallel 0 "load_multiple_operation"
8603 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8604 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8605 (set (match_operand:SI 3 "gpc_reg_operand" "")
8606 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8607 (set (match_operand:SI 4 "gpc_reg_operand" "")
8608 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8609 (set (match_operand:SI 5 "gpc_reg_operand" "")
8610 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8611 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8613 { return rs6000_output_load_multiple (operands); }"
8614 [(set_attr "type" "load")
8615 (set_attr "length" "32")])
8617 (define_insn "*ldmsi3"
8618 [(match_parallel 0 "load_multiple_operation"
8619 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8620 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8621 (set (match_operand:SI 3 "gpc_reg_operand" "")
8622 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8623 (set (match_operand:SI 4 "gpc_reg_operand" "")
8624 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8625 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8627 { return rs6000_output_load_multiple (operands); }"
8628 [(set_attr "type" "load")
8629 (set_attr "length" "32")])
8631 (define_expand "store_multiple"
8632 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8633 (match_operand:SI 1 "" ""))
8634 (clobber (scratch:SI))
8635 (use (match_operand:SI 2 "" ""))])]
8636 "TARGET_STRING && !TARGET_POWERPC64"
8645 /* Support only storing a constant number of fixed-point registers to
8646 memory and only bother with this if more than two; the machine
8647 doesn't support more than eight. */
8648 if (GET_CODE (operands[2]) != CONST_INT
8649 || INTVAL (operands[2]) <= 2
8650 || INTVAL (operands[2]) > 8
8651 || GET_CODE (operands[0]) != MEM
8652 || GET_CODE (operands[1]) != REG
8653 || REGNO (operands[1]) >= 32)
8656 count = INTVAL (operands[2]);
8657 regno = REGNO (operands[1]);
8659 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8660 to = force_reg (SImode, XEXP (operands[0], 0));
8661 op0 = replace_equiv_address (operands[0], to);
8663 XVECEXP (operands[3], 0, 0)
8664 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8665 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8666 gen_rtx_SCRATCH (SImode));
8668 for (i = 1; i < count; i++)
8669 XVECEXP (operands[3], 0, i + 1)
8670 = gen_rtx_SET (VOIDmode,
8671 adjust_address_nv (op0, SImode, i * 4),
8672 gen_rtx_REG (SImode, regno + i));
8675 (define_insn "*store_multiple_power"
8676 [(match_parallel 0 "store_multiple_operation"
8677 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8678 (match_operand:SI 2 "gpc_reg_operand" "r"))
8679 (clobber (match_scratch:SI 3 "=q"))])]
8680 "TARGET_STRING && TARGET_POWER"
8681 "{stsi|stswi} %2,%P1,%O0"
8682 [(set_attr "type" "store")])
8684 (define_insn "*stmsi8"
8685 [(match_parallel 0 "store_multiple_operation"
8686 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8687 (match_operand:SI 2 "gpc_reg_operand" "r"))
8688 (clobber (match_scratch:SI 3 "X"))
8689 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8690 (match_operand:SI 4 "gpc_reg_operand" "r"))
8691 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8692 (match_operand:SI 5 "gpc_reg_operand" "r"))
8693 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8694 (match_operand:SI 6 "gpc_reg_operand" "r"))
8695 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8696 (match_operand:SI 7 "gpc_reg_operand" "r"))
8697 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8698 (match_operand:SI 8 "gpc_reg_operand" "r"))
8699 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8700 (match_operand:SI 9 "gpc_reg_operand" "r"))
8701 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8702 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8703 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8704 "{stsi|stswi} %2,%1,%O0"
8705 [(set_attr "type" "store")])
8707 (define_insn "*stmsi7"
8708 [(match_parallel 0 "store_multiple_operation"
8709 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8710 (match_operand:SI 2 "gpc_reg_operand" "r"))
8711 (clobber (match_scratch:SI 3 "X"))
8712 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8713 (match_operand:SI 4 "gpc_reg_operand" "r"))
8714 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8715 (match_operand:SI 5 "gpc_reg_operand" "r"))
8716 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8717 (match_operand:SI 6 "gpc_reg_operand" "r"))
8718 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8719 (match_operand:SI 7 "gpc_reg_operand" "r"))
8720 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8721 (match_operand:SI 8 "gpc_reg_operand" "r"))
8722 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8723 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8724 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8725 "{stsi|stswi} %2,%1,%O0"
8726 [(set_attr "type" "store")])
8728 (define_insn "*stmsi6"
8729 [(match_parallel 0 "store_multiple_operation"
8730 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8731 (match_operand:SI 2 "gpc_reg_operand" "r"))
8732 (clobber (match_scratch:SI 3 "X"))
8733 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8734 (match_operand:SI 4 "gpc_reg_operand" "r"))
8735 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8736 (match_operand:SI 5 "gpc_reg_operand" "r"))
8737 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8738 (match_operand:SI 6 "gpc_reg_operand" "r"))
8739 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8740 (match_operand:SI 7 "gpc_reg_operand" "r"))
8741 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8742 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8743 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8744 "{stsi|stswi} %2,%1,%O0"
8745 [(set_attr "type" "store")])
8747 (define_insn "*stmsi5"
8748 [(match_parallel 0 "store_multiple_operation"
8749 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8750 (match_operand:SI 2 "gpc_reg_operand" "r"))
8751 (clobber (match_scratch:SI 3 "X"))
8752 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8753 (match_operand:SI 4 "gpc_reg_operand" "r"))
8754 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8755 (match_operand:SI 5 "gpc_reg_operand" "r"))
8756 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8757 (match_operand:SI 6 "gpc_reg_operand" "r"))
8758 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8759 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8760 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8761 "{stsi|stswi} %2,%1,%O0"
8762 [(set_attr "type" "store")])
8764 (define_insn "*stmsi4"
8765 [(match_parallel 0 "store_multiple_operation"
8766 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8767 (match_operand:SI 2 "gpc_reg_operand" "r"))
8768 (clobber (match_scratch:SI 3 "X"))
8769 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8770 (match_operand:SI 4 "gpc_reg_operand" "r"))
8771 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8772 (match_operand:SI 5 "gpc_reg_operand" "r"))
8773 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8774 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8775 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8776 "{stsi|stswi} %2,%1,%O0"
8777 [(set_attr "type" "store")])
8779 (define_insn "*stmsi3"
8780 [(match_parallel 0 "store_multiple_operation"
8781 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8782 (match_operand:SI 2 "gpc_reg_operand" "r"))
8783 (clobber (match_scratch:SI 3 "X"))
8784 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8785 (match_operand:SI 4 "gpc_reg_operand" "r"))
8786 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8787 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8788 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8789 "{stsi|stswi} %2,%1,%O0"
8790 [(set_attr "type" "store")])
8792 (define_expand "clrmemsi"
8793 [(parallel [(set (match_operand:BLK 0 "" "")
8795 (use (match_operand:SI 1 "" ""))
8796 (use (match_operand:SI 2 "" ""))])]
8800 if (expand_block_clear (operands))
8806 ;; String/block move insn.
8807 ;; Argument 0 is the destination
8808 ;; Argument 1 is the source
8809 ;; Argument 2 is the length
8810 ;; Argument 3 is the alignment
8812 (define_expand "movmemsi"
8813 [(parallel [(set (match_operand:BLK 0 "" "")
8814 (match_operand:BLK 1 "" ""))
8815 (use (match_operand:SI 2 "" ""))
8816 (use (match_operand:SI 3 "" ""))])]
8820 if (expand_block_move (operands))
8826 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8827 ;; register allocator doesn't have a clue about allocating 8 word registers.
8828 ;; rD/rS = r5 is preferred, efficient form.
8829 (define_expand "movmemsi_8reg"
8830 [(parallel [(set (match_operand 0 "" "")
8831 (match_operand 1 "" ""))
8832 (use (match_operand 2 "" ""))
8833 (use (match_operand 3 "" ""))
8834 (clobber (reg:SI 5))
8835 (clobber (reg:SI 6))
8836 (clobber (reg:SI 7))
8837 (clobber (reg:SI 8))
8838 (clobber (reg:SI 9))
8839 (clobber (reg:SI 10))
8840 (clobber (reg:SI 11))
8841 (clobber (reg:SI 12))
8842 (clobber (match_scratch:SI 4 ""))])]
8847 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8848 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8849 (use (match_operand:SI 2 "immediate_operand" "i"))
8850 (use (match_operand:SI 3 "immediate_operand" "i"))
8851 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8852 (clobber (reg:SI 6))
8853 (clobber (reg:SI 7))
8854 (clobber (reg:SI 8))
8855 (clobber (reg:SI 9))
8856 (clobber (reg:SI 10))
8857 (clobber (reg:SI 11))
8858 (clobber (reg:SI 12))
8859 (clobber (match_scratch:SI 5 "=q"))]
8860 "TARGET_STRING && TARGET_POWER
8861 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8862 || INTVAL (operands[2]) == 0)
8863 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8864 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8865 && REGNO (operands[4]) == 5"
8866 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8867 [(set_attr "type" "load")
8868 (set_attr "length" "8")])
8871 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8872 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8873 (use (match_operand:SI 2 "immediate_operand" "i"))
8874 (use (match_operand:SI 3 "immediate_operand" "i"))
8875 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8876 (clobber (reg:SI 6))
8877 (clobber (reg:SI 7))
8878 (clobber (reg:SI 8))
8879 (clobber (reg:SI 9))
8880 (clobber (reg:SI 10))
8881 (clobber (reg:SI 11))
8882 (clobber (reg:SI 12))
8883 (clobber (match_scratch:SI 5 "X"))]
8884 "TARGET_STRING && ! TARGET_POWER
8885 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8886 || INTVAL (operands[2]) == 0)
8887 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8888 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8889 && REGNO (operands[4]) == 5"
8890 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8891 [(set_attr "type" "load")
8892 (set_attr "length" "8")])
8895 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8896 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8897 (use (match_operand:SI 2 "immediate_operand" "i"))
8898 (use (match_operand:SI 3 "immediate_operand" "i"))
8899 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8900 (clobber (reg:SI 6))
8901 (clobber (reg:SI 7))
8902 (clobber (reg:SI 8))
8903 (clobber (reg:SI 9))
8904 (clobber (reg:SI 10))
8905 (clobber (reg:SI 11))
8906 (clobber (reg:SI 12))
8907 (clobber (match_scratch:SI 5 "X"))]
8908 "TARGET_STRING && TARGET_POWERPC64
8909 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8910 || INTVAL (operands[2]) == 0)
8911 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8912 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8913 && REGNO (operands[4]) == 5"
8914 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8915 [(set_attr "type" "load")
8916 (set_attr "length" "8")])
8918 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8919 ;; register allocator doesn't have a clue about allocating 6 word registers.
8920 ;; rD/rS = r5 is preferred, efficient form.
8921 (define_expand "movmemsi_6reg"
8922 [(parallel [(set (match_operand 0 "" "")
8923 (match_operand 1 "" ""))
8924 (use (match_operand 2 "" ""))
8925 (use (match_operand 3 "" ""))
8926 (clobber (reg:SI 5))
8927 (clobber (reg:SI 6))
8928 (clobber (reg:SI 7))
8929 (clobber (reg:SI 8))
8930 (clobber (reg:SI 9))
8931 (clobber (reg:SI 10))
8932 (clobber (match_scratch:SI 4 ""))])]
8937 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8938 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8939 (use (match_operand:SI 2 "immediate_operand" "i"))
8940 (use (match_operand:SI 3 "immediate_operand" "i"))
8941 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8942 (clobber (reg:SI 6))
8943 (clobber (reg:SI 7))
8944 (clobber (reg:SI 8))
8945 (clobber (reg:SI 9))
8946 (clobber (reg:SI 10))
8947 (clobber (match_scratch:SI 5 "=q"))]
8948 "TARGET_STRING && TARGET_POWER
8949 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8950 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8951 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8952 && REGNO (operands[4]) == 5"
8953 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8954 [(set_attr "type" "load")
8955 (set_attr "length" "8")])
8958 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8959 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8960 (use (match_operand:SI 2 "immediate_operand" "i"))
8961 (use (match_operand:SI 3 "immediate_operand" "i"))
8962 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8963 (clobber (reg:SI 6))
8964 (clobber (reg:SI 7))
8965 (clobber (reg:SI 8))
8966 (clobber (reg:SI 9))
8967 (clobber (reg:SI 10))
8968 (clobber (match_scratch:SI 5 "X"))]
8969 "TARGET_STRING && ! TARGET_POWER
8970 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8971 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8972 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8973 && REGNO (operands[4]) == 5"
8974 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8975 [(set_attr "type" "load")
8976 (set_attr "length" "8")])
8979 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8980 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8981 (use (match_operand:SI 2 "immediate_operand" "i"))
8982 (use (match_operand:SI 3 "immediate_operand" "i"))
8983 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8984 (clobber (reg:SI 6))
8985 (clobber (reg:SI 7))
8986 (clobber (reg:SI 8))
8987 (clobber (reg:SI 9))
8988 (clobber (reg:SI 10))
8989 (clobber (match_scratch:SI 5 "X"))]
8990 "TARGET_STRING && TARGET_POWERPC64
8991 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8992 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8993 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8994 && REGNO (operands[4]) == 5"
8995 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8996 [(set_attr "type" "load")
8997 (set_attr "length" "8")])
8999 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9000 ;; problems with TImode.
9001 ;; rD/rS = r5 is preferred, efficient form.
9002 (define_expand "movmemsi_4reg"
9003 [(parallel [(set (match_operand 0 "" "")
9004 (match_operand 1 "" ""))
9005 (use (match_operand 2 "" ""))
9006 (use (match_operand 3 "" ""))
9007 (clobber (reg:SI 5))
9008 (clobber (reg:SI 6))
9009 (clobber (reg:SI 7))
9010 (clobber (reg:SI 8))
9011 (clobber (match_scratch:SI 4 ""))])]
9016 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9017 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9018 (use (match_operand:SI 2 "immediate_operand" "i"))
9019 (use (match_operand:SI 3 "immediate_operand" "i"))
9020 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9021 (clobber (reg:SI 6))
9022 (clobber (reg:SI 7))
9023 (clobber (reg:SI 8))
9024 (clobber (match_scratch:SI 5 "=q"))]
9025 "TARGET_STRING && TARGET_POWER
9026 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9027 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9028 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9029 && REGNO (operands[4]) == 5"
9030 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9031 [(set_attr "type" "load")
9032 (set_attr "length" "8")])
9035 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9036 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9037 (use (match_operand:SI 2 "immediate_operand" "i"))
9038 (use (match_operand:SI 3 "immediate_operand" "i"))
9039 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9040 (clobber (reg:SI 6))
9041 (clobber (reg:SI 7))
9042 (clobber (reg:SI 8))
9043 (clobber (match_scratch:SI 5 "X"))]
9044 "TARGET_STRING && ! TARGET_POWER
9045 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9046 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9047 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9048 && REGNO (operands[4]) == 5"
9049 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9050 [(set_attr "type" "load")
9051 (set_attr "length" "8")])
9054 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9055 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9056 (use (match_operand:SI 2 "immediate_operand" "i"))
9057 (use (match_operand:SI 3 "immediate_operand" "i"))
9058 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9059 (clobber (reg:SI 6))
9060 (clobber (reg:SI 7))
9061 (clobber (reg:SI 8))
9062 (clobber (match_scratch:SI 5 "X"))]
9063 "TARGET_STRING && TARGET_POWERPC64
9064 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9065 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9066 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9067 && REGNO (operands[4]) == 5"
9068 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9069 [(set_attr "type" "load")
9070 (set_attr "length" "8")])
9072 ;; Move up to 8 bytes at a time.
9073 (define_expand "movmemsi_2reg"
9074 [(parallel [(set (match_operand 0 "" "")
9075 (match_operand 1 "" ""))
9076 (use (match_operand 2 "" ""))
9077 (use (match_operand 3 "" ""))
9078 (clobber (match_scratch:DI 4 ""))
9079 (clobber (match_scratch:SI 5 ""))])]
9080 "TARGET_STRING && ! TARGET_POWERPC64"
9084 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9085 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9086 (use (match_operand:SI 2 "immediate_operand" "i"))
9087 (use (match_operand:SI 3 "immediate_operand" "i"))
9088 (clobber (match_scratch:DI 4 "=&r"))
9089 (clobber (match_scratch:SI 5 "=q"))]
9090 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9091 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9092 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9093 [(set_attr "type" "load")
9094 (set_attr "length" "8")])
9097 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9098 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9099 (use (match_operand:SI 2 "immediate_operand" "i"))
9100 (use (match_operand:SI 3 "immediate_operand" "i"))
9101 (clobber (match_scratch:DI 4 "=&r"))
9102 (clobber (match_scratch:SI 5 "X"))]
9103 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9104 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9105 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9106 [(set_attr "type" "load")
9107 (set_attr "length" "8")])
9109 ;; Move up to 4 bytes at a time.
9110 (define_expand "movmemsi_1reg"
9111 [(parallel [(set (match_operand 0 "" "")
9112 (match_operand 1 "" ""))
9113 (use (match_operand 2 "" ""))
9114 (use (match_operand 3 "" ""))
9115 (clobber (match_scratch:SI 4 ""))
9116 (clobber (match_scratch:SI 5 ""))])]
9121 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9122 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9123 (use (match_operand:SI 2 "immediate_operand" "i"))
9124 (use (match_operand:SI 3 "immediate_operand" "i"))
9125 (clobber (match_scratch:SI 4 "=&r"))
9126 (clobber (match_scratch:SI 5 "=q"))]
9127 "TARGET_STRING && TARGET_POWER
9128 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9129 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9130 [(set_attr "type" "load")
9131 (set_attr "length" "8")])
9134 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9135 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9136 (use (match_operand:SI 2 "immediate_operand" "i"))
9137 (use (match_operand:SI 3 "immediate_operand" "i"))
9138 (clobber (match_scratch:SI 4 "=&r"))
9139 (clobber (match_scratch:SI 5 "X"))]
9140 "TARGET_STRING && ! TARGET_POWER
9141 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9142 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9143 [(set_attr "type" "load")
9144 (set_attr "length" "8")])
9147 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9148 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9149 (use (match_operand:SI 2 "immediate_operand" "i"))
9150 (use (match_operand:SI 3 "immediate_operand" "i"))
9151 (clobber (match_scratch:SI 4 "=&r"))
9152 (clobber (match_scratch:SI 5 "X"))]
9153 "TARGET_STRING && TARGET_POWERPC64
9154 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9155 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9156 [(set_attr "type" "load")
9157 (set_attr "length" "8")])
9160 ;; Define insns that do load or store with update. Some of these we can
9161 ;; get by using pre-decrement or pre-increment, but the hardware can also
9162 ;; do cases where the increment is not the size of the object.
9164 ;; In all these cases, we use operands 0 and 1 for the register being
9165 ;; incremented because those are the operands that local-alloc will
9166 ;; tie and these are the pair most likely to be tieable (and the ones
9167 ;; that will benefit the most).
9169 (define_insn "*movdi_update1"
9170 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9171 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9172 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9173 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9174 (plus:DI (match_dup 1) (match_dup 2)))]
9175 "TARGET_POWERPC64 && TARGET_UPDATE"
9179 [(set_attr "type" "load_ux,load_u")])
9181 (define_insn "movdi_<mode>_update"
9182 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9183 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9184 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9185 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9186 (plus:P (match_dup 1) (match_dup 2)))]
9187 "TARGET_POWERPC64 && TARGET_UPDATE"
9191 [(set_attr "type" "store_ux,store_u")])
9193 (define_insn "*movsi_update1"
9194 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9195 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9196 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9197 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9198 (plus:SI (match_dup 1) (match_dup 2)))]
9201 {lux|lwzux} %3,%0,%2
9202 {lu|lwzu} %3,%2(%0)"
9203 [(set_attr "type" "load_ux,load_u")])
9205 (define_insn "*movsi_update2"
9206 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9208 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9209 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9210 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9211 (plus:DI (match_dup 1) (match_dup 2)))]
9214 [(set_attr "type" "load_ext_ux")])
9216 (define_insn "movsi_update"
9217 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9218 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9219 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9220 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9221 (plus:SI (match_dup 1) (match_dup 2)))]
9224 {stux|stwux} %3,%0,%2
9225 {stu|stwu} %3,%2(%0)"
9226 [(set_attr "type" "store_ux,store_u")])
9228 (define_insn "*movhi_update1"
9229 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9230 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9231 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9232 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9233 (plus:SI (match_dup 1) (match_dup 2)))]
9238 [(set_attr "type" "load_ux,load_u")])
9240 (define_insn "*movhi_update2"
9241 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9243 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9244 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9245 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9246 (plus:SI (match_dup 1) (match_dup 2)))]
9251 [(set_attr "type" "load_ux,load_u")])
9253 (define_insn "*movhi_update3"
9254 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9256 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9257 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9258 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9259 (plus:SI (match_dup 1) (match_dup 2)))]
9264 [(set_attr "type" "load_ext_ux,load_ext_u")])
9266 (define_insn "*movhi_update4"
9267 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9269 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9270 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9271 (plus:SI (match_dup 1) (match_dup 2)))]
9276 [(set_attr "type" "store_ux,store_u")])
9278 (define_insn "*movqi_update1"
9279 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9280 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9281 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9282 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9283 (plus:SI (match_dup 1) (match_dup 2)))]
9288 [(set_attr "type" "load_ux,load_u")])
9290 (define_insn "*movqi_update2"
9291 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9293 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9294 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9295 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9296 (plus:SI (match_dup 1) (match_dup 2)))]
9301 [(set_attr "type" "load_ux,load_u")])
9303 (define_insn "*movqi_update3"
9304 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9305 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9306 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9307 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9308 (plus:SI (match_dup 1) (match_dup 2)))]
9313 [(set_attr "type" "store_ux,store_u")])
9315 (define_insn "*movsf_update1"
9316 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9317 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9318 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9319 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9320 (plus:SI (match_dup 1) (match_dup 2)))]
9321 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9325 [(set_attr "type" "fpload_ux,fpload_u")])
9327 (define_insn "*movsf_update2"
9328 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9329 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9330 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9331 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9332 (plus:SI (match_dup 1) (match_dup 2)))]
9333 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9337 [(set_attr "type" "fpstore_ux,fpstore_u")])
9339 (define_insn "*movsf_update3"
9340 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9341 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9342 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9343 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9344 (plus:SI (match_dup 1) (match_dup 2)))]
9345 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9347 {lux|lwzux} %3,%0,%2
9348 {lu|lwzu} %3,%2(%0)"
9349 [(set_attr "type" "load_ux,load_u")])
9351 (define_insn "*movsf_update4"
9352 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9353 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9354 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9355 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9356 (plus:SI (match_dup 1) (match_dup 2)))]
9357 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9359 {stux|stwux} %3,%0,%2
9360 {stu|stwu} %3,%2(%0)"
9361 [(set_attr "type" "store_ux,store_u")])
9363 (define_insn "*movdf_update1"
9364 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9365 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9366 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9367 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9368 (plus:SI (match_dup 1) (match_dup 2)))]
9369 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9373 [(set_attr "type" "fpload_ux,fpload_u")])
9375 (define_insn "*movdf_update2"
9376 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9377 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9378 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9379 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9380 (plus:SI (match_dup 1) (match_dup 2)))]
9381 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9385 [(set_attr "type" "fpstore_ux,fpstore_u")])
9387 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9389 (define_insn "*lfq_power2"
9390 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9391 (match_operand:TF 1 "memory_operand" ""))]
9393 && TARGET_HARD_FLOAT && TARGET_FPRS"
9397 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9398 (match_operand:DF 1 "memory_operand" ""))
9399 (set (match_operand:DF 2 "gpc_reg_operand" "")
9400 (match_operand:DF 3 "memory_operand" ""))]
9402 && TARGET_HARD_FLOAT && TARGET_FPRS
9403 && registers_ok_for_quad_peep (operands[0], operands[2])
9404 && mems_ok_for_quad_peep (operands[1], operands[3])"
9407 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9408 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9410 (define_insn "*stfq_power2"
9411 [(set (match_operand:TF 0 "memory_operand" "")
9412 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9414 && TARGET_HARD_FLOAT && TARGET_FPRS"
9419 [(set (match_operand:DF 0 "memory_operand" "")
9420 (match_operand:DF 1 "gpc_reg_operand" ""))
9421 (set (match_operand:DF 2 "memory_operand" "")
9422 (match_operand:DF 3 "gpc_reg_operand" ""))]
9424 && TARGET_HARD_FLOAT && TARGET_FPRS
9425 && registers_ok_for_quad_peep (operands[1], operands[3])
9426 && mems_ok_for_quad_peep (operands[0], operands[2])"
9429 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9430 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9432 ;; after inserting conditional returns we can sometimes have
9433 ;; unnecessary register moves. Unfortunately we cannot have a
9434 ;; modeless peephole here, because some single SImode sets have early
9435 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9436 ;; sequences, using get_attr_length here will smash the operands
9437 ;; array. Neither is there an early_cobbler_p predicate.
9439 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9440 (match_operand:DF 1 "any_operand" ""))
9441 (set (match_operand:DF 2 "gpc_reg_operand" "")
9443 "peep2_reg_dead_p (2, operands[0])"
9444 [(set (match_dup 2) (match_dup 1))])
9447 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9448 (match_operand:SF 1 "any_operand" ""))
9449 (set (match_operand:SF 2 "gpc_reg_operand" "")
9451 "peep2_reg_dead_p (2, operands[0])"
9452 [(set (match_dup 2) (match_dup 1))])
9457 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9458 (define_insn "tls_gd_32"
9459 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9460 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9461 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9463 "HAVE_AS_TLS && !TARGET_64BIT"
9464 "addi %0,%1,%2@got@tlsgd")
9466 (define_insn "tls_gd_64"
9467 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9468 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9469 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9471 "HAVE_AS_TLS && TARGET_64BIT"
9472 "addi %0,%1,%2@got@tlsgd")
9474 (define_insn "tls_ld_32"
9475 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9476 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9478 "HAVE_AS_TLS && !TARGET_64BIT"
9479 "addi %0,%1,%&@got@tlsld")
9481 (define_insn "tls_ld_64"
9482 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9483 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9485 "HAVE_AS_TLS && TARGET_64BIT"
9486 "addi %0,%1,%&@got@tlsld")
9488 (define_insn "tls_dtprel_32"
9489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9490 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9491 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9493 "HAVE_AS_TLS && !TARGET_64BIT"
9494 "addi %0,%1,%2@dtprel")
9496 (define_insn "tls_dtprel_64"
9497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9498 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9499 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9501 "HAVE_AS_TLS && TARGET_64BIT"
9502 "addi %0,%1,%2@dtprel")
9504 (define_insn "tls_dtprel_ha_32"
9505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9506 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9507 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9508 UNSPEC_TLSDTPRELHA))]
9509 "HAVE_AS_TLS && !TARGET_64BIT"
9510 "addis %0,%1,%2@dtprel@ha")
9512 (define_insn "tls_dtprel_ha_64"
9513 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9514 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9515 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9516 UNSPEC_TLSDTPRELHA))]
9517 "HAVE_AS_TLS && TARGET_64BIT"
9518 "addis %0,%1,%2@dtprel@ha")
9520 (define_insn "tls_dtprel_lo_32"
9521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9522 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9523 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9524 UNSPEC_TLSDTPRELLO))]
9525 "HAVE_AS_TLS && !TARGET_64BIT"
9526 "addi %0,%1,%2@dtprel@l")
9528 (define_insn "tls_dtprel_lo_64"
9529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9530 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9531 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9532 UNSPEC_TLSDTPRELLO))]
9533 "HAVE_AS_TLS && TARGET_64BIT"
9534 "addi %0,%1,%2@dtprel@l")
9536 (define_insn "tls_got_dtprel_32"
9537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9538 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9539 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9540 UNSPEC_TLSGOTDTPREL))]
9541 "HAVE_AS_TLS && !TARGET_64BIT"
9542 "lwz %0,%2@got@dtprel(%1)")
9544 (define_insn "tls_got_dtprel_64"
9545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9546 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9547 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9548 UNSPEC_TLSGOTDTPREL))]
9549 "HAVE_AS_TLS && TARGET_64BIT"
9550 "ld %0,%2@got@dtprel(%1)")
9552 (define_insn "tls_tprel_32"
9553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9554 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9555 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9557 "HAVE_AS_TLS && !TARGET_64BIT"
9558 "addi %0,%1,%2@tprel")
9560 (define_insn "tls_tprel_64"
9561 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9562 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9563 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9565 "HAVE_AS_TLS && TARGET_64BIT"
9566 "addi %0,%1,%2@tprel")
9568 (define_insn "tls_tprel_ha_32"
9569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9570 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9571 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9572 UNSPEC_TLSTPRELHA))]
9573 "HAVE_AS_TLS && !TARGET_64BIT"
9574 "addis %0,%1,%2@tprel@ha")
9576 (define_insn "tls_tprel_ha_64"
9577 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9578 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9579 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9580 UNSPEC_TLSTPRELHA))]
9581 "HAVE_AS_TLS && TARGET_64BIT"
9582 "addis %0,%1,%2@tprel@ha")
9584 (define_insn "tls_tprel_lo_32"
9585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9586 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9587 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9588 UNSPEC_TLSTPRELLO))]
9589 "HAVE_AS_TLS && !TARGET_64BIT"
9590 "addi %0,%1,%2@tprel@l")
9592 (define_insn "tls_tprel_lo_64"
9593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9594 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9595 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9596 UNSPEC_TLSTPRELLO))]
9597 "HAVE_AS_TLS && TARGET_64BIT"
9598 "addi %0,%1,%2@tprel@l")
9600 ;; "b" output constraint here and on tls_tls input to support linker tls
9601 ;; optimization. The linker may edit the instructions emitted by a
9602 ;; tls_got_tprel/tls_tls pair to addis,addi.
9603 (define_insn "tls_got_tprel_32"
9604 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9605 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9606 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9607 UNSPEC_TLSGOTTPREL))]
9608 "HAVE_AS_TLS && !TARGET_64BIT"
9609 "lwz %0,%2@got@tprel(%1)")
9611 (define_insn "tls_got_tprel_64"
9612 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9613 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9614 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9615 UNSPEC_TLSGOTTPREL))]
9616 "HAVE_AS_TLS && TARGET_64BIT"
9617 "ld %0,%2@got@tprel(%1)")
9619 (define_insn "tls_tls_32"
9620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9621 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9622 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9624 "HAVE_AS_TLS && !TARGET_64BIT"
9627 (define_insn "tls_tls_64"
9628 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9629 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9630 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9632 "HAVE_AS_TLS && TARGET_64BIT"
9635 ;; Next come insns related to the calling sequence.
9637 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9638 ;; We move the back-chain and decrement the stack pointer.
9640 (define_expand "allocate_stack"
9641 [(set (match_operand 0 "gpc_reg_operand" "=r")
9642 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9644 (minus (reg 1) (match_dup 1)))]
9647 { rtx chain = gen_reg_rtx (Pmode);
9648 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9651 emit_move_insn (chain, stack_bot);
9653 /* Check stack bounds if necessary. */
9654 if (current_function_limit_stack)
9657 available = expand_binop (Pmode, sub_optab,
9658 stack_pointer_rtx, stack_limit_rtx,
9659 NULL_RTX, 1, OPTAB_WIDEN);
9660 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9663 if (GET_CODE (operands[1]) != CONST_INT
9664 || INTVAL (operands[1]) < -32767
9665 || INTVAL (operands[1]) > 32768)
9667 neg_op0 = gen_reg_rtx (Pmode);
9669 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9671 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9674 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9677 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9678 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9682 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9683 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9684 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9687 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9691 ;; These patterns say how to save and restore the stack pointer. We need not
9692 ;; save the stack pointer at function level since we are careful to
9693 ;; preserve the backchain. At block level, we have to restore the backchain
9694 ;; when we restore the stack pointer.
9696 ;; For nonlocal gotos, we must save both the stack pointer and its
9697 ;; backchain and restore both. Note that in the nonlocal case, the
9698 ;; save area is a memory location.
9700 (define_expand "save_stack_function"
9701 [(match_operand 0 "any_operand" "")
9702 (match_operand 1 "any_operand" "")]
9706 (define_expand "restore_stack_function"
9707 [(match_operand 0 "any_operand" "")
9708 (match_operand 1 "any_operand" "")]
9712 (define_expand "restore_stack_block"
9713 [(use (match_operand 0 "register_operand" ""))
9714 (set (match_dup 2) (match_dup 3))
9715 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9716 (set (match_dup 3) (match_dup 2))]
9720 operands[2] = gen_reg_rtx (Pmode);
9721 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9724 (define_expand "save_stack_nonlocal"
9725 [(match_operand 0 "memory_operand" "")
9726 (match_operand 1 "register_operand" "")]
9730 rtx temp = gen_reg_rtx (Pmode);
9731 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9733 /* Copy the backchain to the first word, sp to the second. */
9734 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9735 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9736 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9741 (define_expand "restore_stack_nonlocal"
9742 [(match_operand 0 "register_operand" "")
9743 (match_operand 1 "memory_operand" "")]
9747 rtx temp = gen_reg_rtx (Pmode);
9748 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9750 /* Restore the backchain from the first word, sp from the second. */
9751 emit_move_insn (temp,
9752 adjust_address_nv (operands[1], Pmode, 0));
9753 emit_move_insn (operands[0],
9754 adjust_address_nv (operands[1], Pmode, units_per_word));
9755 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9759 ;; TOC register handling.
9761 ;; Code to initialize the TOC register...
9763 (define_insn "load_toc_aix_si"
9764 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9765 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9767 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9771 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9772 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9773 operands[2] = gen_rtx_REG (Pmode, 2);
9774 return \"{l|lwz} %0,%1(%2)\";
9776 [(set_attr "type" "load")])
9778 (define_insn "load_toc_aix_di"
9779 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9780 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9782 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9786 #ifdef TARGET_RELOCATABLE
9787 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9788 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9790 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9793 strcat (buf, \"@toc\");
9794 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9795 operands[2] = gen_rtx_REG (Pmode, 2);
9796 return \"ld %0,%1(%2)\";
9798 [(set_attr "type" "load")])
9800 (define_insn "load_toc_v4_pic_si"
9801 [(set (match_operand:SI 0 "register_operand" "=l")
9802 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9803 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9804 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9805 [(set_attr "type" "branch")
9806 (set_attr "length" "4")])
9808 (define_insn "load_toc_v4_PIC_1"
9809 [(set (match_operand:SI 0 "register_operand" "=l")
9810 (match_operand:SI 1 "immediate_operand" "s"))
9811 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9812 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9813 "bcl 20,31,%1\\n%1:"
9814 [(set_attr "type" "branch")
9815 (set_attr "length" "4")])
9817 (define_insn "load_toc_v4_PIC_1b"
9818 [(set (match_operand:SI 0 "register_operand" "=l")
9819 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9821 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9822 "bcl 20,31,$+8\\n\\t.long %1-$"
9823 [(set_attr "type" "branch")
9824 (set_attr "length" "8")])
9826 (define_insn "load_toc_v4_PIC_2"
9827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9828 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9829 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9830 (match_operand:SI 3 "immediate_operand" "s")))))]
9831 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9832 "{l|lwz} %0,%2-%3(%1)"
9833 [(set_attr "type" "load")])
9836 ;; If the TOC is shared over a translation unit, as happens with all
9837 ;; the kinds of PIC that we support, we need to restore the TOC
9838 ;; pointer only when jumping over units of translation.
9839 ;; On Darwin, we need to reload the picbase.
9841 (define_expand "builtin_setjmp_receiver"
9842 [(use (label_ref (match_operand 0 "" "")))]
9843 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9844 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9845 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9849 if (DEFAULT_ABI == ABI_DARWIN)
9851 const char *picbase = machopic_function_base_name ();
9852 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9853 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9857 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9858 CODE_LABEL_NUMBER (operands[0]));
9859 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9861 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9862 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9866 rs6000_emit_load_toc_table (FALSE);
9870 ;; A function pointer under AIX is a pointer to a data area whose first word
9871 ;; contains the actual address of the function, whose second word contains a
9872 ;; pointer to its TOC, and whose third word contains a value to place in the
9873 ;; static chain register (r11). Note that if we load the static chain, our
9874 ;; "trampoline" need not have any executable code.
9876 (define_expand "call_indirect_aix32"
9878 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9879 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9882 (mem:SI (plus:SI (match_dup 0)
9885 (mem:SI (plus:SI (match_dup 0)
9887 (parallel [(call (mem:SI (match_dup 2))
9888 (match_operand 1 "" ""))
9892 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9893 (clobber (scratch:SI))])]
9896 { operands[2] = gen_reg_rtx (SImode); }")
9898 (define_expand "call_indirect_aix64"
9900 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9901 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9904 (mem:DI (plus:DI (match_dup 0)
9907 (mem:DI (plus:DI (match_dup 0)
9909 (parallel [(call (mem:SI (match_dup 2))
9910 (match_operand 1 "" ""))
9914 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9915 (clobber (scratch:SI))])]
9918 { operands[2] = gen_reg_rtx (DImode); }")
9920 (define_expand "call_value_indirect_aix32"
9922 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9923 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9926 (mem:SI (plus:SI (match_dup 1)
9929 (mem:SI (plus:SI (match_dup 1)
9931 (parallel [(set (match_operand 0 "" "")
9932 (call (mem:SI (match_dup 3))
9933 (match_operand 2 "" "")))
9937 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9938 (clobber (scratch:SI))])]
9941 { operands[3] = gen_reg_rtx (SImode); }")
9943 (define_expand "call_value_indirect_aix64"
9945 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9946 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9949 (mem:DI (plus:DI (match_dup 1)
9952 (mem:DI (plus:DI (match_dup 1)
9954 (parallel [(set (match_operand 0 "" "")
9955 (call (mem:SI (match_dup 3))
9956 (match_operand 2 "" "")))
9960 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9961 (clobber (scratch:SI))])]
9964 { operands[3] = gen_reg_rtx (DImode); }")
9966 ;; Now the definitions for the call and call_value insns
9967 (define_expand "call"
9968 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9969 (match_operand 1 "" ""))
9970 (use (match_operand 2 "" ""))
9971 (clobber (scratch:SI))])]
9976 if (MACHOPIC_INDIRECT)
9977 operands[0] = machopic_indirect_call_target (operands[0]);
9980 gcc_assert (GET_CODE (operands[0]) == MEM);
9981 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9983 operands[0] = XEXP (operands[0], 0);
9985 if (GET_CODE (operands[0]) != SYMBOL_REF
9986 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9987 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9989 if (INTVAL (operands[2]) & CALL_LONG)
9990 operands[0] = rs6000_longcall_ref (operands[0]);
9992 switch (DEFAULT_ABI)
9996 operands[0] = force_reg (Pmode, operands[0]);
10000 /* AIX function pointers are really pointers to a three word
10002 emit_call_insn (TARGET_32BIT
10003 ? gen_call_indirect_aix32 (force_reg (SImode,
10006 : gen_call_indirect_aix64 (force_reg (DImode,
10012 gcc_unreachable ();
10017 (define_expand "call_value"
10018 [(parallel [(set (match_operand 0 "" "")
10019 (call (mem:SI (match_operand 1 "address_operand" ""))
10020 (match_operand 2 "" "")))
10021 (use (match_operand 3 "" ""))
10022 (clobber (scratch:SI))])]
10027 if (MACHOPIC_INDIRECT)
10028 operands[1] = machopic_indirect_call_target (operands[1]);
10031 gcc_assert (GET_CODE (operands[1]) == MEM);
10032 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10034 operands[1] = XEXP (operands[1], 0);
10036 if (GET_CODE (operands[1]) != SYMBOL_REF
10037 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10038 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10040 if (INTVAL (operands[3]) & CALL_LONG)
10041 operands[1] = rs6000_longcall_ref (operands[1]);
10043 switch (DEFAULT_ABI)
10047 operands[1] = force_reg (Pmode, operands[1]);
10051 /* AIX function pointers are really pointers to a three word
10053 emit_call_insn (TARGET_32BIT
10054 ? gen_call_value_indirect_aix32 (operands[0],
10058 : gen_call_value_indirect_aix64 (operands[0],
10065 gcc_unreachable ();
10070 ;; Call to function in current module. No TOC pointer reload needed.
10071 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10072 ;; either the function was not prototyped, or it was prototyped as a
10073 ;; variable argument function. It is > 0 if FP registers were passed
10074 ;; and < 0 if they were not.
10076 (define_insn "*call_local32"
10077 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10078 (match_operand 1 "" "g,g"))
10079 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10080 (clobber (match_scratch:SI 3 "=l,l"))]
10081 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10084 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10085 output_asm_insn (\"crxor 6,6,6\", operands);
10087 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10088 output_asm_insn (\"creqv 6,6,6\", operands);
10090 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10092 [(set_attr "type" "branch")
10093 (set_attr "length" "4,8")])
10095 (define_insn "*call_local64"
10096 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10097 (match_operand 1 "" "g,g"))
10098 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10099 (clobber (match_scratch:SI 3 "=l,l"))]
10100 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10103 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10104 output_asm_insn (\"crxor 6,6,6\", operands);
10106 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10107 output_asm_insn (\"creqv 6,6,6\", operands);
10109 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10111 [(set_attr "type" "branch")
10112 (set_attr "length" "4,8")])
10114 (define_insn "*call_value_local32"
10115 [(set (match_operand 0 "" "")
10116 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10117 (match_operand 2 "" "g,g")))
10118 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10119 (clobber (match_scratch:SI 4 "=l,l"))]
10120 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10123 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10124 output_asm_insn (\"crxor 6,6,6\", operands);
10126 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10127 output_asm_insn (\"creqv 6,6,6\", operands);
10129 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10131 [(set_attr "type" "branch")
10132 (set_attr "length" "4,8")])
10135 (define_insn "*call_value_local64"
10136 [(set (match_operand 0 "" "")
10137 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10138 (match_operand 2 "" "g,g")))
10139 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10140 (clobber (match_scratch:SI 4 "=l,l"))]
10141 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10144 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10145 output_asm_insn (\"crxor 6,6,6\", operands);
10147 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10148 output_asm_insn (\"creqv 6,6,6\", operands);
10150 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10152 [(set_attr "type" "branch")
10153 (set_attr "length" "4,8")])
10155 ;; Call to function which may be in another module. Restore the TOC
10156 ;; pointer (r2) after the call unless this is System V.
10157 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10158 ;; either the function was not prototyped, or it was prototyped as a
10159 ;; variable argument function. It is > 0 if FP registers were passed
10160 ;; and < 0 if they were not.
10162 (define_insn "*call_indirect_nonlocal_aix32"
10163 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10164 (match_operand 1 "" "g"))
10168 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10169 (clobber (match_scratch:SI 2 "=l"))]
10170 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10171 "b%T0l\;{l|lwz} 2,20(1)"
10172 [(set_attr "type" "jmpreg")
10173 (set_attr "length" "8")])
10175 (define_insn "*call_nonlocal_aix32"
10176 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10177 (match_operand 1 "" "g"))
10178 (use (match_operand:SI 2 "immediate_operand" "O"))
10179 (clobber (match_scratch:SI 3 "=l"))]
10181 && DEFAULT_ABI == ABI_AIX
10182 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10184 [(set_attr "type" "branch")
10185 (set_attr "length" "8")])
10187 (define_insn "*call_indirect_nonlocal_aix64"
10188 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10189 (match_operand 1 "" "g"))
10193 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10194 (clobber (match_scratch:SI 2 "=l"))]
10195 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10196 "b%T0l\;ld 2,40(1)"
10197 [(set_attr "type" "jmpreg")
10198 (set_attr "length" "8")])
10200 (define_insn "*call_nonlocal_aix64"
10201 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10202 (match_operand 1 "" "g"))
10203 (use (match_operand:SI 2 "immediate_operand" "O"))
10204 (clobber (match_scratch:SI 3 "=l"))]
10206 && DEFAULT_ABI == ABI_AIX
10207 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10209 [(set_attr "type" "branch")
10210 (set_attr "length" "8")])
10212 (define_insn "*call_value_indirect_nonlocal_aix32"
10213 [(set (match_operand 0 "" "")
10214 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10215 (match_operand 2 "" "g")))
10219 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10220 (clobber (match_scratch:SI 3 "=l"))]
10221 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10222 "b%T1l\;{l|lwz} 2,20(1)"
10223 [(set_attr "type" "jmpreg")
10224 (set_attr "length" "8")])
10226 (define_insn "*call_value_nonlocal_aix32"
10227 [(set (match_operand 0 "" "")
10228 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10229 (match_operand 2 "" "g")))
10230 (use (match_operand:SI 3 "immediate_operand" "O"))
10231 (clobber (match_scratch:SI 4 "=l"))]
10233 && DEFAULT_ABI == ABI_AIX
10234 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10236 [(set_attr "type" "branch")
10237 (set_attr "length" "8")])
10239 (define_insn "*call_value_indirect_nonlocal_aix64"
10240 [(set (match_operand 0 "" "")
10241 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10242 (match_operand 2 "" "g")))
10246 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10247 (clobber (match_scratch:SI 3 "=l"))]
10248 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10249 "b%T1l\;ld 2,40(1)"
10250 [(set_attr "type" "jmpreg")
10251 (set_attr "length" "8")])
10253 (define_insn "*call_value_nonlocal_aix64"
10254 [(set (match_operand 0 "" "")
10255 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10256 (match_operand 2 "" "g")))
10257 (use (match_operand:SI 3 "immediate_operand" "O"))
10258 (clobber (match_scratch:SI 4 "=l"))]
10260 && DEFAULT_ABI == ABI_AIX
10261 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10263 [(set_attr "type" "branch")
10264 (set_attr "length" "8")])
10266 ;; A function pointer under System V is just a normal pointer
10267 ;; operands[0] is the function pointer
10268 ;; operands[1] is the stack size to clean up
10269 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10270 ;; which indicates how to set cr1
10272 (define_insn "*call_indirect_nonlocal_sysv"
10273 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10274 (match_operand 1 "" "g,g"))
10275 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10276 (clobber (match_scratch:SI 3 "=l,l"))]
10277 "DEFAULT_ABI == ABI_V4
10278 || DEFAULT_ABI == ABI_DARWIN"
10280 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10281 output_asm_insn ("crxor 6,6,6", operands);
10283 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10284 output_asm_insn ("creqv 6,6,6", operands);
10288 [(set_attr "type" "jmpreg,jmpreg")
10289 (set_attr "length" "4,8")])
10291 (define_insn "*call_nonlocal_sysv"
10292 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10293 (match_operand 1 "" "g,g"))
10294 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10295 (clobber (match_scratch:SI 3 "=l,l"))]
10296 "(DEFAULT_ABI == ABI_DARWIN
10297 || (DEFAULT_ABI == ABI_V4
10298 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10300 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10301 output_asm_insn ("crxor 6,6,6", operands);
10303 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10304 output_asm_insn ("creqv 6,6,6", operands);
10307 return output_call(insn, operands, 0, 2);
10309 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10312 [(set_attr "type" "branch,branch")
10313 (set_attr "length" "4,8")])
10315 (define_insn "*call_value_indirect_nonlocal_sysv"
10316 [(set (match_operand 0 "" "")
10317 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10318 (match_operand 2 "" "g,g")))
10319 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10320 (clobber (match_scratch:SI 4 "=l,l"))]
10321 "DEFAULT_ABI == ABI_V4
10322 || DEFAULT_ABI == ABI_DARWIN"
10324 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10325 output_asm_insn ("crxor 6,6,6", operands);
10327 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10328 output_asm_insn ("creqv 6,6,6", operands);
10332 [(set_attr "type" "jmpreg,jmpreg")
10333 (set_attr "length" "4,8")])
10335 (define_insn "*call_value_nonlocal_sysv"
10336 [(set (match_operand 0 "" "")
10337 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10338 (match_operand 2 "" "g,g")))
10339 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10340 (clobber (match_scratch:SI 4 "=l,l"))]
10341 "(DEFAULT_ABI == ABI_DARWIN
10342 || (DEFAULT_ABI == ABI_V4
10343 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10345 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10346 output_asm_insn ("crxor 6,6,6", operands);
10348 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10349 output_asm_insn ("creqv 6,6,6", operands);
10352 return output_call(insn, operands, 1, 3);
10354 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10357 [(set_attr "type" "branch,branch")
10358 (set_attr "length" "4,8")])
10360 ;; Call subroutine returning any type.
10361 (define_expand "untyped_call"
10362 [(parallel [(call (match_operand 0 "" "")
10364 (match_operand 1 "" "")
10365 (match_operand 2 "" "")])]
10371 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10373 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10375 rtx set = XVECEXP (operands[2], 0, i);
10376 emit_move_insn (SET_DEST (set), SET_SRC (set));
10379 /* The optimizer does not know that the call sets the function value
10380 registers we stored in the result block. We avoid problems by
10381 claiming that all hard registers are used and clobbered at this
10383 emit_insn (gen_blockage ());
10388 ;; sibling call patterns
10389 (define_expand "sibcall"
10390 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10391 (match_operand 1 "" ""))
10392 (use (match_operand 2 "" ""))
10393 (use (match_operand 3 "" ""))
10399 if (MACHOPIC_INDIRECT)
10400 operands[0] = machopic_indirect_call_target (operands[0]);
10403 gcc_assert (GET_CODE (operands[0]) == MEM);
10404 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10406 operands[0] = XEXP (operands[0], 0);
10407 operands[3] = gen_reg_rtx (SImode);
10411 ;; this and similar patterns must be marked as using LR, otherwise
10412 ;; dataflow will try to delete the store into it. This is true
10413 ;; even when the actual reg to jump to is in CTR, when LR was
10414 ;; saved and restored around the PIC-setting BCL.
10415 (define_insn "*sibcall_local32"
10416 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10417 (match_operand 1 "" "g,g"))
10418 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10419 (use (match_operand:SI 3 "register_operand" "l,l"))
10421 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10424 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10425 output_asm_insn (\"crxor 6,6,6\", operands);
10427 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10428 output_asm_insn (\"creqv 6,6,6\", operands);
10430 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10432 [(set_attr "type" "branch")
10433 (set_attr "length" "4,8")])
10435 (define_insn "*sibcall_local64"
10436 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10437 (match_operand 1 "" "g,g"))
10438 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10439 (use (match_operand:SI 3 "register_operand" "l,l"))
10441 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10444 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10445 output_asm_insn (\"crxor 6,6,6\", operands);
10447 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10448 output_asm_insn (\"creqv 6,6,6\", operands);
10450 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10452 [(set_attr "type" "branch")
10453 (set_attr "length" "4,8")])
10455 (define_insn "*sibcall_value_local32"
10456 [(set (match_operand 0 "" "")
10457 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10458 (match_operand 2 "" "g,g")))
10459 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10460 (use (match_operand:SI 4 "register_operand" "l,l"))
10462 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10465 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10466 output_asm_insn (\"crxor 6,6,6\", operands);
10468 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10469 output_asm_insn (\"creqv 6,6,6\", operands);
10471 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10473 [(set_attr "type" "branch")
10474 (set_attr "length" "4,8")])
10477 (define_insn "*sibcall_value_local64"
10478 [(set (match_operand 0 "" "")
10479 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10480 (match_operand 2 "" "g,g")))
10481 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10482 (use (match_operand:SI 4 "register_operand" "l,l"))
10484 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10487 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10488 output_asm_insn (\"crxor 6,6,6\", operands);
10490 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10491 output_asm_insn (\"creqv 6,6,6\", operands);
10493 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10495 [(set_attr "type" "branch")
10496 (set_attr "length" "4,8")])
10498 (define_insn "*sibcall_nonlocal_aix32"
10499 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10500 (match_operand 1 "" "g"))
10501 (use (match_operand:SI 2 "immediate_operand" "O"))
10502 (use (match_operand:SI 3 "register_operand" "l"))
10505 && DEFAULT_ABI == ABI_AIX
10506 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10508 [(set_attr "type" "branch")
10509 (set_attr "length" "4")])
10511 (define_insn "*sibcall_nonlocal_aix64"
10512 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10513 (match_operand 1 "" "g"))
10514 (use (match_operand:SI 2 "immediate_operand" "O"))
10515 (use (match_operand:SI 3 "register_operand" "l"))
10518 && DEFAULT_ABI == ABI_AIX
10519 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10521 [(set_attr "type" "branch")
10522 (set_attr "length" "4")])
10524 (define_insn "*sibcall_value_nonlocal_aix32"
10525 [(set (match_operand 0 "" "")
10526 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10527 (match_operand 2 "" "g")))
10528 (use (match_operand:SI 3 "immediate_operand" "O"))
10529 (use (match_operand:SI 4 "register_operand" "l"))
10532 && DEFAULT_ABI == ABI_AIX
10533 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10535 [(set_attr "type" "branch")
10536 (set_attr "length" "4")])
10538 (define_insn "*sibcall_value_nonlocal_aix64"
10539 [(set (match_operand 0 "" "")
10540 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10541 (match_operand 2 "" "g")))
10542 (use (match_operand:SI 3 "immediate_operand" "O"))
10543 (use (match_operand:SI 4 "register_operand" "l"))
10546 && DEFAULT_ABI == ABI_AIX
10547 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10549 [(set_attr "type" "branch")
10550 (set_attr "length" "4")])
10552 (define_insn "*sibcall_nonlocal_sysv"
10553 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10554 (match_operand 1 "" ""))
10555 (use (match_operand 2 "immediate_operand" "O,n"))
10556 (use (match_operand:SI 3 "register_operand" "l,l"))
10558 "(DEFAULT_ABI == ABI_DARWIN
10559 || DEFAULT_ABI == ABI_V4)
10560 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10563 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10564 output_asm_insn (\"crxor 6,6,6\", operands);
10566 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10567 output_asm_insn (\"creqv 6,6,6\", operands);
10569 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10571 [(set_attr "type" "branch,branch")
10572 (set_attr "length" "4,8")])
10574 (define_expand "sibcall_value"
10575 [(parallel [(set (match_operand 0 "register_operand" "")
10576 (call (mem:SI (match_operand 1 "address_operand" ""))
10577 (match_operand 2 "" "")))
10578 (use (match_operand 3 "" ""))
10579 (use (match_operand 4 "" ""))
10585 if (MACHOPIC_INDIRECT)
10586 operands[1] = machopic_indirect_call_target (operands[1]);
10589 gcc_assert (GET_CODE (operands[1]) == MEM);
10590 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10592 operands[1] = XEXP (operands[1], 0);
10593 operands[4] = gen_reg_rtx (SImode);
10597 (define_insn "*sibcall_value_nonlocal_sysv"
10598 [(set (match_operand 0 "" "")
10599 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10600 (match_operand 2 "" "")))
10601 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10602 (use (match_operand:SI 4 "register_operand" "l,l"))
10604 "(DEFAULT_ABI == ABI_DARWIN
10605 || DEFAULT_ABI == ABI_V4)
10606 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10609 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10610 output_asm_insn (\"crxor 6,6,6\", operands);
10612 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10613 output_asm_insn (\"creqv 6,6,6\", operands);
10615 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10617 [(set_attr "type" "branch,branch")
10618 (set_attr "length" "4,8")])
10620 (define_expand "sibcall_epilogue"
10621 [(use (const_int 0))]
10622 "TARGET_SCHED_PROLOG"
10625 rs6000_emit_epilogue (TRUE);
10629 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10630 ;; all of memory. This blocks insns from being moved across this point.
10632 (define_insn "blockage"
10633 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10637 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10638 ;; signed & unsigned, and one type of branch.
10640 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10641 ;; insns, and branches. We store the operands of compares until we see
10643 (define_expand "cmpsi"
10645 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10646 (match_operand:SI 1 "reg_or_short_operand" "")))]
10650 /* Take care of the possibility that operands[1] might be negative but
10651 this might be a logical operation. That insn doesn't exist. */
10652 if (GET_CODE (operands[1]) == CONST_INT
10653 && INTVAL (operands[1]) < 0)
10654 operands[1] = force_reg (SImode, operands[1]);
10656 rs6000_compare_op0 = operands[0];
10657 rs6000_compare_op1 = operands[1];
10658 rs6000_compare_fp_p = 0;
10662 (define_expand "cmpdi"
10664 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10665 (match_operand:DI 1 "reg_or_short_operand" "")))]
10669 /* Take care of the possibility that operands[1] might be negative but
10670 this might be a logical operation. That insn doesn't exist. */
10671 if (GET_CODE (operands[1]) == CONST_INT
10672 && INTVAL (operands[1]) < 0)
10673 operands[1] = force_reg (DImode, operands[1]);
10675 rs6000_compare_op0 = operands[0];
10676 rs6000_compare_op1 = operands[1];
10677 rs6000_compare_fp_p = 0;
10681 (define_expand "cmpsf"
10682 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10683 (match_operand:SF 1 "gpc_reg_operand" "")))]
10684 "TARGET_HARD_FLOAT"
10687 rs6000_compare_op0 = operands[0];
10688 rs6000_compare_op1 = operands[1];
10689 rs6000_compare_fp_p = 1;
10693 (define_expand "cmpdf"
10694 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10695 (match_operand:DF 1 "gpc_reg_operand" "")))]
10696 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
10699 rs6000_compare_op0 = operands[0];
10700 rs6000_compare_op1 = operands[1];
10701 rs6000_compare_fp_p = 1;
10705 (define_expand "cmptf"
10706 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10707 (match_operand:TF 1 "gpc_reg_operand" "")))]
10708 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10709 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10712 rs6000_compare_op0 = operands[0];
10713 rs6000_compare_op1 = operands[1];
10714 rs6000_compare_fp_p = 1;
10718 (define_expand "beq"
10719 [(use (match_operand 0 "" ""))]
10721 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10723 (define_expand "bne"
10724 [(use (match_operand 0 "" ""))]
10726 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10728 (define_expand "bge"
10729 [(use (match_operand 0 "" ""))]
10731 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10733 (define_expand "bgt"
10734 [(use (match_operand 0 "" ""))]
10736 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10738 (define_expand "ble"
10739 [(use (match_operand 0 "" ""))]
10741 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10743 (define_expand "blt"
10744 [(use (match_operand 0 "" ""))]
10746 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10748 (define_expand "bgeu"
10749 [(use (match_operand 0 "" ""))]
10751 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10753 (define_expand "bgtu"
10754 [(use (match_operand 0 "" ""))]
10756 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10758 (define_expand "bleu"
10759 [(use (match_operand 0 "" ""))]
10761 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10763 (define_expand "bltu"
10764 [(use (match_operand 0 "" ""))]
10766 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10768 (define_expand "bunordered"
10769 [(use (match_operand 0 "" ""))]
10770 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10771 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10773 (define_expand "bordered"
10774 [(use (match_operand 0 "" ""))]
10775 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10776 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10778 (define_expand "buneq"
10779 [(use (match_operand 0 "" ""))]
10781 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10783 (define_expand "bunge"
10784 [(use (match_operand 0 "" ""))]
10786 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10788 (define_expand "bungt"
10789 [(use (match_operand 0 "" ""))]
10791 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10793 (define_expand "bunle"
10794 [(use (match_operand 0 "" ""))]
10796 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10798 (define_expand "bunlt"
10799 [(use (match_operand 0 "" ""))]
10801 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10803 (define_expand "bltgt"
10804 [(use (match_operand 0 "" ""))]
10806 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10808 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10809 ;; For SEQ, likewise, except that comparisons with zero should be done
10810 ;; with an scc insns. However, due to the order that combine see the
10811 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10812 ;; the cases we don't want to handle.
10813 (define_expand "seq"
10814 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10816 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10818 (define_expand "sne"
10819 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10823 if (! rs6000_compare_fp_p)
10826 rs6000_emit_sCOND (NE, operands[0]);
10830 ;; A >= 0 is best done the portable way for A an integer.
10831 (define_expand "sge"
10832 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10836 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10839 rs6000_emit_sCOND (GE, operands[0]);
10843 ;; A > 0 is best done using the portable sequence, so fail in that case.
10844 (define_expand "sgt"
10845 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10849 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10852 rs6000_emit_sCOND (GT, operands[0]);
10856 ;; A <= 0 is best done the portable way for A an integer.
10857 (define_expand "sle"
10858 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10862 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10865 rs6000_emit_sCOND (LE, operands[0]);
10869 ;; A < 0 is best done in the portable way for A an integer.
10870 (define_expand "slt"
10871 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10875 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10878 rs6000_emit_sCOND (LT, operands[0]);
10882 (define_expand "sgeu"
10883 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10885 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10887 (define_expand "sgtu"
10888 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10890 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10892 (define_expand "sleu"
10893 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10895 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10897 (define_expand "sltu"
10898 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10900 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10902 (define_expand "sunordered"
10903 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10904 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10905 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10907 (define_expand "sordered"
10908 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10909 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10910 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10912 (define_expand "suneq"
10913 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10915 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10917 (define_expand "sunge"
10918 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10920 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10922 (define_expand "sungt"
10923 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10925 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10927 (define_expand "sunle"
10928 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10930 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10932 (define_expand "sunlt"
10933 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10935 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10937 (define_expand "sltgt"
10938 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10940 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10943 ;; Here are the actual compare insns.
10944 (define_insn "*cmpsi_internal1"
10945 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10946 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10947 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10949 "{cmp%I2|cmpw%I2} %0,%1,%2"
10950 [(set_attr "type" "cmp")])
10952 (define_insn "*cmpdi_internal1"
10953 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10954 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10955 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10958 [(set_attr "type" "cmp")])
10960 ;; If we are comparing a register for equality with a large constant,
10961 ;; we can do this with an XOR followed by a compare. But we need a scratch
10962 ;; register for the result of the XOR.
10965 [(set (match_operand:CC 0 "cc_reg_operand" "")
10966 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10967 (match_operand:SI 2 "non_short_cint_operand" "")))
10968 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10969 "find_single_use (operands[0], insn, 0)
10970 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10971 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10972 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10973 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10976 /* Get the constant we are comparing against, C, and see what it looks like
10977 sign-extended to 16 bits. Then see what constant could be XOR'ed
10978 with C to get the sign-extended value. */
10980 HOST_WIDE_INT c = INTVAL (operands[2]);
10981 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10982 HOST_WIDE_INT xorv = c ^ sextc;
10984 operands[4] = GEN_INT (xorv);
10985 operands[5] = GEN_INT (sextc);
10988 (define_insn "*cmpsi_internal2"
10989 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10990 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10991 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10993 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10994 [(set_attr "type" "cmp")])
10996 (define_insn "*cmpdi_internal2"
10997 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10998 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10999 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11001 "cmpld%I2 %0,%1,%b2"
11002 [(set_attr "type" "cmp")])
11004 ;; The following two insns don't exist as single insns, but if we provide
11005 ;; them, we can swap an add and compare, which will enable us to overlap more
11006 ;; of the required delay between a compare and branch. We generate code for
11007 ;; them by splitting.
11010 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11011 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11012 (match_operand:SI 2 "short_cint_operand" "i")))
11013 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11014 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11017 [(set_attr "length" "8")])
11020 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11021 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11022 (match_operand:SI 2 "u_short_cint_operand" "i")))
11023 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11024 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11027 [(set_attr "length" "8")])
11030 [(set (match_operand:CC 3 "cc_reg_operand" "")
11031 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11032 (match_operand:SI 2 "short_cint_operand" "")))
11033 (set (match_operand:SI 0 "gpc_reg_operand" "")
11034 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11036 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11037 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11040 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11041 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11042 (match_operand:SI 2 "u_short_cint_operand" "")))
11043 (set (match_operand:SI 0 "gpc_reg_operand" "")
11044 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11046 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11047 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11049 (define_insn "*cmpsf_internal1"
11050 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11051 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11052 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11053 "TARGET_HARD_FLOAT && TARGET_FPRS"
11055 [(set_attr "type" "fpcompare")])
11057 (define_insn "*cmpdf_internal1"
11058 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11059 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11060 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11061 "TARGET_HARD_FLOAT && TARGET_FPRS"
11063 [(set_attr "type" "fpcompare")])
11065 ;; Only need to compare second words if first words equal
11066 (define_insn "*cmptf_internal1"
11067 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11068 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11069 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11070 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11071 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11072 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11073 [(set_attr "type" "fpcompare")
11074 (set_attr "length" "12")])
11076 (define_insn_and_split "*cmptf_internal2"
11077 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11078 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11079 (match_operand:TF 2 "gpc_reg_operand" "f")))
11080 (clobber (match_scratch:DF 3 "=f"))
11081 (clobber (match_scratch:DF 4 "=f"))
11082 (clobber (match_scratch:DF 5 "=f"))
11083 (clobber (match_scratch:DF 6 "=f"))
11084 (clobber (match_scratch:DF 7 "=f"))
11085 (clobber (match_scratch:DF 8 "=f"))
11086 (clobber (match_scratch:DF 9 "=f"))
11087 (clobber (match_scratch:DF 10 "=f"))]
11088 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11089 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11091 "&& reload_completed"
11092 [(set (match_dup 3) (match_dup 13))
11093 (set (match_dup 4) (match_dup 14))
11094 (set (match_dup 9) (abs:DF (match_dup 5)))
11095 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11096 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11097 (label_ref (match_dup 11))
11099 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11100 (set (pc) (label_ref (match_dup 12)))
11102 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11103 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11104 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11105 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11108 REAL_VALUE_TYPE rv;
11109 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11110 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11112 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11113 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11114 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11115 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11116 operands[11] = gen_label_rtx ();
11117 operands[12] = gen_label_rtx ();
11119 operands[13] = force_const_mem (DFmode,
11120 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11121 operands[14] = force_const_mem (DFmode,
11122 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11126 operands[13] = gen_const_mem (DFmode,
11127 create_TOC_reference (XEXP (operands[13], 0)));
11128 operands[14] = gen_const_mem (DFmode,
11129 create_TOC_reference (XEXP (operands[14], 0)));
11130 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11131 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11135 ;; Now we have the scc insns. We can do some combinations because of the
11136 ;; way the machine works.
11138 ;; Note that this is probably faster if we can put an insn between the
11139 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11140 ;; cases the insns below which don't use an intermediate CR field will
11141 ;; be used instead.
11143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11144 (match_operator:SI 1 "scc_comparison_operator"
11145 [(match_operand 2 "cc_reg_operand" "y")
11148 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11149 [(set (attr "type")
11150 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11151 (const_string "mfcrf")
11153 (const_string "mfcr")))
11154 (set_attr "length" "8")])
11156 ;; Same as above, but get the GT bit.
11157 (define_insn "move_from_CR_gt_bit"
11158 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11159 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11161 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11162 [(set_attr "type" "mfcr")
11163 (set_attr "length" "8")])
11165 ;; Same as above, but get the OV/ORDERED bit.
11166 (define_insn "move_from_CR_ov_bit"
11167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11168 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11170 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11171 [(set_attr "type" "mfcr")
11172 (set_attr "length" "8")])
11175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11176 (match_operator:DI 1 "scc_comparison_operator"
11177 [(match_operand 2 "cc_reg_operand" "y")
11180 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11181 [(set (attr "type")
11182 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11183 (const_string "mfcrf")
11185 (const_string "mfcr")))
11186 (set_attr "length" "8")])
11189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11190 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11191 [(match_operand 2 "cc_reg_operand" "y,y")
11194 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11195 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11198 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11200 [(set_attr "type" "delayed_compare")
11201 (set_attr "length" "8,16")])
11204 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11205 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11206 [(match_operand 2 "cc_reg_operand" "")
11209 (set (match_operand:SI 3 "gpc_reg_operand" "")
11210 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11211 "TARGET_32BIT && reload_completed"
11212 [(set (match_dup 3)
11213 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11215 (compare:CC (match_dup 3)
11220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11221 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11222 [(match_operand 2 "cc_reg_operand" "y")
11224 (match_operand:SI 3 "const_int_operand" "n")))]
11228 int is_bit = ccr_bit (operands[1], 1);
11229 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11232 if (is_bit >= put_bit)
11233 count = is_bit - put_bit;
11235 count = 32 - (put_bit - is_bit);
11237 operands[4] = GEN_INT (count);
11238 operands[5] = GEN_INT (put_bit);
11240 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11242 [(set (attr "type")
11243 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11244 (const_string "mfcrf")
11246 (const_string "mfcr")))
11247 (set_attr "length" "8")])
11250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11252 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11253 [(match_operand 2 "cc_reg_operand" "y,y")
11255 (match_operand:SI 3 "const_int_operand" "n,n"))
11257 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11258 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11263 int is_bit = ccr_bit (operands[1], 1);
11264 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11267 /* Force split for non-cc0 compare. */
11268 if (which_alternative == 1)
11271 if (is_bit >= put_bit)
11272 count = is_bit - put_bit;
11274 count = 32 - (put_bit - is_bit);
11276 operands[5] = GEN_INT (count);
11277 operands[6] = GEN_INT (put_bit);
11279 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11281 [(set_attr "type" "delayed_compare")
11282 (set_attr "length" "8,16")])
11285 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11287 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11288 [(match_operand 2 "cc_reg_operand" "")
11290 (match_operand:SI 3 "const_int_operand" ""))
11292 (set (match_operand:SI 4 "gpc_reg_operand" "")
11293 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11296 [(set (match_dup 4)
11297 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11300 (compare:CC (match_dup 4)
11304 ;; There is a 3 cycle delay between consecutive mfcr instructions
11305 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11309 (match_operator:SI 1 "scc_comparison_operator"
11310 [(match_operand 2 "cc_reg_operand" "y")
11312 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11313 (match_operator:SI 4 "scc_comparison_operator"
11314 [(match_operand 5 "cc_reg_operand" "y")
11316 "REGNO (operands[2]) != REGNO (operands[5])"
11317 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11318 [(set_attr "type" "mfcr")
11319 (set_attr "length" "12")])
11322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11323 (match_operator:DI 1 "scc_comparison_operator"
11324 [(match_operand 2 "cc_reg_operand" "y")
11326 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11327 (match_operator:DI 4 "scc_comparison_operator"
11328 [(match_operand 5 "cc_reg_operand" "y")
11330 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11331 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11332 [(set_attr "type" "mfcr")
11333 (set_attr "length" "12")])
11335 ;; There are some scc insns that can be done directly, without a compare.
11336 ;; These are faster because they don't involve the communications between
11337 ;; the FXU and branch units. In fact, we will be replacing all of the
11338 ;; integer scc insns here or in the portable methods in emit_store_flag.
11340 ;; Also support (neg (scc ..)) since that construct is used to replace
11341 ;; branches, (plus (scc ..) ..) since that construct is common and
11342 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11343 ;; cases where it is no more expensive than (neg (scc ..)).
11345 ;; Have reload force a constant into a register for the simple insns that
11346 ;; otherwise won't accept constants. We do this because it is faster than
11347 ;; the cmp/mfcr sequence we would otherwise generate.
11350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11351 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11352 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11353 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11356 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11357 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11358 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11359 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11360 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11361 [(set_attr "type" "three,two,three,three,three")
11362 (set_attr "length" "12,8,12,12,12")])
11365 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11366 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11367 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11368 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11371 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11372 subfic %3,%1,0\;adde %0,%3,%1
11373 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11374 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11375 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11376 [(set_attr "type" "three,two,three,three,three")
11377 (set_attr "length" "12,8,12,12,12")])
11380 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11382 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11383 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11385 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11386 (eq:SI (match_dup 1) (match_dup 2)))
11387 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11390 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11391 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11392 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11393 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11394 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11400 [(set_attr "type" "compare")
11401 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11404 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11406 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11407 (match_operand:SI 2 "reg_or_cint_operand" ""))
11409 (set (match_operand:SI 0 "gpc_reg_operand" "")
11410 (eq:SI (match_dup 1) (match_dup 2)))
11411 (clobber (match_scratch:SI 3 ""))]
11412 "TARGET_32BIT && reload_completed"
11413 [(parallel [(set (match_dup 0)
11414 (eq:SI (match_dup 1) (match_dup 2)))
11415 (clobber (match_dup 3))])
11417 (compare:CC (match_dup 0)
11422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11424 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11425 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11427 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11428 (eq:DI (match_dup 1) (match_dup 2)))
11429 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11432 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11433 subfic %3,%1,0\;adde. %0,%3,%1
11434 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11435 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11436 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11442 [(set_attr "type" "compare")
11443 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11446 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11448 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11449 (match_operand:DI 2 "reg_or_cint_operand" ""))
11451 (set (match_operand:DI 0 "gpc_reg_operand" "")
11452 (eq:DI (match_dup 1) (match_dup 2)))
11453 (clobber (match_scratch:DI 3 ""))]
11454 "TARGET_64BIT && reload_completed"
11455 [(parallel [(set (match_dup 0)
11456 (eq:DI (match_dup 1) (match_dup 2)))
11457 (clobber (match_dup 3))])
11459 (compare:CC (match_dup 0)
11463 ;; We have insns of the form shown by the first define_insn below. If
11464 ;; there is something inside the comparison operation, we must split it.
11466 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11467 (plus:SI (match_operator 1 "comparison_operator"
11468 [(match_operand:SI 2 "" "")
11469 (match_operand:SI 3
11470 "reg_or_cint_operand" "")])
11471 (match_operand:SI 4 "gpc_reg_operand" "")))
11472 (clobber (match_operand:SI 5 "register_operand" ""))]
11473 "! gpc_reg_operand (operands[2], SImode)"
11474 [(set (match_dup 5) (match_dup 2))
11475 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11479 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11480 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11481 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11482 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11485 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11486 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11487 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11488 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11489 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11490 [(set_attr "type" "three,two,three,three,three")
11491 (set_attr "length" "12,8,12,12,12")])
11494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11497 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11498 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11499 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11501 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11504 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11505 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11506 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11507 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11508 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11514 [(set_attr "type" "compare")
11515 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11518 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11521 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11522 (match_operand:SI 2 "reg_or_cint_operand" ""))
11523 (match_operand:SI 3 "gpc_reg_operand" ""))
11525 (clobber (match_scratch:SI 4 ""))]
11526 "TARGET_32BIT && reload_completed"
11527 [(set (match_dup 4)
11528 (plus:SI (eq:SI (match_dup 1)
11532 (compare:CC (match_dup 4)
11537 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11540 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11541 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11542 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11544 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11545 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11548 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11549 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11550 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11551 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11552 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11558 [(set_attr "type" "compare")
11559 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11562 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11565 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11566 (match_operand:SI 2 "reg_or_cint_operand" ""))
11567 (match_operand:SI 3 "gpc_reg_operand" ""))
11569 (set (match_operand:SI 0 "gpc_reg_operand" "")
11570 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11571 "TARGET_32BIT && reload_completed"
11572 [(set (match_dup 0)
11573 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11575 (compare:CC (match_dup 0)
11580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11581 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11582 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11585 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11586 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11587 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11588 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11589 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11590 [(set_attr "type" "three,two,three,three,three")
11591 (set_attr "length" "12,8,12,12,12")])
11593 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11594 ;; since it nabs/sr is just as fast.
11595 (define_insn "*ne0"
11596 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11597 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11599 (clobber (match_scratch:SI 2 "=&r"))]
11600 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11601 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11602 [(set_attr "type" "two")
11603 (set_attr "length" "8")])
11606 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11607 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11609 (clobber (match_scratch:DI 2 "=&r"))]
11611 "addic %2,%1,-1\;subfe %0,%2,%1"
11612 [(set_attr "type" "two")
11613 (set_attr "length" "8")])
11615 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11618 (plus:SI (lshiftrt:SI
11619 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11621 (match_operand:SI 2 "gpc_reg_operand" "r")))
11622 (clobber (match_scratch:SI 3 "=&r"))]
11624 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11625 [(set_attr "type" "two")
11626 (set_attr "length" "8")])
11629 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11630 (plus:DI (lshiftrt:DI
11631 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11633 (match_operand:DI 2 "gpc_reg_operand" "r")))
11634 (clobber (match_scratch:DI 3 "=&r"))]
11636 "addic %3,%1,-1\;addze %0,%2"
11637 [(set_attr "type" "two")
11638 (set_attr "length" "8")])
11641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11643 (plus:SI (lshiftrt:SI
11644 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11646 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11648 (clobber (match_scratch:SI 3 "=&r,&r"))
11649 (clobber (match_scratch:SI 4 "=X,&r"))]
11652 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11654 [(set_attr "type" "compare")
11655 (set_attr "length" "8,12")])
11658 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11660 (plus:SI (lshiftrt:SI
11661 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11663 (match_operand:SI 2 "gpc_reg_operand" ""))
11665 (clobber (match_scratch:SI 3 ""))
11666 (clobber (match_scratch:SI 4 ""))]
11667 "TARGET_32BIT && reload_completed"
11668 [(parallel [(set (match_dup 3)
11669 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11672 (clobber (match_dup 4))])
11674 (compare:CC (match_dup 3)
11679 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11681 (plus:DI (lshiftrt:DI
11682 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11684 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11686 (clobber (match_scratch:DI 3 "=&r,&r"))]
11689 addic %3,%1,-1\;addze. %3,%2
11691 [(set_attr "type" "compare")
11692 (set_attr "length" "8,12")])
11695 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11697 (plus:DI (lshiftrt:DI
11698 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11700 (match_operand:DI 2 "gpc_reg_operand" ""))
11702 (clobber (match_scratch:DI 3 ""))]
11703 "TARGET_64BIT && reload_completed"
11704 [(set (match_dup 3)
11705 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11709 (compare:CC (match_dup 3)
11714 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11716 (plus:SI (lshiftrt:SI
11717 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11719 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11721 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11722 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11724 (clobber (match_scratch:SI 3 "=&r,&r"))]
11727 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11729 [(set_attr "type" "compare")
11730 (set_attr "length" "8,12")])
11733 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11735 (plus:SI (lshiftrt:SI
11736 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11738 (match_operand:SI 2 "gpc_reg_operand" ""))
11740 (set (match_operand:SI 0 "gpc_reg_operand" "")
11741 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11743 (clobber (match_scratch:SI 3 ""))]
11744 "TARGET_32BIT && reload_completed"
11745 [(parallel [(set (match_dup 0)
11746 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11748 (clobber (match_dup 3))])
11750 (compare:CC (match_dup 0)
11755 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11757 (plus:DI (lshiftrt:DI
11758 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11760 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11762 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11763 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11765 (clobber (match_scratch:DI 3 "=&r,&r"))]
11768 addic %3,%1,-1\;addze. %0,%2
11770 [(set_attr "type" "compare")
11771 (set_attr "length" "8,12")])
11774 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11776 (plus:DI (lshiftrt:DI
11777 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11779 (match_operand:DI 2 "gpc_reg_operand" ""))
11781 (set (match_operand:DI 0 "gpc_reg_operand" "")
11782 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11784 (clobber (match_scratch:DI 3 ""))]
11785 "TARGET_64BIT && reload_completed"
11786 [(parallel [(set (match_dup 0)
11787 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11789 (clobber (match_dup 3))])
11791 (compare:CC (match_dup 0)
11796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11797 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11798 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11799 (clobber (match_scratch:SI 3 "=r,X"))]
11802 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11803 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11804 [(set_attr "length" "12")])
11807 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11809 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11810 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11813 (le:SI (match_dup 1) (match_dup 2)))
11814 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11817 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11818 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11821 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11822 (set_attr "length" "12,12,16,16")])
11825 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11827 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11828 (match_operand:SI 2 "reg_or_short_operand" ""))
11830 (set (match_operand:SI 0 "gpc_reg_operand" "")
11831 (le:SI (match_dup 1) (match_dup 2)))
11832 (clobber (match_scratch:SI 3 ""))]
11833 "TARGET_POWER && reload_completed"
11834 [(parallel [(set (match_dup 0)
11835 (le:SI (match_dup 1) (match_dup 2)))
11836 (clobber (match_dup 3))])
11838 (compare:CC (match_dup 0)
11843 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11844 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11845 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11846 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11849 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11850 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11851 [(set_attr "length" "12")])
11854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11856 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11857 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11858 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11860 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11863 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11864 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11867 [(set_attr "type" "compare")
11868 (set_attr "length" "12,12,16,16")])
11871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11873 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11874 (match_operand:SI 2 "reg_or_short_operand" ""))
11875 (match_operand:SI 3 "gpc_reg_operand" ""))
11877 (clobber (match_scratch:SI 4 ""))]
11878 "TARGET_POWER && reload_completed"
11879 [(set (match_dup 4)
11880 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11883 (compare:CC (match_dup 4)
11888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11890 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11891 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11892 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11894 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11895 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11898 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11899 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11902 [(set_attr "type" "compare")
11903 (set_attr "length" "12,12,16,16")])
11906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11908 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11909 (match_operand:SI 2 "reg_or_short_operand" ""))
11910 (match_operand:SI 3 "gpc_reg_operand" ""))
11912 (set (match_operand:SI 0 "gpc_reg_operand" "")
11913 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11914 "TARGET_POWER && reload_completed"
11915 [(set (match_dup 0)
11916 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11918 (compare:CC (match_dup 0)
11923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11924 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11925 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11928 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11929 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11930 [(set_attr "length" "12")])
11933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11934 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11935 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11937 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11938 [(set_attr "type" "three")
11939 (set_attr "length" "12")])
11942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11943 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11944 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11946 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11947 [(set_attr "type" "three")
11948 (set_attr "length" "12")])
11951 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11953 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11954 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11956 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11957 (leu:DI (match_dup 1) (match_dup 2)))]
11960 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11962 [(set_attr "type" "compare")
11963 (set_attr "length" "12,16")])
11966 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11968 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11969 (match_operand:DI 2 "reg_or_short_operand" ""))
11971 (set (match_operand:DI 0 "gpc_reg_operand" "")
11972 (leu:DI (match_dup 1) (match_dup 2)))]
11973 "TARGET_64BIT && reload_completed"
11974 [(set (match_dup 0)
11975 (leu:DI (match_dup 1) (match_dup 2)))
11977 (compare:CC (match_dup 0)
11982 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11984 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11985 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11987 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11988 (leu:SI (match_dup 1) (match_dup 2)))]
11991 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11993 [(set_attr "type" "compare")
11994 (set_attr "length" "12,16")])
11997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11999 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12000 (match_operand:SI 2 "reg_or_short_operand" ""))
12002 (set (match_operand:SI 0 "gpc_reg_operand" "")
12003 (leu:SI (match_dup 1) (match_dup 2)))]
12004 "TARGET_32BIT && reload_completed"
12005 [(set (match_dup 0)
12006 (leu:SI (match_dup 1) (match_dup 2)))
12008 (compare:CC (match_dup 0)
12013 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12014 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12015 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12016 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12018 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12019 [(set_attr "type" "two")
12020 (set_attr "length" "8")])
12023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12025 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12026 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12027 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12029 (clobber (match_scratch:SI 4 "=&r,&r"))]
12032 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12034 [(set_attr "type" "compare")
12035 (set_attr "length" "8,12")])
12038 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12040 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12041 (match_operand:SI 2 "reg_or_short_operand" ""))
12042 (match_operand:SI 3 "gpc_reg_operand" ""))
12044 (clobber (match_scratch:SI 4 ""))]
12045 "TARGET_32BIT && reload_completed"
12046 [(set (match_dup 4)
12047 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12050 (compare:CC (match_dup 4)
12055 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12057 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12058 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12059 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12061 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12062 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12065 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12067 [(set_attr "type" "compare")
12068 (set_attr "length" "8,12")])
12071 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12073 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12074 (match_operand:SI 2 "reg_or_short_operand" ""))
12075 (match_operand:SI 3 "gpc_reg_operand" ""))
12077 (set (match_operand:SI 0 "gpc_reg_operand" "")
12078 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12079 "TARGET_32BIT && reload_completed"
12080 [(set (match_dup 0)
12081 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12083 (compare:CC (match_dup 0)
12088 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12089 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12090 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12092 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12093 [(set_attr "type" "three")
12094 (set_attr "length" "12")])
12097 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12099 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12100 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12101 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12103 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12104 [(set_attr "type" "three")
12105 (set_attr "length" "12")])
12108 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12111 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12112 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12113 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12115 (clobber (match_scratch:SI 4 "=&r,&r"))]
12118 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12120 [(set_attr "type" "compare")
12121 (set_attr "length" "12,16")])
12124 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12127 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12128 (match_operand:SI 2 "reg_or_short_operand" "")))
12129 (match_operand:SI 3 "gpc_reg_operand" ""))
12131 (clobber (match_scratch:SI 4 ""))]
12132 "TARGET_32BIT && reload_completed"
12133 [(set (match_dup 4)
12134 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12137 (compare:CC (match_dup 4)
12142 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12145 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12146 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12147 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12149 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12150 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12153 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12155 [(set_attr "type" "compare")
12156 (set_attr "length" "12,16")])
12159 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12162 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12163 (match_operand:SI 2 "reg_or_short_operand" "")))
12164 (match_operand:SI 3 "gpc_reg_operand" ""))
12166 (set (match_operand:SI 0 "gpc_reg_operand" "")
12167 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12168 "TARGET_32BIT && reload_completed"
12169 [(set (match_dup 0)
12170 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12173 (compare:CC (match_dup 0)
12178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12179 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12180 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12182 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12183 [(set_attr "length" "12")])
12186 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12188 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12189 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12191 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12192 (lt:SI (match_dup 1) (match_dup 2)))]
12195 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12197 [(set_attr "type" "delayed_compare")
12198 (set_attr "length" "12,16")])
12201 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12203 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12204 (match_operand:SI 2 "reg_or_short_operand" ""))
12206 (set (match_operand:SI 0 "gpc_reg_operand" "")
12207 (lt:SI (match_dup 1) (match_dup 2)))]
12208 "TARGET_POWER && reload_completed"
12209 [(set (match_dup 0)
12210 (lt:SI (match_dup 1) (match_dup 2)))
12212 (compare:CC (match_dup 0)
12217 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12218 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12219 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12220 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12222 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12223 [(set_attr "length" "12")])
12226 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12228 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12229 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12230 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12232 (clobber (match_scratch:SI 4 "=&r,&r"))]
12235 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12237 [(set_attr "type" "compare")
12238 (set_attr "length" "12,16")])
12241 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12243 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12244 (match_operand:SI 2 "reg_or_short_operand" ""))
12245 (match_operand:SI 3 "gpc_reg_operand" ""))
12247 (clobber (match_scratch:SI 4 ""))]
12248 "TARGET_POWER && reload_completed"
12249 [(set (match_dup 4)
12250 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12253 (compare:CC (match_dup 4)
12258 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12260 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12261 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12262 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12264 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12265 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12268 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "12,16")])
12274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12276 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12277 (match_operand:SI 2 "reg_or_short_operand" ""))
12278 (match_operand:SI 3 "gpc_reg_operand" ""))
12280 (set (match_operand:SI 0 "gpc_reg_operand" "")
12281 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12282 "TARGET_POWER && reload_completed"
12283 [(set (match_dup 0)
12284 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12286 (compare:CC (match_dup 0)
12291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12292 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12293 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12295 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12296 [(set_attr "length" "12")])
12298 (define_insn_and_split ""
12299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12300 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12301 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12305 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12306 (set (match_dup 0) (neg:SI (match_dup 0)))]
12309 (define_insn_and_split ""
12310 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12311 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12312 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12316 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12317 (set (match_dup 0) (neg:DI (match_dup 0)))]
12321 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12323 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12324 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12327 (ltu:SI (match_dup 1) (match_dup 2)))]
12330 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12331 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12334 [(set_attr "type" "compare")
12335 (set_attr "length" "12,12,16,16")])
12338 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12340 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12341 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12343 (set (match_operand:SI 0 "gpc_reg_operand" "")
12344 (ltu:SI (match_dup 1) (match_dup 2)))]
12345 "TARGET_32BIT && reload_completed"
12346 [(set (match_dup 0)
12347 (ltu:SI (match_dup 1) (match_dup 2)))
12349 (compare:CC (match_dup 0)
12353 (define_insn_and_split ""
12354 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12355 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12356 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12357 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12360 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12361 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12362 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12365 (define_insn_and_split ""
12366 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12367 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12368 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12369 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12372 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12373 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12374 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12380 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12381 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12382 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12384 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12387 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12388 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12391 [(set_attr "type" "compare")
12392 (set_attr "length" "12,12,16,16")])
12395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12397 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12398 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12399 (match_operand:SI 3 "gpc_reg_operand" ""))
12401 (clobber (match_scratch:SI 4 ""))]
12402 "TARGET_32BIT && reload_completed"
12403 [(set (match_dup 4)
12404 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12407 (compare:CC (match_dup 4)
12412 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12414 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12415 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12416 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12418 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12419 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12422 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12423 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12426 [(set_attr "type" "compare")
12427 (set_attr "length" "12,12,16,16")])
12430 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12432 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12433 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12434 (match_operand:SI 3 "gpc_reg_operand" ""))
12436 (set (match_operand:SI 0 "gpc_reg_operand" "")
12437 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12438 "TARGET_32BIT && reload_completed"
12439 [(set (match_dup 0)
12440 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12442 (compare:CC (match_dup 0)
12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12448 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12449 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12452 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12453 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12454 [(set_attr "type" "two")
12455 (set_attr "length" "8")])
12458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12459 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12460 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12463 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12464 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12465 [(set_attr "type" "two")
12466 (set_attr "length" "8")])
12469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12470 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12471 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12472 (clobber (match_scratch:SI 3 "=r"))]
12474 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12475 [(set_attr "length" "12")])
12478 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12480 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12481 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12483 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12484 (ge:SI (match_dup 1) (match_dup 2)))
12485 (clobber (match_scratch:SI 3 "=r,r"))]
12488 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12490 [(set_attr "type" "compare")
12491 (set_attr "length" "12,16")])
12494 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12496 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12497 (match_operand:SI 2 "reg_or_short_operand" ""))
12499 (set (match_operand:SI 0 "gpc_reg_operand" "")
12500 (ge:SI (match_dup 1) (match_dup 2)))
12501 (clobber (match_scratch:SI 3 ""))]
12502 "TARGET_POWER && reload_completed"
12503 [(parallel [(set (match_dup 0)
12504 (ge:SI (match_dup 1) (match_dup 2)))
12505 (clobber (match_dup 3))])
12507 (compare:CC (match_dup 0)
12512 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12513 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12514 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12515 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12517 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12518 [(set_attr "length" "12")])
12521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12523 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12524 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12525 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12527 (clobber (match_scratch:SI 4 "=&r,&r"))]
12530 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12532 [(set_attr "type" "compare")
12533 (set_attr "length" "12,16")])
12536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12538 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12539 (match_operand:SI 2 "reg_or_short_operand" ""))
12540 (match_operand:SI 3 "gpc_reg_operand" ""))
12542 (clobber (match_scratch:SI 4 ""))]
12543 "TARGET_POWER && reload_completed"
12544 [(set (match_dup 4)
12545 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12548 (compare:CC (match_dup 4)
12553 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12555 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12556 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12557 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12559 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12560 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12563 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12565 [(set_attr "type" "compare")
12566 (set_attr "length" "12,16")])
12569 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12571 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12572 (match_operand:SI 2 "reg_or_short_operand" ""))
12573 (match_operand:SI 3 "gpc_reg_operand" ""))
12575 (set (match_operand:SI 0 "gpc_reg_operand" "")
12576 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12577 "TARGET_POWER && reload_completed"
12578 [(set (match_dup 0)
12579 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12581 (compare:CC (match_dup 0)
12586 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12587 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12588 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12590 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12591 [(set_attr "length" "12")])
12594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12595 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12596 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12599 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12600 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12601 [(set_attr "type" "three")
12602 (set_attr "length" "12")])
12605 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12606 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12607 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12610 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12611 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12612 [(set_attr "type" "three")
12613 (set_attr "length" "12")])
12616 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12618 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12619 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12621 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12622 (geu:SI (match_dup 1) (match_dup 2)))]
12625 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12626 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12629 [(set_attr "type" "compare")
12630 (set_attr "length" "12,12,16,16")])
12633 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12635 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12636 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12638 (set (match_operand:SI 0 "gpc_reg_operand" "")
12639 (geu:SI (match_dup 1) (match_dup 2)))]
12640 "TARGET_32BIT && reload_completed"
12641 [(set (match_dup 0)
12642 (geu:SI (match_dup 1) (match_dup 2)))
12644 (compare:CC (match_dup 0)
12649 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12651 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12652 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12655 (geu:DI (match_dup 1) (match_dup 2)))]
12658 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12659 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12662 [(set_attr "type" "compare")
12663 (set_attr "length" "12,12,16,16")])
12666 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12668 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12669 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12671 (set (match_operand:DI 0 "gpc_reg_operand" "")
12672 (geu:DI (match_dup 1) (match_dup 2)))]
12673 "TARGET_64BIT && reload_completed"
12674 [(set (match_dup 0)
12675 (geu:DI (match_dup 1) (match_dup 2)))
12677 (compare:CC (match_dup 0)
12682 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12683 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12684 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12685 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12688 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12689 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12690 [(set_attr "type" "two")
12691 (set_attr "length" "8")])
12694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12696 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12697 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12698 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12700 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12703 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12704 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12707 [(set_attr "type" "compare")
12708 (set_attr "length" "8,8,12,12")])
12711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12713 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12714 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12715 (match_operand:SI 3 "gpc_reg_operand" ""))
12717 (clobber (match_scratch:SI 4 ""))]
12718 "TARGET_32BIT && reload_completed"
12719 [(set (match_dup 4)
12720 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12723 (compare:CC (match_dup 4)
12728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12730 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12731 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12732 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12735 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12738 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12739 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12742 [(set_attr "type" "compare")
12743 (set_attr "length" "8,8,12,12")])
12746 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12748 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12749 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12750 (match_operand:SI 3 "gpc_reg_operand" ""))
12752 (set (match_operand:SI 0 "gpc_reg_operand" "")
12753 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12754 "TARGET_32BIT && reload_completed"
12755 [(set (match_dup 0)
12756 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12758 (compare:CC (match_dup 0)
12763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12764 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12765 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12768 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12769 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12770 [(set_attr "type" "three")
12771 (set_attr "length" "12")])
12774 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12776 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12777 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12778 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12781 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12782 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12783 [(set_attr "type" "three")
12784 (set_attr "length" "12")])
12787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12790 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12791 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12792 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12794 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12797 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12798 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12801 [(set_attr "type" "compare")
12802 (set_attr "length" "12,12,16,16")])
12805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12808 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12809 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12810 (match_operand:SI 3 "gpc_reg_operand" ""))
12812 (clobber (match_scratch:SI 4 ""))]
12813 "TARGET_32BIT && reload_completed"
12814 [(set (match_dup 4)
12815 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12818 (compare:CC (match_dup 4)
12823 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12826 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12827 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12828 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12830 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12831 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12834 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12835 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12838 [(set_attr "type" "compare")
12839 (set_attr "length" "12,12,16,16")])
12842 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12845 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12846 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12847 (match_operand:SI 3 "gpc_reg_operand" ""))
12849 (set (match_operand:SI 0 "gpc_reg_operand" "")
12850 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12851 "TARGET_32BIT && reload_completed"
12852 [(set (match_dup 0)
12853 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12855 (compare:CC (match_dup 0)
12860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12861 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12864 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12865 [(set_attr "type" "three")
12866 (set_attr "length" "12")])
12869 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12870 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12873 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12874 [(set_attr "type" "three")
12875 (set_attr "length" "12")])
12878 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12880 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12884 (gt:SI (match_dup 1) (const_int 0)))]
12887 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12889 [(set_attr "type" "delayed_compare")
12890 (set_attr "length" "12,16")])
12893 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12895 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12898 (set (match_operand:SI 0 "gpc_reg_operand" "")
12899 (gt:SI (match_dup 1) (const_int 0)))]
12900 "TARGET_32BIT && reload_completed"
12901 [(set (match_dup 0)
12902 (gt:SI (match_dup 1) (const_int 0)))
12904 (compare:CC (match_dup 0)
12909 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12911 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12914 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12915 (gt:DI (match_dup 1) (const_int 0)))]
12918 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12920 [(set_attr "type" "delayed_compare")
12921 (set_attr "length" "12,16")])
12924 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12926 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12929 (set (match_operand:DI 0 "gpc_reg_operand" "")
12930 (gt:DI (match_dup 1) (const_int 0)))]
12931 "TARGET_64BIT && reload_completed"
12932 [(set (match_dup 0)
12933 (gt:DI (match_dup 1) (const_int 0)))
12935 (compare:CC (match_dup 0)
12940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12941 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12942 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12944 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12945 [(set_attr "length" "12")])
12948 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12950 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12951 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12954 (gt:SI (match_dup 1) (match_dup 2)))]
12957 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12959 [(set_attr "type" "delayed_compare")
12960 (set_attr "length" "12,16")])
12963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12965 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12966 (match_operand:SI 2 "reg_or_short_operand" ""))
12968 (set (match_operand:SI 0 "gpc_reg_operand" "")
12969 (gt:SI (match_dup 1) (match_dup 2)))]
12970 "TARGET_POWER && reload_completed"
12971 [(set (match_dup 0)
12972 (gt:SI (match_dup 1) (match_dup 2)))
12974 (compare:CC (match_dup 0)
12979 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12980 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12982 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12984 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12985 [(set_attr "type" "three")
12986 (set_attr "length" "12")])
12989 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12990 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12992 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12994 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12995 [(set_attr "type" "three")
12996 (set_attr "length" "12")])
12999 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13001 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13003 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13005 (clobber (match_scratch:SI 3 "=&r,&r"))]
13008 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13010 [(set_attr "type" "compare")
13011 (set_attr "length" "12,16")])
13014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13016 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13018 (match_operand:SI 2 "gpc_reg_operand" ""))
13020 (clobber (match_scratch:SI 3 ""))]
13021 "TARGET_32BIT && reload_completed"
13022 [(set (match_dup 3)
13023 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13026 (compare:CC (match_dup 3)
13031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13033 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13035 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13037 (clobber (match_scratch:DI 3 "=&r,&r"))]
13040 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13042 [(set_attr "type" "compare")
13043 (set_attr "length" "12,16")])
13046 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13048 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13050 (match_operand:DI 2 "gpc_reg_operand" ""))
13052 (clobber (match_scratch:DI 3 ""))]
13053 "TARGET_64BIT && reload_completed"
13054 [(set (match_dup 3)
13055 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13058 (compare:CC (match_dup 3)
13063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13065 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13067 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13069 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13070 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13073 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13075 [(set_attr "type" "compare")
13076 (set_attr "length" "12,16")])
13079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13081 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13083 (match_operand:SI 2 "gpc_reg_operand" ""))
13085 (set (match_operand:SI 0 "gpc_reg_operand" "")
13086 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13087 "TARGET_32BIT && reload_completed"
13088 [(set (match_dup 0)
13089 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13091 (compare:CC (match_dup 0)
13096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13098 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13100 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13102 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13103 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13106 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13108 [(set_attr "type" "compare")
13109 (set_attr "length" "12,16")])
13112 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13114 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13116 (match_operand:DI 2 "gpc_reg_operand" ""))
13118 (set (match_operand:DI 0 "gpc_reg_operand" "")
13119 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13120 "TARGET_64BIT && reload_completed"
13121 [(set (match_dup 0)
13122 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13124 (compare:CC (match_dup 0)
13129 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13130 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13131 (match_operand:SI 2 "reg_or_short_operand" "r"))
13132 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13134 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13135 [(set_attr "length" "12")])
13138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13140 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13141 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13142 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13144 (clobber (match_scratch:SI 4 "=&r,&r"))]
13147 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13149 [(set_attr "type" "compare")
13150 (set_attr "length" "12,16")])
13153 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13155 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13156 (match_operand:SI 2 "reg_or_short_operand" ""))
13157 (match_operand:SI 3 "gpc_reg_operand" ""))
13159 (clobber (match_scratch:SI 4 ""))]
13160 "TARGET_POWER && reload_completed"
13161 [(set (match_dup 4)
13162 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13164 (compare:CC (match_dup 4)
13169 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13171 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13172 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13173 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13175 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13176 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13179 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13181 [(set_attr "type" "compare")
13182 (set_attr "length" "12,16")])
13185 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13187 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13188 (match_operand:SI 2 "reg_or_short_operand" ""))
13189 (match_operand:SI 3 "gpc_reg_operand" ""))
13191 (set (match_operand:SI 0 "gpc_reg_operand" "")
13192 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13193 "TARGET_POWER && reload_completed"
13194 [(set (match_dup 0)
13195 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13197 (compare:CC (match_dup 0)
13202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13203 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13206 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13207 [(set_attr "type" "three")
13208 (set_attr "length" "12")])
13211 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13212 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13215 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13216 [(set_attr "type" "three")
13217 (set_attr "length" "12")])
13220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13221 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13222 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13224 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13225 [(set_attr "length" "12")])
13227 (define_insn_and_split ""
13228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13229 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13230 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13234 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13235 (set (match_dup 0) (neg:SI (match_dup 0)))]
13238 (define_insn_and_split ""
13239 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13240 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13241 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13245 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13246 (set (match_dup 0) (neg:DI (match_dup 0)))]
13250 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13252 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13253 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13256 (gtu:SI (match_dup 1) (match_dup 2)))]
13259 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13261 [(set_attr "type" "compare")
13262 (set_attr "length" "12,16")])
13265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13267 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13268 (match_operand:SI 2 "reg_or_short_operand" ""))
13270 (set (match_operand:SI 0 "gpc_reg_operand" "")
13271 (gtu:SI (match_dup 1) (match_dup 2)))]
13272 "TARGET_32BIT && reload_completed"
13273 [(set (match_dup 0)
13274 (gtu:SI (match_dup 1) (match_dup 2)))
13276 (compare:CC (match_dup 0)
13281 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13283 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13284 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13286 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13287 (gtu:DI (match_dup 1) (match_dup 2)))]
13290 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13292 [(set_attr "type" "compare")
13293 (set_attr "length" "12,16")])
13296 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13298 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13299 (match_operand:DI 2 "reg_or_short_operand" ""))
13301 (set (match_operand:DI 0 "gpc_reg_operand" "")
13302 (gtu:DI (match_dup 1) (match_dup 2)))]
13303 "TARGET_64BIT && reload_completed"
13304 [(set (match_dup 0)
13305 (gtu:DI (match_dup 1) (match_dup 2)))
13307 (compare:CC (match_dup 0)
13311 (define_insn_and_split ""
13312 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13313 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13314 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13315 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13318 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13319 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13320 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13323 (define_insn_and_split ""
13324 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13325 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13326 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13327 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13330 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13331 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13332 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13338 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13339 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13340 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13342 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13345 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13346 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13349 [(set_attr "type" "compare")
13350 (set_attr "length" "8,12,12,16")])
13353 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13355 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13356 (match_operand:SI 2 "reg_or_short_operand" ""))
13357 (match_operand:SI 3 "gpc_reg_operand" ""))
13359 (clobber (match_scratch:SI 4 ""))]
13360 "TARGET_32BIT && reload_completed"
13361 [(set (match_dup 4)
13362 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13365 (compare:CC (match_dup 4)
13370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13372 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13373 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13374 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13376 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13379 addic %4,%1,%k2\;addze. %4,%3
13380 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13383 [(set_attr "type" "compare")
13384 (set_attr "length" "8,12,12,16")])
13387 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13389 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13390 (match_operand:DI 2 "reg_or_short_operand" ""))
13391 (match_operand:DI 3 "gpc_reg_operand" ""))
13393 (clobber (match_scratch:DI 4 ""))]
13394 "TARGET_64BIT && reload_completed"
13395 [(set (match_dup 4)
13396 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13399 (compare:CC (match_dup 4)
13404 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13406 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13407 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13408 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13410 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13411 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13414 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13415 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13418 [(set_attr "type" "compare")
13419 (set_attr "length" "8,12,12,16")])
13422 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13424 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13425 (match_operand:SI 2 "reg_or_short_operand" ""))
13426 (match_operand:SI 3 "gpc_reg_operand" ""))
13428 (set (match_operand:SI 0 "gpc_reg_operand" "")
13429 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13430 "TARGET_32BIT && reload_completed"
13431 [(set (match_dup 0)
13432 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13434 (compare:CC (match_dup 0)
13439 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13441 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13442 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13443 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13445 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13446 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13449 addic %0,%1,%k2\;addze. %0,%3
13450 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13453 [(set_attr "type" "compare")
13454 (set_attr "length" "8,12,12,16")])
13457 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13459 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13460 (match_operand:DI 2 "reg_or_short_operand" ""))
13461 (match_operand:DI 3 "gpc_reg_operand" ""))
13463 (set (match_operand:DI 0 "gpc_reg_operand" "")
13464 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13465 "TARGET_64BIT && reload_completed"
13466 [(set (match_dup 0)
13467 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13469 (compare:CC (match_dup 0)
13474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13475 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13476 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13478 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13479 [(set_attr "type" "two")
13480 (set_attr "length" "8")])
13483 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13484 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13485 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13487 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13488 [(set_attr "type" "two")
13489 (set_attr "length" "8")])
13491 ;; Define both directions of branch and return. If we need a reload
13492 ;; register, we'd rather use CR0 since it is much easier to copy a
13493 ;; register CC value to there.
13497 (if_then_else (match_operator 1 "branch_comparison_operator"
13499 "cc_reg_operand" "y")
13501 (label_ref (match_operand 0 "" ""))
13506 return output_cbranch (operands[1], \"%l0\", 0, insn);
13508 [(set_attr "type" "branch")])
13512 (if_then_else (match_operator 0 "branch_comparison_operator"
13514 "cc_reg_operand" "y")
13521 return output_cbranch (operands[0], NULL, 0, insn);
13523 [(set_attr "type" "branch")
13524 (set_attr "length" "4")])
13528 (if_then_else (match_operator 1 "branch_comparison_operator"
13530 "cc_reg_operand" "y")
13533 (label_ref (match_operand 0 "" ""))))]
13537 return output_cbranch (operands[1], \"%l0\", 1, insn);
13539 [(set_attr "type" "branch")])
13543 (if_then_else (match_operator 0 "branch_comparison_operator"
13545 "cc_reg_operand" "y")
13552 return output_cbranch (operands[0], NULL, 1, insn);
13554 [(set_attr "type" "branch")
13555 (set_attr "length" "4")])
13557 ;; Logic on condition register values.
13559 ; This pattern matches things like
13560 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13561 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13563 ; which are generated by the branch logic.
13564 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13566 (define_insn "*cceq_ior_compare"
13567 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13568 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13569 [(match_operator:SI 2
13570 "branch_positive_comparison_operator"
13572 "cc_reg_operand" "y,y")
13574 (match_operator:SI 4
13575 "branch_positive_comparison_operator"
13577 "cc_reg_operand" "0,y")
13581 "cr%q1 %E0,%j2,%j4"
13582 [(set_attr "type" "cr_logical,delayed_cr")])
13584 ; Why is the constant -1 here, but 1 in the previous pattern?
13585 ; Because ~1 has all but the low bit set.
13587 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13588 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13589 [(not:SI (match_operator:SI 2
13590 "branch_positive_comparison_operator"
13592 "cc_reg_operand" "y,y")
13594 (match_operator:SI 4
13595 "branch_positive_comparison_operator"
13597 "cc_reg_operand" "0,y")
13601 "cr%q1 %E0,%j2,%j4"
13602 [(set_attr "type" "cr_logical,delayed_cr")])
13604 (define_insn "*cceq_rev_compare"
13605 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13606 (compare:CCEQ (match_operator:SI 1
13607 "branch_positive_comparison_operator"
13609 "cc_reg_operand" "0,y")
13613 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13614 [(set_attr "type" "cr_logical,delayed_cr")])
13616 ;; If we are comparing the result of two comparisons, this can be done
13617 ;; using creqv or crxor.
13619 (define_insn_and_split ""
13620 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13621 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13622 [(match_operand 2 "cc_reg_operand" "y")
13624 (match_operator 3 "branch_comparison_operator"
13625 [(match_operand 4 "cc_reg_operand" "y")
13630 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13634 int positive_1, positive_2;
13636 positive_1 = branch_positive_comparison_operator (operands[1],
13637 GET_MODE (operands[1]));
13638 positive_2 = branch_positive_comparison_operator (operands[3],
13639 GET_MODE (operands[3]));
13642 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13643 GET_CODE (operands[1])),
13645 operands[2], const0_rtx);
13646 else if (GET_MODE (operands[1]) != SImode)
13647 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13648 operands[2], const0_rtx);
13651 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13652 GET_CODE (operands[3])),
13654 operands[4], const0_rtx);
13655 else if (GET_MODE (operands[3]) != SImode)
13656 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13657 operands[4], const0_rtx);
13659 if (positive_1 == positive_2)
13661 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13662 operands[5] = constm1_rtx;
13666 operands[5] = const1_rtx;
13670 ;; Unconditional branch and return.
13672 (define_insn "jump"
13674 (label_ref (match_operand 0 "" "")))]
13677 [(set_attr "type" "branch")])
13679 (define_insn "return"
13683 [(set_attr "type" "jmpreg")])
13685 (define_expand "indirect_jump"
13686 [(set (pc) (match_operand 0 "register_operand" ""))]
13691 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13693 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13697 (define_insn "indirect_jumpsi"
13698 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13703 [(set_attr "type" "jmpreg")])
13705 (define_insn "indirect_jumpdi"
13706 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13711 [(set_attr "type" "jmpreg")])
13713 ;; Table jump for switch statements:
13714 (define_expand "tablejump"
13715 [(use (match_operand 0 "" ""))
13716 (use (label_ref (match_operand 1 "" "")))]
13721 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13723 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13727 (define_expand "tablejumpsi"
13728 [(set (match_dup 3)
13729 (plus:SI (match_operand:SI 0 "" "")
13731 (parallel [(set (pc) (match_dup 3))
13732 (use (label_ref (match_operand 1 "" "")))])]
13735 { operands[0] = force_reg (SImode, operands[0]);
13736 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13737 operands[3] = gen_reg_rtx (SImode);
13740 (define_expand "tablejumpdi"
13741 [(set (match_dup 4)
13742 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13744 (plus:DI (match_dup 4)
13746 (parallel [(set (pc) (match_dup 3))
13747 (use (label_ref (match_operand 1 "" "")))])]
13750 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13751 operands[3] = gen_reg_rtx (DImode);
13752 operands[4] = gen_reg_rtx (DImode);
13757 (match_operand:SI 0 "register_operand" "c,*l"))
13758 (use (label_ref (match_operand 1 "" "")))]
13763 [(set_attr "type" "jmpreg")])
13767 (match_operand:DI 0 "register_operand" "c,*l"))
13768 (use (label_ref (match_operand 1 "" "")))]
13773 [(set_attr "type" "jmpreg")])
13778 "{cror 0,0,0|nop}")
13780 ;; Define the subtract-one-and-jump insns, starting with the template
13781 ;; so loop.c knows what to generate.
13783 (define_expand "doloop_end"
13784 [(use (match_operand 0 "" "")) ; loop pseudo
13785 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13786 (use (match_operand 2 "" "")) ; max iterations
13787 (use (match_operand 3 "" "")) ; loop level
13788 (use (match_operand 4 "" ""))] ; label
13792 /* Only use this on innermost loops. */
13793 if (INTVAL (operands[3]) > 1)
13797 if (GET_MODE (operands[0]) != DImode)
13799 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13803 if (GET_MODE (operands[0]) != SImode)
13805 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13810 (define_expand "ctrsi"
13811 [(parallel [(set (pc)
13812 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13814 (label_ref (match_operand 1 "" ""))
13817 (plus:SI (match_dup 0)
13819 (clobber (match_scratch:CC 2 ""))
13820 (clobber (match_scratch:SI 3 ""))])]
13824 (define_expand "ctrdi"
13825 [(parallel [(set (pc)
13826 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13828 (label_ref (match_operand 1 "" ""))
13831 (plus:DI (match_dup 0)
13833 (clobber (match_scratch:CC 2 ""))
13834 (clobber (match_scratch:DI 3 ""))])]
13838 ;; We need to be able to do this for any operand, including MEM, or we
13839 ;; will cause reload to blow up since we don't allow output reloads on
13841 ;; For the length attribute to be calculated correctly, the
13842 ;; label MUST be operand 0.
13844 (define_insn "*ctrsi_internal1"
13846 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13848 (label_ref (match_operand 0 "" ""))
13850 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13851 (plus:SI (match_dup 1)
13853 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13854 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13858 if (which_alternative != 0)
13860 else if (get_attr_length (insn) == 4)
13861 return \"{bdn|bdnz} %l0\";
13863 return \"bdz $+8\;b %l0\";
13865 [(set_attr "type" "branch")
13866 (set_attr "length" "*,12,16,16")])
13868 (define_insn "*ctrsi_internal2"
13870 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13873 (label_ref (match_operand 0 "" ""))))
13874 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13875 (plus:SI (match_dup 1)
13877 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13878 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13882 if (which_alternative != 0)
13884 else if (get_attr_length (insn) == 4)
13885 return \"bdz %l0\";
13887 return \"{bdn|bdnz} $+8\;b %l0\";
13889 [(set_attr "type" "branch")
13890 (set_attr "length" "*,12,16,16")])
13892 (define_insn "*ctrdi_internal1"
13894 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13896 (label_ref (match_operand 0 "" ""))
13898 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13899 (plus:DI (match_dup 1)
13901 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13902 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13906 if (which_alternative != 0)
13908 else if (get_attr_length (insn) == 4)
13909 return \"{bdn|bdnz} %l0\";
13911 return \"bdz $+8\;b %l0\";
13913 [(set_attr "type" "branch")
13914 (set_attr "length" "*,12,16,16")])
13916 (define_insn "*ctrdi_internal2"
13918 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13921 (label_ref (match_operand 0 "" ""))))
13922 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13923 (plus:DI (match_dup 1)
13925 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13926 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13930 if (which_alternative != 0)
13932 else if (get_attr_length (insn) == 4)
13933 return \"bdz %l0\";
13935 return \"{bdn|bdnz} $+8\;b %l0\";
13937 [(set_attr "type" "branch")
13938 (set_attr "length" "*,12,16,16")])
13940 ;; Similar but use EQ
13942 (define_insn "*ctrsi_internal5"
13944 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13946 (label_ref (match_operand 0 "" ""))
13948 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13949 (plus:SI (match_dup 1)
13951 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13952 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13956 if (which_alternative != 0)
13958 else if (get_attr_length (insn) == 4)
13959 return \"bdz %l0\";
13961 return \"{bdn|bdnz} $+8\;b %l0\";
13963 [(set_attr "type" "branch")
13964 (set_attr "length" "*,12,16,16")])
13966 (define_insn "*ctrsi_internal6"
13968 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13971 (label_ref (match_operand 0 "" ""))))
13972 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13973 (plus:SI (match_dup 1)
13975 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13976 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13980 if (which_alternative != 0)
13982 else if (get_attr_length (insn) == 4)
13983 return \"{bdn|bdnz} %l0\";
13985 return \"bdz $+8\;b %l0\";
13987 [(set_attr "type" "branch")
13988 (set_attr "length" "*,12,16,16")])
13990 (define_insn "*ctrdi_internal5"
13992 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13994 (label_ref (match_operand 0 "" ""))
13996 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13997 (plus:DI (match_dup 1)
13999 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14000 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14004 if (which_alternative != 0)
14006 else if (get_attr_length (insn) == 4)
14007 return \"bdz %l0\";
14009 return \"{bdn|bdnz} $+8\;b %l0\";
14011 [(set_attr "type" "branch")
14012 (set_attr "length" "*,12,16,16")])
14014 (define_insn "*ctrdi_internal6"
14016 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14019 (label_ref (match_operand 0 "" ""))))
14020 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14021 (plus:DI (match_dup 1)
14023 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14024 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14028 if (which_alternative != 0)
14030 else if (get_attr_length (insn) == 4)
14031 return \"{bdn|bdnz} %l0\";
14033 return \"bdz $+8\;b %l0\";
14035 [(set_attr "type" "branch")
14036 (set_attr "length" "*,12,16,16")])
14038 ;; Now the splitters if we could not allocate the CTR register
14042 (if_then_else (match_operator 2 "comparison_operator"
14043 [(match_operand:SI 1 "gpc_reg_operand" "")
14045 (match_operand 5 "" "")
14046 (match_operand 6 "" "")))
14047 (set (match_operand:SI 0 "gpc_reg_operand" "")
14048 (plus:SI (match_dup 1)
14050 (clobber (match_scratch:CC 3 ""))
14051 (clobber (match_scratch:SI 4 ""))]
14052 "TARGET_32BIT && reload_completed"
14053 [(parallel [(set (match_dup 3)
14054 (compare:CC (plus:SI (match_dup 1)
14058 (plus:SI (match_dup 1)
14060 (set (pc) (if_then_else (match_dup 7)
14064 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14065 operands[3], const0_rtx); }")
14069 (if_then_else (match_operator 2 "comparison_operator"
14070 [(match_operand:SI 1 "gpc_reg_operand" "")
14072 (match_operand 5 "" "")
14073 (match_operand 6 "" "")))
14074 (set (match_operand:SI 0 "nonimmediate_operand" "")
14075 (plus:SI (match_dup 1) (const_int -1)))
14076 (clobber (match_scratch:CC 3 ""))
14077 (clobber (match_scratch:SI 4 ""))]
14078 "TARGET_32BIT && reload_completed
14079 && ! gpc_reg_operand (operands[0], SImode)"
14080 [(parallel [(set (match_dup 3)
14081 (compare:CC (plus:SI (match_dup 1)
14085 (plus:SI (match_dup 1)
14089 (set (pc) (if_then_else (match_dup 7)
14093 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14094 operands[3], const0_rtx); }")
14097 (if_then_else (match_operator 2 "comparison_operator"
14098 [(match_operand:DI 1 "gpc_reg_operand" "")
14100 (match_operand 5 "" "")
14101 (match_operand 6 "" "")))
14102 (set (match_operand:DI 0 "gpc_reg_operand" "")
14103 (plus:DI (match_dup 1)
14105 (clobber (match_scratch:CC 3 ""))
14106 (clobber (match_scratch:DI 4 ""))]
14107 "TARGET_64BIT && reload_completed"
14108 [(parallel [(set (match_dup 3)
14109 (compare:CC (plus:DI (match_dup 1)
14113 (plus:DI (match_dup 1)
14115 (set (pc) (if_then_else (match_dup 7)
14119 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14120 operands[3], const0_rtx); }")
14124 (if_then_else (match_operator 2 "comparison_operator"
14125 [(match_operand:DI 1 "gpc_reg_operand" "")
14127 (match_operand 5 "" "")
14128 (match_operand 6 "" "")))
14129 (set (match_operand:DI 0 "nonimmediate_operand" "")
14130 (plus:DI (match_dup 1) (const_int -1)))
14131 (clobber (match_scratch:CC 3 ""))
14132 (clobber (match_scratch:DI 4 ""))]
14133 "TARGET_64BIT && reload_completed
14134 && ! gpc_reg_operand (operands[0], DImode)"
14135 [(parallel [(set (match_dup 3)
14136 (compare:CC (plus:DI (match_dup 1)
14140 (plus:DI (match_dup 1)
14144 (set (pc) (if_then_else (match_dup 7)
14148 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14149 operands[3], const0_rtx); }")
14151 (define_insn "trap"
14152 [(trap_if (const_int 1) (const_int 0))]
14156 (define_expand "conditional_trap"
14157 [(trap_if (match_operator 0 "trap_comparison_operator"
14158 [(match_dup 2) (match_dup 3)])
14159 (match_operand 1 "const_int_operand" ""))]
14161 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14162 operands[2] = rs6000_compare_op0;
14163 operands[3] = rs6000_compare_op1;")
14166 [(trap_if (match_operator 0 "trap_comparison_operator"
14167 [(match_operand:SI 1 "register_operand" "r")
14168 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14171 "{t|tw}%V0%I2 %1,%2")
14174 [(trap_if (match_operator 0 "trap_comparison_operator"
14175 [(match_operand:DI 1 "register_operand" "r")
14176 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14181 ;; Insns related to generating the function prologue and epilogue.
14183 (define_expand "prologue"
14184 [(use (const_int 0))]
14185 "TARGET_SCHED_PROLOG"
14188 rs6000_emit_prologue ();
14192 (define_insn "*movesi_from_cr_one"
14193 [(match_parallel 0 "mfcr_operation"
14194 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14195 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14196 (match_operand 3 "immediate_operand" "n")]
14197 UNSPEC_MOVESI_FROM_CR))])]
14203 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14205 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14206 operands[4] = GEN_INT (mask);
14207 output_asm_insn (\"mfcr %1,%4\", operands);
14211 [(set_attr "type" "mfcrf")])
14213 (define_insn "movesi_from_cr"
14214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14215 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14216 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14217 UNSPEC_MOVESI_FROM_CR))]
14220 [(set_attr "type" "mfcr")])
14222 (define_insn "*stmw"
14223 [(match_parallel 0 "stmw_operation"
14224 [(set (match_operand:SI 1 "memory_operand" "=m")
14225 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14227 "{stm|stmw} %2,%1")
14229 (define_insn "*save_fpregs_si"
14230 [(match_parallel 0 "any_parallel_operand"
14231 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14232 (use (match_operand:SI 2 "call_operand" "s"))
14233 (set (match_operand:DF 3 "memory_operand" "=m")
14234 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14237 [(set_attr "type" "branch")
14238 (set_attr "length" "4")])
14240 (define_insn "*save_fpregs_di"
14241 [(match_parallel 0 "any_parallel_operand"
14242 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14243 (use (match_operand:DI 2 "call_operand" "s"))
14244 (set (match_operand:DF 3 "memory_operand" "=m")
14245 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14248 [(set_attr "type" "branch")
14249 (set_attr "length" "4")])
14251 ; These are to explain that changes to the stack pointer should
14252 ; not be moved over stores to stack memory.
14253 (define_insn "stack_tie"
14254 [(set (match_operand:BLK 0 "memory_operand" "+m")
14255 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14258 [(set_attr "length" "0")])
14261 (define_expand "epilogue"
14262 [(use (const_int 0))]
14263 "TARGET_SCHED_PROLOG"
14266 rs6000_emit_epilogue (FALSE);
14270 ; On some processors, doing the mtcrf one CC register at a time is
14271 ; faster (like on the 604e). On others, doing them all at once is
14272 ; faster; for instance, on the 601 and 750.
14274 (define_expand "movsi_to_cr_one"
14275 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14276 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14277 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14279 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14281 (define_insn "*movsi_to_cr"
14282 [(match_parallel 0 "mtcrf_operation"
14283 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14284 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14285 (match_operand 3 "immediate_operand" "n")]
14286 UNSPEC_MOVESI_TO_CR))])]
14292 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14293 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14294 operands[4] = GEN_INT (mask);
14295 return \"mtcrf %4,%2\";
14297 [(set_attr "type" "mtcr")])
14299 (define_insn "*mtcrfsi"
14300 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14301 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14302 (match_operand 2 "immediate_operand" "n")]
14303 UNSPEC_MOVESI_TO_CR))]
14304 "GET_CODE (operands[0]) == REG
14305 && CR_REGNO_P (REGNO (operands[0]))
14306 && GET_CODE (operands[2]) == CONST_INT
14307 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14309 [(set_attr "type" "mtcr")])
14311 ; The load-multiple instructions have similar properties.
14312 ; Note that "load_multiple" is a name known to the machine-independent
14313 ; code that actually corresponds to the powerpc load-string.
14315 (define_insn "*lmw"
14316 [(match_parallel 0 "lmw_operation"
14317 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14318 (match_operand:SI 2 "memory_operand" "m"))])]
14322 (define_insn "*return_internal_si"
14324 (use (match_operand:SI 0 "register_operand" "lc"))]
14327 [(set_attr "type" "jmpreg")])
14329 (define_insn "*return_internal_di"
14331 (use (match_operand:DI 0 "register_operand" "lc"))]
14334 [(set_attr "type" "jmpreg")])
14336 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14337 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14339 (define_insn "*return_and_restore_fpregs_si"
14340 [(match_parallel 0 "any_parallel_operand"
14342 (use (match_operand:SI 1 "register_operand" "l"))
14343 (use (match_operand:SI 2 "call_operand" "s"))
14344 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14345 (match_operand:DF 4 "memory_operand" "m"))])]
14349 (define_insn "*return_and_restore_fpregs_di"
14350 [(match_parallel 0 "any_parallel_operand"
14352 (use (match_operand:DI 1 "register_operand" "l"))
14353 (use (match_operand:DI 2 "call_operand" "s"))
14354 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14355 (match_operand:DF 4 "memory_operand" "m"))])]
14359 ; This is used in compiling the unwind routines.
14360 (define_expand "eh_return"
14361 [(use (match_operand 0 "general_operand" ""))]
14366 emit_insn (gen_eh_set_lr_si (operands[0]));
14368 emit_insn (gen_eh_set_lr_di (operands[0]));
14372 ; We can't expand this before we know where the link register is stored.
14373 (define_insn "eh_set_lr_si"
14374 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14376 (clobber (match_scratch:SI 1 "=&b"))]
14380 (define_insn "eh_set_lr_di"
14381 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14383 (clobber (match_scratch:DI 1 "=&b"))]
14388 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14389 (clobber (match_scratch 1 ""))]
14394 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14398 (define_insn "prefetch"
14399 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14400 (match_operand:SI 1 "const_int_operand" "n")
14401 (match_operand:SI 2 "const_int_operand" "n"))]
14405 if (GET_CODE (operands[0]) == REG)
14406 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14407 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14409 [(set_attr "type" "load")])
14411 ; Atomic instructions
14413 (define_insn "memory_barrier"
14414 [(set (mem:BLK (match_scratch 0 "X"))
14415 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))]
14419 (define_insn "sync_compare_and_swap<mode>"
14420 [(set (match_operand:GPR 1 "memory_operand" "+Z")
14421 (unspec:GPR [(match_dup 1)
14422 (match_operand:GPR 2 "reg_or_short_operand" "rI")
14423 (match_operand:GPR 3 "gpc_reg_operand" "r")]
14425 (set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1))
14426 (set (mem:BLK (match_scratch 5 "X"))
14427 (unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
14428 (clobber (match_scratch:CC 4 "=&x"))]
14430 "sync\n\t<larx> %0,%y1\n\tcmp<wd>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
14431 [(set_attr "length" "28")])
14433 (define_expand "sync_add<mode>"
14434 [(use (match_operand:INT1 0 "memory_operand" ""))
14435 (use (match_operand:INT1 1 "add_operand" ""))]
14439 rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1],
14440 NULL_RTX, NULL_RTX, true);
14444 (define_expand "sync_sub<mode>"
14445 [(use (match_operand:GPR 0 "memory_operand" ""))
14446 (use (match_operand:GPR 1 "gpc_reg_operand" ""))]
14450 rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1],
14451 NULL_RTX, NULL_RTX, true);
14455 (define_expand "sync_ior<mode>"
14456 [(use (match_operand:INT1 0 "memory_operand" ""))
14457 (use (match_operand:INT1 1 "logical_operand" ""))]
14461 rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1],
14462 NULL_RTX, NULL_RTX, true);
14466 (define_expand "sync_and<mode>"
14467 [(use (match_operand:INT1 0 "memory_operand" ""))
14468 (use (match_operand:INT1 1 "and_operand" ""))]
14472 rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1],
14473 NULL_RTX, NULL_RTX, true);
14477 (define_expand "sync_xor<mode>"
14478 [(use (match_operand:INT1 0 "memory_operand" ""))
14479 (use (match_operand:INT1 1 "logical_operand" ""))]
14483 rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1],
14484 NULL_RTX, NULL_RTX, true);
14488 (define_expand "sync_nand<mode>"
14489 [(use (match_operand:INT1 0 "memory_operand" ""))
14490 (use (match_operand:INT1 1 "gpc_reg_operand" ""))]
14494 rs6000_emit_sync (AND, <MODE>mode,
14495 gen_rtx_NOT (<MODE>mode, operands[0]),
14497 NULL_RTX, NULL_RTX, true);
14501 (define_expand "sync_old_add<mode>"
14502 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14503 (use (match_operand:INT1 1 "memory_operand" ""))
14504 (use (match_operand:INT1 2 "add_operand" ""))]
14508 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14509 operands[0], NULL_RTX, true);
14513 (define_expand "sync_old_sub<mode>"
14514 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14515 (use (match_operand:GPR 1 "memory_operand" ""))
14516 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14520 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14521 operands[0], NULL_RTX, true);
14525 (define_expand "sync_old_ior<mode>"
14526 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14527 (use (match_operand:INT1 1 "memory_operand" ""))
14528 (use (match_operand:INT1 2 "logical_operand" ""))]
14532 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14533 operands[0], NULL_RTX, true);
14537 (define_expand "sync_old_and<mode>"
14538 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14539 (use (match_operand:INT1 1 "memory_operand" ""))
14540 (use (match_operand:INT1 2 "and_operand" ""))]
14544 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14545 operands[0], NULL_RTX, true);
14549 (define_expand "sync_old_xor<mode>"
14550 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14551 (use (match_operand:INT1 1 "memory_operand" ""))
14552 (use (match_operand:INT1 2 "logical_operand" ""))]
14556 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14557 operands[0], NULL_RTX, true);
14561 (define_expand "sync_old_nand<mode>"
14562 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14563 (use (match_operand:INT1 1 "memory_operand" ""))
14564 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14568 rs6000_emit_sync (AND, <MODE>mode,
14569 gen_rtx_NOT (<MODE>mode, operands[1]),
14571 operands[0], NULL_RTX, true);
14575 (define_expand "sync_new_add<mode>"
14576 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14577 (use (match_operand:INT1 1 "memory_operand" ""))
14578 (use (match_operand:INT1 2 "add_operand" ""))]
14582 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14583 NULL_RTX, operands[0], true);
14587 (define_expand "sync_new_sub<mode>"
14588 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14589 (use (match_operand:GPR 1 "memory_operand" ""))
14590 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14594 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14595 NULL_RTX, operands[0], true);
14599 (define_expand "sync_new_ior<mode>"
14600 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14601 (use (match_operand:INT1 1 "memory_operand" ""))
14602 (use (match_operand:INT1 2 "logical_operand" ""))]
14606 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14607 NULL_RTX, operands[0], true);
14611 (define_expand "sync_new_and<mode>"
14612 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14613 (use (match_operand:INT1 1 "memory_operand" ""))
14614 (use (match_operand:INT1 2 "and_operand" ""))]
14618 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14619 NULL_RTX, operands[0], true);
14623 (define_expand "sync_new_xor<mode>"
14624 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14625 (use (match_operand:INT1 1 "memory_operand" ""))
14626 (use (match_operand:INT1 2 "logical_operand" ""))]
14630 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14631 NULL_RTX, operands[0], true);
14635 (define_expand "sync_new_nand<mode>"
14636 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14637 (use (match_operand:INT1 1 "memory_operand" ""))
14638 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14642 rs6000_emit_sync (AND, <MODE>mode,
14643 gen_rtx_NOT (<MODE>mode, operands[1]),
14645 NULL_RTX, operands[0], true);
14649 ; the sync_*_internal patterns all have these operands:
14650 ; 0 - memory location
14652 ; 2 - value in memory after operation
14653 ; 3 - value in memory immediately before operation
14655 (define_insn "*sync_add<mode>_internal"
14656 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r")
14657 (plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z")
14658 (match_operand:GPR 1 "add_operand" "rI,L")))
14659 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0))
14661 (unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))]
14663 (clobber (match_scratch:CC 4 "=&x,&x"))]
14666 <larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12
14667 <larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- $-12"
14668 [(set_attr "length" "16,16")])
14670 (define_insn "*sync_addshort_internal"
14671 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
14672 (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
14673 (match_operand:SI 1 "add_operand" "rI"))
14674 (match_operand:SI 4 "gpc_reg_operand" "r"))
14675 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
14676 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
14678 (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
14680 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
14682 (clobber (match_scratch:CC 5 "=&x"))
14683 (clobber (match_scratch:SI 6 "=&r"))]
14685 "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
14686 [(set_attr "length" "28")])
14688 (define_insn "*sync_sub<mode>_internal"
14689 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14690 (minus:GPR (match_operand:GPR 0 "memory_operand" "+Z")
14691 (match_operand:GPR 1 "gpc_reg_operand" "r")))
14692 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14694 (unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))]
14696 (clobber (match_scratch:CC 4 "=&x"))]
14698 "<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14699 [(set_attr "length" "16")])
14701 (define_insn "*sync_andsi_internal"
14702 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
14703 (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
14704 (match_operand:SI 1 "and_operand" "r,T,K,L")))
14705 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
14707 (unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
14709 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
14712 lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14713 lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12
14714 lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14715 lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14716 [(set_attr "length" "16,16,16,16")])
14718 (define_insn "*sync_anddi_internal"
14719 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
14720 (and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z")
14721 (match_operand:DI 1 "and_operand" "r,S,T,K,J")))
14722 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0))
14724 (unspec:DI [(and:DI (match_dup 0) (match_dup 1))]
14726 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
14729 ldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14730 ldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- $-12
14731 ldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- $-12
14732 ldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14733 ldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12"
14734 [(set_attr "length" "16,16,16,16,16")])
14736 (define_insn "*sync_boolsi_internal"
14737 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
14738 (match_operator:SI 4 "boolean_or_operator"
14739 [(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
14740 (match_operand:SI 1 "logical_operand" "r,K,L")]))
14741 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14742 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
14743 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14746 lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14747 lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14748 lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14749 [(set_attr "length" "16,16,16")])
14751 (define_insn "*sync_booldi_internal"
14752 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r")
14753 (match_operator:DI 4 "boolean_or_operator"
14754 [(match_operand:DI 0 "memory_operand" "+Z,Z,Z")
14755 (match_operand:DI 1 "logical_operand" "r,K,JF")]))
14756 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14757 (set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP))
14758 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14761 ldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14762 ldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14763 ldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- $-12"
14764 [(set_attr "length" "16,16,16")])
14766 (define_insn "*sync_boolc<mode>_internal"
14767 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14768 (match_operator:GPR 4 "boolean_operator"
14769 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14770 (match_operand:GPR 1 "gpc_reg_operand" "r")]))
14771 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14772 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14773 (clobber (match_scratch:CC 5 "=&x"))]
14775 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14776 [(set_attr "length" "16")])
14778 (define_insn "*sync_boolc<mode>_internal2"
14779 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14780 (match_operator:GPR 4 "boolean_operator"
14781 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
14782 (match_operand:GPR 0 "memory_operand" "+Z")]))
14783 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14784 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14785 (clobber (match_scratch:CC 5 "=&x"))]
14787 "<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12"
14788 [(set_attr "length" "16")])
14790 (define_insn "*sync_boolcc<mode>_internal"
14791 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14792 (match_operator:GPR 4 "boolean_operator"
14793 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14794 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))]))
14795 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14796 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14797 (clobber (match_scratch:CC 5 "=&x"))]
14799 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14800 [(set_attr "length" "16")])
14802 (define_insn "isync"
14803 [(set (mem:BLK (match_scratch 0 "X"))
14804 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))]
14808 (define_insn "sync_lock_test_and_set<mode>"
14809 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
14810 (match_operand:GPR 1 "memory_operand" "+Z"))
14811 (set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")]
14813 (clobber (match_scratch:CC 3 "=&x"))
14814 (set (mem:BLK (match_scratch 4 "X"))
14815 (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
14817 "<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- $-8\n\tisync"
14818 [(set_attr "length" "16")])
14820 (define_expand "sync_lock_release<mode>"
14821 [(set (match_operand:INT 0 "memory_operand")
14822 (match_operand:INT 1 "any_operand"))]
14826 emit_insn (gen_lwsync ());
14827 emit_move_insn (operands[0], operands[1]);
14831 ; Some AIX assemblers don't accept lwsync, so we use a .long.
14832 (define_insn "lwsync"
14833 [(set (mem:BLK (match_scratch 0 "X"))
14834 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
14836 ".long 0x7c2004ac")
14840 (include "altivec.md")