1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common ASM definitions used by ASM_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define ASM_CPU_SPEC \
52 %{mpower: %{!mpower2: -mpwr}} \
55 %{mno-power: %{!mpowerpc*: -mcom}} \
56 %{!mno-power: %{!mpower2: %(asm_default)}}} \
57 %{mcpu=common: -mcom} \
58 %{mcpu=power: -mpwr} \
59 %{mcpu=power2: -mpwrx} \
60 %{mcpu=power3: -m604} \
61 %{mcpu=power4: -mpower4} \
62 %{mcpu=powerpc: -mppc} \
64 %{mcpu=rios1: -mpwr} \
65 %{mcpu=rios2: -mpwrx} \
71 %{mcpu=405fp: -m405} \
73 %{mcpu=440fp: -m440} \
79 %{mcpu=ec603e: -mppc} \
92 %{mcpu=8540: -me500} \
93 %{maltivec: -maltivec}"
95 #define CPP_DEFAULT_SPEC ""
97 #define ASM_DEFAULT_SPEC ""
99 /* This macro defines names of additional specifications to put in the specs
100 that can be used in various specifications like CC1_SPEC. Its definition
101 is an initializer with a subgrouping for each command option.
103 Each subgrouping contains a string constant, that defines the
104 specification name, and a string constant that used by the GCC driver
107 Do not define this macro if it does not need to do anything. */
109 #define SUBTARGET_EXTRA_SPECS
111 #define EXTRA_SPECS \
112 { "cpp_default", CPP_DEFAULT_SPEC }, \
113 { "asm_cpu", ASM_CPU_SPEC }, \
114 { "asm_default", ASM_DEFAULT_SPEC }, \
115 SUBTARGET_EXTRA_SPECS
117 /* Architecture type. */
119 extern int target_flags;
121 /* Use POWER architecture instructions and MQ register. */
122 #define MASK_POWER 0x00000001
124 /* Use POWER2 extensions to POWER architecture. */
125 #define MASK_POWER2 0x00000002
127 /* Use PowerPC architecture instructions. */
128 #define MASK_POWERPC 0x00000004
130 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
131 #define MASK_PPC_GPOPT 0x00000008
133 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
134 #define MASK_PPC_GFXOPT 0x00000010
136 /* Use PowerPC-64 architecture instructions. */
137 #define MASK_POWERPC64 0x00000020
139 /* Use revised mnemonic names defined for PowerPC architecture. */
140 #define MASK_NEW_MNEMONICS 0x00000040
142 /* Disable placing fp constants in the TOC; can be turned on when the
144 #define MASK_NO_FP_IN_TOC 0x00000080
146 /* Disable placing symbol+offset constants in the TOC; can be turned on when
147 the TOC overflows. */
148 #define MASK_NO_SUM_IN_TOC 0x00000100
150 /* Output only one TOC entry per module. Normally linking fails if
151 there are more than 16K unique variables/constants in an executable. With
152 this option, linking fails only if there are more than 16K modules, or
153 if there are more than 16K unique variables/constant in a single module.
155 This is at the cost of having 2 extra loads and one extra store per
156 function, and one less allocable register. */
157 #define MASK_MINIMAL_TOC 0x00000200
159 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
160 #define MASK_64BIT 0x00000400
162 /* Disable use of FPRs. */
163 #define MASK_SOFT_FLOAT 0x00000800
165 /* Enable load/store multiple, even on PowerPC */
166 #define MASK_MULTIPLE 0x00001000
168 /* Use string instructions for block moves */
169 #define MASK_STRING 0x00002000
171 /* Disable update form of load/store */
172 #define MASK_NO_UPDATE 0x00004000
174 /* Disable fused multiply/add operations */
175 #define MASK_NO_FUSED_MADD 0x00008000
177 /* Nonzero if we need to schedule the prolog and epilog. */
178 #define MASK_SCHED_PROLOG 0x00010000
180 /* Use AltiVec instructions. */
181 #define MASK_ALTIVEC 0x00020000
183 /* Return small structures in memory (as the AIX ABI requires). */
184 #define MASK_AIX_STRUCT_RET 0x00040000
186 /* The only remaining free bits are 0x00780000. sysv4.h uses
187 0x00800000 -> 0x40000000, and 0x80000000 is not available
188 because target_flags is signed. */
190 #define TARGET_POWER (target_flags & MASK_POWER)
191 #define TARGET_POWER2 (target_flags & MASK_POWER2)
192 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
193 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
194 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
195 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
196 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
197 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
198 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
199 #define TARGET_64BIT (target_flags & MASK_64BIT)
200 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
201 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
202 #define TARGET_STRING (target_flags & MASK_STRING)
203 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
204 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
205 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
206 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
207 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
209 #define TARGET_32BIT (! TARGET_64BIT)
210 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
211 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
212 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
215 #define HAVE_AS_TLS 0
219 /* For libgcc2 we make sure this is a compile time constant */
220 #if defined (__64BIT__) || defined (__powerpc64__)
221 #define TARGET_POWERPC64 1
223 #define TARGET_POWERPC64 0
226 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
229 #define TARGET_XL_CALL 0
231 /* Run-time compilation parameters selecting different hardware subsets.
233 Macro to define tables used to set the flags.
234 This is a list in braces of pairs in braces,
235 each pair being { "NAME", VALUE }
236 where VALUE is the bits to set or minus the bits to clear.
237 An empty string NAME is used to identify the default VALUE. */
239 #define TARGET_SWITCHES \
240 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
241 N_("Use POWER instruction set")}, \
242 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
244 N_("Use POWER2 instruction set")}, \
245 {"no-power2", - MASK_POWER2, \
246 N_("Do not use POWER2 instruction set")}, \
247 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
249 N_("Do not use POWER instruction set")}, \
250 {"powerpc", MASK_POWERPC, \
251 N_("Use PowerPC instruction set")}, \
252 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
253 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
254 N_("Do not use PowerPC instruction set")}, \
255 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
256 N_("Use PowerPC General Purpose group optional instructions")},\
257 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
258 N_("Don't use PowerPC General Purpose group optional instructions")},\
259 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
260 N_("Use PowerPC Graphics group optional instructions")},\
261 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
262 N_("Don't use PowerPC Graphics group optional instructions")},\
263 {"powerpc64", MASK_POWERPC64, \
264 N_("Use PowerPC-64 instruction set")}, \
265 {"no-powerpc64", - MASK_POWERPC64, \
266 N_("Don't use PowerPC-64 instruction set")}, \
267 {"altivec", MASK_ALTIVEC , \
268 N_("Use AltiVec instructions")}, \
269 {"no-altivec", - MASK_ALTIVEC , \
270 N_("Don't use AltiVec instructions")}, \
271 {"new-mnemonics", MASK_NEW_MNEMONICS, \
272 N_("Use new mnemonics for PowerPC architecture")},\
273 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
274 N_("Use old mnemonics for PowerPC architecture")},\
275 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
276 | MASK_MINIMAL_TOC), \
277 N_("Put everything in the regular TOC")}, \
278 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
279 N_("Place floating point constants in TOC")}, \
280 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
281 N_("Don't place floating point constants in TOC")},\
282 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
283 N_("Place symbol+offset constants in TOC")}, \
284 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
285 N_("Don't place symbol+offset constants in TOC")},\
286 {"minimal-toc", MASK_MINIMAL_TOC, \
287 "Use only one TOC entry per procedure"}, \
288 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
290 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
291 N_("Place variable addresses in the regular TOC")},\
292 {"hard-float", - MASK_SOFT_FLOAT, \
293 N_("Use hardware fp")}, \
294 {"soft-float", MASK_SOFT_FLOAT, \
295 N_("Do not use hardware fp")}, \
296 {"multiple", MASK_MULTIPLE, \
297 N_("Generate load/store multiple instructions")}, \
298 {"no-multiple", - MASK_MULTIPLE, \
299 N_("Do not generate load/store multiple instructions")},\
300 {"string", MASK_STRING, \
301 N_("Generate string instructions for block moves")},\
302 {"no-string", - MASK_STRING, \
303 N_("Do not generate string instructions for block moves")},\
304 {"update", - MASK_NO_UPDATE, \
305 N_("Generate load/store with update instructions")},\
306 {"no-update", MASK_NO_UPDATE, \
307 N_("Do not generate load/store with update instructions")},\
308 {"fused-madd", - MASK_NO_FUSED_MADD, \
309 N_("Generate fused multiply/add instructions")},\
310 {"no-fused-madd", MASK_NO_FUSED_MADD, \
311 N_("Don't generate fused multiply/add instructions")},\
312 {"sched-prolog", MASK_SCHED_PROLOG, \
314 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
315 N_("Don't schedule the start and end of the procedure")},\
316 {"sched-epilog", MASK_SCHED_PROLOG, \
318 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
320 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
321 N_("Return all structures in memory (AIX default)")},\
322 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
323 N_("Return small structures in registers (SVR4 default)")},\
324 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
326 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
329 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
332 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
334 /* This is meant to be redefined in the host dependent files */
335 #define SUBTARGET_SWITCHES
337 /* Processor type. Order must match cpu attribute in MD file. */
360 extern enum processor_type rs6000_cpu;
362 /* Recast the processor type to the cpu attribute. */
363 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
365 /* Define generic processor types based upon current deployment. */
366 #define PROCESSOR_COMMON PROCESSOR_PPC601
367 #define PROCESSOR_POWER PROCESSOR_RIOS1
368 #define PROCESSOR_POWERPC PROCESSOR_PPC604
369 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
371 /* Define the default processor. This is overridden by other tm.h files. */
372 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
373 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
375 /* Specify the dialect of assembler to use. New mnemonics is dialect one
376 and the old mnemonics are dialect zero. */
377 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
379 /* Types of costly dependences. */
380 enum rs6000_dependence_cost
382 max_dep_latency = 1000,
385 true_store_to_load_dep_costly,
386 store_to_load_dep_costly
389 /* Types of nop insertion schemes in sched target hook sched_finish. */
390 enum rs6000_nop_insertion
392 sched_finish_regroup_exact = 1000,
393 sched_finish_pad_groups,
397 /* Dispatch group termination caused by an insn. */
398 enum group_termination
404 /* This is meant to be overridden in target specific files. */
405 #define SUBTARGET_OPTIONS
407 #define TARGET_OPTIONS \
409 {"cpu=", &rs6000_select[1].string, \
410 N_("Use features of and schedule code for given CPU"), 0}, \
411 {"tune=", &rs6000_select[2].string, \
412 N_("Schedule code for given CPU"), 0}, \
413 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
414 {"traceback=", &rs6000_traceback_name, \
415 N_("Select full, part, or no traceback table"), 0}, \
416 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
417 {"long-double-", &rs6000_long_double_size_string, \
418 N_("Specify size of long double (64 or 128 bits)"), 0}, \
419 {"isel=", &rs6000_isel_string, \
420 N_("Specify yes/no if isel instructions should be generated"), 0}, \
421 {"spe=", &rs6000_spe_string, \
422 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
423 {"float-gprs=", &rs6000_float_gprs_string, \
424 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
425 {"vrsave=", &rs6000_altivec_vrsave_string, \
426 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
427 {"longcall", &rs6000_longcall_switch, \
428 N_("Avoid all range limits on call instructions"), 0}, \
429 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
430 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
431 N_("Determine which dependences between insns are considered costly"), 0}, \
432 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
433 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
434 {"align-", &rs6000_alignment_string, \
435 N_("Specify alignment of structure fields default/natural"), 0}, \
436 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
437 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
441 /* Support for a compile-time default CPU, et cetera. The rules are:
442 --with-cpu is ignored if -mcpu is specified.
443 --with-tune is ignored if -mtune is specified.
444 --with-float is ignored if -mhard-float or -msoft-float are
446 #define OPTION_DEFAULT_SPECS \
447 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
448 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
449 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
451 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
452 struct rs6000_cpu_select
460 extern struct rs6000_cpu_select rs6000_select[];
463 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
464 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
465 extern int rs6000_debug_stack; /* debug stack applications */
466 extern int rs6000_debug_arg; /* debug argument handling */
468 #define TARGET_DEBUG_STACK rs6000_debug_stack
469 #define TARGET_DEBUG_ARG rs6000_debug_arg
471 extern const char *rs6000_traceback_name; /* Type of traceback table. */
473 /* These are separate from target_flags because we've run out of bits
475 extern const char *rs6000_long_double_size_string;
476 extern int rs6000_long_double_type_size;
477 extern int rs6000_altivec_abi;
478 extern int rs6000_spe_abi;
479 extern int rs6000_isel;
480 extern int rs6000_spe;
481 extern int rs6000_float_gprs;
482 extern const char *rs6000_float_gprs_string;
483 extern const char *rs6000_isel_string;
484 extern const char *rs6000_spe_string;
485 extern const char *rs6000_altivec_vrsave_string;
486 extern int rs6000_altivec_vrsave;
487 extern const char *rs6000_longcall_switch;
488 extern int rs6000_default_long_calls;
489 extern const char* rs6000_alignment_string;
490 extern int rs6000_alignment_flags;
491 extern const char *rs6000_sched_restricted_insns_priority_str;
492 extern int rs6000_sched_restricted_insns_priority;
493 extern const char *rs6000_sched_costly_dep_str;
494 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
495 extern const char *rs6000_sched_insert_nops_str;
496 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
498 /* Alignment options for fields in structures for sub-targets following
500 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
501 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
503 Override the macro definitions when compiling libobjc to avoid undefined
504 reference to rs6000_alignment_flags due to library's use of GCC alignment
505 macros which use the macros below. */
507 #ifndef IN_TARGET_LIBS
508 #define MASK_ALIGN_POWER 0x00000000
509 #define MASK_ALIGN_NATURAL 0x00000001
510 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
512 #define TARGET_ALIGN_NATURAL 0
515 /* Set a default value for DEFAULT_SCHED_COSTLY_DEP used by target hook
516 is_costly_dependence. */
517 #define DEFAULT_SCHED_COSTLY_DEP \
518 (rs6000_cpu == PROCESSOR_POWER4 ? store_to_load_dep_costly : no_dep_costly)
520 /* Define if the target has restricted dispatch slot instructions. */
521 #define DEFAULT_RESTRICTED_INSNS_PRIORITY (rs6000_cpu == PROCESSOR_POWER4 ? 1 : 0)
523 /* Set a default value for post scheduling nop insertion scheme
524 (used by taget hook sched_finish). */
525 #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
526 (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
528 /* Define TARGET_MFCRF if the target assembler supports the optional
529 field operand for mfcr and the target processor supports the
533 #define TARGET_MFCRF (rs6000_cpu == PROCESSOR_POWER4)
535 #define TARGET_MFCRF 0
538 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
539 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
540 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
542 #define TARGET_SPE_ABI 0
544 #define TARGET_E500 0
545 #define TARGET_ISEL 0
546 #define TARGET_FPRS 1
548 /* Sometimes certain combinations of command options do not make sense
549 on a particular target machine. You can define a macro
550 `OVERRIDE_OPTIONS' to take account of this. This macro, if
551 defined, is executed once just after all the command options have
554 Don't use this macro to turn on various extra optimizations for
555 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
557 On the RS/6000 this is used to define the target cpu type. */
559 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
561 /* Define this to change the optimizations performed by default. */
562 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
564 /* Show we can debug even without a frame pointer. */
565 #define CAN_DEBUG_WITHOUT_FP
568 #define REGISTER_TARGET_PRAGMAS() do { \
569 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
572 /* Target #defines. */
573 #define TARGET_CPU_CPP_BUILTINS() \
574 rs6000_cpu_cpp_builtins (pfile)
576 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
577 we're compiling for. Some configurations may need to override it. */
578 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
581 if (BYTES_BIG_ENDIAN) \
583 builtin_define ("__BIG_ENDIAN__"); \
584 builtin_define ("_BIG_ENDIAN"); \
585 builtin_assert ("machine=bigendian"); \
589 builtin_define ("__LITTLE_ENDIAN__"); \
590 builtin_define ("_LITTLE_ENDIAN"); \
591 builtin_assert ("machine=littleendian"); \
596 /* Target machine storage layout. */
598 /* Define this macro if it is advisable to hold scalars in registers
599 in a wider mode than that declared by the program. In such cases,
600 the value is constrained to be within the bounds of the declared
601 type, but kept valid in the wider mode. The signedness of the
602 extension may differ from that of the type. */
604 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
605 if (GET_MODE_CLASS (MODE) == MODE_INT \
606 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
609 /* Define this if most significant bit is lowest numbered
610 in instructions that operate on numbered bit-fields. */
611 /* That is true on RS/6000. */
612 #define BITS_BIG_ENDIAN 1
614 /* Define this if most significant byte of a word is the lowest numbered. */
615 /* That is true on RS/6000. */
616 #define BYTES_BIG_ENDIAN 1
618 /* Define this if most significant word of a multiword number is lowest
621 For RS/6000 we can decide arbitrarily since there are no machine
622 instructions for them. Might as well be consistent with bits and bytes. */
623 #define WORDS_BIG_ENDIAN 1
625 #define MAX_BITS_PER_WORD 64
627 /* Width of a word, in units (bytes). */
628 #define UNITS_PER_WORD (TARGET_32BIT ? 4 : 8)
630 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
632 #define MIN_UNITS_PER_WORD 4
634 #define UNITS_PER_FP_WORD 8
635 #define UNITS_PER_ALTIVEC_WORD 16
636 #define UNITS_PER_SPE_WORD 8
638 /* Type used for ptrdiff_t, as a string used in a declaration. */
639 #define PTRDIFF_TYPE "int"
641 /* Type used for size_t, as a string used in a declaration. */
642 #define SIZE_TYPE "long unsigned int"
644 /* Type used for wchar_t, as a string used in a declaration. */
645 #define WCHAR_TYPE "short unsigned int"
647 /* Width of wchar_t in bits. */
648 #define WCHAR_TYPE_SIZE 16
650 /* A C expression for the size in bits of the type `short' on the
651 target machine. If you don't define this, the default is half a
652 word. (If this would be less than one storage unit, it is
653 rounded up to one unit.) */
654 #define SHORT_TYPE_SIZE 16
656 /* A C expression for the size in bits of the type `int' on the
657 target machine. If you don't define this, the default is one
659 #define INT_TYPE_SIZE 32
661 /* A C expression for the size in bits of the type `long' on the
662 target machine. If you don't define this, the default is one
664 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
665 #define MAX_LONG_TYPE_SIZE 64
667 /* A C expression for the size in bits of the type `long long' on the
668 target machine. If you don't define this, the default is two
670 #define LONG_LONG_TYPE_SIZE 64
672 /* A C expression for the size in bits of the type `float' on the
673 target machine. If you don't define this, the default is one
675 #define FLOAT_TYPE_SIZE 32
677 /* A C expression for the size in bits of the type `double' on the
678 target machine. If you don't define this, the default is two
680 #define DOUBLE_TYPE_SIZE 64
682 /* A C expression for the size in bits of the type `long double' on
683 the target machine. If you don't define this, the default is two
685 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
687 /* Constant which presents upper bound of the above value. */
688 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
690 /* Define this to set long double type size to use in libgcc2.c, which can
691 not depend on target_flags. */
692 #ifdef __LONG_DOUBLE_128__
693 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
695 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
698 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
699 #define WIDEST_HARDWARE_FP_SIZE 64
701 /* Width in bits of a pointer.
702 See also the macro `Pmode' defined below. */
703 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
705 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
706 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
708 /* Boundary (in *bits*) on which stack pointer should be aligned. */
709 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
711 /* Allocation boundary (in *bits*) for the code of a function. */
712 #define FUNCTION_BOUNDARY 32
714 /* No data type wants to be aligned rounder than this. */
715 #define BIGGEST_ALIGNMENT 128
717 /* A C expression to compute the alignment for a variables in the
718 local store. TYPE is the data type, and ALIGN is the alignment
719 that the object would ordinarily have. */
720 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
721 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
722 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
724 /* Alignment of field after `int : 0' in a structure. */
725 #define EMPTY_FIELD_BOUNDARY 32
727 /* Every structure's size must be a multiple of this. */
728 #define STRUCTURE_SIZE_BOUNDARY 8
730 /* Return 1 if a structure or array containing FIELD should be
731 accessed using `BLKMODE'.
733 For the SPE, simd types are V2SI, and gcc can be tempted to put the
734 entire thing in a DI and use subregs to access the internals.
735 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
736 back-end. Because a single GPR can hold a V2SI, but not a DI, the
737 best thing to do is set structs to BLKmode and avoid Severe Tire
739 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
740 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
742 /* A bit-field declared as `int' forces `int' alignment for the struct. */
743 #define PCC_BITFIELD_TYPE_MATTERS 1
745 /* Make strings word-aligned so strcpy from constants will be faster.
746 Make vector constants quadword aligned. */
747 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
748 (TREE_CODE (EXP) == STRING_CST \
749 && (ALIGN) < BITS_PER_WORD \
753 /* Make arrays of chars word-aligned for the same reasons.
754 Align vectors to 128 bits. */
755 #define DATA_ALIGNMENT(TYPE, ALIGN) \
756 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
757 : TREE_CODE (TYPE) == ARRAY_TYPE \
758 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
759 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
761 /* Nonzero if move instructions will actually fail to work
762 when given unaligned data. */
763 #define STRICT_ALIGNMENT 0
765 /* Define this macro to be the value 1 if unaligned accesses have a cost
766 many times greater than aligned accesses, for example if they are
767 emulated in a trap handler. */
768 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
770 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
771 || (MODE) == DImode) \
774 /* Standard register usage. */
776 /* Number of actual hardware registers.
777 The hardware registers are assigned numbers for the compiler
778 from 0 to just below FIRST_PSEUDO_REGISTER.
779 All registers that the compiler knows about must be given numbers,
780 even those that are not normally considered general registers.
782 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
783 an MQ register, a count register, a link register, and 8 condition
784 register fields, which we view here as separate registers. AltiVec
785 adds 32 vector registers and a VRsave register.
787 In addition, the difference between the frame and argument pointers is
788 a function of the number of registers saved, so we need to have a
789 register for AP that will later be eliminated in favor of SP or FP.
790 This is a normal register, but it is fixed.
792 We also create a pseudo register for float/int conversions, that will
793 really represent the memory location used. It is represented here as
794 a register, in order to work around problems in allocating stack storage
795 in inline functions. */
797 #define FIRST_PSEUDO_REGISTER 113
799 /* This must be included for pre gcc 3.0 glibc compatibility. */
800 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
802 /* Add 32 dwarf columns for synthetic SPE registers. The SPE
803 synthetic registers are 113 through 145. */
804 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
806 /* The SPE has an additional 32 synthetic registers starting at 1200.
807 We must map them here to sane values in the unwinder to avoid a
808 huge hole in the unwind tables.
810 FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
811 the VRSAVE SPR (SPR256) assigned to register 356. When AltiVec EH
812 is verified to be working, this macro should be changed
814 #define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
816 /* 1 for registers that have pervasive standard uses
817 and are not available for the register allocator.
819 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
820 as a local register; for all other OS's r2 is the TOC pointer.
822 cr5 is not supposed to be used.
824 On System V implementations, r13 is fixed and not available for use. */
826 #define FIXED_REGISTERS \
827 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
828 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
829 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
830 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
831 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
832 /* AltiVec registers. */ \
833 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
834 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
839 /* 1 for registers not available across function calls.
840 These must include the FIXED_REGISTERS and also any
841 registers that can be used without being saved.
842 The latter must include the registers where values are returned
843 and the register where structure-value addresses are passed.
844 Aside from that, you can include as many other registers as you like. */
846 #define CALL_USED_REGISTERS \
847 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
848 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
849 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
851 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
852 /* AltiVec registers. */ \
853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
859 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
860 the entire set of `FIXED_REGISTERS' be included.
861 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
862 This macro is optional. If not specified, it defaults to the value
863 of `CALL_USED_REGISTERS'. */
865 #define CALL_REALLY_USED_REGISTERS \
866 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
868 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
869 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
870 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
871 /* AltiVec registers. */ \
872 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
884 #define MAX_CR_REGNO 75
886 #define FIRST_ALTIVEC_REGNO 77
887 #define LAST_ALTIVEC_REGNO 108
888 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
889 #define VRSAVE_REGNO 109
890 #define VSCR_REGNO 110
891 #define SPE_ACC_REGNO 111
892 #define SPEFSCR_REGNO 112
894 /* List the order in which to allocate registers. Each register must be
895 listed once, even those in FIXED_REGISTERS.
897 We allocate in the following order:
898 fp0 (not saved or used for anything)
899 fp13 - fp2 (not saved; incoming fp arg registers)
900 fp1 (not saved; return value)
901 fp31 - fp14 (saved; order given to save least number)
902 cr7, cr6 (not saved or special)
903 cr1 (not saved, but used for FP operations)
904 cr0 (not saved, but used for arithmetic operations)
905 cr4, cr3, cr2 (saved)
906 r0 (not saved; cannot be base reg)
907 r9 (not saved; best for TImode)
908 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
909 r3 (not saved; return value register)
910 r31 - r13 (saved; order given to save least number)
911 r12 (not saved; if used for DImode or DFmode would use r13)
912 mq (not saved; best to use it if we can)
913 ctr (not saved; when we have the choice ctr is better)
915 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
916 spe_acc, spefscr (fixed)
919 v0 - v1 (not saved or used for anything)
920 v13 - v3 (not saved; incoming vector arg registers)
921 v2 (not saved; incoming vector arg reg; return value)
922 v19 - v14 (not saved or used for anything)
923 v31 - v20 (saved; order given to save least number)
927 #define MAYBE_R2_AVAILABLE
928 #define MAYBE_R2_FIXED 2,
930 #define MAYBE_R2_AVAILABLE 2,
931 #define MAYBE_R2_FIXED
934 #define REG_ALLOC_ORDER \
936 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
938 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
939 50, 49, 48, 47, 46, \
940 75, 74, 69, 68, 72, 71, 70, \
941 0, MAYBE_R2_AVAILABLE \
942 9, 11, 10, 8, 7, 6, 5, 4, \
944 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
945 18, 17, 16, 15, 14, 13, 12, \
947 73, 1, MAYBE_R2_FIXED 67, 76, \
948 /* AltiVec registers. */ \
950 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
952 96, 95, 94, 93, 92, 91, \
953 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
958 /* True if register is floating-point. */
959 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
961 /* True if register is a condition register. */
962 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
964 /* True if register is a condition register, but not cr0. */
965 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
967 /* True if register is an integer register. */
968 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
970 /* SPE SIMD registers are just the GPRs. */
971 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
973 /* True if register is the XER register. */
974 #define XER_REGNO_P(N) ((N) == XER_REGNO)
976 /* True if register is an AltiVec register. */
977 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
979 /* Return number of consecutive hard regs needed starting at reg REGNO
980 to hold something of mode MODE.
981 This is ordinarily the length in words of a value of mode MODE
982 but can be less for certain modes in special long registers.
984 For the SPE, GPRs are 64 bits but only 32 bits are visible in
985 scalar instructions. The upper 32 bits are only available to the
988 POWER and PowerPC GPRs hold 32 bits worth;
989 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
991 #define UNITS_PER_GPR_WORD (! TARGET_POWERPC64 ? 4 : 8)
993 #define HARD_REGNO_NREGS(REGNO, MODE) \
994 (FP_REGNO_P (REGNO) \
995 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
996 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
997 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
998 : ALTIVEC_REGNO_P (REGNO) \
999 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
1000 : ((GET_MODE_SIZE (MODE) + UNITS_PER_GPR_WORD - 1) / UNITS_PER_GPR_WORD))
1002 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1003 ((TARGET_32BIT && TARGET_POWERPC64 \
1004 && (MODE == DImode || MODE == DFmode) \
1005 && INT_REGNO_P (REGNO)) ? 1 : 0)
1007 #define ALTIVEC_VECTOR_MODE(MODE) \
1008 ((MODE) == V16QImode \
1009 || (MODE) == V8HImode \
1010 || (MODE) == V4SFmode \
1011 || (MODE) == V4SImode)
1013 #define SPE_VECTOR_MODE(MODE) \
1014 ((MODE) == V4HImode \
1015 || (MODE) == V2SFmode \
1016 || (MODE) == V1DImode \
1017 || (MODE) == V2SImode)
1019 /* Define this macro to be nonzero if the port is prepared to handle
1020 insns involving vector mode MODE. At the very least, it must have
1021 move patterns for this mode. */
1023 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1024 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1025 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
1027 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1028 For POWER and PowerPC, the GPRs can hold any mode, but values bigger
1029 than one register cannot go past R31. The float
1030 registers only can hold floating modes and DImode, and CR register only
1031 can hold CC modes. We cannot put TImode anywhere except general
1032 register and it must be able to fit within the register set. */
1034 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1035 (INT_REGNO_P (REGNO) ? \
1036 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
1037 : FP_REGNO_P (REGNO) ? \
1038 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1039 || (GET_MODE_CLASS (MODE) == MODE_INT \
1040 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
1041 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
1042 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
1043 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
1044 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
1045 : GET_MODE_SIZE (MODE) <= UNITS_PER_GPR_WORD)
1047 /* Value is 1 if it is a good idea to tie two pseudo registers
1048 when one has mode MODE1 and one has mode MODE2.
1049 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1050 for any hard reg, then this must be 0 for correct output. */
1051 #define MODES_TIEABLE_P(MODE1, MODE2) \
1052 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1053 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1054 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1055 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1056 : GET_MODE_CLASS (MODE1) == MODE_CC \
1057 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1058 : GET_MODE_CLASS (MODE2) == MODE_CC \
1059 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1060 : SPE_VECTOR_MODE (MODE1) \
1061 ? SPE_VECTOR_MODE (MODE2) \
1062 : SPE_VECTOR_MODE (MODE2) \
1063 ? SPE_VECTOR_MODE (MODE1) \
1064 : ALTIVEC_VECTOR_MODE (MODE1) \
1065 ? ALTIVEC_VECTOR_MODE (MODE2) \
1066 : ALTIVEC_VECTOR_MODE (MODE2) \
1067 ? ALTIVEC_VECTOR_MODE (MODE1) \
1070 /* Post-reload, we can't use any new AltiVec registers, as we already
1071 emitted the vrsave mask. */
1073 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1074 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1076 /* A C expression returning the cost of moving data from a register of class
1077 CLASS1 to one of CLASS2. */
1079 #define REGISTER_MOVE_COST rs6000_register_move_cost
1081 /* A C expressions returning the cost of moving data of MODE from a register to
1084 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1086 /* Specify the cost of a branch insn; roughly the number of extra insns that
1087 should be added to avoid a branch.
1089 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1090 unscheduled conditional branch. */
1092 #define BRANCH_COST 3
1094 /* Override BRANCH_COST heuristic which empirically produces worse
1095 performance for fold_range_test(). */
1097 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1099 /* A fixed register used at prologue and epilogue generation to fix
1100 addressing modes. The SPE needs heavy addressing fixes at the last
1101 minute, and it's best to save a register for it.
1103 AltiVec also needs fixes, but we've gotten around using r11, which
1104 is actually wrong because when use_backchain_to_restore_sp is true,
1105 we end up clobbering r11.
1107 The AltiVec case needs to be fixed. Dunno if we should break ABI
1108 compatibility and reserve a register for it as well.. */
1110 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1112 /* Define this macro to change register usage conditional on target flags.
1113 Set MQ register fixed (already call_used) if not POWER architecture
1114 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
1115 64-bit AIX reserves GPR13 for thread-private data.
1116 Conditionally disable FPRs. */
1118 #define CONDITIONAL_REGISTER_USAGE \
1121 if (! TARGET_POWER) \
1122 fixed_regs[64] = 1; \
1124 fixed_regs[13] = call_used_regs[13] \
1125 = call_really_used_regs[13] = 1; \
1126 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
1127 for (i = 32; i < 64; i++) \
1128 fixed_regs[i] = call_used_regs[i] \
1129 = call_really_used_regs[i] = 1; \
1130 if (DEFAULT_ABI == ABI_V4 \
1131 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1133 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1134 if (DEFAULT_ABI == ABI_V4 \
1135 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1137 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1138 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1139 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1140 if (DEFAULT_ABI == ABI_DARWIN \
1141 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1142 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1143 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1144 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1145 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1146 if (TARGET_ALTIVEC) \
1147 global_regs[VSCR_REGNO] = 1; \
1150 global_regs[SPEFSCR_REGNO] = 1; \
1151 fixed_regs[FIXED_SCRATCH] \
1152 = call_used_regs[FIXED_SCRATCH] \
1153 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1155 if (! TARGET_ALTIVEC) \
1157 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1158 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1159 call_really_used_regs[VRSAVE_REGNO] = 1; \
1161 if (TARGET_ALTIVEC_ABI) \
1162 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1163 call_used_regs[i] = call_really_used_regs[i] = 1; \
1166 /* Specify the registers used for certain standard purposes.
1167 The values of these macros are register numbers. */
1169 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1170 /* #define PC_REGNUM */
1172 /* Register to use for pushing function arguments. */
1173 #define STACK_POINTER_REGNUM 1
1175 /* Base register for access to local variables of the function. */
1176 #define FRAME_POINTER_REGNUM 31
1178 /* Value should be nonzero if functions must have frame pointers.
1179 Zero means the frame pointer need not be set up (and parms
1180 may be accessed via the stack pointer) in functions that seem suitable.
1181 This is computed in `reload', in reload1.c. */
1182 #define FRAME_POINTER_REQUIRED 0
1184 /* Base register for access to arguments of the function. */
1185 #define ARG_POINTER_REGNUM 67
1187 /* Place to put static chain when calling a function that requires it. */
1188 #define STATIC_CHAIN_REGNUM 11
1190 /* Link register number. */
1191 #define LINK_REGISTER_REGNUM 65
1193 /* Count register number. */
1194 #define COUNT_REGISTER_REGNUM 66
1196 /* Define the classes of registers for register constraints in the
1197 machine description. Also define ranges of constants.
1199 One of the classes must always be named ALL_REGS and include all hard regs.
1200 If there is more than one class, another class must be named NO_REGS
1201 and contain no registers.
1203 The name GENERAL_REGS must be the name of a class (or an alias for
1204 another name such as ALL_REGS). This is the class of registers
1205 that is allowed by "g" or "r" in a register constraint.
1206 Also, registers outside this class are allocated only when
1207 instructions express preferences for them.
1209 The classes must be numbered in nondecreasing order; that is,
1210 a larger-numbered class must never be contained completely
1211 in a smaller-numbered class.
1213 For any two classes, it is very desirable that there be another
1214 class that represents their union. */
1216 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1217 and condition registers, plus three special registers, MQ, CTR, and the
1218 link register. AltiVec adds a vector register class.
1220 However, r0 is special in that it cannot be used as a base register.
1221 So make a class for registers valid as base registers.
1223 Also, cr0 is the only condition code register that can be used in
1224 arithmetic insns, so make a separate class for it. */
1252 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1254 /* Give names of register classes as strings for dump file. */
1256 #define REG_CLASS_NAMES \
1267 "NON_SPECIAL_REGS", \
1271 "LINK_OR_CTR_REGS", \
1273 "SPEC_OR_GEN_REGS", \
1281 /* Define which registers fit in which classes.
1282 This is an initializer for a vector of HARD_REG_SET
1283 of length N_REG_CLASSES. */
1285 #define REG_CLASS_CONTENTS \
1287 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1288 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1289 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1290 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1291 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1292 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1293 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1294 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1295 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1296 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1297 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1298 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1299 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1300 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1301 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1302 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1303 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1304 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1305 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1306 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1307 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1310 /* The same information, inverted:
1311 Return the class number of the smallest class containing
1312 reg number REGNO. This could be a conditional expression
1313 or could index an array. */
1315 #define REGNO_REG_CLASS(REGNO) \
1316 ((REGNO) == 0 ? GENERAL_REGS \
1317 : (REGNO) < 32 ? BASE_REGS \
1318 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1319 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1320 : (REGNO) == CR0_REGNO ? CR0_REGS \
1321 : CR_REGNO_P (REGNO) ? CR_REGS \
1322 : (REGNO) == MQ_REGNO ? MQ_REGS \
1323 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1324 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1325 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1326 : (REGNO) == XER_REGNO ? XER_REGS \
1327 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1328 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1329 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1330 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1333 /* The class value for index registers, and the one for base regs. */
1334 #define INDEX_REG_CLASS GENERAL_REGS
1335 #define BASE_REG_CLASS BASE_REGS
1337 /* Get reg_class from a letter such as appears in the machine description. */
1339 #define REG_CLASS_FROM_LETTER(C) \
1340 ((C) == 'f' ? FLOAT_REGS \
1341 : (C) == 'b' ? BASE_REGS \
1342 : (C) == 'h' ? SPECIAL_REGS \
1343 : (C) == 'q' ? MQ_REGS \
1344 : (C) == 'c' ? CTR_REGS \
1345 : (C) == 'l' ? LINK_REGS \
1346 : (C) == 'v' ? ALTIVEC_REGS \
1347 : (C) == 'x' ? CR0_REGS \
1348 : (C) == 'y' ? CR_REGS \
1349 : (C) == 'z' ? XER_REGS \
1352 /* The letters I, J, K, L, M, N, and P in a register constraint string
1353 can be used to stand for particular ranges of immediate operands.
1354 This macro defines what the ranges are.
1355 C is the letter, and VALUE is a constant value.
1356 Return 1 if VALUE is in the range specified by C.
1358 `I' is a signed 16-bit constant
1359 `J' is a constant with only the high-order 16 bits nonzero
1360 `K' is a constant with only the low-order 16 bits nonzero
1361 `L' is a signed 16-bit constant shifted left 16 bits
1362 `M' is a constant that is greater than 31
1363 `N' is a positive constant that is an exact power of two
1364 `O' is the constant zero
1365 `P' is a constant whose negation is a signed 16-bit constant */
1367 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1368 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1369 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1370 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1371 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1372 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1373 : (C) == 'M' ? (VALUE) > 31 \
1374 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1375 : (C) == 'O' ? (VALUE) == 0 \
1376 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1379 /* Similar, but for floating constants, and defining letters G and H.
1380 Here VALUE is the CONST_DOUBLE rtx itself.
1382 We flag for special constants when we can copy the constant into
1383 a general register in two insns for DF/DI and one insn for SF.
1385 'H' is used for DI/DF constants that take 3 insns. */
1387 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1388 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1389 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1390 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1393 /* Optional extra constraints for this machine.
1395 'Q' means that is a memory operand that is just an offset from a reg.
1396 'R' is for AIX TOC entries.
1397 'S' is a constant that can be placed into a 64-bit mask operand
1398 'T' is a constant that can be placed into a 32-bit mask operand
1399 'U' is for V.4 small data references.
1400 'W' is a vector constant that can be easily generated (no mem refs).
1401 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1403 #define EXTRA_CONSTRAINT(OP, C) \
1404 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1405 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1406 : (C) == 'S' ? mask64_operand (OP, DImode) \
1407 : (C) == 'T' ? mask_operand (OP, SImode) \
1408 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1409 && small_data_operand (OP, GET_MODE (OP))) \
1410 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1411 && (fixed_regs[CR0_REGNO] \
1412 || !logical_operand (OP, DImode)) \
1413 && !mask64_operand (OP, DImode)) \
1414 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1417 /* Given an rtx X being reloaded into a reg required to be
1418 in class CLASS, return the class of reg to actually use.
1419 In general this is just CLASS; but on some machines
1420 in some cases it is preferable to use a more restrictive class.
1422 On the RS/6000, we have to return NO_REGS when we want to reload a
1423 floating-point CONST_DOUBLE to force it to be copied to memory.
1425 We also don't want to reload integer values into floating-point
1426 registers if we can at all help it. In fact, this can
1427 cause reload to abort, if it tries to generate a reload of CTR
1428 into a FP register and discovers it doesn't have the memory location
1431 ??? Would it be a good idea to have reload do the converse, that is
1432 try to reload floating modes into FP registers if possible?
1435 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1436 (((GET_CODE (X) == CONST_DOUBLE \
1437 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1439 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1440 && (CLASS) == NON_SPECIAL_REGS) \
1444 /* Return the register class of a scratch register needed to copy IN into
1445 or out of a register in CLASS in MODE. If it can be done directly,
1446 NO_REGS is returned. */
1448 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1449 secondary_reload_class (CLASS, MODE, IN)
1451 /* If we are copying between FP or AltiVec registers and anything
1452 else, we need a memory location. */
1454 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1455 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1456 || (CLASS2) == FLOAT_REGS \
1457 || (CLASS1) == ALTIVEC_REGS \
1458 || (CLASS2) == ALTIVEC_REGS))
1460 /* Return the maximum number of consecutive registers
1461 needed to represent mode MODE in a register of class CLASS.
1463 On RS/6000, this is the size of MODE in words,
1464 except in the FP regs, where a single reg is enough for two words. */
1465 #define CLASS_MAX_NREGS(CLASS, MODE) \
1466 (((CLASS) == FLOAT_REGS) \
1467 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1468 : ((GET_MODE_SIZE (MODE) + UNITS_PER_GPR_WORD - 1) / UNITS_PER_GPR_WORD))
1471 /* Return a class of registers that cannot change FROM mode to TO mode. */
1473 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1474 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1475 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1476 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1477 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1480 /* Stack layout; function entry, exit and calling. */
1482 /* Enumeration to give which calling sequence to use. */
1485 ABI_AIX, /* IBM's AIX */
1486 ABI_V4, /* System V.4/eabi */
1487 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1490 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1492 /* Structure used to define the rs6000 stack */
1493 typedef struct rs6000_stack {
1494 int first_gp_reg_save; /* first callee saved GP register used */
1495 int first_fp_reg_save; /* first callee saved FP register used */
1496 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1497 int lr_save_p; /* true if the link reg needs to be saved */
1498 int cr_save_p; /* true if the CR reg needs to be saved */
1499 unsigned int vrsave_mask; /* mask of vec registers to save */
1500 int toc_save_p; /* true if the TOC needs to be saved */
1501 int push_p; /* true if we need to allocate stack space */
1502 int calls_p; /* true if the function makes any calls */
1503 enum rs6000_abi abi; /* which ABI to use */
1504 int gp_save_offset; /* offset to save GP regs from initial SP */
1505 int fp_save_offset; /* offset to save FP regs from initial SP */
1506 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
1507 int lr_save_offset; /* offset to save LR from initial SP */
1508 int cr_save_offset; /* offset to save CR from initial SP */
1509 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1510 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
1511 int toc_save_offset; /* offset to save the TOC pointer */
1512 int varargs_save_offset; /* offset to save the varargs registers */
1513 int ehrd_offset; /* offset to EH return data */
1514 int reg_size; /* register size (4 or 8) */
1515 int varargs_size; /* size to hold V.4 args passed in regs */
1516 int vars_size; /* variable save area size */
1517 int parm_size; /* outgoing parameter size */
1518 int save_size; /* save area size */
1519 int fixed_size; /* fixed size of stack frame */
1520 int gp_size; /* size of saved GP registers */
1521 int fp_size; /* size of saved FP registers */
1522 int altivec_size; /* size of saved AltiVec registers */
1523 int cr_size; /* size to hold CR if not in save_size */
1524 int lr_size; /* size to hold LR if not in save_size */
1525 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1526 int altivec_padding_size; /* size of altivec alignment padding if
1528 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
1529 int spe_padding_size;
1530 int toc_size; /* size to hold TOC if not in save_size */
1531 int total_size; /* total bytes allocated for stack */
1532 int spe_64bit_regs_used;
1535 /* Define this if pushing a word on the stack
1536 makes the stack pointer a smaller address. */
1537 #define STACK_GROWS_DOWNWARD
1539 /* Define this if the nominal address of the stack frame
1540 is at the high-address end of the local variables;
1541 that is, each additional local variable allocated
1542 goes at a more negative offset in the frame.
1544 On the RS/6000, we grow upwards, from the area after the outgoing
1546 /* #define FRAME_GROWS_DOWNWARD */
1548 /* Size of the outgoing register save area */
1549 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1550 || DEFAULT_ABI == ABI_DARWIN) \
1551 ? (TARGET_64BIT ? 64 : 32) \
1554 /* Size of the fixed area on the stack */
1555 #define RS6000_SAVE_AREA \
1556 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1557 << (TARGET_64BIT ? 1 : 0))
1559 /* MEM representing address to save the TOC register */
1560 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1561 plus_constant (stack_pointer_rtx, \
1562 (TARGET_32BIT ? 20 : 40)))
1564 /* Size of the V.4 varargs area if needed */
1565 #define RS6000_VARARGS_AREA 0
1567 /* Align an address */
1568 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1570 /* Size of V.4 varargs area in bytes */
1571 #define RS6000_VARARGS_SIZE \
1572 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1574 /* Offset within stack frame to start allocating local variables at.
1575 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1576 first local allocated. Otherwise, it is the offset to the BEGINNING
1577 of the first local allocated.
1579 On the RS/6000, the frame pointer is the same as the stack pointer,
1580 except for dynamic allocations. So we start after the fixed area and
1581 outgoing parameter area. */
1583 #define STARTING_FRAME_OFFSET \
1584 (RS6000_ALIGN (current_function_outgoing_args_size, \
1585 TARGET_ALTIVEC ? 16 : 8) \
1586 + RS6000_VARARGS_AREA \
1589 /* Offset from the stack pointer register to an item dynamically
1590 allocated on the stack, e.g., by `alloca'.
1592 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1593 length of the outgoing arguments. The default is correct for most
1594 machines. See `function.c' for details. */
1595 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1596 (RS6000_ALIGN (current_function_outgoing_args_size, \
1597 TARGET_ALTIVEC ? 16 : 8) \
1598 + (STACK_POINTER_OFFSET))
1600 /* If we generate an insn to push BYTES bytes,
1601 this says how many the stack pointer really advances by.
1602 On RS/6000, don't define this because there are no push insns. */
1603 /* #define PUSH_ROUNDING(BYTES) */
1605 /* Offset of first parameter from the argument pointer register value.
1606 On the RS/6000, we define the argument pointer to the start of the fixed
1608 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1610 /* Offset from the argument pointer register value to the top of
1611 stack. This is different from FIRST_PARM_OFFSET because of the
1612 register save area. */
1613 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1615 /* Define this if stack space is still allocated for a parameter passed
1616 in a register. The value is the number of bytes allocated to this
1618 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1620 /* Define this if the above stack space is to be considered part of the
1621 space allocated by the caller. */
1622 #define OUTGOING_REG_PARM_STACK_SPACE
1624 /* This is the difference between the logical top of stack and the actual sp.
1626 For the RS/6000, sp points past the fixed area. */
1627 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1629 /* Define this if the maximum size of all the outgoing args is to be
1630 accumulated and pushed during the prologue. The amount can be
1631 found in the variable current_function_outgoing_args_size. */
1632 #define ACCUMULATE_OUTGOING_ARGS 1
1634 /* Value is the number of bytes of arguments automatically
1635 popped when returning from a subroutine call.
1636 FUNDECL is the declaration node of the function (as a tree),
1637 FUNTYPE is the data type of the function (as a tree),
1638 or for a library call it is an identifier node for the subroutine name.
1639 SIZE is the number of bytes of arguments passed on the stack. */
1641 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1643 /* Define how to find the value returned by a function.
1644 VALTYPE is the data type of the value (as a tree).
1645 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1646 otherwise, FUNC is 0. */
1648 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1650 /* Define how to find the value returned by a library function
1651 assuming the value has mode MODE. */
1653 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1655 /* DRAFT_V4_STRUCT_RET defaults off. */
1656 #define DRAFT_V4_STRUCT_RET 0
1658 /* Let RETURN_IN_MEMORY control what happens. */
1659 #define DEFAULT_PCC_STRUCT_RETURN 0
1661 /* Mode of stack savearea.
1662 FUNCTION is VOIDmode because calling convention maintains SP.
1663 BLOCK needs Pmode for SP.
1664 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1665 #define STACK_SAVEAREA_MODE(LEVEL) \
1666 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1667 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1669 /* Minimum and maximum general purpose registers used to hold arguments. */
1670 #define GP_ARG_MIN_REG 3
1671 #define GP_ARG_MAX_REG 10
1672 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1674 /* Minimum and maximum floating point registers used to hold arguments. */
1675 #define FP_ARG_MIN_REG 33
1676 #define FP_ARG_AIX_MAX_REG 45
1677 #define FP_ARG_V4_MAX_REG 40
1678 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1679 || DEFAULT_ABI == ABI_DARWIN) \
1680 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1681 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1683 /* Minimum and maximum AltiVec registers used to hold arguments. */
1684 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1685 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1686 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1688 /* Return registers */
1689 #define GP_ARG_RETURN GP_ARG_MIN_REG
1690 #define FP_ARG_RETURN FP_ARG_MIN_REG
1691 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1693 /* Flags for the call/call_value rtl operations set up by function_arg */
1694 #define CALL_NORMAL 0x00000000 /* no special processing */
1695 /* Bits in 0x00000001 are unused. */
1696 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1697 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1698 #define CALL_LONG 0x00000008 /* always call indirect */
1699 #define CALL_LIBCALL 0x00000010 /* libcall */
1701 /* 1 if N is a possible register number for a function value
1702 as seen by the caller.
1704 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1705 #define FUNCTION_VALUE_REGNO_P(N) \
1706 ((N) == GP_ARG_RETURN \
1707 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1708 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
1710 /* 1 if N is a possible register number for function argument passing.
1711 On RS/6000, these are r3-r10 and fp1-fp13.
1712 On AltiVec, v2 - v13 are used for passing vectors. */
1713 #define FUNCTION_ARG_REGNO_P(N) \
1714 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1715 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1716 && TARGET_ALTIVEC) \
1717 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1718 && TARGET_HARD_FLOAT))
1720 /* A C structure for machine-specific, per-function data.
1721 This is added to the cfun structure. */
1722 typedef struct machine_function GTY(())
1724 /* Whether a System V.4 varargs area was created. */
1726 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1727 int ra_needs_full_frame;
1728 /* Some local-dynamic symbol. */
1729 const char *some_ld_name;
1730 /* Whether the instruction chain has been scanned already. */
1731 int insn_chain_scanned_p;
1732 /* Flags if __builtin_return_address (0) was used. */
1736 /* Define a data type for recording info about an argument list
1737 during the scan of that argument list. This data type should
1738 hold all necessary information about the function itself
1739 and about the args processed so far, enough to enable macros
1740 such as FUNCTION_ARG to determine where the next arg should go.
1742 On the RS/6000, this is a structure. The first element is the number of
1743 total argument words, the second is used to store the next
1744 floating-point register number, and the third says how many more args we
1745 have prototype types for.
1747 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1748 the next available GP register, `fregno' is the next available FP
1749 register, and `words' is the number of words used on the stack.
1751 The varargs/stdarg support requires that this structure's size
1752 be a multiple of sizeof(int). */
1754 typedef struct rs6000_args
1756 int words; /* # words used for passing GP registers */
1757 int fregno; /* next available FP register */
1758 int vregno; /* next available AltiVec register */
1759 int nargs_prototype; /* # args left in the current prototype */
1760 int prototype; /* Whether a prototype was defined */
1761 int stdarg; /* Whether function is a stdarg function. */
1762 int call_cookie; /* Do special things for this call */
1763 int sysv_gregno; /* next available GP register */
1766 /* Define intermediate macro to compute the size (in registers) of an argument
1769 #define RS6000_ARG_SIZE(MODE, TYPE) \
1770 ((MODE) != BLKmode \
1771 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1772 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1774 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1775 for a call to a function whose data type is FNTYPE.
1776 For a library call, FNTYPE is 0. */
1778 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1779 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE)
1781 /* Similar, but when scanning the definition of a procedure. We always
1782 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1784 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1785 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE)
1787 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1789 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1790 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE)
1792 /* Update the data in CUM to advance over an argument
1793 of mode MODE and data type TYPE.
1794 (TYPE is null for libcalls where that information may not be available.) */
1796 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1797 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1799 /* Nonzero if we can use a floating-point register to pass this arg. */
1800 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1801 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1802 && (CUM).fregno <= FP_ARG_MAX_REG \
1803 && TARGET_HARD_FLOAT && TARGET_FPRS)
1805 /* Nonzero if we can use an AltiVec register to pass this arg. */
1806 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1807 (ALTIVEC_VECTOR_MODE (MODE) \
1808 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1809 && TARGET_ALTIVEC_ABI)
1811 /* Determine where to put an argument to a function.
1812 Value is zero to push the argument on the stack,
1813 or a hard register in which to store the argument.
1815 MODE is the argument's machine mode.
1816 TYPE is the data type of the argument (as a tree).
1817 This is null for libcalls where that information may
1819 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1820 the preceding args and about the function being called.
1821 NAMED is nonzero if this argument is a named parameter
1822 (otherwise it is an extra parameter matching an ellipsis).
1824 On RS/6000 the first eight words of non-FP are normally in registers
1825 and the rest are pushed. The first 13 FP args are in registers.
1827 If this is floating-point and no prototype is specified, we use
1828 both an FP and integer register (or possibly FP reg and stack). Library
1829 functions (when TYPE is zero) always have the proper types for args,
1830 so we can pass the FP value just in one register. emit_library_function
1831 doesn't support EXPR_LIST anyway. */
1833 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1834 function_arg (&CUM, MODE, TYPE, NAMED)
1836 /* For an arg passed partly in registers and partly in memory,
1837 this is the number of registers used.
1838 For args passed entirely in registers or entirely in memory, zero. */
1840 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1841 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1843 /* A C expression that indicates when an argument must be passed by
1844 reference. If nonzero for an argument, a copy of that argument is
1845 made in memory and a pointer to the argument is passed instead of
1846 the argument itself. The pointer is passed in whatever way is
1847 appropriate for passing a pointer to that type. */
1849 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1850 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1852 /* If defined, a C expression which determines whether, and in which
1853 direction, to pad out an argument with extra space. The value
1854 should be of type `enum direction': either `upward' to pad above
1855 the argument, `downward' to pad below, or `none' to inhibit
1858 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1860 /* If defined, a C expression that gives the alignment boundary, in bits,
1861 of an argument with the specified mode and type. If it is not defined,
1862 PARM_BOUNDARY is used for all arguments. */
1864 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1865 function_arg_boundary (MODE, TYPE)
1867 /* Define to nonzero if complex arguments should be split into their
1868 corresponding components.
1870 This should be set for Linux and Darwin as well, but we can't break
1871 the ABIs at the moment. For now, only AIX gets fixed. */
1872 #define SPLIT_COMPLEX_ARGS (DEFAULT_ABI == ABI_AIX)
1874 /* Define the `__builtin_va_list' type for the ABI. */
1875 #define BUILD_VA_LIST_TYPE(VALIST) \
1876 (VALIST) = rs6000_build_va_list ()
1878 /* Implement `va_start' for varargs and stdarg. */
1879 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1880 rs6000_va_start (valist, nextarg)
1882 /* Implement `va_arg'. */
1883 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1884 rs6000_va_arg (valist, type)
1886 #define PAD_VARARGS_DOWN \
1887 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1889 /* Define this macro to be a nonzero value if the location where a function
1890 argument is passed depends on whether or not it is a named argument. */
1891 #define STRICT_ARGUMENT_NAMING 1
1893 /* Output assembler code to FILE to increment profiler label # LABELNO
1894 for profiling a function entry. */
1896 #define FUNCTION_PROFILER(FILE, LABELNO) \
1897 output_function_profiler ((FILE), (LABELNO));
1899 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1900 the stack pointer does not matter. No definition is equivalent to
1903 On the RS/6000, this is nonzero because we can restore the stack from
1904 its backpointer, which we maintain. */
1905 #define EXIT_IGNORE_STACK 1
1907 /* Define this macro as a C expression that is nonzero for registers
1908 that are used by the epilogue or the return' pattern. The stack
1909 and frame pointer registers are already be assumed to be used as
1912 #define EPILOGUE_USES(REGNO) \
1913 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1914 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1915 || (current_function_calls_eh_return \
1920 /* TRAMPOLINE_TEMPLATE deleted */
1922 /* Length in units of the trampoline for entering a nested function. */
1924 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1926 /* Emit RTL insns to initialize the variable parts of a trampoline.
1927 FNADDR is an RTX for the address of the function's pure code.
1928 CXT is an RTX for the static chain value for the function. */
1930 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1931 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1933 /* Definitions for __builtin_return_address and __builtin_frame_address.
1934 __builtin_return_address (0) should give link register (65), enable
1936 /* This should be uncommented, so that the link register is used, but
1937 currently this would result in unmatched insns and spilling fixed
1938 registers so we'll leave it for another day. When these problems are
1939 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1941 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1943 /* Number of bytes into the frame return addresses can be found. See
1944 rs6000_stack_info in rs6000.c for more information on how the different
1945 abi's store the return address. */
1946 #define RETURN_ADDRESS_OFFSET \
1947 ((DEFAULT_ABI == ABI_AIX \
1948 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1949 (DEFAULT_ABI == ABI_V4) ? 4 : \
1950 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1952 /* The current return address is in link register (65). The return address
1953 of anything farther back is accessed normally at an offset of 8 from the
1955 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1956 (rs6000_return_addr (COUNT, FRAME))
1959 /* Definitions for register eliminations.
1961 We have two registers that can be eliminated on the RS/6000. First, the
1962 frame pointer register can often be eliminated in favor of the stack
1963 pointer register. Secondly, the argument pointer register can always be
1964 eliminated; it is replaced with either the stack or frame pointer.
1966 In addition, we use the elimination mechanism to see if r30 is needed
1967 Initially we assume that it isn't. If it is, we spill it. This is done
1968 by making it an eliminable register. We replace it with itself so that
1969 if it isn't needed, then existing uses won't be modified. */
1971 /* This is an array of structures. Each structure initializes one pair
1972 of eliminable registers. The "from" register number is given first,
1973 followed by "to". Eliminations of the same "from" register are listed
1974 in order of preference. */
1975 #define ELIMINABLE_REGS \
1976 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1977 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1978 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1979 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1981 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1982 Frame pointer elimination is automatically handled.
1984 For the RS/6000, if frame pointer elimination is being done, we would like
1985 to convert ap into fp, not sp.
1987 We need r30 if -mminimal-toc was specified, and there are constant pool
1990 #define CAN_ELIMINATE(FROM, TO) \
1991 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1992 ? ! frame_pointer_needed \
1993 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1994 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1997 /* Define the offset between two registers, one to be eliminated, and the other
1998 its replacement, at the start of a routine. */
1999 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2001 rs6000_stack_t *info = rs6000_stack_info (); \
2003 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
2004 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
2005 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
2006 (OFFSET) = info->total_size; \
2007 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
2008 (OFFSET) = (info->push_p) ? info->total_size : 0; \
2009 else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \
2015 /* Addressing modes, and classification of registers for them. */
2017 #define HAVE_PRE_DECREMENT 1
2018 #define HAVE_PRE_INCREMENT 1
2020 /* Macros to check register numbers against specific register classes. */
2022 /* These assume that REGNO is a hard or pseudo reg number.
2023 They give nonzero only if REGNO is a hard reg of the suitable class
2024 or a pseudo reg currently allocated to a suitable hard reg.
2025 Since they use reg_renumber, they are safe only once reg_renumber
2026 has been allocated, which happens in local-alloc.c. */
2028 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2029 ((REGNO) < FIRST_PSEUDO_REGISTER \
2030 ? (REGNO) <= 31 || (REGNO) == 67 \
2031 : (reg_renumber[REGNO] >= 0 \
2032 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
2034 #define REGNO_OK_FOR_BASE_P(REGNO) \
2035 ((REGNO) < FIRST_PSEUDO_REGISTER \
2036 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
2037 : (reg_renumber[REGNO] > 0 \
2038 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
2040 /* Maximum number of registers that can appear in a valid memory address. */
2042 #define MAX_REGS_PER_ADDRESS 2
2044 /* Recognize any constant value that is a valid address. */
2046 #define CONSTANT_ADDRESS_P(X) \
2047 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2048 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2049 || GET_CODE (X) == HIGH)
2051 /* Nonzero if the constant value X is a legitimate general operand.
2052 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2054 On the RS/6000, all integer constants are acceptable, most won't be valid
2055 for particular insns, though. Only easy FP constants are
2058 #define LEGITIMATE_CONSTANT_P(X) \
2059 (((GET_CODE (X) != CONST_DOUBLE \
2060 && GET_CODE (X) != CONST_VECTOR) \
2061 || GET_MODE (X) == VOIDmode \
2062 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
2063 || easy_fp_constant (X, GET_MODE (X)) \
2064 || easy_vector_constant (X, GET_MODE (X))) \
2065 && !rs6000_tls_referenced_p (X))
2067 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2068 and check its validity for a certain class.
2069 We have two alternate definitions for each of them.
2070 The usual definition accepts all pseudo regs; the other rejects
2071 them unless they have been allocated suitable hard regs.
2072 The symbol REG_OK_STRICT causes the latter definition to be used.
2074 Most source files want to accept pseudo regs in the hope that
2075 they will get allocated to the class that the insn wants them to be in.
2076 Source files for reload pass need to be strict.
2077 After reload, it makes no difference, since pseudo regs have
2078 been eliminated by then. */
2080 #ifdef REG_OK_STRICT
2081 # define REG_OK_STRICT_FLAG 1
2083 # define REG_OK_STRICT_FLAG 0
2086 /* Nonzero if X is a hard reg that can be used as an index
2087 or if it is a pseudo reg in the non-strict case. */
2088 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2090 && (REGNO (X) <= 31 \
2091 || REGNO (X) == ARG_POINTER_REGNUM \
2092 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2093 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2095 /* Nonzero if X is a hard reg that can be used as a base reg
2096 or if it is a pseudo reg in the non-strict case. */
2097 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2098 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2100 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2101 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2103 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2104 that is a valid memory address for an instruction.
2105 The MODE argument is the machine mode for the MEM expression
2106 that wants to use this address.
2108 On the RS/6000, there are four valid address: a SYMBOL_REF that
2109 refers to a constant pool entry of an address (or the sum of it
2110 plus a constant), a short (16-bit signed) constant plus a register,
2111 the sum of two registers, or a register indirect, possibly with an
2112 auto-increment. For DFmode and DImode with a constant plus register,
2113 we must ensure that both words are addressable or PowerPC64 with offset
2116 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2117 32-bit DImode, TImode), indexed addressing cannot be used because
2118 adjacent memory cells are accessed by adding word-sized offsets
2119 during assembly output. */
2121 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2122 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2126 /* Try machine-dependent ways of modifying an illegitimate address
2127 to be legitimate. If we find one, return the new, valid address.
2128 This macro is used in only one place: `memory_address' in explow.c.
2130 OLDX is the address as it was before break_out_memory_refs was called.
2131 In some cases it is useful to look at this to decide what needs to be done.
2133 MODE and WIN are passed so that this macro can use
2134 GO_IF_LEGITIMATE_ADDRESS.
2136 It is always safe for this macro to do nothing. It exists to recognize
2137 opportunities to optimize the output.
2139 On RS/6000, first check for the sum of a register with a constant
2140 integer that is out of range. If so, generate code to add the
2141 constant with the low-order 16 bits masked to the register and force
2142 this result into another register (this can be done with `cau').
2143 Then generate an address of REG+(CONST&0xffff), allowing for the
2144 possibility of bit 16 being a one.
2146 Then check for the sum of a register and something not constant, try to
2147 load the other things into a register and return the sum. */
2149 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2150 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2151 if (result != NULL_RTX) \
2158 /* Try a machine-dependent way of reloading an illegitimate address
2159 operand. If we find one, push the reload and jump to WIN. This
2160 macro is used in only one place: `find_reloads_address' in reload.c.
2162 Implemented on rs6000 by rs6000_legitimize_reload_address.
2163 Note that (X) is evaluated twice; this is safe in current usage. */
2165 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2168 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2169 (int)(TYPE), (IND_LEVELS), &win); \
2174 /* Go to LABEL if ADDR (a legitimate address expression)
2175 has an effect that depends on the machine mode it is used for. */
2177 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2179 if (rs6000_mode_dependent_address (ADDR)) \
2183 /* The register number of the register used to address a table of
2184 static data addresses in memory. In some cases this register is
2185 defined by a processor's "application binary interface" (ABI).
2186 When this macro is defined, RTL is generated for this register
2187 once, as with the stack pointer and frame pointer registers. If
2188 this macro is not defined, it is up to the machine-dependent files
2189 to allocate such a register (if necessary). */
2191 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2192 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2194 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2196 /* Define this macro if the register defined by
2197 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2198 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2200 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2202 /* By generating position-independent code, when two different
2203 programs (A and B) share a common library (libC.a), the text of
2204 the library can be shared whether or not the library is linked at
2205 the same address for both programs. In some of these
2206 environments, position-independent code requires not only the use
2207 of different addressing modes, but also special code to enable the
2208 use of these addressing modes.
2210 The `FINALIZE_PIC' macro serves as a hook to emit these special
2211 codes once the function is being compiled into assembly code, but
2212 not before. (It is not done before, because in the case of
2213 compiling an inline function, it would lead to multiple PIC
2214 prologues being included in functions which used inline functions
2215 and were compiled to assembly language.) */
2217 /* #define FINALIZE_PIC */
2219 /* A C expression that is nonzero if X is a legitimate immediate
2220 operand on the target machine when generating position independent
2221 code. You can assume that X satisfies `CONSTANT_P', so you need
2222 not check this. You can also assume FLAG_PIC is true, so you need
2223 not check it either. You need not define this macro if all
2224 constants (including `SYMBOL_REF') can be immediate operands when
2225 generating position independent code. */
2227 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2229 /* Define this if some processing needs to be done immediately before
2230 emitting code for an insn. */
2232 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2234 /* Specify the machine mode that this machine uses
2235 for the index in the tablejump instruction. */
2236 #define CASE_VECTOR_MODE SImode
2238 /* Define as C expression which evaluates to nonzero if the tablejump
2239 instruction expects the table to contain offsets from the address of the
2241 Do not define this if the table should contain absolute addresses. */
2242 #define CASE_VECTOR_PC_RELATIVE 1
2244 /* Define this as 1 if `char' should by default be signed; else as 0. */
2245 #define DEFAULT_SIGNED_CHAR 0
2247 /* This flag, if defined, says the same insns that convert to a signed fixnum
2248 also convert validly to an unsigned one. */
2250 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2252 /* Max number of bytes we can move from memory to memory
2253 in one reasonably fast instruction. */
2254 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2255 #define MAX_MOVE_MAX 8
2257 /* Nonzero if access to memory by bytes is no faster than for words.
2258 Also nonzero if doing byte operations (specifically shifts) in registers
2260 #define SLOW_BYTE_ACCESS 1
2262 /* Define if operations between registers always perform the operation
2263 on the full register even if a narrower mode is specified. */
2264 #define WORD_REGISTER_OPERATIONS
2266 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2267 will either zero-extend or sign-extend. The value of this macro should
2268 be the code that says which one of the two operations is implicitly
2269 done, NIL if none. */
2270 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2272 /* Define if loading short immediate values into registers sign extends. */
2273 #define SHORT_IMMEDIATES_SIGN_EXTEND
2275 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2276 is done just by pretending it is already truncated. */
2277 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2279 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2280 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2281 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2283 /* The CTZ patterns return -1 for input of zero. */
2284 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2286 /* Specify the machine mode that pointers have.
2287 After generation of rtl, the compiler makes no further distinction
2288 between pointers and any other objects of this machine mode. */
2289 #define Pmode (TARGET_32BIT ? SImode : DImode)
2291 /* Mode of a function address in a call instruction (for indexing purposes).
2292 Doesn't matter on RS/6000. */
2293 #define FUNCTION_MODE SImode
2295 /* Define this if addresses of constant functions
2296 shouldn't be put through pseudo regs where they can be cse'd.
2297 Desirable on machines where ordinary constants are expensive
2298 but a CALL with constant address is cheap. */
2299 #define NO_FUNCTION_CSE
2301 /* Define this to be nonzero if shift instructions ignore all but the low-order
2304 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2305 have been dropped from the PowerPC architecture. */
2307 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2309 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2310 should be adjusted to reflect any required changes. This macro is used when
2311 there is some systematic length adjustment required that would be difficult
2312 to express in the length attribute. */
2314 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2316 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2317 COMPARE, return the mode to be used for the comparison. For
2318 floating-point, CCFPmode should be used. CCUNSmode should be used
2319 for unsigned comparisons. CCEQmode should be used when we are
2320 doing an inequality comparison on the result of a
2321 comparison. CCmode should be used in all other cases. */
2323 #define SELECT_CC_MODE(OP,X,Y) \
2324 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2325 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2326 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2327 ? CCEQmode : CCmode))
2329 /* Can the condition code MODE be safely reversed? This is safe in
2330 all cases on this port, because at present it doesn't use the
2331 trapping FP comparisons (fcmpo). */
2332 #define REVERSIBLE_CC_MODE(MODE) 1
2334 /* Given a condition code and a mode, return the inverse condition. */
2335 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2337 /* Define the information needed to generate branch and scc insns. This is
2338 stored from the compare operation. */
2340 extern GTY(()) rtx rs6000_compare_op0;
2341 extern GTY(()) rtx rs6000_compare_op1;
2342 extern int rs6000_compare_fp_p;
2344 /* Control the assembler format that we output. */
2346 /* A C string constant describing how to begin a comment in the target
2347 assembler language. The compiler assumes that the comment will end at
2348 the end of the line. */
2349 #define ASM_COMMENT_START " #"
2351 /* Implicit library calls should use memcpy, not bcopy, etc. */
2353 #define TARGET_MEM_FUNCTIONS
2355 /* Flag to say the TOC is initialized */
2356 extern int toc_initialized;
2358 /* Macro to output a special constant pool entry. Go to WIN if we output
2359 it. Otherwise, it is written the usual way.
2361 On the RS/6000, toc entries are handled this way. */
2363 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2364 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2366 output_toc (FILE, X, LABELNO, MODE); \
2371 #ifdef HAVE_GAS_WEAK
2372 #define RS6000_WEAK 1
2374 #define RS6000_WEAK 0
2378 /* Used in lieu of ASM_WEAKEN_LABEL. */
2379 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2382 fputs ("\t.weak\t", (FILE)); \
2383 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2384 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2385 && DEFAULT_ABI == ABI_AIX) \
2388 fputs ("[DS]", (FILE)); \
2389 fputs ("\n\t.weak\t.", (FILE)); \
2390 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2392 fputc ('\n', (FILE)); \
2395 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2396 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2397 && DEFAULT_ABI == ABI_AIX) \
2399 fputs ("\t.set\t.", (FILE)); \
2400 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2401 fputs (",.", (FILE)); \
2402 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2403 fputc ('\n', (FILE)); \
2410 /* This implements the `alias' attribute. */
2411 #undef ASM_OUTPUT_DEF_FROM_DECLS
2412 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2415 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2416 const char *name = IDENTIFIER_POINTER (TARGET); \
2417 if (TREE_CODE (DECL) == FUNCTION_DECL \
2418 && DEFAULT_ABI == ABI_AIX) \
2420 if (TREE_PUBLIC (DECL)) \
2422 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2424 fputs ("\t.globl\t.", FILE); \
2425 RS6000_OUTPUT_BASENAME (FILE, alias); \
2426 putc ('\n', FILE); \
2429 else if (TARGET_XCOFF) \
2431 fputs ("\t.lglobl\t.", FILE); \
2432 RS6000_OUTPUT_BASENAME (FILE, alias); \
2433 putc ('\n', FILE); \
2435 fputs ("\t.set\t.", FILE); \
2436 RS6000_OUTPUT_BASENAME (FILE, alias); \
2437 fputs (",.", FILE); \
2438 RS6000_OUTPUT_BASENAME (FILE, name); \
2439 fputc ('\n', FILE); \
2441 ASM_OUTPUT_DEF (FILE, alias, name); \
2445 #define TARGET_ASM_FILE_START rs6000_file_start
2447 /* Output to assembler file text saying following lines
2448 may contain character constants, extra white space, comments, etc. */
2450 #define ASM_APP_ON ""
2452 /* Output to assembler file text saying following lines
2453 no longer contain unusual constructs. */
2455 #define ASM_APP_OFF ""
2457 /* How to refer to registers in assembler output.
2458 This sequence is indexed by compiler's hard-register-number (see above). */
2460 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2462 #define REGISTER_NAMES \
2464 &rs6000_reg_names[ 0][0], /* r0 */ \
2465 &rs6000_reg_names[ 1][0], /* r1 */ \
2466 &rs6000_reg_names[ 2][0], /* r2 */ \
2467 &rs6000_reg_names[ 3][0], /* r3 */ \
2468 &rs6000_reg_names[ 4][0], /* r4 */ \
2469 &rs6000_reg_names[ 5][0], /* r5 */ \
2470 &rs6000_reg_names[ 6][0], /* r6 */ \
2471 &rs6000_reg_names[ 7][0], /* r7 */ \
2472 &rs6000_reg_names[ 8][0], /* r8 */ \
2473 &rs6000_reg_names[ 9][0], /* r9 */ \
2474 &rs6000_reg_names[10][0], /* r10 */ \
2475 &rs6000_reg_names[11][0], /* r11 */ \
2476 &rs6000_reg_names[12][0], /* r12 */ \
2477 &rs6000_reg_names[13][0], /* r13 */ \
2478 &rs6000_reg_names[14][0], /* r14 */ \
2479 &rs6000_reg_names[15][0], /* r15 */ \
2480 &rs6000_reg_names[16][0], /* r16 */ \
2481 &rs6000_reg_names[17][0], /* r17 */ \
2482 &rs6000_reg_names[18][0], /* r18 */ \
2483 &rs6000_reg_names[19][0], /* r19 */ \
2484 &rs6000_reg_names[20][0], /* r20 */ \
2485 &rs6000_reg_names[21][0], /* r21 */ \
2486 &rs6000_reg_names[22][0], /* r22 */ \
2487 &rs6000_reg_names[23][0], /* r23 */ \
2488 &rs6000_reg_names[24][0], /* r24 */ \
2489 &rs6000_reg_names[25][0], /* r25 */ \
2490 &rs6000_reg_names[26][0], /* r26 */ \
2491 &rs6000_reg_names[27][0], /* r27 */ \
2492 &rs6000_reg_names[28][0], /* r28 */ \
2493 &rs6000_reg_names[29][0], /* r29 */ \
2494 &rs6000_reg_names[30][0], /* r30 */ \
2495 &rs6000_reg_names[31][0], /* r31 */ \
2497 &rs6000_reg_names[32][0], /* fr0 */ \
2498 &rs6000_reg_names[33][0], /* fr1 */ \
2499 &rs6000_reg_names[34][0], /* fr2 */ \
2500 &rs6000_reg_names[35][0], /* fr3 */ \
2501 &rs6000_reg_names[36][0], /* fr4 */ \
2502 &rs6000_reg_names[37][0], /* fr5 */ \
2503 &rs6000_reg_names[38][0], /* fr6 */ \
2504 &rs6000_reg_names[39][0], /* fr7 */ \
2505 &rs6000_reg_names[40][0], /* fr8 */ \
2506 &rs6000_reg_names[41][0], /* fr9 */ \
2507 &rs6000_reg_names[42][0], /* fr10 */ \
2508 &rs6000_reg_names[43][0], /* fr11 */ \
2509 &rs6000_reg_names[44][0], /* fr12 */ \
2510 &rs6000_reg_names[45][0], /* fr13 */ \
2511 &rs6000_reg_names[46][0], /* fr14 */ \
2512 &rs6000_reg_names[47][0], /* fr15 */ \
2513 &rs6000_reg_names[48][0], /* fr16 */ \
2514 &rs6000_reg_names[49][0], /* fr17 */ \
2515 &rs6000_reg_names[50][0], /* fr18 */ \
2516 &rs6000_reg_names[51][0], /* fr19 */ \
2517 &rs6000_reg_names[52][0], /* fr20 */ \
2518 &rs6000_reg_names[53][0], /* fr21 */ \
2519 &rs6000_reg_names[54][0], /* fr22 */ \
2520 &rs6000_reg_names[55][0], /* fr23 */ \
2521 &rs6000_reg_names[56][0], /* fr24 */ \
2522 &rs6000_reg_names[57][0], /* fr25 */ \
2523 &rs6000_reg_names[58][0], /* fr26 */ \
2524 &rs6000_reg_names[59][0], /* fr27 */ \
2525 &rs6000_reg_names[60][0], /* fr28 */ \
2526 &rs6000_reg_names[61][0], /* fr29 */ \
2527 &rs6000_reg_names[62][0], /* fr30 */ \
2528 &rs6000_reg_names[63][0], /* fr31 */ \
2530 &rs6000_reg_names[64][0], /* mq */ \
2531 &rs6000_reg_names[65][0], /* lr */ \
2532 &rs6000_reg_names[66][0], /* ctr */ \
2533 &rs6000_reg_names[67][0], /* ap */ \
2535 &rs6000_reg_names[68][0], /* cr0 */ \
2536 &rs6000_reg_names[69][0], /* cr1 */ \
2537 &rs6000_reg_names[70][0], /* cr2 */ \
2538 &rs6000_reg_names[71][0], /* cr3 */ \
2539 &rs6000_reg_names[72][0], /* cr4 */ \
2540 &rs6000_reg_names[73][0], /* cr5 */ \
2541 &rs6000_reg_names[74][0], /* cr6 */ \
2542 &rs6000_reg_names[75][0], /* cr7 */ \
2544 &rs6000_reg_names[76][0], /* xer */ \
2546 &rs6000_reg_names[77][0], /* v0 */ \
2547 &rs6000_reg_names[78][0], /* v1 */ \
2548 &rs6000_reg_names[79][0], /* v2 */ \
2549 &rs6000_reg_names[80][0], /* v3 */ \
2550 &rs6000_reg_names[81][0], /* v4 */ \
2551 &rs6000_reg_names[82][0], /* v5 */ \
2552 &rs6000_reg_names[83][0], /* v6 */ \
2553 &rs6000_reg_names[84][0], /* v7 */ \
2554 &rs6000_reg_names[85][0], /* v8 */ \
2555 &rs6000_reg_names[86][0], /* v9 */ \
2556 &rs6000_reg_names[87][0], /* v10 */ \
2557 &rs6000_reg_names[88][0], /* v11 */ \
2558 &rs6000_reg_names[89][0], /* v12 */ \
2559 &rs6000_reg_names[90][0], /* v13 */ \
2560 &rs6000_reg_names[91][0], /* v14 */ \
2561 &rs6000_reg_names[92][0], /* v15 */ \
2562 &rs6000_reg_names[93][0], /* v16 */ \
2563 &rs6000_reg_names[94][0], /* v17 */ \
2564 &rs6000_reg_names[95][0], /* v18 */ \
2565 &rs6000_reg_names[96][0], /* v19 */ \
2566 &rs6000_reg_names[97][0], /* v20 */ \
2567 &rs6000_reg_names[98][0], /* v21 */ \
2568 &rs6000_reg_names[99][0], /* v22 */ \
2569 &rs6000_reg_names[100][0], /* v23 */ \
2570 &rs6000_reg_names[101][0], /* v24 */ \
2571 &rs6000_reg_names[102][0], /* v25 */ \
2572 &rs6000_reg_names[103][0], /* v26 */ \
2573 &rs6000_reg_names[104][0], /* v27 */ \
2574 &rs6000_reg_names[105][0], /* v28 */ \
2575 &rs6000_reg_names[106][0], /* v29 */ \
2576 &rs6000_reg_names[107][0], /* v30 */ \
2577 &rs6000_reg_names[108][0], /* v31 */ \
2578 &rs6000_reg_names[109][0], /* vrsave */ \
2579 &rs6000_reg_names[110][0], /* vscr */ \
2580 &rs6000_reg_names[111][0], /* spe_acc */ \
2581 &rs6000_reg_names[112][0], /* spefscr */ \
2584 /* Table of additional register names to use in user input. */
2586 #define ADDITIONAL_REGISTER_NAMES \
2587 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2588 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2589 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2590 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2591 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2592 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2593 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2594 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2595 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2596 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2597 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2598 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2599 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2600 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2601 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2602 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2603 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2604 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2605 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2606 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2607 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2608 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2609 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2610 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2611 {"vrsave", 109}, {"vscr", 110}, \
2612 {"spe_acc", 111}, {"spefscr", 112}, \
2613 /* no additional names for: mq, lr, ctr, ap */ \
2614 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2615 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2616 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2618 /* Text to write out after a CALL that may be replaced by glue code by
2619 the loader. This depends on the AIX version. */
2620 #define RS6000_CALL_GLUE "cror 31,31,31"
2622 /* This is how to output an element of a case-vector that is relative. */
2624 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2625 do { char buf[100]; \
2626 fputs ("\t.long ", FILE); \
2627 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2628 assemble_name (FILE, buf); \
2630 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2631 assemble_name (FILE, buf); \
2632 putc ('\n', FILE); \
2635 /* This is how to output an assembler line
2636 that says to advance the location counter
2637 to a multiple of 2**LOG bytes. */
2639 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2641 fprintf (FILE, "\t.align %d\n", (LOG))
2643 /* Pick up the return address upon entry to a procedure. Used for
2644 dwarf2 unwind information. This also enables the table driven
2647 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2648 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2650 /* Describe how we implement __builtin_eh_return. */
2651 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2652 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2654 /* Print operand X (an rtx) in assembler syntax to file FILE.
2655 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2656 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2658 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2660 /* Define which CODE values are valid. */
2662 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2663 ((CODE) == '.' || (CODE) == '&')
2665 /* Print a memory address as an operand to reference that memory location. */
2667 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2669 /* Define the codes that are matched by predicates in rs6000.c. */
2671 #define PREDICATE_CODES \
2672 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2673 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2674 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2675 LABEL_REF, SUBREG, REG, MEM}}, \
2676 {"short_cint_operand", {CONST_INT}}, \
2677 {"u_short_cint_operand", {CONST_INT}}, \
2678 {"non_short_cint_operand", {CONST_INT}}, \
2679 {"exact_log2_cint_operand", {CONST_INT}}, \
2680 {"gpc_reg_operand", {SUBREG, REG}}, \
2681 {"cc_reg_operand", {SUBREG, REG}}, \
2682 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2683 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2684 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2685 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2686 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2687 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2688 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2689 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2690 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2691 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2692 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2693 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2694 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2695 {"easy_fp_constant", {CONST_DOUBLE}}, \
2696 {"easy_vector_constant", {CONST_VECTOR}}, \
2697 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2698 {"zero_fp_constant", {CONST_DOUBLE}}, \
2699 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2700 {"lwa_operand", {SUBREG, MEM, REG}}, \
2701 {"volatile_mem_operand", {MEM}}, \
2702 {"offsettable_mem_operand", {MEM}}, \
2703 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2704 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2705 {"non_add_cint_operand", {CONST_INT}}, \
2706 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2707 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2708 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2709 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2710 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2711 {"mask_operand", {CONST_INT}}, \
2712 {"mask_operand_wrap", {CONST_INT}}, \
2713 {"mask64_operand", {CONST_INT}}, \
2714 {"mask64_2_operand", {CONST_INT}}, \
2715 {"count_register_operand", {REG}}, \
2716 {"xer_operand", {REG}}, \
2717 {"symbol_ref_operand", {SYMBOL_REF}}, \
2718 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2719 {"call_operand", {SYMBOL_REF, REG}}, \
2720 {"current_file_function_operand", {SYMBOL_REF}}, \
2721 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2722 CONST_DOUBLE, SYMBOL_REF}}, \
2723 {"load_multiple_operation", {PARALLEL}}, \
2724 {"store_multiple_operation", {PARALLEL}}, \
2725 {"vrsave_operation", {PARALLEL}}, \
2726 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2727 GT, LEU, LTU, GEU, GTU, \
2728 UNORDERED, ORDERED, \
2730 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2732 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2733 GT, LEU, LTU, GEU, GTU, \
2734 UNORDERED, ORDERED, \
2736 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2737 GT, LEU, LTU, GEU, GTU}}, \
2738 {"boolean_operator", {AND, IOR, XOR}}, \
2739 {"boolean_or_operator", {IOR, XOR}}, \
2740 {"altivec_register_operand", {REG}}, \
2741 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2743 /* uncomment for disabling the corresponding default options */
2744 /* #define MACHINE_no_sched_interblock */
2745 /* #define MACHINE_no_sched_speculative */
2746 /* #define MACHINE_no_sched_speculative_load */
2748 /* General flags. */
2749 extern int flag_pic;
2750 extern int optimize;
2751 extern int flag_expensive_optimizations;
2752 extern int frame_pointer_needed;
2754 enum rs6000_builtins
2756 /* AltiVec builtins. */
2757 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2758 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2759 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2760 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2761 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2762 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2763 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2764 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2765 ALTIVEC_BUILTIN_VADDUBM,
2766 ALTIVEC_BUILTIN_VADDUHM,
2767 ALTIVEC_BUILTIN_VADDUWM,
2768 ALTIVEC_BUILTIN_VADDFP,
2769 ALTIVEC_BUILTIN_VADDCUW,
2770 ALTIVEC_BUILTIN_VADDUBS,
2771 ALTIVEC_BUILTIN_VADDSBS,
2772 ALTIVEC_BUILTIN_VADDUHS,
2773 ALTIVEC_BUILTIN_VADDSHS,
2774 ALTIVEC_BUILTIN_VADDUWS,
2775 ALTIVEC_BUILTIN_VADDSWS,
2776 ALTIVEC_BUILTIN_VAND,
2777 ALTIVEC_BUILTIN_VANDC,
2778 ALTIVEC_BUILTIN_VAVGUB,
2779 ALTIVEC_BUILTIN_VAVGSB,
2780 ALTIVEC_BUILTIN_VAVGUH,
2781 ALTIVEC_BUILTIN_VAVGSH,
2782 ALTIVEC_BUILTIN_VAVGUW,
2783 ALTIVEC_BUILTIN_VAVGSW,
2784 ALTIVEC_BUILTIN_VCFUX,
2785 ALTIVEC_BUILTIN_VCFSX,
2786 ALTIVEC_BUILTIN_VCTSXS,
2787 ALTIVEC_BUILTIN_VCTUXS,
2788 ALTIVEC_BUILTIN_VCMPBFP,
2789 ALTIVEC_BUILTIN_VCMPEQUB,
2790 ALTIVEC_BUILTIN_VCMPEQUH,
2791 ALTIVEC_BUILTIN_VCMPEQUW,
2792 ALTIVEC_BUILTIN_VCMPEQFP,
2793 ALTIVEC_BUILTIN_VCMPGEFP,
2794 ALTIVEC_BUILTIN_VCMPGTUB,
2795 ALTIVEC_BUILTIN_VCMPGTSB,
2796 ALTIVEC_BUILTIN_VCMPGTUH,
2797 ALTIVEC_BUILTIN_VCMPGTSH,
2798 ALTIVEC_BUILTIN_VCMPGTUW,
2799 ALTIVEC_BUILTIN_VCMPGTSW,
2800 ALTIVEC_BUILTIN_VCMPGTFP,
2801 ALTIVEC_BUILTIN_VEXPTEFP,
2802 ALTIVEC_BUILTIN_VLOGEFP,
2803 ALTIVEC_BUILTIN_VMADDFP,
2804 ALTIVEC_BUILTIN_VMAXUB,
2805 ALTIVEC_BUILTIN_VMAXSB,
2806 ALTIVEC_BUILTIN_VMAXUH,
2807 ALTIVEC_BUILTIN_VMAXSH,
2808 ALTIVEC_BUILTIN_VMAXUW,
2809 ALTIVEC_BUILTIN_VMAXSW,
2810 ALTIVEC_BUILTIN_VMAXFP,
2811 ALTIVEC_BUILTIN_VMHADDSHS,
2812 ALTIVEC_BUILTIN_VMHRADDSHS,
2813 ALTIVEC_BUILTIN_VMLADDUHM,
2814 ALTIVEC_BUILTIN_VMRGHB,
2815 ALTIVEC_BUILTIN_VMRGHH,
2816 ALTIVEC_BUILTIN_VMRGHW,
2817 ALTIVEC_BUILTIN_VMRGLB,
2818 ALTIVEC_BUILTIN_VMRGLH,
2819 ALTIVEC_BUILTIN_VMRGLW,
2820 ALTIVEC_BUILTIN_VMSUMUBM,
2821 ALTIVEC_BUILTIN_VMSUMMBM,
2822 ALTIVEC_BUILTIN_VMSUMUHM,
2823 ALTIVEC_BUILTIN_VMSUMSHM,
2824 ALTIVEC_BUILTIN_VMSUMUHS,
2825 ALTIVEC_BUILTIN_VMSUMSHS,
2826 ALTIVEC_BUILTIN_VMINUB,
2827 ALTIVEC_BUILTIN_VMINSB,
2828 ALTIVEC_BUILTIN_VMINUH,
2829 ALTIVEC_BUILTIN_VMINSH,
2830 ALTIVEC_BUILTIN_VMINUW,
2831 ALTIVEC_BUILTIN_VMINSW,
2832 ALTIVEC_BUILTIN_VMINFP,
2833 ALTIVEC_BUILTIN_VMULEUB,
2834 ALTIVEC_BUILTIN_VMULESB,
2835 ALTIVEC_BUILTIN_VMULEUH,
2836 ALTIVEC_BUILTIN_VMULESH,
2837 ALTIVEC_BUILTIN_VMULOUB,
2838 ALTIVEC_BUILTIN_VMULOSB,
2839 ALTIVEC_BUILTIN_VMULOUH,
2840 ALTIVEC_BUILTIN_VMULOSH,
2841 ALTIVEC_BUILTIN_VNMSUBFP,
2842 ALTIVEC_BUILTIN_VNOR,
2843 ALTIVEC_BUILTIN_VOR,
2844 ALTIVEC_BUILTIN_VSEL_4SI,
2845 ALTIVEC_BUILTIN_VSEL_4SF,
2846 ALTIVEC_BUILTIN_VSEL_8HI,
2847 ALTIVEC_BUILTIN_VSEL_16QI,
2848 ALTIVEC_BUILTIN_VPERM_4SI,
2849 ALTIVEC_BUILTIN_VPERM_4SF,
2850 ALTIVEC_BUILTIN_VPERM_8HI,
2851 ALTIVEC_BUILTIN_VPERM_16QI,
2852 ALTIVEC_BUILTIN_VPKUHUM,
2853 ALTIVEC_BUILTIN_VPKUWUM,
2854 ALTIVEC_BUILTIN_VPKPX,
2855 ALTIVEC_BUILTIN_VPKUHSS,
2856 ALTIVEC_BUILTIN_VPKSHSS,
2857 ALTIVEC_BUILTIN_VPKUWSS,
2858 ALTIVEC_BUILTIN_VPKSWSS,
2859 ALTIVEC_BUILTIN_VPKUHUS,
2860 ALTIVEC_BUILTIN_VPKSHUS,
2861 ALTIVEC_BUILTIN_VPKUWUS,
2862 ALTIVEC_BUILTIN_VPKSWUS,
2863 ALTIVEC_BUILTIN_VREFP,
2864 ALTIVEC_BUILTIN_VRFIM,
2865 ALTIVEC_BUILTIN_VRFIN,
2866 ALTIVEC_BUILTIN_VRFIP,
2867 ALTIVEC_BUILTIN_VRFIZ,
2868 ALTIVEC_BUILTIN_VRLB,
2869 ALTIVEC_BUILTIN_VRLH,
2870 ALTIVEC_BUILTIN_VRLW,
2871 ALTIVEC_BUILTIN_VRSQRTEFP,
2872 ALTIVEC_BUILTIN_VSLB,
2873 ALTIVEC_BUILTIN_VSLH,
2874 ALTIVEC_BUILTIN_VSLW,
2875 ALTIVEC_BUILTIN_VSL,
2876 ALTIVEC_BUILTIN_VSLO,
2877 ALTIVEC_BUILTIN_VSPLTB,
2878 ALTIVEC_BUILTIN_VSPLTH,
2879 ALTIVEC_BUILTIN_VSPLTW,
2880 ALTIVEC_BUILTIN_VSPLTISB,
2881 ALTIVEC_BUILTIN_VSPLTISH,
2882 ALTIVEC_BUILTIN_VSPLTISW,
2883 ALTIVEC_BUILTIN_VSRB,
2884 ALTIVEC_BUILTIN_VSRH,
2885 ALTIVEC_BUILTIN_VSRW,
2886 ALTIVEC_BUILTIN_VSRAB,
2887 ALTIVEC_BUILTIN_VSRAH,
2888 ALTIVEC_BUILTIN_VSRAW,
2889 ALTIVEC_BUILTIN_VSR,
2890 ALTIVEC_BUILTIN_VSRO,
2891 ALTIVEC_BUILTIN_VSUBUBM,
2892 ALTIVEC_BUILTIN_VSUBUHM,
2893 ALTIVEC_BUILTIN_VSUBUWM,
2894 ALTIVEC_BUILTIN_VSUBFP,
2895 ALTIVEC_BUILTIN_VSUBCUW,
2896 ALTIVEC_BUILTIN_VSUBUBS,
2897 ALTIVEC_BUILTIN_VSUBSBS,
2898 ALTIVEC_BUILTIN_VSUBUHS,
2899 ALTIVEC_BUILTIN_VSUBSHS,
2900 ALTIVEC_BUILTIN_VSUBUWS,
2901 ALTIVEC_BUILTIN_VSUBSWS,
2902 ALTIVEC_BUILTIN_VSUM4UBS,
2903 ALTIVEC_BUILTIN_VSUM4SBS,
2904 ALTIVEC_BUILTIN_VSUM4SHS,
2905 ALTIVEC_BUILTIN_VSUM2SWS,
2906 ALTIVEC_BUILTIN_VSUMSWS,
2907 ALTIVEC_BUILTIN_VXOR,
2908 ALTIVEC_BUILTIN_VSLDOI_16QI,
2909 ALTIVEC_BUILTIN_VSLDOI_8HI,
2910 ALTIVEC_BUILTIN_VSLDOI_4SI,
2911 ALTIVEC_BUILTIN_VSLDOI_4SF,
2912 ALTIVEC_BUILTIN_VUPKHSB,
2913 ALTIVEC_BUILTIN_VUPKHPX,
2914 ALTIVEC_BUILTIN_VUPKHSH,
2915 ALTIVEC_BUILTIN_VUPKLSB,
2916 ALTIVEC_BUILTIN_VUPKLPX,
2917 ALTIVEC_BUILTIN_VUPKLSH,
2918 ALTIVEC_BUILTIN_MTVSCR,
2919 ALTIVEC_BUILTIN_MFVSCR,
2920 ALTIVEC_BUILTIN_DSSALL,
2921 ALTIVEC_BUILTIN_DSS,
2922 ALTIVEC_BUILTIN_LVSL,
2923 ALTIVEC_BUILTIN_LVSR,
2924 ALTIVEC_BUILTIN_DSTT,
2925 ALTIVEC_BUILTIN_DSTST,
2926 ALTIVEC_BUILTIN_DSTSTT,
2927 ALTIVEC_BUILTIN_DST,
2928 ALTIVEC_BUILTIN_LVEBX,
2929 ALTIVEC_BUILTIN_LVEHX,
2930 ALTIVEC_BUILTIN_LVEWX,
2931 ALTIVEC_BUILTIN_LVXL,
2932 ALTIVEC_BUILTIN_LVX,
2933 ALTIVEC_BUILTIN_STVX,
2934 ALTIVEC_BUILTIN_STVEBX,
2935 ALTIVEC_BUILTIN_STVEHX,
2936 ALTIVEC_BUILTIN_STVEWX,
2937 ALTIVEC_BUILTIN_STVXL,
2938 ALTIVEC_BUILTIN_VCMPBFP_P,
2939 ALTIVEC_BUILTIN_VCMPEQFP_P,
2940 ALTIVEC_BUILTIN_VCMPEQUB_P,
2941 ALTIVEC_BUILTIN_VCMPEQUH_P,
2942 ALTIVEC_BUILTIN_VCMPEQUW_P,
2943 ALTIVEC_BUILTIN_VCMPGEFP_P,
2944 ALTIVEC_BUILTIN_VCMPGTFP_P,
2945 ALTIVEC_BUILTIN_VCMPGTSB_P,
2946 ALTIVEC_BUILTIN_VCMPGTSH_P,
2947 ALTIVEC_BUILTIN_VCMPGTSW_P,
2948 ALTIVEC_BUILTIN_VCMPGTUB_P,
2949 ALTIVEC_BUILTIN_VCMPGTUH_P,
2950 ALTIVEC_BUILTIN_VCMPGTUW_P,
2951 ALTIVEC_BUILTIN_ABSS_V4SI,
2952 ALTIVEC_BUILTIN_ABSS_V8HI,
2953 ALTIVEC_BUILTIN_ABSS_V16QI,
2954 ALTIVEC_BUILTIN_ABS_V4SI,
2955 ALTIVEC_BUILTIN_ABS_V4SF,
2956 ALTIVEC_BUILTIN_ABS_V8HI,
2957 ALTIVEC_BUILTIN_ABS_V16QI
2959 , SPE_BUILTIN_EVADDW,
2962 SPE_BUILTIN_EVDIVWS,
2963 SPE_BUILTIN_EVDIVWU,
2965 SPE_BUILTIN_EVFSADD,
2966 SPE_BUILTIN_EVFSDIV,
2967 SPE_BUILTIN_EVFSMUL,
2968 SPE_BUILTIN_EVFSSUB,
2972 SPE_BUILTIN_EVLHHESPLATX,
2973 SPE_BUILTIN_EVLHHOSSPLATX,
2974 SPE_BUILTIN_EVLHHOUSPLATX,
2975 SPE_BUILTIN_EVLWHEX,
2976 SPE_BUILTIN_EVLWHOSX,
2977 SPE_BUILTIN_EVLWHOUX,
2978 SPE_BUILTIN_EVLWHSPLATX,
2979 SPE_BUILTIN_EVLWWSPLATX,
2980 SPE_BUILTIN_EVMERGEHI,
2981 SPE_BUILTIN_EVMERGEHILO,
2982 SPE_BUILTIN_EVMERGELO,
2983 SPE_BUILTIN_EVMERGELOHI,
2984 SPE_BUILTIN_EVMHEGSMFAA,
2985 SPE_BUILTIN_EVMHEGSMFAN,
2986 SPE_BUILTIN_EVMHEGSMIAA,
2987 SPE_BUILTIN_EVMHEGSMIAN,
2988 SPE_BUILTIN_EVMHEGUMIAA,
2989 SPE_BUILTIN_EVMHEGUMIAN,
2990 SPE_BUILTIN_EVMHESMF,
2991 SPE_BUILTIN_EVMHESMFA,
2992 SPE_BUILTIN_EVMHESMFAAW,
2993 SPE_BUILTIN_EVMHESMFANW,
2994 SPE_BUILTIN_EVMHESMI,
2995 SPE_BUILTIN_EVMHESMIA,
2996 SPE_BUILTIN_EVMHESMIAAW,
2997 SPE_BUILTIN_EVMHESMIANW,
2998 SPE_BUILTIN_EVMHESSF,
2999 SPE_BUILTIN_EVMHESSFA,
3000 SPE_BUILTIN_EVMHESSFAAW,
3001 SPE_BUILTIN_EVMHESSFANW,
3002 SPE_BUILTIN_EVMHESSIAAW,
3003 SPE_BUILTIN_EVMHESSIANW,
3004 SPE_BUILTIN_EVMHEUMI,
3005 SPE_BUILTIN_EVMHEUMIA,
3006 SPE_BUILTIN_EVMHEUMIAAW,
3007 SPE_BUILTIN_EVMHEUMIANW,
3008 SPE_BUILTIN_EVMHEUSIAAW,
3009 SPE_BUILTIN_EVMHEUSIANW,
3010 SPE_BUILTIN_EVMHOGSMFAA,
3011 SPE_BUILTIN_EVMHOGSMFAN,
3012 SPE_BUILTIN_EVMHOGSMIAA,
3013 SPE_BUILTIN_EVMHOGSMIAN,
3014 SPE_BUILTIN_EVMHOGUMIAA,
3015 SPE_BUILTIN_EVMHOGUMIAN,
3016 SPE_BUILTIN_EVMHOSMF,
3017 SPE_BUILTIN_EVMHOSMFA,
3018 SPE_BUILTIN_EVMHOSMFAAW,
3019 SPE_BUILTIN_EVMHOSMFANW,
3020 SPE_BUILTIN_EVMHOSMI,
3021 SPE_BUILTIN_EVMHOSMIA,
3022 SPE_BUILTIN_EVMHOSMIAAW,
3023 SPE_BUILTIN_EVMHOSMIANW,
3024 SPE_BUILTIN_EVMHOSSF,
3025 SPE_BUILTIN_EVMHOSSFA,
3026 SPE_BUILTIN_EVMHOSSFAAW,
3027 SPE_BUILTIN_EVMHOSSFANW,
3028 SPE_BUILTIN_EVMHOSSIAAW,
3029 SPE_BUILTIN_EVMHOSSIANW,
3030 SPE_BUILTIN_EVMHOUMI,
3031 SPE_BUILTIN_EVMHOUMIA,
3032 SPE_BUILTIN_EVMHOUMIAAW,
3033 SPE_BUILTIN_EVMHOUMIANW,
3034 SPE_BUILTIN_EVMHOUSIAAW,
3035 SPE_BUILTIN_EVMHOUSIANW,
3036 SPE_BUILTIN_EVMWHSMF,
3037 SPE_BUILTIN_EVMWHSMFA,
3038 SPE_BUILTIN_EVMWHSMI,
3039 SPE_BUILTIN_EVMWHSMIA,
3040 SPE_BUILTIN_EVMWHSSF,
3041 SPE_BUILTIN_EVMWHSSFA,
3042 SPE_BUILTIN_EVMWHUMI,
3043 SPE_BUILTIN_EVMWHUMIA,
3044 SPE_BUILTIN_EVMWLSMIAAW,
3045 SPE_BUILTIN_EVMWLSMIANW,
3046 SPE_BUILTIN_EVMWLSSIAAW,
3047 SPE_BUILTIN_EVMWLSSIANW,
3048 SPE_BUILTIN_EVMWLUMI,
3049 SPE_BUILTIN_EVMWLUMIA,
3050 SPE_BUILTIN_EVMWLUMIAAW,
3051 SPE_BUILTIN_EVMWLUMIANW,
3052 SPE_BUILTIN_EVMWLUSIAAW,
3053 SPE_BUILTIN_EVMWLUSIANW,
3054 SPE_BUILTIN_EVMWSMF,
3055 SPE_BUILTIN_EVMWSMFA,
3056 SPE_BUILTIN_EVMWSMFAA,
3057 SPE_BUILTIN_EVMWSMFAN,
3058 SPE_BUILTIN_EVMWSMI,
3059 SPE_BUILTIN_EVMWSMIA,
3060 SPE_BUILTIN_EVMWSMIAA,
3061 SPE_BUILTIN_EVMWSMIAN,
3062 SPE_BUILTIN_EVMWHSSFAA,
3063 SPE_BUILTIN_EVMWSSF,
3064 SPE_BUILTIN_EVMWSSFA,
3065 SPE_BUILTIN_EVMWSSFAA,
3066 SPE_BUILTIN_EVMWSSFAN,
3067 SPE_BUILTIN_EVMWUMI,
3068 SPE_BUILTIN_EVMWUMIA,
3069 SPE_BUILTIN_EVMWUMIAA,
3070 SPE_BUILTIN_EVMWUMIAN,
3079 SPE_BUILTIN_EVSTDDX,
3080 SPE_BUILTIN_EVSTDHX,
3081 SPE_BUILTIN_EVSTDWX,
3082 SPE_BUILTIN_EVSTWHEX,
3083 SPE_BUILTIN_EVSTWHOX,
3084 SPE_BUILTIN_EVSTWWEX,
3085 SPE_BUILTIN_EVSTWWOX,
3086 SPE_BUILTIN_EVSUBFW,
3089 SPE_BUILTIN_EVADDSMIAAW,
3090 SPE_BUILTIN_EVADDSSIAAW,
3091 SPE_BUILTIN_EVADDUMIAAW,
3092 SPE_BUILTIN_EVADDUSIAAW,
3093 SPE_BUILTIN_EVCNTLSW,
3094 SPE_BUILTIN_EVCNTLZW,
3095 SPE_BUILTIN_EVEXTSB,
3096 SPE_BUILTIN_EVEXTSH,
3097 SPE_BUILTIN_EVFSABS,
3098 SPE_BUILTIN_EVFSCFSF,
3099 SPE_BUILTIN_EVFSCFSI,
3100 SPE_BUILTIN_EVFSCFUF,
3101 SPE_BUILTIN_EVFSCFUI,
3102 SPE_BUILTIN_EVFSCTSF,
3103 SPE_BUILTIN_EVFSCTSI,
3104 SPE_BUILTIN_EVFSCTSIZ,
3105 SPE_BUILTIN_EVFSCTUF,
3106 SPE_BUILTIN_EVFSCTUI,
3107 SPE_BUILTIN_EVFSCTUIZ,
3108 SPE_BUILTIN_EVFSNABS,
3109 SPE_BUILTIN_EVFSNEG,
3113 SPE_BUILTIN_EVSUBFSMIAAW,
3114 SPE_BUILTIN_EVSUBFSSIAAW,
3115 SPE_BUILTIN_EVSUBFUMIAAW,
3116 SPE_BUILTIN_EVSUBFUSIAAW,
3117 SPE_BUILTIN_EVADDIW,
3121 SPE_BUILTIN_EVLHHESPLAT,
3122 SPE_BUILTIN_EVLHHOSSPLAT,
3123 SPE_BUILTIN_EVLHHOUSPLAT,
3125 SPE_BUILTIN_EVLWHOS,
3126 SPE_BUILTIN_EVLWHOU,
3127 SPE_BUILTIN_EVLWHSPLAT,
3128 SPE_BUILTIN_EVLWWSPLAT,
3131 SPE_BUILTIN_EVSRWIS,
3132 SPE_BUILTIN_EVSRWIU,
3136 SPE_BUILTIN_EVSTWHE,
3137 SPE_BUILTIN_EVSTWHO,
3138 SPE_BUILTIN_EVSTWWE,
3139 SPE_BUILTIN_EVSTWWO,
3140 SPE_BUILTIN_EVSUBIFW,
3143 SPE_BUILTIN_EVCMPEQ,
3144 SPE_BUILTIN_EVCMPGTS,
3145 SPE_BUILTIN_EVCMPGTU,
3146 SPE_BUILTIN_EVCMPLTS,
3147 SPE_BUILTIN_EVCMPLTU,
3148 SPE_BUILTIN_EVFSCMPEQ,
3149 SPE_BUILTIN_EVFSCMPGT,
3150 SPE_BUILTIN_EVFSCMPLT,
3151 SPE_BUILTIN_EVFSTSTEQ,
3152 SPE_BUILTIN_EVFSTSTGT,
3153 SPE_BUILTIN_EVFSTSTLT,
3155 /* EVSEL compares. */
3156 SPE_BUILTIN_EVSEL_CMPEQ,
3157 SPE_BUILTIN_EVSEL_CMPGTS,
3158 SPE_BUILTIN_EVSEL_CMPGTU,
3159 SPE_BUILTIN_EVSEL_CMPLTS,
3160 SPE_BUILTIN_EVSEL_CMPLTU,
3161 SPE_BUILTIN_EVSEL_FSCMPEQ,
3162 SPE_BUILTIN_EVSEL_FSCMPGT,
3163 SPE_BUILTIN_EVSEL_FSCMPLT,
3164 SPE_BUILTIN_EVSEL_FSTSTEQ,
3165 SPE_BUILTIN_EVSEL_FSTSTGT,
3166 SPE_BUILTIN_EVSEL_FSTSTLT,
3168 SPE_BUILTIN_EVSPLATFI,
3169 SPE_BUILTIN_EVSPLATI,
3170 SPE_BUILTIN_EVMWHSSMAA,
3171 SPE_BUILTIN_EVMWHSMFAA,
3172 SPE_BUILTIN_EVMWHSMIAA,
3173 SPE_BUILTIN_EVMWHUSIAA,
3174 SPE_BUILTIN_EVMWHUMIAA,
3175 SPE_BUILTIN_EVMWHSSFAN,
3176 SPE_BUILTIN_EVMWHSSIAN,
3177 SPE_BUILTIN_EVMWHSMFAN,
3178 SPE_BUILTIN_EVMWHSMIAN,
3179 SPE_BUILTIN_EVMWHUSIAN,
3180 SPE_BUILTIN_EVMWHUMIAN,
3181 SPE_BUILTIN_EVMWHGSSFAA,
3182 SPE_BUILTIN_EVMWHGSMFAA,
3183 SPE_BUILTIN_EVMWHGSMIAA,
3184 SPE_BUILTIN_EVMWHGUMIAA,
3185 SPE_BUILTIN_EVMWHGSSFAN,
3186 SPE_BUILTIN_EVMWHGSMFAN,
3187 SPE_BUILTIN_EVMWHGSMIAN,
3188 SPE_BUILTIN_EVMWHGUMIAN,
3189 SPE_BUILTIN_MTSPEFSCR,
3190 SPE_BUILTIN_MFSPEFSCR,
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