1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common ASM definitions used by ASM_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define ASM_CPU_SPEC \
53 %{mpower: %{!mpower2: -mpwr}} \
56 %{mno-power: %{!mpowerpc*: -mcom}} \
57 %{!mno-power: %{!mpower2: %(asm_default)}}} \
58 %{mcpu=common: -mcom} \
59 %{mcpu=power: -mpwr} \
60 %{mcpu=power2: -mpwrx} \
61 %{mcpu=power3: -m604} \
62 %{mcpu=power4: -mpower4} \
63 %{mcpu=powerpc: -mppc} \
65 %{mcpu=rios1: -mpwr} \
66 %{mcpu=rios2: -mpwrx} \
78 %{mcpu=ec603e: -mppc} \
91 %{mcpu=8540: -me500} \
92 %{maltivec: -maltivec}"
94 #define CPP_DEFAULT_SPEC ""
96 #define ASM_DEFAULT_SPEC ""
98 /* This macro defines names of additional specifications to put in the specs
99 that can be used in various specifications like CC1_SPEC. Its definition
100 is an initializer with a subgrouping for each command option.
102 Each subgrouping contains a string constant, that defines the
103 specification name, and a string constant that used by the GNU CC driver
106 Do not define this macro if it does not need to do anything. */
108 #define SUBTARGET_EXTRA_SPECS
110 #define EXTRA_SPECS \
111 { "cpp_default", CPP_DEFAULT_SPEC }, \
112 { "asm_cpu", ASM_CPU_SPEC }, \
113 { "asm_default", ASM_DEFAULT_SPEC }, \
114 SUBTARGET_EXTRA_SPECS
116 /* Architecture type. */
118 extern int target_flags;
120 /* Use POWER architecture instructions and MQ register. */
121 #define MASK_POWER 0x00000001
123 /* Use POWER2 extensions to POWER architecture. */
124 #define MASK_POWER2 0x00000002
126 /* Use PowerPC architecture instructions. */
127 #define MASK_POWERPC 0x00000004
129 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
130 #define MASK_PPC_GPOPT 0x00000008
132 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
133 #define MASK_PPC_GFXOPT 0x00000010
135 /* Use PowerPC-64 architecture instructions. */
136 #define MASK_POWERPC64 0x00000020
138 /* Use revised mnemonic names defined for PowerPC architecture. */
139 #define MASK_NEW_MNEMONICS 0x00000040
141 /* Disable placing fp constants in the TOC; can be turned on when the
143 #define MASK_NO_FP_IN_TOC 0x00000080
145 /* Disable placing symbol+offset constants in the TOC; can be turned on when
146 the TOC overflows. */
147 #define MASK_NO_SUM_IN_TOC 0x00000100
149 /* Output only one TOC entry per module. Normally linking fails if
150 there are more than 16K unique variables/constants in an executable. With
151 this option, linking fails only if there are more than 16K modules, or
152 if there are more than 16K unique variables/constant in a single module.
154 This is at the cost of having 2 extra loads and one extra store per
155 function, and one less allocable register. */
156 #define MASK_MINIMAL_TOC 0x00000200
158 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
159 #define MASK_64BIT 0x00000400
161 /* Disable use of FPRs. */
162 #define MASK_SOFT_FLOAT 0x00000800
164 /* Enable load/store multiple, even on PowerPC */
165 #define MASK_MULTIPLE 0x00001000
167 /* Use string instructions for block moves */
168 #define MASK_STRING 0x00002000
170 /* Disable update form of load/store */
171 #define MASK_NO_UPDATE 0x00004000
173 /* Disable fused multiply/add operations */
174 #define MASK_NO_FUSED_MADD 0x00008000
176 /* Nonzero if we need to schedule the prolog and epilog. */
177 #define MASK_SCHED_PROLOG 0x00010000
179 /* Use AltiVec instructions. */
180 #define MASK_ALTIVEC 0x00020000
182 /* Return small structures in memory (as the AIX ABI requires). */
183 #define MASK_AIX_STRUCT_RET 0x00040000
185 /* The only remaining free bits are 0x00780000. sysv4.h uses
186 0x00800000 -> 0x40000000, and 0x80000000 is not available
187 because target_flags is signed. */
189 #define TARGET_POWER (target_flags & MASK_POWER)
190 #define TARGET_POWER2 (target_flags & MASK_POWER2)
191 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
192 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
193 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
194 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
195 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
196 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
197 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
198 #define TARGET_64BIT (target_flags & MASK_64BIT)
199 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
200 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
201 #define TARGET_STRING (target_flags & MASK_STRING)
202 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
203 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
204 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
205 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
206 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
208 #define TARGET_32BIT (! TARGET_64BIT)
209 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
210 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
211 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
214 /* For libgcc2 we make sure this is a compile time constant */
215 #if defined (__64BIT__) || defined (__powerpc64__)
216 #define TARGET_POWERPC64 1
218 #define TARGET_POWERPC64 0
221 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
224 #define TARGET_XL_CALL 0
226 /* Run-time compilation parameters selecting different hardware subsets.
228 Macro to define tables used to set the flags.
229 This is a list in braces of pairs in braces,
230 each pair being { "NAME", VALUE }
231 where VALUE is the bits to set or minus the bits to clear.
232 An empty string NAME is used to identify the default VALUE. */
234 #define TARGET_SWITCHES \
235 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
236 N_("Use POWER instruction set")}, \
237 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
239 N_("Use POWER2 instruction set")}, \
240 {"no-power2", - MASK_POWER2, \
241 N_("Do not use POWER2 instruction set")}, \
242 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
244 N_("Do not use POWER instruction set")}, \
245 {"powerpc", MASK_POWERPC, \
246 N_("Use PowerPC instruction set")}, \
247 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
248 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
249 N_("Do not use PowerPC instruction set")}, \
250 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
251 N_("Use PowerPC General Purpose group optional instructions")},\
252 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
253 N_("Don't use PowerPC General Purpose group optional instructions")},\
254 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
255 N_("Use PowerPC Graphics group optional instructions")},\
256 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
257 N_("Don't use PowerPC Graphics group optional instructions")},\
258 {"powerpc64", MASK_POWERPC64, \
259 N_("Use PowerPC-64 instruction set")}, \
260 {"no-powerpc64", - MASK_POWERPC64, \
261 N_("Don't use PowerPC-64 instruction set")}, \
262 {"altivec", MASK_ALTIVEC , \
263 N_("Use AltiVec instructions")}, \
264 {"no-altivec", - MASK_ALTIVEC , \
265 N_("Don't use AltiVec instructions")}, \
266 {"new-mnemonics", MASK_NEW_MNEMONICS, \
267 N_("Use new mnemonics for PowerPC architecture")},\
268 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
269 N_("Use old mnemonics for PowerPC architecture")},\
270 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
271 | MASK_MINIMAL_TOC), \
272 N_("Put everything in the regular TOC")}, \
273 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
274 N_("Place floating point constants in TOC")}, \
275 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
276 N_("Don't place floating point constants in TOC")},\
277 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
278 N_("Place symbol+offset constants in TOC")}, \
279 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
280 N_("Don't place symbol+offset constants in TOC")},\
281 {"minimal-toc", MASK_MINIMAL_TOC, \
282 "Use only one TOC entry per procedure"}, \
283 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
285 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
286 N_("Place variable addresses in the regular TOC")},\
287 {"hard-float", - MASK_SOFT_FLOAT, \
288 N_("Use hardware fp")}, \
289 {"soft-float", MASK_SOFT_FLOAT, \
290 N_("Do not use hardware fp")}, \
291 {"multiple", MASK_MULTIPLE, \
292 N_("Generate load/store multiple instructions")}, \
293 {"no-multiple", - MASK_MULTIPLE, \
294 N_("Do not generate load/store multiple instructions")},\
295 {"string", MASK_STRING, \
296 N_("Generate string instructions for block moves")},\
297 {"no-string", - MASK_STRING, \
298 N_("Do not generate string instructions for block moves")},\
299 {"update", - MASK_NO_UPDATE, \
300 N_("Generate load/store with update instructions")},\
301 {"no-update", MASK_NO_UPDATE, \
302 N_("Do not generate load/store with update instructions")},\
303 {"fused-madd", - MASK_NO_FUSED_MADD, \
304 N_("Generate fused multiply/add instructions")},\
305 {"no-fused-madd", MASK_NO_FUSED_MADD, \
306 N_("Don't generate fused multiply/add instructions")},\
307 {"sched-prolog", MASK_SCHED_PROLOG, \
309 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
310 N_("Don't schedule the start and end of the procedure")},\
311 {"sched-epilog", MASK_SCHED_PROLOG, \
313 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
315 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
316 N_("Return all structures in memory (AIX default)")},\
317 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
318 N_("Return small structures in registers (SVR4 default)")},\
319 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
321 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
324 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
327 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
329 /* This is meant to be redefined in the host dependent files */
330 #define SUBTARGET_SWITCHES
332 /* Processor type. Order must match cpu attribute in MD file. */
355 extern enum processor_type rs6000_cpu;
357 /* Recast the processor type to the cpu attribute. */
358 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
360 /* Define generic processor types based upon current deployment. */
361 #define PROCESSOR_COMMON PROCESSOR_PPC601
362 #define PROCESSOR_POWER PROCESSOR_RIOS1
363 #define PROCESSOR_POWERPC PROCESSOR_PPC604
364 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
366 /* Define the default processor. This is overridden by other tm.h files. */
367 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
368 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
370 /* Specify the dialect of assembler to use. New mnemonics is dialect one
371 and the old mnemonics are dialect zero. */
372 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
374 /* This is meant to be overridden in target specific files. */
375 #define SUBTARGET_OPTIONS
377 #define TARGET_OPTIONS \
379 {"cpu=", &rs6000_select[1].string, \
380 N_("Use features of and schedule code for given CPU") }, \
381 {"tune=", &rs6000_select[2].string, \
382 N_("Schedule code for given CPU") }, \
383 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
384 {"traceback=", &rs6000_traceback_name, \
385 N_("Select full, part, or no traceback table") }, \
386 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
387 {"long-double-", &rs6000_long_double_size_string, \
388 N_("Specify size of long double (64 or 128 bits)") }, \
389 {"isel=", &rs6000_isel_string, \
390 N_("Specify yes/no if isel instructions should be generated") }, \
391 {"vrsave=", &rs6000_altivec_vrsave_string, \
392 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
393 {"longcall", &rs6000_longcall_switch, \
394 N_("Avoid all range limits on call instructions") }, \
395 {"no-longcall", &rs6000_longcall_switch, "" }, \
399 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
400 struct rs6000_cpu_select
408 extern struct rs6000_cpu_select rs6000_select[];
411 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
412 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
413 extern int rs6000_debug_stack; /* debug stack applications */
414 extern int rs6000_debug_arg; /* debug argument handling */
416 #define TARGET_DEBUG_STACK rs6000_debug_stack
417 #define TARGET_DEBUG_ARG rs6000_debug_arg
419 extern const char *rs6000_traceback_name; /* Type of traceback table. */
421 /* These are separate from target_flags because we've run out of bits
423 extern const char *rs6000_long_double_size_string;
424 extern int rs6000_long_double_type_size;
425 extern int rs6000_altivec_abi;
426 extern int rs6000_spe_abi;
427 extern int rs6000_isel;
428 extern int rs6000_fprs;
429 extern const char *rs6000_isel_string;
430 extern const char *rs6000_altivec_vrsave_string;
431 extern int rs6000_altivec_vrsave;
432 extern const char *rs6000_longcall_switch;
433 extern int rs6000_default_long_calls;
435 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
436 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
437 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
439 #define TARGET_SPE_ABI 0
441 #define TARGET_ISEL 0
442 #define TARGET_FPRS 1
444 /* Sometimes certain combinations of command options do not make sense
445 on a particular target machine. You can define a macro
446 `OVERRIDE_OPTIONS' to take account of this. This macro, if
447 defined, is executed once just after all the command options have
450 Don't use this macro to turn on various extra optimizations for
451 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
453 On the RS/6000 this is used to define the target cpu type. */
455 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
457 /* Define this to change the optimizations performed by default. */
458 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
460 /* Show we can debug even without a frame pointer. */
461 #define CAN_DEBUG_WITHOUT_FP
464 #define REGISTER_TARGET_PRAGMAS() do { \
465 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
468 /* Target #defines. */
469 #define TARGET_CPU_CPP_BUILTINS() \
470 rs6000_cpu_cpp_builtins (pfile)
472 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
473 we're compiling for. Some configurations may need to override it. */
474 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
477 if (BYTES_BIG_ENDIAN) \
479 builtin_define ("__BIG_ENDIAN__"); \
480 builtin_define ("_BIG_ENDIAN"); \
481 builtin_assert ("machine=bigendian"); \
485 builtin_define ("__LITTLE_ENDIAN__"); \
486 builtin_define ("_LITTLE_ENDIAN"); \
487 builtin_assert ("machine=littleendian"); \
492 /* Target machine storage layout. */
494 /* Define this macro if it is advisable to hold scalars in registers
495 in a wider mode than that declared by the program. In such cases,
496 the value is constrained to be within the bounds of the declared
497 type, but kept valid in the wider mode. The signedness of the
498 extension may differ from that of the type. */
500 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
501 if (GET_MODE_CLASS (MODE) == MODE_INT \
502 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
505 /* Define this if function arguments should also be promoted using the above
508 #define PROMOTE_FUNCTION_ARGS
510 /* Likewise, if the function return value is promoted. */
512 #define PROMOTE_FUNCTION_RETURN
514 /* Define this if most significant bit is lowest numbered
515 in instructions that operate on numbered bit-fields. */
516 /* That is true on RS/6000. */
517 #define BITS_BIG_ENDIAN 1
519 /* Define this if most significant byte of a word is the lowest numbered. */
520 /* That is true on RS/6000. */
521 #define BYTES_BIG_ENDIAN 1
523 /* Define this if most significant word of a multiword number is lowest
526 For RS/6000 we can decide arbitrarily since there are no machine
527 instructions for them. Might as well be consistent with bits and bytes. */
528 #define WORDS_BIG_ENDIAN 1
530 #define MAX_BITS_PER_WORD 64
532 /* Width of a word, in units (bytes). */
533 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
535 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
537 #define MIN_UNITS_PER_WORD 4
539 #define UNITS_PER_FP_WORD 8
540 #define UNITS_PER_ALTIVEC_WORD 16
541 #define UNITS_PER_SPE_WORD 8
543 /* Type used for ptrdiff_t, as a string used in a declaration. */
544 #define PTRDIFF_TYPE "int"
546 /* Type used for size_t, as a string used in a declaration. */
547 #define SIZE_TYPE "long unsigned int"
549 /* Type used for wchar_t, as a string used in a declaration. */
550 #define WCHAR_TYPE "short unsigned int"
552 /* Width of wchar_t in bits. */
553 #define WCHAR_TYPE_SIZE 16
555 /* A C expression for the size in bits of the type `short' on the
556 target machine. If you don't define this, the default is half a
557 word. (If this would be less than one storage unit, it is
558 rounded up to one unit.) */
559 #define SHORT_TYPE_SIZE 16
561 /* A C expression for the size in bits of the type `int' on the
562 target machine. If you don't define this, the default is one
564 #define INT_TYPE_SIZE 32
566 /* A C expression for the size in bits of the type `long' on the
567 target machine. If you don't define this, the default is one
569 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
570 #define MAX_LONG_TYPE_SIZE 64
572 /* A C expression for the size in bits of the type `long long' on the
573 target machine. If you don't define this, the default is two
575 #define LONG_LONG_TYPE_SIZE 64
577 /* A C expression for the size in bits of the type `float' on the
578 target machine. If you don't define this, the default is one
580 #define FLOAT_TYPE_SIZE 32
582 /* A C expression for the size in bits of the type `double' on the
583 target machine. If you don't define this, the default is two
585 #define DOUBLE_TYPE_SIZE 64
587 /* A C expression for the size in bits of the type `long double' on
588 the target machine. If you don't define this, the default is two
590 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
592 /* Constant which presents upper bound of the above value. */
593 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
595 /* Define this to set long double type size to use in libgcc2.c, which can
596 not depend on target_flags. */
597 #ifdef __LONG_DOUBLE_128__
598 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
600 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
603 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
604 #define WIDEST_HARDWARE_FP_SIZE 64
606 /* Width in bits of a pointer.
607 See also the macro `Pmode' defined below. */
608 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
610 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
611 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
613 /* Boundary (in *bits*) on which stack pointer should be aligned. */
614 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
616 /* Allocation boundary (in *bits*) for the code of a function. */
617 #define FUNCTION_BOUNDARY 32
619 /* No data type wants to be aligned rounder than this. */
620 #define BIGGEST_ALIGNMENT 128
622 /* A C expression to compute the alignment for a variables in the
623 local store. TYPE is the data type, and ALIGN is the alignment
624 that the object would ordinarily have. */
625 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
626 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
627 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
629 /* Alignment of field after `int : 0' in a structure. */
630 #define EMPTY_FIELD_BOUNDARY 32
632 /* Every structure's size must be a multiple of this. */
633 #define STRUCTURE_SIZE_BOUNDARY 8
635 /* Return 1 if a structure or array containing FIELD should be
636 accessed using `BLKMODE'.
638 For the SPE, simd types are V2SI, and gcc can be tempted to put the
639 entire thing in a DI and use subregs to access the internals.
640 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
641 back-end. Because a single GPR can hold a V2SI, but not a DI, the
642 best thing to do is set structs to BLKmode and avoid Severe Tire
644 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
645 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
647 /* A bit-field declared as `int' forces `int' alignment for the struct. */
648 #define PCC_BITFIELD_TYPE_MATTERS 1
650 /* Make strings word-aligned so strcpy from constants will be faster.
651 Make vector constants quadword aligned. */
652 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
653 (TREE_CODE (EXP) == STRING_CST \
654 && (ALIGN) < BITS_PER_WORD \
658 /* Make arrays of chars word-aligned for the same reasons.
659 Align vectors to 128 bits. */
660 #define DATA_ALIGNMENT(TYPE, ALIGN) \
661 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
662 : TREE_CODE (TYPE) == ARRAY_TYPE \
663 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
664 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
666 /* Nonzero if move instructions will actually fail to work
667 when given unaligned data. */
668 #define STRICT_ALIGNMENT 0
670 /* Define this macro to be the value 1 if unaligned accesses have a cost
671 many times greater than aligned accesses, for example if they are
672 emulated in a trap handler. */
673 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
675 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
676 || (MODE) == DImode) \
679 /* Standard register usage. */
681 /* Number of actual hardware registers.
682 The hardware registers are assigned numbers for the compiler
683 from 0 to just below FIRST_PSEUDO_REGISTER.
684 All registers that the compiler knows about must be given numbers,
685 even those that are not normally considered general registers.
687 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
688 an MQ register, a count register, a link register, and 8 condition
689 register fields, which we view here as separate registers. AltiVec
690 adds 32 vector registers and a VRsave register.
692 In addition, the difference between the frame and argument pointers is
693 a function of the number of registers saved, so we need to have a
694 register for AP that will later be eliminated in favor of SP or FP.
695 This is a normal register, but it is fixed.
697 We also create a pseudo register for float/int conversions, that will
698 really represent the memory location used. It is represented here as
699 a register, in order to work around problems in allocating stack storage
700 in inline functions. */
702 #define FIRST_PSEUDO_REGISTER 113
704 /* This must be included for pre gcc 3.0 glibc compatibility. */
705 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
707 /* Add 32 dwarf columns for synthetic SPE registers. The SPE
708 synthetic registers are 113 through 145. */
709 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
711 /* 1 for registers that have pervasive standard uses
712 and are not available for the register allocator.
714 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
715 as a local register; for all other OS's r2 is the TOC pointer.
717 cr5 is not supposed to be used.
719 On System V implementations, r13 is fixed and not available for use. */
721 #define FIXED_REGISTERS \
722 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
725 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
726 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
727 /* AltiVec registers. */ \
728 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
729 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
734 /* 1 for registers not available across function calls.
735 These must include the FIXED_REGISTERS and also any
736 registers that can be used without being saved.
737 The latter must include the registers where values are returned
738 and the register where structure-value addresses are passed.
739 Aside from that, you can include as many other registers as you like. */
741 #define CALL_USED_REGISTERS \
742 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
745 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
746 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
747 /* AltiVec registers. */ \
748 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
749 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
754 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
755 the entire set of `FIXED_REGISTERS' be included.
756 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
757 This macro is optional. If not specified, it defaults to the value
758 of `CALL_USED_REGISTERS'. */
760 #define CALL_REALLY_USED_REGISTERS \
761 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
763 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
765 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
766 /* AltiVec registers. */ \
767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
779 #define MAX_CR_REGNO 75
781 #define FIRST_ALTIVEC_REGNO 77
782 #define LAST_ALTIVEC_REGNO 108
783 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
784 #define VRSAVE_REGNO 109
785 #define VSCR_REGNO 110
786 #define SPE_ACC_REGNO 111
787 #define SPEFSCR_REGNO 112
789 /* List the order in which to allocate registers. Each register must be
790 listed once, even those in FIXED_REGISTERS.
792 We allocate in the following order:
793 fp0 (not saved or used for anything)
794 fp13 - fp2 (not saved; incoming fp arg registers)
795 fp1 (not saved; return value)
796 fp31 - fp14 (saved; order given to save least number)
797 cr7, cr6 (not saved or special)
798 cr1 (not saved, but used for FP operations)
799 cr0 (not saved, but used for arithmetic operations)
800 cr4, cr3, cr2 (saved)
801 r0 (not saved; cannot be base reg)
802 r9 (not saved; best for TImode)
803 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
804 r3 (not saved; return value register)
805 r31 - r13 (saved; order given to save least number)
806 r12 (not saved; if used for DImode or DFmode would use r13)
807 mq (not saved; best to use it if we can)
808 ctr (not saved; when we have the choice ctr is better)
810 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
811 spe_acc, spefscr (fixed)
814 v0 - v1 (not saved or used for anything)
815 v13 - v3 (not saved; incoming vector arg registers)
816 v2 (not saved; incoming vector arg reg; return value)
817 v19 - v14 (not saved or used for anything)
818 v31 - v20 (saved; order given to save least number)
822 #define REG_ALLOC_ORDER \
824 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
826 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
827 50, 49, 48, 47, 46, \
828 75, 74, 69, 68, 72, 71, 70, \
830 9, 11, 10, 8, 7, 6, 5, 4, \
832 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
833 18, 17, 16, 15, 14, 13, 12, \
836 /* AltiVec registers. */ \
838 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
840 96, 95, 94, 93, 92, 91, \
841 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
846 /* True if register is floating-point. */
847 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
849 /* True if register is a condition register. */
850 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
852 /* True if register is a condition register, but not cr0. */
853 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
855 /* True if register is an integer register. */
856 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
858 /* SPE SIMD registers are just the GPRs. */
859 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
861 /* True if register is the XER register. */
862 #define XER_REGNO_P(N) ((N) == XER_REGNO)
864 /* True if register is an AltiVec register. */
865 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
867 /* Return number of consecutive hard regs needed starting at reg REGNO
868 to hold something of mode MODE.
869 This is ordinarily the length in words of a value of mode MODE
870 but can be less for certain modes in special long registers.
872 For the SPE, GPRs are 64 bits but only 32 bits are visible in
873 scalar instructions. The upper 32 bits are only available to the
876 POWER and PowerPC GPRs hold 32 bits worth;
877 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
879 #define HARD_REGNO_NREGS(REGNO, MODE) \
880 (FP_REGNO_P (REGNO) \
881 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
882 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
883 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
884 : ALTIVEC_REGNO_P (REGNO) \
885 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
886 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
888 #define ALTIVEC_VECTOR_MODE(MODE) \
889 ((MODE) == V16QImode \
890 || (MODE) == V8HImode \
891 || (MODE) == V4SFmode \
892 || (MODE) == V4SImode)
894 #define SPE_VECTOR_MODE(MODE) \
895 ((MODE) == V4HImode \
896 || (MODE) == V2SFmode \
897 || (MODE) == V1DImode \
898 || (MODE) == V2SImode)
900 /* Define this macro to be nonzero if the port is prepared to handle
901 insns involving vector mode MODE. At the very least, it must have
902 move patterns for this mode. */
904 #define VECTOR_MODE_SUPPORTED_P(MODE) \
905 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
906 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
908 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
909 For POWER and PowerPC, the GPRs can hold any mode, but the float
910 registers only can hold floating modes and DImode, and CR register only
911 can hold CC modes. We cannot put TImode anywhere except general
912 register and it must be able to fit within the register set. */
914 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
915 (FP_REGNO_P (REGNO) ? \
916 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
917 || (GET_MODE_CLASS (MODE) == MODE_INT \
918 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
919 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
920 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
921 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
922 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
923 : ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
926 /* Value is 1 if it is a good idea to tie two pseudo registers
927 when one has mode MODE1 and one has mode MODE2.
928 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
929 for any hard reg, then this must be 0 for correct output. */
930 #define MODES_TIEABLE_P(MODE1, MODE2) \
931 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
932 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
933 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
934 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
935 : GET_MODE_CLASS (MODE1) == MODE_CC \
936 ? GET_MODE_CLASS (MODE2) == MODE_CC \
937 : GET_MODE_CLASS (MODE2) == MODE_CC \
938 ? GET_MODE_CLASS (MODE1) == MODE_CC \
939 : ALTIVEC_VECTOR_MODE (MODE1) \
940 ? ALTIVEC_VECTOR_MODE (MODE2) \
941 : ALTIVEC_VECTOR_MODE (MODE2) \
942 ? ALTIVEC_VECTOR_MODE (MODE1) \
945 /* A C expression returning the cost of moving data from a register of class
946 CLASS1 to one of CLASS2. */
948 #define REGISTER_MOVE_COST rs6000_register_move_cost
950 /* A C expressions returning the cost of moving data of MODE from a register to
953 #define MEMORY_MOVE_COST rs6000_memory_move_cost
955 /* Specify the cost of a branch insn; roughly the number of extra insns that
956 should be added to avoid a branch.
958 Set this to 3 on the RS/6000 since that is roughly the average cost of an
959 unscheduled conditional branch. */
961 #define BRANCH_COST 3
964 /* A fixed register used at prologue and epilogue generation to fix
965 addressing modes. The SPE needs heavy addressing fixes at the last
966 minute, and it's best to save a register for it.
968 AltiVec also needs fixes, but we've gotten around using r11, which
969 is actually wrong because when use_backchain_to_restore_sp is true,
970 we end up clobbering r11.
972 The AltiVec case needs to be fixed. Dunno if we should break ABI
973 compatibility and reserve a register for it as well.. */
975 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
977 /* Define this macro to change register usage conditional on target flags.
978 Set MQ register fixed (already call_used) if not POWER architecture
979 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
980 64-bit AIX reserves GPR13 for thread-private data.
981 Conditionally disable FPRs. */
983 #define CONDITIONAL_REGISTER_USAGE \
986 if (! TARGET_POWER) \
987 fixed_regs[64] = 1; \
989 fixed_regs[13] = call_used_regs[13] \
990 = call_really_used_regs[13] = 1; \
991 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
992 for (i = 32; i < 64; i++) \
993 fixed_regs[i] = call_used_regs[i] \
994 = call_really_used_regs[i] = 1; \
995 if (DEFAULT_ABI == ABI_V4 \
996 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
998 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
999 if (DEFAULT_ABI == ABI_V4 \
1000 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1002 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1003 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1004 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1005 if (DEFAULT_ABI == ABI_DARWIN \
1006 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1007 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1008 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1009 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1010 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1011 if (TARGET_ALTIVEC) \
1012 global_regs[VSCR_REGNO] = 1; \
1015 global_regs[SPEFSCR_REGNO] = 1; \
1016 fixed_regs[FIXED_SCRATCH] \
1017 = call_used_regs[FIXED_SCRATCH] \
1018 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1020 if (! TARGET_ALTIVEC) \
1022 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1023 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1024 call_really_used_regs[VRSAVE_REGNO] = 1; \
1026 if (TARGET_ALTIVEC_ABI) \
1027 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1028 call_used_regs[i] = call_really_used_regs[i] = 1; \
1031 /* Specify the registers used for certain standard purposes.
1032 The values of these macros are register numbers. */
1034 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1035 /* #define PC_REGNUM */
1037 /* Register to use for pushing function arguments. */
1038 #define STACK_POINTER_REGNUM 1
1040 /* Base register for access to local variables of the function. */
1041 #define FRAME_POINTER_REGNUM 31
1043 /* Value should be nonzero if functions must have frame pointers.
1044 Zero means the frame pointer need not be set up (and parms
1045 may be accessed via the stack pointer) in functions that seem suitable.
1046 This is computed in `reload', in reload1.c. */
1047 #define FRAME_POINTER_REQUIRED 0
1049 /* Base register for access to arguments of the function. */
1050 #define ARG_POINTER_REGNUM 67
1052 /* Place to put static chain when calling a function that requires it. */
1053 #define STATIC_CHAIN_REGNUM 11
1055 /* Link register number. */
1056 #define LINK_REGISTER_REGNUM 65
1058 /* Count register number. */
1059 #define COUNT_REGISTER_REGNUM 66
1061 /* Place that structure value return address is placed.
1063 On the RS/6000, it is passed as an extra parameter. */
1064 #define STRUCT_VALUE 0
1066 /* Define the classes of registers for register constraints in the
1067 machine description. Also define ranges of constants.
1069 One of the classes must always be named ALL_REGS and include all hard regs.
1070 If there is more than one class, another class must be named NO_REGS
1071 and contain no registers.
1073 The name GENERAL_REGS must be the name of a class (or an alias for
1074 another name such as ALL_REGS). This is the class of registers
1075 that is allowed by "g" or "r" in a register constraint.
1076 Also, registers outside this class are allocated only when
1077 instructions express preferences for them.
1079 The classes must be numbered in nondecreasing order; that is,
1080 a larger-numbered class must never be contained completely
1081 in a smaller-numbered class.
1083 For any two classes, it is very desirable that there be another
1084 class that represents their union. */
1086 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1087 and condition registers, plus three special registers, MQ, CTR, and the
1088 link register. AltiVec adds a vector register class.
1090 However, r0 is special in that it cannot be used as a base register.
1091 So make a class for registers valid as base registers.
1093 Also, cr0 is the only condition code register that can be used in
1094 arithmetic insns, so make a separate class for it. */
1122 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1124 /* Give names of register classes as strings for dump file. */
1126 #define REG_CLASS_NAMES \
1137 "NON_SPECIAL_REGS", \
1141 "LINK_OR_CTR_REGS", \
1143 "SPEC_OR_GEN_REGS", \
1151 /* Define which registers fit in which classes.
1152 This is an initializer for a vector of HARD_REG_SET
1153 of length N_REG_CLASSES. */
1155 #define REG_CLASS_CONTENTS \
1157 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1158 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1159 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1160 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1161 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1162 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1164 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1166 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1167 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1168 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1169 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1170 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1171 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1172 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1173 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1174 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1175 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1176 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1177 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1180 /* The same information, inverted:
1181 Return the class number of the smallest class containing
1182 reg number REGNO. This could be a conditional expression
1183 or could index an array. */
1185 #define REGNO_REG_CLASS(REGNO) \
1186 ((REGNO) == 0 ? GENERAL_REGS \
1187 : (REGNO) < 32 ? BASE_REGS \
1188 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1189 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1190 : (REGNO) == CR0_REGNO ? CR0_REGS \
1191 : CR_REGNO_P (REGNO) ? CR_REGS \
1192 : (REGNO) == MQ_REGNO ? MQ_REGS \
1193 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1194 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1195 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1196 : (REGNO) == XER_REGNO ? XER_REGS \
1197 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1198 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1199 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1200 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1203 /* The class value for index registers, and the one for base regs. */
1204 #define INDEX_REG_CLASS GENERAL_REGS
1205 #define BASE_REG_CLASS BASE_REGS
1207 /* Get reg_class from a letter such as appears in the machine description. */
1209 #define REG_CLASS_FROM_LETTER(C) \
1210 ((C) == 'f' ? FLOAT_REGS \
1211 : (C) == 'b' ? BASE_REGS \
1212 : (C) == 'h' ? SPECIAL_REGS \
1213 : (C) == 'q' ? MQ_REGS \
1214 : (C) == 'c' ? CTR_REGS \
1215 : (C) == 'l' ? LINK_REGS \
1216 : (C) == 'v' ? ALTIVEC_REGS \
1217 : (C) == 'x' ? CR0_REGS \
1218 : (C) == 'y' ? CR_REGS \
1219 : (C) == 'z' ? XER_REGS \
1222 /* The letters I, J, K, L, M, N, and P in a register constraint string
1223 can be used to stand for particular ranges of immediate operands.
1224 This macro defines what the ranges are.
1225 C is the letter, and VALUE is a constant value.
1226 Return 1 if VALUE is in the range specified by C.
1228 `I' is a signed 16-bit constant
1229 `J' is a constant with only the high-order 16 bits nonzero
1230 `K' is a constant with only the low-order 16 bits nonzero
1231 `L' is a signed 16-bit constant shifted left 16 bits
1232 `M' is a constant that is greater than 31
1233 `N' is a positive constant that is an exact power of two
1234 `O' is the constant zero
1235 `P' is a constant whose negation is a signed 16-bit constant */
1237 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1238 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1239 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1240 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1241 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1242 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1243 : (C) == 'M' ? (VALUE) > 31 \
1244 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1245 : (C) == 'O' ? (VALUE) == 0 \
1246 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1249 /* Similar, but for floating constants, and defining letters G and H.
1250 Here VALUE is the CONST_DOUBLE rtx itself.
1252 We flag for special constants when we can copy the constant into
1253 a general register in two insns for DF/DI and one insn for SF.
1255 'H' is used for DI/DF constants that take 3 insns. */
1257 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1258 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1259 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1260 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1263 /* Optional extra constraints for this machine.
1265 'Q' means that is a memory operand that is just an offset from a reg.
1266 'R' is for AIX TOC entries.
1267 'S' is a constant that can be placed into a 64-bit mask operand
1268 'T' is a constant that can be placed into a 32-bit mask operand
1269 'U' is for V.4 small data references.
1270 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1272 #define EXTRA_CONSTRAINT(OP, C) \
1273 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1274 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1275 : (C) == 'S' ? mask64_operand (OP, DImode) \
1276 : (C) == 'T' ? mask_operand (OP, SImode) \
1277 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1278 && small_data_operand (OP, GET_MODE (OP))) \
1279 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1280 && (fixed_regs[CR0_REGNO] \
1281 || !logical_operand (OP, DImode)) \
1282 && !mask64_operand (OP, DImode)) \
1285 /* Given an rtx X being reloaded into a reg required to be
1286 in class CLASS, return the class of reg to actually use.
1287 In general this is just CLASS; but on some machines
1288 in some cases it is preferable to use a more restrictive class.
1290 On the RS/6000, we have to return NO_REGS when we want to reload a
1291 floating-point CONST_DOUBLE to force it to be copied to memory.
1293 We also don't want to reload integer values into floating-point
1294 registers if we can at all help it. In fact, this can
1295 cause reload to abort, if it tries to generate a reload of CTR
1296 into a FP register and discovers it doesn't have the memory location
1299 ??? Would it be a good idea to have reload do the converse, that is
1300 try to reload floating modes into FP registers if possible?
1303 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1304 (((GET_CODE (X) == CONST_DOUBLE \
1305 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1307 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1308 && (CLASS) == NON_SPECIAL_REGS) \
1312 /* Return the register class of a scratch register needed to copy IN into
1313 or out of a register in CLASS in MODE. If it can be done directly,
1314 NO_REGS is returned. */
1316 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1317 secondary_reload_class (CLASS, MODE, IN)
1319 /* If we are copying between FP or AltiVec registers and anything
1320 else, we need a memory location. */
1322 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1323 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1324 || (CLASS2) == FLOAT_REGS \
1325 || (CLASS1) == ALTIVEC_REGS \
1326 || (CLASS2) == ALTIVEC_REGS))
1328 /* Return the maximum number of consecutive registers
1329 needed to represent mode MODE in a register of class CLASS.
1331 On RS/6000, this is the size of MODE in words,
1332 except in the FP regs, where a single reg is enough for two words. */
1333 #define CLASS_MAX_NREGS(CLASS, MODE) \
1334 (((CLASS) == FLOAT_REGS) \
1335 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1336 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1339 /* Return a class of registers that cannot change FROM mode to TO mode. */
1341 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1342 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1343 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1344 : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \
1345 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1348 /* Stack layout; function entry, exit and calling. */
1350 /* Enumeration to give which calling sequence to use. */
1353 ABI_AIX, /* IBM's AIX */
1354 ABI_AIX_NODESC, /* AIX calling sequence minus
1355 function descriptors */
1356 ABI_V4, /* System V.4/eabi */
1357 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1360 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1362 /* Structure used to define the rs6000 stack */
1363 typedef struct rs6000_stack {
1364 int first_gp_reg_save; /* first callee saved GP register used */
1365 int first_fp_reg_save; /* first callee saved FP register used */
1366 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1367 int lr_save_p; /* true if the link reg needs to be saved */
1368 int cr_save_p; /* true if the CR reg needs to be saved */
1369 unsigned int vrsave_mask; /* mask of vec registers to save */
1370 int toc_save_p; /* true if the TOC needs to be saved */
1371 int push_p; /* true if we need to allocate stack space */
1372 int calls_p; /* true if the function makes any calls */
1373 enum rs6000_abi abi; /* which ABI to use */
1374 int gp_save_offset; /* offset to save GP regs from initial SP */
1375 int fp_save_offset; /* offset to save FP regs from initial SP */
1376 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
1377 int lr_save_offset; /* offset to save LR from initial SP */
1378 int cr_save_offset; /* offset to save CR from initial SP */
1379 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1380 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
1381 int toc_save_offset; /* offset to save the TOC pointer */
1382 int varargs_save_offset; /* offset to save the varargs registers */
1383 int ehrd_offset; /* offset to EH return data */
1384 int reg_size; /* register size (4 or 8) */
1385 int varargs_size; /* size to hold V.4 args passed in regs */
1386 int vars_size; /* variable save area size */
1387 int parm_size; /* outgoing parameter size */
1388 int save_size; /* save area size */
1389 int fixed_size; /* fixed size of stack frame */
1390 int gp_size; /* size of saved GP registers */
1391 int fp_size; /* size of saved FP registers */
1392 int altivec_size; /* size of saved AltiVec registers */
1393 int cr_size; /* size to hold CR if not in save_size */
1394 int lr_size; /* size to hold LR if not in save_size */
1395 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1396 int altivec_padding_size; /* size of altivec alignment padding if
1398 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
1399 int spe_padding_size;
1400 int toc_size; /* size to hold TOC if not in save_size */
1401 int total_size; /* total bytes allocated for stack */
1402 int spe_64bit_regs_used;
1405 /* Define this if pushing a word on the stack
1406 makes the stack pointer a smaller address. */
1407 #define STACK_GROWS_DOWNWARD
1409 /* Define this if the nominal address of the stack frame
1410 is at the high-address end of the local variables;
1411 that is, each additional local variable allocated
1412 goes at a more negative offset in the frame.
1414 On the RS/6000, we grow upwards, from the area after the outgoing
1416 /* #define FRAME_GROWS_DOWNWARD */
1418 /* Size of the outgoing register save area */
1419 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1420 || DEFAULT_ABI == ABI_AIX_NODESC \
1421 || DEFAULT_ABI == ABI_DARWIN) \
1422 ? (TARGET_64BIT ? 64 : 32) \
1425 /* Size of the fixed area on the stack */
1426 #define RS6000_SAVE_AREA \
1427 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1428 << (TARGET_64BIT ? 1 : 0))
1430 /* MEM representing address to save the TOC register */
1431 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1432 plus_constant (stack_pointer_rtx, \
1433 (TARGET_32BIT ? 20 : 40)))
1435 /* Size of the V.4 varargs area if needed */
1436 #define RS6000_VARARGS_AREA 0
1438 /* Align an address */
1439 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1441 /* Size of V.4 varargs area in bytes */
1442 #define RS6000_VARARGS_SIZE \
1443 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1445 /* Offset within stack frame to start allocating local variables at.
1446 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1447 first local allocated. Otherwise, it is the offset to the BEGINNING
1448 of the first local allocated.
1450 On the RS/6000, the frame pointer is the same as the stack pointer,
1451 except for dynamic allocations. So we start after the fixed area and
1452 outgoing parameter area. */
1454 #define STARTING_FRAME_OFFSET \
1455 (RS6000_ALIGN (current_function_outgoing_args_size, \
1456 TARGET_ALTIVEC ? 16 : 8) \
1457 + RS6000_VARARGS_AREA \
1460 /* Offset from the stack pointer register to an item dynamically
1461 allocated on the stack, e.g., by `alloca'.
1463 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1464 length of the outgoing arguments. The default is correct for most
1465 machines. See `function.c' for details. */
1466 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1467 (RS6000_ALIGN (current_function_outgoing_args_size, \
1468 TARGET_ALTIVEC ? 16 : 8) \
1469 + (STACK_POINTER_OFFSET))
1471 /* If we generate an insn to push BYTES bytes,
1472 this says how many the stack pointer really advances by.
1473 On RS/6000, don't define this because there are no push insns. */
1474 /* #define PUSH_ROUNDING(BYTES) */
1476 /* Offset of first parameter from the argument pointer register value.
1477 On the RS/6000, we define the argument pointer to the start of the fixed
1479 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1481 /* Offset from the argument pointer register value to the top of
1482 stack. This is different from FIRST_PARM_OFFSET because of the
1483 register save area. */
1484 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1486 /* Define this if stack space is still allocated for a parameter passed
1487 in a register. The value is the number of bytes allocated to this
1489 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1491 /* Define this if the above stack space is to be considered part of the
1492 space allocated by the caller. */
1493 #define OUTGOING_REG_PARM_STACK_SPACE
1495 /* This is the difference between the logical top of stack and the actual sp.
1497 For the RS/6000, sp points past the fixed area. */
1498 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1500 /* Define this if the maximum size of all the outgoing args is to be
1501 accumulated and pushed during the prologue. The amount can be
1502 found in the variable current_function_outgoing_args_size. */
1503 #define ACCUMULATE_OUTGOING_ARGS 1
1505 /* Value is the number of bytes of arguments automatically
1506 popped when returning from a subroutine call.
1507 FUNDECL is the declaration node of the function (as a tree),
1508 FUNTYPE is the data type of the function (as a tree),
1509 or for a library call it is an identifier node for the subroutine name.
1510 SIZE is the number of bytes of arguments passed on the stack. */
1512 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1514 /* Define how to find the value returned by a function.
1515 VALTYPE is the data type of the value (as a tree).
1516 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1517 otherwise, FUNC is 0.
1519 On the SPE, both FPs and vectors are returned in r3.
1521 On RS/6000 an integer value is in r3 and a floating-point value is in
1522 fp1, unless -msoft-float. */
1524 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1525 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1526 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1527 || POINTER_TYPE_P (VALTYPE) \
1528 ? word_mode : TYPE_MODE (VALTYPE), \
1529 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1530 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1531 : TREE_CODE (VALTYPE) == REAL_TYPE \
1532 && TARGET_SPE_ABI && !TARGET_FPRS \
1534 : TREE_CODE (VALTYPE) == REAL_TYPE \
1535 && TARGET_HARD_FLOAT && TARGET_FPRS \
1536 ? FP_ARG_RETURN : GP_ARG_RETURN)
1538 /* Define how to find the value returned by a library function
1539 assuming the value has mode MODE. */
1541 #define LIBCALL_VALUE(MODE) \
1542 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1543 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1544 && TARGET_HARD_FLOAT && TARGET_FPRS \
1545 ? FP_ARG_RETURN : GP_ARG_RETURN)
1547 /* The AIX ABI for the RS/6000 specifies that all structures are
1548 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1549 specifies that structures <= 8 bytes are returned in r3/r4, but a
1550 draft put them in memory, and GCC used to implement the draft
1551 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1552 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1553 compatibility can change DRAFT_V4_STRUCT_RET to override the
1554 default, and -m switches get the final word. See
1555 rs6000_override_options for more details.
1557 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
1558 long double support is enabled. These values are returned in memory.
1560 int_size_in_bytes returns -1 for variable size objects, which go in
1561 memory always. The cast to unsigned makes -1 > 8. */
1563 #define RETURN_IN_MEMORY(TYPE) \
1564 ((AGGREGATE_TYPE_P (TYPE) \
1565 && (TARGET_AIX_STRUCT_RET \
1566 || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \
1567 || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode))
1569 /* DRAFT_V4_STRUCT_RET defaults off. */
1570 #define DRAFT_V4_STRUCT_RET 0
1572 /* Let RETURN_IN_MEMORY control what happens. */
1573 #define DEFAULT_PCC_STRUCT_RETURN 0
1575 /* Mode of stack savearea.
1576 FUNCTION is VOIDmode because calling convention maintains SP.
1577 BLOCK needs Pmode for SP.
1578 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1579 #define STACK_SAVEAREA_MODE(LEVEL) \
1580 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1581 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1583 /* Minimum and maximum general purpose registers used to hold arguments. */
1584 #define GP_ARG_MIN_REG 3
1585 #define GP_ARG_MAX_REG 10
1586 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1588 /* Minimum and maximum floating point registers used to hold arguments. */
1589 #define FP_ARG_MIN_REG 33
1590 #define FP_ARG_AIX_MAX_REG 45
1591 #define FP_ARG_V4_MAX_REG 40
1592 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1593 || DEFAULT_ABI == ABI_AIX_NODESC \
1594 || DEFAULT_ABI == ABI_DARWIN) \
1595 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1596 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1598 /* Minimum and maximum AltiVec registers used to hold arguments. */
1599 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1600 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1601 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1603 /* Return registers */
1604 #define GP_ARG_RETURN GP_ARG_MIN_REG
1605 #define FP_ARG_RETURN FP_ARG_MIN_REG
1606 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1608 /* Flags for the call/call_value rtl operations set up by function_arg */
1609 #define CALL_NORMAL 0x00000000 /* no special processing */
1610 /* Bits in 0x00000001 are unused. */
1611 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1612 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1613 #define CALL_LONG 0x00000008 /* always call indirect */
1615 /* 1 if N is a possible register number for a function value
1616 as seen by the caller.
1618 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1619 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1620 || ((N) == FP_ARG_RETURN) \
1621 || (TARGET_ALTIVEC && \
1622 (N) == ALTIVEC_ARG_RETURN))
1624 /* 1 if N is a possible register number for function argument passing.
1625 On RS/6000, these are r3-r10 and fp1-fp13.
1626 On AltiVec, v2 - v13 are used for passing vectors. */
1627 #define FUNCTION_ARG_REGNO_P(N) \
1628 (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1629 || (TARGET_ALTIVEC && \
1630 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1631 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1634 /* A C structure for machine-specific, per-function data.
1635 This is added to the cfun structure. */
1636 typedef struct machine_function GTY(())
1638 /* Whether a System V.4 varargs area was created. */
1640 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1641 int ra_needs_full_frame;
1644 /* Define a data type for recording info about an argument list
1645 during the scan of that argument list. This data type should
1646 hold all necessary information about the function itself
1647 and about the args processed so far, enough to enable macros
1648 such as FUNCTION_ARG to determine where the next arg should go.
1650 On the RS/6000, this is a structure. The first element is the number of
1651 total argument words, the second is used to store the next
1652 floating-point register number, and the third says how many more args we
1653 have prototype types for.
1655 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1656 the next available GP register, `fregno' is the next available FP
1657 register, and `words' is the number of words used on the stack.
1659 The varargs/stdarg support requires that this structure's size
1660 be a multiple of sizeof(int). */
1662 typedef struct rs6000_args
1664 int words; /* # words used for passing GP registers */
1665 int fregno; /* next available FP register */
1666 int vregno; /* next available AltiVec register */
1667 int nargs_prototype; /* # args left in the current prototype */
1668 int orig_nargs; /* Original value of nargs_prototype */
1669 int prototype; /* Whether a prototype was defined */
1670 int call_cookie; /* Do special things for this call */
1671 int sysv_gregno; /* next available GP register */
1674 /* Define intermediate macro to compute the size (in registers) of an argument
1677 #define RS6000_ARG_SIZE(MODE, TYPE) \
1678 ((MODE) != BLKmode \
1679 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1680 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1682 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1683 for a call to a function whose data type is FNTYPE.
1684 For a library call, FNTYPE is 0. */
1686 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1687 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1689 /* Similar, but when scanning the definition of a procedure. We always
1690 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1692 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1693 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1695 /* Update the data in CUM to advance over an argument
1696 of mode MODE and data type TYPE.
1697 (TYPE is null for libcalls where that information may not be available.) */
1699 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1700 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1702 /* Nonzero if we can use a floating-point register to pass this arg. */
1703 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1704 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1705 && (CUM).fregno <= FP_ARG_MAX_REG \
1706 && TARGET_HARD_FLOAT && TARGET_FPRS)
1708 /* Nonzero if we can use an AltiVec register to pass this arg. */
1709 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1710 (ALTIVEC_VECTOR_MODE (MODE) \
1711 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1712 && TARGET_ALTIVEC_ABI)
1714 /* Determine where to put an argument to a function.
1715 Value is zero to push the argument on the stack,
1716 or a hard register in which to store the argument.
1718 MODE is the argument's machine mode.
1719 TYPE is the data type of the argument (as a tree).
1720 This is null for libcalls where that information may
1722 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1723 the preceding args and about the function being called.
1724 NAMED is nonzero if this argument is a named parameter
1725 (otherwise it is an extra parameter matching an ellipsis).
1727 On RS/6000 the first eight words of non-FP are normally in registers
1728 and the rest are pushed. The first 13 FP args are in registers.
1730 If this is floating-point and no prototype is specified, we use
1731 both an FP and integer register (or possibly FP reg and stack). Library
1732 functions (when TYPE is zero) always have the proper types for args,
1733 so we can pass the FP value just in one register. emit_library_function
1734 doesn't support EXPR_LIST anyway. */
1736 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1737 function_arg (&CUM, MODE, TYPE, NAMED)
1739 /* For an arg passed partly in registers and partly in memory,
1740 this is the number of registers used.
1741 For args passed entirely in registers or entirely in memory, zero. */
1743 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1744 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1746 /* A C expression that indicates when an argument must be passed by
1747 reference. If nonzero for an argument, a copy of that argument is
1748 made in memory and a pointer to the argument is passed instead of
1749 the argument itself. The pointer is passed in whatever way is
1750 appropriate for passing a pointer to that type. */
1752 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1753 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1755 /* If defined, a C expression which determines whether, and in which
1756 direction, to pad out an argument with extra space. The value
1757 should be of type `enum direction': either `upward' to pad above
1758 the argument, `downward' to pad below, or `none' to inhibit
1761 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1763 /* If defined, a C expression that gives the alignment boundary, in bits,
1764 of an argument with the specified mode and type. If it is not defined,
1765 PARM_BOUNDARY is used for all arguments. */
1767 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1768 function_arg_boundary (MODE, TYPE)
1770 /* Perform any needed actions needed for a function that is receiving a
1771 variable number of arguments.
1775 MODE and TYPE are the mode and type of the current parameter.
1777 PRETEND_SIZE is a variable that should be set to the amount of stack
1778 that must be pushed by the prolog to pretend that our caller pushed
1781 Normally, this macro will push all remaining incoming registers on the
1782 stack and set PRETEND_SIZE to the length of the registers pushed. */
1784 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1785 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1787 /* Define the `__builtin_va_list' type for the ABI. */
1788 #define BUILD_VA_LIST_TYPE(VALIST) \
1789 (VALIST) = rs6000_build_va_list ()
1791 /* Implement `va_start' for varargs and stdarg. */
1792 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1793 rs6000_va_start (valist, nextarg)
1795 /* Implement `va_arg'. */
1796 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1797 rs6000_va_arg (valist, type)
1799 /* For AIX, the rule is that structures are passed left-aligned in
1800 their stack slot. However, GCC does not presently do this:
1801 structures which are the same size as integer types are passed
1802 right-aligned, as if they were in fact integers. This only
1803 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1804 ABI_V4 does not use std_expand_builtin_va_arg. */
1805 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1807 /* Define this macro to be a nonzero value if the location where a function
1808 argument is passed depends on whether or not it is a named argument. */
1809 #define STRICT_ARGUMENT_NAMING 1
1811 /* Output assembler code to FILE to increment profiler label # LABELNO
1812 for profiling a function entry. */
1814 #define FUNCTION_PROFILER(FILE, LABELNO) \
1815 output_function_profiler ((FILE), (LABELNO));
1817 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1818 the stack pointer does not matter. No definition is equivalent to
1821 On the RS/6000, this is nonzero because we can restore the stack from
1822 its backpointer, which we maintain. */
1823 #define EXIT_IGNORE_STACK 1
1825 /* Define this macro as a C expression that is nonzero for registers
1826 that are used by the epilogue or the return' pattern. The stack
1827 and frame pointer registers are already be assumed to be used as
1830 #define EPILOGUE_USES(REGNO) \
1831 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1832 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1833 || (current_function_calls_eh_return \
1835 && (REGNO) == TOC_REGISTER))
1838 /* TRAMPOLINE_TEMPLATE deleted */
1840 /* Length in units of the trampoline for entering a nested function. */
1842 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1844 /* Emit RTL insns to initialize the variable parts of a trampoline.
1845 FNADDR is an RTX for the address of the function's pure code.
1846 CXT is an RTX for the static chain value for the function. */
1848 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1849 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1851 /* Definitions for __builtin_return_address and __builtin_frame_address.
1852 __builtin_return_address (0) should give link register (65), enable
1854 /* This should be uncommented, so that the link register is used, but
1855 currently this would result in unmatched insns and spilling fixed
1856 registers so we'll leave it for another day. When these problems are
1857 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1859 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1861 /* Number of bytes into the frame return addresses can be found. See
1862 rs6000_stack_info in rs6000.c for more information on how the different
1863 abi's store the return address. */
1864 #define RETURN_ADDRESS_OFFSET \
1865 ((DEFAULT_ABI == ABI_AIX \
1866 || DEFAULT_ABI == ABI_DARWIN \
1867 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1868 (DEFAULT_ABI == ABI_V4) ? 4 : \
1869 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1871 /* The current return address is in link register (65). The return address
1872 of anything farther back is accessed normally at an offset of 8 from the
1874 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1875 (rs6000_return_addr (COUNT, FRAME))
1878 /* Definitions for register eliminations.
1880 We have two registers that can be eliminated on the RS/6000. First, the
1881 frame pointer register can often be eliminated in favor of the stack
1882 pointer register. Secondly, the argument pointer register can always be
1883 eliminated; it is replaced with either the stack or frame pointer.
1885 In addition, we use the elimination mechanism to see if r30 is needed
1886 Initially we assume that it isn't. If it is, we spill it. This is done
1887 by making it an eliminable register. We replace it with itself so that
1888 if it isn't needed, then existing uses won't be modified. */
1890 /* This is an array of structures. Each structure initializes one pair
1891 of eliminable registers. The "from" register number is given first,
1892 followed by "to". Eliminations of the same "from" register are listed
1893 in order of preference. */
1894 #define ELIMINABLE_REGS \
1895 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1896 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1897 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1898 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1900 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1901 Frame pointer elimination is automatically handled.
1903 For the RS/6000, if frame pointer elimination is being done, we would like
1904 to convert ap into fp, not sp.
1906 We need r30 if -mminimal-toc was specified, and there are constant pool
1909 #define CAN_ELIMINATE(FROM, TO) \
1910 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1911 ? ! frame_pointer_needed \
1912 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1913 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1916 /* Define the offset between two registers, one to be eliminated, and the other
1917 its replacement, at the start of a routine. */
1918 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1920 rs6000_stack_t *info = rs6000_stack_info (); \
1922 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1923 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1924 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1925 (OFFSET) = info->total_size; \
1926 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1927 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1928 else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \
1934 /* Addressing modes, and classification of registers for them. */
1936 #define HAVE_PRE_DECREMENT 1
1937 #define HAVE_PRE_INCREMENT 1
1939 /* Macros to check register numbers against specific register classes. */
1941 /* These assume that REGNO is a hard or pseudo reg number.
1942 They give nonzero only if REGNO is a hard reg of the suitable class
1943 or a pseudo reg currently allocated to a suitable hard reg.
1944 Since they use reg_renumber, they are safe only once reg_renumber
1945 has been allocated, which happens in local-alloc.c. */
1947 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1948 ((REGNO) < FIRST_PSEUDO_REGISTER \
1949 ? (REGNO) <= 31 || (REGNO) == 67 \
1950 : (reg_renumber[REGNO] >= 0 \
1951 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1953 #define REGNO_OK_FOR_BASE_P(REGNO) \
1954 ((REGNO) < FIRST_PSEUDO_REGISTER \
1955 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1956 : (reg_renumber[REGNO] > 0 \
1957 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1959 /* Maximum number of registers that can appear in a valid memory address. */
1961 #define MAX_REGS_PER_ADDRESS 2
1963 /* Recognize any constant value that is a valid address. */
1965 #define CONSTANT_ADDRESS_P(X) \
1966 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1967 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1968 || GET_CODE (X) == HIGH)
1970 /* Nonzero if the constant value X is a legitimate general operand.
1971 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1973 On the RS/6000, all integer constants are acceptable, most won't be valid
1974 for particular insns, though. Only easy FP constants are
1977 #define LEGITIMATE_CONSTANT_P(X) \
1978 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1979 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1980 || easy_fp_constant (X, GET_MODE (X)))
1982 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1983 and check its validity for a certain class.
1984 We have two alternate definitions for each of them.
1985 The usual definition accepts all pseudo regs; the other rejects
1986 them unless they have been allocated suitable hard regs.
1987 The symbol REG_OK_STRICT causes the latter definition to be used.
1989 Most source files want to accept pseudo regs in the hope that
1990 they will get allocated to the class that the insn wants them to be in.
1991 Source files for reload pass need to be strict.
1992 After reload, it makes no difference, since pseudo regs have
1993 been eliminated by then. */
1995 #ifdef REG_OK_STRICT
1996 # define REG_OK_STRICT_FLAG 1
1998 # define REG_OK_STRICT_FLAG 0
2001 /* Nonzero if X is a hard reg that can be used as an index
2002 or if it is a pseudo reg in the non-strict case. */
2003 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2005 && (REGNO (X) <= 31 \
2006 || REGNO (X) == ARG_POINTER_REGNUM \
2007 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2008 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2010 /* Nonzero if X is a hard reg that can be used as a base reg
2011 or if it is a pseudo reg in the non-strict case. */
2012 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2013 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2015 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2016 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2018 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2019 that is a valid memory address for an instruction.
2020 The MODE argument is the machine mode for the MEM expression
2021 that wants to use this address.
2023 On the RS/6000, there are four valid address: a SYMBOL_REF that
2024 refers to a constant pool entry of an address (or the sum of it
2025 plus a constant), a short (16-bit signed) constant plus a register,
2026 the sum of two registers, or a register indirect, possibly with an
2027 auto-increment. For DFmode and DImode with a constant plus register,
2028 we must ensure that both words are addressable or PowerPC64 with offset
2031 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2032 32-bit DImode, TImode), indexed addressing cannot be used because
2033 adjacent memory cells are accessed by adding word-sized offsets
2034 during assembly output. */
2036 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
2038 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
2040 /* SPE offset addressing is limited to 5-bits worth of double words. */
2041 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2043 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
2045 && GET_CODE (X) == PLUS \
2046 && GET_CODE (XEXP (X, 0)) == REG \
2047 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
2048 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
2050 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
2051 (DEFAULT_ABI == ABI_V4 \
2052 && !flag_pic && !TARGET_TOC \
2053 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
2054 && small_data_operand (X, MODE))
2056 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
2057 (GET_CODE (X) == CONST_INT \
2058 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
2060 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
2061 (GET_CODE (X) == PLUS \
2062 && GET_CODE (XEXP (X, 0)) == REG \
2063 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2064 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
2065 && (! ALTIVEC_VECTOR_MODE (MODE) \
2066 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
2067 && (! SPE_VECTOR_MODE (MODE) \
2068 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
2069 && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \
2070 && (((MODE) != DFmode && (MODE) != DImode) \
2072 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
2073 : ! (INTVAL (XEXP (X, 1)) & 3))) \
2074 && (((MODE) != TFmode && (MODE) != TImode) \
2076 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
2077 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2078 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2080 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2081 (GET_CODE (X) == PLUS \
2082 && GET_CODE (XEXP (X, 0)) == REG \
2083 && GET_CODE (XEXP (X, 1)) == REG \
2084 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2085 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2086 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2087 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2089 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2090 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2092 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2094 && ! flag_pic && ! TARGET_TOC \
2095 && GET_MODE_NUNITS (MODE) == 1 \
2096 && (GET_MODE_BITSIZE (MODE) <= 32 \
2097 || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \
2098 && GET_CODE (X) == LO_SUM \
2099 && GET_CODE (XEXP (X, 0)) == REG \
2100 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2101 && CONSTANT_P (XEXP (X, 1)))
2103 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2104 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2108 /* Try machine-dependent ways of modifying an illegitimate address
2109 to be legitimate. If we find one, return the new, valid address.
2110 This macro is used in only one place: `memory_address' in explow.c.
2112 OLDX is the address as it was before break_out_memory_refs was called.
2113 In some cases it is useful to look at this to decide what needs to be done.
2115 MODE and WIN are passed so that this macro can use
2116 GO_IF_LEGITIMATE_ADDRESS.
2118 It is always safe for this macro to do nothing. It exists to recognize
2119 opportunities to optimize the output.
2121 On RS/6000, first check for the sum of a register with a constant
2122 integer that is out of range. If so, generate code to add the
2123 constant with the low-order 16 bits masked to the register and force
2124 this result into another register (this can be done with `cau').
2125 Then generate an address of REG+(CONST&0xffff), allowing for the
2126 possibility of bit 16 being a one.
2128 Then check for the sum of a register and something not constant, try to
2129 load the other things into a register and return the sum. */
2131 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2132 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2133 if (result != NULL_RTX) \
2140 /* Try a machine-dependent way of reloading an illegitimate address
2141 operand. If we find one, push the reload and jump to WIN. This
2142 macro is used in only one place: `find_reloads_address' in reload.c.
2144 Implemented on rs6000 by rs6000_legitimize_reload_address.
2145 Note that (X) is evaluated twice; this is safe in current usage. */
2147 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2150 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2151 (int)(TYPE), (IND_LEVELS), &win); \
2156 /* Go to LABEL if ADDR (a legitimate address expression)
2157 has an effect that depends on the machine mode it is used for.
2159 On the RS/6000 this is true if the address is valid with a zero offset
2160 but not with an offset of four (this means it cannot be used as an
2161 address for DImode or DFmode) or is a pre-increment or decrement. Since
2162 we know it is valid, we just check for an address that is not valid with
2163 an offset of four. */
2165 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2166 { if (GET_CODE (ADDR) == PLUS \
2167 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2168 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2169 (TARGET_32BIT ? 4 : 8))) \
2171 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2173 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2175 if (GET_CODE (ADDR) == LO_SUM) \
2179 /* The register number of the register used to address a table of
2180 static data addresses in memory. In some cases this register is
2181 defined by a processor's "application binary interface" (ABI).
2182 When this macro is defined, RTL is generated for this register
2183 once, as with the stack pointer and frame pointer registers. If
2184 this macro is not defined, it is up to the machine-dependent files
2185 to allocate such a register (if necessary). */
2187 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2188 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2190 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2192 /* Define this macro if the register defined by
2193 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2194 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2196 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2198 /* By generating position-independent code, when two different
2199 programs (A and B) share a common library (libC.a), the text of
2200 the library can be shared whether or not the library is linked at
2201 the same address for both programs. In some of these
2202 environments, position-independent code requires not only the use
2203 of different addressing modes, but also special code to enable the
2204 use of these addressing modes.
2206 The `FINALIZE_PIC' macro serves as a hook to emit these special
2207 codes once the function is being compiled into assembly code, but
2208 not before. (It is not done before, because in the case of
2209 compiling an inline function, it would lead to multiple PIC
2210 prologues being included in functions which used inline functions
2211 and were compiled to assembly language.) */
2213 /* #define FINALIZE_PIC */
2215 /* A C expression that is nonzero if X is a legitimate immediate
2216 operand on the target machine when generating position independent
2217 code. You can assume that X satisfies `CONSTANT_P', so you need
2218 not check this. You can also assume FLAG_PIC is true, so you need
2219 not check it either. You need not define this macro if all
2220 constants (including `SYMBOL_REF') can be immediate operands when
2221 generating position independent code. */
2223 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2225 /* In rare cases, correct code generation requires extra machine
2226 dependent processing between the second jump optimization pass and
2227 delayed branch scheduling. On those machines, define this macro
2228 as a C statement to act on the code starting at INSN. */
2230 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2233 /* Define this if some processing needs to be done immediately before
2234 emitting code for an insn. */
2236 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2238 /* Specify the machine mode that this machine uses
2239 for the index in the tablejump instruction. */
2240 #define CASE_VECTOR_MODE SImode
2242 /* Define as C expression which evaluates to nonzero if the tablejump
2243 instruction expects the table to contain offsets from the address of the
2245 Do not define this if the table should contain absolute addresses. */
2246 #define CASE_VECTOR_PC_RELATIVE 1
2248 /* Define this as 1 if `char' should by default be signed; else as 0. */
2249 #define DEFAULT_SIGNED_CHAR 0
2251 /* This flag, if defined, says the same insns that convert to a signed fixnum
2252 also convert validly to an unsigned one. */
2254 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2256 /* Max number of bytes we can move from memory to memory
2257 in one reasonably fast instruction. */
2258 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2259 #define MAX_MOVE_MAX 8
2261 /* Nonzero if access to memory by bytes is no faster than for words.
2262 Also nonzero if doing byte operations (specifically shifts) in registers
2264 #define SLOW_BYTE_ACCESS 1
2266 /* Define if operations between registers always perform the operation
2267 on the full register even if a narrower mode is specified. */
2268 #define WORD_REGISTER_OPERATIONS
2270 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2271 will either zero-extend or sign-extend. The value of this macro should
2272 be the code that says which one of the two operations is implicitly
2273 done, NIL if none. */
2274 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2276 /* Define if loading short immediate values into registers sign extends. */
2277 #define SHORT_IMMEDIATES_SIGN_EXTEND
2279 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2280 is done just by pretending it is already truncated. */
2281 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2283 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2284 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2285 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2287 /* The CTZ patterns return -1 for input of zero. */
2288 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2290 /* Specify the machine mode that pointers have.
2291 After generation of rtl, the compiler makes no further distinction
2292 between pointers and any other objects of this machine mode. */
2293 #define Pmode (TARGET_32BIT ? SImode : DImode)
2295 /* Mode of a function address in a call instruction (for indexing purposes).
2296 Doesn't matter on RS/6000. */
2297 #define FUNCTION_MODE SImode
2299 /* Define this if addresses of constant functions
2300 shouldn't be put through pseudo regs where they can be cse'd.
2301 Desirable on machines where ordinary constants are expensive
2302 but a CALL with constant address is cheap. */
2303 #define NO_FUNCTION_CSE
2305 /* Define this to be nonzero if shift instructions ignore all but the low-order
2308 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2309 have been dropped from the PowerPC architecture. */
2311 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2313 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2314 should be adjusted to reflect any required changes. This macro is used when
2315 there is some systematic length adjustment required that would be difficult
2316 to express in the length attribute. */
2318 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2320 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2321 COMPARE, return the mode to be used for the comparison. For
2322 floating-point, CCFPmode should be used. CCUNSmode should be used
2323 for unsigned comparisons. CCEQmode should be used when we are
2324 doing an inequality comparison on the result of a
2325 comparison. CCmode should be used in all other cases. */
2327 #define SELECT_CC_MODE(OP,X,Y) \
2328 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2329 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2330 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2331 ? CCEQmode : CCmode))
2333 /* Define the information needed to generate branch and scc insns. This is
2334 stored from the compare operation. Note that we can't use "rtx" here
2335 since it hasn't been defined! */
2337 extern GTY(()) rtx rs6000_compare_op0;
2338 extern GTY(()) rtx rs6000_compare_op1;
2339 extern int rs6000_compare_fp_p;
2341 /* Control the assembler format that we output. */
2343 /* A C string constant describing how to begin a comment in the target
2344 assembler language. The compiler assumes that the comment will end at
2345 the end of the line. */
2346 #define ASM_COMMENT_START " #"
2348 /* Implicit library calls should use memcpy, not bcopy, etc. */
2350 #define TARGET_MEM_FUNCTIONS
2352 /* Flag to say the TOC is initialized */
2353 extern int toc_initialized;
2355 /* Macro to output a special constant pool entry. Go to WIN if we output
2356 it. Otherwise, it is written the usual way.
2358 On the RS/6000, toc entries are handled this way. */
2360 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2361 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2363 output_toc (FILE, X, LABELNO, MODE); \
2368 #ifdef HAVE_GAS_WEAK
2369 #define RS6000_WEAK 1
2371 #define RS6000_WEAK 0
2375 /* Used in lieu of ASM_WEAKEN_LABEL. */
2376 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2379 fputs ("\t.weak\t", (FILE)); \
2380 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2381 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2382 && DEFAULT_ABI == ABI_AIX) \
2385 fputs ("[DS]", (FILE)); \
2386 fputs ("\n\t.weak\t.", (FILE)); \
2387 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2389 fputc ('\n', (FILE)); \
2392 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2393 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2394 && DEFAULT_ABI == ABI_AIX) \
2396 fputs ("\t.set\t.", (FILE)); \
2397 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2398 fputs (",.", (FILE)); \
2399 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2400 fputc ('\n', (FILE)); \
2407 /* This implements the `alias' attribute. */
2408 #undef ASM_OUTPUT_DEF_FROM_DECLS
2409 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2412 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2413 const char *name = IDENTIFIER_POINTER (TARGET); \
2414 if (TREE_CODE (DECL) == FUNCTION_DECL \
2415 && DEFAULT_ABI == ABI_AIX) \
2417 if (TREE_PUBLIC (DECL)) \
2419 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2421 fputs ("\t.globl\t.", FILE); \
2422 RS6000_OUTPUT_BASENAME (FILE, alias); \
2423 putc ('\n', FILE); \
2426 else if (TARGET_XCOFF) \
2428 fputs ("\t.lglobl\t.", FILE); \
2429 RS6000_OUTPUT_BASENAME (FILE, alias); \
2430 putc ('\n', FILE); \
2432 fputs ("\t.set\t.", FILE); \
2433 RS6000_OUTPUT_BASENAME (FILE, alias); \
2434 fputs (",.", FILE); \
2435 RS6000_OUTPUT_BASENAME (FILE, name); \
2436 fputc ('\n', FILE); \
2438 ASM_OUTPUT_DEF (FILE, alias, name); \
2442 /* Output to assembler file text saying following lines
2443 may contain character constants, extra white space, comments, etc. */
2445 #define ASM_APP_ON ""
2447 /* Output to assembler file text saying following lines
2448 no longer contain unusual constructs. */
2450 #define ASM_APP_OFF ""
2452 /* How to refer to registers in assembler output.
2453 This sequence is indexed by compiler's hard-register-number (see above). */
2455 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2457 #define REGISTER_NAMES \
2459 &rs6000_reg_names[ 0][0], /* r0 */ \
2460 &rs6000_reg_names[ 1][0], /* r1 */ \
2461 &rs6000_reg_names[ 2][0], /* r2 */ \
2462 &rs6000_reg_names[ 3][0], /* r3 */ \
2463 &rs6000_reg_names[ 4][0], /* r4 */ \
2464 &rs6000_reg_names[ 5][0], /* r5 */ \
2465 &rs6000_reg_names[ 6][0], /* r6 */ \
2466 &rs6000_reg_names[ 7][0], /* r7 */ \
2467 &rs6000_reg_names[ 8][0], /* r8 */ \
2468 &rs6000_reg_names[ 9][0], /* r9 */ \
2469 &rs6000_reg_names[10][0], /* r10 */ \
2470 &rs6000_reg_names[11][0], /* r11 */ \
2471 &rs6000_reg_names[12][0], /* r12 */ \
2472 &rs6000_reg_names[13][0], /* r13 */ \
2473 &rs6000_reg_names[14][0], /* r14 */ \
2474 &rs6000_reg_names[15][0], /* r15 */ \
2475 &rs6000_reg_names[16][0], /* r16 */ \
2476 &rs6000_reg_names[17][0], /* r17 */ \
2477 &rs6000_reg_names[18][0], /* r18 */ \
2478 &rs6000_reg_names[19][0], /* r19 */ \
2479 &rs6000_reg_names[20][0], /* r20 */ \
2480 &rs6000_reg_names[21][0], /* r21 */ \
2481 &rs6000_reg_names[22][0], /* r22 */ \
2482 &rs6000_reg_names[23][0], /* r23 */ \
2483 &rs6000_reg_names[24][0], /* r24 */ \
2484 &rs6000_reg_names[25][0], /* r25 */ \
2485 &rs6000_reg_names[26][0], /* r26 */ \
2486 &rs6000_reg_names[27][0], /* r27 */ \
2487 &rs6000_reg_names[28][0], /* r28 */ \
2488 &rs6000_reg_names[29][0], /* r29 */ \
2489 &rs6000_reg_names[30][0], /* r30 */ \
2490 &rs6000_reg_names[31][0], /* r31 */ \
2492 &rs6000_reg_names[32][0], /* fr0 */ \
2493 &rs6000_reg_names[33][0], /* fr1 */ \
2494 &rs6000_reg_names[34][0], /* fr2 */ \
2495 &rs6000_reg_names[35][0], /* fr3 */ \
2496 &rs6000_reg_names[36][0], /* fr4 */ \
2497 &rs6000_reg_names[37][0], /* fr5 */ \
2498 &rs6000_reg_names[38][0], /* fr6 */ \
2499 &rs6000_reg_names[39][0], /* fr7 */ \
2500 &rs6000_reg_names[40][0], /* fr8 */ \
2501 &rs6000_reg_names[41][0], /* fr9 */ \
2502 &rs6000_reg_names[42][0], /* fr10 */ \
2503 &rs6000_reg_names[43][0], /* fr11 */ \
2504 &rs6000_reg_names[44][0], /* fr12 */ \
2505 &rs6000_reg_names[45][0], /* fr13 */ \
2506 &rs6000_reg_names[46][0], /* fr14 */ \
2507 &rs6000_reg_names[47][0], /* fr15 */ \
2508 &rs6000_reg_names[48][0], /* fr16 */ \
2509 &rs6000_reg_names[49][0], /* fr17 */ \
2510 &rs6000_reg_names[50][0], /* fr18 */ \
2511 &rs6000_reg_names[51][0], /* fr19 */ \
2512 &rs6000_reg_names[52][0], /* fr20 */ \
2513 &rs6000_reg_names[53][0], /* fr21 */ \
2514 &rs6000_reg_names[54][0], /* fr22 */ \
2515 &rs6000_reg_names[55][0], /* fr23 */ \
2516 &rs6000_reg_names[56][0], /* fr24 */ \
2517 &rs6000_reg_names[57][0], /* fr25 */ \
2518 &rs6000_reg_names[58][0], /* fr26 */ \
2519 &rs6000_reg_names[59][0], /* fr27 */ \
2520 &rs6000_reg_names[60][0], /* fr28 */ \
2521 &rs6000_reg_names[61][0], /* fr29 */ \
2522 &rs6000_reg_names[62][0], /* fr30 */ \
2523 &rs6000_reg_names[63][0], /* fr31 */ \
2525 &rs6000_reg_names[64][0], /* mq */ \
2526 &rs6000_reg_names[65][0], /* lr */ \
2527 &rs6000_reg_names[66][0], /* ctr */ \
2528 &rs6000_reg_names[67][0], /* ap */ \
2530 &rs6000_reg_names[68][0], /* cr0 */ \
2531 &rs6000_reg_names[69][0], /* cr1 */ \
2532 &rs6000_reg_names[70][0], /* cr2 */ \
2533 &rs6000_reg_names[71][0], /* cr3 */ \
2534 &rs6000_reg_names[72][0], /* cr4 */ \
2535 &rs6000_reg_names[73][0], /* cr5 */ \
2536 &rs6000_reg_names[74][0], /* cr6 */ \
2537 &rs6000_reg_names[75][0], /* cr7 */ \
2539 &rs6000_reg_names[76][0], /* xer */ \
2541 &rs6000_reg_names[77][0], /* v0 */ \
2542 &rs6000_reg_names[78][0], /* v1 */ \
2543 &rs6000_reg_names[79][0], /* v2 */ \
2544 &rs6000_reg_names[80][0], /* v3 */ \
2545 &rs6000_reg_names[81][0], /* v4 */ \
2546 &rs6000_reg_names[82][0], /* v5 */ \
2547 &rs6000_reg_names[83][0], /* v6 */ \
2548 &rs6000_reg_names[84][0], /* v7 */ \
2549 &rs6000_reg_names[85][0], /* v8 */ \
2550 &rs6000_reg_names[86][0], /* v9 */ \
2551 &rs6000_reg_names[87][0], /* v10 */ \
2552 &rs6000_reg_names[88][0], /* v11 */ \
2553 &rs6000_reg_names[89][0], /* v12 */ \
2554 &rs6000_reg_names[90][0], /* v13 */ \
2555 &rs6000_reg_names[91][0], /* v14 */ \
2556 &rs6000_reg_names[92][0], /* v15 */ \
2557 &rs6000_reg_names[93][0], /* v16 */ \
2558 &rs6000_reg_names[94][0], /* v17 */ \
2559 &rs6000_reg_names[95][0], /* v18 */ \
2560 &rs6000_reg_names[96][0], /* v19 */ \
2561 &rs6000_reg_names[97][0], /* v20 */ \
2562 &rs6000_reg_names[98][0], /* v21 */ \
2563 &rs6000_reg_names[99][0], /* v22 */ \
2564 &rs6000_reg_names[100][0], /* v23 */ \
2565 &rs6000_reg_names[101][0], /* v24 */ \
2566 &rs6000_reg_names[102][0], /* v25 */ \
2567 &rs6000_reg_names[103][0], /* v26 */ \
2568 &rs6000_reg_names[104][0], /* v27 */ \
2569 &rs6000_reg_names[105][0], /* v28 */ \
2570 &rs6000_reg_names[106][0], /* v29 */ \
2571 &rs6000_reg_names[107][0], /* v30 */ \
2572 &rs6000_reg_names[108][0], /* v31 */ \
2573 &rs6000_reg_names[109][0], /* vrsave */ \
2574 &rs6000_reg_names[110][0], /* vscr */ \
2575 &rs6000_reg_names[111][0], /* spe_acc */ \
2576 &rs6000_reg_names[112][0], /* spefscr */ \
2579 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2580 following for it. Switch to use the alternate names since
2581 they are more mnemonic. */
2583 #define DEBUG_REGISTER_NAMES \
2585 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2586 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2587 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2588 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2589 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2590 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2591 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2592 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2593 "mq", "lr", "ctr", "ap", \
2594 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2596 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2597 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2598 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2599 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2601 "spe_acc", "spefscr" \
2604 /* Table of additional register names to use in user input. */
2606 #define ADDITIONAL_REGISTER_NAMES \
2607 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2608 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2609 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2610 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2611 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2612 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2613 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2614 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2615 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2616 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2617 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2618 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2619 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2620 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2621 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2622 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2623 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2624 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2625 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2626 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2627 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2628 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2629 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2630 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2631 {"vrsave", 109}, {"vscr", 110}, \
2632 {"spe_acc", 111}, {"spefscr", 112}, \
2633 /* no additional names for: mq, lr, ctr, ap */ \
2634 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2635 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2636 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2638 /* Text to write out after a CALL that may be replaced by glue code by
2639 the loader. This depends on the AIX version. */
2640 #define RS6000_CALL_GLUE "cror 31,31,31"
2642 /* This is how to output an element of a case-vector that is relative. */
2644 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2645 do { char buf[100]; \
2646 fputs ("\t.long ", FILE); \
2647 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2648 assemble_name (FILE, buf); \
2650 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2651 assemble_name (FILE, buf); \
2652 putc ('\n', FILE); \
2655 /* This is how to output an assembler line
2656 that says to advance the location counter
2657 to a multiple of 2**LOG bytes. */
2659 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2661 fprintf (FILE, "\t.align %d\n", (LOG))
2663 /* Pick up the return address upon entry to a procedure. Used for
2664 dwarf2 unwind information. This also enables the table driven
2667 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2668 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2670 /* Describe how we implement __builtin_eh_return. */
2671 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2672 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2674 /* Print operand X (an rtx) in assembler syntax to file FILE.
2675 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2676 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2678 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2680 /* Define which CODE values are valid. */
2682 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2685 /* Print a memory address as an operand to reference that memory location. */
2687 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2689 /* Define the codes that are matched by predicates in rs6000.c. */
2691 #define PREDICATE_CODES \
2692 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2693 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2694 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2695 LABEL_REF, SUBREG, REG, MEM}}, \
2696 {"short_cint_operand", {CONST_INT}}, \
2697 {"u_short_cint_operand", {CONST_INT}}, \
2698 {"non_short_cint_operand", {CONST_INT}}, \
2699 {"exact_log2_cint_operand", {CONST_INT}}, \
2700 {"gpc_reg_operand", {SUBREG, REG}}, \
2701 {"cc_reg_operand", {SUBREG, REG}}, \
2702 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2703 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2704 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2705 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2706 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2707 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2708 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2709 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2710 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2711 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2712 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2713 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2714 {"easy_fp_constant", {CONST_DOUBLE}}, \
2715 {"zero_fp_constant", {CONST_DOUBLE}}, \
2716 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2717 {"lwa_operand", {SUBREG, MEM, REG}}, \
2718 {"volatile_mem_operand", {MEM}}, \
2719 {"offsettable_mem_operand", {MEM}}, \
2720 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2721 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2722 {"non_add_cint_operand", {CONST_INT}}, \
2723 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2724 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2725 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2726 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2727 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2728 {"mask_operand", {CONST_INT}}, \
2729 {"mask_operand_wrap", {CONST_INT}}, \
2730 {"mask64_operand", {CONST_INT}}, \
2731 {"mask64_2_operand", {CONST_INT}}, \
2732 {"count_register_operand", {REG}}, \
2733 {"xer_operand", {REG}}, \
2734 {"symbol_ref_operand", {SYMBOL_REF}}, \
2735 {"call_operand", {SYMBOL_REF, REG}}, \
2736 {"current_file_function_operand", {SYMBOL_REF}}, \
2737 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2738 CONST_DOUBLE, SYMBOL_REF}}, \
2739 {"load_multiple_operation", {PARALLEL}}, \
2740 {"store_multiple_operation", {PARALLEL}}, \
2741 {"vrsave_operation", {PARALLEL}}, \
2742 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2743 GT, LEU, LTU, GEU, GTU, \
2744 UNORDERED, ORDERED, \
2746 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2748 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2749 GT, LEU, LTU, GEU, GTU, \
2750 UNORDERED, ORDERED, \
2752 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2753 GT, LEU, LTU, GEU, GTU}}, \
2754 {"boolean_operator", {AND, IOR, XOR}}, \
2755 {"boolean_or_operator", {IOR, XOR}}, \
2756 {"altivec_register_operand", {REG}}, \
2757 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2759 /* uncomment for disabling the corresponding default options */
2760 /* #define MACHINE_no_sched_interblock */
2761 /* #define MACHINE_no_sched_speculative */
2762 /* #define MACHINE_no_sched_speculative_load */
2764 /* General flags. */
2765 extern int flag_pic;
2766 extern int optimize;
2767 extern int flag_expensive_optimizations;
2768 extern int frame_pointer_needed;
2770 enum rs6000_builtins
2772 /* AltiVec builtins. */
2773 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2774 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2775 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2776 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2777 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2778 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2779 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2780 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2781 ALTIVEC_BUILTIN_VADDUBM,
2782 ALTIVEC_BUILTIN_VADDUHM,
2783 ALTIVEC_BUILTIN_VADDUWM,
2784 ALTIVEC_BUILTIN_VADDFP,
2785 ALTIVEC_BUILTIN_VADDCUW,
2786 ALTIVEC_BUILTIN_VADDUBS,
2787 ALTIVEC_BUILTIN_VADDSBS,
2788 ALTIVEC_BUILTIN_VADDUHS,
2789 ALTIVEC_BUILTIN_VADDSHS,
2790 ALTIVEC_BUILTIN_VADDUWS,
2791 ALTIVEC_BUILTIN_VADDSWS,
2792 ALTIVEC_BUILTIN_VAND,
2793 ALTIVEC_BUILTIN_VANDC,
2794 ALTIVEC_BUILTIN_VAVGUB,
2795 ALTIVEC_BUILTIN_VAVGSB,
2796 ALTIVEC_BUILTIN_VAVGUH,
2797 ALTIVEC_BUILTIN_VAVGSH,
2798 ALTIVEC_BUILTIN_VAVGUW,
2799 ALTIVEC_BUILTIN_VAVGSW,
2800 ALTIVEC_BUILTIN_VCFUX,
2801 ALTIVEC_BUILTIN_VCFSX,
2802 ALTIVEC_BUILTIN_VCTSXS,
2803 ALTIVEC_BUILTIN_VCTUXS,
2804 ALTIVEC_BUILTIN_VCMPBFP,
2805 ALTIVEC_BUILTIN_VCMPEQUB,
2806 ALTIVEC_BUILTIN_VCMPEQUH,
2807 ALTIVEC_BUILTIN_VCMPEQUW,
2808 ALTIVEC_BUILTIN_VCMPEQFP,
2809 ALTIVEC_BUILTIN_VCMPGEFP,
2810 ALTIVEC_BUILTIN_VCMPGTUB,
2811 ALTIVEC_BUILTIN_VCMPGTSB,
2812 ALTIVEC_BUILTIN_VCMPGTUH,
2813 ALTIVEC_BUILTIN_VCMPGTSH,
2814 ALTIVEC_BUILTIN_VCMPGTUW,
2815 ALTIVEC_BUILTIN_VCMPGTSW,
2816 ALTIVEC_BUILTIN_VCMPGTFP,
2817 ALTIVEC_BUILTIN_VEXPTEFP,
2818 ALTIVEC_BUILTIN_VLOGEFP,
2819 ALTIVEC_BUILTIN_VMADDFP,
2820 ALTIVEC_BUILTIN_VMAXUB,
2821 ALTIVEC_BUILTIN_VMAXSB,
2822 ALTIVEC_BUILTIN_VMAXUH,
2823 ALTIVEC_BUILTIN_VMAXSH,
2824 ALTIVEC_BUILTIN_VMAXUW,
2825 ALTIVEC_BUILTIN_VMAXSW,
2826 ALTIVEC_BUILTIN_VMAXFP,
2827 ALTIVEC_BUILTIN_VMHADDSHS,
2828 ALTIVEC_BUILTIN_VMHRADDSHS,
2829 ALTIVEC_BUILTIN_VMLADDUHM,
2830 ALTIVEC_BUILTIN_VMRGHB,
2831 ALTIVEC_BUILTIN_VMRGHH,
2832 ALTIVEC_BUILTIN_VMRGHW,
2833 ALTIVEC_BUILTIN_VMRGLB,
2834 ALTIVEC_BUILTIN_VMRGLH,
2835 ALTIVEC_BUILTIN_VMRGLW,
2836 ALTIVEC_BUILTIN_VMSUMUBM,
2837 ALTIVEC_BUILTIN_VMSUMMBM,
2838 ALTIVEC_BUILTIN_VMSUMUHM,
2839 ALTIVEC_BUILTIN_VMSUMSHM,
2840 ALTIVEC_BUILTIN_VMSUMUHS,
2841 ALTIVEC_BUILTIN_VMSUMSHS,
2842 ALTIVEC_BUILTIN_VMINUB,
2843 ALTIVEC_BUILTIN_VMINSB,
2844 ALTIVEC_BUILTIN_VMINUH,
2845 ALTIVEC_BUILTIN_VMINSH,
2846 ALTIVEC_BUILTIN_VMINUW,
2847 ALTIVEC_BUILTIN_VMINSW,
2848 ALTIVEC_BUILTIN_VMINFP,
2849 ALTIVEC_BUILTIN_VMULEUB,
2850 ALTIVEC_BUILTIN_VMULESB,
2851 ALTIVEC_BUILTIN_VMULEUH,
2852 ALTIVEC_BUILTIN_VMULESH,
2853 ALTIVEC_BUILTIN_VMULOUB,
2854 ALTIVEC_BUILTIN_VMULOSB,
2855 ALTIVEC_BUILTIN_VMULOUH,
2856 ALTIVEC_BUILTIN_VMULOSH,
2857 ALTIVEC_BUILTIN_VNMSUBFP,
2858 ALTIVEC_BUILTIN_VNOR,
2859 ALTIVEC_BUILTIN_VOR,
2860 ALTIVEC_BUILTIN_VSEL_4SI,
2861 ALTIVEC_BUILTIN_VSEL_4SF,
2862 ALTIVEC_BUILTIN_VSEL_8HI,
2863 ALTIVEC_BUILTIN_VSEL_16QI,
2864 ALTIVEC_BUILTIN_VPERM_4SI,
2865 ALTIVEC_BUILTIN_VPERM_4SF,
2866 ALTIVEC_BUILTIN_VPERM_8HI,
2867 ALTIVEC_BUILTIN_VPERM_16QI,
2868 ALTIVEC_BUILTIN_VPKUHUM,
2869 ALTIVEC_BUILTIN_VPKUWUM,
2870 ALTIVEC_BUILTIN_VPKPX,
2871 ALTIVEC_BUILTIN_VPKUHSS,
2872 ALTIVEC_BUILTIN_VPKSHSS,
2873 ALTIVEC_BUILTIN_VPKUWSS,
2874 ALTIVEC_BUILTIN_VPKSWSS,
2875 ALTIVEC_BUILTIN_VPKUHUS,
2876 ALTIVEC_BUILTIN_VPKSHUS,
2877 ALTIVEC_BUILTIN_VPKUWUS,
2878 ALTIVEC_BUILTIN_VPKSWUS,
2879 ALTIVEC_BUILTIN_VREFP,
2880 ALTIVEC_BUILTIN_VRFIM,
2881 ALTIVEC_BUILTIN_VRFIN,
2882 ALTIVEC_BUILTIN_VRFIP,
2883 ALTIVEC_BUILTIN_VRFIZ,
2884 ALTIVEC_BUILTIN_VRLB,
2885 ALTIVEC_BUILTIN_VRLH,
2886 ALTIVEC_BUILTIN_VRLW,
2887 ALTIVEC_BUILTIN_VRSQRTEFP,
2888 ALTIVEC_BUILTIN_VSLB,
2889 ALTIVEC_BUILTIN_VSLH,
2890 ALTIVEC_BUILTIN_VSLW,
2891 ALTIVEC_BUILTIN_VSL,
2892 ALTIVEC_BUILTIN_VSLO,
2893 ALTIVEC_BUILTIN_VSPLTB,
2894 ALTIVEC_BUILTIN_VSPLTH,
2895 ALTIVEC_BUILTIN_VSPLTW,
2896 ALTIVEC_BUILTIN_VSPLTISB,
2897 ALTIVEC_BUILTIN_VSPLTISH,
2898 ALTIVEC_BUILTIN_VSPLTISW,
2899 ALTIVEC_BUILTIN_VSRB,
2900 ALTIVEC_BUILTIN_VSRH,
2901 ALTIVEC_BUILTIN_VSRW,
2902 ALTIVEC_BUILTIN_VSRAB,
2903 ALTIVEC_BUILTIN_VSRAH,
2904 ALTIVEC_BUILTIN_VSRAW,
2905 ALTIVEC_BUILTIN_VSR,
2906 ALTIVEC_BUILTIN_VSRO,
2907 ALTIVEC_BUILTIN_VSUBUBM,
2908 ALTIVEC_BUILTIN_VSUBUHM,
2909 ALTIVEC_BUILTIN_VSUBUWM,
2910 ALTIVEC_BUILTIN_VSUBFP,
2911 ALTIVEC_BUILTIN_VSUBCUW,
2912 ALTIVEC_BUILTIN_VSUBUBS,
2913 ALTIVEC_BUILTIN_VSUBSBS,
2914 ALTIVEC_BUILTIN_VSUBUHS,
2915 ALTIVEC_BUILTIN_VSUBSHS,
2916 ALTIVEC_BUILTIN_VSUBUWS,
2917 ALTIVEC_BUILTIN_VSUBSWS,
2918 ALTIVEC_BUILTIN_VSUM4UBS,
2919 ALTIVEC_BUILTIN_VSUM4SBS,
2920 ALTIVEC_BUILTIN_VSUM4SHS,
2921 ALTIVEC_BUILTIN_VSUM2SWS,
2922 ALTIVEC_BUILTIN_VSUMSWS,
2923 ALTIVEC_BUILTIN_VXOR,
2924 ALTIVEC_BUILTIN_VSLDOI_16QI,
2925 ALTIVEC_BUILTIN_VSLDOI_8HI,
2926 ALTIVEC_BUILTIN_VSLDOI_4SI,
2927 ALTIVEC_BUILTIN_VSLDOI_4SF,
2928 ALTIVEC_BUILTIN_VUPKHSB,
2929 ALTIVEC_BUILTIN_VUPKHPX,
2930 ALTIVEC_BUILTIN_VUPKHSH,
2931 ALTIVEC_BUILTIN_VUPKLSB,
2932 ALTIVEC_BUILTIN_VUPKLPX,
2933 ALTIVEC_BUILTIN_VUPKLSH,
2934 ALTIVEC_BUILTIN_MTVSCR,
2935 ALTIVEC_BUILTIN_MFVSCR,
2936 ALTIVEC_BUILTIN_DSSALL,
2937 ALTIVEC_BUILTIN_DSS,
2938 ALTIVEC_BUILTIN_LVSL,
2939 ALTIVEC_BUILTIN_LVSR,
2940 ALTIVEC_BUILTIN_DSTT,
2941 ALTIVEC_BUILTIN_DSTST,
2942 ALTIVEC_BUILTIN_DSTSTT,
2943 ALTIVEC_BUILTIN_DST,
2944 ALTIVEC_BUILTIN_LVEBX,
2945 ALTIVEC_BUILTIN_LVEHX,
2946 ALTIVEC_BUILTIN_LVEWX,
2947 ALTIVEC_BUILTIN_LVXL,
2948 ALTIVEC_BUILTIN_LVX,
2949 ALTIVEC_BUILTIN_STVX,
2950 ALTIVEC_BUILTIN_STVEBX,
2951 ALTIVEC_BUILTIN_STVEHX,
2952 ALTIVEC_BUILTIN_STVEWX,
2953 ALTIVEC_BUILTIN_STVXL,
2954 ALTIVEC_BUILTIN_VCMPBFP_P,
2955 ALTIVEC_BUILTIN_VCMPEQFP_P,
2956 ALTIVEC_BUILTIN_VCMPEQUB_P,
2957 ALTIVEC_BUILTIN_VCMPEQUH_P,
2958 ALTIVEC_BUILTIN_VCMPEQUW_P,
2959 ALTIVEC_BUILTIN_VCMPGEFP_P,
2960 ALTIVEC_BUILTIN_VCMPGTFP_P,
2961 ALTIVEC_BUILTIN_VCMPGTSB_P,
2962 ALTIVEC_BUILTIN_VCMPGTSH_P,
2963 ALTIVEC_BUILTIN_VCMPGTSW_P,
2964 ALTIVEC_BUILTIN_VCMPGTUB_P,
2965 ALTIVEC_BUILTIN_VCMPGTUH_P,
2966 ALTIVEC_BUILTIN_VCMPGTUW_P,
2967 ALTIVEC_BUILTIN_ABSS_V4SI,
2968 ALTIVEC_BUILTIN_ABSS_V8HI,
2969 ALTIVEC_BUILTIN_ABSS_V16QI,
2970 ALTIVEC_BUILTIN_ABS_V4SI,
2971 ALTIVEC_BUILTIN_ABS_V4SF,
2972 ALTIVEC_BUILTIN_ABS_V8HI,
2973 ALTIVEC_BUILTIN_ABS_V16QI
2975 , SPE_BUILTIN_EVADDW,
2978 SPE_BUILTIN_EVDIVWS,
2979 SPE_BUILTIN_EVDIVWU,
2981 SPE_BUILTIN_EVFSADD,
2982 SPE_BUILTIN_EVFSDIV,
2983 SPE_BUILTIN_EVFSMUL,
2984 SPE_BUILTIN_EVFSSUB,
2988 SPE_BUILTIN_EVLHHESPLATX,
2989 SPE_BUILTIN_EVLHHOSSPLATX,
2990 SPE_BUILTIN_EVLHHOUSPLATX,
2991 SPE_BUILTIN_EVLWHEX,
2992 SPE_BUILTIN_EVLWHOSX,
2993 SPE_BUILTIN_EVLWHOUX,
2994 SPE_BUILTIN_EVLWHSPLATX,
2995 SPE_BUILTIN_EVLWWSPLATX,
2996 SPE_BUILTIN_EVMERGEHI,
2997 SPE_BUILTIN_EVMERGEHILO,
2998 SPE_BUILTIN_EVMERGELO,
2999 SPE_BUILTIN_EVMERGELOHI,
3000 SPE_BUILTIN_EVMHEGSMFAA,
3001 SPE_BUILTIN_EVMHEGSMFAN,
3002 SPE_BUILTIN_EVMHEGSMIAA,
3003 SPE_BUILTIN_EVMHEGSMIAN,
3004 SPE_BUILTIN_EVMHEGUMIAA,
3005 SPE_BUILTIN_EVMHEGUMIAN,
3006 SPE_BUILTIN_EVMHESMF,
3007 SPE_BUILTIN_EVMHESMFA,
3008 SPE_BUILTIN_EVMHESMFAAW,
3009 SPE_BUILTIN_EVMHESMFANW,
3010 SPE_BUILTIN_EVMHESMI,
3011 SPE_BUILTIN_EVMHESMIA,
3012 SPE_BUILTIN_EVMHESMIAAW,
3013 SPE_BUILTIN_EVMHESMIANW,
3014 SPE_BUILTIN_EVMHESSF,
3015 SPE_BUILTIN_EVMHESSFA,
3016 SPE_BUILTIN_EVMHESSFAAW,
3017 SPE_BUILTIN_EVMHESSFANW,
3018 SPE_BUILTIN_EVMHESSIAAW,
3019 SPE_BUILTIN_EVMHESSIANW,
3020 SPE_BUILTIN_EVMHEUMI,
3021 SPE_BUILTIN_EVMHEUMIA,
3022 SPE_BUILTIN_EVMHEUMIAAW,
3023 SPE_BUILTIN_EVMHEUMIANW,
3024 SPE_BUILTIN_EVMHEUSIAAW,
3025 SPE_BUILTIN_EVMHEUSIANW,
3026 SPE_BUILTIN_EVMHOGSMFAA,
3027 SPE_BUILTIN_EVMHOGSMFAN,
3028 SPE_BUILTIN_EVMHOGSMIAA,
3029 SPE_BUILTIN_EVMHOGSMIAN,
3030 SPE_BUILTIN_EVMHOGUMIAA,
3031 SPE_BUILTIN_EVMHOGUMIAN,
3032 SPE_BUILTIN_EVMHOSMF,
3033 SPE_BUILTIN_EVMHOSMFA,
3034 SPE_BUILTIN_EVMHOSMFAAW,
3035 SPE_BUILTIN_EVMHOSMFANW,
3036 SPE_BUILTIN_EVMHOSMI,
3037 SPE_BUILTIN_EVMHOSMIA,
3038 SPE_BUILTIN_EVMHOSMIAAW,
3039 SPE_BUILTIN_EVMHOSMIANW,
3040 SPE_BUILTIN_EVMHOSSF,
3041 SPE_BUILTIN_EVMHOSSFA,
3042 SPE_BUILTIN_EVMHOSSFAAW,
3043 SPE_BUILTIN_EVMHOSSFANW,
3044 SPE_BUILTIN_EVMHOSSIAAW,
3045 SPE_BUILTIN_EVMHOSSIANW,
3046 SPE_BUILTIN_EVMHOUMI,
3047 SPE_BUILTIN_EVMHOUMIA,
3048 SPE_BUILTIN_EVMHOUMIAAW,
3049 SPE_BUILTIN_EVMHOUMIANW,
3050 SPE_BUILTIN_EVMHOUSIAAW,
3051 SPE_BUILTIN_EVMHOUSIANW,
3052 SPE_BUILTIN_EVMWHSMF,
3053 SPE_BUILTIN_EVMWHSMFA,
3054 SPE_BUILTIN_EVMWHSMI,
3055 SPE_BUILTIN_EVMWHSMIA,
3056 SPE_BUILTIN_EVMWHSSF,
3057 SPE_BUILTIN_EVMWHSSFA,
3058 SPE_BUILTIN_EVMWHUMI,
3059 SPE_BUILTIN_EVMWHUMIA,
3060 SPE_BUILTIN_EVMWLSMIAAW,
3061 SPE_BUILTIN_EVMWLSMIANW,
3062 SPE_BUILTIN_EVMWLSSIAAW,
3063 SPE_BUILTIN_EVMWLSSIANW,
3064 SPE_BUILTIN_EVMWLUMI,
3065 SPE_BUILTIN_EVMWLUMIA,
3066 SPE_BUILTIN_EVMWLUMIAAW,
3067 SPE_BUILTIN_EVMWLUMIANW,
3068 SPE_BUILTIN_EVMWLUSIAAW,
3069 SPE_BUILTIN_EVMWLUSIANW,
3070 SPE_BUILTIN_EVMWSMF,
3071 SPE_BUILTIN_EVMWSMFA,
3072 SPE_BUILTIN_EVMWSMFAA,
3073 SPE_BUILTIN_EVMWSMFAN,
3074 SPE_BUILTIN_EVMWSMI,
3075 SPE_BUILTIN_EVMWSMIA,
3076 SPE_BUILTIN_EVMWSMIAA,
3077 SPE_BUILTIN_EVMWSMIAN,
3078 SPE_BUILTIN_EVMWHSSFAA,
3079 SPE_BUILTIN_EVMWSSF,
3080 SPE_BUILTIN_EVMWSSFA,
3081 SPE_BUILTIN_EVMWSSFAA,
3082 SPE_BUILTIN_EVMWSSFAN,
3083 SPE_BUILTIN_EVMWUMI,
3084 SPE_BUILTIN_EVMWUMIA,
3085 SPE_BUILTIN_EVMWUMIAA,
3086 SPE_BUILTIN_EVMWUMIAN,
3095 SPE_BUILTIN_EVSTDDX,
3096 SPE_BUILTIN_EVSTDHX,
3097 SPE_BUILTIN_EVSTDWX,
3098 SPE_BUILTIN_EVSTWHEX,
3099 SPE_BUILTIN_EVSTWHOX,
3100 SPE_BUILTIN_EVSTWWEX,
3101 SPE_BUILTIN_EVSTWWOX,
3102 SPE_BUILTIN_EVSUBFW,
3105 SPE_BUILTIN_EVADDSMIAAW,
3106 SPE_BUILTIN_EVADDSSIAAW,
3107 SPE_BUILTIN_EVADDUMIAAW,
3108 SPE_BUILTIN_EVADDUSIAAW,
3109 SPE_BUILTIN_EVCNTLSW,
3110 SPE_BUILTIN_EVCNTLZW,
3111 SPE_BUILTIN_EVEXTSB,
3112 SPE_BUILTIN_EVEXTSH,
3113 SPE_BUILTIN_EVFSABS,
3114 SPE_BUILTIN_EVFSCFSF,
3115 SPE_BUILTIN_EVFSCFSI,
3116 SPE_BUILTIN_EVFSCFUF,
3117 SPE_BUILTIN_EVFSCFUI,
3118 SPE_BUILTIN_EVFSCTSF,
3119 SPE_BUILTIN_EVFSCTSI,
3120 SPE_BUILTIN_EVFSCTSIZ,
3121 SPE_BUILTIN_EVFSCTUF,
3122 SPE_BUILTIN_EVFSCTUI,
3123 SPE_BUILTIN_EVFSCTUIZ,
3124 SPE_BUILTIN_EVFSNABS,
3125 SPE_BUILTIN_EVFSNEG,
3129 SPE_BUILTIN_EVSUBFSMIAAW,
3130 SPE_BUILTIN_EVSUBFSSIAAW,
3131 SPE_BUILTIN_EVSUBFUMIAAW,
3132 SPE_BUILTIN_EVSUBFUSIAAW,
3133 SPE_BUILTIN_EVADDIW,
3137 SPE_BUILTIN_EVLHHESPLAT,
3138 SPE_BUILTIN_EVLHHOSSPLAT,
3139 SPE_BUILTIN_EVLHHOUSPLAT,
3141 SPE_BUILTIN_EVLWHOS,
3142 SPE_BUILTIN_EVLWHOU,
3143 SPE_BUILTIN_EVLWHSPLAT,
3144 SPE_BUILTIN_EVLWWSPLAT,
3147 SPE_BUILTIN_EVSRWIS,
3148 SPE_BUILTIN_EVSRWIU,
3152 SPE_BUILTIN_EVSTWHE,
3153 SPE_BUILTIN_EVSTWHO,
3154 SPE_BUILTIN_EVSTWWE,
3155 SPE_BUILTIN_EVSTWWO,
3156 SPE_BUILTIN_EVSUBIFW,
3159 SPE_BUILTIN_EVCMPEQ,
3160 SPE_BUILTIN_EVCMPGTS,
3161 SPE_BUILTIN_EVCMPGTU,
3162 SPE_BUILTIN_EVCMPLTS,
3163 SPE_BUILTIN_EVCMPLTU,
3164 SPE_BUILTIN_EVFSCMPEQ,
3165 SPE_BUILTIN_EVFSCMPGT,
3166 SPE_BUILTIN_EVFSCMPLT,
3167 SPE_BUILTIN_EVFSTSTEQ,
3168 SPE_BUILTIN_EVFSTSTGT,
3169 SPE_BUILTIN_EVFSTSTLT,
3171 /* EVSEL compares. */
3172 SPE_BUILTIN_EVSEL_CMPEQ,
3173 SPE_BUILTIN_EVSEL_CMPGTS,
3174 SPE_BUILTIN_EVSEL_CMPGTU,
3175 SPE_BUILTIN_EVSEL_CMPLTS,
3176 SPE_BUILTIN_EVSEL_CMPLTU,
3177 SPE_BUILTIN_EVSEL_FSCMPEQ,
3178 SPE_BUILTIN_EVSEL_FSCMPGT,
3179 SPE_BUILTIN_EVSEL_FSCMPLT,
3180 SPE_BUILTIN_EVSEL_FSTSTEQ,
3181 SPE_BUILTIN_EVSEL_FSTSTGT,
3182 SPE_BUILTIN_EVSEL_FSTSTLT,
3184 SPE_BUILTIN_EVSPLATFI,
3185 SPE_BUILTIN_EVSPLATI,
3186 SPE_BUILTIN_EVMWHSSMAA,
3187 SPE_BUILTIN_EVMWHSMFAA,
3188 SPE_BUILTIN_EVMWHSMIAA,
3189 SPE_BUILTIN_EVMWHUSIAA,
3190 SPE_BUILTIN_EVMWHUMIAA,
3191 SPE_BUILTIN_EVMWHSSFAN,
3192 SPE_BUILTIN_EVMWHSSIAN,
3193 SPE_BUILTIN_EVMWHSMFAN,
3194 SPE_BUILTIN_EVMWHSMIAN,
3195 SPE_BUILTIN_EVMWHUSIAN,
3196 SPE_BUILTIN_EVMWHUMIAN,
3197 SPE_BUILTIN_EVMWHGSSFAA,
3198 SPE_BUILTIN_EVMWHGSMFAA,
3199 SPE_BUILTIN_EVMWHGSMIAA,
3200 SPE_BUILTIN_EVMWHGUMIAA,
3201 SPE_BUILTIN_EVMWHGSSFAN,
3202 SPE_BUILTIN_EVMWHGSMFAN,
3203 SPE_BUILTIN_EVMWHGSMIAN,
3204 SPE_BUILTIN_EVMWHGUMIAN,
3205 SPE_BUILTIN_MTSPEFSCR,
3206 SPE_BUILTIN_MFSPEFSCR,
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