1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common ASM definitions used by ASM_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define ASM_CPU_SPEC \
52 %{mpower: %{!mpower2: -mpwr}} \
55 %{mno-power: %{!mpowerpc*: -mcom}} \
56 %{!mno-power: %{!mpower2: %(asm_default)}}} \
57 %{mcpu=common: -mcom} \
58 %{mcpu=power: -mpwr} \
59 %{mcpu=power2: -mpwrx} \
60 %{mcpu=power3: -m604} \
61 %{mcpu=power4: -mpower4} \
62 %{mcpu=powerpc: -mppc} \
64 %{mcpu=rios1: -mpwr} \
65 %{mcpu=rios2: -mpwrx} \
77 %{mcpu=ec603e: -mppc} \
90 %{mcpu=8540: -me500} \
91 %{maltivec: -maltivec}"
93 #define CPP_DEFAULT_SPEC ""
95 #define ASM_DEFAULT_SPEC ""
97 /* This macro defines names of additional specifications to put in the specs
98 that can be used in various specifications like CC1_SPEC. Its definition
99 is an initializer with a subgrouping for each command option.
101 Each subgrouping contains a string constant, that defines the
102 specification name, and a string constant that used by the GCC driver
105 Do not define this macro if it does not need to do anything. */
107 #define SUBTARGET_EXTRA_SPECS
109 #define EXTRA_SPECS \
110 { "cpp_default", CPP_DEFAULT_SPEC }, \
111 { "asm_cpu", ASM_CPU_SPEC }, \
112 { "asm_default", ASM_DEFAULT_SPEC }, \
113 SUBTARGET_EXTRA_SPECS
115 /* Architecture type. */
117 extern int target_flags;
119 /* Use POWER architecture instructions and MQ register. */
120 #define MASK_POWER 0x00000001
122 /* Use POWER2 extensions to POWER architecture. */
123 #define MASK_POWER2 0x00000002
125 /* Use PowerPC architecture instructions. */
126 #define MASK_POWERPC 0x00000004
128 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
129 #define MASK_PPC_GPOPT 0x00000008
131 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
132 #define MASK_PPC_GFXOPT 0x00000010
134 /* Use PowerPC-64 architecture instructions. */
135 #define MASK_POWERPC64 0x00000020
137 /* Use revised mnemonic names defined for PowerPC architecture. */
138 #define MASK_NEW_MNEMONICS 0x00000040
140 /* Disable placing fp constants in the TOC; can be turned on when the
142 #define MASK_NO_FP_IN_TOC 0x00000080
144 /* Disable placing symbol+offset constants in the TOC; can be turned on when
145 the TOC overflows. */
146 #define MASK_NO_SUM_IN_TOC 0x00000100
148 /* Output only one TOC entry per module. Normally linking fails if
149 there are more than 16K unique variables/constants in an executable. With
150 this option, linking fails only if there are more than 16K modules, or
151 if there are more than 16K unique variables/constant in a single module.
153 This is at the cost of having 2 extra loads and one extra store per
154 function, and one less allocable register. */
155 #define MASK_MINIMAL_TOC 0x00000200
157 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
158 #define MASK_64BIT 0x00000400
160 /* Disable use of FPRs. */
161 #define MASK_SOFT_FLOAT 0x00000800
163 /* Enable load/store multiple, even on PowerPC */
164 #define MASK_MULTIPLE 0x00001000
166 /* Use string instructions for block moves */
167 #define MASK_STRING 0x00002000
169 /* Disable update form of load/store */
170 #define MASK_NO_UPDATE 0x00004000
172 /* Disable fused multiply/add operations */
173 #define MASK_NO_FUSED_MADD 0x00008000
175 /* Nonzero if we need to schedule the prolog and epilog. */
176 #define MASK_SCHED_PROLOG 0x00010000
178 /* Use AltiVec instructions. */
179 #define MASK_ALTIVEC 0x00020000
181 /* Return small structures in memory (as the AIX ABI requires). */
182 #define MASK_AIX_STRUCT_RET 0x00040000
184 /* The only remaining free bits are 0x00780000. sysv4.h uses
185 0x00800000 -> 0x40000000, and 0x80000000 is not available
186 because target_flags is signed. */
188 #define TARGET_POWER (target_flags & MASK_POWER)
189 #define TARGET_POWER2 (target_flags & MASK_POWER2)
190 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
191 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
192 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
193 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
194 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
195 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
196 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
197 #define TARGET_64BIT (target_flags & MASK_64BIT)
198 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
199 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
200 #define TARGET_STRING (target_flags & MASK_STRING)
201 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
202 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
203 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
204 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
205 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
207 #define TARGET_32BIT (! TARGET_64BIT)
208 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
209 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
210 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
213 /* For libgcc2 we make sure this is a compile time constant */
214 #if defined (__64BIT__) || defined (__powerpc64__)
215 #define TARGET_POWERPC64 1
217 #define TARGET_POWERPC64 0
220 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
223 #define TARGET_XL_CALL 0
225 /* Run-time compilation parameters selecting different hardware subsets.
227 Macro to define tables used to set the flags.
228 This is a list in braces of pairs in braces,
229 each pair being { "NAME", VALUE }
230 where VALUE is the bits to set or minus the bits to clear.
231 An empty string NAME is used to identify the default VALUE. */
233 #define TARGET_SWITCHES \
234 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
235 N_("Use POWER instruction set")}, \
236 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
238 N_("Use POWER2 instruction set")}, \
239 {"no-power2", - MASK_POWER2, \
240 N_("Do not use POWER2 instruction set")}, \
241 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
243 N_("Do not use POWER instruction set")}, \
244 {"powerpc", MASK_POWERPC, \
245 N_("Use PowerPC instruction set")}, \
246 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
247 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
248 N_("Do not use PowerPC instruction set")}, \
249 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
250 N_("Use PowerPC General Purpose group optional instructions")},\
251 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
252 N_("Don't use PowerPC General Purpose group optional instructions")},\
253 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
254 N_("Use PowerPC Graphics group optional instructions")},\
255 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
256 N_("Don't use PowerPC Graphics group optional instructions")},\
257 {"powerpc64", MASK_POWERPC64, \
258 N_("Use PowerPC-64 instruction set")}, \
259 {"no-powerpc64", - MASK_POWERPC64, \
260 N_("Don't use PowerPC-64 instruction set")}, \
261 {"altivec", MASK_ALTIVEC , \
262 N_("Use AltiVec instructions")}, \
263 {"no-altivec", - MASK_ALTIVEC , \
264 N_("Don't use AltiVec instructions")}, \
265 {"new-mnemonics", MASK_NEW_MNEMONICS, \
266 N_("Use new mnemonics for PowerPC architecture")},\
267 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
268 N_("Use old mnemonics for PowerPC architecture")},\
269 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
270 | MASK_MINIMAL_TOC), \
271 N_("Put everything in the regular TOC")}, \
272 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
273 N_("Place floating point constants in TOC")}, \
274 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
275 N_("Don't place floating point constants in TOC")},\
276 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
277 N_("Place symbol+offset constants in TOC")}, \
278 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
279 N_("Don't place symbol+offset constants in TOC")},\
280 {"minimal-toc", MASK_MINIMAL_TOC, \
281 "Use only one TOC entry per procedure"}, \
282 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
284 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
285 N_("Place variable addresses in the regular TOC")},\
286 {"hard-float", - MASK_SOFT_FLOAT, \
287 N_("Use hardware fp")}, \
288 {"soft-float", MASK_SOFT_FLOAT, \
289 N_("Do not use hardware fp")}, \
290 {"multiple", MASK_MULTIPLE, \
291 N_("Generate load/store multiple instructions")}, \
292 {"no-multiple", - MASK_MULTIPLE, \
293 N_("Do not generate load/store multiple instructions")},\
294 {"string", MASK_STRING, \
295 N_("Generate string instructions for block moves")},\
296 {"no-string", - MASK_STRING, \
297 N_("Do not generate string instructions for block moves")},\
298 {"update", - MASK_NO_UPDATE, \
299 N_("Generate load/store with update instructions")},\
300 {"no-update", MASK_NO_UPDATE, \
301 N_("Do not generate load/store with update instructions")},\
302 {"fused-madd", - MASK_NO_FUSED_MADD, \
303 N_("Generate fused multiply/add instructions")},\
304 {"no-fused-madd", MASK_NO_FUSED_MADD, \
305 N_("Don't generate fused multiply/add instructions")},\
306 {"sched-prolog", MASK_SCHED_PROLOG, \
308 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
309 N_("Don't schedule the start and end of the procedure")},\
310 {"sched-epilog", MASK_SCHED_PROLOG, \
312 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
314 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
315 N_("Return all structures in memory (AIX default)")},\
316 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
317 N_("Return small structures in registers (SVR4 default)")},\
318 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
320 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
323 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
326 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
328 /* This is meant to be redefined in the host dependent files */
329 #define SUBTARGET_SWITCHES
331 /* Processor type. Order must match cpu attribute in MD file. */
354 extern enum processor_type rs6000_cpu;
356 /* Recast the processor type to the cpu attribute. */
357 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
359 /* Define generic processor types based upon current deployment. */
360 #define PROCESSOR_COMMON PROCESSOR_PPC601
361 #define PROCESSOR_POWER PROCESSOR_RIOS1
362 #define PROCESSOR_POWERPC PROCESSOR_PPC604
363 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
365 /* Define the default processor. This is overridden by other tm.h files. */
366 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
367 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
369 /* Specify the dialect of assembler to use. New mnemonics is dialect one
370 and the old mnemonics are dialect zero. */
371 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
373 /* This is meant to be overridden in target specific files. */
374 #define SUBTARGET_OPTIONS
376 #define TARGET_OPTIONS \
378 {"cpu=", &rs6000_select[1].string, \
379 N_("Use features of and schedule code for given CPU"), 0}, \
380 {"tune=", &rs6000_select[2].string, \
381 N_("Schedule code for given CPU"), 0}, \
382 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
383 {"traceback=", &rs6000_traceback_name, \
384 N_("Select full, part, or no traceback table"), 0}, \
385 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
386 {"long-double-", &rs6000_long_double_size_string, \
387 N_("Specify size of long double (64 or 128 bits)"), 0}, \
388 {"isel=", &rs6000_isel_string, \
389 N_("Specify yes/no if isel instructions should be generated"), 0}, \
390 {"spe=", &rs6000_spe_string, \
391 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
392 {"float-gprs=", &rs6000_float_gprs_string, \
393 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
394 {"vrsave=", &rs6000_altivec_vrsave_string, \
395 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
396 {"longcall", &rs6000_longcall_switch, \
397 N_("Avoid all range limits on call instructions"), 0}, \
398 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
402 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
403 struct rs6000_cpu_select
411 extern struct rs6000_cpu_select rs6000_select[];
414 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
415 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
416 extern int rs6000_debug_stack; /* debug stack applications */
417 extern int rs6000_debug_arg; /* debug argument handling */
419 #define TARGET_DEBUG_STACK rs6000_debug_stack
420 #define TARGET_DEBUG_ARG rs6000_debug_arg
422 extern const char *rs6000_traceback_name; /* Type of traceback table. */
424 /* These are separate from target_flags because we've run out of bits
426 extern const char *rs6000_long_double_size_string;
427 extern int rs6000_long_double_type_size;
428 extern int rs6000_altivec_abi;
429 extern int rs6000_spe_abi;
430 extern int rs6000_isel;
431 extern int rs6000_spe;
432 extern int rs6000_float_gprs;
433 extern const char *rs6000_float_gprs_string;
434 extern const char *rs6000_isel_string;
435 extern const char *rs6000_spe_string;
436 extern const char *rs6000_altivec_vrsave_string;
437 extern int rs6000_altivec_vrsave;
438 extern const char *rs6000_longcall_switch;
439 extern int rs6000_default_long_calls;
441 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
442 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
443 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
445 #define TARGET_SPE_ABI 0
447 #define TARGET_E500 0
448 #define TARGET_ISEL 0
449 #define TARGET_FPRS 1
451 /* Sometimes certain combinations of command options do not make sense
452 on a particular target machine. You can define a macro
453 `OVERRIDE_OPTIONS' to take account of this. This macro, if
454 defined, is executed once just after all the command options have
457 Don't use this macro to turn on various extra optimizations for
458 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
460 On the RS/6000 this is used to define the target cpu type. */
462 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
464 /* Define this to change the optimizations performed by default. */
465 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
467 /* Show we can debug even without a frame pointer. */
468 #define CAN_DEBUG_WITHOUT_FP
471 #define REGISTER_TARGET_PRAGMAS() do { \
472 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
475 /* Target #defines. */
476 #define TARGET_CPU_CPP_BUILTINS() \
477 rs6000_cpu_cpp_builtins (pfile)
479 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
480 we're compiling for. Some configurations may need to override it. */
481 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
484 if (BYTES_BIG_ENDIAN) \
486 builtin_define ("__BIG_ENDIAN__"); \
487 builtin_define ("_BIG_ENDIAN"); \
488 builtin_assert ("machine=bigendian"); \
492 builtin_define ("__LITTLE_ENDIAN__"); \
493 builtin_define ("_LITTLE_ENDIAN"); \
494 builtin_assert ("machine=littleendian"); \
499 /* Target machine storage layout. */
501 /* Define this macro if it is advisable to hold scalars in registers
502 in a wider mode than that declared by the program. In such cases,
503 the value is constrained to be within the bounds of the declared
504 type, but kept valid in the wider mode. The signedness of the
505 extension may differ from that of the type. */
507 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
508 if (GET_MODE_CLASS (MODE) == MODE_INT \
509 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
512 /* Define this if function arguments should also be promoted using the above
515 #define PROMOTE_FUNCTION_ARGS
517 /* Likewise, if the function return value is promoted. */
519 #define PROMOTE_FUNCTION_RETURN
521 /* Define this if most significant bit is lowest numbered
522 in instructions that operate on numbered bit-fields. */
523 /* That is true on RS/6000. */
524 #define BITS_BIG_ENDIAN 1
526 /* Define this if most significant byte of a word is the lowest numbered. */
527 /* That is true on RS/6000. */
528 #define BYTES_BIG_ENDIAN 1
530 /* Define this if most significant word of a multiword number is lowest
533 For RS/6000 we can decide arbitrarily since there are no machine
534 instructions for them. Might as well be consistent with bits and bytes. */
535 #define WORDS_BIG_ENDIAN 1
537 #define MAX_BITS_PER_WORD 64
539 /* Width of a word, in units (bytes). */
540 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
542 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
544 #define MIN_UNITS_PER_WORD 4
546 #define UNITS_PER_FP_WORD 8
547 #define UNITS_PER_ALTIVEC_WORD 16
548 #define UNITS_PER_SPE_WORD 8
550 /* Type used for ptrdiff_t, as a string used in a declaration. */
551 #define PTRDIFF_TYPE "int"
553 /* Type used for size_t, as a string used in a declaration. */
554 #define SIZE_TYPE "long unsigned int"
556 /* Type used for wchar_t, as a string used in a declaration. */
557 #define WCHAR_TYPE "short unsigned int"
559 /* Width of wchar_t in bits. */
560 #define WCHAR_TYPE_SIZE 16
562 /* A C expression for the size in bits of the type `short' on the
563 target machine. If you don't define this, the default is half a
564 word. (If this would be less than one storage unit, it is
565 rounded up to one unit.) */
566 #define SHORT_TYPE_SIZE 16
568 /* A C expression for the size in bits of the type `int' on the
569 target machine. If you don't define this, the default is one
571 #define INT_TYPE_SIZE 32
573 /* A C expression for the size in bits of the type `long' on the
574 target machine. If you don't define this, the default is one
576 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
577 #define MAX_LONG_TYPE_SIZE 64
579 /* A C expression for the size in bits of the type `long long' on the
580 target machine. If you don't define this, the default is two
582 #define LONG_LONG_TYPE_SIZE 64
584 /* A C expression for the size in bits of the type `float' on the
585 target machine. If you don't define this, the default is one
587 #define FLOAT_TYPE_SIZE 32
589 /* A C expression for the size in bits of the type `double' on the
590 target machine. If you don't define this, the default is two
592 #define DOUBLE_TYPE_SIZE 64
594 /* A C expression for the size in bits of the type `long double' on
595 the target machine. If you don't define this, the default is two
597 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
599 /* Constant which presents upper bound of the above value. */
600 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
602 /* Define this to set long double type size to use in libgcc2.c, which can
603 not depend on target_flags. */
604 #ifdef __LONG_DOUBLE_128__
605 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
607 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
610 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
611 #define WIDEST_HARDWARE_FP_SIZE 64
613 /* Width in bits of a pointer.
614 See also the macro `Pmode' defined below. */
615 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
617 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
618 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
620 /* Boundary (in *bits*) on which stack pointer should be aligned. */
621 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
623 /* Allocation boundary (in *bits*) for the code of a function. */
624 #define FUNCTION_BOUNDARY 32
626 /* No data type wants to be aligned rounder than this. */
627 #define BIGGEST_ALIGNMENT 128
629 /* A C expression to compute the alignment for a variables in the
630 local store. TYPE is the data type, and ALIGN is the alignment
631 that the object would ordinarily have. */
632 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
633 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
634 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
636 /* Alignment of field after `int : 0' in a structure. */
637 #define EMPTY_FIELD_BOUNDARY 32
639 /* Every structure's size must be a multiple of this. */
640 #define STRUCTURE_SIZE_BOUNDARY 8
642 /* Return 1 if a structure or array containing FIELD should be
643 accessed using `BLKMODE'.
645 For the SPE, simd types are V2SI, and gcc can be tempted to put the
646 entire thing in a DI and use subregs to access the internals.
647 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
648 back-end. Because a single GPR can hold a V2SI, but not a DI, the
649 best thing to do is set structs to BLKmode and avoid Severe Tire
651 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
652 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
654 /* A bit-field declared as `int' forces `int' alignment for the struct. */
655 #define PCC_BITFIELD_TYPE_MATTERS 1
657 /* Make strings word-aligned so strcpy from constants will be faster.
658 Make vector constants quadword aligned. */
659 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
660 (TREE_CODE (EXP) == STRING_CST \
661 && (ALIGN) < BITS_PER_WORD \
665 /* Make arrays of chars word-aligned for the same reasons.
666 Align vectors to 128 bits. */
667 #define DATA_ALIGNMENT(TYPE, ALIGN) \
668 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
669 : TREE_CODE (TYPE) == ARRAY_TYPE \
670 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
671 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
673 /* Nonzero if move instructions will actually fail to work
674 when given unaligned data. */
675 #define STRICT_ALIGNMENT 0
677 /* Define this macro to be the value 1 if unaligned accesses have a cost
678 many times greater than aligned accesses, for example if they are
679 emulated in a trap handler. */
680 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
682 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
683 || (MODE) == DImode) \
686 /* Standard register usage. */
688 /* Number of actual hardware registers.
689 The hardware registers are assigned numbers for the compiler
690 from 0 to just below FIRST_PSEUDO_REGISTER.
691 All registers that the compiler knows about must be given numbers,
692 even those that are not normally considered general registers.
694 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
695 an MQ register, a count register, a link register, and 8 condition
696 register fields, which we view here as separate registers. AltiVec
697 adds 32 vector registers and a VRsave register.
699 In addition, the difference between the frame and argument pointers is
700 a function of the number of registers saved, so we need to have a
701 register for AP that will later be eliminated in favor of SP or FP.
702 This is a normal register, but it is fixed.
704 We also create a pseudo register for float/int conversions, that will
705 really represent the memory location used. It is represented here as
706 a register, in order to work around problems in allocating stack storage
707 in inline functions. */
709 #define FIRST_PSEUDO_REGISTER 113
711 /* This must be included for pre gcc 3.0 glibc compatibility. */
712 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
714 /* Add 32 dwarf columns for synthetic SPE registers. The SPE
715 synthetic registers are 113 through 145. */
716 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
718 /* The SPE has an additional 32 synthetic registers starting at 1200.
719 We must map them here to sane values in the unwinder to avoid a
720 huge hole in the unwind tables.
722 FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
723 the VRSAVE SPR (SPR256) assigned to register 356. When AltiVec EH
724 is verified to be working, this macro should be changed
726 #define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
728 /* 1 for registers that have pervasive standard uses
729 and are not available for the register allocator.
731 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
732 as a local register; for all other OS's r2 is the TOC pointer.
734 cr5 is not supposed to be used.
736 On System V implementations, r13 is fixed and not available for use. */
738 #define FIXED_REGISTERS \
739 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
743 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
744 /* AltiVec registers. */ \
745 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
751 /* 1 for registers not available across function calls.
752 These must include the FIXED_REGISTERS and also any
753 registers that can be used without being saved.
754 The latter must include the registers where values are returned
755 and the register where structure-value addresses are passed.
756 Aside from that, you can include as many other registers as you like. */
758 #define CALL_USED_REGISTERS \
759 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
761 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
763 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
764 /* AltiVec registers. */ \
765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
766 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
771 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
772 the entire set of `FIXED_REGISTERS' be included.
773 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
774 This macro is optional. If not specified, it defaults to the value
775 of `CALL_USED_REGISTERS'. */
777 #define CALL_REALLY_USED_REGISTERS \
778 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
779 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
780 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
782 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
783 /* AltiVec registers. */ \
784 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
785 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
796 #define MAX_CR_REGNO 75
798 #define FIRST_ALTIVEC_REGNO 77
799 #define LAST_ALTIVEC_REGNO 108
800 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
801 #define VRSAVE_REGNO 109
802 #define VSCR_REGNO 110
803 #define SPE_ACC_REGNO 111
804 #define SPEFSCR_REGNO 112
806 /* List the order in which to allocate registers. Each register must be
807 listed once, even those in FIXED_REGISTERS.
809 We allocate in the following order:
810 fp0 (not saved or used for anything)
811 fp13 - fp2 (not saved; incoming fp arg registers)
812 fp1 (not saved; return value)
813 fp31 - fp14 (saved; order given to save least number)
814 cr7, cr6 (not saved or special)
815 cr1 (not saved, but used for FP operations)
816 cr0 (not saved, but used for arithmetic operations)
817 cr4, cr3, cr2 (saved)
818 r0 (not saved; cannot be base reg)
819 r9 (not saved; best for TImode)
820 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
821 r3 (not saved; return value register)
822 r31 - r13 (saved; order given to save least number)
823 r12 (not saved; if used for DImode or DFmode would use r13)
824 mq (not saved; best to use it if we can)
825 ctr (not saved; when we have the choice ctr is better)
827 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
828 spe_acc, spefscr (fixed)
831 v0 - v1 (not saved or used for anything)
832 v13 - v3 (not saved; incoming vector arg registers)
833 v2 (not saved; incoming vector arg reg; return value)
834 v19 - v14 (not saved or used for anything)
835 v31 - v20 (saved; order given to save least number)
839 #define MAYBE_R2_AVAILABLE
840 #define MAYBE_R2_FIXED 2,
842 #define MAYBE_R2_AVAILABLE 2,
843 #define MAYBE_R2_FIXED
846 #define REG_ALLOC_ORDER \
848 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
850 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
851 50, 49, 48, 47, 46, \
852 75, 74, 69, 68, 72, 71, 70, \
853 0, MAYBE_R2_AVAILABLE \
854 9, 11, 10, 8, 7, 6, 5, 4, \
856 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
857 18, 17, 16, 15, 14, 13, 12, \
859 73, 1, MAYBE_R2_FIXED 67, 76, \
860 /* AltiVec registers. */ \
862 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
864 96, 95, 94, 93, 92, 91, \
865 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
870 /* True if register is floating-point. */
871 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
873 /* True if register is a condition register. */
874 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
876 /* True if register is a condition register, but not cr0. */
877 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
879 /* True if register is an integer register. */
880 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
882 /* SPE SIMD registers are just the GPRs. */
883 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
885 /* True if register is the XER register. */
886 #define XER_REGNO_P(N) ((N) == XER_REGNO)
888 /* True if register is an AltiVec register. */
889 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
891 /* Return number of consecutive hard regs needed starting at reg REGNO
892 to hold something of mode MODE.
893 This is ordinarily the length in words of a value of mode MODE
894 but can be less for certain modes in special long registers.
896 For the SPE, GPRs are 64 bits but only 32 bits are visible in
897 scalar instructions. The upper 32 bits are only available to the
900 POWER and PowerPC GPRs hold 32 bits worth;
901 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
903 #define HARD_REGNO_NREGS(REGNO, MODE) \
904 (FP_REGNO_P (REGNO) \
905 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
906 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
907 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
908 : ALTIVEC_REGNO_P (REGNO) \
909 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
910 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
912 #define ALTIVEC_VECTOR_MODE(MODE) \
913 ((MODE) == V16QImode \
914 || (MODE) == V8HImode \
915 || (MODE) == V4SFmode \
916 || (MODE) == V4SImode)
918 #define SPE_VECTOR_MODE(MODE) \
919 ((MODE) == V4HImode \
920 || (MODE) == V2SFmode \
921 || (MODE) == V1DImode \
922 || (MODE) == V2SImode)
924 /* Define this macro to be nonzero if the port is prepared to handle
925 insns involving vector mode MODE. At the very least, it must have
926 move patterns for this mode. */
928 #define VECTOR_MODE_SUPPORTED_P(MODE) \
929 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
930 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
932 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
933 For POWER and PowerPC, the GPRs can hold any mode, but values bigger
934 than one register cannot go past R31. The float
935 registers only can hold floating modes and DImode, and CR register only
936 can hold CC modes. We cannot put TImode anywhere except general
937 register and it must be able to fit within the register set. */
939 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
940 (INT_REGNO_P (REGNO) ? \
941 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
942 : FP_REGNO_P (REGNO) ? \
943 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
944 || (GET_MODE_CLASS (MODE) == MODE_INT \
945 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
946 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
947 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
948 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
949 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
950 : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
952 /* Value is 1 if it is a good idea to tie two pseudo registers
953 when one has mode MODE1 and one has mode MODE2.
954 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
955 for any hard reg, then this must be 0 for correct output. */
956 #define MODES_TIEABLE_P(MODE1, MODE2) \
957 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
958 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
959 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
960 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
961 : GET_MODE_CLASS (MODE1) == MODE_CC \
962 ? GET_MODE_CLASS (MODE2) == MODE_CC \
963 : GET_MODE_CLASS (MODE2) == MODE_CC \
964 ? GET_MODE_CLASS (MODE1) == MODE_CC \
965 : ALTIVEC_VECTOR_MODE (MODE1) \
966 ? ALTIVEC_VECTOR_MODE (MODE2) \
967 : ALTIVEC_VECTOR_MODE (MODE2) \
968 ? ALTIVEC_VECTOR_MODE (MODE1) \
971 /* Post-reload, we can't use any new AltiVec registers, as we already
972 emitted the vrsave mask. */
974 #define HARD_REGNO_RENAME_OK(SRC, DST) \
975 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
977 /* A C expression returning the cost of moving data from a register of class
978 CLASS1 to one of CLASS2. */
980 #define REGISTER_MOVE_COST rs6000_register_move_cost
982 /* A C expressions returning the cost of moving data of MODE from a register to
985 #define MEMORY_MOVE_COST rs6000_memory_move_cost
987 /* Specify the cost of a branch insn; roughly the number of extra insns that
988 should be added to avoid a branch.
990 Set this to 3 on the RS/6000 since that is roughly the average cost of an
991 unscheduled conditional branch. */
993 #define BRANCH_COST 3
995 /* Override BRANCH_COST heuristic which empirically produces worse
996 performance for fold_range_test(). */
998 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1000 /* A fixed register used at prologue and epilogue generation to fix
1001 addressing modes. The SPE needs heavy addressing fixes at the last
1002 minute, and it's best to save a register for it.
1004 AltiVec also needs fixes, but we've gotten around using r11, which
1005 is actually wrong because when use_backchain_to_restore_sp is true,
1006 we end up clobbering r11.
1008 The AltiVec case needs to be fixed. Dunno if we should break ABI
1009 compatibility and reserve a register for it as well.. */
1011 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1013 /* Define this macro to change register usage conditional on target flags.
1014 Set MQ register fixed (already call_used) if not POWER architecture
1015 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
1016 64-bit AIX reserves GPR13 for thread-private data.
1017 Conditionally disable FPRs. */
1019 #define CONDITIONAL_REGISTER_USAGE \
1022 if (! TARGET_POWER) \
1023 fixed_regs[64] = 1; \
1025 fixed_regs[13] = call_used_regs[13] \
1026 = call_really_used_regs[13] = 1; \
1027 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
1028 for (i = 32; i < 64; i++) \
1029 fixed_regs[i] = call_used_regs[i] \
1030 = call_really_used_regs[i] = 1; \
1031 if (DEFAULT_ABI == ABI_V4 \
1032 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1034 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1035 if (DEFAULT_ABI == ABI_V4 \
1036 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1038 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1039 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1040 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1041 if (DEFAULT_ABI == ABI_DARWIN \
1042 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1043 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1044 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1045 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1046 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1047 if (TARGET_ALTIVEC) \
1048 global_regs[VSCR_REGNO] = 1; \
1051 global_regs[SPEFSCR_REGNO] = 1; \
1052 fixed_regs[FIXED_SCRATCH] \
1053 = call_used_regs[FIXED_SCRATCH] \
1054 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1056 if (! TARGET_ALTIVEC) \
1058 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1059 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1060 call_really_used_regs[VRSAVE_REGNO] = 1; \
1062 if (TARGET_ALTIVEC_ABI) \
1063 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1064 call_used_regs[i] = call_really_used_regs[i] = 1; \
1067 /* Specify the registers used for certain standard purposes.
1068 The values of these macros are register numbers. */
1070 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1071 /* #define PC_REGNUM */
1073 /* Register to use for pushing function arguments. */
1074 #define STACK_POINTER_REGNUM 1
1076 /* Base register for access to local variables of the function. */
1077 #define FRAME_POINTER_REGNUM 31
1079 /* Value should be nonzero if functions must have frame pointers.
1080 Zero means the frame pointer need not be set up (and parms
1081 may be accessed via the stack pointer) in functions that seem suitable.
1082 This is computed in `reload', in reload1.c. */
1083 #define FRAME_POINTER_REQUIRED 0
1085 /* Base register for access to arguments of the function. */
1086 #define ARG_POINTER_REGNUM 67
1088 /* Place to put static chain when calling a function that requires it. */
1089 #define STATIC_CHAIN_REGNUM 11
1091 /* Link register number. */
1092 #define LINK_REGISTER_REGNUM 65
1094 /* Count register number. */
1095 #define COUNT_REGISTER_REGNUM 66
1097 /* Place that structure value return address is placed.
1099 On the RS/6000, it is passed as an extra parameter. */
1100 #define STRUCT_VALUE 0
1102 /* Define the classes of registers for register constraints in the
1103 machine description. Also define ranges of constants.
1105 One of the classes must always be named ALL_REGS and include all hard regs.
1106 If there is more than one class, another class must be named NO_REGS
1107 and contain no registers.
1109 The name GENERAL_REGS must be the name of a class (or an alias for
1110 another name such as ALL_REGS). This is the class of registers
1111 that is allowed by "g" or "r" in a register constraint.
1112 Also, registers outside this class are allocated only when
1113 instructions express preferences for them.
1115 The classes must be numbered in nondecreasing order; that is,
1116 a larger-numbered class must never be contained completely
1117 in a smaller-numbered class.
1119 For any two classes, it is very desirable that there be another
1120 class that represents their union. */
1122 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1123 and condition registers, plus three special registers, MQ, CTR, and the
1124 link register. AltiVec adds a vector register class.
1126 However, r0 is special in that it cannot be used as a base register.
1127 So make a class for registers valid as base registers.
1129 Also, cr0 is the only condition code register that can be used in
1130 arithmetic insns, so make a separate class for it. */
1158 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1160 /* Give names of register classes as strings for dump file. */
1162 #define REG_CLASS_NAMES \
1173 "NON_SPECIAL_REGS", \
1177 "LINK_OR_CTR_REGS", \
1179 "SPEC_OR_GEN_REGS", \
1187 /* Define which registers fit in which classes.
1188 This is an initializer for a vector of HARD_REG_SET
1189 of length N_REG_CLASSES. */
1191 #define REG_CLASS_CONTENTS \
1193 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1194 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1195 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1196 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1197 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1198 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1199 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1200 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1201 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1202 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1203 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1204 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1205 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1206 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1207 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1208 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1209 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1210 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1211 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1212 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1213 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1216 /* The same information, inverted:
1217 Return the class number of the smallest class containing
1218 reg number REGNO. This could be a conditional expression
1219 or could index an array. */
1221 #define REGNO_REG_CLASS(REGNO) \
1222 ((REGNO) == 0 ? GENERAL_REGS \
1223 : (REGNO) < 32 ? BASE_REGS \
1224 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1225 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1226 : (REGNO) == CR0_REGNO ? CR0_REGS \
1227 : CR_REGNO_P (REGNO) ? CR_REGS \
1228 : (REGNO) == MQ_REGNO ? MQ_REGS \
1229 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1230 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1231 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1232 : (REGNO) == XER_REGNO ? XER_REGS \
1233 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1234 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1235 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1236 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1239 /* The class value for index registers, and the one for base regs. */
1240 #define INDEX_REG_CLASS GENERAL_REGS
1241 #define BASE_REG_CLASS BASE_REGS
1243 /* Get reg_class from a letter such as appears in the machine description. */
1245 #define REG_CLASS_FROM_LETTER(C) \
1246 ((C) == 'f' ? FLOAT_REGS \
1247 : (C) == 'b' ? BASE_REGS \
1248 : (C) == 'h' ? SPECIAL_REGS \
1249 : (C) == 'q' ? MQ_REGS \
1250 : (C) == 'c' ? CTR_REGS \
1251 : (C) == 'l' ? LINK_REGS \
1252 : (C) == 'v' ? ALTIVEC_REGS \
1253 : (C) == 'x' ? CR0_REGS \
1254 : (C) == 'y' ? CR_REGS \
1255 : (C) == 'z' ? XER_REGS \
1258 /* The letters I, J, K, L, M, N, and P in a register constraint string
1259 can be used to stand for particular ranges of immediate operands.
1260 This macro defines what the ranges are.
1261 C is the letter, and VALUE is a constant value.
1262 Return 1 if VALUE is in the range specified by C.
1264 `I' is a signed 16-bit constant
1265 `J' is a constant with only the high-order 16 bits nonzero
1266 `K' is a constant with only the low-order 16 bits nonzero
1267 `L' is a signed 16-bit constant shifted left 16 bits
1268 `M' is a constant that is greater than 31
1269 `N' is a positive constant that is an exact power of two
1270 `O' is the constant zero
1271 `P' is a constant whose negation is a signed 16-bit constant */
1273 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1274 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1275 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1276 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1277 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1278 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1279 : (C) == 'M' ? (VALUE) > 31 \
1280 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1281 : (C) == 'O' ? (VALUE) == 0 \
1282 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1285 /* Similar, but for floating constants, and defining letters G and H.
1286 Here VALUE is the CONST_DOUBLE rtx itself.
1288 We flag for special constants when we can copy the constant into
1289 a general register in two insns for DF/DI and one insn for SF.
1291 'H' is used for DI/DF constants that take 3 insns. */
1293 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1294 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1295 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1296 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1299 /* Optional extra constraints for this machine.
1301 'Q' means that is a memory operand that is just an offset from a reg.
1302 'R' is for AIX TOC entries.
1303 'S' is a constant that can be placed into a 64-bit mask operand
1304 'T' is a constant that can be placed into a 32-bit mask operand
1305 'U' is for V.4 small data references.
1306 'W' is a vector constant that can be easily generated (no mem refs).
1307 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1309 #define EXTRA_CONSTRAINT(OP, C) \
1310 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1311 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1312 : (C) == 'S' ? mask64_operand (OP, DImode) \
1313 : (C) == 'T' ? mask_operand (OP, SImode) \
1314 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1315 && small_data_operand (OP, GET_MODE (OP))) \
1316 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1317 && (fixed_regs[CR0_REGNO] \
1318 || !logical_operand (OP, DImode)) \
1319 && !mask64_operand (OP, DImode)) \
1320 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1323 /* Given an rtx X being reloaded into a reg required to be
1324 in class CLASS, return the class of reg to actually use.
1325 In general this is just CLASS; but on some machines
1326 in some cases it is preferable to use a more restrictive class.
1328 On the RS/6000, we have to return NO_REGS when we want to reload a
1329 floating-point CONST_DOUBLE to force it to be copied to memory.
1331 We also don't want to reload integer values into floating-point
1332 registers if we can at all help it. In fact, this can
1333 cause reload to abort, if it tries to generate a reload of CTR
1334 into a FP register and discovers it doesn't have the memory location
1337 ??? Would it be a good idea to have reload do the converse, that is
1338 try to reload floating modes into FP registers if possible?
1341 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1342 (((GET_CODE (X) == CONST_DOUBLE \
1343 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1345 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1346 && (CLASS) == NON_SPECIAL_REGS) \
1350 /* Return the register class of a scratch register needed to copy IN into
1351 or out of a register in CLASS in MODE. If it can be done directly,
1352 NO_REGS is returned. */
1354 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1355 secondary_reload_class (CLASS, MODE, IN)
1357 /* If we are copying between FP or AltiVec registers and anything
1358 else, we need a memory location. */
1360 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1361 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1362 || (CLASS2) == FLOAT_REGS \
1363 || (CLASS1) == ALTIVEC_REGS \
1364 || (CLASS2) == ALTIVEC_REGS))
1366 /* Return the maximum number of consecutive registers
1367 needed to represent mode MODE in a register of class CLASS.
1369 On RS/6000, this is the size of MODE in words,
1370 except in the FP regs, where a single reg is enough for two words. */
1371 #define CLASS_MAX_NREGS(CLASS, MODE) \
1372 (((CLASS) == FLOAT_REGS) \
1373 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1374 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1377 /* Return a class of registers that cannot change FROM mode to TO mode. */
1379 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1380 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1381 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1382 : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \
1383 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1386 /* Stack layout; function entry, exit and calling. */
1388 /* Enumeration to give which calling sequence to use. */
1391 ABI_AIX, /* IBM's AIX */
1392 ABI_V4, /* System V.4/eabi */
1393 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1396 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1398 /* Structure used to define the rs6000 stack */
1399 typedef struct rs6000_stack {
1400 int first_gp_reg_save; /* first callee saved GP register used */
1401 int first_fp_reg_save; /* first callee saved FP register used */
1402 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1403 int lr_save_p; /* true if the link reg needs to be saved */
1404 int cr_save_p; /* true if the CR reg needs to be saved */
1405 unsigned int vrsave_mask; /* mask of vec registers to save */
1406 int toc_save_p; /* true if the TOC needs to be saved */
1407 int push_p; /* true if we need to allocate stack space */
1408 int calls_p; /* true if the function makes any calls */
1409 enum rs6000_abi abi; /* which ABI to use */
1410 int gp_save_offset; /* offset to save GP regs from initial SP */
1411 int fp_save_offset; /* offset to save FP regs from initial SP */
1412 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
1413 int lr_save_offset; /* offset to save LR from initial SP */
1414 int cr_save_offset; /* offset to save CR from initial SP */
1415 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1416 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
1417 int toc_save_offset; /* offset to save the TOC pointer */
1418 int varargs_save_offset; /* offset to save the varargs registers */
1419 int ehrd_offset; /* offset to EH return data */
1420 int reg_size; /* register size (4 or 8) */
1421 int varargs_size; /* size to hold V.4 args passed in regs */
1422 int vars_size; /* variable save area size */
1423 int parm_size; /* outgoing parameter size */
1424 int save_size; /* save area size */
1425 int fixed_size; /* fixed size of stack frame */
1426 int gp_size; /* size of saved GP registers */
1427 int fp_size; /* size of saved FP registers */
1428 int altivec_size; /* size of saved AltiVec registers */
1429 int cr_size; /* size to hold CR if not in save_size */
1430 int lr_size; /* size to hold LR if not in save_size */
1431 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1432 int altivec_padding_size; /* size of altivec alignment padding if
1434 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
1435 int spe_padding_size;
1436 int toc_size; /* size to hold TOC if not in save_size */
1437 int total_size; /* total bytes allocated for stack */
1438 int spe_64bit_regs_used;
1441 /* Define this if pushing a word on the stack
1442 makes the stack pointer a smaller address. */
1443 #define STACK_GROWS_DOWNWARD
1445 /* Define this if the nominal address of the stack frame
1446 is at the high-address end of the local variables;
1447 that is, each additional local variable allocated
1448 goes at a more negative offset in the frame.
1450 On the RS/6000, we grow upwards, from the area after the outgoing
1452 /* #define FRAME_GROWS_DOWNWARD */
1454 /* Size of the outgoing register save area */
1455 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1456 || DEFAULT_ABI == ABI_DARWIN) \
1457 ? (TARGET_64BIT ? 64 : 32) \
1460 /* Size of the fixed area on the stack */
1461 #define RS6000_SAVE_AREA \
1462 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1463 << (TARGET_64BIT ? 1 : 0))
1465 /* MEM representing address to save the TOC register */
1466 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1467 plus_constant (stack_pointer_rtx, \
1468 (TARGET_32BIT ? 20 : 40)))
1470 /* Size of the V.4 varargs area if needed */
1471 #define RS6000_VARARGS_AREA 0
1473 /* Align an address */
1474 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1476 /* Size of V.4 varargs area in bytes */
1477 #define RS6000_VARARGS_SIZE \
1478 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1480 /* Offset within stack frame to start allocating local variables at.
1481 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1482 first local allocated. Otherwise, it is the offset to the BEGINNING
1483 of the first local allocated.
1485 On the RS/6000, the frame pointer is the same as the stack pointer,
1486 except for dynamic allocations. So we start after the fixed area and
1487 outgoing parameter area. */
1489 #define STARTING_FRAME_OFFSET \
1490 (RS6000_ALIGN (current_function_outgoing_args_size, \
1491 TARGET_ALTIVEC ? 16 : 8) \
1492 + RS6000_VARARGS_AREA \
1495 /* Offset from the stack pointer register to an item dynamically
1496 allocated on the stack, e.g., by `alloca'.
1498 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1499 length of the outgoing arguments. The default is correct for most
1500 machines. See `function.c' for details. */
1501 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1502 (RS6000_ALIGN (current_function_outgoing_args_size, \
1503 TARGET_ALTIVEC ? 16 : 8) \
1504 + (STACK_POINTER_OFFSET))
1506 /* If we generate an insn to push BYTES bytes,
1507 this says how many the stack pointer really advances by.
1508 On RS/6000, don't define this because there are no push insns. */
1509 /* #define PUSH_ROUNDING(BYTES) */
1511 /* Offset of first parameter from the argument pointer register value.
1512 On the RS/6000, we define the argument pointer to the start of the fixed
1514 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1516 /* Offset from the argument pointer register value to the top of
1517 stack. This is different from FIRST_PARM_OFFSET because of the
1518 register save area. */
1519 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1521 /* Define this if stack space is still allocated for a parameter passed
1522 in a register. The value is the number of bytes allocated to this
1524 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1526 /* Define this if the above stack space is to be considered part of the
1527 space allocated by the caller. */
1528 #define OUTGOING_REG_PARM_STACK_SPACE
1530 /* This is the difference between the logical top of stack and the actual sp.
1532 For the RS/6000, sp points past the fixed area. */
1533 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1535 /* Define this if the maximum size of all the outgoing args is to be
1536 accumulated and pushed during the prologue. The amount can be
1537 found in the variable current_function_outgoing_args_size. */
1538 #define ACCUMULATE_OUTGOING_ARGS 1
1540 /* Value is the number of bytes of arguments automatically
1541 popped when returning from a subroutine call.
1542 FUNDECL is the declaration node of the function (as a tree),
1543 FUNTYPE is the data type of the function (as a tree),
1544 or for a library call it is an identifier node for the subroutine name.
1545 SIZE is the number of bytes of arguments passed on the stack. */
1547 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1549 /* Define how to find the value returned by a function.
1550 VALTYPE is the data type of the value (as a tree).
1551 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1552 otherwise, FUNC is 0.
1554 On the SPE, both FPs and vectors are returned in r3.
1556 On RS/6000 an integer value is in r3 and a floating-point value is in
1557 fp1, unless -msoft-float. */
1559 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1560 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1561 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1562 || POINTER_TYPE_P (VALTYPE) \
1563 ? word_mode : TYPE_MODE (VALTYPE), \
1564 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1565 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1566 : TREE_CODE (VALTYPE) == REAL_TYPE \
1567 && TARGET_SPE_ABI && !TARGET_FPRS \
1569 : TREE_CODE (VALTYPE) == REAL_TYPE \
1570 && TARGET_HARD_FLOAT && TARGET_FPRS \
1571 ? FP_ARG_RETURN : GP_ARG_RETURN)
1573 /* Define how to find the value returned by a library function
1574 assuming the value has mode MODE. */
1576 #define LIBCALL_VALUE(MODE) \
1577 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1578 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1579 && TARGET_HARD_FLOAT && TARGET_FPRS \
1580 ? FP_ARG_RETURN : GP_ARG_RETURN)
1582 /* The AIX ABI for the RS/6000 specifies that all structures are
1583 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1584 specifies that structures <= 8 bytes are returned in r3/r4, but a
1585 draft put them in memory, and GCC used to implement the draft
1586 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1587 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1588 compatibility can change DRAFT_V4_STRUCT_RET to override the
1589 default, and -m switches get the final word. See
1590 rs6000_override_options for more details.
1592 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
1593 long double support is enabled. These values are returned in memory.
1595 int_size_in_bytes returns -1 for variable size objects, which go in
1596 memory always. The cast to unsigned makes -1 > 8. */
1598 #define RETURN_IN_MEMORY(TYPE) \
1599 ((AGGREGATE_TYPE_P (TYPE) \
1600 && (TARGET_AIX_STRUCT_RET \
1601 || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \
1602 || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode))
1604 /* DRAFT_V4_STRUCT_RET defaults off. */
1605 #define DRAFT_V4_STRUCT_RET 0
1607 /* Let RETURN_IN_MEMORY control what happens. */
1608 #define DEFAULT_PCC_STRUCT_RETURN 0
1610 /* Mode of stack savearea.
1611 FUNCTION is VOIDmode because calling convention maintains SP.
1612 BLOCK needs Pmode for SP.
1613 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1614 #define STACK_SAVEAREA_MODE(LEVEL) \
1615 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1616 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1618 /* Minimum and maximum general purpose registers used to hold arguments. */
1619 #define GP_ARG_MIN_REG 3
1620 #define GP_ARG_MAX_REG 10
1621 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1623 /* Minimum and maximum floating point registers used to hold arguments. */
1624 #define FP_ARG_MIN_REG 33
1625 #define FP_ARG_AIX_MAX_REG 45
1626 #define FP_ARG_V4_MAX_REG 40
1627 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1628 || DEFAULT_ABI == ABI_DARWIN) \
1629 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1630 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1632 /* Minimum and maximum AltiVec registers used to hold arguments. */
1633 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1634 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1635 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1637 /* Return registers */
1638 #define GP_ARG_RETURN GP_ARG_MIN_REG
1639 #define FP_ARG_RETURN FP_ARG_MIN_REG
1640 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1642 /* Flags for the call/call_value rtl operations set up by function_arg */
1643 #define CALL_NORMAL 0x00000000 /* no special processing */
1644 /* Bits in 0x00000001 are unused. */
1645 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1646 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1647 #define CALL_LONG 0x00000008 /* always call indirect */
1649 /* 1 if N is a possible register number for a function value
1650 as seen by the caller.
1652 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1653 #define FUNCTION_VALUE_REGNO_P(N) \
1654 ((N) == GP_ARG_RETURN \
1655 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1656 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
1658 /* 1 if N is a possible register number for function argument passing.
1659 On RS/6000, these are r3-r10 and fp1-fp13.
1660 On AltiVec, v2 - v13 are used for passing vectors. */
1661 #define FUNCTION_ARG_REGNO_P(N) \
1662 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1663 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1664 && TARGET_ALTIVEC) \
1665 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1666 && TARGET_HARD_FLOAT))
1668 /* A C structure for machine-specific, per-function data.
1669 This is added to the cfun structure. */
1670 typedef struct machine_function GTY(())
1672 /* Whether a System V.4 varargs area was created. */
1674 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1675 int ra_needs_full_frame;
1676 /* Whether the instruction chain has been scanned already. */
1677 int insn_chain_scanned_p;
1680 /* Define a data type for recording info about an argument list
1681 during the scan of that argument list. This data type should
1682 hold all necessary information about the function itself
1683 and about the args processed so far, enough to enable macros
1684 such as FUNCTION_ARG to determine where the next arg should go.
1686 On the RS/6000, this is a structure. The first element is the number of
1687 total argument words, the second is used to store the next
1688 floating-point register number, and the third says how many more args we
1689 have prototype types for.
1691 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1692 the next available GP register, `fregno' is the next available FP
1693 register, and `words' is the number of words used on the stack.
1695 The varargs/stdarg support requires that this structure's size
1696 be a multiple of sizeof(int). */
1698 typedef struct rs6000_args
1700 int words; /* # words used for passing GP registers */
1701 int fregno; /* next available FP register */
1702 int vregno; /* next available AltiVec register */
1703 int nargs_prototype; /* # args left in the current prototype */
1704 int orig_nargs; /* Original value of nargs_prototype */
1705 int prototype; /* Whether a prototype was defined */
1706 int call_cookie; /* Do special things for this call */
1707 int sysv_gregno; /* next available GP register */
1710 /* Define intermediate macro to compute the size (in registers) of an argument
1713 #define RS6000_ARG_SIZE(MODE, TYPE) \
1714 ((MODE) != BLKmode \
1715 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1716 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1718 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1719 for a call to a function whose data type is FNTYPE.
1720 For a library call, FNTYPE is 0. */
1722 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1723 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1725 /* Similar, but when scanning the definition of a procedure. We always
1726 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1728 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1729 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1731 /* Update the data in CUM to advance over an argument
1732 of mode MODE and data type TYPE.
1733 (TYPE is null for libcalls where that information may not be available.) */
1735 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1736 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1738 /* Nonzero if we can use a floating-point register to pass this arg. */
1739 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1740 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1741 && (CUM).fregno <= FP_ARG_MAX_REG \
1742 && TARGET_HARD_FLOAT && TARGET_FPRS)
1744 /* Nonzero if we can use an AltiVec register to pass this arg. */
1745 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1746 (ALTIVEC_VECTOR_MODE (MODE) \
1747 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1748 && TARGET_ALTIVEC_ABI)
1750 /* Determine where to put an argument to a function.
1751 Value is zero to push the argument on the stack,
1752 or a hard register in which to store the argument.
1754 MODE is the argument's machine mode.
1755 TYPE is the data type of the argument (as a tree).
1756 This is null for libcalls where that information may
1758 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1759 the preceding args and about the function being called.
1760 NAMED is nonzero if this argument is a named parameter
1761 (otherwise it is an extra parameter matching an ellipsis).
1763 On RS/6000 the first eight words of non-FP are normally in registers
1764 and the rest are pushed. The first 13 FP args are in registers.
1766 If this is floating-point and no prototype is specified, we use
1767 both an FP and integer register (or possibly FP reg and stack). Library
1768 functions (when TYPE is zero) always have the proper types for args,
1769 so we can pass the FP value just in one register. emit_library_function
1770 doesn't support EXPR_LIST anyway. */
1772 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1773 function_arg (&CUM, MODE, TYPE, NAMED)
1775 /* For an arg passed partly in registers and partly in memory,
1776 this is the number of registers used.
1777 For args passed entirely in registers or entirely in memory, zero. */
1779 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1780 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1782 /* A C expression that indicates when an argument must be passed by
1783 reference. If nonzero for an argument, a copy of that argument is
1784 made in memory and a pointer to the argument is passed instead of
1785 the argument itself. The pointer is passed in whatever way is
1786 appropriate for passing a pointer to that type. */
1788 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1789 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1791 /* If defined, a C expression which determines whether, and in which
1792 direction, to pad out an argument with extra space. The value
1793 should be of type `enum direction': either `upward' to pad above
1794 the argument, `downward' to pad below, or `none' to inhibit
1797 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1799 /* If defined, a C expression that gives the alignment boundary, in bits,
1800 of an argument with the specified mode and type. If it is not defined,
1801 PARM_BOUNDARY is used for all arguments. */
1803 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1804 function_arg_boundary (MODE, TYPE)
1806 /* Perform any needed actions needed for a function that is receiving a
1807 variable number of arguments.
1811 MODE and TYPE are the mode and type of the current parameter.
1813 PRETEND_SIZE is a variable that should be set to the amount of stack
1814 that must be pushed by the prolog to pretend that our caller pushed
1817 Normally, this macro will push all remaining incoming registers on the
1818 stack and set PRETEND_SIZE to the length of the registers pushed. */
1820 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1821 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1823 /* Define the `__builtin_va_list' type for the ABI. */
1824 #define BUILD_VA_LIST_TYPE(VALIST) \
1825 (VALIST) = rs6000_build_va_list ()
1827 /* Implement `va_start' for varargs and stdarg. */
1828 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1829 rs6000_va_start (valist, nextarg)
1831 /* Implement `va_arg'. */
1832 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1833 rs6000_va_arg (valist, type)
1835 /* For AIX, the rule is that structures are passed left-aligned in
1836 their stack slot. However, GCC does not presently do this:
1837 structures which are the same size as integer types are passed
1838 right-aligned, as if they were in fact integers. This only
1839 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1840 ABI_V4 does not use std_expand_builtin_va_arg. */
1841 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1843 /* Define this macro to be a nonzero value if the location where a function
1844 argument is passed depends on whether or not it is a named argument. */
1845 #define STRICT_ARGUMENT_NAMING 1
1847 /* Output assembler code to FILE to increment profiler label # LABELNO
1848 for profiling a function entry. */
1850 #define FUNCTION_PROFILER(FILE, LABELNO) \
1851 output_function_profiler ((FILE), (LABELNO));
1853 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1854 the stack pointer does not matter. No definition is equivalent to
1857 On the RS/6000, this is nonzero because we can restore the stack from
1858 its backpointer, which we maintain. */
1859 #define EXIT_IGNORE_STACK 1
1861 /* Define this macro as a C expression that is nonzero for registers
1862 that are used by the epilogue or the return' pattern. The stack
1863 and frame pointer registers are already be assumed to be used as
1866 #define EPILOGUE_USES(REGNO) \
1867 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1868 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1869 || (current_function_calls_eh_return \
1874 /* TRAMPOLINE_TEMPLATE deleted */
1876 /* Length in units of the trampoline for entering a nested function. */
1878 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1880 /* Emit RTL insns to initialize the variable parts of a trampoline.
1881 FNADDR is an RTX for the address of the function's pure code.
1882 CXT is an RTX for the static chain value for the function. */
1884 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1885 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1887 /* Definitions for __builtin_return_address and __builtin_frame_address.
1888 __builtin_return_address (0) should give link register (65), enable
1890 /* This should be uncommented, so that the link register is used, but
1891 currently this would result in unmatched insns and spilling fixed
1892 registers so we'll leave it for another day. When these problems are
1893 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1895 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1897 /* Number of bytes into the frame return addresses can be found. See
1898 rs6000_stack_info in rs6000.c for more information on how the different
1899 abi's store the return address. */
1900 #define RETURN_ADDRESS_OFFSET \
1901 ((DEFAULT_ABI == ABI_AIX \
1902 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1903 (DEFAULT_ABI == ABI_V4) ? 4 : \
1904 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1906 /* The current return address is in link register (65). The return address
1907 of anything farther back is accessed normally at an offset of 8 from the
1909 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1910 (rs6000_return_addr (COUNT, FRAME))
1913 /* Definitions for register eliminations.
1915 We have two registers that can be eliminated on the RS/6000. First, the
1916 frame pointer register can often be eliminated in favor of the stack
1917 pointer register. Secondly, the argument pointer register can always be
1918 eliminated; it is replaced with either the stack or frame pointer.
1920 In addition, we use the elimination mechanism to see if r30 is needed
1921 Initially we assume that it isn't. If it is, we spill it. This is done
1922 by making it an eliminable register. We replace it with itself so that
1923 if it isn't needed, then existing uses won't be modified. */
1925 /* This is an array of structures. Each structure initializes one pair
1926 of eliminable registers. The "from" register number is given first,
1927 followed by "to". Eliminations of the same "from" register are listed
1928 in order of preference. */
1929 #define ELIMINABLE_REGS \
1930 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1931 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1932 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1933 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1935 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1936 Frame pointer elimination is automatically handled.
1938 For the RS/6000, if frame pointer elimination is being done, we would like
1939 to convert ap into fp, not sp.
1941 We need r30 if -mminimal-toc was specified, and there are constant pool
1944 #define CAN_ELIMINATE(FROM, TO) \
1945 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1946 ? ! frame_pointer_needed \
1947 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1948 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1951 /* Define the offset between two registers, one to be eliminated, and the other
1952 its replacement, at the start of a routine. */
1953 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1955 rs6000_stack_t *info = rs6000_stack_info (); \
1957 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1958 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1959 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1960 (OFFSET) = info->total_size; \
1961 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1962 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1963 else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \
1969 /* Addressing modes, and classification of registers for them. */
1971 #define HAVE_PRE_DECREMENT 1
1972 #define HAVE_PRE_INCREMENT 1
1974 /* Macros to check register numbers against specific register classes. */
1976 /* These assume that REGNO is a hard or pseudo reg number.
1977 They give nonzero only if REGNO is a hard reg of the suitable class
1978 or a pseudo reg currently allocated to a suitable hard reg.
1979 Since they use reg_renumber, they are safe only once reg_renumber
1980 has been allocated, which happens in local-alloc.c. */
1982 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1983 ((REGNO) < FIRST_PSEUDO_REGISTER \
1984 ? (REGNO) <= 31 || (REGNO) == 67 \
1985 : (reg_renumber[REGNO] >= 0 \
1986 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1988 #define REGNO_OK_FOR_BASE_P(REGNO) \
1989 ((REGNO) < FIRST_PSEUDO_REGISTER \
1990 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1991 : (reg_renumber[REGNO] > 0 \
1992 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1994 /* Maximum number of registers that can appear in a valid memory address. */
1996 #define MAX_REGS_PER_ADDRESS 2
1998 /* Recognize any constant value that is a valid address. */
2000 #define CONSTANT_ADDRESS_P(X) \
2001 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2002 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2003 || GET_CODE (X) == HIGH)
2005 /* Nonzero if the constant value X is a legitimate general operand.
2006 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2008 On the RS/6000, all integer constants are acceptable, most won't be valid
2009 for particular insns, though. Only easy FP constants are
2012 #define LEGITIMATE_CONSTANT_P(X) \
2013 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
2014 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
2015 || easy_fp_constant (X, GET_MODE (X)))
2017 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2018 and check its validity for a certain class.
2019 We have two alternate definitions for each of them.
2020 The usual definition accepts all pseudo regs; the other rejects
2021 them unless they have been allocated suitable hard regs.
2022 The symbol REG_OK_STRICT causes the latter definition to be used.
2024 Most source files want to accept pseudo regs in the hope that
2025 they will get allocated to the class that the insn wants them to be in.
2026 Source files for reload pass need to be strict.
2027 After reload, it makes no difference, since pseudo regs have
2028 been eliminated by then. */
2030 #ifdef REG_OK_STRICT
2031 # define REG_OK_STRICT_FLAG 1
2033 # define REG_OK_STRICT_FLAG 0
2036 /* Nonzero if X is a hard reg that can be used as an index
2037 or if it is a pseudo reg in the non-strict case. */
2038 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2040 && (REGNO (X) <= 31 \
2041 || REGNO (X) == ARG_POINTER_REGNUM \
2042 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2043 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2045 /* Nonzero if X is a hard reg that can be used as a base reg
2046 or if it is a pseudo reg in the non-strict case. */
2047 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2048 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2050 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2051 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2053 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2054 that is a valid memory address for an instruction.
2055 The MODE argument is the machine mode for the MEM expression
2056 that wants to use this address.
2058 On the RS/6000, there are four valid address: a SYMBOL_REF that
2059 refers to a constant pool entry of an address (or the sum of it
2060 plus a constant), a short (16-bit signed) constant plus a register,
2061 the sum of two registers, or a register indirect, possibly with an
2062 auto-increment. For DFmode and DImode with a constant plus register,
2063 we must ensure that both words are addressable or PowerPC64 with offset
2066 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2067 32-bit DImode, TImode), indexed addressing cannot be used because
2068 adjacent memory cells are accessed by adding word-sized offsets
2069 during assembly output. */
2071 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
2073 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
2075 /* SPE offset addressing is limited to 5-bits worth of double words. */
2076 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2078 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
2080 && GET_CODE (X) == PLUS \
2081 && GET_CODE (XEXP (X, 0)) == REG \
2082 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
2083 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
2085 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
2086 (DEFAULT_ABI == ABI_V4 \
2087 && !flag_pic && !TARGET_TOC \
2088 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
2089 && small_data_operand (X, MODE))
2091 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
2092 (GET_CODE (X) == CONST_INT \
2093 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
2095 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
2096 (GET_CODE (X) == PLUS \
2097 && GET_CODE (XEXP (X, 0)) == REG \
2098 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2099 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
2100 && (! ALTIVEC_VECTOR_MODE (MODE) \
2101 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
2102 && (! SPE_VECTOR_MODE (MODE) \
2103 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
2104 && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \
2105 && (((MODE) != DFmode && (MODE) != DImode) \
2107 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
2108 : ! (INTVAL (XEXP (X, 1)) & 3))) \
2109 && (((MODE) != TFmode && (MODE) != TImode) \
2111 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
2112 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2113 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2115 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2116 (GET_CODE (X) == PLUS \
2117 && GET_CODE (XEXP (X, 0)) == REG \
2118 && GET_CODE (XEXP (X, 1)) == REG \
2119 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2120 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2121 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2122 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2124 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2125 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2127 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2129 && (DEFAULT_ABI == ABI_AIX || ! flag_pic) \
2131 && GET_MODE_NUNITS (MODE) == 1 \
2132 && (GET_MODE_BITSIZE (MODE) <= 32 \
2133 || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \
2134 && GET_CODE (X) == LO_SUM \
2135 && GET_CODE (XEXP (X, 0)) == REG \
2136 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2137 && CONSTANT_P (XEXP (X, 1)))
2139 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2140 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2144 /* Try machine-dependent ways of modifying an illegitimate address
2145 to be legitimate. If we find one, return the new, valid address.
2146 This macro is used in only one place: `memory_address' in explow.c.
2148 OLDX is the address as it was before break_out_memory_refs was called.
2149 In some cases it is useful to look at this to decide what needs to be done.
2151 MODE and WIN are passed so that this macro can use
2152 GO_IF_LEGITIMATE_ADDRESS.
2154 It is always safe for this macro to do nothing. It exists to recognize
2155 opportunities to optimize the output.
2157 On RS/6000, first check for the sum of a register with a constant
2158 integer that is out of range. If so, generate code to add the
2159 constant with the low-order 16 bits masked to the register and force
2160 this result into another register (this can be done with `cau').
2161 Then generate an address of REG+(CONST&0xffff), allowing for the
2162 possibility of bit 16 being a one.
2164 Then check for the sum of a register and something not constant, try to
2165 load the other things into a register and return the sum. */
2167 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2168 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2169 if (result != NULL_RTX) \
2176 /* Try a machine-dependent way of reloading an illegitimate address
2177 operand. If we find one, push the reload and jump to WIN. This
2178 macro is used in only one place: `find_reloads_address' in reload.c.
2180 Implemented on rs6000 by rs6000_legitimize_reload_address.
2181 Note that (X) is evaluated twice; this is safe in current usage. */
2183 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2186 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2187 (int)(TYPE), (IND_LEVELS), &win); \
2192 /* Go to LABEL if ADDR (a legitimate address expression)
2193 has an effect that depends on the machine mode it is used for.
2195 On the RS/6000 this is true if the address is valid with a zero offset
2196 but not with an offset of four (this means it cannot be used as an
2197 address for DImode or DFmode) or is a pre-increment or decrement. Since
2198 we know it is valid, we just check for an address that is not valid with
2199 an offset of four. */
2201 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2202 { if (GET_CODE (ADDR) == PLUS \
2203 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2204 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2205 (TARGET_32BIT ? 4 : 8))) \
2207 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2209 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2211 if (GET_CODE (ADDR) == LO_SUM) \
2215 /* The register number of the register used to address a table of
2216 static data addresses in memory. In some cases this register is
2217 defined by a processor's "application binary interface" (ABI).
2218 When this macro is defined, RTL is generated for this register
2219 once, as with the stack pointer and frame pointer registers. If
2220 this macro is not defined, it is up to the machine-dependent files
2221 to allocate such a register (if necessary). */
2223 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2224 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2226 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2228 /* Define this macro if the register defined by
2229 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2230 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2232 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2234 /* By generating position-independent code, when two different
2235 programs (A and B) share a common library (libC.a), the text of
2236 the library can be shared whether or not the library is linked at
2237 the same address for both programs. In some of these
2238 environments, position-independent code requires not only the use
2239 of different addressing modes, but also special code to enable the
2240 use of these addressing modes.
2242 The `FINALIZE_PIC' macro serves as a hook to emit these special
2243 codes once the function is being compiled into assembly code, but
2244 not before. (It is not done before, because in the case of
2245 compiling an inline function, it would lead to multiple PIC
2246 prologues being included in functions which used inline functions
2247 and were compiled to assembly language.) */
2249 /* #define FINALIZE_PIC */
2251 /* A C expression that is nonzero if X is a legitimate immediate
2252 operand on the target machine when generating position independent
2253 code. You can assume that X satisfies `CONSTANT_P', so you need
2254 not check this. You can also assume FLAG_PIC is true, so you need
2255 not check it either. You need not define this macro if all
2256 constants (including `SYMBOL_REF') can be immediate operands when
2257 generating position independent code. */
2259 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2261 /* In rare cases, correct code generation requires extra machine
2262 dependent processing between the second jump optimization pass and
2263 delayed branch scheduling. On those machines, define this macro
2264 as a C statement to act on the code starting at INSN. */
2266 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2269 /* Define this if some processing needs to be done immediately before
2270 emitting code for an insn. */
2272 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2274 /* Specify the machine mode that this machine uses
2275 for the index in the tablejump instruction. */
2276 #define CASE_VECTOR_MODE SImode
2278 /* Define as C expression which evaluates to nonzero if the tablejump
2279 instruction expects the table to contain offsets from the address of the
2281 Do not define this if the table should contain absolute addresses. */
2282 #define CASE_VECTOR_PC_RELATIVE 1
2284 /* Define this as 1 if `char' should by default be signed; else as 0. */
2285 #define DEFAULT_SIGNED_CHAR 0
2287 /* This flag, if defined, says the same insns that convert to a signed fixnum
2288 also convert validly to an unsigned one. */
2290 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2292 /* Max number of bytes we can move from memory to memory
2293 in one reasonably fast instruction. */
2294 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2295 #define MAX_MOVE_MAX 8
2297 /* Nonzero if access to memory by bytes is no faster than for words.
2298 Also nonzero if doing byte operations (specifically shifts) in registers
2300 #define SLOW_BYTE_ACCESS 1
2302 /* Define if operations between registers always perform the operation
2303 on the full register even if a narrower mode is specified. */
2304 #define WORD_REGISTER_OPERATIONS
2306 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2307 will either zero-extend or sign-extend. The value of this macro should
2308 be the code that says which one of the two operations is implicitly
2309 done, NIL if none. */
2310 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2312 /* Define if loading short immediate values into registers sign extends. */
2313 #define SHORT_IMMEDIATES_SIGN_EXTEND
2315 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2316 is done just by pretending it is already truncated. */
2317 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2319 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2320 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2321 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2323 /* The CTZ patterns return -1 for input of zero. */
2324 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2326 /* Specify the machine mode that pointers have.
2327 After generation of rtl, the compiler makes no further distinction
2328 between pointers and any other objects of this machine mode. */
2329 #define Pmode (TARGET_32BIT ? SImode : DImode)
2331 /* Mode of a function address in a call instruction (for indexing purposes).
2332 Doesn't matter on RS/6000. */
2333 #define FUNCTION_MODE SImode
2335 /* Define this if addresses of constant functions
2336 shouldn't be put through pseudo regs where they can be cse'd.
2337 Desirable on machines where ordinary constants are expensive
2338 but a CALL with constant address is cheap. */
2339 #define NO_FUNCTION_CSE
2341 /* Define this to be nonzero if shift instructions ignore all but the low-order
2344 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2345 have been dropped from the PowerPC architecture. */
2347 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2349 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2350 should be adjusted to reflect any required changes. This macro is used when
2351 there is some systematic length adjustment required that would be difficult
2352 to express in the length attribute. */
2354 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2356 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2357 COMPARE, return the mode to be used for the comparison. For
2358 floating-point, CCFPmode should be used. CCUNSmode should be used
2359 for unsigned comparisons. CCEQmode should be used when we are
2360 doing an inequality comparison on the result of a
2361 comparison. CCmode should be used in all other cases. */
2363 #define SELECT_CC_MODE(OP,X,Y) \
2364 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2365 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2366 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2367 ? CCEQmode : CCmode))
2369 /* Define the information needed to generate branch and scc insns. This is
2370 stored from the compare operation. Note that we can't use "rtx" here
2371 since it hasn't been defined! */
2373 extern GTY(()) rtx rs6000_compare_op0;
2374 extern GTY(()) rtx rs6000_compare_op1;
2375 extern int rs6000_compare_fp_p;
2377 /* Control the assembler format that we output. */
2379 /* A C string constant describing how to begin a comment in the target
2380 assembler language. The compiler assumes that the comment will end at
2381 the end of the line. */
2382 #define ASM_COMMENT_START " #"
2384 /* Implicit library calls should use memcpy, not bcopy, etc. */
2386 #define TARGET_MEM_FUNCTIONS
2388 /* Flag to say the TOC is initialized */
2389 extern int toc_initialized;
2391 /* Macro to output a special constant pool entry. Go to WIN if we output
2392 it. Otherwise, it is written the usual way.
2394 On the RS/6000, toc entries are handled this way. */
2396 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2397 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2399 output_toc (FILE, X, LABELNO, MODE); \
2404 #ifdef HAVE_GAS_WEAK
2405 #define RS6000_WEAK 1
2407 #define RS6000_WEAK 0
2411 /* Used in lieu of ASM_WEAKEN_LABEL. */
2412 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2415 fputs ("\t.weak\t", (FILE)); \
2416 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2417 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2418 && DEFAULT_ABI == ABI_AIX) \
2421 fputs ("[DS]", (FILE)); \
2422 fputs ("\n\t.weak\t.", (FILE)); \
2423 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2425 fputc ('\n', (FILE)); \
2428 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2429 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2430 && DEFAULT_ABI == ABI_AIX) \
2432 fputs ("\t.set\t.", (FILE)); \
2433 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2434 fputs (",.", (FILE)); \
2435 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2436 fputc ('\n', (FILE)); \
2443 /* This implements the `alias' attribute. */
2444 #undef ASM_OUTPUT_DEF_FROM_DECLS
2445 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2448 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2449 const char *name = IDENTIFIER_POINTER (TARGET); \
2450 if (TREE_CODE (DECL) == FUNCTION_DECL \
2451 && DEFAULT_ABI == ABI_AIX) \
2453 if (TREE_PUBLIC (DECL)) \
2455 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2457 fputs ("\t.globl\t.", FILE); \
2458 RS6000_OUTPUT_BASENAME (FILE, alias); \
2459 putc ('\n', FILE); \
2462 else if (TARGET_XCOFF) \
2464 fputs ("\t.lglobl\t.", FILE); \
2465 RS6000_OUTPUT_BASENAME (FILE, alias); \
2466 putc ('\n', FILE); \
2468 fputs ("\t.set\t.", FILE); \
2469 RS6000_OUTPUT_BASENAME (FILE, alias); \
2470 fputs (",.", FILE); \
2471 RS6000_OUTPUT_BASENAME (FILE, name); \
2472 fputc ('\n', FILE); \
2474 ASM_OUTPUT_DEF (FILE, alias, name); \
2478 /* Output to assembler file text saying following lines
2479 may contain character constants, extra white space, comments, etc. */
2481 #define ASM_APP_ON ""
2483 /* Output to assembler file text saying following lines
2484 no longer contain unusual constructs. */
2486 #define ASM_APP_OFF ""
2488 /* How to refer to registers in assembler output.
2489 This sequence is indexed by compiler's hard-register-number (see above). */
2491 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2493 #define REGISTER_NAMES \
2495 &rs6000_reg_names[ 0][0], /* r0 */ \
2496 &rs6000_reg_names[ 1][0], /* r1 */ \
2497 &rs6000_reg_names[ 2][0], /* r2 */ \
2498 &rs6000_reg_names[ 3][0], /* r3 */ \
2499 &rs6000_reg_names[ 4][0], /* r4 */ \
2500 &rs6000_reg_names[ 5][0], /* r5 */ \
2501 &rs6000_reg_names[ 6][0], /* r6 */ \
2502 &rs6000_reg_names[ 7][0], /* r7 */ \
2503 &rs6000_reg_names[ 8][0], /* r8 */ \
2504 &rs6000_reg_names[ 9][0], /* r9 */ \
2505 &rs6000_reg_names[10][0], /* r10 */ \
2506 &rs6000_reg_names[11][0], /* r11 */ \
2507 &rs6000_reg_names[12][0], /* r12 */ \
2508 &rs6000_reg_names[13][0], /* r13 */ \
2509 &rs6000_reg_names[14][0], /* r14 */ \
2510 &rs6000_reg_names[15][0], /* r15 */ \
2511 &rs6000_reg_names[16][0], /* r16 */ \
2512 &rs6000_reg_names[17][0], /* r17 */ \
2513 &rs6000_reg_names[18][0], /* r18 */ \
2514 &rs6000_reg_names[19][0], /* r19 */ \
2515 &rs6000_reg_names[20][0], /* r20 */ \
2516 &rs6000_reg_names[21][0], /* r21 */ \
2517 &rs6000_reg_names[22][0], /* r22 */ \
2518 &rs6000_reg_names[23][0], /* r23 */ \
2519 &rs6000_reg_names[24][0], /* r24 */ \
2520 &rs6000_reg_names[25][0], /* r25 */ \
2521 &rs6000_reg_names[26][0], /* r26 */ \
2522 &rs6000_reg_names[27][0], /* r27 */ \
2523 &rs6000_reg_names[28][0], /* r28 */ \
2524 &rs6000_reg_names[29][0], /* r29 */ \
2525 &rs6000_reg_names[30][0], /* r30 */ \
2526 &rs6000_reg_names[31][0], /* r31 */ \
2528 &rs6000_reg_names[32][0], /* fr0 */ \
2529 &rs6000_reg_names[33][0], /* fr1 */ \
2530 &rs6000_reg_names[34][0], /* fr2 */ \
2531 &rs6000_reg_names[35][0], /* fr3 */ \
2532 &rs6000_reg_names[36][0], /* fr4 */ \
2533 &rs6000_reg_names[37][0], /* fr5 */ \
2534 &rs6000_reg_names[38][0], /* fr6 */ \
2535 &rs6000_reg_names[39][0], /* fr7 */ \
2536 &rs6000_reg_names[40][0], /* fr8 */ \
2537 &rs6000_reg_names[41][0], /* fr9 */ \
2538 &rs6000_reg_names[42][0], /* fr10 */ \
2539 &rs6000_reg_names[43][0], /* fr11 */ \
2540 &rs6000_reg_names[44][0], /* fr12 */ \
2541 &rs6000_reg_names[45][0], /* fr13 */ \
2542 &rs6000_reg_names[46][0], /* fr14 */ \
2543 &rs6000_reg_names[47][0], /* fr15 */ \
2544 &rs6000_reg_names[48][0], /* fr16 */ \
2545 &rs6000_reg_names[49][0], /* fr17 */ \
2546 &rs6000_reg_names[50][0], /* fr18 */ \
2547 &rs6000_reg_names[51][0], /* fr19 */ \
2548 &rs6000_reg_names[52][0], /* fr20 */ \
2549 &rs6000_reg_names[53][0], /* fr21 */ \
2550 &rs6000_reg_names[54][0], /* fr22 */ \
2551 &rs6000_reg_names[55][0], /* fr23 */ \
2552 &rs6000_reg_names[56][0], /* fr24 */ \
2553 &rs6000_reg_names[57][0], /* fr25 */ \
2554 &rs6000_reg_names[58][0], /* fr26 */ \
2555 &rs6000_reg_names[59][0], /* fr27 */ \
2556 &rs6000_reg_names[60][0], /* fr28 */ \
2557 &rs6000_reg_names[61][0], /* fr29 */ \
2558 &rs6000_reg_names[62][0], /* fr30 */ \
2559 &rs6000_reg_names[63][0], /* fr31 */ \
2561 &rs6000_reg_names[64][0], /* mq */ \
2562 &rs6000_reg_names[65][0], /* lr */ \
2563 &rs6000_reg_names[66][0], /* ctr */ \
2564 &rs6000_reg_names[67][0], /* ap */ \
2566 &rs6000_reg_names[68][0], /* cr0 */ \
2567 &rs6000_reg_names[69][0], /* cr1 */ \
2568 &rs6000_reg_names[70][0], /* cr2 */ \
2569 &rs6000_reg_names[71][0], /* cr3 */ \
2570 &rs6000_reg_names[72][0], /* cr4 */ \
2571 &rs6000_reg_names[73][0], /* cr5 */ \
2572 &rs6000_reg_names[74][0], /* cr6 */ \
2573 &rs6000_reg_names[75][0], /* cr7 */ \
2575 &rs6000_reg_names[76][0], /* xer */ \
2577 &rs6000_reg_names[77][0], /* v0 */ \
2578 &rs6000_reg_names[78][0], /* v1 */ \
2579 &rs6000_reg_names[79][0], /* v2 */ \
2580 &rs6000_reg_names[80][0], /* v3 */ \
2581 &rs6000_reg_names[81][0], /* v4 */ \
2582 &rs6000_reg_names[82][0], /* v5 */ \
2583 &rs6000_reg_names[83][0], /* v6 */ \
2584 &rs6000_reg_names[84][0], /* v7 */ \
2585 &rs6000_reg_names[85][0], /* v8 */ \
2586 &rs6000_reg_names[86][0], /* v9 */ \
2587 &rs6000_reg_names[87][0], /* v10 */ \
2588 &rs6000_reg_names[88][0], /* v11 */ \
2589 &rs6000_reg_names[89][0], /* v12 */ \
2590 &rs6000_reg_names[90][0], /* v13 */ \
2591 &rs6000_reg_names[91][0], /* v14 */ \
2592 &rs6000_reg_names[92][0], /* v15 */ \
2593 &rs6000_reg_names[93][0], /* v16 */ \
2594 &rs6000_reg_names[94][0], /* v17 */ \
2595 &rs6000_reg_names[95][0], /* v18 */ \
2596 &rs6000_reg_names[96][0], /* v19 */ \
2597 &rs6000_reg_names[97][0], /* v20 */ \
2598 &rs6000_reg_names[98][0], /* v21 */ \
2599 &rs6000_reg_names[99][0], /* v22 */ \
2600 &rs6000_reg_names[100][0], /* v23 */ \
2601 &rs6000_reg_names[101][0], /* v24 */ \
2602 &rs6000_reg_names[102][0], /* v25 */ \
2603 &rs6000_reg_names[103][0], /* v26 */ \
2604 &rs6000_reg_names[104][0], /* v27 */ \
2605 &rs6000_reg_names[105][0], /* v28 */ \
2606 &rs6000_reg_names[106][0], /* v29 */ \
2607 &rs6000_reg_names[107][0], /* v30 */ \
2608 &rs6000_reg_names[108][0], /* v31 */ \
2609 &rs6000_reg_names[109][0], /* vrsave */ \
2610 &rs6000_reg_names[110][0], /* vscr */ \
2611 &rs6000_reg_names[111][0], /* spe_acc */ \
2612 &rs6000_reg_names[112][0], /* spefscr */ \
2615 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2616 following for it. Switch to use the alternate names since
2617 they are more mnemonic. */
2619 #define DEBUG_REGISTER_NAMES \
2621 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2622 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2623 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2624 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2625 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2626 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2627 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2628 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2629 "mq", "lr", "ctr", "ap", \
2630 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2632 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2633 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2634 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2635 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2637 "spe_acc", "spefscr" \
2640 /* Table of additional register names to use in user input. */
2642 #define ADDITIONAL_REGISTER_NAMES \
2643 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2644 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2645 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2646 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2647 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2648 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2649 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2650 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2651 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2652 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2653 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2654 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2655 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2656 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2657 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2658 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2659 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2660 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2661 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2662 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2663 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2664 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2665 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2666 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2667 {"vrsave", 109}, {"vscr", 110}, \
2668 {"spe_acc", 111}, {"spefscr", 112}, \
2669 /* no additional names for: mq, lr, ctr, ap */ \
2670 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2671 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2672 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2674 /* Text to write out after a CALL that may be replaced by glue code by
2675 the loader. This depends on the AIX version. */
2676 #define RS6000_CALL_GLUE "cror 31,31,31"
2678 /* This is how to output an element of a case-vector that is relative. */
2680 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2681 do { char buf[100]; \
2682 fputs ("\t.long ", FILE); \
2683 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2684 assemble_name (FILE, buf); \
2686 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2687 assemble_name (FILE, buf); \
2688 putc ('\n', FILE); \
2691 /* This is how to output an assembler line
2692 that says to advance the location counter
2693 to a multiple of 2**LOG bytes. */
2695 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2697 fprintf (FILE, "\t.align %d\n", (LOG))
2699 /* Pick up the return address upon entry to a procedure. Used for
2700 dwarf2 unwind information. This also enables the table driven
2703 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2704 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2706 /* Describe how we implement __builtin_eh_return. */
2707 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2708 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2710 /* Print operand X (an rtx) in assembler syntax to file FILE.
2711 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2712 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2714 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2716 /* Define which CODE values are valid. */
2718 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2721 /* Print a memory address as an operand to reference that memory location. */
2723 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2725 /* Define the codes that are matched by predicates in rs6000.c. */
2727 #define PREDICATE_CODES \
2728 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2729 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2730 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2731 LABEL_REF, SUBREG, REG, MEM}}, \
2732 {"short_cint_operand", {CONST_INT}}, \
2733 {"u_short_cint_operand", {CONST_INT}}, \
2734 {"non_short_cint_operand", {CONST_INT}}, \
2735 {"exact_log2_cint_operand", {CONST_INT}}, \
2736 {"gpc_reg_operand", {SUBREG, REG}}, \
2737 {"cc_reg_operand", {SUBREG, REG}}, \
2738 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2739 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2740 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2741 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2742 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2743 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2744 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2745 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2746 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2747 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2748 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2749 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2750 {"easy_fp_constant", {CONST_DOUBLE}}, \
2751 {"easy_vector_constant", {CONST_VECTOR}}, \
2752 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2753 {"zero_fp_constant", {CONST_DOUBLE}}, \
2754 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2755 {"lwa_operand", {SUBREG, MEM, REG}}, \
2756 {"volatile_mem_operand", {MEM}}, \
2757 {"offsettable_mem_operand", {MEM}}, \
2758 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2759 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2760 {"non_add_cint_operand", {CONST_INT}}, \
2761 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2762 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2763 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2764 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2765 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2766 {"mask_operand", {CONST_INT}}, \
2767 {"mask_operand_wrap", {CONST_INT}}, \
2768 {"mask64_operand", {CONST_INT}}, \
2769 {"mask64_2_operand", {CONST_INT}}, \
2770 {"count_register_operand", {REG}}, \
2771 {"xer_operand", {REG}}, \
2772 {"symbol_ref_operand", {SYMBOL_REF}}, \
2773 {"call_operand", {SYMBOL_REF, REG}}, \
2774 {"current_file_function_operand", {SYMBOL_REF}}, \
2775 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2776 CONST_DOUBLE, SYMBOL_REF}}, \
2777 {"load_multiple_operation", {PARALLEL}}, \
2778 {"store_multiple_operation", {PARALLEL}}, \
2779 {"vrsave_operation", {PARALLEL}}, \
2780 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2781 GT, LEU, LTU, GEU, GTU, \
2782 UNORDERED, ORDERED, \
2784 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2786 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2787 GT, LEU, LTU, GEU, GTU, \
2788 UNORDERED, ORDERED, \
2790 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2791 GT, LEU, LTU, GEU, GTU}}, \
2792 {"boolean_operator", {AND, IOR, XOR}}, \
2793 {"boolean_or_operator", {IOR, XOR}}, \
2794 {"altivec_register_operand", {REG}}, \
2795 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2797 /* uncomment for disabling the corresponding default options */
2798 /* #define MACHINE_no_sched_interblock */
2799 /* #define MACHINE_no_sched_speculative */
2800 /* #define MACHINE_no_sched_speculative_load */
2802 /* General flags. */
2803 extern int flag_pic;
2804 extern int optimize;
2805 extern int flag_expensive_optimizations;
2806 extern int frame_pointer_needed;
2808 enum rs6000_builtins
2810 /* AltiVec builtins. */
2811 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2812 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2813 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2814 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2815 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2816 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2817 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2818 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2819 ALTIVEC_BUILTIN_VADDUBM,
2820 ALTIVEC_BUILTIN_VADDUHM,
2821 ALTIVEC_BUILTIN_VADDUWM,
2822 ALTIVEC_BUILTIN_VADDFP,
2823 ALTIVEC_BUILTIN_VADDCUW,
2824 ALTIVEC_BUILTIN_VADDUBS,
2825 ALTIVEC_BUILTIN_VADDSBS,
2826 ALTIVEC_BUILTIN_VADDUHS,
2827 ALTIVEC_BUILTIN_VADDSHS,
2828 ALTIVEC_BUILTIN_VADDUWS,
2829 ALTIVEC_BUILTIN_VADDSWS,
2830 ALTIVEC_BUILTIN_VAND,
2831 ALTIVEC_BUILTIN_VANDC,
2832 ALTIVEC_BUILTIN_VAVGUB,
2833 ALTIVEC_BUILTIN_VAVGSB,
2834 ALTIVEC_BUILTIN_VAVGUH,
2835 ALTIVEC_BUILTIN_VAVGSH,
2836 ALTIVEC_BUILTIN_VAVGUW,
2837 ALTIVEC_BUILTIN_VAVGSW,
2838 ALTIVEC_BUILTIN_VCFUX,
2839 ALTIVEC_BUILTIN_VCFSX,
2840 ALTIVEC_BUILTIN_VCTSXS,
2841 ALTIVEC_BUILTIN_VCTUXS,
2842 ALTIVEC_BUILTIN_VCMPBFP,
2843 ALTIVEC_BUILTIN_VCMPEQUB,
2844 ALTIVEC_BUILTIN_VCMPEQUH,
2845 ALTIVEC_BUILTIN_VCMPEQUW,
2846 ALTIVEC_BUILTIN_VCMPEQFP,
2847 ALTIVEC_BUILTIN_VCMPGEFP,
2848 ALTIVEC_BUILTIN_VCMPGTUB,
2849 ALTIVEC_BUILTIN_VCMPGTSB,
2850 ALTIVEC_BUILTIN_VCMPGTUH,
2851 ALTIVEC_BUILTIN_VCMPGTSH,
2852 ALTIVEC_BUILTIN_VCMPGTUW,
2853 ALTIVEC_BUILTIN_VCMPGTSW,
2854 ALTIVEC_BUILTIN_VCMPGTFP,
2855 ALTIVEC_BUILTIN_VEXPTEFP,
2856 ALTIVEC_BUILTIN_VLOGEFP,
2857 ALTIVEC_BUILTIN_VMADDFP,
2858 ALTIVEC_BUILTIN_VMAXUB,
2859 ALTIVEC_BUILTIN_VMAXSB,
2860 ALTIVEC_BUILTIN_VMAXUH,
2861 ALTIVEC_BUILTIN_VMAXSH,
2862 ALTIVEC_BUILTIN_VMAXUW,
2863 ALTIVEC_BUILTIN_VMAXSW,
2864 ALTIVEC_BUILTIN_VMAXFP,
2865 ALTIVEC_BUILTIN_VMHADDSHS,
2866 ALTIVEC_BUILTIN_VMHRADDSHS,
2867 ALTIVEC_BUILTIN_VMLADDUHM,
2868 ALTIVEC_BUILTIN_VMRGHB,
2869 ALTIVEC_BUILTIN_VMRGHH,
2870 ALTIVEC_BUILTIN_VMRGHW,
2871 ALTIVEC_BUILTIN_VMRGLB,
2872 ALTIVEC_BUILTIN_VMRGLH,
2873 ALTIVEC_BUILTIN_VMRGLW,
2874 ALTIVEC_BUILTIN_VMSUMUBM,
2875 ALTIVEC_BUILTIN_VMSUMMBM,
2876 ALTIVEC_BUILTIN_VMSUMUHM,
2877 ALTIVEC_BUILTIN_VMSUMSHM,
2878 ALTIVEC_BUILTIN_VMSUMUHS,
2879 ALTIVEC_BUILTIN_VMSUMSHS,
2880 ALTIVEC_BUILTIN_VMINUB,
2881 ALTIVEC_BUILTIN_VMINSB,
2882 ALTIVEC_BUILTIN_VMINUH,
2883 ALTIVEC_BUILTIN_VMINSH,
2884 ALTIVEC_BUILTIN_VMINUW,
2885 ALTIVEC_BUILTIN_VMINSW,
2886 ALTIVEC_BUILTIN_VMINFP,
2887 ALTIVEC_BUILTIN_VMULEUB,
2888 ALTIVEC_BUILTIN_VMULESB,
2889 ALTIVEC_BUILTIN_VMULEUH,
2890 ALTIVEC_BUILTIN_VMULESH,
2891 ALTIVEC_BUILTIN_VMULOUB,
2892 ALTIVEC_BUILTIN_VMULOSB,
2893 ALTIVEC_BUILTIN_VMULOUH,
2894 ALTIVEC_BUILTIN_VMULOSH,
2895 ALTIVEC_BUILTIN_VNMSUBFP,
2896 ALTIVEC_BUILTIN_VNOR,
2897 ALTIVEC_BUILTIN_VOR,
2898 ALTIVEC_BUILTIN_VSEL_4SI,
2899 ALTIVEC_BUILTIN_VSEL_4SF,
2900 ALTIVEC_BUILTIN_VSEL_8HI,
2901 ALTIVEC_BUILTIN_VSEL_16QI,
2902 ALTIVEC_BUILTIN_VPERM_4SI,
2903 ALTIVEC_BUILTIN_VPERM_4SF,
2904 ALTIVEC_BUILTIN_VPERM_8HI,
2905 ALTIVEC_BUILTIN_VPERM_16QI,
2906 ALTIVEC_BUILTIN_VPKUHUM,
2907 ALTIVEC_BUILTIN_VPKUWUM,
2908 ALTIVEC_BUILTIN_VPKPX,
2909 ALTIVEC_BUILTIN_VPKUHSS,
2910 ALTIVEC_BUILTIN_VPKSHSS,
2911 ALTIVEC_BUILTIN_VPKUWSS,
2912 ALTIVEC_BUILTIN_VPKSWSS,
2913 ALTIVEC_BUILTIN_VPKUHUS,
2914 ALTIVEC_BUILTIN_VPKSHUS,
2915 ALTIVEC_BUILTIN_VPKUWUS,
2916 ALTIVEC_BUILTIN_VPKSWUS,
2917 ALTIVEC_BUILTIN_VREFP,
2918 ALTIVEC_BUILTIN_VRFIM,
2919 ALTIVEC_BUILTIN_VRFIN,
2920 ALTIVEC_BUILTIN_VRFIP,
2921 ALTIVEC_BUILTIN_VRFIZ,
2922 ALTIVEC_BUILTIN_VRLB,
2923 ALTIVEC_BUILTIN_VRLH,
2924 ALTIVEC_BUILTIN_VRLW,
2925 ALTIVEC_BUILTIN_VRSQRTEFP,
2926 ALTIVEC_BUILTIN_VSLB,
2927 ALTIVEC_BUILTIN_VSLH,
2928 ALTIVEC_BUILTIN_VSLW,
2929 ALTIVEC_BUILTIN_VSL,
2930 ALTIVEC_BUILTIN_VSLO,
2931 ALTIVEC_BUILTIN_VSPLTB,
2932 ALTIVEC_BUILTIN_VSPLTH,
2933 ALTIVEC_BUILTIN_VSPLTW,
2934 ALTIVEC_BUILTIN_VSPLTISB,
2935 ALTIVEC_BUILTIN_VSPLTISH,
2936 ALTIVEC_BUILTIN_VSPLTISW,
2937 ALTIVEC_BUILTIN_VSRB,
2938 ALTIVEC_BUILTIN_VSRH,
2939 ALTIVEC_BUILTIN_VSRW,
2940 ALTIVEC_BUILTIN_VSRAB,
2941 ALTIVEC_BUILTIN_VSRAH,
2942 ALTIVEC_BUILTIN_VSRAW,
2943 ALTIVEC_BUILTIN_VSR,
2944 ALTIVEC_BUILTIN_VSRO,
2945 ALTIVEC_BUILTIN_VSUBUBM,
2946 ALTIVEC_BUILTIN_VSUBUHM,
2947 ALTIVEC_BUILTIN_VSUBUWM,
2948 ALTIVEC_BUILTIN_VSUBFP,
2949 ALTIVEC_BUILTIN_VSUBCUW,
2950 ALTIVEC_BUILTIN_VSUBUBS,
2951 ALTIVEC_BUILTIN_VSUBSBS,
2952 ALTIVEC_BUILTIN_VSUBUHS,
2953 ALTIVEC_BUILTIN_VSUBSHS,
2954 ALTIVEC_BUILTIN_VSUBUWS,
2955 ALTIVEC_BUILTIN_VSUBSWS,
2956 ALTIVEC_BUILTIN_VSUM4UBS,
2957 ALTIVEC_BUILTIN_VSUM4SBS,
2958 ALTIVEC_BUILTIN_VSUM4SHS,
2959 ALTIVEC_BUILTIN_VSUM2SWS,
2960 ALTIVEC_BUILTIN_VSUMSWS,
2961 ALTIVEC_BUILTIN_VXOR,
2962 ALTIVEC_BUILTIN_VSLDOI_16QI,
2963 ALTIVEC_BUILTIN_VSLDOI_8HI,
2964 ALTIVEC_BUILTIN_VSLDOI_4SI,
2965 ALTIVEC_BUILTIN_VSLDOI_4SF,
2966 ALTIVEC_BUILTIN_VUPKHSB,
2967 ALTIVEC_BUILTIN_VUPKHPX,
2968 ALTIVEC_BUILTIN_VUPKHSH,
2969 ALTIVEC_BUILTIN_VUPKLSB,
2970 ALTIVEC_BUILTIN_VUPKLPX,
2971 ALTIVEC_BUILTIN_VUPKLSH,
2972 ALTIVEC_BUILTIN_MTVSCR,
2973 ALTIVEC_BUILTIN_MFVSCR,
2974 ALTIVEC_BUILTIN_DSSALL,
2975 ALTIVEC_BUILTIN_DSS,
2976 ALTIVEC_BUILTIN_LVSL,
2977 ALTIVEC_BUILTIN_LVSR,
2978 ALTIVEC_BUILTIN_DSTT,
2979 ALTIVEC_BUILTIN_DSTST,
2980 ALTIVEC_BUILTIN_DSTSTT,
2981 ALTIVEC_BUILTIN_DST,
2982 ALTIVEC_BUILTIN_LVEBX,
2983 ALTIVEC_BUILTIN_LVEHX,
2984 ALTIVEC_BUILTIN_LVEWX,
2985 ALTIVEC_BUILTIN_LVXL,
2986 ALTIVEC_BUILTIN_LVX,
2987 ALTIVEC_BUILTIN_STVX,
2988 ALTIVEC_BUILTIN_STVEBX,
2989 ALTIVEC_BUILTIN_STVEHX,
2990 ALTIVEC_BUILTIN_STVEWX,
2991 ALTIVEC_BUILTIN_STVXL,
2992 ALTIVEC_BUILTIN_VCMPBFP_P,
2993 ALTIVEC_BUILTIN_VCMPEQFP_P,
2994 ALTIVEC_BUILTIN_VCMPEQUB_P,
2995 ALTIVEC_BUILTIN_VCMPEQUH_P,
2996 ALTIVEC_BUILTIN_VCMPEQUW_P,
2997 ALTIVEC_BUILTIN_VCMPGEFP_P,
2998 ALTIVEC_BUILTIN_VCMPGTFP_P,
2999 ALTIVEC_BUILTIN_VCMPGTSB_P,
3000 ALTIVEC_BUILTIN_VCMPGTSH_P,
3001 ALTIVEC_BUILTIN_VCMPGTSW_P,
3002 ALTIVEC_BUILTIN_VCMPGTUB_P,
3003 ALTIVEC_BUILTIN_VCMPGTUH_P,
3004 ALTIVEC_BUILTIN_VCMPGTUW_P,
3005 ALTIVEC_BUILTIN_ABSS_V4SI,
3006 ALTIVEC_BUILTIN_ABSS_V8HI,
3007 ALTIVEC_BUILTIN_ABSS_V16QI,
3008 ALTIVEC_BUILTIN_ABS_V4SI,
3009 ALTIVEC_BUILTIN_ABS_V4SF,
3010 ALTIVEC_BUILTIN_ABS_V8HI,
3011 ALTIVEC_BUILTIN_ABS_V16QI
3013 , SPE_BUILTIN_EVADDW,
3016 SPE_BUILTIN_EVDIVWS,
3017 SPE_BUILTIN_EVDIVWU,
3019 SPE_BUILTIN_EVFSADD,
3020 SPE_BUILTIN_EVFSDIV,
3021 SPE_BUILTIN_EVFSMUL,
3022 SPE_BUILTIN_EVFSSUB,
3026 SPE_BUILTIN_EVLHHESPLATX,
3027 SPE_BUILTIN_EVLHHOSSPLATX,
3028 SPE_BUILTIN_EVLHHOUSPLATX,
3029 SPE_BUILTIN_EVLWHEX,
3030 SPE_BUILTIN_EVLWHOSX,
3031 SPE_BUILTIN_EVLWHOUX,
3032 SPE_BUILTIN_EVLWHSPLATX,
3033 SPE_BUILTIN_EVLWWSPLATX,
3034 SPE_BUILTIN_EVMERGEHI,
3035 SPE_BUILTIN_EVMERGEHILO,
3036 SPE_BUILTIN_EVMERGELO,
3037 SPE_BUILTIN_EVMERGELOHI,
3038 SPE_BUILTIN_EVMHEGSMFAA,
3039 SPE_BUILTIN_EVMHEGSMFAN,
3040 SPE_BUILTIN_EVMHEGSMIAA,
3041 SPE_BUILTIN_EVMHEGSMIAN,
3042 SPE_BUILTIN_EVMHEGUMIAA,
3043 SPE_BUILTIN_EVMHEGUMIAN,
3044 SPE_BUILTIN_EVMHESMF,
3045 SPE_BUILTIN_EVMHESMFA,
3046 SPE_BUILTIN_EVMHESMFAAW,
3047 SPE_BUILTIN_EVMHESMFANW,
3048 SPE_BUILTIN_EVMHESMI,
3049 SPE_BUILTIN_EVMHESMIA,
3050 SPE_BUILTIN_EVMHESMIAAW,
3051 SPE_BUILTIN_EVMHESMIANW,
3052 SPE_BUILTIN_EVMHESSF,
3053 SPE_BUILTIN_EVMHESSFA,
3054 SPE_BUILTIN_EVMHESSFAAW,
3055 SPE_BUILTIN_EVMHESSFANW,
3056 SPE_BUILTIN_EVMHESSIAAW,
3057 SPE_BUILTIN_EVMHESSIANW,
3058 SPE_BUILTIN_EVMHEUMI,
3059 SPE_BUILTIN_EVMHEUMIA,
3060 SPE_BUILTIN_EVMHEUMIAAW,
3061 SPE_BUILTIN_EVMHEUMIANW,
3062 SPE_BUILTIN_EVMHEUSIAAW,
3063 SPE_BUILTIN_EVMHEUSIANW,
3064 SPE_BUILTIN_EVMHOGSMFAA,
3065 SPE_BUILTIN_EVMHOGSMFAN,
3066 SPE_BUILTIN_EVMHOGSMIAA,
3067 SPE_BUILTIN_EVMHOGSMIAN,
3068 SPE_BUILTIN_EVMHOGUMIAA,
3069 SPE_BUILTIN_EVMHOGUMIAN,
3070 SPE_BUILTIN_EVMHOSMF,
3071 SPE_BUILTIN_EVMHOSMFA,
3072 SPE_BUILTIN_EVMHOSMFAAW,
3073 SPE_BUILTIN_EVMHOSMFANW,
3074 SPE_BUILTIN_EVMHOSMI,
3075 SPE_BUILTIN_EVMHOSMIA,
3076 SPE_BUILTIN_EVMHOSMIAAW,
3077 SPE_BUILTIN_EVMHOSMIANW,
3078 SPE_BUILTIN_EVMHOSSF,
3079 SPE_BUILTIN_EVMHOSSFA,
3080 SPE_BUILTIN_EVMHOSSFAAW,
3081 SPE_BUILTIN_EVMHOSSFANW,
3082 SPE_BUILTIN_EVMHOSSIAAW,
3083 SPE_BUILTIN_EVMHOSSIANW,
3084 SPE_BUILTIN_EVMHOUMI,
3085 SPE_BUILTIN_EVMHOUMIA,
3086 SPE_BUILTIN_EVMHOUMIAAW,
3087 SPE_BUILTIN_EVMHOUMIANW,
3088 SPE_BUILTIN_EVMHOUSIAAW,
3089 SPE_BUILTIN_EVMHOUSIANW,
3090 SPE_BUILTIN_EVMWHSMF,
3091 SPE_BUILTIN_EVMWHSMFA,
3092 SPE_BUILTIN_EVMWHSMI,
3093 SPE_BUILTIN_EVMWHSMIA,
3094 SPE_BUILTIN_EVMWHSSF,
3095 SPE_BUILTIN_EVMWHSSFA,
3096 SPE_BUILTIN_EVMWHUMI,
3097 SPE_BUILTIN_EVMWHUMIA,
3098 SPE_BUILTIN_EVMWLSMIAAW,
3099 SPE_BUILTIN_EVMWLSMIANW,
3100 SPE_BUILTIN_EVMWLSSIAAW,
3101 SPE_BUILTIN_EVMWLSSIANW,
3102 SPE_BUILTIN_EVMWLUMI,
3103 SPE_BUILTIN_EVMWLUMIA,
3104 SPE_BUILTIN_EVMWLUMIAAW,
3105 SPE_BUILTIN_EVMWLUMIANW,
3106 SPE_BUILTIN_EVMWLUSIAAW,
3107 SPE_BUILTIN_EVMWLUSIANW,
3108 SPE_BUILTIN_EVMWSMF,
3109 SPE_BUILTIN_EVMWSMFA,
3110 SPE_BUILTIN_EVMWSMFAA,
3111 SPE_BUILTIN_EVMWSMFAN,
3112 SPE_BUILTIN_EVMWSMI,
3113 SPE_BUILTIN_EVMWSMIA,
3114 SPE_BUILTIN_EVMWSMIAA,
3115 SPE_BUILTIN_EVMWSMIAN,
3116 SPE_BUILTIN_EVMWHSSFAA,
3117 SPE_BUILTIN_EVMWSSF,
3118 SPE_BUILTIN_EVMWSSFA,
3119 SPE_BUILTIN_EVMWSSFAA,
3120 SPE_BUILTIN_EVMWSSFAN,
3121 SPE_BUILTIN_EVMWUMI,
3122 SPE_BUILTIN_EVMWUMIA,
3123 SPE_BUILTIN_EVMWUMIAA,
3124 SPE_BUILTIN_EVMWUMIAN,
3133 SPE_BUILTIN_EVSTDDX,
3134 SPE_BUILTIN_EVSTDHX,
3135 SPE_BUILTIN_EVSTDWX,
3136 SPE_BUILTIN_EVSTWHEX,
3137 SPE_BUILTIN_EVSTWHOX,
3138 SPE_BUILTIN_EVSTWWEX,
3139 SPE_BUILTIN_EVSTWWOX,
3140 SPE_BUILTIN_EVSUBFW,
3143 SPE_BUILTIN_EVADDSMIAAW,
3144 SPE_BUILTIN_EVADDSSIAAW,
3145 SPE_BUILTIN_EVADDUMIAAW,
3146 SPE_BUILTIN_EVADDUSIAAW,
3147 SPE_BUILTIN_EVCNTLSW,
3148 SPE_BUILTIN_EVCNTLZW,
3149 SPE_BUILTIN_EVEXTSB,
3150 SPE_BUILTIN_EVEXTSH,
3151 SPE_BUILTIN_EVFSABS,
3152 SPE_BUILTIN_EVFSCFSF,
3153 SPE_BUILTIN_EVFSCFSI,
3154 SPE_BUILTIN_EVFSCFUF,
3155 SPE_BUILTIN_EVFSCFUI,
3156 SPE_BUILTIN_EVFSCTSF,
3157 SPE_BUILTIN_EVFSCTSI,
3158 SPE_BUILTIN_EVFSCTSIZ,
3159 SPE_BUILTIN_EVFSCTUF,
3160 SPE_BUILTIN_EVFSCTUI,
3161 SPE_BUILTIN_EVFSCTUIZ,
3162 SPE_BUILTIN_EVFSNABS,
3163 SPE_BUILTIN_EVFSNEG,
3167 SPE_BUILTIN_EVSUBFSMIAAW,
3168 SPE_BUILTIN_EVSUBFSSIAAW,
3169 SPE_BUILTIN_EVSUBFUMIAAW,
3170 SPE_BUILTIN_EVSUBFUSIAAW,
3171 SPE_BUILTIN_EVADDIW,
3175 SPE_BUILTIN_EVLHHESPLAT,
3176 SPE_BUILTIN_EVLHHOSSPLAT,
3177 SPE_BUILTIN_EVLHHOUSPLAT,
3179 SPE_BUILTIN_EVLWHOS,
3180 SPE_BUILTIN_EVLWHOU,
3181 SPE_BUILTIN_EVLWHSPLAT,
3182 SPE_BUILTIN_EVLWWSPLAT,
3185 SPE_BUILTIN_EVSRWIS,
3186 SPE_BUILTIN_EVSRWIU,
3190 SPE_BUILTIN_EVSTWHE,
3191 SPE_BUILTIN_EVSTWHO,
3192 SPE_BUILTIN_EVSTWWE,
3193 SPE_BUILTIN_EVSTWWO,
3194 SPE_BUILTIN_EVSUBIFW,
3197 SPE_BUILTIN_EVCMPEQ,
3198 SPE_BUILTIN_EVCMPGTS,
3199 SPE_BUILTIN_EVCMPGTU,
3200 SPE_BUILTIN_EVCMPLTS,
3201 SPE_BUILTIN_EVCMPLTU,
3202 SPE_BUILTIN_EVFSCMPEQ,
3203 SPE_BUILTIN_EVFSCMPGT,
3204 SPE_BUILTIN_EVFSCMPLT,
3205 SPE_BUILTIN_EVFSTSTEQ,
3206 SPE_BUILTIN_EVFSTSTGT,
3207 SPE_BUILTIN_EVFSTSTLT,
3209 /* EVSEL compares. */
3210 SPE_BUILTIN_EVSEL_CMPEQ,
3211 SPE_BUILTIN_EVSEL_CMPGTS,
3212 SPE_BUILTIN_EVSEL_CMPGTU,
3213 SPE_BUILTIN_EVSEL_CMPLTS,
3214 SPE_BUILTIN_EVSEL_CMPLTU,
3215 SPE_BUILTIN_EVSEL_FSCMPEQ,
3216 SPE_BUILTIN_EVSEL_FSCMPGT,
3217 SPE_BUILTIN_EVSEL_FSCMPLT,
3218 SPE_BUILTIN_EVSEL_FSTSTEQ,
3219 SPE_BUILTIN_EVSEL_FSTSTGT,
3220 SPE_BUILTIN_EVSEL_FSTSTLT,
3222 SPE_BUILTIN_EVSPLATFI,
3223 SPE_BUILTIN_EVSPLATI,
3224 SPE_BUILTIN_EVMWHSSMAA,
3225 SPE_BUILTIN_EVMWHSMFAA,
3226 SPE_BUILTIN_EVMWHSMIAA,
3227 SPE_BUILTIN_EVMWHUSIAA,
3228 SPE_BUILTIN_EVMWHUMIAA,
3229 SPE_BUILTIN_EVMWHSSFAN,
3230 SPE_BUILTIN_EVMWHSSIAN,
3231 SPE_BUILTIN_EVMWHSMFAN,
3232 SPE_BUILTIN_EVMWHSMIAN,
3233 SPE_BUILTIN_EVMWHUSIAN,
3234 SPE_BUILTIN_EVMWHUMIAN,
3235 SPE_BUILTIN_EVMWHGSSFAA,
3236 SPE_BUILTIN_EVMWHGSMFAA,
3237 SPE_BUILTIN_EVMWHGSMIAA,
3238 SPE_BUILTIN_EVMWHGUMIAA,
3239 SPE_BUILTIN_EVMWHGSSFAN,
3240 SPE_BUILTIN_EVMWHGSMFAN,
3241 SPE_BUILTIN_EVMWHGSMIAN,
3242 SPE_BUILTIN_EVMWHGUMIAN,
3243 SPE_BUILTIN_MTSPEFSCR,
3244 SPE_BUILTIN_MFSPEFSCR,
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