1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common CPP definitions used by CPP_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define CPP_CPU_SPEC \
53 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
54 %{mpower2: -D_ARCH_PWR2} \
55 %{mpowerpc*: -D_ARCH_PPC} \
56 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
57 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
58 %{mcpu=common: -D_ARCH_COM} \
59 %{mcpu=power: -D_ARCH_PWR} \
60 %{mcpu=power2: -D_ARCH_PWR2} \
61 %{mcpu=power3: -D_ARCH_PPC} \
62 %{mcpu=power4: -D_ARCH_PPC} \
63 %{mcpu=powerpc: -D_ARCH_PPC} \
64 %{mcpu=rios: -D_ARCH_PWR} \
65 %{mcpu=rios1: -D_ARCH_PWR} \
66 %{mcpu=rios2: -D_ARCH_PWR2} \
67 %{mcpu=rsc: -D_ARCH_PWR} \
68 %{mcpu=rsc1: -D_ARCH_PWR} \
69 %{mcpu=401: -D_ARCH_PPC} \
70 %{mcpu=403: -D_ARCH_PPC} \
71 %{mcpu=405: -D_ARCH_PPC} \
72 %{mcpu=505: -D_ARCH_PPC} \
73 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
74 %{mcpu=602: -D_ARCH_PPC} \
75 %{mcpu=603: -D_ARCH_PPC} \
76 %{mcpu=603e: -D_ARCH_PPC} \
77 %{mcpu=ec603e: -D_ARCH_PPC} \
78 %{mcpu=604: -D_ARCH_PPC} \
79 %{mcpu=604e: -D_ARCH_PPC} \
80 %{mcpu=620: -D_ARCH_PPC} \
81 %{mcpu=740: -D_ARCH_PPC} \
82 %{mcpu=7400: -D_ARCH_PPC} \
83 %{mcpu=7450: -D_ARCH_PPC} \
84 %{mcpu=750: -D_ARCH_PPC} \
85 %{mcpu=801: -D_ARCH_PPC} \
86 %{mcpu=821: -D_ARCH_PPC} \
87 %{mcpu=823: -D_ARCH_PPC} \
88 %{mcpu=860: -D_ARCH_PPC} \
89 %{maltivec: -D__ALTIVEC__}"
91 /* Common ASM definitions used by ASM_SPEC among the various targets
92 for handling -mcpu=xxx switches. */
93 #define ASM_CPU_SPEC \
95 %{mpower: %{!mpower2: -mpwr}} \
98 %{mno-power: %{!mpowerpc*: -mcom}} \
99 %{!mno-power: %{!mpower2: %(asm_default)}}} \
100 %{mcpu=common: -mcom} \
101 %{mcpu=power: -mpwr} \
102 %{mcpu=power2: -mpwrx} \
103 %{mcpu=power3: -m604} \
104 %{mcpu=power4: -m604} \
105 %{mcpu=powerpc: -mppc} \
106 %{mcpu=rios: -mpwr} \
107 %{mcpu=rios1: -mpwr} \
108 %{mcpu=rios2: -mpwrx} \
110 %{mcpu=rsc1: -mpwr} \
118 %{mcpu=603e: -mppc} \
119 %{mcpu=ec603e: -mppc} \
121 %{mcpu=604e: -mppc} \
125 %{mcpu=7400: -mppc} \
126 %{mcpu=7450: -mppc} \
132 %{maltivec: -maltivec}"
134 #define CPP_DEFAULT_SPEC ""
136 #define ASM_DEFAULT_SPEC ""
138 /* This macro defines names of additional specifications to put in the specs
139 that can be used in various specifications like CC1_SPEC. Its definition
140 is an initializer with a subgrouping for each command option.
142 Each subgrouping contains a string constant, that defines the
143 specification name, and a string constant that used by the GNU CC driver
146 Do not define this macro if it does not need to do anything. */
148 #define SUBTARGET_EXTRA_SPECS
150 #define EXTRA_SPECS \
151 { "cpp_cpu", CPP_CPU_SPEC }, \
152 { "cpp_default", CPP_DEFAULT_SPEC }, \
153 { "asm_cpu", ASM_CPU_SPEC }, \
154 { "asm_default", ASM_DEFAULT_SPEC }, \
155 SUBTARGET_EXTRA_SPECS
157 /* Architecture type. */
159 extern int target_flags;
161 /* Use POWER architecture instructions and MQ register. */
162 #define MASK_POWER 0x00000001
164 /* Use POWER2 extensions to POWER architecture. */
165 #define MASK_POWER2 0x00000002
167 /* Use PowerPC architecture instructions. */
168 #define MASK_POWERPC 0x00000004
170 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
171 #define MASK_PPC_GPOPT 0x00000008
173 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
174 #define MASK_PPC_GFXOPT 0x00000010
176 /* Use PowerPC-64 architecture instructions. */
177 #define MASK_POWERPC64 0x00000020
179 /* Use revised mnemonic names defined for PowerPC architecture. */
180 #define MASK_NEW_MNEMONICS 0x00000040
182 /* Disable placing fp constants in the TOC; can be turned on when the
184 #define MASK_NO_FP_IN_TOC 0x00000080
186 /* Disable placing symbol+offset constants in the TOC; can be turned on when
187 the TOC overflows. */
188 #define MASK_NO_SUM_IN_TOC 0x00000100
190 /* Output only one TOC entry per module. Normally linking fails if
191 there are more than 16K unique variables/constants in an executable. With
192 this option, linking fails only if there are more than 16K modules, or
193 if there are more than 16K unique variables/constant in a single module.
195 This is at the cost of having 2 extra loads and one extra store per
196 function, and one less allocable register. */
197 #define MASK_MINIMAL_TOC 0x00000200
199 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
200 #define MASK_64BIT 0x00000400
202 /* Disable use of FPRs. */
203 #define MASK_SOFT_FLOAT 0x00000800
205 /* Enable load/store multiple, even on powerpc */
206 #define MASK_MULTIPLE 0x00001000
207 #define MASK_MULTIPLE_SET 0x00002000
209 /* Use string instructions for block moves */
210 #define MASK_STRING 0x00004000
211 #define MASK_STRING_SET 0x00008000
213 /* Disable update form of load/store */
214 #define MASK_NO_UPDATE 0x00010000
216 /* Disable fused multiply/add operations */
217 #define MASK_NO_FUSED_MADD 0x00020000
219 /* Nonzero if we need to schedule the prolog and epilog. */
220 #define MASK_SCHED_PROLOG 0x00040000
222 /* Use AltiVec instructions. */
223 #define MASK_ALTIVEC 0x00080000
225 /* Return small structures in memory (as the AIX ABI requires). */
226 #define MASK_AIX_STRUCT_RET 0x00100000
227 #define MASK_AIX_STRUCT_RET_SET 0x00200000
229 /* The only remaining free bit is 0x00400000. sysv4.h uses
230 0x00800000 -> 0x40000000, and 0x80000000 is not available
231 because target_flags is signed. */
233 #define TARGET_POWER (target_flags & MASK_POWER)
234 #define TARGET_POWER2 (target_flags & MASK_POWER2)
235 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
236 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
237 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
238 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
239 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
240 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
241 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
242 #define TARGET_64BIT (target_flags & MASK_64BIT)
243 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
244 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
245 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
246 #define TARGET_STRING (target_flags & MASK_STRING)
247 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
248 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
249 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
250 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
251 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
252 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
254 #define TARGET_32BIT (! TARGET_64BIT)
255 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
256 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
257 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
260 /* For libgcc2 we make sure this is a compile time constant */
261 #if defined (__64BIT__) || defined (__powerpc64__)
262 #define TARGET_POWERPC64 1
264 #define TARGET_POWERPC64 0
267 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
270 #define TARGET_XL_CALL 0
272 /* Run-time compilation parameters selecting different hardware subsets.
274 Macro to define tables used to set the flags.
275 This is a list in braces of pairs in braces,
276 each pair being { "NAME", VALUE }
277 where VALUE is the bits to set or minus the bits to clear.
278 An empty string NAME is used to identify the default VALUE. */
280 #define TARGET_SWITCHES \
281 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
282 N_("Use POWER instruction set")}, \
283 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
285 N_("Use POWER2 instruction set")}, \
286 {"no-power2", - MASK_POWER2, \
287 N_("Do not use POWER2 instruction set")}, \
288 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
290 N_("Do not use POWER instruction set")}, \
291 {"powerpc", MASK_POWERPC, \
292 N_("Use PowerPC instruction set")}, \
293 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
294 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
295 N_("Do not use PowerPC instruction set")}, \
296 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
297 N_("Use PowerPC General Purpose group optional instructions")},\
298 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
299 N_("Don't use PowerPC General Purpose group optional instructions")},\
300 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
301 N_("Use PowerPC Graphics group optional instructions")},\
302 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
303 N_("Don't use PowerPC Graphics group optional instructions")},\
304 {"powerpc64", MASK_POWERPC64, \
305 N_("Use PowerPC-64 instruction set")}, \
306 {"no-powerpc64", - MASK_POWERPC64, \
307 N_("Don't use PowerPC-64 instruction set")}, \
308 {"altivec", MASK_ALTIVEC , \
309 N_("Use AltiVec instructions")}, \
310 {"no-altivec", - MASK_ALTIVEC , \
311 N_("Don't use AltiVec instructions")}, \
312 {"new-mnemonics", MASK_NEW_MNEMONICS, \
313 N_("Use new mnemonics for PowerPC architecture")},\
314 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
315 N_("Use old mnemonics for PowerPC architecture")},\
316 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
317 | MASK_MINIMAL_TOC), \
318 N_("Put everything in the regular TOC")}, \
319 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
320 N_("Place floating point constants in TOC")}, \
321 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
322 N_("Don't place floating point constants in TOC")},\
323 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
324 N_("Place symbol+offset constants in TOC")}, \
325 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
326 N_("Don't place symbol+offset constants in TOC")},\
327 {"minimal-toc", MASK_MINIMAL_TOC, \
328 "Use only one TOC entry per procedure"}, \
329 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
331 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
332 N_("Place variable addresses in the regular TOC")},\
333 {"hard-float", - MASK_SOFT_FLOAT, \
334 N_("Use hardware fp")}, \
335 {"soft-float", MASK_SOFT_FLOAT, \
336 N_("Do not use hardware fp")}, \
337 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
338 N_("Generate load/store multiple instructions")}, \
339 {"no-multiple", - MASK_MULTIPLE, \
340 N_("Do not generate load/store multiple instructions")},\
341 {"no-multiple", MASK_MULTIPLE_SET, \
343 {"string", MASK_STRING | MASK_STRING_SET, \
344 N_("Generate string instructions for block moves")},\
345 {"no-string", - MASK_STRING, \
346 N_("Do not generate string instructions for block moves")},\
347 {"no-string", MASK_STRING_SET, \
349 {"update", - MASK_NO_UPDATE, \
350 N_("Generate load/store with update instructions")},\
351 {"no-update", MASK_NO_UPDATE, \
352 N_("Do not generate load/store with update instructions")},\
353 {"fused-madd", - MASK_NO_FUSED_MADD, \
354 N_("Generate fused multiply/add instructions")},\
355 {"no-fused-madd", MASK_NO_FUSED_MADD, \
356 N_("Don't generate fused multiply/add instructions")},\
357 {"sched-prolog", MASK_SCHED_PROLOG, \
359 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
360 N_("Don't schedule the start and end of the procedure")},\
361 {"sched-epilog", MASK_SCHED_PROLOG, \
363 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
365 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \
366 N_("Return all structures in memory (AIX default)")},\
367 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\
368 N_("Return small structures in registers (SVR4 default)")},\
369 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\
371 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\
373 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\
375 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\
378 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
381 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
383 /* This is meant to be redefined in the host dependent files */
384 #define SUBTARGET_SWITCHES
386 /* Processor type. Order must match cpu attribute in MD file. */
407 extern enum processor_type rs6000_cpu;
409 /* Recast the processor type to the cpu attribute. */
410 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
412 /* Define generic processor types based upon current deployment. */
413 #define PROCESSOR_COMMON PROCESSOR_PPC601
414 #define PROCESSOR_POWER PROCESSOR_RIOS1
415 #define PROCESSOR_POWERPC PROCESSOR_PPC604
416 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
418 /* Define the default processor. This is overridden by other tm.h files. */
419 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
420 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
422 /* Specify the dialect of assembler to use. New mnemonics is dialect one
423 and the old mnemonics are dialect zero. */
424 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
426 /* This is meant to be overridden in target specific files. */
427 #define SUBTARGET_OPTIONS
429 #define TARGET_OPTIONS \
431 {"cpu=", &rs6000_select[1].string, \
432 N_("Use features of and schedule code for given CPU") }, \
433 {"tune=", &rs6000_select[2].string, \
434 N_("Schedule code for given CPU") }, \
435 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
436 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
437 {"long-double-", &rs6000_long_double_size_string, \
438 N_("Specify size of long double (64 or 128 bits)") }, \
439 {"vrsave=", &rs6000_altivec_vrsave_string, \
440 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
441 {"longcall", &rs6000_longcall_switch, \
442 N_("Avoid all range limits on call instructions") }, \
443 {"no-longcall", &rs6000_longcall_switch, "" }, \
447 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
448 struct rs6000_cpu_select
456 extern struct rs6000_cpu_select rs6000_select[];
459 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
460 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
461 extern int rs6000_debug_stack; /* debug stack applications */
462 extern int rs6000_debug_arg; /* debug argument handling */
464 #define TARGET_DEBUG_STACK rs6000_debug_stack
465 #define TARGET_DEBUG_ARG rs6000_debug_arg
467 /* These are separate from target_flags because we've run out of bits
469 extern const char *rs6000_long_double_size_string;
470 extern int rs6000_long_double_type_size;
471 extern int rs6000_altivec_abi;
472 extern const char *rs6000_altivec_vrsave_string;
473 extern int rs6000_altivec_vrsave;
474 extern const char *rs6000_longcall_switch;
475 extern int rs6000_default_long_calls;
477 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
478 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
479 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
481 /* Sometimes certain combinations of command options do not make sense
482 on a particular target machine. You can define a macro
483 `OVERRIDE_OPTIONS' to take account of this. This macro, if
484 defined, is executed once just after all the command options have
487 Don't use this macro to turn on various extra optimizations for
488 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
490 On the RS/6000 this is used to define the target cpu type. */
492 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
494 /* Define this to change the optimizations performed by default. */
495 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
498 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
499 cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \
502 /* Show we can debug even without a frame pointer. */
503 #define CAN_DEBUG_WITHOUT_FP
505 /* target machine storage layout */
507 /* Define this macro if it is advisable to hold scalars in registers
508 in a wider mode than that declared by the program. In such cases,
509 the value is constrained to be within the bounds of the declared
510 type, but kept valid in the wider mode. The signedness of the
511 extension may differ from that of the type. */
513 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
514 if (GET_MODE_CLASS (MODE) == MODE_INT \
515 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
518 /* Define this if function arguments should also be promoted using the above
521 #define PROMOTE_FUNCTION_ARGS
523 /* Likewise, if the function return value is promoted. */
525 #define PROMOTE_FUNCTION_RETURN
527 /* Define this if most significant bit is lowest numbered
528 in instructions that operate on numbered bit-fields. */
529 /* That is true on RS/6000. */
530 #define BITS_BIG_ENDIAN 1
532 /* Define this if most significant byte of a word is the lowest numbered. */
533 /* That is true on RS/6000. */
534 #define BYTES_BIG_ENDIAN 1
536 /* Define this if most significant word of a multiword number is lowest
539 For RS/6000 we can decide arbitrarily since there are no machine
540 instructions for them. Might as well be consistent with bits and bytes. */
541 #define WORDS_BIG_ENDIAN 1
543 #define MAX_BITS_PER_WORD 64
545 /* Width of a word, in units (bytes). */
546 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
547 #define MIN_UNITS_PER_WORD 4
548 #define UNITS_PER_FP_WORD 8
549 #define UNITS_PER_ALTIVEC_WORD 16
551 /* Type used for ptrdiff_t, as a string used in a declaration. */
552 #define PTRDIFF_TYPE "int"
554 /* Type used for size_t, as a string used in a declaration. */
555 #define SIZE_TYPE "long unsigned int"
557 /* Type used for wchar_t, as a string used in a declaration. */
558 #define WCHAR_TYPE "short unsigned int"
560 /* Width of wchar_t in bits. */
561 #define WCHAR_TYPE_SIZE 16
563 /* A C expression for the size in bits of the type `short' on the
564 target machine. If you don't define this, the default is half a
565 word. (If this would be less than one storage unit, it is
566 rounded up to one unit.) */
567 #define SHORT_TYPE_SIZE 16
569 /* A C expression for the size in bits of the type `int' on the
570 target machine. If you don't define this, the default is one
572 #define INT_TYPE_SIZE 32
574 /* A C expression for the size in bits of the type `long' on the
575 target machine. If you don't define this, the default is one
577 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
578 #define MAX_LONG_TYPE_SIZE 64
580 /* A C expression for the size in bits of the type `long long' on the
581 target machine. If you don't define this, the default is two
583 #define LONG_LONG_TYPE_SIZE 64
585 /* A C expression for the size in bits of the type `float' on the
586 target machine. If you don't define this, the default is one
588 #define FLOAT_TYPE_SIZE 32
590 /* A C expression for the size in bits of the type `double' on the
591 target machine. If you don't define this, the default is two
593 #define DOUBLE_TYPE_SIZE 64
595 /* A C expression for the size in bits of the type `long double' on
596 the target machine. If you don't define this, the default is two
598 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
600 /* Constant which presents upper bound of the above value. */
601 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
603 /* Define this to set long double type size to use in libgcc2.c, which can
604 not depend on target_flags. */
605 #ifdef __LONG_DOUBLE_128__
606 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
608 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
611 /* Width in bits of a pointer.
612 See also the macro `Pmode' defined below. */
613 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
615 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
616 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
618 /* Boundary (in *bits*) on which stack pointer should be aligned. */
619 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
621 /* Allocation boundary (in *bits*) for the code of a function. */
622 #define FUNCTION_BOUNDARY 32
624 /* No data type wants to be aligned rounder than this. */
625 #define BIGGEST_ALIGNMENT 128
627 /* A C expression to compute the alignment for a variables in the
628 local store. TYPE is the data type, and ALIGN is the alignment
629 that the object would ordinarily have. */
630 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
631 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN)
633 /* Alignment of field after `int : 0' in a structure. */
634 #define EMPTY_FIELD_BOUNDARY 32
636 /* Every structure's size must be a multiple of this. */
637 #define STRUCTURE_SIZE_BOUNDARY 8
639 /* A bitfield declared as `int' forces `int' alignment for the struct. */
640 #define PCC_BITFIELD_TYPE_MATTERS 1
642 /* Make strings word-aligned so strcpy from constants will be faster.
643 Make vector constants quadword aligned. */
644 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
645 (TREE_CODE (EXP) == STRING_CST \
646 && (ALIGN) < BITS_PER_WORD \
650 /* Make arrays of chars word-aligned for the same reasons.
651 Align vectors to 128 bits. */
652 #define DATA_ALIGNMENT(TYPE, ALIGN) \
653 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
654 : TREE_CODE (TYPE) == ARRAY_TYPE \
655 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
656 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
658 /* Non-zero if move instructions will actually fail to work
659 when given unaligned data. */
660 #define STRICT_ALIGNMENT 0
662 /* Define this macro to be the value 1 if unaligned accesses have a cost
663 many times greater than aligned accesses, for example if they are
664 emulated in a trap handler. */
665 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
667 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
670 /* Standard register usage. */
672 /* Number of actual hardware registers.
673 The hardware registers are assigned numbers for the compiler
674 from 0 to just below FIRST_PSEUDO_REGISTER.
675 All registers that the compiler knows about must be given numbers,
676 even those that are not normally considered general registers.
678 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
679 an MQ register, a count register, a link register, and 8 condition
680 register fields, which we view here as separate registers.
682 In addition, the difference between the frame and argument pointers is
683 a function of the number of registers saved, so we need to have a
684 register for AP that will later be eliminated in favor of SP or FP.
685 This is a normal register, but it is fixed.
687 We also create a pseudo register for float/int conversions, that will
688 really represent the memory location used. It is represented here as
689 a register, in order to work around problems in allocating stack storage
690 in inline functions. */
692 #define FIRST_PSEUDO_REGISTER 111
694 /* This must be included for pre gcc 3.0 glibc compatibility. */
695 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
697 /* 1 for registers that have pervasive standard uses
698 and are not available for the register allocator.
700 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
701 as a local register; for all other OS's r2 is the TOC pointer.
703 cr5 is not supposed to be used.
705 On System V implementations, r13 is fixed and not available for use. */
707 #define FIXED_REGISTERS \
708 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
712 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
713 /* AltiVec registers. */ \
714 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
719 /* 1 for registers not available across function calls.
720 These must include the FIXED_REGISTERS and also any
721 registers that can be used without being saved.
722 The latter must include the registers where values are returned
723 and the register where structure-value addresses are passed.
724 Aside from that, you can include as many other registers as you like. */
726 #define CALL_USED_REGISTERS \
727 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
728 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
729 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
730 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
731 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
732 /* AltiVec registers. */ \
733 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
738 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
739 the entire set of `FIXED_REGISTERS' be included.
740 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
741 This macro is optional. If not specified, it defaults to the value
742 of `CALL_USED_REGISTERS'. */
744 #define CALL_REALLY_USED_REGISTERS \
745 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
748 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
749 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
750 /* AltiVec registers. */ \
751 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
752 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
762 #define MAX_CR_REGNO 75
764 #define FIRST_ALTIVEC_REGNO 77
765 #define LAST_ALTIVEC_REGNO 108
766 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
767 #define VRSAVE_REGNO 109
768 #define VSCR_REGNO 110
770 /* List the order in which to allocate registers. Each register must be
771 listed once, even those in FIXED_REGISTERS.
773 We allocate in the following order:
774 fp0 (not saved or used for anything)
775 fp13 - fp2 (not saved; incoming fp arg registers)
776 fp1 (not saved; return value)
777 fp31 - fp14 (saved; order given to save least number)
778 cr7, cr6 (not saved or special)
779 cr1 (not saved, but used for FP operations)
780 cr0 (not saved, but used for arithmetic operations)
781 cr4, cr3, cr2 (saved)
782 r0 (not saved; cannot be base reg)
783 r9 (not saved; best for TImode)
784 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
785 r3 (not saved; return value register)
786 r31 - r13 (saved; order given to save least number)
787 r12 (not saved; if used for DImode or DFmode would use r13)
788 mq (not saved; best to use it if we can)
789 ctr (not saved; when we have the choice ctr is better)
791 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
794 v0 - v1 (not saved or used for anything)
795 v13 - v3 (not saved; incoming vector arg registers)
796 v2 (not saved; incoming vector arg reg; return value)
797 v19 - v14 (not saved or used for anything)
798 v31 - v20 (saved; order given to save least number)
802 #define REG_ALLOC_ORDER \
804 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
806 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
807 50, 49, 48, 47, 46, \
808 75, 74, 69, 68, 72, 71, 70, \
810 9, 11, 10, 8, 7, 6, 5, 4, \
812 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
813 18, 17, 16, 15, 14, 13, 12, \
816 /* AltiVec registers. */ \
818 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
820 96, 95, 94, 93, 92, 91, \
821 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
825 /* True if register is floating-point. */
826 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
828 /* True if register is a condition register. */
829 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
831 /* True if register is a condition register, but not cr0. */
832 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
834 /* True if register is an integer register. */
835 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
837 /* True if register is the XER register. */
838 #define XER_REGNO_P(N) ((N) == XER_REGNO)
840 /* True if register is an AltiVec register. */
841 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
843 /* Return number of consecutive hard regs needed starting at reg REGNO
844 to hold something of mode MODE.
845 This is ordinarily the length in words of a value of mode MODE
846 but can be less for certain modes in special long registers.
848 POWER and PowerPC GPRs hold 32 bits worth;
849 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
851 #define HARD_REGNO_NREGS(REGNO, MODE) \
852 (FP_REGNO_P (REGNO) \
853 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
854 : ALTIVEC_REGNO_P (REGNO) \
855 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
856 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
858 #define ALTIVEC_VECTOR_MODE(MODE) \
859 ((MODE) == V16QImode \
860 || (MODE) == V8HImode \
861 || (MODE) == V4SFmode \
862 || (MODE) == V4SImode)
864 /* Define this macro to be nonzero if the port is prepared to handle
865 insns involving vector mode MODE. At the very least, it must have
866 move patterns for this mode. */
868 #define VECTOR_MODE_SUPPORTED_P(MODE) \
869 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
871 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
872 For POWER and PowerPC, the GPRs can hold any mode, but the float
873 registers only can hold floating modes and DImode, and CR register only
874 can hold CC modes. We cannot put TImode anywhere except general
875 register and it must be able to fit within the register set. */
877 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
878 (FP_REGNO_P (REGNO) ? \
879 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
880 || (GET_MODE_CLASS (MODE) == MODE_INT \
881 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
882 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
883 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
884 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
885 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
886 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
889 /* Value is 1 if it is a good idea to tie two pseudo registers
890 when one has mode MODE1 and one has mode MODE2.
891 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
892 for any hard reg, then this must be 0 for correct output. */
893 #define MODES_TIEABLE_P(MODE1, MODE2) \
894 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
895 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
896 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
897 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
898 : GET_MODE_CLASS (MODE1) == MODE_CC \
899 ? GET_MODE_CLASS (MODE2) == MODE_CC \
900 : GET_MODE_CLASS (MODE2) == MODE_CC \
901 ? GET_MODE_CLASS (MODE1) == MODE_CC \
902 : ALTIVEC_VECTOR_MODE (MODE1) \
903 ? ALTIVEC_VECTOR_MODE (MODE2) \
904 : ALTIVEC_VECTOR_MODE (MODE2) \
905 ? ALTIVEC_VECTOR_MODE (MODE1) \
908 /* A C expression returning the cost of moving data from a register of class
909 CLASS1 to one of CLASS2.
911 On the RS/6000, copying between floating-point and fixed-point
912 registers is expensive. */
914 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
915 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
916 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
917 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
918 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
919 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
920 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
921 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
922 || (CLASS1) == LINK_OR_CTR_REGS) \
923 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
924 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
925 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
928 /* A C expressions returning the cost of moving data of MODE from a register to
931 On the RS/6000, bump this up a bit. */
933 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
934 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
935 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
939 /* Specify the cost of a branch insn; roughly the number of extra insns that
940 should be added to avoid a branch.
942 Set this to 3 on the RS/6000 since that is roughly the average cost of an
943 unscheduled conditional branch. */
945 #define BRANCH_COST 3
947 /* Define this macro to change register usage conditional on target flags.
948 Set MQ register fixed (already call_used) if not POWER architecture
949 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
950 64-bit AIX reserves GPR13 for thread-private data.
951 Conditionally disable FPRs. */
953 #define CONDITIONAL_REGISTER_USAGE \
956 if (! TARGET_POWER) \
957 fixed_regs[64] = 1; \
959 fixed_regs[13] = call_used_regs[13] \
960 = call_really_used_regs[13] = 1; \
961 if (TARGET_SOFT_FLOAT) \
962 for (i = 32; i < 64; i++) \
963 fixed_regs[i] = call_used_regs[i] \
964 = call_really_used_regs[i] = 1; \
965 if (DEFAULT_ABI == ABI_V4 \
966 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
968 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
969 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
970 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
971 if (DEFAULT_ABI == ABI_DARWIN \
972 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
973 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
974 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
975 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
976 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
977 if (TARGET_ALTIVEC) \
978 global_regs[VSCR_REGNO] = 1; \
979 if (! TARGET_ALTIVEC) \
981 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
982 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
983 call_really_used_regs[VRSAVE_REGNO] = 1; \
985 if (TARGET_ALTIVEC_ABI) \
986 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
987 call_used_regs[i] = call_really_used_regs[i] = 1; \
990 /* Specify the registers used for certain standard purposes.
991 The values of these macros are register numbers. */
993 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
994 /* #define PC_REGNUM */
996 /* Register to use for pushing function arguments. */
997 #define STACK_POINTER_REGNUM 1
999 /* Base register for access to local variables of the function. */
1000 #define FRAME_POINTER_REGNUM 31
1002 /* Value should be nonzero if functions must have frame pointers.
1003 Zero means the frame pointer need not be set up (and parms
1004 may be accessed via the stack pointer) in functions that seem suitable.
1005 This is computed in `reload', in reload1.c. */
1006 #define FRAME_POINTER_REQUIRED 0
1008 /* Base register for access to arguments of the function. */
1009 #define ARG_POINTER_REGNUM 67
1011 /* Place to put static chain when calling a function that requires it. */
1012 #define STATIC_CHAIN_REGNUM 11
1014 /* Link register number. */
1015 #define LINK_REGISTER_REGNUM 65
1017 /* Count register number. */
1018 #define COUNT_REGISTER_REGNUM 66
1020 /* Place that structure value return address is placed.
1022 On the RS/6000, it is passed as an extra parameter. */
1023 #define STRUCT_VALUE 0
1025 /* Define the classes of registers for register constraints in the
1026 machine description. Also define ranges of constants.
1028 One of the classes must always be named ALL_REGS and include all hard regs.
1029 If there is more than one class, another class must be named NO_REGS
1030 and contain no registers.
1032 The name GENERAL_REGS must be the name of a class (or an alias for
1033 another name such as ALL_REGS). This is the class of registers
1034 that is allowed by "g" or "r" in a register constraint.
1035 Also, registers outside this class are allocated only when
1036 instructions express preferences for them.
1038 The classes must be numbered in nondecreasing order; that is,
1039 a larger-numbered class must never be contained completely
1040 in a smaller-numbered class.
1042 For any two classes, it is very desirable that there be another
1043 class that represents their union. */
1045 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1046 and condition registers, plus three special registers, MQ, CTR, and the
1049 However, r0 is special in that it cannot be used as a base register.
1050 So make a class for registers valid as base registers.
1052 Also, cr0 is the only condition code register that can be used in
1053 arithmetic insns, so make a separate class for it. */
1079 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1081 /* Give names of register classes as strings for dump file. */
1083 #define REG_CLASS_NAMES \
1092 "NON_SPECIAL_REGS", \
1096 "LINK_OR_CTR_REGS", \
1098 "SPEC_OR_GEN_REGS", \
1106 /* Define which registers fit in which classes.
1107 This is an initializer for a vector of HARD_REG_SET
1108 of length N_REG_CLASSES. */
1110 #define REG_CLASS_CONTENTS \
1112 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1113 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1114 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1115 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1116 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1117 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1118 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1119 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1120 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1121 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1122 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1123 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1124 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1125 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1126 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1127 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1128 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1129 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1130 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1133 /* The same information, inverted:
1134 Return the class number of the smallest class containing
1135 reg number REGNO. This could be a conditional expression
1136 or could index an array. */
1138 #define REGNO_REG_CLASS(REGNO) \
1139 ((REGNO) == 0 ? GENERAL_REGS \
1140 : (REGNO) < 32 ? BASE_REGS \
1141 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1142 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1143 : (REGNO) == CR0_REGNO ? CR0_REGS \
1144 : CR_REGNO_P (REGNO) ? CR_REGS \
1145 : (REGNO) == MQ_REGNO ? MQ_REGS \
1146 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1147 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1148 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1149 : (REGNO) == XER_REGNO ? XER_REGS \
1150 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1151 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1154 /* The class value for index registers, and the one for base regs. */
1155 #define INDEX_REG_CLASS GENERAL_REGS
1156 #define BASE_REG_CLASS BASE_REGS
1158 /* Get reg_class from a letter such as appears in the machine description. */
1160 #define REG_CLASS_FROM_LETTER(C) \
1161 ((C) == 'f' ? FLOAT_REGS \
1162 : (C) == 'b' ? BASE_REGS \
1163 : (C) == 'h' ? SPECIAL_REGS \
1164 : (C) == 'q' ? MQ_REGS \
1165 : (C) == 'c' ? CTR_REGS \
1166 : (C) == 'l' ? LINK_REGS \
1167 : (C) == 'v' ? ALTIVEC_REGS \
1168 : (C) == 'x' ? CR0_REGS \
1169 : (C) == 'y' ? CR_REGS \
1170 : (C) == 'z' ? XER_REGS \
1173 /* The letters I, J, K, L, M, N, and P in a register constraint string
1174 can be used to stand for particular ranges of immediate operands.
1175 This macro defines what the ranges are.
1176 C is the letter, and VALUE is a constant value.
1177 Return 1 if VALUE is in the range specified by C.
1179 `I' is a signed 16-bit constant
1180 `J' is a constant with only the high-order 16 bits non-zero
1181 `K' is a constant with only the low-order 16 bits non-zero
1182 `L' is a signed 16-bit constant shifted left 16 bits
1183 `M' is a constant that is greater than 31
1184 `N' is a positive constant that is an exact power of two
1185 `O' is the constant zero
1186 `P' is a constant whose negation is a signed 16-bit constant */
1188 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1189 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1190 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1191 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1192 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1193 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1194 : (C) == 'M' ? (VALUE) > 31 \
1195 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1196 : (C) == 'O' ? (VALUE) == 0 \
1197 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1200 /* Similar, but for floating constants, and defining letters G and H.
1201 Here VALUE is the CONST_DOUBLE rtx itself.
1203 We flag for special constants when we can copy the constant into
1204 a general register in two insns for DF/DI and one insn for SF.
1206 'H' is used for DI/DF constants that take 3 insns. */
1208 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1209 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1210 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1211 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1214 /* Optional extra constraints for this machine.
1216 'Q' means that is a memory operand that is just an offset from a reg.
1217 'R' is for AIX TOC entries.
1218 'S' is a constant that can be placed into a 64-bit mask operand
1219 'T' is a constant that can be placed into a 32-bit mask operand
1220 'U' is for V.4 small data references. */
1222 #define EXTRA_CONSTRAINT(OP, C) \
1223 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1224 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1225 : (C) == 'S' ? mask64_operand (OP, DImode) \
1226 : (C) == 'T' ? mask_operand (OP, SImode) \
1227 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1228 && small_data_operand (OP, GET_MODE (OP))) \
1231 /* Given an rtx X being reloaded into a reg required to be
1232 in class CLASS, return the class of reg to actually use.
1233 In general this is just CLASS; but on some machines
1234 in some cases it is preferable to use a more restrictive class.
1236 On the RS/6000, we have to return NO_REGS when we want to reload a
1237 floating-point CONST_DOUBLE to force it to be copied to memory.
1239 We also don't want to reload integer values into floating-point
1240 registers if we can at all help it. In fact, this can
1241 cause reload to abort, if it tries to generate a reload of CTR
1242 into a FP register and discovers it doesn't have the memory location
1245 ??? Would it be a good idea to have reload do the converse, that is
1246 try to reload floating modes into FP registers if possible?
1249 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1250 (((GET_CODE (X) == CONST_DOUBLE \
1251 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1253 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1254 && (CLASS) == NON_SPECIAL_REGS) \
1258 /* Return the register class of a scratch register needed to copy IN into
1259 or out of a register in CLASS in MODE. If it can be done directly,
1260 NO_REGS is returned. */
1262 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1263 secondary_reload_class (CLASS, MODE, IN)
1265 /* If we are copying between FP or AltiVec registers and anything
1266 else, we need a memory location. */
1268 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1269 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1270 || (CLASS2) == FLOAT_REGS \
1271 || (CLASS1) == ALTIVEC_REGS \
1272 || (CLASS2) == ALTIVEC_REGS))
1274 /* Return the maximum number of consecutive registers
1275 needed to represent mode MODE in a register of class CLASS.
1277 On RS/6000, this is the size of MODE in words,
1278 except in the FP regs, where a single reg is enough for two words. */
1279 #define CLASS_MAX_NREGS(CLASS, MODE) \
1280 (((CLASS) == FLOAT_REGS) \
1281 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1282 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1284 /* If defined, gives a class of registers that cannot be used as the
1285 operand of a SUBREG that changes the mode of the object illegally. */
1287 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1289 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1291 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1292 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1294 /* Stack layout; function entry, exit and calling. */
1296 /* Enumeration to give which calling sequence to use. */
1299 ABI_AIX, /* IBM's AIX */
1300 ABI_AIX_NODESC, /* AIX calling sequence minus
1301 function descriptors */
1302 ABI_V4, /* System V.4/eabi */
1303 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1306 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1308 /* Structure used to define the rs6000 stack */
1309 typedef struct rs6000_stack {
1310 int first_gp_reg_save; /* first callee saved GP register used */
1311 int first_fp_reg_save; /* first callee saved FP register used */
1312 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1313 int lr_save_p; /* true if the link reg needs to be saved */
1314 int cr_save_p; /* true if the CR reg needs to be saved */
1315 unsigned int vrsave_mask; /* mask of vec registers to save */
1316 int toc_save_p; /* true if the TOC needs to be saved */
1317 int push_p; /* true if we need to allocate stack space */
1318 int calls_p; /* true if the function makes any calls */
1319 enum rs6000_abi abi; /* which ABI to use */
1320 int gp_save_offset; /* offset to save GP regs from initial SP */
1321 int fp_save_offset; /* offset to save FP regs from initial SP */
1322 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */
1323 int lr_save_offset; /* offset to save LR from initial SP */
1324 int cr_save_offset; /* offset to save CR from initial SP */
1325 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1326 int toc_save_offset; /* offset to save the TOC pointer */
1327 int varargs_save_offset; /* offset to save the varargs registers */
1328 int ehrd_offset; /* offset to EH return data */
1329 int reg_size; /* register size (4 or 8) */
1330 int varargs_size; /* size to hold V.4 args passed in regs */
1331 int vars_size; /* variable save area size */
1332 int parm_size; /* outgoing parameter size */
1333 int save_size; /* save area size */
1334 int fixed_size; /* fixed size of stack frame */
1335 int gp_size; /* size of saved GP registers */
1336 int fp_size; /* size of saved FP registers */
1337 int altivec_size; /* size of saved AltiVec registers */
1338 int cr_size; /* size to hold CR if not in save_size */
1339 int lr_size; /* size to hold LR if not in save_size */
1340 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1341 int altivec_padding_size; /* size of altivec alignment padding if
1343 int toc_size; /* size to hold TOC if not in save_size */
1344 int total_size; /* total bytes allocated for stack */
1347 /* Define this if pushing a word on the stack
1348 makes the stack pointer a smaller address. */
1349 #define STACK_GROWS_DOWNWARD
1351 /* Define this if the nominal address of the stack frame
1352 is at the high-address end of the local variables;
1353 that is, each additional local variable allocated
1354 goes at a more negative offset in the frame.
1356 On the RS/6000, we grow upwards, from the area after the outgoing
1358 /* #define FRAME_GROWS_DOWNWARD */
1360 /* Size of the outgoing register save area */
1361 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1362 || DEFAULT_ABI == ABI_AIX_NODESC \
1363 || DEFAULT_ABI == ABI_DARWIN) \
1364 ? (TARGET_64BIT ? 64 : 32) \
1367 /* Size of the fixed area on the stack */
1368 #define RS6000_SAVE_AREA \
1369 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1370 << (TARGET_64BIT ? 1 : 0))
1372 /* MEM representing address to save the TOC register */
1373 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1374 plus_constant (stack_pointer_rtx, \
1375 (TARGET_32BIT ? 20 : 40)))
1377 /* Size of the V.4 varargs area if needed */
1378 #define RS6000_VARARGS_AREA 0
1380 /* Align an address */
1381 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1383 /* Size of V.4 varargs area in bytes */
1384 #define RS6000_VARARGS_SIZE \
1385 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1387 /* Offset within stack frame to start allocating local variables at.
1388 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1389 first local allocated. Otherwise, it is the offset to the BEGINNING
1390 of the first local allocated.
1392 On the RS/6000, the frame pointer is the same as the stack pointer,
1393 except for dynamic allocations. So we start after the fixed area and
1394 outgoing parameter area. */
1396 #define STARTING_FRAME_OFFSET \
1397 (RS6000_ALIGN (current_function_outgoing_args_size, \
1398 TARGET_ALTIVEC ? 16 : 8) \
1399 + RS6000_VARARGS_AREA \
1402 /* Offset from the stack pointer register to an item dynamically
1403 allocated on the stack, e.g., by `alloca'.
1405 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1406 length of the outgoing arguments. The default is correct for most
1407 machines. See `function.c' for details. */
1408 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1409 (RS6000_ALIGN (current_function_outgoing_args_size, \
1410 TARGET_ALTIVEC ? 16 : 8) \
1411 + (STACK_POINTER_OFFSET))
1413 /* If we generate an insn to push BYTES bytes,
1414 this says how many the stack pointer really advances by.
1415 On RS/6000, don't define this because there are no push insns. */
1416 /* #define PUSH_ROUNDING(BYTES) */
1418 /* Offset of first parameter from the argument pointer register value.
1419 On the RS/6000, we define the argument pointer to the start of the fixed
1421 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1423 /* Offset from the argument pointer register value to the top of
1424 stack. This is different from FIRST_PARM_OFFSET because of the
1425 register save area. */
1426 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1428 /* Define this if stack space is still allocated for a parameter passed
1429 in a register. The value is the number of bytes allocated to this
1431 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1433 /* Define this if the above stack space is to be considered part of the
1434 space allocated by the caller. */
1435 #define OUTGOING_REG_PARM_STACK_SPACE
1437 /* This is the difference between the logical top of stack and the actual sp.
1439 For the RS/6000, sp points past the fixed area. */
1440 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1442 /* Define this if the maximum size of all the outgoing args is to be
1443 accumulated and pushed during the prologue. The amount can be
1444 found in the variable current_function_outgoing_args_size. */
1445 #define ACCUMULATE_OUTGOING_ARGS 1
1447 /* Value is the number of bytes of arguments automatically
1448 popped when returning from a subroutine call.
1449 FUNDECL is the declaration node of the function (as a tree),
1450 FUNTYPE is the data type of the function (as a tree),
1451 or for a library call it is an identifier node for the subroutine name.
1452 SIZE is the number of bytes of arguments passed on the stack. */
1454 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1456 /* Define how to find the value returned by a function.
1457 VALTYPE is the data type of the value (as a tree).
1458 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1459 otherwise, FUNC is 0.
1461 On RS/6000 an integer value is in r3 and a floating-point value is in
1462 fp1, unless -msoft-float. */
1464 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1465 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1466 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1467 || POINTER_TYPE_P (VALTYPE) \
1468 ? word_mode : TYPE_MODE (VALTYPE), \
1469 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1470 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1471 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1472 ? FP_ARG_RETURN : GP_ARG_RETURN)
1474 /* Define how to find the value returned by a library function
1475 assuming the value has mode MODE. */
1477 #define LIBCALL_VALUE(MODE) \
1478 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1479 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1480 && TARGET_HARD_FLOAT \
1481 ? FP_ARG_RETURN : GP_ARG_RETURN)
1483 /* The AIX ABI for the RS/6000 specifies that all structures are
1484 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1485 specifies that structures <= 8 bytes are returned in r3/r4, but a
1486 draft put them in memory, and GCC used to implement the draft
1487 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1488 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1489 compatibility can change DRAFT_V4_STRUCT_RET to override the
1490 default, and -m switches get the final word. See
1491 rs6000_override_options for more details.
1493 int_size_in_bytes returns -1 for variable size objects, which go in
1494 memory always. The cast to unsigned makes -1 > 8. */
1496 #define RETURN_IN_MEMORY(TYPE) \
1497 (AGGREGATE_TYPE_P (TYPE) && \
1498 (TARGET_AIX_STRUCT_RET || \
1499 (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8))
1501 /* DRAFT_V4_STRUCT_RET defaults off. */
1502 #define DRAFT_V4_STRUCT_RET 0
1504 /* Let RETURN_IN_MEMORY control what happens. */
1505 #define DEFAULT_PCC_STRUCT_RETURN 0
1507 /* Mode of stack savearea.
1508 FUNCTION is VOIDmode because calling convention maintains SP.
1509 BLOCK needs Pmode for SP.
1510 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1511 #define STACK_SAVEAREA_MODE(LEVEL) \
1512 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1513 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1515 /* Minimum and maximum general purpose registers used to hold arguments. */
1516 #define GP_ARG_MIN_REG 3
1517 #define GP_ARG_MAX_REG 10
1518 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1520 /* Minimum and maximum floating point registers used to hold arguments. */
1521 #define FP_ARG_MIN_REG 33
1522 #define FP_ARG_AIX_MAX_REG 45
1523 #define FP_ARG_V4_MAX_REG 40
1524 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1525 || DEFAULT_ABI == ABI_AIX_NODESC \
1526 || DEFAULT_ABI == ABI_DARWIN) \
1527 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1528 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1530 /* Minimum and maximum AltiVec registers used to hold arguments. */
1531 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1532 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1533 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1535 /* Return registers */
1536 #define GP_ARG_RETURN GP_ARG_MIN_REG
1537 #define FP_ARG_RETURN FP_ARG_MIN_REG
1538 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1540 /* Flags for the call/call_value rtl operations set up by function_arg */
1541 #define CALL_NORMAL 0x00000000 /* no special processing */
1542 /* Bits in 0x00000001 are unused. */
1543 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1544 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1545 #define CALL_LONG 0x00000008 /* always call indirect */
1547 /* 1 if N is a possible register number for a function value
1548 as seen by the caller.
1550 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1551 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1552 || ((N) == FP_ARG_RETURN) \
1553 || (TARGET_ALTIVEC && \
1554 (N) == ALTIVEC_ARG_RETURN))
1556 /* 1 if N is a possible register number for function argument passing.
1557 On RS/6000, these are r3-r10 and fp1-fp13.
1558 On AltiVec, v2 - v13 are used for passing vectors. */
1559 #define FUNCTION_ARG_REGNO_P(N) \
1560 (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1561 || (TARGET_ALTIVEC && \
1562 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1563 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1566 /* A C structure for machine-specific, per-function data.
1567 This is added to the cfun structure. */
1568 typedef struct machine_function GTY(())
1570 /* Whether a System V.4 varargs area was created. */
1572 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1573 int ra_needs_full_frame;
1576 /* Define a data type for recording info about an argument list
1577 during the scan of that argument list. This data type should
1578 hold all necessary information about the function itself
1579 and about the args processed so far, enough to enable macros
1580 such as FUNCTION_ARG to determine where the next arg should go.
1582 On the RS/6000, this is a structure. The first element is the number of
1583 total argument words, the second is used to store the next
1584 floating-point register number, and the third says how many more args we
1585 have prototype types for.
1587 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1588 the next availible GP register, `fregno' is the next available FP
1589 register, and `words' is the number of words used on the stack.
1591 The varargs/stdarg support requires that this structure's size
1592 be a multiple of sizeof(int). */
1594 typedef struct rs6000_args
1596 int words; /* # words used for passing GP registers */
1597 int fregno; /* next available FP register */
1598 int vregno; /* next available AltiVec register */
1599 int nargs_prototype; /* # args left in the current prototype */
1600 int orig_nargs; /* Original value of nargs_prototype */
1601 int prototype; /* Whether a prototype was defined */
1602 int call_cookie; /* Do special things for this call */
1603 int sysv_gregno; /* next available GP register */
1606 /* Define intermediate macro to compute the size (in registers) of an argument
1609 #define RS6000_ARG_SIZE(MODE, TYPE) \
1610 ((MODE) != BLKmode \
1611 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1612 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1614 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1615 for a call to a function whose data type is FNTYPE.
1616 For a library call, FNTYPE is 0. */
1618 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1619 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1621 /* Similar, but when scanning the definition of a procedure. We always
1622 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1624 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1625 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1627 /* Update the data in CUM to advance over an argument
1628 of mode MODE and data type TYPE.
1629 (TYPE is null for libcalls where that information may not be available.) */
1631 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1632 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1634 /* Non-zero if we can use a floating-point register to pass this arg. */
1635 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1636 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1637 && (CUM).fregno <= FP_ARG_MAX_REG \
1638 && TARGET_HARD_FLOAT)
1640 /* Non-zero if we can use an AltiVec register to pass this arg. */
1641 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1642 (ALTIVEC_VECTOR_MODE (MODE) \
1643 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1644 && TARGET_ALTIVEC_ABI)
1646 /* Determine where to put an argument to a function.
1647 Value is zero to push the argument on the stack,
1648 or a hard register in which to store the argument.
1650 MODE is the argument's machine mode.
1651 TYPE is the data type of the argument (as a tree).
1652 This is null for libcalls where that information may
1654 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1655 the preceding args and about the function being called.
1656 NAMED is nonzero if this argument is a named parameter
1657 (otherwise it is an extra parameter matching an ellipsis).
1659 On RS/6000 the first eight words of non-FP are normally in registers
1660 and the rest are pushed. The first 13 FP args are in registers.
1662 If this is floating-point and no prototype is specified, we use
1663 both an FP and integer register (or possibly FP reg and stack). Library
1664 functions (when TYPE is zero) always have the proper types for args,
1665 so we can pass the FP value just in one register. emit_library_function
1666 doesn't support EXPR_LIST anyway. */
1668 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1669 function_arg (&CUM, MODE, TYPE, NAMED)
1671 /* For an arg passed partly in registers and partly in memory,
1672 this is the number of registers used.
1673 For args passed entirely in registers or entirely in memory, zero. */
1675 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1676 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1678 /* A C expression that indicates when an argument must be passed by
1679 reference. If nonzero for an argument, a copy of that argument is
1680 made in memory and a pointer to the argument is passed instead of
1681 the argument itself. The pointer is passed in whatever way is
1682 appropriate for passing a pointer to that type. */
1684 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1685 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1687 /* If defined, a C expression which determines whether, and in which
1688 direction, to pad out an argument with extra space. The value
1689 should be of type `enum direction': either `upward' to pad above
1690 the argument, `downward' to pad below, or `none' to inhibit
1693 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1695 /* If defined, a C expression that gives the alignment boundary, in bits,
1696 of an argument with the specified mode and type. If it is not defined,
1697 PARM_BOUNDARY is used for all arguments. */
1699 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1700 function_arg_boundary (MODE, TYPE)
1702 /* Perform any needed actions needed for a function that is receiving a
1703 variable number of arguments.
1707 MODE and TYPE are the mode and type of the current parameter.
1709 PRETEND_SIZE is a variable that should be set to the amount of stack
1710 that must be pushed by the prolog to pretend that our caller pushed
1713 Normally, this macro will push all remaining incoming registers on the
1714 stack and set PRETEND_SIZE to the length of the registers pushed. */
1716 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1717 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1719 /* Define the `__builtin_va_list' type for the ABI. */
1720 #define BUILD_VA_LIST_TYPE(VALIST) \
1721 (VALIST) = rs6000_build_va_list ()
1723 /* Implement `va_start' for varargs and stdarg. */
1724 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1725 rs6000_va_start (stdarg, valist, nextarg)
1727 /* Implement `va_arg'. */
1728 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1729 rs6000_va_arg (valist, type)
1731 /* For AIX, the rule is that structures are passed left-aligned in
1732 their stack slot. However, GCC does not presently do this:
1733 structures which are the same size as integer types are passed
1734 right-aligned, as if they were in fact integers. This only
1735 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1736 ABI_V4 does not use std_expand_builtin_va_arg. */
1737 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1739 /* Define this macro to be a nonzero value if the location where a function
1740 argument is passed depends on whether or not it is a named argument. */
1741 #define STRICT_ARGUMENT_NAMING 1
1743 /* Output assembler code to FILE to increment profiler label # LABELNO
1744 for profiling a function entry. */
1746 #define FUNCTION_PROFILER(FILE, LABELNO) \
1747 output_function_profiler ((FILE), (LABELNO));
1749 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1750 the stack pointer does not matter. No definition is equivalent to
1753 On the RS/6000, this is non-zero because we can restore the stack from
1754 its backpointer, which we maintain. */
1755 #define EXIT_IGNORE_STACK 1
1757 /* Define this macro as a C expression that is nonzero for registers
1758 that are used by the epilogue or the return' pattern. The stack
1759 and frame pointer registers are already be assumed to be used as
1762 #define EPILOGUE_USES(REGNO) \
1763 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1764 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1765 || (current_function_calls_eh_return \
1767 && (REGNO) == TOC_REGISTER))
1770 /* TRAMPOLINE_TEMPLATE deleted */
1772 /* Length in units of the trampoline for entering a nested function. */
1774 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1776 /* Emit RTL insns to initialize the variable parts of a trampoline.
1777 FNADDR is an RTX for the address of the function's pure code.
1778 CXT is an RTX for the static chain value for the function. */
1780 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1781 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1783 /* Definitions for __builtin_return_address and __builtin_frame_address.
1784 __builtin_return_address (0) should give link register (65), enable
1786 /* This should be uncommented, so that the link register is used, but
1787 currently this would result in unmatched insns and spilling fixed
1788 registers so we'll leave it for another day. When these problems are
1789 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1791 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1793 /* Number of bytes into the frame return addresses can be found. See
1794 rs6000_stack_info in rs6000.c for more information on how the different
1795 abi's store the return address. */
1796 #define RETURN_ADDRESS_OFFSET \
1797 ((DEFAULT_ABI == ABI_AIX \
1798 || DEFAULT_ABI == ABI_DARWIN \
1799 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1800 (DEFAULT_ABI == ABI_V4) ? 4 : \
1801 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1803 /* The current return address is in link register (65). The return address
1804 of anything farther back is accessed normally at an offset of 8 from the
1806 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1807 (rs6000_return_addr (COUNT, FRAME))
1810 /* Definitions for register eliminations.
1812 We have two registers that can be eliminated on the RS/6000. First, the
1813 frame pointer register can often be eliminated in favor of the stack
1814 pointer register. Secondly, the argument pointer register can always be
1815 eliminated; it is replaced with either the stack or frame pointer.
1817 In addition, we use the elimination mechanism to see if r30 is needed
1818 Initially we assume that it isn't. If it is, we spill it. This is done
1819 by making it an eliminable register. We replace it with itself so that
1820 if it isn't needed, then existing uses won't be modified. */
1822 /* This is an array of structures. Each structure initializes one pair
1823 of eliminable registers. The "from" register number is given first,
1824 followed by "to". Eliminations of the same "from" register are listed
1825 in order of preference. */
1826 #define ELIMINABLE_REGS \
1827 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1828 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1829 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1832 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1833 Frame pointer elimination is automatically handled.
1835 For the RS/6000, if frame pointer elimination is being done, we would like
1836 to convert ap into fp, not sp.
1838 We need r30 if -mminimal-toc was specified, and there are constant pool
1841 #define CAN_ELIMINATE(FROM, TO) \
1842 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1843 ? ! frame_pointer_needed \
1844 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1847 /* Define the offset between two registers, one to be eliminated, and the other
1848 its replacement, at the start of a routine. */
1849 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1851 rs6000_stack_t *info = rs6000_stack_info (); \
1853 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1854 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1855 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1856 (OFFSET) = info->total_size; \
1857 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1858 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1859 else if ((FROM) == 30) \
1865 /* Addressing modes, and classification of registers for them. */
1867 /* #define HAVE_POST_INCREMENT 0 */
1868 /* #define HAVE_POST_DECREMENT 0 */
1870 #define HAVE_PRE_DECREMENT 1
1871 #define HAVE_PRE_INCREMENT 1
1873 /* Macros to check register numbers against specific register classes. */
1875 /* These assume that REGNO is a hard or pseudo reg number.
1876 They give nonzero only if REGNO is a hard reg of the suitable class
1877 or a pseudo reg currently allocated to a suitable hard reg.
1878 Since they use reg_renumber, they are safe only once reg_renumber
1879 has been allocated, which happens in local-alloc.c. */
1881 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1882 ((REGNO) < FIRST_PSEUDO_REGISTER \
1883 ? (REGNO) <= 31 || (REGNO) == 67 \
1884 : (reg_renumber[REGNO] >= 0 \
1885 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1887 #define REGNO_OK_FOR_BASE_P(REGNO) \
1888 ((REGNO) < FIRST_PSEUDO_REGISTER \
1889 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1890 : (reg_renumber[REGNO] > 0 \
1891 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1893 /* Maximum number of registers that can appear in a valid memory address. */
1895 #define MAX_REGS_PER_ADDRESS 2
1897 /* Recognize any constant value that is a valid address. */
1899 #define CONSTANT_ADDRESS_P(X) \
1900 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1901 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1902 || GET_CODE (X) == HIGH)
1904 /* Nonzero if the constant value X is a legitimate general operand.
1905 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1907 On the RS/6000, all integer constants are acceptable, most won't be valid
1908 for particular insns, though. Only easy FP constants are
1911 #define LEGITIMATE_CONSTANT_P(X) \
1912 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1913 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1914 || easy_fp_constant (X, GET_MODE (X)))
1916 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1917 and check its validity for a certain class.
1918 We have two alternate definitions for each of them.
1919 The usual definition accepts all pseudo regs; the other rejects
1920 them unless they have been allocated suitable hard regs.
1921 The symbol REG_OK_STRICT causes the latter definition to be used.
1923 Most source files want to accept pseudo regs in the hope that
1924 they will get allocated to the class that the insn wants them to be in.
1925 Source files for reload pass need to be strict.
1926 After reload, it makes no difference, since pseudo regs have
1927 been eliminated by then. */
1929 #ifdef REG_OK_STRICT
1930 # define REG_OK_STRICT_FLAG 1
1932 # define REG_OK_STRICT_FLAG 0
1935 /* Nonzero if X is a hard reg that can be used as an index
1936 or if it is a pseudo reg in the non-strict case. */
1937 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1939 && (REGNO (X) <= 31 \
1940 || REGNO (X) == ARG_POINTER_REGNUM \
1941 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1942 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1944 /* Nonzero if X is a hard reg that can be used as a base reg
1945 or if it is a pseudo reg in the non-strict case. */
1946 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1947 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1949 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1950 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1952 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1953 that is a valid memory address for an instruction.
1954 The MODE argument is the machine mode for the MEM expression
1955 that wants to use this address.
1957 On the RS/6000, there are four valid address: a SYMBOL_REF that
1958 refers to a constant pool entry of an address (or the sum of it
1959 plus a constant), a short (16-bit signed) constant plus a register,
1960 the sum of two registers, or a register indirect, possibly with an
1961 auto-increment. For DFmode and DImode with an constant plus register,
1962 we must ensure that both words are addressable or PowerPC64 with offset
1965 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1966 32-bit DImode, TImode), indexed addressing cannot be used because
1967 adjacent memory cells are accessed by adding word-sized offsets
1968 during assembly output. */
1970 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1972 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1974 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1976 && GET_CODE (X) == PLUS \
1977 && GET_CODE (XEXP (X, 0)) == REG \
1978 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1979 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1981 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1982 (DEFAULT_ABI == ABI_V4 \
1983 && !flag_pic && !TARGET_TOC \
1984 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1985 && small_data_operand (X, MODE))
1987 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1988 (GET_CODE (X) == CONST_INT \
1989 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1991 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1992 (GET_CODE (X) == PLUS \
1993 && GET_CODE (XEXP (X, 0)) == REG \
1994 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1995 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1996 && (! ALTIVEC_VECTOR_MODE (MODE) \
1997 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
1998 && (((MODE) != DFmode && (MODE) != DImode) \
2000 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
2001 : ! (INTVAL (XEXP (X, 1)) & 3))) \
2002 && ((MODE) != TImode \
2004 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
2005 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2006 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2008 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2009 (GET_CODE (X) == PLUS \
2010 && GET_CODE (XEXP (X, 0)) == REG \
2011 && GET_CODE (XEXP (X, 1)) == REG \
2012 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2013 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2014 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2015 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2017 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2018 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2020 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2022 && ! flag_pic && ! TARGET_TOC \
2023 && GET_MODE_NUNITS (MODE) == 1 \
2024 && (GET_MODE_BITSIZE (MODE) <= 32 \
2025 || (TARGET_HARD_FLOAT && (MODE) == DFmode)) \
2026 && GET_CODE (X) == LO_SUM \
2027 && GET_CODE (XEXP (X, 0)) == REG \
2028 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2029 && CONSTANT_P (XEXP (X, 1)))
2031 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2032 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2036 /* Try machine-dependent ways of modifying an illegitimate address
2037 to be legitimate. If we find one, return the new, valid address.
2038 This macro is used in only one place: `memory_address' in explow.c.
2040 OLDX is the address as it was before break_out_memory_refs was called.
2041 In some cases it is useful to look at this to decide what needs to be done.
2043 MODE and WIN are passed so that this macro can use
2044 GO_IF_LEGITIMATE_ADDRESS.
2046 It is always safe for this macro to do nothing. It exists to recognize
2047 opportunities to optimize the output.
2049 On RS/6000, first check for the sum of a register with a constant
2050 integer that is out of range. If so, generate code to add the
2051 constant with the low-order 16 bits masked to the register and force
2052 this result into another register (this can be done with `cau').
2053 Then generate an address of REG+(CONST&0xffff), allowing for the
2054 possibility of bit 16 being a one.
2056 Then check for the sum of a register and something not constant, try to
2057 load the other things into a register and return the sum. */
2059 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2060 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2061 if (result != NULL_RTX) \
2068 /* Try a machine-dependent way of reloading an illegitimate address
2069 operand. If we find one, push the reload and jump to WIN. This
2070 macro is used in only one place: `find_reloads_address' in reload.c.
2072 Implemented on rs6000 by rs6000_legitimize_reload_address.
2073 Note that (X) is evaluated twice; this is safe in current usage. */
2075 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2078 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2079 (int)(TYPE), (IND_LEVELS), &win); \
2084 /* Go to LABEL if ADDR (a legitimate address expression)
2085 has an effect that depends on the machine mode it is used for.
2087 On the RS/6000 this is true if the address is valid with a zero offset
2088 but not with an offset of four (this means it cannot be used as an
2089 address for DImode or DFmode) or is a pre-increment or decrement. Since
2090 we know it is valid, we just check for an address that is not valid with
2091 an offset of four. */
2093 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2094 { if (GET_CODE (ADDR) == PLUS \
2095 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2096 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2097 (TARGET_32BIT ? 4 : 8))) \
2099 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2101 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2103 if (GET_CODE (ADDR) == LO_SUM) \
2107 /* The register number of the register used to address a table of
2108 static data addresses in memory. In some cases this register is
2109 defined by a processor's "application binary interface" (ABI).
2110 When this macro is defined, RTL is generated for this register
2111 once, as with the stack pointer and frame pointer registers. If
2112 this macro is not defined, it is up to the machine-dependent files
2113 to allocate such a register (if necessary). */
2115 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2116 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2118 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2120 /* Define this macro if the register defined by
2121 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2122 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2124 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2126 /* By generating position-independent code, when two different
2127 programs (A and B) share a common library (libC.a), the text of
2128 the library can be shared whether or not the library is linked at
2129 the same address for both programs. In some of these
2130 environments, position-independent code requires not only the use
2131 of different addressing modes, but also special code to enable the
2132 use of these addressing modes.
2134 The `FINALIZE_PIC' macro serves as a hook to emit these special
2135 codes once the function is being compiled into assembly code, but
2136 not before. (It is not done before, because in the case of
2137 compiling an inline function, it would lead to multiple PIC
2138 prologues being included in functions which used inline functions
2139 and were compiled to assembly language.) */
2141 /* #define FINALIZE_PIC */
2143 /* A C expression that is nonzero if X is a legitimate immediate
2144 operand on the target machine when generating position independent
2145 code. You can assume that X satisfies `CONSTANT_P', so you need
2146 not check this. You can also assume FLAG_PIC is true, so you need
2147 not check it either. You need not define this macro if all
2148 constants (including `SYMBOL_REF') can be immediate operands when
2149 generating position independent code. */
2151 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2153 /* In rare cases, correct code generation requires extra machine
2154 dependent processing between the second jump optimization pass and
2155 delayed branch scheduling. On those machines, define this macro
2156 as a C statement to act on the code starting at INSN. */
2158 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2161 /* Define this if some processing needs to be done immediately before
2162 emitting code for an insn. */
2164 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2166 /* Specify the machine mode that this machine uses
2167 for the index in the tablejump instruction. */
2168 #define CASE_VECTOR_MODE SImode
2170 /* Define as C expression which evaluates to nonzero if the tablejump
2171 instruction expects the table to contain offsets from the address of the
2173 Do not define this if the table should contain absolute addresses. */
2174 #define CASE_VECTOR_PC_RELATIVE 1
2176 /* Define this as 1 if `char' should by default be signed; else as 0. */
2177 #define DEFAULT_SIGNED_CHAR 0
2179 /* This flag, if defined, says the same insns that convert to a signed fixnum
2180 also convert validly to an unsigned one. */
2182 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2184 /* Max number of bytes we can move from memory to memory
2185 in one reasonably fast instruction. */
2186 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2187 #define MAX_MOVE_MAX 8
2189 /* Nonzero if access to memory by bytes is no faster than for words.
2190 Also non-zero if doing byte operations (specifically shifts) in registers
2192 #define SLOW_BYTE_ACCESS 1
2194 /* Define if operations between registers always perform the operation
2195 on the full register even if a narrower mode is specified. */
2196 #define WORD_REGISTER_OPERATIONS
2198 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2199 will either zero-extend or sign-extend. The value of this macro should
2200 be the code that says which one of the two operations is implicitly
2201 done, NIL if none. */
2202 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2204 /* Define if loading short immediate values into registers sign extends. */
2205 #define SHORT_IMMEDIATES_SIGN_EXTEND
2207 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2208 is done just by pretending it is already truncated. */
2209 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2211 /* Specify the machine mode that pointers have.
2212 After generation of rtl, the compiler makes no further distinction
2213 between pointers and any other objects of this machine mode. */
2214 #define Pmode (TARGET_32BIT ? SImode : DImode)
2216 /* Mode of a function address in a call instruction (for indexing purposes).
2217 Doesn't matter on RS/6000. */
2218 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2220 /* Define this if addresses of constant functions
2221 shouldn't be put through pseudo regs where they can be cse'd.
2222 Desirable on machines where ordinary constants are expensive
2223 but a CALL with constant address is cheap. */
2224 #define NO_FUNCTION_CSE
2226 /* Define this to be nonzero if shift instructions ignore all but the low-order
2229 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2230 have been dropped from the PowerPC architecture. */
2232 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2234 /* Compute the cost of computing a constant rtl expression RTX
2235 whose rtx-code is CODE. The body of this macro is a portion
2236 of a switch statement. If the code is computed here,
2237 return it with a return statement. Otherwise, break from the switch.
2239 On the RS/6000, if it is valid in the insn, it is free. So this
2240 always returns 0. */
2242 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2247 case CONST_DOUBLE: \
2251 /* Provide the costs of a rtl expression. This is in the body of a
2254 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2256 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2257 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2258 + 0x8000) >= 0x10000) \
2259 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2260 ? COSTS_N_INSNS (2) \
2261 : COSTS_N_INSNS (1)); \
2265 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2266 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2267 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2268 ? COSTS_N_INSNS (2) \
2269 : COSTS_N_INSNS (1)); \
2271 switch (rs6000_cpu) \
2273 case PROCESSOR_RIOS1: \
2274 case PROCESSOR_PPC405: \
2275 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2276 ? COSTS_N_INSNS (5) \
2277 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2278 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2279 case PROCESSOR_RS64A: \
2280 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2281 ? GET_MODE (XEXP (X, 1)) != DImode \
2282 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2283 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2284 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \
2285 case PROCESSOR_RIOS2: \
2286 case PROCESSOR_MPCCORE: \
2287 case PROCESSOR_PPC604e: \
2288 return COSTS_N_INSNS (2); \
2289 case PROCESSOR_PPC601: \
2290 return COSTS_N_INSNS (5); \
2291 case PROCESSOR_PPC603: \
2292 case PROCESSOR_PPC7400: \
2293 case PROCESSOR_PPC750: \
2294 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2295 ? COSTS_N_INSNS (5) \
2296 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2297 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2298 case PROCESSOR_PPC7450: \
2299 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2300 ? COSTS_N_INSNS (4) \
2301 : COSTS_N_INSNS (3)); \
2302 case PROCESSOR_PPC403: \
2303 case PROCESSOR_PPC604: \
2304 return COSTS_N_INSNS (4); \
2305 case PROCESSOR_PPC620: \
2306 case PROCESSOR_PPC630: \
2307 case PROCESSOR_POWER4: \
2308 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2309 ? GET_MODE (XEXP (X, 1)) != DImode \
2310 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
2311 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2312 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2316 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2317 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2318 return COSTS_N_INSNS (2); \
2319 /* otherwise fall through to normal divide. */ \
2322 switch (rs6000_cpu) \
2324 case PROCESSOR_RIOS1: \
2325 return COSTS_N_INSNS (19); \
2326 case PROCESSOR_RIOS2: \
2327 return COSTS_N_INSNS (13); \
2328 case PROCESSOR_RS64A: \
2329 return (GET_MODE (XEXP (X, 1)) != DImode \
2330 ? COSTS_N_INSNS (65) \
2331 : COSTS_N_INSNS (67)); \
2332 case PROCESSOR_MPCCORE: \
2333 return COSTS_N_INSNS (6); \
2334 case PROCESSOR_PPC403: \
2335 return COSTS_N_INSNS (33); \
2336 case PROCESSOR_PPC405: \
2337 return COSTS_N_INSNS (35); \
2338 case PROCESSOR_PPC601: \
2339 return COSTS_N_INSNS (36); \
2340 case PROCESSOR_PPC603: \
2341 return COSTS_N_INSNS (37); \
2342 case PROCESSOR_PPC604: \
2343 case PROCESSOR_PPC604e: \
2344 return COSTS_N_INSNS (20); \
2345 case PROCESSOR_PPC620: \
2346 case PROCESSOR_PPC630: \
2347 case PROCESSOR_POWER4: \
2348 return (GET_MODE (XEXP (X, 1)) != DImode \
2349 ? COSTS_N_INSNS (21) \
2350 : COSTS_N_INSNS (37)); \
2351 case PROCESSOR_PPC750: \
2352 case PROCESSOR_PPC7400: \
2353 return COSTS_N_INSNS (19); \
2354 case PROCESSOR_PPC7450: \
2355 return COSTS_N_INSNS (23); \
2358 return COSTS_N_INSNS (4); \
2360 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2363 /* Compute the cost of an address. This is meant to approximate the size
2364 and/or execution delay of an insn using that address. If the cost is
2365 approximated by the RTL complexity, including CONST_COSTS above, as
2366 is usually the case for CISC machines, this macro should not be defined.
2367 For aggressively RISCy machines, only one insn format is allowed, so
2368 this macro should be a constant. The value of this macro only matters
2369 for valid addresses.
2371 For the RS/6000, everything is cost 0. */
2373 #define ADDRESS_COST(RTX) 0
2375 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2376 should be adjusted to reflect any required changes. This macro is used when
2377 there is some systematic length adjustment required that would be difficult
2378 to express in the length attribute. */
2380 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2382 /* Add any extra modes needed to represent the condition code.
2384 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2385 are being done and we need a separate mode for floating-point. We also
2386 use a mode for the case when we are comparing the results of two
2387 comparisons, as then only the EQ bit is valid in the register. */
2389 #define EXTRA_CC_MODES \
2390 CC(CCUNSmode, "CCUNS") \
2391 CC(CCFPmode, "CCFP") \
2392 CC(CCEQmode, "CCEQ")
2394 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2395 COMPARE, return the mode to be used for the comparison. For
2396 floating-point, CCFPmode should be used. CCUNSmode should be used
2397 for unsigned comparisons. CCEQmode should be used when we are
2398 doing an inequality comparison on the result of a
2399 comparison. CCmode should be used in all other cases. */
2401 #define SELECT_CC_MODE(OP,X,Y) \
2402 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2403 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2404 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2405 ? CCEQmode : CCmode))
2407 /* Define the information needed to generate branch and scc insns. This is
2408 stored from the compare operation. Note that we can't use "rtx" here
2409 since it hasn't been defined! */
2411 extern GTY(()) rtx rs6000_compare_op0;
2412 extern GTY(()) rtx rs6000_compare_op1;
2413 extern int rs6000_compare_fp_p;
2415 /* Control the assembler format that we output. */
2417 /* A C string constant describing how to begin a comment in the target
2418 assembler language. The compiler assumes that the comment will end at
2419 the end of the line. */
2420 #define ASM_COMMENT_START " #"
2422 /* Implicit library calls should use memcpy, not bcopy, etc. */
2424 #define TARGET_MEM_FUNCTIONS
2426 /* Flag to say the TOC is initialized */
2427 extern int toc_initialized;
2429 /* Macro to output a special constant pool entry. Go to WIN if we output
2430 it. Otherwise, it is written the usual way.
2432 On the RS/6000, toc entries are handled this way. */
2434 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2435 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2437 output_toc (FILE, X, LABELNO, MODE); \
2442 #ifdef HAVE_GAS_WEAK
2443 #define RS6000_WEAK 1
2445 #define RS6000_WEAK 0
2449 /* Used in lieu of ASM_WEAKEN_LABEL. */
2450 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2453 fputs ("\t.weak\t", (FILE)); \
2454 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2455 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2456 && DEFAULT_ABI == ABI_AIX) \
2459 fputs ("[DS]", (FILE)); \
2460 fputs ("\n\t.weak\t.", (FILE)); \
2461 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2463 fputc ('\n', (FILE)); \
2466 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2467 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2468 && DEFAULT_ABI == ABI_AIX) \
2470 fputs ("\t.set\t.", (FILE)); \
2471 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2472 fputs (",.", (FILE)); \
2473 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2474 fputc ('\n', (FILE)); \
2481 /* This implements the `alias' attribute. */
2482 #undef ASM_OUTPUT_DEF_FROM_DECLS
2483 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2486 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2487 const char *name = IDENTIFIER_POINTER (TARGET); \
2488 if (TREE_CODE (DECL) == FUNCTION_DECL \
2489 && DEFAULT_ABI == ABI_AIX) \
2491 if (TREE_PUBLIC (DECL)) \
2493 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2495 fputs ("\t.globl\t.", FILE); \
2496 RS6000_OUTPUT_BASENAME (FILE, alias); \
2497 putc ('\n', FILE); \
2500 else if (TARGET_XCOFF) \
2502 fputs ("\t.lglobl\t.", FILE); \
2503 RS6000_OUTPUT_BASENAME (FILE, alias); \
2504 putc ('\n', FILE); \
2506 fputs ("\t.set\t.", FILE); \
2507 RS6000_OUTPUT_BASENAME (FILE, alias); \
2508 fputs (",.", FILE); \
2509 RS6000_OUTPUT_BASENAME (FILE, name); \
2510 fputc ('\n', FILE); \
2512 ASM_OUTPUT_DEF (FILE, alias, name); \
2516 /* Output to assembler file text saying following lines
2517 may contain character constants, extra white space, comments, etc. */
2519 #define ASM_APP_ON ""
2521 /* Output to assembler file text saying following lines
2522 no longer contain unusual constructs. */
2524 #define ASM_APP_OFF ""
2526 /* How to refer to registers in assembler output.
2527 This sequence is indexed by compiler's hard-register-number (see above). */
2529 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2531 #define REGISTER_NAMES \
2533 &rs6000_reg_names[ 0][0], /* r0 */ \
2534 &rs6000_reg_names[ 1][0], /* r1 */ \
2535 &rs6000_reg_names[ 2][0], /* r2 */ \
2536 &rs6000_reg_names[ 3][0], /* r3 */ \
2537 &rs6000_reg_names[ 4][0], /* r4 */ \
2538 &rs6000_reg_names[ 5][0], /* r5 */ \
2539 &rs6000_reg_names[ 6][0], /* r6 */ \
2540 &rs6000_reg_names[ 7][0], /* r7 */ \
2541 &rs6000_reg_names[ 8][0], /* r8 */ \
2542 &rs6000_reg_names[ 9][0], /* r9 */ \
2543 &rs6000_reg_names[10][0], /* r10 */ \
2544 &rs6000_reg_names[11][0], /* r11 */ \
2545 &rs6000_reg_names[12][0], /* r12 */ \
2546 &rs6000_reg_names[13][0], /* r13 */ \
2547 &rs6000_reg_names[14][0], /* r14 */ \
2548 &rs6000_reg_names[15][0], /* r15 */ \
2549 &rs6000_reg_names[16][0], /* r16 */ \
2550 &rs6000_reg_names[17][0], /* r17 */ \
2551 &rs6000_reg_names[18][0], /* r18 */ \
2552 &rs6000_reg_names[19][0], /* r19 */ \
2553 &rs6000_reg_names[20][0], /* r20 */ \
2554 &rs6000_reg_names[21][0], /* r21 */ \
2555 &rs6000_reg_names[22][0], /* r22 */ \
2556 &rs6000_reg_names[23][0], /* r23 */ \
2557 &rs6000_reg_names[24][0], /* r24 */ \
2558 &rs6000_reg_names[25][0], /* r25 */ \
2559 &rs6000_reg_names[26][0], /* r26 */ \
2560 &rs6000_reg_names[27][0], /* r27 */ \
2561 &rs6000_reg_names[28][0], /* r28 */ \
2562 &rs6000_reg_names[29][0], /* r29 */ \
2563 &rs6000_reg_names[30][0], /* r30 */ \
2564 &rs6000_reg_names[31][0], /* r31 */ \
2566 &rs6000_reg_names[32][0], /* fr0 */ \
2567 &rs6000_reg_names[33][0], /* fr1 */ \
2568 &rs6000_reg_names[34][0], /* fr2 */ \
2569 &rs6000_reg_names[35][0], /* fr3 */ \
2570 &rs6000_reg_names[36][0], /* fr4 */ \
2571 &rs6000_reg_names[37][0], /* fr5 */ \
2572 &rs6000_reg_names[38][0], /* fr6 */ \
2573 &rs6000_reg_names[39][0], /* fr7 */ \
2574 &rs6000_reg_names[40][0], /* fr8 */ \
2575 &rs6000_reg_names[41][0], /* fr9 */ \
2576 &rs6000_reg_names[42][0], /* fr10 */ \
2577 &rs6000_reg_names[43][0], /* fr11 */ \
2578 &rs6000_reg_names[44][0], /* fr12 */ \
2579 &rs6000_reg_names[45][0], /* fr13 */ \
2580 &rs6000_reg_names[46][0], /* fr14 */ \
2581 &rs6000_reg_names[47][0], /* fr15 */ \
2582 &rs6000_reg_names[48][0], /* fr16 */ \
2583 &rs6000_reg_names[49][0], /* fr17 */ \
2584 &rs6000_reg_names[50][0], /* fr18 */ \
2585 &rs6000_reg_names[51][0], /* fr19 */ \
2586 &rs6000_reg_names[52][0], /* fr20 */ \
2587 &rs6000_reg_names[53][0], /* fr21 */ \
2588 &rs6000_reg_names[54][0], /* fr22 */ \
2589 &rs6000_reg_names[55][0], /* fr23 */ \
2590 &rs6000_reg_names[56][0], /* fr24 */ \
2591 &rs6000_reg_names[57][0], /* fr25 */ \
2592 &rs6000_reg_names[58][0], /* fr26 */ \
2593 &rs6000_reg_names[59][0], /* fr27 */ \
2594 &rs6000_reg_names[60][0], /* fr28 */ \
2595 &rs6000_reg_names[61][0], /* fr29 */ \
2596 &rs6000_reg_names[62][0], /* fr30 */ \
2597 &rs6000_reg_names[63][0], /* fr31 */ \
2599 &rs6000_reg_names[64][0], /* mq */ \
2600 &rs6000_reg_names[65][0], /* lr */ \
2601 &rs6000_reg_names[66][0], /* ctr */ \
2602 &rs6000_reg_names[67][0], /* ap */ \
2604 &rs6000_reg_names[68][0], /* cr0 */ \
2605 &rs6000_reg_names[69][0], /* cr1 */ \
2606 &rs6000_reg_names[70][0], /* cr2 */ \
2607 &rs6000_reg_names[71][0], /* cr3 */ \
2608 &rs6000_reg_names[72][0], /* cr4 */ \
2609 &rs6000_reg_names[73][0], /* cr5 */ \
2610 &rs6000_reg_names[74][0], /* cr6 */ \
2611 &rs6000_reg_names[75][0], /* cr7 */ \
2613 &rs6000_reg_names[76][0], /* xer */ \
2615 &rs6000_reg_names[77][0], /* v0 */ \
2616 &rs6000_reg_names[78][0], /* v1 */ \
2617 &rs6000_reg_names[79][0], /* v2 */ \
2618 &rs6000_reg_names[80][0], /* v3 */ \
2619 &rs6000_reg_names[81][0], /* v4 */ \
2620 &rs6000_reg_names[82][0], /* v5 */ \
2621 &rs6000_reg_names[83][0], /* v6 */ \
2622 &rs6000_reg_names[84][0], /* v7 */ \
2623 &rs6000_reg_names[85][0], /* v8 */ \
2624 &rs6000_reg_names[86][0], /* v9 */ \
2625 &rs6000_reg_names[87][0], /* v10 */ \
2626 &rs6000_reg_names[88][0], /* v11 */ \
2627 &rs6000_reg_names[89][0], /* v12 */ \
2628 &rs6000_reg_names[90][0], /* v13 */ \
2629 &rs6000_reg_names[91][0], /* v14 */ \
2630 &rs6000_reg_names[92][0], /* v15 */ \
2631 &rs6000_reg_names[93][0], /* v16 */ \
2632 &rs6000_reg_names[94][0], /* v17 */ \
2633 &rs6000_reg_names[95][0], /* v18 */ \
2634 &rs6000_reg_names[96][0], /* v19 */ \
2635 &rs6000_reg_names[97][0], /* v20 */ \
2636 &rs6000_reg_names[98][0], /* v21 */ \
2637 &rs6000_reg_names[99][0], /* v22 */ \
2638 &rs6000_reg_names[100][0], /* v23 */ \
2639 &rs6000_reg_names[101][0], /* v24 */ \
2640 &rs6000_reg_names[102][0], /* v25 */ \
2641 &rs6000_reg_names[103][0], /* v26 */ \
2642 &rs6000_reg_names[104][0], /* v27 */ \
2643 &rs6000_reg_names[105][0], /* v28 */ \
2644 &rs6000_reg_names[106][0], /* v29 */ \
2645 &rs6000_reg_names[107][0], /* v30 */ \
2646 &rs6000_reg_names[108][0], /* v31 */ \
2647 &rs6000_reg_names[109][0], /* vrsave */ \
2648 &rs6000_reg_names[110][0], /* vscr */ \
2651 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2652 following for it. Switch to use the alternate names since
2653 they are more mnemonic. */
2655 #define DEBUG_REGISTER_NAMES \
2657 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2658 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2659 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2660 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2661 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2662 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2663 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2664 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2665 "mq", "lr", "ctr", "ap", \
2666 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2668 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2669 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2670 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2671 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2675 /* Table of additional register names to use in user input. */
2677 #define ADDITIONAL_REGISTER_NAMES \
2678 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2679 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2680 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2681 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2682 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2683 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2684 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2685 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2686 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2687 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2688 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2689 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2690 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2691 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2692 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2693 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2694 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2695 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2696 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2697 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2698 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2699 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2700 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2701 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2702 {"vrsave", 109}, {"vscr", 110}, \
2703 /* no additional names for: mq, lr, ctr, ap */ \
2704 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2705 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2706 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2708 /* Text to write out after a CALL that may be replaced by glue code by
2709 the loader. This depends on the AIX version. */
2710 #define RS6000_CALL_GLUE "cror 31,31,31"
2712 /* This is how to output an element of a case-vector that is relative. */
2714 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2715 do { char buf[100]; \
2716 fputs ("\t.long ", FILE); \
2717 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2718 assemble_name (FILE, buf); \
2720 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2721 assemble_name (FILE, buf); \
2722 putc ('\n', FILE); \
2725 /* This is how to output an assembler line
2726 that says to advance the location counter
2727 to a multiple of 2**LOG bytes. */
2729 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2731 fprintf (FILE, "\t.align %d\n", (LOG))
2733 /* Store in OUTPUT a string (made with alloca) containing
2734 an assembler-name for a local static variable named NAME.
2735 LABELNO is an integer which is different for each call. */
2737 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2738 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2739 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2741 /* Pick up the return address upon entry to a procedure. Used for
2742 dwarf2 unwind information. This also enables the table driven
2745 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2746 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2748 /* Describe how we implement __builtin_eh_return. */
2749 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2750 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2752 /* Print operand X (an rtx) in assembler syntax to file FILE.
2753 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2754 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2756 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2758 /* Define which CODE values are valid. */
2760 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2763 /* Print a memory address as an operand to reference that memory location. */
2765 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2767 /* Define the codes that are matched by predicates in rs6000.c. */
2769 #define PREDICATE_CODES \
2770 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2771 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2772 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2773 LABEL_REF, SUBREG, REG, MEM}}, \
2774 {"short_cint_operand", {CONST_INT}}, \
2775 {"u_short_cint_operand", {CONST_INT}}, \
2776 {"non_short_cint_operand", {CONST_INT}}, \
2777 {"exact_log2_cint_operand", {CONST_INT}}, \
2778 {"gpc_reg_operand", {SUBREG, REG}}, \
2779 {"cc_reg_operand", {SUBREG, REG}}, \
2780 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2781 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2782 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2783 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2784 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2785 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2786 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2787 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2788 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2789 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2790 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2791 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2792 {"easy_fp_constant", {CONST_DOUBLE}}, \
2793 {"zero_fp_constant", {CONST_DOUBLE}}, \
2794 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2795 {"lwa_operand", {SUBREG, MEM, REG}}, \
2796 {"volatile_mem_operand", {MEM}}, \
2797 {"offsettable_mem_operand", {MEM}}, \
2798 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2799 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2800 {"non_add_cint_operand", {CONST_INT}}, \
2801 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2802 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2803 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2804 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2805 {"mask_operand", {CONST_INT}}, \
2806 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2807 {"count_register_operand", {REG}}, \
2808 {"xer_operand", {REG}}, \
2809 {"symbol_ref_operand", {SYMBOL_REF}}, \
2810 {"call_operand", {SYMBOL_REF, REG}}, \
2811 {"current_file_function_operand", {SYMBOL_REF}}, \
2812 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2813 CONST_DOUBLE, SYMBOL_REF}}, \
2814 {"load_multiple_operation", {PARALLEL}}, \
2815 {"store_multiple_operation", {PARALLEL}}, \
2816 {"vrsave_operation", {PARALLEL}}, \
2817 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2818 GT, LEU, LTU, GEU, GTU, \
2819 UNORDERED, ORDERED, \
2821 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2823 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2824 GT, LEU, LTU, GEU, GTU, \
2825 UNORDERED, ORDERED, \
2827 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2828 GT, LEU, LTU, GEU, GTU}}, \
2829 {"boolean_operator", {AND, IOR, XOR}}, \
2830 {"boolean_or_operator", {IOR, XOR}}, \
2831 {"altivec_register_operand", {REG}}, \
2832 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2834 /* uncomment for disabling the corresponding default options */
2835 /* #define MACHINE_no_sched_interblock */
2836 /* #define MACHINE_no_sched_speculative */
2837 /* #define MACHINE_no_sched_speculative_load */
2839 /* General flags. */
2840 extern int flag_pic;
2841 extern int optimize;
2842 extern int flag_expensive_optimizations;
2843 extern int frame_pointer_needed;
2845 enum rs6000_builtins
2847 /* AltiVec builtins. */
2848 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2849 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2850 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2851 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2852 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2853 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2854 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2855 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2856 ALTIVEC_BUILTIN_VADDUBM,
2857 ALTIVEC_BUILTIN_VADDUHM,
2858 ALTIVEC_BUILTIN_VADDUWM,
2859 ALTIVEC_BUILTIN_VADDFP,
2860 ALTIVEC_BUILTIN_VADDCUW,
2861 ALTIVEC_BUILTIN_VADDUBS,
2862 ALTIVEC_BUILTIN_VADDSBS,
2863 ALTIVEC_BUILTIN_VADDUHS,
2864 ALTIVEC_BUILTIN_VADDSHS,
2865 ALTIVEC_BUILTIN_VADDUWS,
2866 ALTIVEC_BUILTIN_VADDSWS,
2867 ALTIVEC_BUILTIN_VAND,
2868 ALTIVEC_BUILTIN_VANDC,
2869 ALTIVEC_BUILTIN_VAVGUB,
2870 ALTIVEC_BUILTIN_VAVGSB,
2871 ALTIVEC_BUILTIN_VAVGUH,
2872 ALTIVEC_BUILTIN_VAVGSH,
2873 ALTIVEC_BUILTIN_VAVGUW,
2874 ALTIVEC_BUILTIN_VAVGSW,
2875 ALTIVEC_BUILTIN_VCFUX,
2876 ALTIVEC_BUILTIN_VCFSX,
2877 ALTIVEC_BUILTIN_VCTSXS,
2878 ALTIVEC_BUILTIN_VCTUXS,
2879 ALTIVEC_BUILTIN_VCMPBFP,
2880 ALTIVEC_BUILTIN_VCMPEQUB,
2881 ALTIVEC_BUILTIN_VCMPEQUH,
2882 ALTIVEC_BUILTIN_VCMPEQUW,
2883 ALTIVEC_BUILTIN_VCMPEQFP,
2884 ALTIVEC_BUILTIN_VCMPGEFP,
2885 ALTIVEC_BUILTIN_VCMPGTUB,
2886 ALTIVEC_BUILTIN_VCMPGTSB,
2887 ALTIVEC_BUILTIN_VCMPGTUH,
2888 ALTIVEC_BUILTIN_VCMPGTSH,
2889 ALTIVEC_BUILTIN_VCMPGTUW,
2890 ALTIVEC_BUILTIN_VCMPGTSW,
2891 ALTIVEC_BUILTIN_VCMPGTFP,
2892 ALTIVEC_BUILTIN_VEXPTEFP,
2893 ALTIVEC_BUILTIN_VLOGEFP,
2894 ALTIVEC_BUILTIN_VMADDFP,
2895 ALTIVEC_BUILTIN_VMAXUB,
2896 ALTIVEC_BUILTIN_VMAXSB,
2897 ALTIVEC_BUILTIN_VMAXUH,
2898 ALTIVEC_BUILTIN_VMAXSH,
2899 ALTIVEC_BUILTIN_VMAXUW,
2900 ALTIVEC_BUILTIN_VMAXSW,
2901 ALTIVEC_BUILTIN_VMAXFP,
2902 ALTIVEC_BUILTIN_VMHADDSHS,
2903 ALTIVEC_BUILTIN_VMHRADDSHS,
2904 ALTIVEC_BUILTIN_VMLADDUHM,
2905 ALTIVEC_BUILTIN_VMRGHB,
2906 ALTIVEC_BUILTIN_VMRGHH,
2907 ALTIVEC_BUILTIN_VMRGHW,
2908 ALTIVEC_BUILTIN_VMRGLB,
2909 ALTIVEC_BUILTIN_VMRGLH,
2910 ALTIVEC_BUILTIN_VMRGLW,
2911 ALTIVEC_BUILTIN_VMSUMUBM,
2912 ALTIVEC_BUILTIN_VMSUMMBM,
2913 ALTIVEC_BUILTIN_VMSUMUHM,
2914 ALTIVEC_BUILTIN_VMSUMSHM,
2915 ALTIVEC_BUILTIN_VMSUMUHS,
2916 ALTIVEC_BUILTIN_VMSUMSHS,
2917 ALTIVEC_BUILTIN_VMINUB,
2918 ALTIVEC_BUILTIN_VMINSB,
2919 ALTIVEC_BUILTIN_VMINUH,
2920 ALTIVEC_BUILTIN_VMINSH,
2921 ALTIVEC_BUILTIN_VMINUW,
2922 ALTIVEC_BUILTIN_VMINSW,
2923 ALTIVEC_BUILTIN_VMINFP,
2924 ALTIVEC_BUILTIN_VMULEUB,
2925 ALTIVEC_BUILTIN_VMULESB,
2926 ALTIVEC_BUILTIN_VMULEUH,
2927 ALTIVEC_BUILTIN_VMULESH,
2928 ALTIVEC_BUILTIN_VMULOUB,
2929 ALTIVEC_BUILTIN_VMULOSB,
2930 ALTIVEC_BUILTIN_VMULOUH,
2931 ALTIVEC_BUILTIN_VMULOSH,
2932 ALTIVEC_BUILTIN_VNMSUBFP,
2933 ALTIVEC_BUILTIN_VNOR,
2934 ALTIVEC_BUILTIN_VOR,
2935 ALTIVEC_BUILTIN_VSEL_4SI,
2936 ALTIVEC_BUILTIN_VSEL_4SF,
2937 ALTIVEC_BUILTIN_VSEL_8HI,
2938 ALTIVEC_BUILTIN_VSEL_16QI,
2939 ALTIVEC_BUILTIN_VPERM_4SI,
2940 ALTIVEC_BUILTIN_VPERM_4SF,
2941 ALTIVEC_BUILTIN_VPERM_8HI,
2942 ALTIVEC_BUILTIN_VPERM_16QI,
2943 ALTIVEC_BUILTIN_VPKUHUM,
2944 ALTIVEC_BUILTIN_VPKUWUM,
2945 ALTIVEC_BUILTIN_VPKPX,
2946 ALTIVEC_BUILTIN_VPKUHSS,
2947 ALTIVEC_BUILTIN_VPKSHSS,
2948 ALTIVEC_BUILTIN_VPKUWSS,
2949 ALTIVEC_BUILTIN_VPKSWSS,
2950 ALTIVEC_BUILTIN_VPKUHUS,
2951 ALTIVEC_BUILTIN_VPKSHUS,
2952 ALTIVEC_BUILTIN_VPKUWUS,
2953 ALTIVEC_BUILTIN_VPKSWUS,
2954 ALTIVEC_BUILTIN_VREFP,
2955 ALTIVEC_BUILTIN_VRFIM,
2956 ALTIVEC_BUILTIN_VRFIN,
2957 ALTIVEC_BUILTIN_VRFIP,
2958 ALTIVEC_BUILTIN_VRFIZ,
2959 ALTIVEC_BUILTIN_VRLB,
2960 ALTIVEC_BUILTIN_VRLH,
2961 ALTIVEC_BUILTIN_VRLW,
2962 ALTIVEC_BUILTIN_VRSQRTEFP,
2963 ALTIVEC_BUILTIN_VSLB,
2964 ALTIVEC_BUILTIN_VSLH,
2965 ALTIVEC_BUILTIN_VSLW,
2966 ALTIVEC_BUILTIN_VSL,
2967 ALTIVEC_BUILTIN_VSLO,
2968 ALTIVEC_BUILTIN_VSPLTB,
2969 ALTIVEC_BUILTIN_VSPLTH,
2970 ALTIVEC_BUILTIN_VSPLTW,
2971 ALTIVEC_BUILTIN_VSPLTISB,
2972 ALTIVEC_BUILTIN_VSPLTISH,
2973 ALTIVEC_BUILTIN_VSPLTISW,
2974 ALTIVEC_BUILTIN_VSRB,
2975 ALTIVEC_BUILTIN_VSRH,
2976 ALTIVEC_BUILTIN_VSRW,
2977 ALTIVEC_BUILTIN_VSRAB,
2978 ALTIVEC_BUILTIN_VSRAH,
2979 ALTIVEC_BUILTIN_VSRAW,
2980 ALTIVEC_BUILTIN_VSR,
2981 ALTIVEC_BUILTIN_VSRO,
2982 ALTIVEC_BUILTIN_VSUBUBM,
2983 ALTIVEC_BUILTIN_VSUBUHM,
2984 ALTIVEC_BUILTIN_VSUBUWM,
2985 ALTIVEC_BUILTIN_VSUBFP,
2986 ALTIVEC_BUILTIN_VSUBCUW,
2987 ALTIVEC_BUILTIN_VSUBUBS,
2988 ALTIVEC_BUILTIN_VSUBSBS,
2989 ALTIVEC_BUILTIN_VSUBUHS,
2990 ALTIVEC_BUILTIN_VSUBSHS,
2991 ALTIVEC_BUILTIN_VSUBUWS,
2992 ALTIVEC_BUILTIN_VSUBSWS,
2993 ALTIVEC_BUILTIN_VSUM4UBS,
2994 ALTIVEC_BUILTIN_VSUM4SBS,
2995 ALTIVEC_BUILTIN_VSUM4SHS,
2996 ALTIVEC_BUILTIN_VSUM2SWS,
2997 ALTIVEC_BUILTIN_VSUMSWS,
2998 ALTIVEC_BUILTIN_VXOR,
2999 ALTIVEC_BUILTIN_VSLDOI_16QI,
3000 ALTIVEC_BUILTIN_VSLDOI_8HI,
3001 ALTIVEC_BUILTIN_VSLDOI_4SI,
3002 ALTIVEC_BUILTIN_VSLDOI_4SF,
3003 ALTIVEC_BUILTIN_VUPKHSB,
3004 ALTIVEC_BUILTIN_VUPKHPX,
3005 ALTIVEC_BUILTIN_VUPKHSH,
3006 ALTIVEC_BUILTIN_VUPKLSB,
3007 ALTIVEC_BUILTIN_VUPKLPX,
3008 ALTIVEC_BUILTIN_VUPKLSH,
3009 ALTIVEC_BUILTIN_MTVSCR,
3010 ALTIVEC_BUILTIN_MFVSCR,
3011 ALTIVEC_BUILTIN_DSSALL,
3012 ALTIVEC_BUILTIN_DSS,
3013 ALTIVEC_BUILTIN_LVSL,
3014 ALTIVEC_BUILTIN_LVSR,
3015 ALTIVEC_BUILTIN_DSTT,
3016 ALTIVEC_BUILTIN_DSTST,
3017 ALTIVEC_BUILTIN_DSTSTT,
3018 ALTIVEC_BUILTIN_DST,
3019 ALTIVEC_BUILTIN_LVEBX,
3020 ALTIVEC_BUILTIN_LVEHX,
3021 ALTIVEC_BUILTIN_LVEWX,
3022 ALTIVEC_BUILTIN_LVXL,
3023 ALTIVEC_BUILTIN_LVX,
3024 ALTIVEC_BUILTIN_STVX,
3025 ALTIVEC_BUILTIN_STVEBX,
3026 ALTIVEC_BUILTIN_STVEHX,
3027 ALTIVEC_BUILTIN_STVEWX,
3028 ALTIVEC_BUILTIN_STVXL,
3029 ALTIVEC_BUILTIN_VCMPBFP_P,
3030 ALTIVEC_BUILTIN_VCMPEQFP_P,
3031 ALTIVEC_BUILTIN_VCMPEQUB_P,
3032 ALTIVEC_BUILTIN_VCMPEQUH_P,
3033 ALTIVEC_BUILTIN_VCMPEQUW_P,
3034 ALTIVEC_BUILTIN_VCMPGEFP_P,
3035 ALTIVEC_BUILTIN_VCMPGTFP_P,
3036 ALTIVEC_BUILTIN_VCMPGTSB_P,
3037 ALTIVEC_BUILTIN_VCMPGTSH_P,
3038 ALTIVEC_BUILTIN_VCMPGTSW_P,
3039 ALTIVEC_BUILTIN_VCMPGTUB_P,
3040 ALTIVEC_BUILTIN_VCMPGTUH_P,
3041 ALTIVEC_BUILTIN_VCMPGTUW_P,
3042 ALTIVEC_BUILTIN_ABSS_V4SI,
3043 ALTIVEC_BUILTIN_ABSS_V8HI,
3044 ALTIVEC_BUILTIN_ABSS_V16QI,
3045 ALTIVEC_BUILTIN_ABS_V4SI,
3046 ALTIVEC_BUILTIN_ABS_V4SF,
3047 ALTIVEC_BUILTIN_ABS_V8HI,
3048 ALTIVEC_BUILTIN_ABS_V16QI
OSDN Git Service
