1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common CPP definitions used by CPP_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define CPP_CPU_SPEC \
53 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
54 %{mpower2: -D_ARCH_PWR2} \
55 %{mpowerpc*: -D_ARCH_PPC} \
56 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
57 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
58 %{mcpu=common: -D_ARCH_COM} \
59 %{mcpu=power: -D_ARCH_PWR} \
60 %{mcpu=power2: -D_ARCH_PWR2} \
61 %{mcpu=powerpc: -D_ARCH_PPC} \
62 %{mcpu=rios: -D_ARCH_PWR} \
63 %{mcpu=rios1: -D_ARCH_PWR} \
64 %{mcpu=rios2: -D_ARCH_PWR2} \
65 %{mcpu=rsc: -D_ARCH_PWR} \
66 %{mcpu=rsc1: -D_ARCH_PWR} \
67 %{mcpu=401: -D_ARCH_PPC} \
68 %{mcpu=403: -D_ARCH_PPC} \
69 %{mcpu=505: -D_ARCH_PPC} \
70 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
71 %{mcpu=602: -D_ARCH_PPC} \
72 %{mcpu=603: -D_ARCH_PPC} \
73 %{mcpu=603e: -D_ARCH_PPC} \
74 %{mcpu=ec603e: -D_ARCH_PPC} \
75 %{mcpu=604: -D_ARCH_PPC} \
76 %{mcpu=604e: -D_ARCH_PPC} \
77 %{mcpu=620: -D_ARCH_PPC} \
78 %{mcpu=740: -D_ARCH_PPC} \
79 %{mcpu=750: -D_ARCH_PPC} \
80 %{mcpu=801: -D_ARCH_PPC} \
81 %{mcpu=821: -D_ARCH_PPC} \
82 %{mcpu=823: -D_ARCH_PPC} \
83 %{mcpu=860: -D_ARCH_PPC} \
84 %{maltivec: -D__ALTIVEC__}"
86 /* Common ASM definitions used by ASM_SPEC among the various targets
87 for handling -mcpu=xxx switches. */
88 #define ASM_CPU_SPEC \
90 %{mpower: %{!mpower2: -mpwr}} \
93 %{mno-power: %{!mpowerpc*: -mcom}} \
94 %{!mno-power: %{!mpower2: %(asm_default)}}} \
95 %{mcpu=common: -mcom} \
96 %{mcpu=power: -mpwr} \
97 %{mcpu=power2: -mpwrx} \
98 %{mcpu=powerpc: -mppc} \
100 %{mcpu=rios1: -mpwr} \
101 %{mcpu=rios2: -mpwrx} \
103 %{mcpu=rsc1: -mpwr} \
110 %{mcpu=603e: -mppc} \
111 %{mcpu=ec603e: -mppc} \
113 %{mcpu=604e: -mppc} \
121 %{maltivec: -maltivec}"
123 #define CPP_DEFAULT_SPEC ""
125 #define ASM_DEFAULT_SPEC ""
127 /* This macro defines names of additional specifications to put in the specs
128 that can be used in various specifications like CC1_SPEC. Its definition
129 is an initializer with a subgrouping for each command option.
131 Each subgrouping contains a string constant, that defines the
132 specification name, and a string constant that used by the GNU CC driver
135 Do not define this macro if it does not need to do anything. */
137 #define SUBTARGET_EXTRA_SPECS
139 #define EXTRA_SPECS \
140 { "cpp_cpu", CPP_CPU_SPEC }, \
141 { "cpp_default", CPP_DEFAULT_SPEC }, \
142 { "asm_cpu", ASM_CPU_SPEC }, \
143 { "asm_default", ASM_DEFAULT_SPEC }, \
144 SUBTARGET_EXTRA_SPECS
146 /* Architecture type. */
148 extern int target_flags;
150 /* Use POWER architecture instructions and MQ register. */
151 #define MASK_POWER 0x00000001
153 /* Use POWER2 extensions to POWER architecture. */
154 #define MASK_POWER2 0x00000002
156 /* Use PowerPC architecture instructions. */
157 #define MASK_POWERPC 0x00000004
159 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
160 #define MASK_PPC_GPOPT 0x00000008
162 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
163 #define MASK_PPC_GFXOPT 0x00000010
165 /* Use PowerPC-64 architecture instructions. */
166 #define MASK_POWERPC64 0x00000020
168 /* Use revised mnemonic names defined for PowerPC architecture. */
169 #define MASK_NEW_MNEMONICS 0x00000040
171 /* Disable placing fp constants in the TOC; can be turned on when the
173 #define MASK_NO_FP_IN_TOC 0x00000080
175 /* Disable placing symbol+offset constants in the TOC; can be turned on when
176 the TOC overflows. */
177 #define MASK_NO_SUM_IN_TOC 0x00000100
179 /* Output only one TOC entry per module. Normally linking fails if
180 there are more than 16K unique variables/constants in an executable. With
181 this option, linking fails only if there are more than 16K modules, or
182 if there are more than 16K unique variables/constant in a single module.
184 This is at the cost of having 2 extra loads and one extra store per
185 function, and one less allocable register. */
186 #define MASK_MINIMAL_TOC 0x00000200
188 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
189 #define MASK_64BIT 0x00000400
191 /* Disable use of FPRs. */
192 #define MASK_SOFT_FLOAT 0x00000800
194 /* Enable load/store multiple, even on powerpc */
195 #define MASK_MULTIPLE 0x00001000
196 #define MASK_MULTIPLE_SET 0x00002000
198 /* Use string instructions for block moves */
199 #define MASK_STRING 0x00004000
200 #define MASK_STRING_SET 0x00008000
202 /* Disable update form of load/store */
203 #define MASK_NO_UPDATE 0x00010000
205 /* Disable fused multiply/add operations */
206 #define MASK_NO_FUSED_MADD 0x00020000
208 /* Nonzero if we need to schedule the prolog and epilog. */
209 #define MASK_SCHED_PROLOG 0x00040000
211 /* Use AltiVec instructions. */
212 #define MASK_ALTIVEC 0x00080000
214 /* Enhance the current ABI with AltiVec extensions. */
215 #define MASK_ALTIVEC_ABI 0x00100000
217 /* Use 128-bit long double. */
218 #define MASK_LONG_DOUBLE_128 0x00200000
220 #define TARGET_POWER (target_flags & MASK_POWER)
221 #define TARGET_POWER2 (target_flags & MASK_POWER2)
222 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
223 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
224 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
225 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
226 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
227 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
228 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
229 #define TARGET_64BIT (target_flags & MASK_64BIT)
230 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
231 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
232 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
233 #define TARGET_STRING (target_flags & MASK_STRING)
234 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
235 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
236 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
237 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
238 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
239 #define TARGET_ALTIVEC_ABI (target_flags & MASK_ALTIVEC_ABI)
240 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
242 #define TARGET_32BIT (! TARGET_64BIT)
243 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
244 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
245 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
248 /* For libgcc2 we make sure this is a compile time constant */
250 #define TARGET_POWERPC64 1
252 #define TARGET_POWERPC64 0
255 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
258 #define TARGET_XL_CALL 0
260 /* Run-time compilation parameters selecting different hardware subsets.
262 Macro to define tables used to set the flags.
263 This is a list in braces of pairs in braces,
264 each pair being { "NAME", VALUE }
265 where VALUE is the bits to set or minus the bits to clear.
266 An empty string NAME is used to identify the default VALUE. */
268 #define TARGET_SWITCHES \
269 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
270 N_("Use POWER instruction set")}, \
271 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
273 N_("Use POWER2 instruction set")}, \
274 {"no-power2", - MASK_POWER2, \
275 N_("Do not use POWER2 instruction set")}, \
276 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
278 N_("Do not use POWER instruction set")}, \
279 {"powerpc", MASK_POWERPC, \
280 N_("Use PowerPC instruction set")}, \
281 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
282 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
283 N_("Do not use PowerPC instruction set")}, \
284 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
285 N_("Use PowerPC General Purpose group optional instructions")},\
286 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
287 N_("Don't use PowerPC General Purpose group optional instructions")},\
288 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
289 N_("Use PowerPC Graphics group optional instructions")},\
290 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
291 N_("Don't use PowerPC Graphics group optional instructions")},\
292 {"powerpc64", MASK_POWERPC64, \
293 N_("Use PowerPC-64 instruction set")}, \
294 {"no-powerpc64", - MASK_POWERPC64, \
295 N_("Don't use PowerPC-64 instruction set")}, \
296 {"altivec", MASK_ALTIVEC, \
297 N_("Use AltiVec instructions.")}, \
298 {"no-altivec", - MASK_ALTIVEC, \
299 N_("Don't use AltiVec instructions.")}, \
300 {"new-mnemonics", MASK_NEW_MNEMONICS, \
301 N_("Use new mnemonics for PowerPC architecture")},\
302 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
303 N_("Use old mnemonics for PowerPC architecture")},\
304 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
305 | MASK_MINIMAL_TOC), \
306 N_("Put everything in the regular TOC")}, \
307 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
308 N_("Place floating point constants in TOC")}, \
309 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
310 N_("Don't place floating point constants in TOC")},\
311 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
312 N_("Place symbol+offset constants in TOC")}, \
313 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
314 N_("Don't place symbol+offset constants in TOC")},\
315 {"minimal-toc", MASK_MINIMAL_TOC, \
316 "Use only one TOC entry per procedure"}, \
317 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
319 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
320 N_("Place variable addresses in the regular TOC")},\
321 {"hard-float", - MASK_SOFT_FLOAT, \
322 N_("Use hardware fp")}, \
323 {"soft-float", MASK_SOFT_FLOAT, \
324 N_("Do not use hardware fp")}, \
325 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
326 N_("Generate load/store multiple instructions")}, \
327 {"no-multiple", - MASK_MULTIPLE, \
328 N_("Do not generate load/store multiple instructions")},\
329 {"no-multiple", MASK_MULTIPLE_SET, \
331 {"string", MASK_STRING | MASK_STRING_SET, \
332 N_("Generate string instructions for block moves")},\
333 {"no-string", - MASK_STRING, \
334 N_("Do not generate string instructions for block moves")},\
335 {"no-string", MASK_STRING_SET, \
337 {"update", - MASK_NO_UPDATE, \
338 N_("Generate load/store with update instructions")},\
339 {"no-update", MASK_NO_UPDATE, \
340 N_("Do not generate load/store with update instructions")},\
341 {"fused-madd", - MASK_NO_FUSED_MADD, \
342 N_("Generate fused multiply/add instructions")},\
343 {"no-fused-madd", MASK_NO_FUSED_MADD, \
344 N_("Don't generate fused multiply/add instructions")},\
345 {"long-double-64", -MASK_LONG_DOUBLE_128, \
346 N_("Use 64 bit long doubles") }, \
347 {"long-double-128", MASK_LONG_DOUBLE_128, \
348 N_("Use 128 bit long doubles") }, \
349 {"sched-prolog", MASK_SCHED_PROLOG, \
351 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
352 N_("Don't schedule the start and end of the procedure")},\
353 {"sched-epilog", MASK_SCHED_PROLOG, \
355 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
358 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
361 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
363 /* This is meant to be redefined in the host dependent files */
364 #define SUBTARGET_SWITCHES
366 /* Processor type. Order must match cpu attribute in MD file. */
385 extern enum processor_type rs6000_cpu;
387 /* Recast the processor type to the cpu attribute. */
388 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
390 /* Define generic processor types based upon current deployment. */
391 #define PROCESSOR_COMMON PROCESSOR_PPC601
392 #define PROCESSOR_POWER PROCESSOR_RIOS1
393 #define PROCESSOR_POWERPC PROCESSOR_PPC604
394 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
396 /* Define the default processor. This is overridden by other tm.h files. */
397 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
398 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
400 /* Specify the dialect of assembler to use. New mnemonics is dialect one
401 and the old mnemonics are dialect zero. */
402 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
404 /* This macro is similar to `TARGET_SWITCHES' but defines names of
405 command options that have values. Its definition is an
406 initializer with a subgrouping for each command option.
408 Each subgrouping contains a string constant, that defines the
409 fixed part of the option name, and the address of a variable.
410 The variable, type `char *', is set to the variable part of the
411 given option if the fixed part matches. The actual option name
412 is made by appending `-m' to the specified name.
414 Here is an example which defines `-mshort-data-NUMBER'. If the
415 given option is `-mshort-data-512', the variable `m88k_short_data'
416 will be set to the string `"512"'.
418 extern char *m88k_short_data;
419 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
421 /* This is meant to be overridden in target specific files. */
422 #define SUBTARGET_OPTIONS
424 #define TARGET_OPTIONS \
426 {"cpu=", &rs6000_select[1].string, \
427 N_("Use features of and schedule code for given CPU") }, \
428 {"tune=", &rs6000_select[2].string, \
429 N_("Schedule code for given CPU") }, \
430 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
431 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
435 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
436 struct rs6000_cpu_select
444 extern struct rs6000_cpu_select rs6000_select[];
447 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
448 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
449 extern int rs6000_debug_stack; /* debug stack applications */
450 extern int rs6000_debug_arg; /* debug argument handling */
452 #define TARGET_DEBUG_STACK rs6000_debug_stack
453 #define TARGET_DEBUG_ARG rs6000_debug_arg
455 /* Sometimes certain combinations of command options do not make sense
456 on a particular target machine. You can define a macro
457 `OVERRIDE_OPTIONS' to take account of this. This macro, if
458 defined, is executed once just after all the command options have
461 Don't use this macro to turn on various extra optimizations for
462 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
464 On the RS/6000 this is used to define the target cpu type. */
466 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
468 /* Define this to change the optimizations performed by default. */
469 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
471 /* Show we can debug even without a frame pointer. */
472 #define CAN_DEBUG_WITHOUT_FP
474 /* target machine storage layout */
476 /* Define to support cross compilation to an RS6000 target. */
477 #define REAL_ARITHMETIC
479 /* Define this macro if it is advisable to hold scalars in registers
480 in a wider mode than that declared by the program. In such cases,
481 the value is constrained to be within the bounds of the declared
482 type, but kept valid in the wider mode. The signedness of the
483 extension may differ from that of the type. */
485 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
486 if (GET_MODE_CLASS (MODE) == MODE_INT \
487 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
490 /* Define this if function arguments should also be promoted using the above
493 #define PROMOTE_FUNCTION_ARGS
495 /* Likewise, if the function return value is promoted. */
497 #define PROMOTE_FUNCTION_RETURN
499 /* Define this if most significant bit is lowest numbered
500 in instructions that operate on numbered bit-fields. */
501 /* That is true on RS/6000. */
502 #define BITS_BIG_ENDIAN 1
504 /* Define this if most significant byte of a word is the lowest numbered. */
505 /* That is true on RS/6000. */
506 #define BYTES_BIG_ENDIAN 1
508 /* Define this if most significant word of a multiword number is lowest
511 For RS/6000 we can decide arbitrarily since there are no machine
512 instructions for them. Might as well be consistent with bits and bytes. */
513 #define WORDS_BIG_ENDIAN 1
515 /* number of bits in an addressable storage unit */
516 #define BITS_PER_UNIT 8
518 /* Width in bits of a "word", which is the contents of a machine register.
519 Note that this is not necessarily the width of data type `int';
520 if using 16-bit ints on a 68000, this would still be 32.
521 But on a machine with 16-bit registers, this would be 16. */
522 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
523 #define MAX_BITS_PER_WORD 64
525 /* Width of a word, in units (bytes). */
526 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
527 #define MIN_UNITS_PER_WORD 4
528 #define UNITS_PER_FP_WORD 8
529 #define UNITS_PER_ALTIVEC_WORD 16
531 /* Type used for ptrdiff_t, as a string used in a declaration. */
532 #define PTRDIFF_TYPE "int"
534 /* Type used for size_t, as a string used in a declaration. */
535 #define SIZE_TYPE "long unsigned int"
537 /* Type used for wchar_t, as a string used in a declaration. */
538 #define WCHAR_TYPE "short unsigned int"
540 /* Width of wchar_t in bits. */
541 #define WCHAR_TYPE_SIZE 16
543 /* A C expression for the size in bits of the type `short' on the
544 target machine. If you don't define this, the default is half a
545 word. (If this would be less than one storage unit, it is
546 rounded up to one unit.) */
547 #define SHORT_TYPE_SIZE 16
549 /* A C expression for the size in bits of the type `int' on the
550 target machine. If you don't define this, the default is one
552 #define INT_TYPE_SIZE 32
554 /* A C expression for the size in bits of the type `long' on the
555 target machine. If you don't define this, the default is one
557 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
558 #define MAX_LONG_TYPE_SIZE 64
560 /* A C expression for the size in bits of the type `long long' on the
561 target machine. If you don't define this, the default is two
563 #define LONG_LONG_TYPE_SIZE 64
565 /* A C expression for the size in bits of the type `char' on the
566 target machine. If you don't define this, the default is one
567 quarter of a word. (If this would be less than one storage unit,
568 it is rounded up to one unit.) */
569 #define CHAR_TYPE_SIZE BITS_PER_UNIT
571 /* A C expression for the size in bits of the type `float' on the
572 target machine. If you don't define this, the default is one
574 #define FLOAT_TYPE_SIZE 32
576 /* A C expression for the size in bits of the type `double' on the
577 target machine. If you don't define this, the default is two
579 #define DOUBLE_TYPE_SIZE 64
581 /* A C expression for the size in bits of the type `long double' on
582 the target machine. If you don't define this, the default is two
584 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
586 /* Constant which presents upper bound of the above value. */
587 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
589 /* Define this to set long double type size to use in libgcc2.c, which can
590 not depend on target_flags. */
591 #ifdef __LONG_DOUBLE_128__
592 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
594 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
597 /* Width in bits of a pointer.
598 See also the macro `Pmode' defined below. */
599 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
601 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
602 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
604 /* Boundary (in *bits*) on which stack pointer should be aligned. */
605 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
607 /* Allocation boundary (in *bits*) for the code of a function. */
608 #define FUNCTION_BOUNDARY 32
610 /* No data type wants to be aligned rounder than this. */
611 #define BIGGEST_ALIGNMENT 128
613 /* A C expression to compute the alignment for a variables in the
614 local store. TYPE is the data type, and ALIGN is the alignment
615 that the object would ordinarily have. */
616 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
618 && TREE_CODE (TYPE)) == VECTOR_TYPE ? 128 : ALIGN)
620 /* Handle #pragma pack. */
621 #define HANDLE_PRAGMA_PACK 1
623 /* Alignment of field after `int : 0' in a structure. */
624 #define EMPTY_FIELD_BOUNDARY 32
626 /* Every structure's size must be a multiple of this. */
627 #define STRUCTURE_SIZE_BOUNDARY 8
629 /* A bitfield declared as `int' forces `int' alignment for the struct. */
630 #define PCC_BITFIELD_TYPE_MATTERS 1
632 /* Make strings word-aligned so strcpy from constants will be faster. */
633 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
634 (TREE_CODE (EXP) == STRING_CST \
635 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
637 /* Make arrays of chars word-aligned for the same reasons.
638 Align vectors to 128 bits. */
639 #define DATA_ALIGNMENT(TYPE, ALIGN) \
640 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
641 : TREE_CODE (TYPE) == ARRAY_TYPE \
642 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
643 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
645 /* Non-zero if move instructions will actually fail to work
646 when given unaligned data. */
647 #define STRICT_ALIGNMENT 0
649 /* Define this macro to be the value 1 if unaligned accesses have a cost
650 many times greater than aligned accesses, for example if they are
651 emulated in a trap handler. */
652 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
654 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
655 && (ALIGN) < 32)) ? 1 : 0)
657 /* Standard register usage. */
659 /* Number of actual hardware registers.
660 The hardware registers are assigned numbers for the compiler
661 from 0 to just below FIRST_PSEUDO_REGISTER.
662 All registers that the compiler knows about must be given numbers,
663 even those that are not normally considered general registers.
665 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
666 an MQ register, a count register, a link register, and 8 condition
667 register fields, which we view here as separate registers.
669 In addition, the difference between the frame and argument pointers is
670 a function of the number of registers saved, so we need to have a
671 register for AP that will later be eliminated in favor of SP or FP.
672 This is a normal register, but it is fixed.
674 We also create a pseudo register for float/int conversions, that will
675 really represent the memory location used. It is represented here as
676 a register, in order to work around problems in allocating stack storage
677 in inline functions. */
679 #define FIRST_PSEUDO_REGISTER 110
681 /* This must not decrease, for backwards compatibility. If
682 FIRST_PSEUDO_REGISTER increases, this should as well. */
683 /* fixme: this needs to be defined to "TARGET_ALTIVEC_ABI ? 110 : 77"
684 and then fix usages of DWARF_FRAME_REGISTERS to work. */
685 #define DWARF_FRAME_REGISTERS 77
687 /* 1 for registers that have pervasive standard uses
688 and are not available for the register allocator.
690 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
691 as a local register; for all other OS's r2 is the TOC pointer.
693 cr5 is not supposed to be used.
695 On System V implementations, r13 is fixed and not available for use. */
697 #define FIXED_REGISTERS \
698 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
699 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
702 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
703 /* AltiVec registers. */ \
704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
709 /* 1 for registers not available across function calls.
710 These must include the FIXED_REGISTERS and also any
711 registers that can be used without being saved.
712 The latter must include the registers where values are returned
713 and the register where structure-value addresses are passed.
714 Aside from that, you can include as many other registers as you like. */
716 #define CALL_USED_REGISTERS \
717 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
719 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
721 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
722 /* AltiVec registers. */ \
723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
728 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
729 the entire set of `FIXED_REGISTERS' be included.
730 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
731 This macro is optional. If not specified, it defaults to the value
732 of `CALL_USED_REGISTERS'. */
734 #define CALL_REALLY_USED_REGISTERS \
735 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
736 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
737 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
739 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
740 /* AltiVec registers. */ \
741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
752 #define MAX_CR_REGNO 75
754 #define FIRST_ALTIVEC_REGNO 77
755 #define LAST_ALTIVEC_REGNO 108
756 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO)
757 #define VRSAVE_REGNO 109
759 /* List the order in which to allocate registers. Each register must be
760 listed once, even those in FIXED_REGISTERS.
762 We allocate in the following order:
763 fp0 (not saved or used for anything)
764 fp13 - fp2 (not saved; incoming fp arg registers)
765 fp1 (not saved; return value)
766 fp31 - fp14 (saved; order given to save least number)
767 cr7, cr6 (not saved or special)
768 cr1 (not saved, but used for FP operations)
769 cr0 (not saved, but used for arithmetic operations)
770 cr4, cr3, cr2 (saved)
771 r0 (not saved; cannot be base reg)
772 r9 (not saved; best for TImode)
773 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
774 r3 (not saved; return value register)
775 r31 - r13 (saved; order given to save least number)
776 r12 (not saved; if used for DImode or DFmode would use r13)
777 mq (not saved; best to use it if we can)
778 ctr (not saved; when we have the choice ctr is better)
780 cr5, r1, r2, ap, xer, vrsave (fixed)
783 v0 - v1 (not saved or used for anything)
784 v13 - v3 (not saved; incoming vector arg registers)
785 v2 (not saved; incoming vector arg reg; return value)
786 v19 - v14 (not saved or used for anything)
787 v31 - v20 (saved; order given to save least number)
791 #define REG_ALLOC_ORDER \
793 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
795 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
796 50, 49, 48, 47, 46, \
797 75, 74, 69, 68, 72, 71, 70, \
799 9, 11, 10, 8, 7, 6, 5, 4, \
801 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
802 18, 17, 16, 15, 14, 13, 12, \
805 /* AltiVec registers. */ \
807 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
809 96, 95, 94, 93, 92, 91, \
810 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
814 /* True if register is floating-point. */
815 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
817 /* True if register is a condition register. */
818 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
820 /* True if register is a condition register, but not cr0. */
821 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
823 /* True if register is an integer register. */
824 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
826 /* True if register is the XER register. */
827 #define XER_REGNO_P(N) ((N) == XER_REGNO)
829 /* True if register is an AltiVec register. */
830 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
832 /* Return number of consecutive hard regs needed starting at reg REGNO
833 to hold something of mode MODE.
834 This is ordinarily the length in words of a value of mode MODE
835 but can be less for certain modes in special long registers.
837 POWER and PowerPC GPRs hold 32 bits worth;
838 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
840 #define HARD_REGNO_NREGS(REGNO, MODE) \
841 (FP_REGNO_P (REGNO) \
842 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
843 : ALTIVEC_REGNO_P (REGNO) \
844 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
845 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
847 #define ALTIVEC_VECTOR_MODE(MODE) \
848 ((MODE) == V16QImode \
849 || (MODE) == V8HImode \
850 || (MODE) == V4SFmode \
851 || (MODE) == V4SImode)
853 /* Define this macro to be nonzero if the port is prepared to handle
854 insns involving vector mode MODE. At the very least, it must have
855 move patterns for this mode. */
857 #define VECTOR_MODE_SUPPORTED_P(MODE) \
858 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
860 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
861 For POWER and PowerPC, the GPRs can hold any mode, but the float
862 registers only can hold floating modes and DImode, and CR register only
863 can hold CC modes. We cannot put TImode anywhere except general
864 register and it must be able to fit within the register set. */
866 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
867 (FP_REGNO_P (REGNO) ? \
868 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
869 || (GET_MODE_CLASS (MODE) == MODE_INT \
870 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
871 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
872 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
873 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
874 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
875 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
878 /* Value is 1 if it is a good idea to tie two pseudo registers
879 when one has mode MODE1 and one has mode MODE2.
880 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
881 for any hard reg, then this must be 0 for correct output. */
882 #define MODES_TIEABLE_P(MODE1, MODE2) \
883 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
884 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
885 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
886 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
887 : GET_MODE_CLASS (MODE1) == MODE_CC \
888 ? GET_MODE_CLASS (MODE2) == MODE_CC \
889 : GET_MODE_CLASS (MODE2) == MODE_CC \
890 ? GET_MODE_CLASS (MODE1) == MODE_CC \
891 : ALTIVEC_VECTOR_MODE (MODE1) \
892 ? ALTIVEC_VECTOR_MODE (MODE2) \
893 : ALTIVEC_VECTOR_MODE (MODE2) \
894 ? ALTIVEC_VECTOR_MODE (MODE1) \
897 /* A C expression returning the cost of moving data from a register of class
898 CLASS1 to one of CLASS2.
900 On the RS/6000, copying between floating-point and fixed-point
901 registers is expensive. */
903 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
904 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
905 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
906 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
907 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
908 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
909 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
910 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
911 || (CLASS1) == LINK_OR_CTR_REGS) \
912 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
913 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
914 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
917 /* A C expressions returning the cost of moving data of MODE from a register to
920 On the RS/6000, bump this up a bit. */
922 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
923 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
924 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
928 /* Specify the cost of a branch insn; roughly the number of extra insns that
929 should be added to avoid a branch.
931 Set this to 3 on the RS/6000 since that is roughly the average cost of an
932 unscheduled conditional branch. */
934 #define BRANCH_COST 3
936 /* Define this macro to change register usage conditional on target flags.
937 Set MQ register fixed (already call_used) if not POWER architecture
938 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
939 64-bit AIX reserves GPR13 for thread-private data.
940 Conditionally disable FPRs. */
942 #define CONDITIONAL_REGISTER_USAGE \
945 if (! TARGET_POWER) \
946 fixed_regs[64] = 1; \
948 fixed_regs[13] = call_used_regs[13] \
949 = call_really_used_regs[13] = 1; \
950 if (TARGET_SOFT_FLOAT) \
951 for (i = 32; i < 64; i++) \
952 fixed_regs[i] = call_used_regs[i] \
953 = call_really_used_regs[i] = 1; \
954 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) \
955 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
956 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
957 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
958 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
959 global_regs[PIC_OFFSET_TABLE_REGNUM] \
960 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
961 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
962 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
963 if (! TARGET_ALTIVEC) \
964 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
965 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
966 if (TARGET_ALTIVEC_ABI) \
967 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
968 call_used_regs[i] = call_really_used_regs[i] = 1; \
971 /* Specify the registers used for certain standard purposes.
972 The values of these macros are register numbers. */
974 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
975 /* #define PC_REGNUM */
977 /* Register to use for pushing function arguments. */
978 #define STACK_POINTER_REGNUM 1
980 /* Base register for access to local variables of the function. */
981 #define FRAME_POINTER_REGNUM 31
983 /* Value should be nonzero if functions must have frame pointers.
984 Zero means the frame pointer need not be set up (and parms
985 may be accessed via the stack pointer) in functions that seem suitable.
986 This is computed in `reload', in reload1.c. */
987 #define FRAME_POINTER_REQUIRED 0
989 /* Base register for access to arguments of the function. */
990 #define ARG_POINTER_REGNUM 67
992 /* Place to put static chain when calling a function that requires it. */
993 #define STATIC_CHAIN_REGNUM 11
995 /* Link register number. */
996 #define LINK_REGISTER_REGNUM 65
998 /* Count register number. */
999 #define COUNT_REGISTER_REGNUM 66
1001 /* Place that structure value return address is placed.
1003 On the RS/6000, it is passed as an extra parameter. */
1004 #define STRUCT_VALUE 0
1006 /* Define the classes of registers for register constraints in the
1007 machine description. Also define ranges of constants.
1009 One of the classes must always be named ALL_REGS and include all hard regs.
1010 If there is more than one class, another class must be named NO_REGS
1011 and contain no registers.
1013 The name GENERAL_REGS must be the name of a class (or an alias for
1014 another name such as ALL_REGS). This is the class of registers
1015 that is allowed by "g" or "r" in a register constraint.
1016 Also, registers outside this class are allocated only when
1017 instructions express preferences for them.
1019 The classes must be numbered in nondecreasing order; that is,
1020 a larger-numbered class must never be contained completely
1021 in a smaller-numbered class.
1023 For any two classes, it is very desirable that there be another
1024 class that represents their union. */
1026 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1027 and condition registers, plus three special registers, MQ, CTR, and the
1030 However, r0 is special in that it cannot be used as a base register.
1031 So make a class for registers valid as base registers.
1033 Also, cr0 is the only condition code register that can be used in
1034 arithmetic insns, so make a separate class for it. */
1059 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1061 /* Give names of register classes as strings for dump file. */
1063 #define REG_CLASS_NAMES \
1071 "NON_SPECIAL_REGS", \
1075 "LINK_OR_CTR_REGS", \
1077 "SPEC_OR_GEN_REGS", \
1085 /* Define which registers fit in which classes.
1086 This is an initializer for a vector of HARD_REG_SET
1087 of length N_REG_CLASSES. */
1089 #define REG_CLASS_CONTENTS \
1091 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1092 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1093 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1094 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1095 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1096 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1097 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1098 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1099 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1100 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1101 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1102 { 0x00000000, 0x00000000, 0x00000007, 0x00000000 }, /* SPECIAL_REGS */ \
1103 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1104 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1105 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1106 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1107 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1108 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1111 /* The same information, inverted:
1112 Return the class number of the smallest class containing
1113 reg number REGNO. This could be a conditional expression
1114 or could index an array. */
1116 #define REGNO_REG_CLASS(REGNO) \
1117 ((REGNO) == 0 ? GENERAL_REGS \
1118 : (REGNO) < 32 ? BASE_REGS \
1119 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1120 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1121 : (REGNO) == CR0_REGNO ? CR0_REGS \
1122 : CR_REGNO_P (REGNO) ? CR_REGS \
1123 : (REGNO) == MQ_REGNO ? MQ_REGS \
1124 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1125 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1126 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1127 : (REGNO) == XER_REGNO ? XER_REGS \
1128 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1131 /* The class value for index registers, and the one for base regs. */
1132 #define INDEX_REG_CLASS GENERAL_REGS
1133 #define BASE_REG_CLASS BASE_REGS
1135 /* Get reg_class from a letter such as appears in the machine description. */
1137 #define REG_CLASS_FROM_LETTER(C) \
1138 ((C) == 'f' ? FLOAT_REGS \
1139 : (C) == 'b' ? BASE_REGS \
1140 : (C) == 'h' ? SPECIAL_REGS \
1141 : (C) == 'q' ? MQ_REGS \
1142 : (C) == 'c' ? CTR_REGS \
1143 : (C) == 'l' ? LINK_REGS \
1144 : (C) == 'v' ? ALTIVEC_REGS \
1145 : (C) == 'x' ? CR0_REGS \
1146 : (C) == 'y' ? CR_REGS \
1147 : (C) == 'z' ? XER_REGS \
1150 /* The letters I, J, K, L, M, N, and P in a register constraint string
1151 can be used to stand for particular ranges of immediate operands.
1152 This macro defines what the ranges are.
1153 C is the letter, and VALUE is a constant value.
1154 Return 1 if VALUE is in the range specified by C.
1156 `I' is a signed 16-bit constant
1157 `J' is a constant with only the high-order 16 bits non-zero
1158 `K' is a constant with only the low-order 16 bits non-zero
1159 `L' is a signed 16-bit constant shifted left 16 bits
1160 `M' is a constant that is greater than 31
1161 `N' is a positive constant that is an exact power of two
1162 `O' is the constant zero
1163 `P' is a constant whose negation is a signed 16-bit constant */
1165 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1166 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1167 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1168 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1169 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1170 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1171 : (C) == 'M' ? (VALUE) > 31 \
1172 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1173 : (C) == 'O' ? (VALUE) == 0 \
1174 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1177 /* Similar, but for floating constants, and defining letters G and H.
1178 Here VALUE is the CONST_DOUBLE rtx itself.
1180 We flag for special constants when we can copy the constant into
1181 a general register in two insns for DF/DI and one insn for SF.
1183 'H' is used for DI/DF constants that take 3 insns. */
1185 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1186 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1187 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1188 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1191 /* Optional extra constraints for this machine.
1193 'Q' means that is a memory operand that is just an offset from a reg.
1194 'R' is for AIX TOC entries.
1195 'S' is a constant that can be placed into a 64-bit mask operand
1196 'T' is a consatnt that can be placed into a 32-bit mask operand
1197 'U' is for V.4 small data references. */
1199 #define EXTRA_CONSTRAINT(OP, C) \
1200 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1201 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1202 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1203 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1204 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1205 && small_data_operand (OP, GET_MODE (OP))) \
1208 /* Given an rtx X being reloaded into a reg required to be
1209 in class CLASS, return the class of reg to actually use.
1210 In general this is just CLASS; but on some machines
1211 in some cases it is preferable to use a more restrictive class.
1213 On the RS/6000, we have to return NO_REGS when we want to reload a
1214 floating-point CONST_DOUBLE to force it to be copied to memory.
1216 We also don't want to reload integer values into floating-point
1217 registers if we can at all help it. In fact, this can
1218 cause reload to abort, if it tries to generate a reload of CTR
1219 into a FP register and discovers it doesn't have the memory location
1222 ??? Would it be a good idea to have reload do the converse, that is
1223 try to reload floating modes into FP registers if possible?
1226 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1227 (((GET_CODE (X) == CONST_DOUBLE \
1228 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1230 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1231 && (CLASS) == NON_SPECIAL_REGS) \
1235 /* Return the register class of a scratch register needed to copy IN into
1236 or out of a register in CLASS in MODE. If it can be done directly,
1237 NO_REGS is returned. */
1239 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1240 secondary_reload_class (CLASS, MODE, IN)
1242 /* If we are copying between FP or AltiVec registers and anything
1243 else, we need a memory location. */
1245 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1246 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1247 || (CLASS2) == FLOAT_REGS \
1248 || (CLASS1) == ALTIVEC_REGS \
1249 || (CLASS2) == ALTIVEC_REGS))
1251 /* Return the maximum number of consecutive registers
1252 needed to represent mode MODE in a register of class CLASS.
1254 On RS/6000, this is the size of MODE in words,
1255 except in the FP regs, where a single reg is enough for two words. */
1256 #define CLASS_MAX_NREGS(CLASS, MODE) \
1257 (((CLASS) == FLOAT_REGS) \
1258 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1259 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1261 /* If defined, gives a class of registers that cannot be used as the
1262 operand of a SUBREG that changes the mode of the object illegally. */
1264 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1266 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1268 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1269 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1271 /* Stack layout; function entry, exit and calling. */
1273 /* Enumeration to give which calling sequence to use. */
1276 ABI_AIX, /* IBM's AIX */
1277 ABI_AIX_NODESC, /* AIX calling sequence minus
1278 function descriptors */
1279 ABI_V4, /* System V.4/eabi */
1280 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1283 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1285 /* Structure used to define the rs6000 stack */
1286 typedef struct rs6000_stack {
1287 int first_gp_reg_save; /* first callee saved GP register used */
1288 int first_fp_reg_save; /* first callee saved FP register used */
1289 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1290 int lr_save_p; /* true if the link reg needs to be saved */
1291 int cr_save_p; /* true if the CR reg needs to be saved */
1292 unsigned int vrsave_mask; /* mask of vec registers to save */
1293 int toc_save_p; /* true if the TOC needs to be saved */
1294 int push_p; /* true if we need to allocate stack space */
1295 int calls_p; /* true if the function makes any calls */
1296 enum rs6000_abi abi; /* which ABI to use */
1297 int gp_save_offset; /* offset to save GP regs from initial SP */
1298 int fp_save_offset; /* offset to save FP regs from initial SP */
1299 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */
1300 int lr_save_offset; /* offset to save LR from initial SP */
1301 int cr_save_offset; /* offset to save CR from initial SP */
1302 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1303 int toc_save_offset; /* offset to save the TOC pointer */
1304 int varargs_save_offset; /* offset to save the varargs registers */
1305 int ehrd_offset; /* offset to EH return data */
1306 int reg_size; /* register size (4 or 8) */
1307 int varargs_size; /* size to hold V.4 args passed in regs */
1308 int vars_size; /* variable save area size */
1309 int parm_size; /* outgoing parameter size */
1310 int save_size; /* save area size */
1311 int fixed_size; /* fixed size of stack frame */
1312 int gp_size; /* size of saved GP registers */
1313 int fp_size; /* size of saved FP registers */
1314 int altivec_size; /* size of saved AltiVec registers */
1315 int cr_size; /* size to hold CR if not in save_size */
1316 int lr_size; /* size to hold LR if not in save_size */
1317 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1318 int altivec_padding_size; /* size of altivec alignment padding if
1320 int toc_size; /* size to hold TOC if not in save_size */
1321 int total_size; /* total bytes allocated for stack */
1324 /* Define this if pushing a word on the stack
1325 makes the stack pointer a smaller address. */
1326 #define STACK_GROWS_DOWNWARD
1328 /* Define this if the nominal address of the stack frame
1329 is at the high-address end of the local variables;
1330 that is, each additional local variable allocated
1331 goes at a more negative offset in the frame.
1333 On the RS/6000, we grow upwards, from the area after the outgoing
1335 /* #define FRAME_GROWS_DOWNWARD */
1337 /* Size of the outgoing register save area */
1338 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1339 || DEFAULT_ABI == ABI_AIX_NODESC \
1340 || DEFAULT_ABI == ABI_DARWIN) \
1341 ? (TARGET_64BIT ? 64 : 32) \
1344 /* Size of the fixed area on the stack */
1345 #define RS6000_SAVE_AREA \
1346 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1347 << (TARGET_64BIT ? 1 : 0))
1349 /* MEM representing address to save the TOC register */
1350 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1351 plus_constant (stack_pointer_rtx, \
1352 (TARGET_32BIT ? 20 : 40)))
1354 /* Size of the V.4 varargs area if needed */
1355 #define RS6000_VARARGS_AREA 0
1357 /* Align an address */
1358 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1360 /* Size of V.4 varargs area in bytes */
1361 #define RS6000_VARARGS_SIZE \
1362 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1364 /* Offset within stack frame to start allocating local variables at.
1365 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1366 first local allocated. Otherwise, it is the offset to the BEGINNING
1367 of the first local allocated.
1369 On the RS/6000, the frame pointer is the same as the stack pointer,
1370 except for dynamic allocations. So we start after the fixed area and
1371 outgoing parameter area. */
1373 #define STARTING_FRAME_OFFSET \
1374 (RS6000_ALIGN (current_function_outgoing_args_size, \
1375 TARGET_ALTIVEC ? 16 : 8) \
1376 + RS6000_VARARGS_AREA \
1379 /* Offset from the stack pointer register to an item dynamically
1380 allocated on the stack, e.g., by `alloca'.
1382 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1383 length of the outgoing arguments. The default is correct for most
1384 machines. See `function.c' for details. */
1385 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1386 (RS6000_ALIGN (current_function_outgoing_args_size, \
1387 TARGET_ALTIVEC ? 16 : 8) \
1388 + (STACK_POINTER_OFFSET))
1390 /* If we generate an insn to push BYTES bytes,
1391 this says how many the stack pointer really advances by.
1392 On RS/6000, don't define this because there are no push insns. */
1393 /* #define PUSH_ROUNDING(BYTES) */
1395 /* Offset of first parameter from the argument pointer register value.
1396 On the RS/6000, we define the argument pointer to the start of the fixed
1398 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1400 /* Offset from the argument pointer register value to the top of
1401 stack. This is different from FIRST_PARM_OFFSET because of the
1402 register save area. */
1403 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1405 /* Define this if stack space is still allocated for a parameter passed
1406 in a register. The value is the number of bytes allocated to this
1408 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1410 /* Define this if the above stack space is to be considered part of the
1411 space allocated by the caller. */
1412 #define OUTGOING_REG_PARM_STACK_SPACE
1414 /* This is the difference between the logical top of stack and the actual sp.
1416 For the RS/6000, sp points past the fixed area. */
1417 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1419 /* Define this if the maximum size of all the outgoing args is to be
1420 accumulated and pushed during the prologue. The amount can be
1421 found in the variable current_function_outgoing_args_size. */
1422 #define ACCUMULATE_OUTGOING_ARGS 1
1424 /* Value is the number of bytes of arguments automatically
1425 popped when returning from a subroutine call.
1426 FUNDECL is the declaration node of the function (as a tree),
1427 FUNTYPE is the data type of the function (as a tree),
1428 or for a library call it is an identifier node for the subroutine name.
1429 SIZE is the number of bytes of arguments passed on the stack. */
1431 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1433 /* Define how to find the value returned by a function.
1434 VALTYPE is the data type of the value (as a tree).
1435 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1436 otherwise, FUNC is 0.
1438 On RS/6000 an integer value is in r3 and a floating-point value is in
1439 fp1, unless -msoft-float. */
1441 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1442 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1443 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1444 || POINTER_TYPE_P (VALTYPE) \
1445 ? word_mode : TYPE_MODE (VALTYPE), \
1446 TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
1447 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1448 ? FP_ARG_RETURN : GP_ARG_RETURN)
1450 /* Define how to find the value returned by a library function
1451 assuming the value has mode MODE. */
1453 #define LIBCALL_VALUE(MODE) \
1454 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1455 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1456 && TARGET_HARD_FLOAT \
1457 ? FP_ARG_RETURN : GP_ARG_RETURN)
1459 /* The definition of this macro implies that there are cases where
1460 a scalar value cannot be returned in registers.
1462 For the RS/6000, any structure or union type is returned in memory.
1463 (FIXME: Except for V.4, where those <= 8 bytes are returned in
1464 registers. Can't change this without breaking compatibility.) */
1466 #define RETURN_IN_MEMORY(TYPE) AGGREGATE_TYPE_P (TYPE)
1468 /* Let RETURN_IN_MEMORY control what happens. */
1469 #define DEFAULT_PCC_STRUCT_RETURN 0
1471 /* Mode of stack savearea.
1472 FUNCTION is VOIDmode because calling convention maintains SP.
1473 BLOCK needs Pmode for SP.
1474 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1475 #define STACK_SAVEAREA_MODE(LEVEL) \
1476 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1477 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1479 /* Minimum and maximum general purpose registers used to hold arguments. */
1480 #define GP_ARG_MIN_REG 3
1481 #define GP_ARG_MAX_REG 10
1482 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1484 /* Minimum and maximum floating point registers used to hold arguments. */
1485 #define FP_ARG_MIN_REG 33
1486 #define FP_ARG_AIX_MAX_REG 45
1487 #define FP_ARG_V4_MAX_REG 40
1488 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1489 || DEFAULT_ABI == ABI_AIX_NODESC \
1490 || DEFAULT_ABI == ABI_DARWIN) \
1491 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1492 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1494 /* Minimum and maximum AltiVec registers used to hold arguments. */
1495 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1496 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1497 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1499 /* Return registers */
1500 #define GP_ARG_RETURN GP_ARG_MIN_REG
1501 #define FP_ARG_RETURN FP_ARG_MIN_REG
1502 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1504 /* Flags for the call/call_value rtl operations set up by function_arg */
1505 #define CALL_NORMAL 0x00000000 /* no special processing */
1506 /* Bits in 0x00000001 are unused. */
1507 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1508 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1509 #define CALL_LONG 0x00000008 /* always call indirect */
1511 /* 1 if N is a possible register number for a function value
1512 as seen by the caller.
1514 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1515 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1516 || ((N) == FP_ARG_RETURN) \
1517 || (TARGET_ALTIVEC && \
1518 (N) == ALTIVEC_ARG_RETURN))
1520 /* 1 if N is a possible register number for function argument passing.
1521 On RS/6000, these are r3-r10 and fp1-fp13.
1522 On AltiVec, v2 - v13 are used for passing vectors. */
1523 #define FUNCTION_ARG_REGNO_P(N) \
1524 ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1525 || (TARGET_ALTIVEC && \
1526 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_MAX_REG)) \
1527 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1530 /* A C structure for machine-specific, per-function data.
1531 This is added to the cfun structure. */
1532 typedef struct machine_function
1534 /* Whether a System V.4 varargs area was created. */
1536 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1537 int ra_needs_full_frame;
1540 /* Define a data type for recording info about an argument list
1541 during the scan of that argument list. This data type should
1542 hold all necessary information about the function itself
1543 and about the args processed so far, enough to enable macros
1544 such as FUNCTION_ARG to determine where the next arg should go.
1546 On the RS/6000, this is a structure. The first element is the number of
1547 total argument words, the second is used to store the next
1548 floating-point register number, and the third says how many more args we
1549 have prototype types for.
1551 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1552 the next availible GP register, `fregno' is the next available FP
1553 register, and `words' is the number of words used on the stack.
1555 The varargs/stdarg support requires that this structure's size
1556 be a multiple of sizeof(int). */
1558 typedef struct rs6000_args
1560 int words; /* # words used for passing GP registers */
1561 int fregno; /* next available FP register */
1562 int vregno; /* next available AltiVec register */
1563 int nargs_prototype; /* # args left in the current prototype */
1564 int orig_nargs; /* Original value of nargs_prototype */
1565 int prototype; /* Whether a prototype was defined */
1566 int call_cookie; /* Do special things for this call */
1567 int sysv_gregno; /* next available GP register */
1570 /* Define intermediate macro to compute the size (in registers) of an argument
1573 #define RS6000_ARG_SIZE(MODE, TYPE) \
1574 ((MODE) != BLKmode \
1575 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1576 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1577 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1579 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1580 for a call to a function whose data type is FNTYPE.
1581 For a library call, FNTYPE is 0. */
1583 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1584 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1586 /* Similar, but when scanning the definition of a procedure. We always
1587 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1589 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1590 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1592 /* Update the data in CUM to advance over an argument
1593 of mode MODE and data type TYPE.
1594 (TYPE is null for libcalls where that information may not be available.) */
1596 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1597 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1599 /* Non-zero if we can use a floating-point register to pass this arg. */
1600 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1601 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1602 && (CUM).fregno <= FP_ARG_MAX_REG \
1603 && TARGET_HARD_FLOAT)
1605 /* Non-zero if we can use an AltiVec register to pass this arg. */
1606 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1607 (ALTIVEC_VECTOR_MODE (MODE) \
1608 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1609 && TARGET_ALTIVEC_ABI)
1611 /* Determine where to put an argument to a function.
1612 Value is zero to push the argument on the stack,
1613 or a hard register in which to store the argument.
1615 MODE is the argument's machine mode.
1616 TYPE is the data type of the argument (as a tree).
1617 This is null for libcalls where that information may
1619 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1620 the preceding args and about the function being called.
1621 NAMED is nonzero if this argument is a named parameter
1622 (otherwise it is an extra parameter matching an ellipsis).
1624 On RS/6000 the first eight words of non-FP are normally in registers
1625 and the rest are pushed. The first 13 FP args are in registers.
1627 If this is floating-point and no prototype is specified, we use
1628 both an FP and integer register (or possibly FP reg and stack). Library
1629 functions (when TYPE is zero) always have the proper types for args,
1630 so we can pass the FP value just in one register. emit_library_function
1631 doesn't support EXPR_LIST anyway. */
1633 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1634 function_arg (&CUM, MODE, TYPE, NAMED)
1636 /* For an arg passed partly in registers and partly in memory,
1637 this is the number of registers used.
1638 For args passed entirely in registers or entirely in memory, zero. */
1640 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1641 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1643 /* A C expression that indicates when an argument must be passed by
1644 reference. If nonzero for an argument, a copy of that argument is
1645 made in memory and a pointer to the argument is passed instead of
1646 the argument itself. The pointer is passed in whatever way is
1647 appropriate for passing a pointer to that type. */
1649 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1650 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1652 /* If defined, a C expression which determines whether, and in which
1653 direction, to pad out an argument with extra space. The value
1654 should be of type `enum direction': either `upward' to pad above
1655 the argument, `downward' to pad below, or `none' to inhibit
1658 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1660 /* If defined, a C expression that gives the alignment boundary, in bits,
1661 of an argument with the specified mode and type. If it is not defined,
1662 PARM_BOUNDARY is used for all arguments. */
1664 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1665 function_arg_boundary (MODE, TYPE)
1667 /* Perform any needed actions needed for a function that is receiving a
1668 variable number of arguments.
1672 MODE and TYPE are the mode and type of the current parameter.
1674 PRETEND_SIZE is a variable that should be set to the amount of stack
1675 that must be pushed by the prolog to pretend that our caller pushed
1678 Normally, this macro will push all remaining incoming registers on the
1679 stack and set PRETEND_SIZE to the length of the registers pushed. */
1681 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1682 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1684 /* Define the `__builtin_va_list' type for the ABI. */
1685 #define BUILD_VA_LIST_TYPE(VALIST) \
1686 (VALIST) = rs6000_build_va_list ()
1688 /* Implement `va_start' for varargs and stdarg. */
1689 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1690 rs6000_va_start (stdarg, valist, nextarg)
1692 /* Implement `va_arg'. */
1693 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1694 rs6000_va_arg (valist, type)
1696 /* Define this macro to be a nonzero value if the location where a function
1697 argument is passed depends on whether or not it is a named argument. */
1698 #define STRICT_ARGUMENT_NAMING 1
1700 /* Output assembler code to FILE to increment profiler label # LABELNO
1701 for profiling a function entry. */
1703 #define FUNCTION_PROFILER(FILE, LABELNO) \
1704 output_function_profiler ((FILE), (LABELNO));
1706 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1707 the stack pointer does not matter. No definition is equivalent to
1710 On the RS/6000, this is non-zero because we can restore the stack from
1711 its backpointer, which we maintain. */
1712 #define EXIT_IGNORE_STACK 1
1714 /* Define this macro as a C expression that is nonzero for registers
1715 that are used by the epilogue or the return' pattern. The stack
1716 and frame pointer registers are already be assumed to be used as
1719 #define EPILOGUE_USES(REGNO) \
1720 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1721 || (REGNO) == VRSAVE_REGNO \
1722 || (current_function_calls_eh_return \
1724 && (REGNO) == TOC_REGISTER))
1727 /* TRAMPOLINE_TEMPLATE deleted */
1729 /* Length in units of the trampoline for entering a nested function. */
1731 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1733 /* Emit RTL insns to initialize the variable parts of a trampoline.
1734 FNADDR is an RTX for the address of the function's pure code.
1735 CXT is an RTX for the static chain value for the function. */
1737 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1738 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1740 /* Definitions for __builtin_return_address and __builtin_frame_address.
1741 __builtin_return_address (0) should give link register (65), enable
1743 /* This should be uncommented, so that the link register is used, but
1744 currently this would result in unmatched insns and spilling fixed
1745 registers so we'll leave it for another day. When these problems are
1746 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1748 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1750 /* Number of bytes into the frame return addresses can be found. See
1751 rs6000_stack_info in rs6000.c for more information on how the different
1752 abi's store the return address. */
1753 #define RETURN_ADDRESS_OFFSET \
1754 ((DEFAULT_ABI == ABI_AIX \
1755 || DEFAULT_ABI == ABI_DARWIN \
1756 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1757 (DEFAULT_ABI == ABI_V4) ? (TARGET_32BIT ? 4 : 8) : \
1758 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1760 /* The current return address is in link register (65). The return address
1761 of anything farther back is accessed normally at an offset of 8 from the
1763 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1764 (rs6000_return_addr (COUNT, FRAME))
1767 /* Definitions for register eliminations.
1769 We have two registers that can be eliminated on the RS/6000. First, the
1770 frame pointer register can often be eliminated in favor of the stack
1771 pointer register. Secondly, the argument pointer register can always be
1772 eliminated; it is replaced with either the stack or frame pointer.
1774 In addition, we use the elimination mechanism to see if r30 is needed
1775 Initially we assume that it isn't. If it is, we spill it. This is done
1776 by making it an eliminable register. We replace it with itself so that
1777 if it isn't needed, then existing uses won't be modified. */
1779 /* This is an array of structures. Each structure initializes one pair
1780 of eliminable registers. The "from" register number is given first,
1781 followed by "to". Eliminations of the same "from" register are listed
1782 in order of preference. */
1783 #define ELIMINABLE_REGS \
1784 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1785 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1786 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1789 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1790 Frame pointer elimination is automatically handled.
1792 For the RS/6000, if frame pointer elimination is being done, we would like
1793 to convert ap into fp, not sp.
1795 We need r30 if -mminimal-toc was specified, and there are constant pool
1798 #define CAN_ELIMINATE(FROM, TO) \
1799 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1800 ? ! frame_pointer_needed \
1801 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1804 /* Define the offset between two registers, one to be eliminated, and the other
1805 its replacement, at the start of a routine. */
1806 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1808 rs6000_stack_t *info = rs6000_stack_info (); \
1810 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1811 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1812 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1813 (OFFSET) = info->total_size; \
1814 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1815 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1816 else if ((FROM) == 30) \
1822 /* Addressing modes, and classification of registers for them. */
1824 /* #define HAVE_POST_INCREMENT 0 */
1825 /* #define HAVE_POST_DECREMENT 0 */
1827 #define HAVE_PRE_DECREMENT 1
1828 #define HAVE_PRE_INCREMENT 1
1830 /* Macros to check register numbers against specific register classes. */
1832 /* These assume that REGNO is a hard or pseudo reg number.
1833 They give nonzero only if REGNO is a hard reg of the suitable class
1834 or a pseudo reg currently allocated to a suitable hard reg.
1835 Since they use reg_renumber, they are safe only once reg_renumber
1836 has been allocated, which happens in local-alloc.c. */
1838 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1839 ((REGNO) < FIRST_PSEUDO_REGISTER \
1840 ? (REGNO) <= 31 || (REGNO) == 67 \
1841 : (reg_renumber[REGNO] >= 0 \
1842 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1844 #define REGNO_OK_FOR_BASE_P(REGNO) \
1845 ((REGNO) < FIRST_PSEUDO_REGISTER \
1846 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1847 : (reg_renumber[REGNO] > 0 \
1848 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1850 /* Maximum number of registers that can appear in a valid memory address. */
1852 #define MAX_REGS_PER_ADDRESS 2
1854 /* Recognize any constant value that is a valid address. */
1856 #define CONSTANT_ADDRESS_P(X) \
1857 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1858 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1859 || GET_CODE (X) == HIGH)
1861 /* Nonzero if the constant value X is a legitimate general operand.
1862 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1864 On the RS/6000, all integer constants are acceptable, most won't be valid
1865 for particular insns, though. Only easy FP constants are
1868 #define LEGITIMATE_CONSTANT_P(X) \
1869 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1870 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1871 || easy_fp_constant (X, GET_MODE (X)))
1873 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1874 and check its validity for a certain class.
1875 We have two alternate definitions for each of them.
1876 The usual definition accepts all pseudo regs; the other rejects
1877 them unless they have been allocated suitable hard regs.
1878 The symbol REG_OK_STRICT causes the latter definition to be used.
1880 Most source files want to accept pseudo regs in the hope that
1881 they will get allocated to the class that the insn wants them to be in.
1882 Source files for reload pass need to be strict.
1883 After reload, it makes no difference, since pseudo regs have
1884 been eliminated by then. */
1886 #ifdef REG_OK_STRICT
1887 # define REG_OK_STRICT_FLAG 1
1889 # define REG_OK_STRICT_FLAG 0
1892 /* Nonzero if X is a hard reg that can be used as an index
1893 or if it is a pseudo reg in the non-strict case. */
1894 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1896 && (REGNO (X) <= 31 \
1897 || REGNO (X) == ARG_POINTER_REGNUM \
1898 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1899 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1901 /* Nonzero if X is a hard reg that can be used as a base reg
1902 or if it is a pseudo reg in the non-strict case. */
1903 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1904 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1906 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1907 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1909 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1910 that is a valid memory address for an instruction.
1911 The MODE argument is the machine mode for the MEM expression
1912 that wants to use this address.
1914 On the RS/6000, there are four valid address: a SYMBOL_REF that
1915 refers to a constant pool entry of an address (or the sum of it
1916 plus a constant), a short (16-bit signed) constant plus a register,
1917 the sum of two registers, or a register indirect, possibly with an
1918 auto-increment. For DFmode and DImode with an constant plus register,
1919 we must ensure that both words are addressable or PowerPC64 with offset
1922 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1923 32-bit DImode, TImode), indexed addressing cannot be used because
1924 adjacent memory cells are accessed by adding word-sized offsets
1925 during assembly output. */
1927 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1929 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1931 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1933 && GET_CODE (X) == PLUS \
1934 && GET_CODE (XEXP (X, 0)) == REG \
1935 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1936 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1938 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1939 (DEFAULT_ABI == ABI_V4 \
1940 && !flag_pic && !TARGET_TOC \
1941 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1942 && small_data_operand (X, MODE))
1944 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1945 (GET_CODE (X) == CONST_INT \
1946 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1948 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1949 (GET_CODE (X) == PLUS \
1950 && GET_CODE (XEXP (X, 0)) == REG \
1951 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1952 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1953 && (! ALTIVEC_VECTOR_MODE (MODE) || INTVAL (X) == 0) \
1954 && (((MODE) != DFmode && (MODE) != DImode) \
1956 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1957 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1958 && ((MODE) != TImode \
1960 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1961 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1962 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1964 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1965 (GET_CODE (X) == PLUS \
1966 && GET_CODE (XEXP (X, 0)) == REG \
1967 && GET_CODE (XEXP (X, 1)) == REG \
1968 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1969 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
1970 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
1971 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
1973 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
1974 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
1976 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
1978 && ! flag_pic && ! TARGET_TOC \
1979 && (MODE) != DImode \
1980 && (MODE) != TImode \
1981 && ! ALTIVEC_VECTOR_MODE (MODE) \
1982 && (TARGET_HARD_FLOAT || (MODE) != DFmode) \
1983 && GET_CODE (X) == LO_SUM \
1984 && GET_CODE (XEXP (X, 0)) == REG \
1985 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1986 && CONSTANT_P (XEXP (X, 1)))
1988 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1989 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1993 /* Try machine-dependent ways of modifying an illegitimate address
1994 to be legitimate. If we find one, return the new, valid address.
1995 This macro is used in only one place: `memory_address' in explow.c.
1997 OLDX is the address as it was before break_out_memory_refs was called.
1998 In some cases it is useful to look at this to decide what needs to be done.
2000 MODE and WIN are passed so that this macro can use
2001 GO_IF_LEGITIMATE_ADDRESS.
2003 It is always safe for this macro to do nothing. It exists to recognize
2004 opportunities to optimize the output.
2006 On RS/6000, first check for the sum of a register with a constant
2007 integer that is out of range. If so, generate code to add the
2008 constant with the low-order 16 bits masked to the register and force
2009 this result into another register (this can be done with `cau').
2010 Then generate an address of REG+(CONST&0xffff), allowing for the
2011 possibility of bit 16 being a one.
2013 Then check for the sum of a register and something not constant, try to
2014 load the other things into a register and return the sum. */
2016 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2017 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2018 if (result != NULL_RTX) \
2025 /* Try a machine-dependent way of reloading an illegitimate address
2026 operand. If we find one, push the reload and jump to WIN. This
2027 macro is used in only one place: `find_reloads_address' in reload.c.
2029 For RS/6000, we wish to handle large displacements off a base
2030 register by splitting the addend across an addiu/addis and the mem insn.
2031 This cuts number of extra insns needed from 3 to 1. */
2033 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2035 /* We must recognize output that we have already generated ourselves. */ \
2036 if (GET_CODE (X) == PLUS \
2037 && GET_CODE (XEXP (X, 0)) == PLUS \
2038 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
2039 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2040 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2042 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2043 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2047 if (GET_CODE (X) == PLUS \
2048 && GET_CODE (XEXP (X, 0)) == REG \
2049 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
2050 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
2051 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2053 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2054 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
2055 HOST_WIDE_INT high \
2056 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
2058 /* Check for 32-bit overflow. */ \
2059 if (high + low != val) \
2062 /* Reload the high part into a base reg; leave the low part \
2063 in the mem directly. */ \
2065 X = gen_rtx_PLUS (GET_MODE (X), \
2066 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
2070 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2071 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2075 else if (TARGET_TOC \
2076 && CONSTANT_POOL_EXPR_P (X) \
2077 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \
2079 (X) = create_TOC_reference (X); \
2084 /* Go to LABEL if ADDR (a legitimate address expression)
2085 has an effect that depends on the machine mode it is used for.
2087 On the RS/6000 this is true if the address is valid with a zero offset
2088 but not with an offset of four (this means it cannot be used as an
2089 address for DImode or DFmode) or is a pre-increment or decrement. Since
2090 we know it is valid, we just check for an address that is not valid with
2091 an offset of four. */
2093 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2094 { if (GET_CODE (ADDR) == PLUS \
2095 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2096 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2097 (TARGET_32BIT ? 4 : 8))) \
2099 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2101 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2103 if (GET_CODE (ADDR) == LO_SUM) \
2107 /* The register number of the register used to address a table of
2108 static data addresses in memory. In some cases this register is
2109 defined by a processor's "application binary interface" (ABI).
2110 When this macro is defined, RTL is generated for this register
2111 once, as with the stack pointer and frame pointer registers. If
2112 this macro is not defined, it is up to the machine-dependent files
2113 to allocate such a register (if necessary). */
2115 #define PIC_OFFSET_TABLE_REGNUM 30
2117 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2119 /* Define this macro if the register defined by
2120 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2121 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2123 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2125 /* By generating position-independent code, when two different
2126 programs (A and B) share a common library (libC.a), the text of
2127 the library can be shared whether or not the library is linked at
2128 the same address for both programs. In some of these
2129 environments, position-independent code requires not only the use
2130 of different addressing modes, but also special code to enable the
2131 use of these addressing modes.
2133 The `FINALIZE_PIC' macro serves as a hook to emit these special
2134 codes once the function is being compiled into assembly code, but
2135 not before. (It is not done before, because in the case of
2136 compiling an inline function, it would lead to multiple PIC
2137 prologues being included in functions which used inline functions
2138 and were compiled to assembly language.) */
2140 /* #define FINALIZE_PIC */
2142 /* A C expression that is nonzero if X is a legitimate immediate
2143 operand on the target machine when generating position independent
2144 code. You can assume that X satisfies `CONSTANT_P', so you need
2145 not check this. You can also assume FLAG_PIC is true, so you need
2146 not check it either. You need not define this macro if all
2147 constants (including `SYMBOL_REF') can be immediate operands when
2148 generating position independent code. */
2150 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2152 /* In rare cases, correct code generation requires extra machine
2153 dependent processing between the second jump optimization pass and
2154 delayed branch scheduling. On those machines, define this macro
2155 as a C statement to act on the code starting at INSN. */
2157 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2160 /* Define this if some processing needs to be done immediately before
2161 emitting code for an insn. */
2163 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2165 /* Specify the machine mode that this machine uses
2166 for the index in the tablejump instruction. */
2167 #define CASE_VECTOR_MODE SImode
2169 /* Define as C expression which evaluates to nonzero if the tablejump
2170 instruction expects the table to contain offsets from the address of the
2172 Do not define this if the table should contain absolute addresses. */
2173 #define CASE_VECTOR_PC_RELATIVE 1
2175 /* Specify the tree operation to be used to convert reals to integers. */
2176 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2178 /* This is the kind of divide that is easiest to do in the general case. */
2179 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2181 /* Define this as 1 if `char' should by default be signed; else as 0. */
2182 #define DEFAULT_SIGNED_CHAR 0
2184 /* This flag, if defined, says the same insns that convert to a signed fixnum
2185 also convert validly to an unsigned one. */
2187 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2189 /* Max number of bytes we can move from memory to memory
2190 in one reasonably fast instruction. */
2191 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2192 #define MAX_MOVE_MAX 8
2194 /* Nonzero if access to memory by bytes is no faster than for words.
2195 Also non-zero if doing byte operations (specifically shifts) in registers
2197 #define SLOW_BYTE_ACCESS 1
2199 /* Define if operations between registers always perform the operation
2200 on the full register even if a narrower mode is specified. */
2201 #define WORD_REGISTER_OPERATIONS
2203 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2204 will either zero-extend or sign-extend. The value of this macro should
2205 be the code that says which one of the two operations is implicitly
2206 done, NIL if none. */
2207 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2209 /* Define if loading short immediate values into registers sign extends. */
2210 #define SHORT_IMMEDIATES_SIGN_EXTEND
2212 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2213 is done just by pretending it is already truncated. */
2214 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2216 /* Specify the machine mode that pointers have.
2217 After generation of rtl, the compiler makes no further distinction
2218 between pointers and any other objects of this machine mode. */
2219 #define Pmode (TARGET_32BIT ? SImode : DImode)
2221 /* Mode of a function address in a call instruction (for indexing purposes).
2222 Doesn't matter on RS/6000. */
2223 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2225 /* Define this if addresses of constant functions
2226 shouldn't be put through pseudo regs where they can be cse'd.
2227 Desirable on machines where ordinary constants are expensive
2228 but a CALL with constant address is cheap. */
2229 #define NO_FUNCTION_CSE
2231 /* Define this to be nonzero if shift instructions ignore all but the low-order
2234 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2235 have been dropped from the PowerPC architecture. */
2237 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2239 /* Compute the cost of computing a constant rtl expression RTX
2240 whose rtx-code is CODE. The body of this macro is a portion
2241 of a switch statement. If the code is computed here,
2242 return it with a return statement. Otherwise, break from the switch.
2244 On the RS/6000, if it is valid in the insn, it is free. So this
2245 always returns 0. */
2247 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2252 case CONST_DOUBLE: \
2256 /* Provide the costs of a rtl expression. This is in the body of a
2259 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2261 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2262 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2263 + 0x8000) >= 0x10000) \
2264 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2265 ? COSTS_N_INSNS (2) \
2266 : COSTS_N_INSNS (1)); \
2270 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2271 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2272 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2273 ? COSTS_N_INSNS (2) \
2274 : COSTS_N_INSNS (1)); \
2276 switch (rs6000_cpu) \
2278 case PROCESSOR_RIOS1: \
2279 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2280 ? COSTS_N_INSNS (5) \
2281 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2282 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2283 case PROCESSOR_RS64A: \
2284 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2285 ? GET_MODE (XEXP (X, 1)) != DImode \
2286 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2287 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2288 ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
2289 case PROCESSOR_RIOS2: \
2290 case PROCESSOR_MPCCORE: \
2291 case PROCESSOR_PPC604e: \
2292 return COSTS_N_INSNS (2); \
2293 case PROCESSOR_PPC601: \
2294 return COSTS_N_INSNS (5); \
2295 case PROCESSOR_PPC603: \
2296 case PROCESSOR_PPC7400: \
2297 case PROCESSOR_PPC7450: \
2298 case PROCESSOR_PPC750: \
2299 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2300 ? COSTS_N_INSNS (5) \
2301 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2302 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2303 case PROCESSOR_PPC403: \
2304 case PROCESSOR_PPC604: \
2305 return COSTS_N_INSNS (4); \
2306 case PROCESSOR_PPC620: \
2307 case PROCESSOR_PPC630: \
2308 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2309 ? GET_MODE (XEXP (X, 1)) != DImode \
2310 ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
2311 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2312 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2316 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2317 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2318 return COSTS_N_INSNS (2); \
2319 /* otherwise fall through to normal divide. */ \
2322 switch (rs6000_cpu) \
2324 case PROCESSOR_RIOS1: \
2325 return COSTS_N_INSNS (19); \
2326 case PROCESSOR_RIOS2: \
2327 return COSTS_N_INSNS (13); \
2328 case PROCESSOR_RS64A: \
2329 return (GET_MODE (XEXP (X, 1)) != DImode \
2330 ? COSTS_N_INSNS (65) \
2331 : COSTS_N_INSNS (67)); \
2332 case PROCESSOR_MPCCORE: \
2333 return COSTS_N_INSNS (6); \
2334 case PROCESSOR_PPC403: \
2335 return COSTS_N_INSNS (33); \
2336 case PROCESSOR_PPC601: \
2337 return COSTS_N_INSNS (36); \
2338 case PROCESSOR_PPC603: \
2339 return COSTS_N_INSNS (37); \
2340 case PROCESSOR_PPC604: \
2341 case PROCESSOR_PPC604e: \
2342 return COSTS_N_INSNS (20); \
2343 case PROCESSOR_PPC620: \
2344 case PROCESSOR_PPC630: \
2345 return (GET_MODE (XEXP (X, 1)) != DImode \
2346 ? COSTS_N_INSNS (21) \
2347 : COSTS_N_INSNS (37)); \
2348 case PROCESSOR_PPC750: \
2349 case PROCESSOR_PPC7400: \
2350 return COSTS_N_INSNS (19); \
2351 case PROCESSOR_PPC7450: \
2352 return COSTS_N_INSNS (23); \
2355 return COSTS_N_INSNS (4); \
2357 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2360 /* Compute the cost of an address. This is meant to approximate the size
2361 and/or execution delay of an insn using that address. If the cost is
2362 approximated by the RTL complexity, including CONST_COSTS above, as
2363 is usually the case for CISC machines, this macro should not be defined.
2364 For aggressively RISCy machines, only one insn format is allowed, so
2365 this macro should be a constant. The value of this macro only matters
2366 for valid addresses.
2368 For the RS/6000, everything is cost 0. */
2370 #define ADDRESS_COST(RTX) 0
2372 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2373 should be adjusted to reflect any required changes. This macro is used when
2374 there is some systematic length adjustment required that would be difficult
2375 to express in the length attribute. */
2377 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2379 /* Add any extra modes needed to represent the condition code.
2381 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2382 are being done and we need a separate mode for floating-point. We also
2383 use a mode for the case when we are comparing the results of two
2384 comparisons, as then only the EQ bit is valid in the register. */
2386 #define EXTRA_CC_MODES \
2387 CC(CCUNSmode, "CCUNS") \
2388 CC(CCFPmode, "CCFP") \
2389 CC(CCEQmode, "CCEQ")
2391 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2392 COMPARE, return the mode to be used for the comparison. For
2393 floating-point, CCFPmode should be used. CCUNSmode should be used
2394 for unsigned comparisons. CCEQmode should be used when we are
2395 doing an inequality comparison on the result of a
2396 comparison. CCmode should be used in all other cases. */
2398 #define SELECT_CC_MODE(OP,X,Y) \
2399 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2400 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2401 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2402 ? CCEQmode : CCmode))
2404 /* Define the information needed to generate branch and scc insns. This is
2405 stored from the compare operation. Note that we can't use "rtx" here
2406 since it hasn't been defined! */
2408 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2409 extern int rs6000_compare_fp_p;
2411 /* Control the assembler format that we output. */
2413 /* A C string constant describing how to begin a comment in the target
2414 assembler language. The compiler assumes that the comment will end at
2415 the end of the line. */
2416 #define ASM_COMMENT_START " #"
2418 /* Implicit library calls should use memcpy, not bcopy, etc. */
2420 #define TARGET_MEM_FUNCTIONS
2422 /* Flag to say the TOC is initialized */
2423 extern int toc_initialized;
2425 /* Macro to output a special constant pool entry. Go to WIN if we output
2426 it. Otherwise, it is written the usual way.
2428 On the RS/6000, toc entries are handled this way. */
2430 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2431 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2433 output_toc (FILE, X, LABELNO, MODE); \
2438 /* This implementes the `alias' attribute. */
2440 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2442 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2443 char * name = IDENTIFIER_POINTER (target); \
2444 if (TREE_CODE (decl) == FUNCTION_DECL \
2445 && DEFAULT_ABI == ABI_AIX) \
2447 if (TREE_PUBLIC (decl)) \
2449 fputs ("\t.globl .", FILE); \
2450 assemble_name (FILE, alias); \
2451 putc ('\n', FILE); \
2455 fputs ("\t.lglobl .", FILE); \
2456 assemble_name (FILE, alias); \
2457 putc ('\n', FILE); \
2459 fputs ("\t.set .", FILE); \
2460 assemble_name (FILE, alias); \
2461 fputs (",.", FILE); \
2462 assemble_name (FILE, name); \
2463 fputc ('\n', FILE); \
2465 ASM_OUTPUT_DEF (FILE, alias, name); \
2468 /* Output to assembler file text saying following lines
2469 may contain character constants, extra white space, comments, etc. */
2471 #define ASM_APP_ON ""
2473 /* Output to assembler file text saying following lines
2474 no longer contain unusual constructs. */
2476 #define ASM_APP_OFF ""
2478 /* How to refer to registers in assembler output.
2479 This sequence is indexed by compiler's hard-register-number (see above). */
2481 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2483 #define REGISTER_NAMES \
2485 &rs6000_reg_names[ 0][0], /* r0 */ \
2486 &rs6000_reg_names[ 1][0], /* r1 */ \
2487 &rs6000_reg_names[ 2][0], /* r2 */ \
2488 &rs6000_reg_names[ 3][0], /* r3 */ \
2489 &rs6000_reg_names[ 4][0], /* r4 */ \
2490 &rs6000_reg_names[ 5][0], /* r5 */ \
2491 &rs6000_reg_names[ 6][0], /* r6 */ \
2492 &rs6000_reg_names[ 7][0], /* r7 */ \
2493 &rs6000_reg_names[ 8][0], /* r8 */ \
2494 &rs6000_reg_names[ 9][0], /* r9 */ \
2495 &rs6000_reg_names[10][0], /* r10 */ \
2496 &rs6000_reg_names[11][0], /* r11 */ \
2497 &rs6000_reg_names[12][0], /* r12 */ \
2498 &rs6000_reg_names[13][0], /* r13 */ \
2499 &rs6000_reg_names[14][0], /* r14 */ \
2500 &rs6000_reg_names[15][0], /* r15 */ \
2501 &rs6000_reg_names[16][0], /* r16 */ \
2502 &rs6000_reg_names[17][0], /* r17 */ \
2503 &rs6000_reg_names[18][0], /* r18 */ \
2504 &rs6000_reg_names[19][0], /* r19 */ \
2505 &rs6000_reg_names[20][0], /* r20 */ \
2506 &rs6000_reg_names[21][0], /* r21 */ \
2507 &rs6000_reg_names[22][0], /* r22 */ \
2508 &rs6000_reg_names[23][0], /* r23 */ \
2509 &rs6000_reg_names[24][0], /* r24 */ \
2510 &rs6000_reg_names[25][0], /* r25 */ \
2511 &rs6000_reg_names[26][0], /* r26 */ \
2512 &rs6000_reg_names[27][0], /* r27 */ \
2513 &rs6000_reg_names[28][0], /* r28 */ \
2514 &rs6000_reg_names[29][0], /* r29 */ \
2515 &rs6000_reg_names[30][0], /* r30 */ \
2516 &rs6000_reg_names[31][0], /* r31 */ \
2518 &rs6000_reg_names[32][0], /* fr0 */ \
2519 &rs6000_reg_names[33][0], /* fr1 */ \
2520 &rs6000_reg_names[34][0], /* fr2 */ \
2521 &rs6000_reg_names[35][0], /* fr3 */ \
2522 &rs6000_reg_names[36][0], /* fr4 */ \
2523 &rs6000_reg_names[37][0], /* fr5 */ \
2524 &rs6000_reg_names[38][0], /* fr6 */ \
2525 &rs6000_reg_names[39][0], /* fr7 */ \
2526 &rs6000_reg_names[40][0], /* fr8 */ \
2527 &rs6000_reg_names[41][0], /* fr9 */ \
2528 &rs6000_reg_names[42][0], /* fr10 */ \
2529 &rs6000_reg_names[43][0], /* fr11 */ \
2530 &rs6000_reg_names[44][0], /* fr12 */ \
2531 &rs6000_reg_names[45][0], /* fr13 */ \
2532 &rs6000_reg_names[46][0], /* fr14 */ \
2533 &rs6000_reg_names[47][0], /* fr15 */ \
2534 &rs6000_reg_names[48][0], /* fr16 */ \
2535 &rs6000_reg_names[49][0], /* fr17 */ \
2536 &rs6000_reg_names[50][0], /* fr18 */ \
2537 &rs6000_reg_names[51][0], /* fr19 */ \
2538 &rs6000_reg_names[52][0], /* fr20 */ \
2539 &rs6000_reg_names[53][0], /* fr21 */ \
2540 &rs6000_reg_names[54][0], /* fr22 */ \
2541 &rs6000_reg_names[55][0], /* fr23 */ \
2542 &rs6000_reg_names[56][0], /* fr24 */ \
2543 &rs6000_reg_names[57][0], /* fr25 */ \
2544 &rs6000_reg_names[58][0], /* fr26 */ \
2545 &rs6000_reg_names[59][0], /* fr27 */ \
2546 &rs6000_reg_names[60][0], /* fr28 */ \
2547 &rs6000_reg_names[61][0], /* fr29 */ \
2548 &rs6000_reg_names[62][0], /* fr30 */ \
2549 &rs6000_reg_names[63][0], /* fr31 */ \
2551 &rs6000_reg_names[64][0], /* mq */ \
2552 &rs6000_reg_names[65][0], /* lr */ \
2553 &rs6000_reg_names[66][0], /* ctr */ \
2554 &rs6000_reg_names[67][0], /* ap */ \
2556 &rs6000_reg_names[68][0], /* cr0 */ \
2557 &rs6000_reg_names[69][0], /* cr1 */ \
2558 &rs6000_reg_names[70][0], /* cr2 */ \
2559 &rs6000_reg_names[71][0], /* cr3 */ \
2560 &rs6000_reg_names[72][0], /* cr4 */ \
2561 &rs6000_reg_names[73][0], /* cr5 */ \
2562 &rs6000_reg_names[74][0], /* cr6 */ \
2563 &rs6000_reg_names[75][0], /* cr7 */ \
2565 &rs6000_reg_names[76][0], /* xer */ \
2567 &rs6000_reg_names[77][0], /* v0 */ \
2568 &rs6000_reg_names[78][0], /* v1 */ \
2569 &rs6000_reg_names[79][0], /* v2 */ \
2570 &rs6000_reg_names[80][0], /* v3 */ \
2571 &rs6000_reg_names[81][0], /* v4 */ \
2572 &rs6000_reg_names[82][0], /* v5 */ \
2573 &rs6000_reg_names[83][0], /* v6 */ \
2574 &rs6000_reg_names[84][0], /* v7 */ \
2575 &rs6000_reg_names[85][0], /* v8 */ \
2576 &rs6000_reg_names[86][0], /* v9 */ \
2577 &rs6000_reg_names[87][0], /* v10 */ \
2578 &rs6000_reg_names[88][0], /* v11 */ \
2579 &rs6000_reg_names[89][0], /* v12 */ \
2580 &rs6000_reg_names[90][0], /* v13 */ \
2581 &rs6000_reg_names[91][0], /* v14 */ \
2582 &rs6000_reg_names[92][0], /* v15 */ \
2583 &rs6000_reg_names[93][0], /* v16 */ \
2584 &rs6000_reg_names[94][0], /* v17 */ \
2585 &rs6000_reg_names[95][0], /* v18 */ \
2586 &rs6000_reg_names[96][0], /* v19 */ \
2587 &rs6000_reg_names[97][0], /* v20 */ \
2588 &rs6000_reg_names[98][0], /* v21 */ \
2589 &rs6000_reg_names[99][0], /* v22 */ \
2590 &rs6000_reg_names[100][0], /* v23 */ \
2591 &rs6000_reg_names[101][0], /* v24 */ \
2592 &rs6000_reg_names[102][0], /* v25 */ \
2593 &rs6000_reg_names[103][0], /* v26 */ \
2594 &rs6000_reg_names[104][0], /* v27 */ \
2595 &rs6000_reg_names[105][0], /* v28 */ \
2596 &rs6000_reg_names[106][0], /* v29 */ \
2597 &rs6000_reg_names[107][0], /* v30 */ \
2598 &rs6000_reg_names[108][0], /* v31 */ \
2599 &rs6000_reg_names[109][0], /* vrsave */ \
2602 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2603 following for it. Switch to use the alternate names since
2604 they are more mnemonic. */
2606 #define DEBUG_REGISTER_NAMES \
2608 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2609 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2610 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2611 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2612 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2613 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2614 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2615 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2616 "mq", "lr", "ctr", "ap", \
2617 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2619 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2620 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2621 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2622 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2626 /* Table of additional register names to use in user input. */
2628 #define ADDITIONAL_REGISTER_NAMES \
2629 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2630 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2631 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2632 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2633 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2634 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2635 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2636 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2637 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2638 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2639 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2640 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2641 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2642 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2643 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2644 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2645 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2646 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2647 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2648 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2649 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2650 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2651 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2652 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2654 /* no additional names for: mq, lr, ctr, ap */ \
2655 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2656 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2657 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2659 /* Text to write out after a CALL that may be replaced by glue code by
2660 the loader. This depends on the AIX version. */
2661 #define RS6000_CALL_GLUE "cror 31,31,31"
2663 /* This is how to output an assembler line defining a `double' constant. */
2665 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
2668 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2669 fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \
2670 t[0] & 0xffffffff, t[1] & 0xffffffff); \
2673 /* This is how to output an assembler line defining a `float' constant. */
2675 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
2678 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2679 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2682 /* This is how to output an assembler line defining an `int' constant. */
2684 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2688 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
2689 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2690 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
2691 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2695 fprintf (FILE, "%s", DOUBLE_INT_ASM_OP); \
2696 output_addr_const (FILE, (VALUE)); \
2697 putc ('\n', FILE); \
2701 #define ASM_OUTPUT_INT(FILE,VALUE) \
2702 ( fputs ("\t.long ", FILE), \
2703 output_addr_const (FILE, (VALUE)), \
2706 /* Likewise for `char' and `short' constants. */
2708 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2709 ( fputs ("\t.short ", FILE), \
2710 output_addr_const (FILE, (VALUE)), \
2713 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2714 ( fputs ("\t.byte ", FILE), \
2715 output_addr_const (FILE, (VALUE)), \
2718 /* This is how to output an assembler line for a numeric constant byte. */
2720 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2721 fprintf (FILE, "\t.byte 0x%x\n", (int)(VALUE))
2723 /* This is used by the definition of ASM_OUTPUT_ADDR_ELT in defaults.h. */
2724 #define ASM_LONG (TARGET_32BIT ? ".long" : DOUBLE_INT_ASM_OP)
2726 /* This is how to output an element of a case-vector that is relative. */
2728 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2729 do { char buf[100]; \
2730 fputs ("\t.long ", FILE); \
2731 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2732 assemble_name (FILE, buf); \
2734 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2735 assemble_name (FILE, buf); \
2736 putc ('\n', FILE); \
2739 /* This is how to output an assembler line
2740 that says to advance the location counter
2741 to a multiple of 2**LOG bytes. */
2743 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2745 fprintf (FILE, "\t.align %d\n", (LOG))
2747 /* Store in OUTPUT a string (made with alloca) containing
2748 an assembler-name for a local static variable named NAME.
2749 LABELNO is an integer which is different for each call. */
2751 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2752 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2753 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2755 /* Pick up the return address upon entry to a procedure. Used for
2756 dwarf2 unwind information. This also enables the table driven
2759 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2760 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2762 /* Describe how we implement __builtin_eh_return. */
2763 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2764 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2766 /* Print operand X (an rtx) in assembler syntax to file FILE.
2767 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2768 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2770 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2772 /* Define which CODE values are valid. */
2774 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2775 ((CODE) == '.' || (CODE) == '*' || (CODE) == '$')
2777 /* Print a memory address as an operand to reference that memory location. */
2779 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2781 /* Define the codes that are matched by predicates in rs6000.c. */
2783 #define PREDICATE_CODES \
2784 {"short_cint_operand", {CONST_INT}}, \
2785 {"u_short_cint_operand", {CONST_INT}}, \
2786 {"non_short_cint_operand", {CONST_INT}}, \
2787 {"exact_log2_cint_operand", {CONST_INT}}, \
2788 {"gpc_reg_operand", {SUBREG, REG}}, \
2789 {"cc_reg_operand", {SUBREG, REG}}, \
2790 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2791 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2792 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2793 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2794 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2795 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2796 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2797 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2798 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2799 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2800 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2801 {"easy_fp_constant", {CONST_DOUBLE}}, \
2802 {"zero_fp_constant", {CONST_DOUBLE}}, \
2803 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2804 {"lwa_operand", {SUBREG, MEM, REG}}, \
2805 {"volatile_mem_operand", {MEM}}, \
2806 {"offsettable_mem_operand", {MEM}}, \
2807 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2808 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2809 {"non_add_cint_operand", {CONST_INT}}, \
2810 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2811 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2812 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2813 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2814 {"mask_operand", {CONST_INT}}, \
2815 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2816 {"count_register_operand", {REG}}, \
2817 {"xer_operand", {REG}}, \
2818 {"call_operand", {SYMBOL_REF, REG}}, \
2819 {"current_file_function_operand", {SYMBOL_REF}}, \
2820 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2821 CONST_DOUBLE, SYMBOL_REF}}, \
2822 {"load_multiple_operation", {PARALLEL}}, \
2823 {"store_multiple_operation", {PARALLEL}}, \
2824 {"vrsave_operation", {PARALLEL}}, \
2825 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2826 GT, LEU, LTU, GEU, GTU, \
2827 UNORDERED, ORDERED, \
2829 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2831 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2832 GT, LEU, LTU, GEU, GTU, \
2833 UNORDERED, ORDERED, \
2835 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2836 GT, LEU, LTU, GEU, GTU}}, \
2837 {"boolean_operator", {AND, IOR, XOR}}, \
2838 {"boolean_or_operator", {IOR, XOR}}, \
2839 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2841 /* uncomment for disabling the corresponding default options */
2842 /* #define MACHINE_no_sched_interblock */
2843 /* #define MACHINE_no_sched_speculative */
2844 /* #define MACHINE_no_sched_speculative_load */
2846 /* General flags. */
2847 extern int flag_pic;
2848 extern int optimize;
2849 extern int flag_expensive_optimizations;
2850 extern int frame_pointer_needed;
2852 enum rs6000_builtins
2854 /* AltiVec builtins. */
2855 ALTIVEC_BUILTIN_ST_INTERNAL,
2856 ALTIVEC_BUILTIN_LD_INTERNAL,
2857 ALTIVEC_BUILTIN_VADDUBM,
2858 ALTIVEC_BUILTIN_VADDUHM,
2859 ALTIVEC_BUILTIN_VADDUWM,
2860 ALTIVEC_BUILTIN_VADDFP,
2861 ALTIVEC_BUILTIN_VADDCUW,
2862 ALTIVEC_BUILTIN_VADDUBS,
2863 ALTIVEC_BUILTIN_VADDSBS,
2864 ALTIVEC_BUILTIN_VADDUHS,
2865 ALTIVEC_BUILTIN_VADDSHS,
2866 ALTIVEC_BUILTIN_VADDUWS,
2867 ALTIVEC_BUILTIN_VADDSWS,
2868 ALTIVEC_BUILTIN_VAND,
2869 ALTIVEC_BUILTIN_VANDC,
2870 ALTIVEC_BUILTIN_VAVGUB,
2871 ALTIVEC_BUILTIN_VAVGSB,
2872 ALTIVEC_BUILTIN_VAVGUH,
2873 ALTIVEC_BUILTIN_VAVGSH,
2874 ALTIVEC_BUILTIN_VAVGUW,
2875 ALTIVEC_BUILTIN_VAVGSW,
2876 ALTIVEC_BUILTIN_VCMPBFP,
2877 ALTIVEC_BUILTIN_VCMPEQUB,
2878 ALTIVEC_BUILTIN_VCMPEQUH,
2879 ALTIVEC_BUILTIN_VCMPEQUW,
2880 ALTIVEC_BUILTIN_VCMPEQFP,
2881 ALTIVEC_BUILTIN_VCMPGEFP,
2882 ALTIVEC_BUILTIN_VCMPGTUB,
2883 ALTIVEC_BUILTIN_VCMPGTSB,
2884 ALTIVEC_BUILTIN_VCMPGTUH,
2885 ALTIVEC_BUILTIN_VCMPGTSH,
2886 ALTIVEC_BUILTIN_VCMPGTUW,
2887 ALTIVEC_BUILTIN_VCMPGTSW,
2888 ALTIVEC_BUILTIN_VCMPGTFP,
2889 ALTIVEC_BUILTIN_VMAXUB,
2890 ALTIVEC_BUILTIN_VMAXSB,
2891 ALTIVEC_BUILTIN_VMAXUH,
2892 ALTIVEC_BUILTIN_VMAXSH,
2893 ALTIVEC_BUILTIN_VMAXUW,
2894 ALTIVEC_BUILTIN_VMAXSW,
2895 ALTIVEC_BUILTIN_VMAXFP,
2896 ALTIVEC_BUILTIN_VMRGHB,
2897 ALTIVEC_BUILTIN_VMRGHH,
2898 ALTIVEC_BUILTIN_VMRGHW,
2899 ALTIVEC_BUILTIN_VMRGLB,
2900 ALTIVEC_BUILTIN_VMRGLH,
2901 ALTIVEC_BUILTIN_VMRGLW,
2902 ALTIVEC_BUILTIN_VMINUB,
2903 ALTIVEC_BUILTIN_VMINSB,
2904 ALTIVEC_BUILTIN_VMINUH,
2905 ALTIVEC_BUILTIN_VMINSH,
2906 ALTIVEC_BUILTIN_VMINUW,
2907 ALTIVEC_BUILTIN_VMINSW,
2908 ALTIVEC_BUILTIN_VMINFP,
2909 ALTIVEC_BUILTIN_VMULEUB,
2910 ALTIVEC_BUILTIN_VMULESB,
2911 ALTIVEC_BUILTIN_VMULEUH,
2912 ALTIVEC_BUILTIN_VMULESH,
2913 ALTIVEC_BUILTIN_VMULOUB,
2914 ALTIVEC_BUILTIN_VMULOSB,
2915 ALTIVEC_BUILTIN_VMULOUH,
2916 ALTIVEC_BUILTIN_VMULOSH,
2917 ALTIVEC_BUILTIN_VNOR,
2918 ALTIVEC_BUILTIN_VOR,
2919 ALTIVEC_BUILTIN_VPKUHUM,
2920 ALTIVEC_BUILTIN_VPKUWUM,
2921 ALTIVEC_BUILTIN_VPKPX,
2922 ALTIVEC_BUILTIN_VPKUHSS,
2923 ALTIVEC_BUILTIN_VPKSHSS,
2924 ALTIVEC_BUILTIN_VPKUWSS,
2925 ALTIVEC_BUILTIN_VPKSWSS,
2926 ALTIVEC_BUILTIN_VPKUHUS,
2927 ALTIVEC_BUILTIN_VPKSHUS,
2928 ALTIVEC_BUILTIN_VPKUWUS,
2929 ALTIVEC_BUILTIN_VPKSWUS,
2930 ALTIVEC_BUILTIN_VRLB,
2931 ALTIVEC_BUILTIN_VRLH,
2932 ALTIVEC_BUILTIN_VRLW,
2933 ALTIVEC_BUILTIN_VSLB,
2934 ALTIVEC_BUILTIN_VSLH,
2935 ALTIVEC_BUILTIN_VSLW,
2936 ALTIVEC_BUILTIN_VSL,
2937 ALTIVEC_BUILTIN_VSLO,
2938 ALTIVEC_BUILTIN_VSRB,
2939 ALTIVEC_BUILTIN_VRSH,
2940 ALTIVEC_BUILTIN_VRSW,
2941 ALTIVEC_BUILTIN_VSRAB,
2942 ALTIVEC_BUILTIN_VSRAH,
2943 ALTIVEC_BUILTIN_VSRAW,
2944 ALTIVEC_BUILTIN_VSR,
2945 ALTIVEC_BUILTIN_VSRO,
2946 ALTIVEC_BUILTIN_VSUBUBM,
2947 ALTIVEC_BUILTIN_VSUBUHM,
2948 ALTIVEC_BUILTIN_VSUBUWM,
2949 ALTIVEC_BUILTIN_VSUBFP,
2950 ALTIVEC_BUILTIN_VSUBCUW,
2951 ALTIVEC_BUILTIN_VSUBUBS,
2952 ALTIVEC_BUILTIN_VSUBSBS,
2953 ALTIVEC_BUILTIN_VSUBUHS,
2954 ALTIVEC_BUILTIN_VSUBSHS,
2955 ALTIVEC_BUILTIN_VSUBUWS,
2956 ALTIVEC_BUILTIN_VSUBSWS,
2957 ALTIVEC_BUILTIN_VSUM4UBS,
2958 ALTIVEC_BUILTIN_VSUM4SBS,
2959 ALTIVEC_BUILTIN_VSUM4SHS,
2960 ALTIVEC_BUILTIN_VSUM2SWS,
2961 ALTIVEC_BUILTIN_VSUMSWS,
2962 ALTIVEC_BUILTIN_VXOR
OSDN Git Service
