1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common CPP definitions used by CPP_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define CPP_CPU_SPEC \
53 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
54 %{mpower2: -D_ARCH_PWR2} \
55 %{mpowerpc*: -D_ARCH_PPC} \
56 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
57 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
58 %{mcpu=common: -D_ARCH_COM} \
59 %{mcpu=power: -D_ARCH_PWR} \
60 %{mcpu=power2: -D_ARCH_PWR2} \
61 %{mcpu=powerpc: -D_ARCH_PPC} \
62 %{mcpu=rios: -D_ARCH_PWR} \
63 %{mcpu=rios1: -D_ARCH_PWR} \
64 %{mcpu=rios2: -D_ARCH_PWR2} \
65 %{mcpu=rsc: -D_ARCH_PWR} \
66 %{mcpu=rsc1: -D_ARCH_PWR} \
67 %{mcpu=401: -D_ARCH_PPC} \
68 %{mcpu=403: -D_ARCH_PPC} \
69 %{mcpu=405: -D_ARCH_PPC} \
70 %{mcpu=505: -D_ARCH_PPC} \
71 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
72 %{mcpu=602: -D_ARCH_PPC} \
73 %{mcpu=603: -D_ARCH_PPC} \
74 %{mcpu=603e: -D_ARCH_PPC} \
75 %{mcpu=ec603e: -D_ARCH_PPC} \
76 %{mcpu=604: -D_ARCH_PPC} \
77 %{mcpu=604e: -D_ARCH_PPC} \
78 %{mcpu=620: -D_ARCH_PPC} \
79 %{mcpu=740: -D_ARCH_PPC} \
80 %{mcpu=7400: -D_ARCH_PPC} \
81 %{mcpu=7450: -D_ARCH_PPC} \
82 %{mcpu=750: -D_ARCH_PPC} \
83 %{mcpu=801: -D_ARCH_PPC} \
84 %{mcpu=821: -D_ARCH_PPC} \
85 %{mcpu=823: -D_ARCH_PPC} \
86 %{mcpu=860: -D_ARCH_PPC} \
87 %{maltivec: -D__ALTIVEC__}"
89 /* Common ASM definitions used by ASM_SPEC among the various targets
90 for handling -mcpu=xxx switches. */
91 #define ASM_CPU_SPEC \
93 %{mpower: %{!mpower2: -mpwr}} \
96 %{mno-power: %{!mpowerpc*: -mcom}} \
97 %{!mno-power: %{!mpower2: %(asm_default)}}} \
98 %{mcpu=common: -mcom} \
99 %{mcpu=power: -mpwr} \
100 %{mcpu=power2: -mpwrx} \
101 %{mcpu=powerpc: -mppc} \
102 %{mcpu=rios: -mpwr} \
103 %{mcpu=rios1: -mpwr} \
104 %{mcpu=rios2: -mpwrx} \
106 %{mcpu=rsc1: -mpwr} \
114 %{mcpu=603e: -mppc} \
115 %{mcpu=ec603e: -mppc} \
117 %{mcpu=604e: -mppc} \
120 %{mcpu=7400: -mppc} \
121 %{mcpu=7450: -mppc} \
127 %{maltivec: -maltivec}"
129 #define CPP_DEFAULT_SPEC ""
131 #define ASM_DEFAULT_SPEC ""
133 /* This macro defines names of additional specifications to put in the specs
134 that can be used in various specifications like CC1_SPEC. Its definition
135 is an initializer with a subgrouping for each command option.
137 Each subgrouping contains a string constant, that defines the
138 specification name, and a string constant that used by the GNU CC driver
141 Do not define this macro if it does not need to do anything. */
143 #define SUBTARGET_EXTRA_SPECS
145 #define EXTRA_SPECS \
146 { "cpp_cpu", CPP_CPU_SPEC }, \
147 { "cpp_default", CPP_DEFAULT_SPEC }, \
148 { "asm_cpu", ASM_CPU_SPEC }, \
149 { "asm_default", ASM_DEFAULT_SPEC }, \
150 SUBTARGET_EXTRA_SPECS
152 /* Architecture type. */
154 extern int target_flags;
156 /* Use POWER architecture instructions and MQ register. */
157 #define MASK_POWER 0x00000001
159 /* Use POWER2 extensions to POWER architecture. */
160 #define MASK_POWER2 0x00000002
162 /* Use PowerPC architecture instructions. */
163 #define MASK_POWERPC 0x00000004
165 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
166 #define MASK_PPC_GPOPT 0x00000008
168 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
169 #define MASK_PPC_GFXOPT 0x00000010
171 /* Use PowerPC-64 architecture instructions. */
172 #define MASK_POWERPC64 0x00000020
174 /* Use revised mnemonic names defined for PowerPC architecture. */
175 #define MASK_NEW_MNEMONICS 0x00000040
177 /* Disable placing fp constants in the TOC; can be turned on when the
179 #define MASK_NO_FP_IN_TOC 0x00000080
181 /* Disable placing symbol+offset constants in the TOC; can be turned on when
182 the TOC overflows. */
183 #define MASK_NO_SUM_IN_TOC 0x00000100
185 /* Output only one TOC entry per module. Normally linking fails if
186 there are more than 16K unique variables/constants in an executable. With
187 this option, linking fails only if there are more than 16K modules, or
188 if there are more than 16K unique variables/constant in a single module.
190 This is at the cost of having 2 extra loads and one extra store per
191 function, and one less allocable register. */
192 #define MASK_MINIMAL_TOC 0x00000200
194 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
195 #define MASK_64BIT 0x00000400
197 /* Disable use of FPRs. */
198 #define MASK_SOFT_FLOAT 0x00000800
200 /* Enable load/store multiple, even on powerpc */
201 #define MASK_MULTIPLE 0x00001000
202 #define MASK_MULTIPLE_SET 0x00002000
204 /* Use string instructions for block moves */
205 #define MASK_STRING 0x00004000
206 #define MASK_STRING_SET 0x00008000
208 /* Disable update form of load/store */
209 #define MASK_NO_UPDATE 0x00010000
211 /* Disable fused multiply/add operations */
212 #define MASK_NO_FUSED_MADD 0x00020000
214 /* Nonzero if we need to schedule the prolog and epilog. */
215 #define MASK_SCHED_PROLOG 0x00040000
217 /* Use AltiVec instructions. */
218 #define MASK_ALTIVEC 0x00080000
220 /* Return small structures in memory (as the AIX ABI requires). */
221 #define MASK_AIX_STRUCT_RET 0x00100000
222 #define MASK_AIX_STRUCT_RET_SET 0x00200000
224 /* The only remaining free bit is 0x00400000. sysv4.h uses
225 0x00800000 -> 0x40000000, and 0x80000000 is not available
226 because target_flags is signed. */
228 #define TARGET_POWER (target_flags & MASK_POWER)
229 #define TARGET_POWER2 (target_flags & MASK_POWER2)
230 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
231 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
232 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
233 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
234 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
235 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
236 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
237 #define TARGET_64BIT (target_flags & MASK_64BIT)
238 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
239 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
240 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
241 #define TARGET_STRING (target_flags & MASK_STRING)
242 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
243 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
244 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
245 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
246 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
247 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
249 #define TARGET_32BIT (! TARGET_64BIT)
250 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
251 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
252 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
255 /* For libgcc2 we make sure this is a compile time constant */
256 #if defined (__64BIT__) || defined (__powerpc64__)
257 #define TARGET_POWERPC64 1
259 #define TARGET_POWERPC64 0
262 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
265 #define TARGET_XL_CALL 0
267 /* Run-time compilation parameters selecting different hardware subsets.
269 Macro to define tables used to set the flags.
270 This is a list in braces of pairs in braces,
271 each pair being { "NAME", VALUE }
272 where VALUE is the bits to set or minus the bits to clear.
273 An empty string NAME is used to identify the default VALUE. */
275 #define TARGET_SWITCHES \
276 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
277 N_("Use POWER instruction set")}, \
278 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
280 N_("Use POWER2 instruction set")}, \
281 {"no-power2", - MASK_POWER2, \
282 N_("Do not use POWER2 instruction set")}, \
283 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
285 N_("Do not use POWER instruction set")}, \
286 {"powerpc", MASK_POWERPC, \
287 N_("Use PowerPC instruction set")}, \
288 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
289 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
290 N_("Do not use PowerPC instruction set")}, \
291 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
292 N_("Use PowerPC General Purpose group optional instructions")},\
293 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
294 N_("Don't use PowerPC General Purpose group optional instructions")},\
295 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
296 N_("Use PowerPC Graphics group optional instructions")},\
297 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
298 N_("Don't use PowerPC Graphics group optional instructions")},\
299 {"powerpc64", MASK_POWERPC64, \
300 N_("Use PowerPC-64 instruction set")}, \
301 {"no-powerpc64", - MASK_POWERPC64, \
302 N_("Don't use PowerPC-64 instruction set")}, \
303 {"altivec", MASK_ALTIVEC , \
304 N_("Use AltiVec instructions")}, \
305 {"no-altivec", - MASK_ALTIVEC , \
306 N_("Don't use AltiVec instructions")}, \
307 {"new-mnemonics", MASK_NEW_MNEMONICS, \
308 N_("Use new mnemonics for PowerPC architecture")},\
309 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
310 N_("Use old mnemonics for PowerPC architecture")},\
311 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
312 | MASK_MINIMAL_TOC), \
313 N_("Put everything in the regular TOC")}, \
314 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
315 N_("Place floating point constants in TOC")}, \
316 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
317 N_("Don't place floating point constants in TOC")},\
318 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
319 N_("Place symbol+offset constants in TOC")}, \
320 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
321 N_("Don't place symbol+offset constants in TOC")},\
322 {"minimal-toc", MASK_MINIMAL_TOC, \
323 "Use only one TOC entry per procedure"}, \
324 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
326 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
327 N_("Place variable addresses in the regular TOC")},\
328 {"hard-float", - MASK_SOFT_FLOAT, \
329 N_("Use hardware fp")}, \
330 {"soft-float", MASK_SOFT_FLOAT, \
331 N_("Do not use hardware fp")}, \
332 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
333 N_("Generate load/store multiple instructions")}, \
334 {"no-multiple", - MASK_MULTIPLE, \
335 N_("Do not generate load/store multiple instructions")},\
336 {"no-multiple", MASK_MULTIPLE_SET, \
338 {"string", MASK_STRING | MASK_STRING_SET, \
339 N_("Generate string instructions for block moves")},\
340 {"no-string", - MASK_STRING, \
341 N_("Do not generate string instructions for block moves")},\
342 {"no-string", MASK_STRING_SET, \
344 {"update", - MASK_NO_UPDATE, \
345 N_("Generate load/store with update instructions")},\
346 {"no-update", MASK_NO_UPDATE, \
347 N_("Do not generate load/store with update instructions")},\
348 {"fused-madd", - MASK_NO_FUSED_MADD, \
349 N_("Generate fused multiply/add instructions")},\
350 {"no-fused-madd", MASK_NO_FUSED_MADD, \
351 N_("Don't generate fused multiply/add instructions")},\
352 {"sched-prolog", MASK_SCHED_PROLOG, \
354 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
355 N_("Don't schedule the start and end of the procedure")},\
356 {"sched-epilog", MASK_SCHED_PROLOG, \
358 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
360 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \
361 N_("Return all structures in memory (AIX default)")},\
362 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\
363 N_("Return small structures in registers (SVR4 default)")},\
364 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\
366 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\
368 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\
370 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\
373 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
376 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
378 /* This is meant to be redefined in the host dependent files */
379 #define SUBTARGET_SWITCHES
381 /* Processor type. Order must match cpu attribute in MD file. */
401 extern enum processor_type rs6000_cpu;
403 /* Recast the processor type to the cpu attribute. */
404 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
406 /* Define generic processor types based upon current deployment. */
407 #define PROCESSOR_COMMON PROCESSOR_PPC601
408 #define PROCESSOR_POWER PROCESSOR_RIOS1
409 #define PROCESSOR_POWERPC PROCESSOR_PPC604
410 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
412 /* Define the default processor. This is overridden by other tm.h files. */
413 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
414 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
416 /* Specify the dialect of assembler to use. New mnemonics is dialect one
417 and the old mnemonics are dialect zero. */
418 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
420 /* This is meant to be overridden in target specific files. */
421 #define SUBTARGET_OPTIONS
423 #define TARGET_OPTIONS \
425 {"cpu=", &rs6000_select[1].string, \
426 N_("Use features of and schedule code for given CPU") }, \
427 {"tune=", &rs6000_select[2].string, \
428 N_("Schedule code for given CPU") }, \
429 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
430 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
431 {"long-double-", &rs6000_long_double_size_string, \
432 N_("Specify size of long double (64 or 128 bits)") }, \
436 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
437 struct rs6000_cpu_select
445 extern struct rs6000_cpu_select rs6000_select[];
448 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
449 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
450 extern int rs6000_debug_stack; /* debug stack applications */
451 extern int rs6000_debug_arg; /* debug argument handling */
453 #define TARGET_DEBUG_STACK rs6000_debug_stack
454 #define TARGET_DEBUG_ARG rs6000_debug_arg
456 /* These are separate from target_flags because we've run out of bits
458 extern const char *rs6000_long_double_size_string;
459 extern int rs6000_long_double_type_size;
460 extern int rs6000_altivec_abi;
462 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
463 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
465 /* Sometimes certain combinations of command options do not make sense
466 on a particular target machine. You can define a macro
467 `OVERRIDE_OPTIONS' to take account of this. This macro, if
468 defined, is executed once just after all the command options have
471 Don't use this macro to turn on various extra optimizations for
472 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
474 On the RS/6000 this is used to define the target cpu type. */
476 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
478 /* Define this to change the optimizations performed by default. */
479 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
481 /* Show we can debug even without a frame pointer. */
482 #define CAN_DEBUG_WITHOUT_FP
484 /* target machine storage layout */
486 /* Define to support cross compilation to an RS6000 target. */
487 #define REAL_ARITHMETIC
489 /* Define this macro if it is advisable to hold scalars in registers
490 in a wider mode than that declared by the program. In such cases,
491 the value is constrained to be within the bounds of the declared
492 type, but kept valid in the wider mode. The signedness of the
493 extension may differ from that of the type. */
495 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
496 if (GET_MODE_CLASS (MODE) == MODE_INT \
497 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
500 /* Define this if function arguments should also be promoted using the above
503 #define PROMOTE_FUNCTION_ARGS
505 /* Likewise, if the function return value is promoted. */
507 #define PROMOTE_FUNCTION_RETURN
509 /* Define this if most significant bit is lowest numbered
510 in instructions that operate on numbered bit-fields. */
511 /* That is true on RS/6000. */
512 #define BITS_BIG_ENDIAN 1
514 /* Define this if most significant byte of a word is the lowest numbered. */
515 /* That is true on RS/6000. */
516 #define BYTES_BIG_ENDIAN 1
518 /* Define this if most significant word of a multiword number is lowest
521 For RS/6000 we can decide arbitrarily since there are no machine
522 instructions for them. Might as well be consistent with bits and bytes. */
523 #define WORDS_BIG_ENDIAN 1
525 /* number of bits in an addressable storage unit */
526 #define BITS_PER_UNIT 8
528 /* Width in bits of a "word", which is the contents of a machine register.
529 Note that this is not necessarily the width of data type `int';
530 if using 16-bit ints on a 68000, this would still be 32.
531 But on a machine with 16-bit registers, this would be 16. */
532 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
533 #define MAX_BITS_PER_WORD 64
535 /* Width of a word, in units (bytes). */
536 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
537 #define MIN_UNITS_PER_WORD 4
538 #define UNITS_PER_FP_WORD 8
539 #define UNITS_PER_ALTIVEC_WORD 16
541 /* Type used for ptrdiff_t, as a string used in a declaration. */
542 #define PTRDIFF_TYPE "int"
544 /* Type used for size_t, as a string used in a declaration. */
545 #define SIZE_TYPE "long unsigned int"
547 /* Type used for wchar_t, as a string used in a declaration. */
548 #define WCHAR_TYPE "short unsigned int"
550 /* Width of wchar_t in bits. */
551 #define WCHAR_TYPE_SIZE 16
553 /* A C expression for the size in bits of the type `short' on the
554 target machine. If you don't define this, the default is half a
555 word. (If this would be less than one storage unit, it is
556 rounded up to one unit.) */
557 #define SHORT_TYPE_SIZE 16
559 /* A C expression for the size in bits of the type `int' on the
560 target machine. If you don't define this, the default is one
562 #define INT_TYPE_SIZE 32
564 /* A C expression for the size in bits of the type `long' on the
565 target machine. If you don't define this, the default is one
567 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
568 #define MAX_LONG_TYPE_SIZE 64
570 /* A C expression for the size in bits of the type `long long' on the
571 target machine. If you don't define this, the default is two
573 #define LONG_LONG_TYPE_SIZE 64
575 /* A C expression for the size in bits of the type `char' on the
576 target machine. If you don't define this, the default is one
577 quarter of a word. (If this would be less than one storage unit,
578 it is rounded up to one unit.) */
579 #define CHAR_TYPE_SIZE BITS_PER_UNIT
581 /* A C expression for the size in bits of the type `float' on the
582 target machine. If you don't define this, the default is one
584 #define FLOAT_TYPE_SIZE 32
586 /* A C expression for the size in bits of the type `double' on the
587 target machine. If you don't define this, the default is two
589 #define DOUBLE_TYPE_SIZE 64
591 /* A C expression for the size in bits of the type `long double' on
592 the target machine. If you don't define this, the default is two
594 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
596 /* Constant which presents upper bound of the above value. */
597 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
599 /* Define this to set long double type size to use in libgcc2.c, which can
600 not depend on target_flags. */
601 #ifdef __LONG_DOUBLE_128__
602 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
604 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
607 /* Width in bits of a pointer.
608 See also the macro `Pmode' defined below. */
609 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
611 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
612 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
614 /* Boundary (in *bits*) on which stack pointer should be aligned. */
615 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
617 /* Allocation boundary (in *bits*) for the code of a function. */
618 #define FUNCTION_BOUNDARY 32
620 /* No data type wants to be aligned rounder than this. */
621 #define BIGGEST_ALIGNMENT 128
623 /* A C expression to compute the alignment for a variables in the
624 local store. TYPE is the data type, and ALIGN is the alignment
625 that the object would ordinarily have. */
626 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
627 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN)
629 /* Handle #pragma pack. */
630 #define HANDLE_PRAGMA_PACK 1
632 /* Alignment of field after `int : 0' in a structure. */
633 #define EMPTY_FIELD_BOUNDARY 32
635 /* Every structure's size must be a multiple of this. */
636 #define STRUCTURE_SIZE_BOUNDARY 8
638 /* A bitfield declared as `int' forces `int' alignment for the struct. */
639 #define PCC_BITFIELD_TYPE_MATTERS 1
641 /* Make strings word-aligned so strcpy from constants will be faster. */
642 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
643 (TREE_CODE (EXP) == STRING_CST \
644 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
646 /* Make arrays of chars word-aligned for the same reasons.
647 Align vectors to 128 bits. */
648 #define DATA_ALIGNMENT(TYPE, ALIGN) \
649 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
650 : TREE_CODE (TYPE) == ARRAY_TYPE \
651 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
652 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
654 /* Non-zero if move instructions will actually fail to work
655 when given unaligned data. */
656 #define STRICT_ALIGNMENT 0
658 /* Define this macro to be the value 1 if unaligned accesses have a cost
659 many times greater than aligned accesses, for example if they are
660 emulated in a trap handler. */
661 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
663 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
666 /* Standard register usage. */
668 /* Number of actual hardware registers.
669 The hardware registers are assigned numbers for the compiler
670 from 0 to just below FIRST_PSEUDO_REGISTER.
671 All registers that the compiler knows about must be given numbers,
672 even those that are not normally considered general registers.
674 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
675 an MQ register, a count register, a link register, and 8 condition
676 register fields, which we view here as separate registers.
678 In addition, the difference between the frame and argument pointers is
679 a function of the number of registers saved, so we need to have a
680 register for AP that will later be eliminated in favor of SP or FP.
681 This is a normal register, but it is fixed.
683 We also create a pseudo register for float/int conversions, that will
684 really represent the memory location used. It is represented here as
685 a register, in order to work around problems in allocating stack storage
686 in inline functions. */
688 #define FIRST_PSEUDO_REGISTER 110
690 /* This must be included for pre gcc 3.0 glibc compatibility. */
691 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
693 /* 1 for registers that have pervasive standard uses
694 and are not available for the register allocator.
696 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
697 as a local register; for all other OS's r2 is the TOC pointer.
699 cr5 is not supposed to be used.
701 On System V implementations, r13 is fixed and not available for use. */
703 #define FIXED_REGISTERS \
704 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
708 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
709 /* AltiVec registers. */ \
710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
715 /* 1 for registers not available across function calls.
716 These must include the FIXED_REGISTERS and also any
717 registers that can be used without being saved.
718 The latter must include the registers where values are returned
719 and the register where structure-value addresses are passed.
720 Aside from that, you can include as many other registers as you like. */
722 #define CALL_USED_REGISTERS \
723 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
725 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
726 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
727 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
728 /* AltiVec registers. */ \
729 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
730 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
734 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
735 the entire set of `FIXED_REGISTERS' be included.
736 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
737 This macro is optional. If not specified, it defaults to the value
738 of `CALL_USED_REGISTERS'. */
740 #define CALL_REALLY_USED_REGISTERS \
741 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
743 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
745 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
746 /* AltiVec registers. */ \
747 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
748 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
758 #define MAX_CR_REGNO 75
760 #define FIRST_ALTIVEC_REGNO 77
761 #define LAST_ALTIVEC_REGNO 108
762 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO)
763 #define VRSAVE_REGNO 109
765 /* List the order in which to allocate registers. Each register must be
766 listed once, even those in FIXED_REGISTERS.
768 We allocate in the following order:
769 fp0 (not saved or used for anything)
770 fp13 - fp2 (not saved; incoming fp arg registers)
771 fp1 (not saved; return value)
772 fp31 - fp14 (saved; order given to save least number)
773 cr7, cr6 (not saved or special)
774 cr1 (not saved, but used for FP operations)
775 cr0 (not saved, but used for arithmetic operations)
776 cr4, cr3, cr2 (saved)
777 r0 (not saved; cannot be base reg)
778 r9 (not saved; best for TImode)
779 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
780 r3 (not saved; return value register)
781 r31 - r13 (saved; order given to save least number)
782 r12 (not saved; if used for DImode or DFmode would use r13)
783 mq (not saved; best to use it if we can)
784 ctr (not saved; when we have the choice ctr is better)
786 cr5, r1, r2, ap, xer, vrsave (fixed)
789 v0 - v1 (not saved or used for anything)
790 v13 - v3 (not saved; incoming vector arg registers)
791 v2 (not saved; incoming vector arg reg; return value)
792 v19 - v14 (not saved or used for anything)
793 v31 - v20 (saved; order given to save least number)
797 #define REG_ALLOC_ORDER \
799 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
801 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
802 50, 49, 48, 47, 46, \
803 75, 74, 69, 68, 72, 71, 70, \
805 9, 11, 10, 8, 7, 6, 5, 4, \
807 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
808 18, 17, 16, 15, 14, 13, 12, \
811 /* AltiVec registers. */ \
813 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
815 96, 95, 94, 93, 92, 91, \
816 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
820 /* True if register is floating-point. */
821 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
823 /* True if register is a condition register. */
824 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
826 /* True if register is a condition register, but not cr0. */
827 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
829 /* True if register is an integer register. */
830 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
832 /* True if register is the XER register. */
833 #define XER_REGNO_P(N) ((N) == XER_REGNO)
835 /* True if register is an AltiVec register. */
836 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
838 /* Return number of consecutive hard regs needed starting at reg REGNO
839 to hold something of mode MODE.
840 This is ordinarily the length in words of a value of mode MODE
841 but can be less for certain modes in special long registers.
843 POWER and PowerPC GPRs hold 32 bits worth;
844 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
846 #define HARD_REGNO_NREGS(REGNO, MODE) \
847 (FP_REGNO_P (REGNO) \
848 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
849 : ALTIVEC_REGNO_P (REGNO) \
850 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
851 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
853 #define ALTIVEC_VECTOR_MODE(MODE) \
854 ((MODE) == V16QImode \
855 || (MODE) == V8HImode \
856 || (MODE) == V4SFmode \
857 || (MODE) == V4SImode)
859 /* Define this macro to be nonzero if the port is prepared to handle
860 insns involving vector mode MODE. At the very least, it must have
861 move patterns for this mode. */
863 #define VECTOR_MODE_SUPPORTED_P(MODE) \
864 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
866 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
867 For POWER and PowerPC, the GPRs can hold any mode, but the float
868 registers only can hold floating modes and DImode, and CR register only
869 can hold CC modes. We cannot put TImode anywhere except general
870 register and it must be able to fit within the register set. */
872 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
873 (FP_REGNO_P (REGNO) ? \
874 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
875 || (GET_MODE_CLASS (MODE) == MODE_INT \
876 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
877 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
878 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
879 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
880 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
881 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
884 /* Value is 1 if it is a good idea to tie two pseudo registers
885 when one has mode MODE1 and one has mode MODE2.
886 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
887 for any hard reg, then this must be 0 for correct output. */
888 #define MODES_TIEABLE_P(MODE1, MODE2) \
889 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
890 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
891 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
892 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
893 : GET_MODE_CLASS (MODE1) == MODE_CC \
894 ? GET_MODE_CLASS (MODE2) == MODE_CC \
895 : GET_MODE_CLASS (MODE2) == MODE_CC \
896 ? GET_MODE_CLASS (MODE1) == MODE_CC \
897 : ALTIVEC_VECTOR_MODE (MODE1) \
898 ? ALTIVEC_VECTOR_MODE (MODE2) \
899 : ALTIVEC_VECTOR_MODE (MODE2) \
900 ? ALTIVEC_VECTOR_MODE (MODE1) \
903 /* A C expression returning the cost of moving data from a register of class
904 CLASS1 to one of CLASS2.
906 On the RS/6000, copying between floating-point and fixed-point
907 registers is expensive. */
909 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
910 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
911 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
912 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
913 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
914 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
915 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
916 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
917 || (CLASS1) == LINK_OR_CTR_REGS) \
918 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
919 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
920 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
923 /* A C expressions returning the cost of moving data of MODE from a register to
926 On the RS/6000, bump this up a bit. */
928 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
929 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
930 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
934 /* Specify the cost of a branch insn; roughly the number of extra insns that
935 should be added to avoid a branch.
937 Set this to 3 on the RS/6000 since that is roughly the average cost of an
938 unscheduled conditional branch. */
940 #define BRANCH_COST 3
942 /* Define this macro to change register usage conditional on target flags.
943 Set MQ register fixed (already call_used) if not POWER architecture
944 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
945 64-bit AIX reserves GPR13 for thread-private data.
946 Conditionally disable FPRs. */
948 #define CONDITIONAL_REGISTER_USAGE \
951 if (! TARGET_POWER) \
952 fixed_regs[64] = 1; \
954 fixed_regs[13] = call_used_regs[13] \
955 = call_really_used_regs[13] = 1; \
956 if (TARGET_SOFT_FLOAT) \
957 for (i = 32; i < 64; i++) \
958 fixed_regs[i] = call_used_regs[i] \
959 = call_really_used_regs[i] = 1; \
960 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) \
961 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
962 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
963 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
964 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
965 global_regs[PIC_OFFSET_TABLE_REGNUM] \
966 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
967 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \
968 = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
969 if (! TARGET_ALTIVEC) \
970 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
971 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
972 if (TARGET_ALTIVEC_ABI) \
973 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
974 call_used_regs[i] = call_really_used_regs[i] = 1; \
977 /* Specify the registers used for certain standard purposes.
978 The values of these macros are register numbers. */
980 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
981 /* #define PC_REGNUM */
983 /* Register to use for pushing function arguments. */
984 #define STACK_POINTER_REGNUM 1
986 /* Base register for access to local variables of the function. */
987 #define FRAME_POINTER_REGNUM 31
989 /* Value should be nonzero if functions must have frame pointers.
990 Zero means the frame pointer need not be set up (and parms
991 may be accessed via the stack pointer) in functions that seem suitable.
992 This is computed in `reload', in reload1.c. */
993 #define FRAME_POINTER_REQUIRED 0
995 /* Base register for access to arguments of the function. */
996 #define ARG_POINTER_REGNUM 67
998 /* Place to put static chain when calling a function that requires it. */
999 #define STATIC_CHAIN_REGNUM 11
1001 /* Link register number. */
1002 #define LINK_REGISTER_REGNUM 65
1004 /* Count register number. */
1005 #define COUNT_REGISTER_REGNUM 66
1007 /* Place that structure value return address is placed.
1009 On the RS/6000, it is passed as an extra parameter. */
1010 #define STRUCT_VALUE 0
1012 /* Define the classes of registers for register constraints in the
1013 machine description. Also define ranges of constants.
1015 One of the classes must always be named ALL_REGS and include all hard regs.
1016 If there is more than one class, another class must be named NO_REGS
1017 and contain no registers.
1019 The name GENERAL_REGS must be the name of a class (or an alias for
1020 another name such as ALL_REGS). This is the class of registers
1021 that is allowed by "g" or "r" in a register constraint.
1022 Also, registers outside this class are allocated only when
1023 instructions express preferences for them.
1025 The classes must be numbered in nondecreasing order; that is,
1026 a larger-numbered class must never be contained completely
1027 in a smaller-numbered class.
1029 For any two classes, it is very desirable that there be another
1030 class that represents their union. */
1032 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1033 and condition registers, plus three special registers, MQ, CTR, and the
1036 However, r0 is special in that it cannot be used as a base register.
1037 So make a class for registers valid as base registers.
1039 Also, cr0 is the only condition code register that can be used in
1040 arithmetic insns, so make a separate class for it. */
1065 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1067 /* Give names of register classes as strings for dump file. */
1069 #define REG_CLASS_NAMES \
1077 "NON_SPECIAL_REGS", \
1081 "LINK_OR_CTR_REGS", \
1083 "SPEC_OR_GEN_REGS", \
1091 /* Define which registers fit in which classes.
1092 This is an initializer for a vector of HARD_REG_SET
1093 of length N_REG_CLASSES. */
1095 #define REG_CLASS_CONTENTS \
1097 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1098 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1099 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1100 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1101 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1102 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1103 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1104 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1105 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1106 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1107 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1108 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1109 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1110 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1111 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1112 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1113 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1114 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1117 /* The same information, inverted:
1118 Return the class number of the smallest class containing
1119 reg number REGNO. This could be a conditional expression
1120 or could index an array. */
1122 #define REGNO_REG_CLASS(REGNO) \
1123 ((REGNO) == 0 ? GENERAL_REGS \
1124 : (REGNO) < 32 ? BASE_REGS \
1125 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1126 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1127 : (REGNO) == CR0_REGNO ? CR0_REGS \
1128 : CR_REGNO_P (REGNO) ? CR_REGS \
1129 : (REGNO) == MQ_REGNO ? MQ_REGS \
1130 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1131 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1132 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1133 : (REGNO) == XER_REGNO ? XER_REGS \
1134 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1137 /* The class value for index registers, and the one for base regs. */
1138 #define INDEX_REG_CLASS GENERAL_REGS
1139 #define BASE_REG_CLASS BASE_REGS
1141 /* Get reg_class from a letter such as appears in the machine description. */
1143 #define REG_CLASS_FROM_LETTER(C) \
1144 ((C) == 'f' ? FLOAT_REGS \
1145 : (C) == 'b' ? BASE_REGS \
1146 : (C) == 'h' ? SPECIAL_REGS \
1147 : (C) == 'q' ? MQ_REGS \
1148 : (C) == 'c' ? CTR_REGS \
1149 : (C) == 'l' ? LINK_REGS \
1150 : (C) == 'v' ? ALTIVEC_REGS \
1151 : (C) == 'x' ? CR0_REGS \
1152 : (C) == 'y' ? CR_REGS \
1153 : (C) == 'z' ? XER_REGS \
1156 /* The letters I, J, K, L, M, N, and P in a register constraint string
1157 can be used to stand for particular ranges of immediate operands.
1158 This macro defines what the ranges are.
1159 C is the letter, and VALUE is a constant value.
1160 Return 1 if VALUE is in the range specified by C.
1162 `I' is a signed 16-bit constant
1163 `J' is a constant with only the high-order 16 bits non-zero
1164 `K' is a constant with only the low-order 16 bits non-zero
1165 `L' is a signed 16-bit constant shifted left 16 bits
1166 `M' is a constant that is greater than 31
1167 `N' is a positive constant that is an exact power of two
1168 `O' is the constant zero
1169 `P' is a constant whose negation is a signed 16-bit constant */
1171 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1172 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1173 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1174 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1175 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1176 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1177 : (C) == 'M' ? (VALUE) > 31 \
1178 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1179 : (C) == 'O' ? (VALUE) == 0 \
1180 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1183 /* Similar, but for floating constants, and defining letters G and H.
1184 Here VALUE is the CONST_DOUBLE rtx itself.
1186 We flag for special constants when we can copy the constant into
1187 a general register in two insns for DF/DI and one insn for SF.
1189 'H' is used for DI/DF constants that take 3 insns. */
1191 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1192 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1193 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1194 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1197 /* Optional extra constraints for this machine.
1199 'Q' means that is a memory operand that is just an offset from a reg.
1200 'R' is for AIX TOC entries.
1201 'S' is a constant that can be placed into a 64-bit mask operand
1202 'T' is a consatnt that can be placed into a 32-bit mask operand
1203 'U' is for V.4 small data references. */
1205 #define EXTRA_CONSTRAINT(OP, C) \
1206 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1207 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1208 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1209 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1210 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1211 && small_data_operand (OP, GET_MODE (OP))) \
1214 /* Given an rtx X being reloaded into a reg required to be
1215 in class CLASS, return the class of reg to actually use.
1216 In general this is just CLASS; but on some machines
1217 in some cases it is preferable to use a more restrictive class.
1219 On the RS/6000, we have to return NO_REGS when we want to reload a
1220 floating-point CONST_DOUBLE to force it to be copied to memory.
1222 We also don't want to reload integer values into floating-point
1223 registers if we can at all help it. In fact, this can
1224 cause reload to abort, if it tries to generate a reload of CTR
1225 into a FP register and discovers it doesn't have the memory location
1228 ??? Would it be a good idea to have reload do the converse, that is
1229 try to reload floating modes into FP registers if possible?
1232 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1233 (((GET_CODE (X) == CONST_DOUBLE \
1234 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1236 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1237 && (CLASS) == NON_SPECIAL_REGS) \
1241 /* Return the register class of a scratch register needed to copy IN into
1242 or out of a register in CLASS in MODE. If it can be done directly,
1243 NO_REGS is returned. */
1245 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1246 secondary_reload_class (CLASS, MODE, IN)
1248 /* If we are copying between FP or AltiVec registers and anything
1249 else, we need a memory location. */
1251 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1252 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1253 || (CLASS2) == FLOAT_REGS \
1254 || (CLASS1) == ALTIVEC_REGS \
1255 || (CLASS2) == ALTIVEC_REGS))
1257 /* Return the maximum number of consecutive registers
1258 needed to represent mode MODE in a register of class CLASS.
1260 On RS/6000, this is the size of MODE in words,
1261 except in the FP regs, where a single reg is enough for two words. */
1262 #define CLASS_MAX_NREGS(CLASS, MODE) \
1263 (((CLASS) == FLOAT_REGS) \
1264 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1265 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1267 /* If defined, gives a class of registers that cannot be used as the
1268 operand of a SUBREG that changes the mode of the object illegally. */
1270 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1272 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1274 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1275 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1277 /* Stack layout; function entry, exit and calling. */
1279 /* Enumeration to give which calling sequence to use. */
1282 ABI_AIX, /* IBM's AIX */
1283 ABI_AIX_NODESC, /* AIX calling sequence minus
1284 function descriptors */
1285 ABI_V4, /* System V.4/eabi */
1286 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1289 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1291 /* Structure used to define the rs6000 stack */
1292 typedef struct rs6000_stack {
1293 int first_gp_reg_save; /* first callee saved GP register used */
1294 int first_fp_reg_save; /* first callee saved FP register used */
1295 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1296 int lr_save_p; /* true if the link reg needs to be saved */
1297 int cr_save_p; /* true if the CR reg needs to be saved */
1298 unsigned int vrsave_mask; /* mask of vec registers to save */
1299 int toc_save_p; /* true if the TOC needs to be saved */
1300 int push_p; /* true if we need to allocate stack space */
1301 int calls_p; /* true if the function makes any calls */
1302 enum rs6000_abi abi; /* which ABI to use */
1303 int gp_save_offset; /* offset to save GP regs from initial SP */
1304 int fp_save_offset; /* offset to save FP regs from initial SP */
1305 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */
1306 int lr_save_offset; /* offset to save LR from initial SP */
1307 int cr_save_offset; /* offset to save CR from initial SP */
1308 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1309 int toc_save_offset; /* offset to save the TOC pointer */
1310 int varargs_save_offset; /* offset to save the varargs registers */
1311 int ehrd_offset; /* offset to EH return data */
1312 int reg_size; /* register size (4 or 8) */
1313 int varargs_size; /* size to hold V.4 args passed in regs */
1314 int vars_size; /* variable save area size */
1315 int parm_size; /* outgoing parameter size */
1316 int save_size; /* save area size */
1317 int fixed_size; /* fixed size of stack frame */
1318 int gp_size; /* size of saved GP registers */
1319 int fp_size; /* size of saved FP registers */
1320 int altivec_size; /* size of saved AltiVec registers */
1321 int cr_size; /* size to hold CR if not in save_size */
1322 int lr_size; /* size to hold LR if not in save_size */
1323 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1324 int altivec_padding_size; /* size of altivec alignment padding if
1326 int toc_size; /* size to hold TOC if not in save_size */
1327 int total_size; /* total bytes allocated for stack */
1330 /* Define this if pushing a word on the stack
1331 makes the stack pointer a smaller address. */
1332 #define STACK_GROWS_DOWNWARD
1334 /* Define this if the nominal address of the stack frame
1335 is at the high-address end of the local variables;
1336 that is, each additional local variable allocated
1337 goes at a more negative offset in the frame.
1339 On the RS/6000, we grow upwards, from the area after the outgoing
1341 /* #define FRAME_GROWS_DOWNWARD */
1343 /* Size of the outgoing register save area */
1344 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1345 || DEFAULT_ABI == ABI_AIX_NODESC \
1346 || DEFAULT_ABI == ABI_DARWIN) \
1347 ? (TARGET_64BIT ? 64 : 32) \
1350 /* Size of the fixed area on the stack */
1351 #define RS6000_SAVE_AREA \
1352 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1353 << (TARGET_64BIT ? 1 : 0))
1355 /* MEM representing address to save the TOC register */
1356 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1357 plus_constant (stack_pointer_rtx, \
1358 (TARGET_32BIT ? 20 : 40)))
1360 /* Size of the V.4 varargs area if needed */
1361 #define RS6000_VARARGS_AREA 0
1363 /* Align an address */
1364 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1366 /* Size of V.4 varargs area in bytes */
1367 #define RS6000_VARARGS_SIZE \
1368 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1370 /* Offset within stack frame to start allocating local variables at.
1371 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1372 first local allocated. Otherwise, it is the offset to the BEGINNING
1373 of the first local allocated.
1375 On the RS/6000, the frame pointer is the same as the stack pointer,
1376 except for dynamic allocations. So we start after the fixed area and
1377 outgoing parameter area. */
1379 #define STARTING_FRAME_OFFSET \
1380 (RS6000_ALIGN (current_function_outgoing_args_size, \
1381 TARGET_ALTIVEC ? 16 : 8) \
1382 + RS6000_VARARGS_AREA \
1385 /* Offset from the stack pointer register to an item dynamically
1386 allocated on the stack, e.g., by `alloca'.
1388 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1389 length of the outgoing arguments. The default is correct for most
1390 machines. See `function.c' for details. */
1391 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1392 (RS6000_ALIGN (current_function_outgoing_args_size, \
1393 TARGET_ALTIVEC ? 16 : 8) \
1394 + (STACK_POINTER_OFFSET))
1396 /* If we generate an insn to push BYTES bytes,
1397 this says how many the stack pointer really advances by.
1398 On RS/6000, don't define this because there are no push insns. */
1399 /* #define PUSH_ROUNDING(BYTES) */
1401 /* Offset of first parameter from the argument pointer register value.
1402 On the RS/6000, we define the argument pointer to the start of the fixed
1404 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1406 /* Offset from the argument pointer register value to the top of
1407 stack. This is different from FIRST_PARM_OFFSET because of the
1408 register save area. */
1409 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1411 /* Define this if stack space is still allocated for a parameter passed
1412 in a register. The value is the number of bytes allocated to this
1414 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1416 /* Define this if the above stack space is to be considered part of the
1417 space allocated by the caller. */
1418 #define OUTGOING_REG_PARM_STACK_SPACE
1420 /* This is the difference between the logical top of stack and the actual sp.
1422 For the RS/6000, sp points past the fixed area. */
1423 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1425 /* Define this if the maximum size of all the outgoing args is to be
1426 accumulated and pushed during the prologue. The amount can be
1427 found in the variable current_function_outgoing_args_size. */
1428 #define ACCUMULATE_OUTGOING_ARGS 1
1430 /* Value is the number of bytes of arguments automatically
1431 popped when returning from a subroutine call.
1432 FUNDECL is the declaration node of the function (as a tree),
1433 FUNTYPE is the data type of the function (as a tree),
1434 or for a library call it is an identifier node for the subroutine name.
1435 SIZE is the number of bytes of arguments passed on the stack. */
1437 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1439 /* Define how to find the value returned by a function.
1440 VALTYPE is the data type of the value (as a tree).
1441 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1442 otherwise, FUNC is 0.
1444 On RS/6000 an integer value is in r3 and a floating-point value is in
1445 fp1, unless -msoft-float. */
1447 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1448 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1449 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1450 || POINTER_TYPE_P (VALTYPE) \
1451 ? word_mode : TYPE_MODE (VALTYPE), \
1452 TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
1453 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1454 ? FP_ARG_RETURN : GP_ARG_RETURN)
1456 /* Define how to find the value returned by a library function
1457 assuming the value has mode MODE. */
1459 #define LIBCALL_VALUE(MODE) \
1460 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1461 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1462 && TARGET_HARD_FLOAT \
1463 ? FP_ARG_RETURN : GP_ARG_RETURN)
1465 /* The AIX ABI for the RS/6000 specifies that all structures are
1466 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1467 specifies that structures <= 8 bytes are returned in r3/r4, but a
1468 draft put them in memory, and GCC used to implement the draft
1469 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1470 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1471 compatibility can change DRAFT_V4_STRUCT_RET to override the
1472 default, and -m switches get the final word. See
1473 rs6000_override_options for more details.
1475 int_size_in_bytes returns -1 for variable size objects, which go in
1476 memory always. The cast to unsigned makes -1 > 8. */
1478 #define RETURN_IN_MEMORY(TYPE) \
1479 (AGGREGATE_TYPE_P (TYPE) && \
1480 (TARGET_AIX_STRUCT_RET || \
1481 (unsigned HOST_WIDEST_INT) int_size_in_bytes (TYPE) > 8))
1483 /* DRAFT_V4_STRUCT_RET defaults off. */
1484 #define DRAFT_V4_STRUCT_RET 0
1486 /* Let RETURN_IN_MEMORY control what happens. */
1487 #define DEFAULT_PCC_STRUCT_RETURN 0
1489 /* Mode of stack savearea.
1490 FUNCTION is VOIDmode because calling convention maintains SP.
1491 BLOCK needs Pmode for SP.
1492 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1493 #define STACK_SAVEAREA_MODE(LEVEL) \
1494 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1495 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1497 /* Minimum and maximum general purpose registers used to hold arguments. */
1498 #define GP_ARG_MIN_REG 3
1499 #define GP_ARG_MAX_REG 10
1500 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1502 /* Minimum and maximum floating point registers used to hold arguments. */
1503 #define FP_ARG_MIN_REG 33
1504 #define FP_ARG_AIX_MAX_REG 45
1505 #define FP_ARG_V4_MAX_REG 40
1506 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1507 || DEFAULT_ABI == ABI_AIX_NODESC \
1508 || DEFAULT_ABI == ABI_DARWIN) \
1509 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1510 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1512 /* Minimum and maximum AltiVec registers used to hold arguments. */
1513 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1514 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1515 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1517 /* Return registers */
1518 #define GP_ARG_RETURN GP_ARG_MIN_REG
1519 #define FP_ARG_RETURN FP_ARG_MIN_REG
1520 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1522 /* Flags for the call/call_value rtl operations set up by function_arg */
1523 #define CALL_NORMAL 0x00000000 /* no special processing */
1524 /* Bits in 0x00000001 are unused. */
1525 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1526 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1527 #define CALL_LONG 0x00000008 /* always call indirect */
1529 /* 1 if N is a possible register number for a function value
1530 as seen by the caller.
1532 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1533 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1534 || ((N) == FP_ARG_RETURN) \
1535 || (TARGET_ALTIVEC && \
1536 (N) == ALTIVEC_ARG_RETURN))
1538 /* 1 if N is a possible register number for function argument passing.
1539 On RS/6000, these are r3-r10 and fp1-fp13.
1540 On AltiVec, v2 - v13 are used for passing vectors. */
1541 #define FUNCTION_ARG_REGNO_P(N) \
1542 ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1543 || (TARGET_ALTIVEC && \
1544 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1545 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1548 /* A C structure for machine-specific, per-function data.
1549 This is added to the cfun structure. */
1550 typedef struct machine_function
1552 /* Whether a System V.4 varargs area was created. */
1554 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1555 int ra_needs_full_frame;
1558 /* Define a data type for recording info about an argument list
1559 during the scan of that argument list. This data type should
1560 hold all necessary information about the function itself
1561 and about the args processed so far, enough to enable macros
1562 such as FUNCTION_ARG to determine where the next arg should go.
1564 On the RS/6000, this is a structure. The first element is the number of
1565 total argument words, the second is used to store the next
1566 floating-point register number, and the third says how many more args we
1567 have prototype types for.
1569 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1570 the next availible GP register, `fregno' is the next available FP
1571 register, and `words' is the number of words used on the stack.
1573 The varargs/stdarg support requires that this structure's size
1574 be a multiple of sizeof(int). */
1576 typedef struct rs6000_args
1578 int words; /* # words used for passing GP registers */
1579 int fregno; /* next available FP register */
1580 int vregno; /* next available AltiVec register */
1581 int nargs_prototype; /* # args left in the current prototype */
1582 int orig_nargs; /* Original value of nargs_prototype */
1583 int prototype; /* Whether a prototype was defined */
1584 int call_cookie; /* Do special things for this call */
1585 int sysv_gregno; /* next available GP register */
1588 /* Define intermediate macro to compute the size (in registers) of an argument
1591 #define RS6000_ARG_SIZE(MODE, TYPE) \
1592 ((MODE) != BLKmode \
1593 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1594 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1595 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1597 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1598 for a call to a function whose data type is FNTYPE.
1599 For a library call, FNTYPE is 0. */
1601 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1602 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1604 /* Similar, but when scanning the definition of a procedure. We always
1605 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1607 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1608 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1610 /* Update the data in CUM to advance over an argument
1611 of mode MODE and data type TYPE.
1612 (TYPE is null for libcalls where that information may not be available.) */
1614 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1615 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1617 /* Non-zero if we can use a floating-point register to pass this arg. */
1618 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1619 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1620 && (CUM).fregno <= FP_ARG_MAX_REG \
1621 && TARGET_HARD_FLOAT)
1623 /* Non-zero if we can use an AltiVec register to pass this arg. */
1624 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1625 (ALTIVEC_VECTOR_MODE (MODE) \
1626 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1627 && TARGET_ALTIVEC_ABI)
1629 /* Determine where to put an argument to a function.
1630 Value is zero to push the argument on the stack,
1631 or a hard register in which to store the argument.
1633 MODE is the argument's machine mode.
1634 TYPE is the data type of the argument (as a tree).
1635 This is null for libcalls where that information may
1637 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1638 the preceding args and about the function being called.
1639 NAMED is nonzero if this argument is a named parameter
1640 (otherwise it is an extra parameter matching an ellipsis).
1642 On RS/6000 the first eight words of non-FP are normally in registers
1643 and the rest are pushed. The first 13 FP args are in registers.
1645 If this is floating-point and no prototype is specified, we use
1646 both an FP and integer register (or possibly FP reg and stack). Library
1647 functions (when TYPE is zero) always have the proper types for args,
1648 so we can pass the FP value just in one register. emit_library_function
1649 doesn't support EXPR_LIST anyway. */
1651 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1652 function_arg (&CUM, MODE, TYPE, NAMED)
1654 /* For an arg passed partly in registers and partly in memory,
1655 this is the number of registers used.
1656 For args passed entirely in registers or entirely in memory, zero. */
1658 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1659 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1661 /* A C expression that indicates when an argument must be passed by
1662 reference. If nonzero for an argument, a copy of that argument is
1663 made in memory and a pointer to the argument is passed instead of
1664 the argument itself. The pointer is passed in whatever way is
1665 appropriate for passing a pointer to that type. */
1667 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1668 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1670 /* If defined, a C expression which determines whether, and in which
1671 direction, to pad out an argument with extra space. The value
1672 should be of type `enum direction': either `upward' to pad above
1673 the argument, `downward' to pad below, or `none' to inhibit
1676 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1678 /* If defined, a C expression that gives the alignment boundary, in bits,
1679 of an argument with the specified mode and type. If it is not defined,
1680 PARM_BOUNDARY is used for all arguments. */
1682 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1683 function_arg_boundary (MODE, TYPE)
1685 /* Perform any needed actions needed for a function that is receiving a
1686 variable number of arguments.
1690 MODE and TYPE are the mode and type of the current parameter.
1692 PRETEND_SIZE is a variable that should be set to the amount of stack
1693 that must be pushed by the prolog to pretend that our caller pushed
1696 Normally, this macro will push all remaining incoming registers on the
1697 stack and set PRETEND_SIZE to the length of the registers pushed. */
1699 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1700 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1702 /* Define the `__builtin_va_list' type for the ABI. */
1703 #define BUILD_VA_LIST_TYPE(VALIST) \
1704 (VALIST) = rs6000_build_va_list ()
1706 /* Implement `va_start' for varargs and stdarg. */
1707 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1708 rs6000_va_start (stdarg, valist, nextarg)
1710 /* Implement `va_arg'. */
1711 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1712 rs6000_va_arg (valist, type)
1714 /* Define this macro to be a nonzero value if the location where a function
1715 argument is passed depends on whether or not it is a named argument. */
1716 #define STRICT_ARGUMENT_NAMING 1
1718 /* Output assembler code to FILE to increment profiler label # LABELNO
1719 for profiling a function entry. */
1721 #define FUNCTION_PROFILER(FILE, LABELNO) \
1722 output_function_profiler ((FILE), (LABELNO));
1724 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1725 the stack pointer does not matter. No definition is equivalent to
1728 On the RS/6000, this is non-zero because we can restore the stack from
1729 its backpointer, which we maintain. */
1730 #define EXIT_IGNORE_STACK 1
1732 /* Define this macro as a C expression that is nonzero for registers
1733 that are used by the epilogue or the return' pattern. The stack
1734 and frame pointer registers are already be assumed to be used as
1737 #define EPILOGUE_USES(REGNO) \
1738 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1739 || (REGNO) == VRSAVE_REGNO \
1740 || (current_function_calls_eh_return \
1742 && (REGNO) == TOC_REGISTER))
1745 /* TRAMPOLINE_TEMPLATE deleted */
1747 /* Length in units of the trampoline for entering a nested function. */
1749 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1751 /* Emit RTL insns to initialize the variable parts of a trampoline.
1752 FNADDR is an RTX for the address of the function's pure code.
1753 CXT is an RTX for the static chain value for the function. */
1755 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1756 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1758 /* Definitions for __builtin_return_address and __builtin_frame_address.
1759 __builtin_return_address (0) should give link register (65), enable
1761 /* This should be uncommented, so that the link register is used, but
1762 currently this would result in unmatched insns and spilling fixed
1763 registers so we'll leave it for another day. When these problems are
1764 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1766 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1768 /* Number of bytes into the frame return addresses can be found. See
1769 rs6000_stack_info in rs6000.c for more information on how the different
1770 abi's store the return address. */
1771 #define RETURN_ADDRESS_OFFSET \
1772 ((DEFAULT_ABI == ABI_AIX \
1773 || DEFAULT_ABI == ABI_DARWIN \
1774 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1775 (DEFAULT_ABI == ABI_V4) ? 4 : \
1776 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1778 /* The current return address is in link register (65). The return address
1779 of anything farther back is accessed normally at an offset of 8 from the
1781 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1782 (rs6000_return_addr (COUNT, FRAME))
1785 /* Definitions for register eliminations.
1787 We have two registers that can be eliminated on the RS/6000. First, the
1788 frame pointer register can often be eliminated in favor of the stack
1789 pointer register. Secondly, the argument pointer register can always be
1790 eliminated; it is replaced with either the stack or frame pointer.
1792 In addition, we use the elimination mechanism to see if r30 is needed
1793 Initially we assume that it isn't. If it is, we spill it. This is done
1794 by making it an eliminable register. We replace it with itself so that
1795 if it isn't needed, then existing uses won't be modified. */
1797 /* This is an array of structures. Each structure initializes one pair
1798 of eliminable registers. The "from" register number is given first,
1799 followed by "to". Eliminations of the same "from" register are listed
1800 in order of preference. */
1801 #define ELIMINABLE_REGS \
1802 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1803 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1804 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1807 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1808 Frame pointer elimination is automatically handled.
1810 For the RS/6000, if frame pointer elimination is being done, we would like
1811 to convert ap into fp, not sp.
1813 We need r30 if -mminimal-toc was specified, and there are constant pool
1816 #define CAN_ELIMINATE(FROM, TO) \
1817 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1818 ? ! frame_pointer_needed \
1819 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1822 /* Define the offset between two registers, one to be eliminated, and the other
1823 its replacement, at the start of a routine. */
1824 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1826 rs6000_stack_t *info = rs6000_stack_info (); \
1828 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1829 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1830 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1831 (OFFSET) = info->total_size; \
1832 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1833 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1834 else if ((FROM) == 30) \
1840 /* Addressing modes, and classification of registers for them. */
1842 /* #define HAVE_POST_INCREMENT 0 */
1843 /* #define HAVE_POST_DECREMENT 0 */
1845 #define HAVE_PRE_DECREMENT 1
1846 #define HAVE_PRE_INCREMENT 1
1848 /* Macros to check register numbers against specific register classes. */
1850 /* These assume that REGNO is a hard or pseudo reg number.
1851 They give nonzero only if REGNO is a hard reg of the suitable class
1852 or a pseudo reg currently allocated to a suitable hard reg.
1853 Since they use reg_renumber, they are safe only once reg_renumber
1854 has been allocated, which happens in local-alloc.c. */
1856 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1857 ((REGNO) < FIRST_PSEUDO_REGISTER \
1858 ? (REGNO) <= 31 || (REGNO) == 67 \
1859 : (reg_renumber[REGNO] >= 0 \
1860 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1862 #define REGNO_OK_FOR_BASE_P(REGNO) \
1863 ((REGNO) < FIRST_PSEUDO_REGISTER \
1864 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1865 : (reg_renumber[REGNO] > 0 \
1866 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1868 /* Maximum number of registers that can appear in a valid memory address. */
1870 #define MAX_REGS_PER_ADDRESS 2
1872 /* Recognize any constant value that is a valid address. */
1874 #define CONSTANT_ADDRESS_P(X) \
1875 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1876 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1877 || GET_CODE (X) == HIGH)
1879 /* Nonzero if the constant value X is a legitimate general operand.
1880 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1882 On the RS/6000, all integer constants are acceptable, most won't be valid
1883 for particular insns, though. Only easy FP constants are
1886 #define LEGITIMATE_CONSTANT_P(X) \
1887 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1888 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1889 || easy_fp_constant (X, GET_MODE (X)))
1891 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1892 and check its validity for a certain class.
1893 We have two alternate definitions for each of them.
1894 The usual definition accepts all pseudo regs; the other rejects
1895 them unless they have been allocated suitable hard regs.
1896 The symbol REG_OK_STRICT causes the latter definition to be used.
1898 Most source files want to accept pseudo regs in the hope that
1899 they will get allocated to the class that the insn wants them to be in.
1900 Source files for reload pass need to be strict.
1901 After reload, it makes no difference, since pseudo regs have
1902 been eliminated by then. */
1904 #ifdef REG_OK_STRICT
1905 # define REG_OK_STRICT_FLAG 1
1907 # define REG_OK_STRICT_FLAG 0
1910 /* Nonzero if X is a hard reg that can be used as an index
1911 or if it is a pseudo reg in the non-strict case. */
1912 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1914 && (REGNO (X) <= 31 \
1915 || REGNO (X) == ARG_POINTER_REGNUM \
1916 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1917 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1919 /* Nonzero if X is a hard reg that can be used as a base reg
1920 or if it is a pseudo reg in the non-strict case. */
1921 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1922 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1924 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1925 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1927 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1928 that is a valid memory address for an instruction.
1929 The MODE argument is the machine mode for the MEM expression
1930 that wants to use this address.
1932 On the RS/6000, there are four valid address: a SYMBOL_REF that
1933 refers to a constant pool entry of an address (or the sum of it
1934 plus a constant), a short (16-bit signed) constant plus a register,
1935 the sum of two registers, or a register indirect, possibly with an
1936 auto-increment. For DFmode and DImode with an constant plus register,
1937 we must ensure that both words are addressable or PowerPC64 with offset
1940 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1941 32-bit DImode, TImode), indexed addressing cannot be used because
1942 adjacent memory cells are accessed by adding word-sized offsets
1943 during assembly output. */
1945 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1947 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1949 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1951 && GET_CODE (X) == PLUS \
1952 && GET_CODE (XEXP (X, 0)) == REG \
1953 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1954 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1956 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1957 (DEFAULT_ABI == ABI_V4 \
1958 && !flag_pic && !TARGET_TOC \
1959 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1960 && small_data_operand (X, MODE))
1962 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1963 (GET_CODE (X) == CONST_INT \
1964 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1966 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1967 (GET_CODE (X) == PLUS \
1968 && GET_CODE (XEXP (X, 0)) == REG \
1969 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1970 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1971 && (! ALTIVEC_VECTOR_MODE (MODE) || INTVAL (X) == 0) \
1972 && (((MODE) != DFmode && (MODE) != DImode) \
1974 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1975 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1976 && ((MODE) != TImode \
1978 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1979 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1980 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1982 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1983 (GET_CODE (X) == PLUS \
1984 && GET_CODE (XEXP (X, 0)) == REG \
1985 && GET_CODE (XEXP (X, 1)) == REG \
1986 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1987 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
1988 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
1989 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
1991 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
1992 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
1994 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
1996 && ! flag_pic && ! TARGET_TOC \
1997 && GET_MODE_NUNITS (MODE) == 1 \
1998 && (GET_MODE_BITSIZE (MODE) <= 32 \
1999 || (TARGET_HARD_FLOAT && (MODE) == DFmode)) \
2000 && GET_CODE (X) == LO_SUM \
2001 && GET_CODE (XEXP (X, 0)) == REG \
2002 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2003 && CONSTANT_P (XEXP (X, 1)))
2005 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2006 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2010 /* Try machine-dependent ways of modifying an illegitimate address
2011 to be legitimate. If we find one, return the new, valid address.
2012 This macro is used in only one place: `memory_address' in explow.c.
2014 OLDX is the address as it was before break_out_memory_refs was called.
2015 In some cases it is useful to look at this to decide what needs to be done.
2017 MODE and WIN are passed so that this macro can use
2018 GO_IF_LEGITIMATE_ADDRESS.
2020 It is always safe for this macro to do nothing. It exists to recognize
2021 opportunities to optimize the output.
2023 On RS/6000, first check for the sum of a register with a constant
2024 integer that is out of range. If so, generate code to add the
2025 constant with the low-order 16 bits masked to the register and force
2026 this result into another register (this can be done with `cau').
2027 Then generate an address of REG+(CONST&0xffff), allowing for the
2028 possibility of bit 16 being a one.
2030 Then check for the sum of a register and something not constant, try to
2031 load the other things into a register and return the sum. */
2033 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2034 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2035 if (result != NULL_RTX) \
2042 /* Try a machine-dependent way of reloading an illegitimate address
2043 operand. If we find one, push the reload and jump to WIN. This
2044 macro is used in only one place: `find_reloads_address' in reload.c.
2046 Implemented on rs6000 by rs6000_legitimize_reload_address.
2047 Note that (X) is evaluated twice; this is safe in current usage. */
2049 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2052 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2053 (int)(TYPE), (IND_LEVELS), &win); \
2058 /* Go to LABEL if ADDR (a legitimate address expression)
2059 has an effect that depends on the machine mode it is used for.
2061 On the RS/6000 this is true if the address is valid with a zero offset
2062 but not with an offset of four (this means it cannot be used as an
2063 address for DImode or DFmode) or is a pre-increment or decrement. Since
2064 we know it is valid, we just check for an address that is not valid with
2065 an offset of four. */
2067 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2068 { if (GET_CODE (ADDR) == PLUS \
2069 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2070 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2071 (TARGET_32BIT ? 4 : 8))) \
2073 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2075 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2077 if (GET_CODE (ADDR) == LO_SUM) \
2081 /* The register number of the register used to address a table of
2082 static data addresses in memory. In some cases this register is
2083 defined by a processor's "application binary interface" (ABI).
2084 When this macro is defined, RTL is generated for this register
2085 once, as with the stack pointer and frame pointer registers. If
2086 this macro is not defined, it is up to the machine-dependent files
2087 to allocate such a register (if necessary). */
2089 #define PIC_OFFSET_TABLE_REGNUM 30
2091 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2093 /* Define this macro if the register defined by
2094 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2095 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2097 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2099 /* By generating position-independent code, when two different
2100 programs (A and B) share a common library (libC.a), the text of
2101 the library can be shared whether or not the library is linked at
2102 the same address for both programs. In some of these
2103 environments, position-independent code requires not only the use
2104 of different addressing modes, but also special code to enable the
2105 use of these addressing modes.
2107 The `FINALIZE_PIC' macro serves as a hook to emit these special
2108 codes once the function is being compiled into assembly code, but
2109 not before. (It is not done before, because in the case of
2110 compiling an inline function, it would lead to multiple PIC
2111 prologues being included in functions which used inline functions
2112 and were compiled to assembly language.) */
2114 /* #define FINALIZE_PIC */
2116 /* A C expression that is nonzero if X is a legitimate immediate
2117 operand on the target machine when generating position independent
2118 code. You can assume that X satisfies `CONSTANT_P', so you need
2119 not check this. You can also assume FLAG_PIC is true, so you need
2120 not check it either. You need not define this macro if all
2121 constants (including `SYMBOL_REF') can be immediate operands when
2122 generating position independent code. */
2124 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2126 /* In rare cases, correct code generation requires extra machine
2127 dependent processing between the second jump optimization pass and
2128 delayed branch scheduling. On those machines, define this macro
2129 as a C statement to act on the code starting at INSN. */
2131 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2134 /* Define this if some processing needs to be done immediately before
2135 emitting code for an insn. */
2137 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2139 /* Specify the machine mode that this machine uses
2140 for the index in the tablejump instruction. */
2141 #define CASE_VECTOR_MODE SImode
2143 /* Define as C expression which evaluates to nonzero if the tablejump
2144 instruction expects the table to contain offsets from the address of the
2146 Do not define this if the table should contain absolute addresses. */
2147 #define CASE_VECTOR_PC_RELATIVE 1
2149 /* Define this as 1 if `char' should by default be signed; else as 0. */
2150 #define DEFAULT_SIGNED_CHAR 0
2152 /* This flag, if defined, says the same insns that convert to a signed fixnum
2153 also convert validly to an unsigned one. */
2155 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2157 /* Max number of bytes we can move from memory to memory
2158 in one reasonably fast instruction. */
2159 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2160 #define MAX_MOVE_MAX 8
2162 /* Nonzero if access to memory by bytes is no faster than for words.
2163 Also non-zero if doing byte operations (specifically shifts) in registers
2165 #define SLOW_BYTE_ACCESS 1
2167 /* Define if operations between registers always perform the operation
2168 on the full register even if a narrower mode is specified. */
2169 #define WORD_REGISTER_OPERATIONS
2171 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2172 will either zero-extend or sign-extend. The value of this macro should
2173 be the code that says which one of the two operations is implicitly
2174 done, NIL if none. */
2175 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2177 /* Define if loading short immediate values into registers sign extends. */
2178 #define SHORT_IMMEDIATES_SIGN_EXTEND
2180 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2181 is done just by pretending it is already truncated. */
2182 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2184 /* Specify the machine mode that pointers have.
2185 After generation of rtl, the compiler makes no further distinction
2186 between pointers and any other objects of this machine mode. */
2187 #define Pmode (TARGET_32BIT ? SImode : DImode)
2189 /* Mode of a function address in a call instruction (for indexing purposes).
2190 Doesn't matter on RS/6000. */
2191 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2193 /* Define this if addresses of constant functions
2194 shouldn't be put through pseudo regs where they can be cse'd.
2195 Desirable on machines where ordinary constants are expensive
2196 but a CALL with constant address is cheap. */
2197 #define NO_FUNCTION_CSE
2199 /* Define this to be nonzero if shift instructions ignore all but the low-order
2202 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2203 have been dropped from the PowerPC architecture. */
2205 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2207 /* Compute the cost of computing a constant rtl expression RTX
2208 whose rtx-code is CODE. The body of this macro is a portion
2209 of a switch statement. If the code is computed here,
2210 return it with a return statement. Otherwise, break from the switch.
2212 On the RS/6000, if it is valid in the insn, it is free. So this
2213 always returns 0. */
2215 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2220 case CONST_DOUBLE: \
2224 /* Provide the costs of a rtl expression. This is in the body of a
2227 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2229 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2230 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2231 + 0x8000) >= 0x10000) \
2232 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2233 ? COSTS_N_INSNS (2) \
2234 : COSTS_N_INSNS (1)); \
2238 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2239 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2240 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2241 ? COSTS_N_INSNS (2) \
2242 : COSTS_N_INSNS (1)); \
2244 switch (rs6000_cpu) \
2246 case PROCESSOR_RIOS1: \
2247 case PROCESSOR_PPC405: \
2248 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2249 ? COSTS_N_INSNS (5) \
2250 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2251 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2252 case PROCESSOR_RS64A: \
2253 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2254 ? GET_MODE (XEXP (X, 1)) != DImode \
2255 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2256 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2257 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \
2258 case PROCESSOR_RIOS2: \
2259 case PROCESSOR_MPCCORE: \
2260 case PROCESSOR_PPC604e: \
2261 return COSTS_N_INSNS (2); \
2262 case PROCESSOR_PPC601: \
2263 return COSTS_N_INSNS (5); \
2264 case PROCESSOR_PPC603: \
2265 case PROCESSOR_PPC7400: \
2266 case PROCESSOR_PPC750: \
2267 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2268 ? COSTS_N_INSNS (5) \
2269 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2270 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2271 case PROCESSOR_PPC7450: \
2272 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2273 ? COSTS_N_INSNS (4) \
2274 : COSTS_N_INSNS (3)); \
2275 case PROCESSOR_PPC403: \
2276 case PROCESSOR_PPC604: \
2277 return COSTS_N_INSNS (4); \
2278 case PROCESSOR_PPC620: \
2279 case PROCESSOR_PPC630: \
2280 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2281 ? GET_MODE (XEXP (X, 1)) != DImode \
2282 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
2283 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2284 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2288 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2289 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2290 return COSTS_N_INSNS (2); \
2291 /* otherwise fall through to normal divide. */ \
2294 switch (rs6000_cpu) \
2296 case PROCESSOR_RIOS1: \
2297 return COSTS_N_INSNS (19); \
2298 case PROCESSOR_RIOS2: \
2299 return COSTS_N_INSNS (13); \
2300 case PROCESSOR_RS64A: \
2301 return (GET_MODE (XEXP (X, 1)) != DImode \
2302 ? COSTS_N_INSNS (65) \
2303 : COSTS_N_INSNS (67)); \
2304 case PROCESSOR_MPCCORE: \
2305 return COSTS_N_INSNS (6); \
2306 case PROCESSOR_PPC403: \
2307 return COSTS_N_INSNS (33); \
2308 case PROCESSOR_PPC405: \
2309 return COSTS_N_INSNS (35); \
2310 case PROCESSOR_PPC601: \
2311 return COSTS_N_INSNS (36); \
2312 case PROCESSOR_PPC603: \
2313 return COSTS_N_INSNS (37); \
2314 case PROCESSOR_PPC604: \
2315 case PROCESSOR_PPC604e: \
2316 return COSTS_N_INSNS (20); \
2317 case PROCESSOR_PPC620: \
2318 case PROCESSOR_PPC630: \
2319 return (GET_MODE (XEXP (X, 1)) != DImode \
2320 ? COSTS_N_INSNS (21) \
2321 : COSTS_N_INSNS (37)); \
2322 case PROCESSOR_PPC750: \
2323 case PROCESSOR_PPC7400: \
2324 return COSTS_N_INSNS (19); \
2325 case PROCESSOR_PPC7450: \
2326 return COSTS_N_INSNS (23); \
2329 return COSTS_N_INSNS (4); \
2331 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2334 /* Compute the cost of an address. This is meant to approximate the size
2335 and/or execution delay of an insn using that address. If the cost is
2336 approximated by the RTL complexity, including CONST_COSTS above, as
2337 is usually the case for CISC machines, this macro should not be defined.
2338 For aggressively RISCy machines, only one insn format is allowed, so
2339 this macro should be a constant. The value of this macro only matters
2340 for valid addresses.
2342 For the RS/6000, everything is cost 0. */
2344 #define ADDRESS_COST(RTX) 0
2346 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2347 should be adjusted to reflect any required changes. This macro is used when
2348 there is some systematic length adjustment required that would be difficult
2349 to express in the length attribute. */
2351 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2353 /* Add any extra modes needed to represent the condition code.
2355 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2356 are being done and we need a separate mode for floating-point. We also
2357 use a mode for the case when we are comparing the results of two
2358 comparisons, as then only the EQ bit is valid in the register. */
2360 #define EXTRA_CC_MODES \
2361 CC(CCUNSmode, "CCUNS") \
2362 CC(CCFPmode, "CCFP") \
2363 CC(CCEQmode, "CCEQ")
2365 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2366 COMPARE, return the mode to be used for the comparison. For
2367 floating-point, CCFPmode should be used. CCUNSmode should be used
2368 for unsigned comparisons. CCEQmode should be used when we are
2369 doing an inequality comparison on the result of a
2370 comparison. CCmode should be used in all other cases. */
2372 #define SELECT_CC_MODE(OP,X,Y) \
2373 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2374 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2375 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2376 ? CCEQmode : CCmode))
2378 /* Define the information needed to generate branch and scc insns. This is
2379 stored from the compare operation. Note that we can't use "rtx" here
2380 since it hasn't been defined! */
2382 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2383 extern int rs6000_compare_fp_p;
2385 /* Control the assembler format that we output. */
2387 /* A C string constant describing how to begin a comment in the target
2388 assembler language. The compiler assumes that the comment will end at
2389 the end of the line. */
2390 #define ASM_COMMENT_START " #"
2392 /* Implicit library calls should use memcpy, not bcopy, etc. */
2394 #define TARGET_MEM_FUNCTIONS
2396 /* Flag to say the TOC is initialized */
2397 extern int toc_initialized;
2399 /* Macro to output a special constant pool entry. Go to WIN if we output
2400 it. Otherwise, it is written the usual way.
2402 On the RS/6000, toc entries are handled this way. */
2404 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2405 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2407 output_toc (FILE, X, LABELNO, MODE); \
2412 #ifdef HAVE_GAS_WEAK
2413 #define RS6000_WEAK 1
2415 #define RS6000_WEAK 0
2418 /* This implementes the `alias' attribute. */
2419 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2421 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2422 char * name = IDENTIFIER_POINTER (target); \
2423 if (TREE_CODE (decl) == FUNCTION_DECL \
2424 && DEFAULT_ABI == ABI_AIX) \
2426 if (TREE_PUBLIC (decl)) \
2428 if (RS6000_WEAK && DECL_WEAK (decl)) \
2430 fputs ("\t.weak .", FILE); \
2431 assemble_name (FILE, alias); \
2432 putc ('\n', FILE); \
2436 fputs ("\t.globl .", FILE); \
2437 assemble_name (FILE, alias); \
2438 putc ('\n', FILE); \
2443 fputs ("\t.lglobl .", FILE); \
2444 assemble_name (FILE, alias); \
2445 putc ('\n', FILE); \
2447 fputs ("\t.set .", FILE); \
2448 assemble_name (FILE, alias); \
2449 fputs (",.", FILE); \
2450 assemble_name (FILE, name); \
2451 fputc ('\n', FILE); \
2453 ASM_OUTPUT_DEF (FILE, alias, name); \
2456 /* Output to assembler file text saying following lines
2457 may contain character constants, extra white space, comments, etc. */
2459 #define ASM_APP_ON ""
2461 /* Output to assembler file text saying following lines
2462 no longer contain unusual constructs. */
2464 #define ASM_APP_OFF ""
2466 /* How to refer to registers in assembler output.
2467 This sequence is indexed by compiler's hard-register-number (see above). */
2469 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2471 #define REGISTER_NAMES \
2473 &rs6000_reg_names[ 0][0], /* r0 */ \
2474 &rs6000_reg_names[ 1][0], /* r1 */ \
2475 &rs6000_reg_names[ 2][0], /* r2 */ \
2476 &rs6000_reg_names[ 3][0], /* r3 */ \
2477 &rs6000_reg_names[ 4][0], /* r4 */ \
2478 &rs6000_reg_names[ 5][0], /* r5 */ \
2479 &rs6000_reg_names[ 6][0], /* r6 */ \
2480 &rs6000_reg_names[ 7][0], /* r7 */ \
2481 &rs6000_reg_names[ 8][0], /* r8 */ \
2482 &rs6000_reg_names[ 9][0], /* r9 */ \
2483 &rs6000_reg_names[10][0], /* r10 */ \
2484 &rs6000_reg_names[11][0], /* r11 */ \
2485 &rs6000_reg_names[12][0], /* r12 */ \
2486 &rs6000_reg_names[13][0], /* r13 */ \
2487 &rs6000_reg_names[14][0], /* r14 */ \
2488 &rs6000_reg_names[15][0], /* r15 */ \
2489 &rs6000_reg_names[16][0], /* r16 */ \
2490 &rs6000_reg_names[17][0], /* r17 */ \
2491 &rs6000_reg_names[18][0], /* r18 */ \
2492 &rs6000_reg_names[19][0], /* r19 */ \
2493 &rs6000_reg_names[20][0], /* r20 */ \
2494 &rs6000_reg_names[21][0], /* r21 */ \
2495 &rs6000_reg_names[22][0], /* r22 */ \
2496 &rs6000_reg_names[23][0], /* r23 */ \
2497 &rs6000_reg_names[24][0], /* r24 */ \
2498 &rs6000_reg_names[25][0], /* r25 */ \
2499 &rs6000_reg_names[26][0], /* r26 */ \
2500 &rs6000_reg_names[27][0], /* r27 */ \
2501 &rs6000_reg_names[28][0], /* r28 */ \
2502 &rs6000_reg_names[29][0], /* r29 */ \
2503 &rs6000_reg_names[30][0], /* r30 */ \
2504 &rs6000_reg_names[31][0], /* r31 */ \
2506 &rs6000_reg_names[32][0], /* fr0 */ \
2507 &rs6000_reg_names[33][0], /* fr1 */ \
2508 &rs6000_reg_names[34][0], /* fr2 */ \
2509 &rs6000_reg_names[35][0], /* fr3 */ \
2510 &rs6000_reg_names[36][0], /* fr4 */ \
2511 &rs6000_reg_names[37][0], /* fr5 */ \
2512 &rs6000_reg_names[38][0], /* fr6 */ \
2513 &rs6000_reg_names[39][0], /* fr7 */ \
2514 &rs6000_reg_names[40][0], /* fr8 */ \
2515 &rs6000_reg_names[41][0], /* fr9 */ \
2516 &rs6000_reg_names[42][0], /* fr10 */ \
2517 &rs6000_reg_names[43][0], /* fr11 */ \
2518 &rs6000_reg_names[44][0], /* fr12 */ \
2519 &rs6000_reg_names[45][0], /* fr13 */ \
2520 &rs6000_reg_names[46][0], /* fr14 */ \
2521 &rs6000_reg_names[47][0], /* fr15 */ \
2522 &rs6000_reg_names[48][0], /* fr16 */ \
2523 &rs6000_reg_names[49][0], /* fr17 */ \
2524 &rs6000_reg_names[50][0], /* fr18 */ \
2525 &rs6000_reg_names[51][0], /* fr19 */ \
2526 &rs6000_reg_names[52][0], /* fr20 */ \
2527 &rs6000_reg_names[53][0], /* fr21 */ \
2528 &rs6000_reg_names[54][0], /* fr22 */ \
2529 &rs6000_reg_names[55][0], /* fr23 */ \
2530 &rs6000_reg_names[56][0], /* fr24 */ \
2531 &rs6000_reg_names[57][0], /* fr25 */ \
2532 &rs6000_reg_names[58][0], /* fr26 */ \
2533 &rs6000_reg_names[59][0], /* fr27 */ \
2534 &rs6000_reg_names[60][0], /* fr28 */ \
2535 &rs6000_reg_names[61][0], /* fr29 */ \
2536 &rs6000_reg_names[62][0], /* fr30 */ \
2537 &rs6000_reg_names[63][0], /* fr31 */ \
2539 &rs6000_reg_names[64][0], /* mq */ \
2540 &rs6000_reg_names[65][0], /* lr */ \
2541 &rs6000_reg_names[66][0], /* ctr */ \
2542 &rs6000_reg_names[67][0], /* ap */ \
2544 &rs6000_reg_names[68][0], /* cr0 */ \
2545 &rs6000_reg_names[69][0], /* cr1 */ \
2546 &rs6000_reg_names[70][0], /* cr2 */ \
2547 &rs6000_reg_names[71][0], /* cr3 */ \
2548 &rs6000_reg_names[72][0], /* cr4 */ \
2549 &rs6000_reg_names[73][0], /* cr5 */ \
2550 &rs6000_reg_names[74][0], /* cr6 */ \
2551 &rs6000_reg_names[75][0], /* cr7 */ \
2553 &rs6000_reg_names[76][0], /* xer */ \
2555 &rs6000_reg_names[77][0], /* v0 */ \
2556 &rs6000_reg_names[78][0], /* v1 */ \
2557 &rs6000_reg_names[79][0], /* v2 */ \
2558 &rs6000_reg_names[80][0], /* v3 */ \
2559 &rs6000_reg_names[81][0], /* v4 */ \
2560 &rs6000_reg_names[82][0], /* v5 */ \
2561 &rs6000_reg_names[83][0], /* v6 */ \
2562 &rs6000_reg_names[84][0], /* v7 */ \
2563 &rs6000_reg_names[85][0], /* v8 */ \
2564 &rs6000_reg_names[86][0], /* v9 */ \
2565 &rs6000_reg_names[87][0], /* v10 */ \
2566 &rs6000_reg_names[88][0], /* v11 */ \
2567 &rs6000_reg_names[89][0], /* v12 */ \
2568 &rs6000_reg_names[90][0], /* v13 */ \
2569 &rs6000_reg_names[91][0], /* v14 */ \
2570 &rs6000_reg_names[92][0], /* v15 */ \
2571 &rs6000_reg_names[93][0], /* v16 */ \
2572 &rs6000_reg_names[94][0], /* v17 */ \
2573 &rs6000_reg_names[95][0], /* v18 */ \
2574 &rs6000_reg_names[96][0], /* v19 */ \
2575 &rs6000_reg_names[97][0], /* v20 */ \
2576 &rs6000_reg_names[98][0], /* v21 */ \
2577 &rs6000_reg_names[99][0], /* v22 */ \
2578 &rs6000_reg_names[100][0], /* v23 */ \
2579 &rs6000_reg_names[101][0], /* v24 */ \
2580 &rs6000_reg_names[102][0], /* v25 */ \
2581 &rs6000_reg_names[103][0], /* v26 */ \
2582 &rs6000_reg_names[104][0], /* v27 */ \
2583 &rs6000_reg_names[105][0], /* v28 */ \
2584 &rs6000_reg_names[106][0], /* v29 */ \
2585 &rs6000_reg_names[107][0], /* v30 */ \
2586 &rs6000_reg_names[108][0], /* v31 */ \
2587 &rs6000_reg_names[109][0], /* vrsave */ \
2590 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2591 following for it. Switch to use the alternate names since
2592 they are more mnemonic. */
2594 #define DEBUG_REGISTER_NAMES \
2596 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2597 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2598 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2599 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2600 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2601 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2602 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2603 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2604 "mq", "lr", "ctr", "ap", \
2605 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2607 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2608 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2609 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2610 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2614 /* Table of additional register names to use in user input. */
2616 #define ADDITIONAL_REGISTER_NAMES \
2617 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2618 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2619 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2620 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2621 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2622 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2623 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2624 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2625 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2626 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2627 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2628 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2629 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2630 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2631 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2632 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2633 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2634 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2635 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2636 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2637 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2638 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2639 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2640 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2642 /* no additional names for: mq, lr, ctr, ap */ \
2643 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2644 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2645 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2647 /* Text to write out after a CALL that may be replaced by glue code by
2648 the loader. This depends on the AIX version. */
2649 #define RS6000_CALL_GLUE "cror 31,31,31"
2651 /* This is how to output an element of a case-vector that is relative. */
2653 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2654 do { char buf[100]; \
2655 fputs ("\t.long ", FILE); \
2656 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2657 assemble_name (FILE, buf); \
2659 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2660 assemble_name (FILE, buf); \
2661 putc ('\n', FILE); \
2664 /* This is how to output an assembler line
2665 that says to advance the location counter
2666 to a multiple of 2**LOG bytes. */
2668 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2670 fprintf (FILE, "\t.align %d\n", (LOG))
2672 /* Store in OUTPUT a string (made with alloca) containing
2673 an assembler-name for a local static variable named NAME.
2674 LABELNO is an integer which is different for each call. */
2676 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2677 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2678 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2680 /* Pick up the return address upon entry to a procedure. Used for
2681 dwarf2 unwind information. This also enables the table driven
2684 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2685 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2687 /* Describe how we implement __builtin_eh_return. */
2688 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2689 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2691 /* Print operand X (an rtx) in assembler syntax to file FILE.
2692 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2693 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2695 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2697 /* Define which CODE values are valid. */
2699 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2702 /* Print a memory address as an operand to reference that memory location. */
2704 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2706 /* Define the codes that are matched by predicates in rs6000.c. */
2708 #define PREDICATE_CODES \
2709 {"short_cint_operand", {CONST_INT}}, \
2710 {"u_short_cint_operand", {CONST_INT}}, \
2711 {"non_short_cint_operand", {CONST_INT}}, \
2712 {"exact_log2_cint_operand", {CONST_INT}}, \
2713 {"gpc_reg_operand", {SUBREG, REG}}, \
2714 {"cc_reg_operand", {SUBREG, REG}}, \
2715 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2716 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2717 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2718 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2719 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2720 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2721 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2722 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2723 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2724 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2725 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2726 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2727 {"easy_fp_constant", {CONST_DOUBLE}}, \
2728 {"zero_fp_constant", {CONST_DOUBLE}}, \
2729 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2730 {"lwa_operand", {SUBREG, MEM, REG}}, \
2731 {"volatile_mem_operand", {MEM}}, \
2732 {"offsettable_mem_operand", {MEM}}, \
2733 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2734 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2735 {"non_add_cint_operand", {CONST_INT}}, \
2736 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2737 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2738 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2739 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2740 {"mask_operand", {CONST_INT}}, \
2741 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2742 {"count_register_operand", {REG}}, \
2743 {"xer_operand", {REG}}, \
2744 {"call_operand", {SYMBOL_REF, REG}}, \
2745 {"current_file_function_operand", {SYMBOL_REF}}, \
2746 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2747 CONST_DOUBLE, SYMBOL_REF}}, \
2748 {"load_multiple_operation", {PARALLEL}}, \
2749 {"store_multiple_operation", {PARALLEL}}, \
2750 {"vrsave_operation", {PARALLEL}}, \
2751 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2752 GT, LEU, LTU, GEU, GTU, \
2753 UNORDERED, ORDERED, \
2755 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2757 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2758 GT, LEU, LTU, GEU, GTU, \
2759 UNORDERED, ORDERED, \
2761 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2762 GT, LEU, LTU, GEU, GTU}}, \
2763 {"boolean_operator", {AND, IOR, XOR}}, \
2764 {"boolean_or_operator", {IOR, XOR}}, \
2765 {"altivec_register_operand", {REG}}, \
2766 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2768 /* uncomment for disabling the corresponding default options */
2769 /* #define MACHINE_no_sched_interblock */
2770 /* #define MACHINE_no_sched_speculative */
2771 /* #define MACHINE_no_sched_speculative_load */
2773 /* General flags. */
2774 extern int flag_pic;
2775 extern int optimize;
2776 extern int flag_expensive_optimizations;
2777 extern int frame_pointer_needed;
2779 enum rs6000_builtins
2781 /* AltiVec builtins. */
2782 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2783 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2784 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2785 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2786 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2787 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2788 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2789 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2790 ALTIVEC_BUILTIN_VADDUBM,
2791 ALTIVEC_BUILTIN_VADDUHM,
2792 ALTIVEC_BUILTIN_VADDUWM,
2793 ALTIVEC_BUILTIN_VADDFP,
2794 ALTIVEC_BUILTIN_VADDCUW,
2795 ALTIVEC_BUILTIN_VADDUBS,
2796 ALTIVEC_BUILTIN_VADDSBS,
2797 ALTIVEC_BUILTIN_VADDUHS,
2798 ALTIVEC_BUILTIN_VADDSHS,
2799 ALTIVEC_BUILTIN_VADDUWS,
2800 ALTIVEC_BUILTIN_VADDSWS,
2801 ALTIVEC_BUILTIN_VAND,
2802 ALTIVEC_BUILTIN_VANDC,
2803 ALTIVEC_BUILTIN_VAVGUB,
2804 ALTIVEC_BUILTIN_VAVGSB,
2805 ALTIVEC_BUILTIN_VAVGUH,
2806 ALTIVEC_BUILTIN_VAVGSH,
2807 ALTIVEC_BUILTIN_VAVGUW,
2808 ALTIVEC_BUILTIN_VAVGSW,
2809 ALTIVEC_BUILTIN_VCFUX,
2810 ALTIVEC_BUILTIN_VCFSX,
2811 ALTIVEC_BUILTIN_VCTSXS,
2812 ALTIVEC_BUILTIN_VCTUXS,
2813 ALTIVEC_BUILTIN_VCMPBFP,
2814 ALTIVEC_BUILTIN_VCMPEQUB,
2815 ALTIVEC_BUILTIN_VCMPEQUH,
2816 ALTIVEC_BUILTIN_VCMPEQUW,
2817 ALTIVEC_BUILTIN_VCMPEQFP,
2818 ALTIVEC_BUILTIN_VCMPGEFP,
2819 ALTIVEC_BUILTIN_VCMPGTUB,
2820 ALTIVEC_BUILTIN_VCMPGTSB,
2821 ALTIVEC_BUILTIN_VCMPGTUH,
2822 ALTIVEC_BUILTIN_VCMPGTSH,
2823 ALTIVEC_BUILTIN_VCMPGTUW,
2824 ALTIVEC_BUILTIN_VCMPGTSW,
2825 ALTIVEC_BUILTIN_VCMPGTFP,
2826 ALTIVEC_BUILTIN_VEXPTEFP,
2827 ALTIVEC_BUILTIN_VLOGEFP,
2828 ALTIVEC_BUILTIN_VMADDFP,
2829 ALTIVEC_BUILTIN_VMAXUB,
2830 ALTIVEC_BUILTIN_VMAXSB,
2831 ALTIVEC_BUILTIN_VMAXUH,
2832 ALTIVEC_BUILTIN_VMAXSH,
2833 ALTIVEC_BUILTIN_VMAXUW,
2834 ALTIVEC_BUILTIN_VMAXSW,
2835 ALTIVEC_BUILTIN_VMAXFP,
2836 ALTIVEC_BUILTIN_VMHADDSHS,
2837 ALTIVEC_BUILTIN_VMHRADDSHS,
2838 ALTIVEC_BUILTIN_VMLADDUHM,
2839 ALTIVEC_BUILTIN_VMRGHB,
2840 ALTIVEC_BUILTIN_VMRGHH,
2841 ALTIVEC_BUILTIN_VMRGHW,
2842 ALTIVEC_BUILTIN_VMRGLB,
2843 ALTIVEC_BUILTIN_VMRGLH,
2844 ALTIVEC_BUILTIN_VMRGLW,
2845 ALTIVEC_BUILTIN_VMSUMUBM,
2846 ALTIVEC_BUILTIN_VMSUMMBM,
2847 ALTIVEC_BUILTIN_VMSUMUHM,
2848 ALTIVEC_BUILTIN_VMSUMSHM,
2849 ALTIVEC_BUILTIN_VMSUMUHS,
2850 ALTIVEC_BUILTIN_VMSUMSHS,
2851 ALTIVEC_BUILTIN_VMINUB,
2852 ALTIVEC_BUILTIN_VMINSB,
2853 ALTIVEC_BUILTIN_VMINUH,
2854 ALTIVEC_BUILTIN_VMINSH,
2855 ALTIVEC_BUILTIN_VMINUW,
2856 ALTIVEC_BUILTIN_VMINSW,
2857 ALTIVEC_BUILTIN_VMINFP,
2858 ALTIVEC_BUILTIN_VMULEUB,
2859 ALTIVEC_BUILTIN_VMULESB,
2860 ALTIVEC_BUILTIN_VMULEUH,
2861 ALTIVEC_BUILTIN_VMULESH,
2862 ALTIVEC_BUILTIN_VMULOUB,
2863 ALTIVEC_BUILTIN_VMULOSB,
2864 ALTIVEC_BUILTIN_VMULOUH,
2865 ALTIVEC_BUILTIN_VMULOSH,
2866 ALTIVEC_BUILTIN_VNMSUBFP,
2867 ALTIVEC_BUILTIN_VNOR,
2868 ALTIVEC_BUILTIN_VOR,
2869 ALTIVEC_BUILTIN_VSEL_4SI,
2870 ALTIVEC_BUILTIN_VSEL_4SF,
2871 ALTIVEC_BUILTIN_VSEL_8HI,
2872 ALTIVEC_BUILTIN_VSEL_16QI,
2873 ALTIVEC_BUILTIN_VPERM_4SI,
2874 ALTIVEC_BUILTIN_VPERM_4SF,
2875 ALTIVEC_BUILTIN_VPERM_8HI,
2876 ALTIVEC_BUILTIN_VPERM_16QI,
2877 ALTIVEC_BUILTIN_VPKUHUM,
2878 ALTIVEC_BUILTIN_VPKUWUM,
2879 ALTIVEC_BUILTIN_VPKPX,
2880 ALTIVEC_BUILTIN_VPKUHSS,
2881 ALTIVEC_BUILTIN_VPKSHSS,
2882 ALTIVEC_BUILTIN_VPKUWSS,
2883 ALTIVEC_BUILTIN_VPKSWSS,
2884 ALTIVEC_BUILTIN_VPKUHUS,
2885 ALTIVEC_BUILTIN_VPKSHUS,
2886 ALTIVEC_BUILTIN_VPKUWUS,
2887 ALTIVEC_BUILTIN_VPKSWUS,
2888 ALTIVEC_BUILTIN_VREFP,
2889 ALTIVEC_BUILTIN_VRFIM,
2890 ALTIVEC_BUILTIN_VRFIN,
2891 ALTIVEC_BUILTIN_VRFIP,
2892 ALTIVEC_BUILTIN_VRFIZ,
2893 ALTIVEC_BUILTIN_VRLB,
2894 ALTIVEC_BUILTIN_VRLH,
2895 ALTIVEC_BUILTIN_VRLW,
2896 ALTIVEC_BUILTIN_VRSQRTEFP,
2897 ALTIVEC_BUILTIN_VSLB,
2898 ALTIVEC_BUILTIN_VSLH,
2899 ALTIVEC_BUILTIN_VSLW,
2900 ALTIVEC_BUILTIN_VSL,
2901 ALTIVEC_BUILTIN_VSLO,
2902 ALTIVEC_BUILTIN_VSPLTB,
2903 ALTIVEC_BUILTIN_VSPLTH,
2904 ALTIVEC_BUILTIN_VSPLTW,
2905 ALTIVEC_BUILTIN_VSPLTISB,
2906 ALTIVEC_BUILTIN_VSPLTISH,
2907 ALTIVEC_BUILTIN_VSPLTISW,
2908 ALTIVEC_BUILTIN_VSRB,
2909 ALTIVEC_BUILTIN_VSRH,
2910 ALTIVEC_BUILTIN_VSRW,
2911 ALTIVEC_BUILTIN_VSRAB,
2912 ALTIVEC_BUILTIN_VSRAH,
2913 ALTIVEC_BUILTIN_VSRAW,
2914 ALTIVEC_BUILTIN_VSR,
2915 ALTIVEC_BUILTIN_VSRO,
2916 ALTIVEC_BUILTIN_VSUBUBM,
2917 ALTIVEC_BUILTIN_VSUBUHM,
2918 ALTIVEC_BUILTIN_VSUBUWM,
2919 ALTIVEC_BUILTIN_VSUBFP,
2920 ALTIVEC_BUILTIN_VSUBCUW,
2921 ALTIVEC_BUILTIN_VSUBUBS,
2922 ALTIVEC_BUILTIN_VSUBSBS,
2923 ALTIVEC_BUILTIN_VSUBUHS,
2924 ALTIVEC_BUILTIN_VSUBSHS,
2925 ALTIVEC_BUILTIN_VSUBUWS,
2926 ALTIVEC_BUILTIN_VSUBSWS,
2927 ALTIVEC_BUILTIN_VSUM4UBS,
2928 ALTIVEC_BUILTIN_VSUM4SBS,
2929 ALTIVEC_BUILTIN_VSUM4SHS,
2930 ALTIVEC_BUILTIN_VSUM2SWS,
2931 ALTIVEC_BUILTIN_VSUMSWS,
2932 ALTIVEC_BUILTIN_VXOR,
2933 ALTIVEC_BUILTIN_VSLDOI_16QI,
2934 ALTIVEC_BUILTIN_VSLDOI_8HI,
2935 ALTIVEC_BUILTIN_VSLDOI_4SI,
2936 ALTIVEC_BUILTIN_VSLDOI_4SF,
2937 ALTIVEC_BUILTIN_VUPKHSB,
2938 ALTIVEC_BUILTIN_VUPKHPX,
2939 ALTIVEC_BUILTIN_VUPKHSH,
2940 ALTIVEC_BUILTIN_VUPKLSB,
2941 ALTIVEC_BUILTIN_VUPKLPX,
2942 ALTIVEC_BUILTIN_VUPKLSH,
2943 ALTIVEC_BUILTIN_MTVSCR,
2944 ALTIVEC_BUILTIN_MFVSCR,
2945 ALTIVEC_BUILTIN_DSSALL,
2946 ALTIVEC_BUILTIN_DSS,
2947 ALTIVEC_BUILTIN_LVSL,
2948 ALTIVEC_BUILTIN_LVSR,
2949 ALTIVEC_BUILTIN_DSTT,
2950 ALTIVEC_BUILTIN_DSTST,
2951 ALTIVEC_BUILTIN_DSTSTT,
2952 ALTIVEC_BUILTIN_DST,
2953 ALTIVEC_BUILTIN_LVEBX,
2954 ALTIVEC_BUILTIN_LVEHX,
2955 ALTIVEC_BUILTIN_LVEWX,
2956 ALTIVEC_BUILTIN_LVXL,
2957 ALTIVEC_BUILTIN_LVX,
2958 ALTIVEC_BUILTIN_STVX,
2959 ALTIVEC_BUILTIN_STVEBX,
2960 ALTIVEC_BUILTIN_STVEHX,
2961 ALTIVEC_BUILTIN_STVEWX,
2962 ALTIVEC_BUILTIN_STVXL,
2963 ALTIVEC_BUILTIN_VCMPBFP_P,
2964 ALTIVEC_BUILTIN_VCMPEQFP_P,
2965 ALTIVEC_BUILTIN_VCMPEQUB_P,
2966 ALTIVEC_BUILTIN_VCMPEQUH_P,
2967 ALTIVEC_BUILTIN_VCMPEQUW_P,
2968 ALTIVEC_BUILTIN_VCMPGEFP_P,
2969 ALTIVEC_BUILTIN_VCMPGTFP_P,
2970 ALTIVEC_BUILTIN_VCMPGTSB_P,
2971 ALTIVEC_BUILTIN_VCMPGTSH_P,
2972 ALTIVEC_BUILTIN_VCMPGTSW_P,
2973 ALTIVEC_BUILTIN_VCMPGTUB_P,
2974 ALTIVEC_BUILTIN_VCMPGTUH_P,
2975 ALTIVEC_BUILTIN_VCMPGTUW_P,
2976 ALTIVEC_BUILTIN_ABSS_V4SI,
2977 ALTIVEC_BUILTIN_ABSS_V8HI,
2978 ALTIVEC_BUILTIN_ABSS_V16QI,
2979 ALTIVEC_BUILTIN_ABS_V4SI,
2980 ALTIVEC_BUILTIN_ABS_V4SF,
2981 ALTIVEC_BUILTIN_ABS_V8HI,
2982 ALTIVEC_BUILTIN_ABS_V16QI
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