1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 #ifndef TARGET_PAIRED_FLOAT
60 #define TARGET_PAIRED_FLOAT 0
63 #ifdef HAVE_AS_POPCNTB
64 #define ASM_CPU_POWER5_SPEC "-mpower5"
66 #define ASM_CPU_POWER5_SPEC "-mpower4"
70 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
72 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
76 #define ASM_CPU_POWER7_SPEC "-mpower7"
78 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
81 /* Common ASM definitions used by ASM_SPEC among the various targets
82 for handling -mcpu=xxx switches. */
83 #define ASM_CPU_SPEC \
85 %{mpower: %{!mpower2: -mpwr}} \
87 %{mpowerpc64*: -mppc64} \
88 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
89 %{mno-power: %{!mpowerpc*: -mcom}} \
90 %{!mno-power: %{!mpower*: %(asm_default)}}} \
91 %{mcpu=common: -mcom} \
92 %{mcpu=cell: -mcell} \
93 %{mcpu=power: -mpwr} \
94 %{mcpu=power2: -mpwrx} \
95 %{mcpu=power3: -mppc64} \
96 %{mcpu=power4: -mpower4} \
97 %{mcpu=power5: %(asm_cpu_power5)} \
98 %{mcpu=power5+: %(asm_cpu_power5)} \
99 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
100 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
101 %{mcpu=power7: %(asm_cpu_power7)} \
102 %{mcpu=powerpc: -mppc} \
103 %{mcpu=rios: -mpwr} \
104 %{mcpu=rios1: -mpwr} \
105 %{mcpu=rios2: -mpwrx} \
107 %{mcpu=rsc1: -mpwr} \
108 %{mcpu=rs64a: -mppc64} \
112 %{mcpu=405fp: -m405} \
114 %{mcpu=440fp: -m440} \
116 %{mcpu=464fp: -m440} \
121 %{mcpu=603e: -mppc} \
122 %{mcpu=ec603e: -mppc} \
124 %{mcpu=604e: -mppc} \
125 %{mcpu=620: -mppc64} \
126 %{mcpu=630: -mppc64} \
130 %{mcpu=7400: -mppc -maltivec} \
131 %{mcpu=7450: -mppc -maltivec} \
132 %{mcpu=G4: -mppc -maltivec} \
137 %{mcpu=970: -mpower4 -maltivec} \
138 %{mcpu=G5: -mpower4 -maltivec} \
139 %{mcpu=8540: -me500} \
140 %{mcpu=8548: -me500} \
141 %{mcpu=e300c2: -me300} \
142 %{mcpu=e300c3: -me300} \
143 %{mcpu=e500mc: -me500mc} \
144 %{maltivec: -maltivec} \
147 #define CPP_DEFAULT_SPEC ""
149 #define ASM_DEFAULT_SPEC ""
151 /* This macro defines names of additional specifications to put in the specs
152 that can be used in various specifications like CC1_SPEC. Its definition
153 is an initializer with a subgrouping for each command option.
155 Each subgrouping contains a string constant, that defines the
156 specification name, and a string constant that used by the GCC driver
159 Do not define this macro if it does not need to do anything. */
161 #define SUBTARGET_EXTRA_SPECS
163 #define EXTRA_SPECS \
164 { "cpp_default", CPP_DEFAULT_SPEC }, \
165 { "asm_cpu", ASM_CPU_SPEC }, \
166 { "asm_default", ASM_DEFAULT_SPEC }, \
167 { "cc1_cpu", CC1_CPU_SPEC }, \
168 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
169 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
170 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
171 SUBTARGET_EXTRA_SPECS
173 /* -mcpu=native handling only makes sense with compiler running on
174 an PowerPC chip. If changing this condition, also change
175 the condition in driver-rs6000.c. */
176 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
177 /* In driver-rs6000.c. */
178 extern const char *host_detect_local_cpu (int argc, const char **argv);
179 #define EXTRA_SPEC_FUNCTIONS \
180 { "local_cpu_detect", host_detect_local_cpu },
181 #define HAVE_LOCAL_CPU_DETECT
185 #ifdef HAVE_LOCAL_CPU_DETECT
186 #define CC1_CPU_SPEC \
187 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
188 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
190 #define CC1_CPU_SPEC ""
194 /* Architecture type. */
196 /* Define TARGET_MFCRF if the target assembler does not support the
197 optional field operand for mfcr. */
199 #ifndef HAVE_AS_MFCRF
201 #define TARGET_MFCRF 0
204 /* Define TARGET_POPCNTB if the target assembler does not support the
205 popcount byte instruction. */
207 #ifndef HAVE_AS_POPCNTB
208 #undef TARGET_POPCNTB
209 #define TARGET_POPCNTB 0
212 /* Define TARGET_FPRND if the target assembler does not support the
213 fp rounding instructions. */
215 #ifndef HAVE_AS_FPRND
217 #define TARGET_FPRND 0
220 /* Define TARGET_CMPB if the target assembler does not support the
225 #define TARGET_CMPB 0
228 /* Define TARGET_MFPGPR if the target assembler does not support the
229 mffpr and mftgpr instructions. */
231 #ifndef HAVE_AS_MFPGPR
233 #define TARGET_MFPGPR 0
236 /* Define TARGET_DFP if the target assembler does not support decimal
237 floating point instructions. */
243 #ifndef TARGET_SECURE_PLT
244 #define TARGET_SECURE_PLT 0
247 #define TARGET_32BIT (! TARGET_64BIT)
250 #define HAVE_AS_TLS 0
253 /* Return 1 for a symbol ref for a thread-local storage symbol. */
254 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
255 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
258 /* For libgcc2 we make sure this is a compile time constant */
259 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
260 #undef TARGET_POWERPC64
261 #define TARGET_POWERPC64 1
263 #undef TARGET_POWERPC64
264 #define TARGET_POWERPC64 0
267 /* The option machinery will define this. */
270 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
272 /* Processor type. Order must match cpu attribute in MD file. */
301 /* FPU operations supported.
302 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
303 also test TARGET_HARD_FLOAT. */
304 #define TARGET_SINGLE_FLOAT 1
305 #define TARGET_DOUBLE_FLOAT 1
306 #define TARGET_SINGLE_FPU 0
307 #define TARGET_SIMPLE_FPU 0
308 #define TARGET_XILINX_FPU 0
310 extern enum processor_type rs6000_cpu;
312 /* Recast the processor type to the cpu attribute. */
313 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
315 /* Define generic processor types based upon current deployment. */
316 #define PROCESSOR_COMMON PROCESSOR_PPC601
317 #define PROCESSOR_POWER PROCESSOR_RIOS1
318 #define PROCESSOR_POWERPC PROCESSOR_PPC604
319 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
321 /* Define the default processor. This is overridden by other tm.h files. */
322 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
323 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
325 /* FP processor type. */
328 FPU_NONE, /* No FPU */
329 FPU_SF_LITE, /* Limited Single Precision FPU */
330 FPU_DF_LITE, /* Limited Double Precision FPU */
331 FPU_SF_FULL, /* Full Single Precision FPU */
332 FPU_DF_FULL /* Full Double Single Precision FPU */
335 extern enum fpu_type_t fpu_type;
337 /* Specify the dialect of assembler to use. New mnemonics is dialect one
338 and the old mnemonics are dialect zero. */
339 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
341 /* Types of costly dependences. */
342 enum rs6000_dependence_cost
344 max_dep_latency = 1000,
347 true_store_to_load_dep_costly,
348 store_to_load_dep_costly
351 /* Types of nop insertion schemes in sched target hook sched_finish. */
352 enum rs6000_nop_insertion
354 sched_finish_regroup_exact = 1000,
355 sched_finish_pad_groups,
359 /* Dispatch group termination caused by an insn. */
360 enum group_termination
366 /* Support for a compile-time default CPU, et cetera. The rules are:
367 --with-cpu is ignored if -mcpu is specified.
368 --with-tune is ignored if -mtune is specified.
369 --with-float is ignored if -mhard-float or -msoft-float are
371 #define OPTION_DEFAULT_SPECS \
372 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
373 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
374 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
376 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
377 struct rs6000_cpu_select
385 extern struct rs6000_cpu_select rs6000_select[];
388 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
389 extern int rs6000_debug_stack; /* debug stack applications */
390 extern int rs6000_debug_arg; /* debug argument handling */
392 #define TARGET_DEBUG_STACK rs6000_debug_stack
393 #define TARGET_DEBUG_ARG rs6000_debug_arg
395 extern const char *rs6000_traceback_name; /* Type of traceback table. */
397 /* These are separate from target_flags because we've run out of bits
399 extern int rs6000_long_double_type_size;
400 extern int rs6000_ieeequad;
401 extern int rs6000_altivec_abi;
402 extern int rs6000_spe_abi;
403 extern int rs6000_spe;
404 extern int rs6000_isel;
405 extern int rs6000_float_gprs;
406 extern int rs6000_alignment_flags;
407 extern const char *rs6000_sched_insert_nops_str;
408 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
409 extern int rs6000_xilinx_fpu;
411 /* Alignment options for fields in structures for sub-targets following
413 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
414 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
416 Override the macro definitions when compiling libobjc to avoid undefined
417 reference to rs6000_alignment_flags due to library's use of GCC alignment
418 macros which use the macros below. */
420 #ifndef IN_TARGET_LIBS
421 #define MASK_ALIGN_POWER 0x00000000
422 #define MASK_ALIGN_NATURAL 0x00000001
423 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
425 #define TARGET_ALIGN_NATURAL 0
428 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
429 #define TARGET_IEEEQUAD rs6000_ieeequad
430 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
432 #define TARGET_SPE_ABI 0
434 #define TARGET_E500 0
435 #define TARGET_ISEL rs6000_isel
436 #define TARGET_FPRS 1
437 #define TARGET_E500_SINGLE 0
438 #define TARGET_E500_DOUBLE 0
439 #define CHECK_E500_OPTIONS do { } while (0)
441 /* E500 processors only support plain "sync", not lwsync. */
442 #define TARGET_NO_LWSYNC TARGET_E500
444 /* Sometimes certain combinations of command options do not make sense
445 on a particular target machine. You can define a macro
446 `OVERRIDE_OPTIONS' to take account of this. This macro, if
447 defined, is executed once just after all the command options have
450 Do not use this macro to turn on various extra optimizations for
451 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
453 On the RS/6000 this is used to define the target cpu type. */
455 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
457 /* Define this to change the optimizations performed by default. */
458 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
460 /* Show we can debug even without a frame pointer. */
461 #define CAN_DEBUG_WITHOUT_FP
464 #define REGISTER_TARGET_PRAGMAS() do { \
465 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
466 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
469 /* Target #defines. */
470 #define TARGET_CPU_CPP_BUILTINS() \
471 rs6000_cpu_cpp_builtins (pfile)
473 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
474 we're compiling for. Some configurations may need to override it. */
475 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
478 if (BYTES_BIG_ENDIAN) \
480 builtin_define ("__BIG_ENDIAN__"); \
481 builtin_define ("_BIG_ENDIAN"); \
482 builtin_assert ("machine=bigendian"); \
486 builtin_define ("__LITTLE_ENDIAN__"); \
487 builtin_define ("_LITTLE_ENDIAN"); \
488 builtin_assert ("machine=littleendian"); \
493 /* Target machine storage layout. */
495 /* Define this macro if it is advisable to hold scalars in registers
496 in a wider mode than that declared by the program. In such cases,
497 the value is constrained to be within the bounds of the declared
498 type, but kept valid in the wider mode. The signedness of the
499 extension may differ from that of the type. */
501 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
502 if (GET_MODE_CLASS (MODE) == MODE_INT \
503 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
504 (MODE) = TARGET_32BIT ? SImode : DImode;
506 /* Define this if most significant bit is lowest numbered
507 in instructions that operate on numbered bit-fields. */
508 /* That is true on RS/6000. */
509 #define BITS_BIG_ENDIAN 1
511 /* Define this if most significant byte of a word is the lowest numbered. */
512 /* That is true on RS/6000. */
513 #define BYTES_BIG_ENDIAN 1
515 /* Define this if most significant word of a multiword number is lowest
518 For RS/6000 we can decide arbitrarily since there are no machine
519 instructions for them. Might as well be consistent with bits and bytes. */
520 #define WORDS_BIG_ENDIAN 1
522 #define MAX_BITS_PER_WORD 64
524 /* Width of a word, in units (bytes). */
525 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
527 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
529 #define MIN_UNITS_PER_WORD 4
531 #define UNITS_PER_FP_WORD 8
532 #define UNITS_PER_ALTIVEC_WORD 16
533 #define UNITS_PER_SPE_WORD 8
534 #define UNITS_PER_PAIRED_WORD 8
536 /* Type used for ptrdiff_t, as a string used in a declaration. */
537 #define PTRDIFF_TYPE "int"
539 /* Type used for size_t, as a string used in a declaration. */
540 #define SIZE_TYPE "long unsigned int"
542 /* Type used for wchar_t, as a string used in a declaration. */
543 #define WCHAR_TYPE "short unsigned int"
545 /* Width of wchar_t in bits. */
546 #define WCHAR_TYPE_SIZE 16
548 /* A C expression for the size in bits of the type `short' on the
549 target machine. If you don't define this, the default is half a
550 word. (If this would be less than one storage unit, it is
551 rounded up to one unit.) */
552 #define SHORT_TYPE_SIZE 16
554 /* A C expression for the size in bits of the type `int' on the
555 target machine. If you don't define this, the default is one
557 #define INT_TYPE_SIZE 32
559 /* A C expression for the size in bits of the type `long' on the
560 target machine. If you don't define this, the default is one
562 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
564 /* A C expression for the size in bits of the type `long long' on the
565 target machine. If you don't define this, the default is two
567 #define LONG_LONG_TYPE_SIZE 64
569 /* A C expression for the size in bits of the type `float' on the
570 target machine. If you don't define this, the default is one
572 #define FLOAT_TYPE_SIZE 32
574 /* A C expression for the size in bits of the type `double' on the
575 target machine. If you don't define this, the default is two
577 #define DOUBLE_TYPE_SIZE 64
579 /* A C expression for the size in bits of the type `long double' on
580 the target machine. If you don't define this, the default is two
582 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
584 /* Define this to set long double type size to use in libgcc2.c, which can
585 not depend on target_flags. */
586 #ifdef __LONG_DOUBLE_128__
587 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
589 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
592 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
593 #define WIDEST_HARDWARE_FP_SIZE 64
595 /* Width in bits of a pointer.
596 See also the macro `Pmode' defined below. */
597 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
599 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
600 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
602 /* Boundary (in *bits*) on which stack pointer should be aligned. */
603 #define STACK_BOUNDARY \
604 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
606 /* Allocation boundary (in *bits*) for the code of a function. */
607 #define FUNCTION_BOUNDARY 32
609 /* No data type wants to be aligned rounder than this. */
610 #define BIGGEST_ALIGNMENT 128
612 /* A C expression to compute the alignment for a variables in the
613 local store. TYPE is the data type, and ALIGN is the alignment
614 that the object would ordinarily have. */
615 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
616 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
617 (TARGET_E500_DOUBLE \
618 && TYPE_MODE (TYPE) == DFmode) ? 64 : \
619 ((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
620 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
621 && TREE_CODE (TYPE) == VECTOR_TYPE \
622 && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) ? 64 : ALIGN)
624 /* Alignment of field after `int : 0' in a structure. */
625 #define EMPTY_FIELD_BOUNDARY 32
627 /* Every structure's size must be a multiple of this. */
628 #define STRUCTURE_SIZE_BOUNDARY 8
630 /* Return 1 if a structure or array containing FIELD should be
631 accessed using `BLKMODE'.
633 For the SPE, simd types are V2SI, and gcc can be tempted to put the
634 entire thing in a DI and use subregs to access the internals.
635 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
636 back-end. Because a single GPR can hold a V2SI, but not a DI, the
637 best thing to do is set structs to BLKmode and avoid Severe Tire
640 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
641 fit into 1, whereas DI still needs two. */
642 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
643 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
644 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
646 /* A bit-field declared as `int' forces `int' alignment for the struct. */
647 #define PCC_BITFIELD_TYPE_MATTERS 1
649 /* Make strings word-aligned so strcpy from constants will be faster.
650 Make vector constants quadword aligned. */
651 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
652 (TREE_CODE (EXP) == STRING_CST \
653 && (STRICT_ALIGNMENT || !optimize_size) \
654 && (ALIGN) < BITS_PER_WORD \
658 /* Make arrays of chars word-aligned for the same reasons.
659 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
661 #define DATA_ALIGNMENT(TYPE, ALIGN) \
662 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
663 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
664 : (TARGET_E500_DOUBLE \
665 && TYPE_MODE (TYPE) == DFmode) ? 64 \
666 : TREE_CODE (TYPE) == ARRAY_TYPE \
667 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
668 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
670 /* Nonzero if move instructions will actually fail to work
671 when given unaligned data. */
672 #define STRICT_ALIGNMENT 0
674 /* Define this macro to be the value 1 if unaligned accesses have a cost
675 many times greater than aligned accesses, for example if they are
676 emulated in a trap handler. */
677 /* Altivec vector memory instructions simply ignore the low bits; SPE
678 vector memory instructions trap on unaligned accesses. */
679 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
681 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
682 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
683 || (MODE) == DImode) \
685 || (VECTOR_MODE_P ((MODE)) && (ALIGN) < GET_MODE_BITSIZE ((MODE))))
687 /* Standard register usage. */
689 /* Number of actual hardware registers.
690 The hardware registers are assigned numbers for the compiler
691 from 0 to just below FIRST_PSEUDO_REGISTER.
692 All registers that the compiler knows about must be given numbers,
693 even those that are not normally considered general registers.
695 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
696 an MQ register, a count register, a link register, and 8 condition
697 register fields, which we view here as separate registers. AltiVec
698 adds 32 vector registers and a VRsave register.
700 In addition, the difference between the frame and argument pointers is
701 a function of the number of registers saved, so we need to have a
702 register for AP that will later be eliminated in favor of SP or FP.
703 This is a normal register, but it is fixed.
705 We also create a pseudo register for float/int conversions, that will
706 really represent the memory location used. It is represented here as
707 a register, in order to work around problems in allocating stack storage
710 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
711 pointer, which is eventually eliminated in favor of SP or FP. */
713 #define FIRST_PSEUDO_REGISTER 114
715 /* This must be included for pre gcc 3.0 glibc compatibility. */
716 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
718 /* Add 32 dwarf columns for synthetic SPE registers. */
719 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
721 /* The SPE has an additional 32 synthetic registers, with DWARF debug
722 info numbering for these registers starting at 1200. While eh_frame
723 register numbering need not be the same as the debug info numbering,
724 we choose to number these regs for eh_frame at 1200 too. This allows
725 future versions of the rs6000 backend to add hard registers and
726 continue to use the gcc hard register numbering for eh_frame. If the
727 extra SPE registers in eh_frame were numbered starting from the
728 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
729 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
730 avoid invalidating older SPE eh_frame info.
732 We must map them here to avoid huge unwinder tables mostly consisting
734 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
735 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
737 /* Use standard DWARF numbering for DWARF debugging information. */
738 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
740 /* Use gcc hard register numbering for eh_frame. */
741 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
743 /* Map register numbers held in the call frame info that gcc has
744 collected using DWARF_FRAME_REGNUM to those that should be output in
745 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
746 for .eh_frame, but use the numbers mandated by the various ABIs for
747 .debug_frame. rs6000_emit_prologue has translated any combination of
748 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
749 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
750 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
751 ((FOR_EH) ? (REGNO) \
752 : (REGNO) == CR2_REGNO ? 64 \
753 : DBX_REGISTER_NUMBER (REGNO))
755 /* 1 for registers that have pervasive standard uses
756 and are not available for the register allocator.
758 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
759 as a local register; for all other OS's r2 is the TOC pointer.
761 cr5 is not supposed to be used.
763 On System V implementations, r13 is fixed and not available for use. */
765 #define FIXED_REGISTERS \
766 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
770 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
771 /* AltiVec registers. */ \
772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
778 /* 1 for registers not available across function calls.
779 These must include the FIXED_REGISTERS and also any
780 registers that can be used without being saved.
781 The latter must include the registers where values are returned
782 and the register where structure-value addresses are passed.
783 Aside from that, you can include as many other registers as you like. */
785 #define CALL_USED_REGISTERS \
786 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
787 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
788 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
789 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
790 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
791 /* AltiVec registers. */ \
792 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
798 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
799 the entire set of `FIXED_REGISTERS' be included.
800 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
801 This macro is optional. If not specified, it defaults to the value
802 of `CALL_USED_REGISTERS'. */
804 #define CALL_REALLY_USED_REGISTERS \
805 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
807 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
809 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
810 /* AltiVec registers. */ \
811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
817 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
819 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
820 #define FIRST_SAVED_FP_REGNO (14+32)
821 #define FIRST_SAVED_GP_REGNO 13
823 /* List the order in which to allocate registers. Each register must be
824 listed once, even those in FIXED_REGISTERS.
826 We allocate in the following order:
827 fp0 (not saved or used for anything)
828 fp13 - fp2 (not saved; incoming fp arg registers)
829 fp1 (not saved; return value)
830 fp31 - fp14 (saved; order given to save least number)
831 cr7, cr6 (not saved or special)
832 cr1 (not saved, but used for FP operations)
833 cr0 (not saved, but used for arithmetic operations)
834 cr4, cr3, cr2 (saved)
835 r0 (not saved; cannot be base reg)
836 r9 (not saved; best for TImode)
837 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
838 r3 (not saved; return value register)
839 r31 - r13 (saved; order given to save least number)
840 r12 (not saved; if used for DImode or DFmode would use r13)
841 mq (not saved; best to use it if we can)
842 ctr (not saved; when we have the choice ctr is better)
844 cr5, r1, r2, ap, xer (fixed)
845 v0 - v1 (not saved or used for anything)
846 v13 - v3 (not saved; incoming vector arg registers)
847 v2 (not saved; incoming vector arg reg; return value)
848 v19 - v14 (not saved or used for anything)
849 v31 - v20 (saved; order given to save least number)
851 spe_acc, spefscr (fixed)
856 #define MAYBE_R2_AVAILABLE
857 #define MAYBE_R2_FIXED 2,
859 #define MAYBE_R2_AVAILABLE 2,
860 #define MAYBE_R2_FIXED
863 #define REG_ALLOC_ORDER \
865 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
867 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
868 50, 49, 48, 47, 46, \
869 75, 74, 69, 68, 72, 71, 70, \
870 0, MAYBE_R2_AVAILABLE \
871 9, 11, 10, 8, 7, 6, 5, 4, \
873 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
874 18, 17, 16, 15, 14, 13, 12, \
876 73, 1, MAYBE_R2_FIXED 67, 76, \
877 /* AltiVec registers. */ \
879 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
881 96, 95, 94, 93, 92, 91, \
882 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
887 /* True if register is floating-point. */
888 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
890 /* True if register is a condition register. */
891 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
893 /* True if register is a condition register, but not cr0. */
894 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
896 /* True if register is an integer register. */
897 #define INT_REGNO_P(N) \
898 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
900 /* SPE SIMD registers are just the GPRs. */
901 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
903 /* PAIRED SIMD registers are just the FPRs. */
904 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
906 /* True if register is the XER register. */
907 #define XER_REGNO_P(N) ((N) == XER_REGNO)
909 /* True if register is an AltiVec register. */
910 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
912 /* Return number of consecutive hard regs needed starting at reg REGNO
913 to hold something of mode MODE. */
915 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
917 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
918 ((TARGET_32BIT && TARGET_POWERPC64 \
919 && (GET_MODE_SIZE (MODE) > 4) \
920 && INT_REGNO_P (REGNO)) ? 1 : 0)
922 #define ALTIVEC_VECTOR_MODE(MODE) \
923 ((MODE) == V16QImode \
924 || (MODE) == V8HImode \
925 || (MODE) == V4SFmode \
926 || (MODE) == V4SImode)
928 #define SPE_VECTOR_MODE(MODE) \
929 ((MODE) == V4HImode \
930 || (MODE) == V2SFmode \
931 || (MODE) == V1DImode \
932 || (MODE) == V2SImode)
934 #define PAIRED_VECTOR_MODE(MODE) \
937 #define UNITS_PER_SIMD_WORD(MODE) \
938 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
939 : (TARGET_SPE ? UNITS_PER_SPE_WORD : (TARGET_PAIRED_FLOAT ? \
940 UNITS_PER_PAIRED_WORD : UNITS_PER_WORD)))
942 /* Value is TRUE if hard register REGNO can hold a value of
943 machine-mode MODE. */
944 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
945 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
947 /* Value is 1 if it is a good idea to tie two pseudo registers
948 when one has mode MODE1 and one has mode MODE2.
949 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
950 for any hard reg, then this must be 0 for correct output. */
951 #define MODES_TIEABLE_P(MODE1, MODE2) \
952 (SCALAR_FLOAT_MODE_P (MODE1) \
953 ? SCALAR_FLOAT_MODE_P (MODE2) \
954 : SCALAR_FLOAT_MODE_P (MODE2) \
955 ? SCALAR_FLOAT_MODE_P (MODE1) \
956 : GET_MODE_CLASS (MODE1) == MODE_CC \
957 ? GET_MODE_CLASS (MODE2) == MODE_CC \
958 : GET_MODE_CLASS (MODE2) == MODE_CC \
959 ? GET_MODE_CLASS (MODE1) == MODE_CC \
960 : SPE_VECTOR_MODE (MODE1) \
961 ? SPE_VECTOR_MODE (MODE2) \
962 : SPE_VECTOR_MODE (MODE2) \
963 ? SPE_VECTOR_MODE (MODE1) \
964 : ALTIVEC_VECTOR_MODE (MODE1) \
965 ? ALTIVEC_VECTOR_MODE (MODE2) \
966 : ALTIVEC_VECTOR_MODE (MODE2) \
967 ? ALTIVEC_VECTOR_MODE (MODE1) \
970 /* Post-reload, we can't use any new AltiVec registers, as we already
971 emitted the vrsave mask. */
973 #define HARD_REGNO_RENAME_OK(SRC, DST) \
974 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
976 /* A C expression returning the cost of moving data from a register of class
977 CLASS1 to one of CLASS2. */
979 #define REGISTER_MOVE_COST rs6000_register_move_cost
981 /* A C expressions returning the cost of moving data of MODE from a register to
984 #define MEMORY_MOVE_COST rs6000_memory_move_cost
986 /* Specify the cost of a branch insn; roughly the number of extra insns that
987 should be added to avoid a branch.
989 Set this to 3 on the RS/6000 since that is roughly the average cost of an
990 unscheduled conditional branch. */
992 #define BRANCH_COST(speed_p, predictable_p) 3
994 /* Override BRANCH_COST heuristic which empirically produces worse
995 performance for removing short circuiting from the logical ops. */
997 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
999 /* A fixed register used at epilogue generation to address SPE registers
1000 with negative offsets. The 64-bit load/store instructions on the SPE
1001 only take positive offsets (and small ones at that), so we need to
1002 reserve a register for consing up negative offsets. */
1004 #define FIXED_SCRATCH 0
1006 /* Define this macro to change register usage conditional on target
1009 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1011 /* Specify the registers used for certain standard purposes.
1012 The values of these macros are register numbers. */
1014 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1015 /* #define PC_REGNUM */
1017 /* Register to use for pushing function arguments. */
1018 #define STACK_POINTER_REGNUM 1
1020 /* Base register for access to local variables of the function. */
1021 #define HARD_FRAME_POINTER_REGNUM 31
1023 /* Base register for access to local variables of the function. */
1024 #define FRAME_POINTER_REGNUM 113
1026 /* Value should be nonzero if functions must have frame pointers.
1027 Zero means the frame pointer need not be set up (and parms
1028 may be accessed via the stack pointer) in functions that seem suitable.
1029 This is computed in `reload', in reload1.c. */
1030 #define FRAME_POINTER_REQUIRED 0
1032 /* Base register for access to arguments of the function. */
1033 #define ARG_POINTER_REGNUM 67
1035 /* Place to put static chain when calling a function that requires it. */
1036 #define STATIC_CHAIN_REGNUM 11
1039 /* Define the classes of registers for register constraints in the
1040 machine description. Also define ranges of constants.
1042 One of the classes must always be named ALL_REGS and include all hard regs.
1043 If there is more than one class, another class must be named NO_REGS
1044 and contain no registers.
1046 The name GENERAL_REGS must be the name of a class (or an alias for
1047 another name such as ALL_REGS). This is the class of registers
1048 that is allowed by "g" or "r" in a register constraint.
1049 Also, registers outside this class are allocated only when
1050 instructions express preferences for them.
1052 The classes must be numbered in nondecreasing order; that is,
1053 a larger-numbered class must never be contained completely
1054 in a smaller-numbered class.
1056 For any two classes, it is very desirable that there be another
1057 class that represents their union. */
1059 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1060 and condition registers, plus three special registers, MQ, CTR, and the
1061 link register. AltiVec adds a vector register class.
1063 However, r0 is special in that it cannot be used as a base register.
1064 So make a class for registers valid as base registers.
1066 Also, cr0 is the only condition code register that can be used in
1067 arithmetic insns, so make a separate class for it. */
1095 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1097 /* Give names of register classes as strings for dump file. */
1099 #define REG_CLASS_NAMES \
1110 "NON_SPECIAL_REGS", \
1114 "LINK_OR_CTR_REGS", \
1116 "SPEC_OR_GEN_REGS", \
1124 /* Define which registers fit in which classes.
1125 This is an initializer for a vector of HARD_REG_SET
1126 of length N_REG_CLASSES. */
1128 #define REG_CLASS_CONTENTS \
1130 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1131 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1132 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1133 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1134 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1135 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1136 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1137 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1138 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1139 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1140 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1141 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1142 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1143 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1144 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1145 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1146 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1147 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1148 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1149 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1150 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1153 /* The following macro defines cover classes for Integrated Register
1154 Allocator. Cover classes is a set of non-intersected register
1155 classes covering all hard registers used for register allocation
1156 purpose. Any move between two registers of a cover class should be
1157 cheaper than load or store of the registers. The macro value is
1158 array of register classes with LIM_REG_CLASSES used as the end
1161 #define IRA_COVER_CLASSES \
1163 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, \
1164 /*VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1165 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1166 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1169 /* The same information, inverted:
1170 Return the class number of the smallest class containing
1171 reg number REGNO. This could be a conditional expression
1172 or could index an array. */
1174 #define REGNO_REG_CLASS(REGNO) \
1175 ((REGNO) == 0 ? GENERAL_REGS \
1176 : (REGNO) < 32 ? BASE_REGS \
1177 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1178 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1179 : (REGNO) == CR0_REGNO ? CR0_REGS \
1180 : CR_REGNO_P (REGNO) ? CR_REGS \
1181 : (REGNO) == MQ_REGNO ? MQ_REGS \
1182 : (REGNO) == LR_REGNO ? LINK_REGS \
1183 : (REGNO) == CTR_REGNO ? CTR_REGS \
1184 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1185 : (REGNO) == XER_REGNO ? XER_REGS \
1186 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1187 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1188 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1189 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1190 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1193 /* The class value for index registers, and the one for base regs. */
1194 #define INDEX_REG_CLASS GENERAL_REGS
1195 #define BASE_REG_CLASS BASE_REGS
1197 /* Given an rtx X being reloaded into a reg required to be
1198 in class CLASS, return the class of reg to actually use.
1199 In general this is just CLASS; but on some machines
1200 in some cases it is preferable to use a more restrictive class.
1202 On the RS/6000, we have to return NO_REGS when we want to reload a
1203 floating-point CONST_DOUBLE to force it to be copied to memory.
1205 We also don't want to reload integer values into floating-point
1206 registers if we can at all help it. In fact, this can
1207 cause reload to die, if it tries to generate a reload of CTR
1208 into a FP register and discovers it doesn't have the memory location
1211 ??? Would it be a good idea to have reload do the converse, that is
1212 try to reload floating modes into FP registers if possible?
1215 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1217 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1219 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1220 && (CLASS) == NON_SPECIAL_REGS) \
1224 /* Return the register class of a scratch register needed to copy IN into
1225 or out of a register in CLASS in MODE. If it can be done directly,
1226 NO_REGS is returned. */
1228 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1229 rs6000_secondary_reload_class (CLASS, MODE, IN)
1231 /* If we are copying between FP or AltiVec registers and anything
1232 else, we need a memory location. The exception is when we are
1233 targeting ppc64 and the move to/from fpr to gpr instructions
1236 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1237 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1238 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1239 || ((MODE != DFmode) \
1240 && (MODE != DDmode) \
1241 && (MODE != DImode)))) \
1242 || ((CLASS2) == FLOAT_REGS \
1243 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1244 || ((MODE != DFmode) \
1245 && (MODE != DDmode) \
1246 && (MODE != DImode)))) \
1247 || (CLASS1) == ALTIVEC_REGS \
1248 || (CLASS2) == ALTIVEC_REGS))
1250 /* For cpus that cannot load/store SDmode values from the 64-bit
1251 FP registers without using a full 64-bit load/store, we need
1252 to allocate a full 64-bit stack slot for them. */
1254 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1255 rs6000_secondary_memory_needed_rtx (MODE)
1257 /* Return the maximum number of consecutive registers
1258 needed to represent mode MODE in a register of class CLASS.
1260 On RS/6000, this is the size of MODE in words,
1261 except in the FP regs, where a single reg is enough for two words. */
1262 #define CLASS_MAX_NREGS(CLASS, MODE) \
1263 (((CLASS) == FLOAT_REGS) \
1264 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1265 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS \
1266 && (MODE) == DFmode) \
1268 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1270 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1272 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1273 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1274 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1275 || TARGET_IEEEQUAD) \
1276 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1277 : (((TARGET_E500_DOUBLE \
1278 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
1279 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
1280 || (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
1281 || (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
1282 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1284 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1285 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
1287 /* Stack layout; function entry, exit and calling. */
1289 /* Enumeration to give which calling sequence to use. */
1292 ABI_AIX, /* IBM's AIX */
1293 ABI_V4, /* System V.4/eabi */
1294 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1297 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1299 /* Define this if pushing a word on the stack
1300 makes the stack pointer a smaller address. */
1301 #define STACK_GROWS_DOWNWARD
1303 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1304 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1306 /* Define this to nonzero if the nominal address of the stack frame
1307 is at the high-address end of the local variables;
1308 that is, each additional local variable allocated
1309 goes at a more negative offset in the frame.
1311 On the RS/6000, we grow upwards, from the area after the outgoing
1313 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1315 /* Size of the outgoing register save area */
1316 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1317 || DEFAULT_ABI == ABI_DARWIN) \
1318 ? (TARGET_64BIT ? 64 : 32) \
1321 /* Size of the fixed area on the stack */
1322 #define RS6000_SAVE_AREA \
1323 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1324 << (TARGET_64BIT ? 1 : 0))
1326 /* MEM representing address to save the TOC register */
1327 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1328 plus_constant (stack_pointer_rtx, \
1329 (TARGET_32BIT ? 20 : 40)))
1331 /* Align an address */
1332 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1334 /* Offset within stack frame to start allocating local variables at.
1335 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1336 first local allocated. Otherwise, it is the offset to the BEGINNING
1337 of the first local allocated.
1339 On the RS/6000, the frame pointer is the same as the stack pointer,
1340 except for dynamic allocations. So we start after the fixed area and
1341 outgoing parameter area. */
1343 #define STARTING_FRAME_OFFSET \
1344 (FRAME_GROWS_DOWNWARD \
1346 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1347 TARGET_ALTIVEC ? 16 : 8) \
1348 + RS6000_SAVE_AREA))
1350 /* Offset from the stack pointer register to an item dynamically
1351 allocated on the stack, e.g., by `alloca'.
1353 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1354 length of the outgoing arguments. The default is correct for most
1355 machines. See `function.c' for details. */
1356 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1357 (RS6000_ALIGN (crtl->outgoing_args_size, \
1358 TARGET_ALTIVEC ? 16 : 8) \
1359 + (STACK_POINTER_OFFSET))
1361 /* If we generate an insn to push BYTES bytes,
1362 this says how many the stack pointer really advances by.
1363 On RS/6000, don't define this because there are no push insns. */
1364 /* #define PUSH_ROUNDING(BYTES) */
1366 /* Offset of first parameter from the argument pointer register value.
1367 On the RS/6000, we define the argument pointer to the start of the fixed
1369 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1371 /* Offset from the argument pointer register value to the top of
1372 stack. This is different from FIRST_PARM_OFFSET because of the
1373 register save area. */
1374 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1376 /* Define this if stack space is still allocated for a parameter passed
1377 in a register. The value is the number of bytes allocated to this
1379 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1381 /* Define this if the above stack space is to be considered part of the
1382 space allocated by the caller. */
1383 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1385 /* This is the difference between the logical top of stack and the actual sp.
1387 For the RS/6000, sp points past the fixed area. */
1388 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1390 /* Define this if the maximum size of all the outgoing args is to be
1391 accumulated and pushed during the prologue. The amount can be
1392 found in the variable crtl->outgoing_args_size. */
1393 #define ACCUMULATE_OUTGOING_ARGS 1
1395 /* Value is the number of bytes of arguments automatically
1396 popped when returning from a subroutine call.
1397 FUNDECL is the declaration node of the function (as a tree),
1398 FUNTYPE is the data type of the function (as a tree),
1399 or for a library call it is an identifier node for the subroutine name.
1400 SIZE is the number of bytes of arguments passed on the stack. */
1402 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1404 /* Define how to find the value returned by a function.
1405 VALTYPE is the data type of the value (as a tree).
1406 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1407 otherwise, FUNC is 0. */
1409 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1411 /* Define how to find the value returned by a library function
1412 assuming the value has mode MODE. */
1414 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1416 /* DRAFT_V4_STRUCT_RET defaults off. */
1417 #define DRAFT_V4_STRUCT_RET 0
1419 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1420 #define DEFAULT_PCC_STRUCT_RETURN 0
1422 /* Mode of stack savearea.
1423 FUNCTION is VOIDmode because calling convention maintains SP.
1424 BLOCK needs Pmode for SP.
1425 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1426 #define STACK_SAVEAREA_MODE(LEVEL) \
1427 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1428 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1430 /* Minimum and maximum general purpose registers used to hold arguments. */
1431 #define GP_ARG_MIN_REG 3
1432 #define GP_ARG_MAX_REG 10
1433 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1435 /* Minimum and maximum floating point registers used to hold arguments. */
1436 #define FP_ARG_MIN_REG 33
1437 #define FP_ARG_AIX_MAX_REG 45
1438 #define FP_ARG_V4_MAX_REG 40
1439 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1440 || DEFAULT_ABI == ABI_DARWIN) \
1441 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1442 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1444 /* Minimum and maximum AltiVec registers used to hold arguments. */
1445 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1446 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1447 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1449 /* Return registers */
1450 #define GP_ARG_RETURN GP_ARG_MIN_REG
1451 #define FP_ARG_RETURN FP_ARG_MIN_REG
1452 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1454 /* Flags for the call/call_value rtl operations set up by function_arg */
1455 #define CALL_NORMAL 0x00000000 /* no special processing */
1456 /* Bits in 0x00000001 are unused. */
1457 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1458 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1459 #define CALL_LONG 0x00000008 /* always call indirect */
1460 #define CALL_LIBCALL 0x00000010 /* libcall */
1462 /* We don't have prologue and epilogue functions to save/restore
1463 everything for most ABIs. */
1464 #define WORLD_SAVE_P(INFO) 0
1466 /* 1 if N is a possible register number for a function value
1467 as seen by the caller.
1469 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1470 #define FUNCTION_VALUE_REGNO_P(N) \
1471 ((N) == GP_ARG_RETURN \
1472 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1473 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1475 /* 1 if N is a possible register number for function argument passing.
1476 On RS/6000, these are r3-r10 and fp1-fp13.
1477 On AltiVec, v2 - v13 are used for passing vectors. */
1478 #define FUNCTION_ARG_REGNO_P(N) \
1479 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1480 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1481 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1482 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1483 && TARGET_HARD_FLOAT && TARGET_FPRS))
1485 /* Define a data type for recording info about an argument list
1486 during the scan of that argument list. This data type should
1487 hold all necessary information about the function itself
1488 and about the args processed so far, enough to enable macros
1489 such as FUNCTION_ARG to determine where the next arg should go.
1491 On the RS/6000, this is a structure. The first element is the number of
1492 total argument words, the second is used to store the next
1493 floating-point register number, and the third says how many more args we
1494 have prototype types for.
1496 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1497 the next available GP register, `fregno' is the next available FP
1498 register, and `words' is the number of words used on the stack.
1500 The varargs/stdarg support requires that this structure's size
1501 be a multiple of sizeof(int). */
1503 typedef struct rs6000_args
1505 int words; /* # words used for passing GP registers */
1506 int fregno; /* next available FP register */
1507 int vregno; /* next available AltiVec register */
1508 int nargs_prototype; /* # args left in the current prototype */
1509 int prototype; /* Whether a prototype was defined */
1510 int stdarg; /* Whether function is a stdarg function. */
1511 int call_cookie; /* Do special things for this call */
1512 int sysv_gregno; /* next available GP register */
1513 int intoffset; /* running offset in struct (darwin64) */
1514 int use_stack; /* any part of struct on stack (darwin64) */
1515 int named; /* false for varargs params */
1518 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1519 for a call to a function whose data type is FNTYPE.
1520 For a library call, FNTYPE is 0. */
1522 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1523 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1525 /* Similar, but when scanning the definition of a procedure. We always
1526 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1528 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1529 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1531 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1533 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1534 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1536 /* Update the data in CUM to advance over an argument
1537 of mode MODE and data type TYPE.
1538 (TYPE is null for libcalls where that information may not be available.) */
1540 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1541 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1543 /* Determine where to put an argument to a function.
1544 Value is zero to push the argument on the stack,
1545 or a hard register in which to store the argument.
1547 MODE is the argument's machine mode.
1548 TYPE is the data type of the argument (as a tree).
1549 This is null for libcalls where that information may
1551 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1552 the preceding args and about the function being called.
1553 NAMED is nonzero if this argument is a named parameter
1554 (otherwise it is an extra parameter matching an ellipsis).
1556 On RS/6000 the first eight words of non-FP are normally in registers
1557 and the rest are pushed. The first 13 FP args are in registers.
1559 If this is floating-point and no prototype is specified, we use
1560 both an FP and integer register (or possibly FP reg and stack). Library
1561 functions (when TYPE is zero) always have the proper types for args,
1562 so we can pass the FP value just in one register. emit_library_function
1563 doesn't support EXPR_LIST anyway. */
1565 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1566 function_arg (&CUM, MODE, TYPE, NAMED)
1568 /* If defined, a C expression which determines whether, and in which
1569 direction, to pad out an argument with extra space. The value
1570 should be of type `enum direction': either `upward' to pad above
1571 the argument, `downward' to pad below, or `none' to inhibit
1574 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1576 /* If defined, a C expression that gives the alignment boundary, in bits,
1577 of an argument with the specified mode and type. If it is not defined,
1578 PARM_BOUNDARY is used for all arguments. */
1580 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1581 function_arg_boundary (MODE, TYPE)
1583 #define PAD_VARARGS_DOWN \
1584 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1586 /* Output assembler code to FILE to increment profiler label # LABELNO
1587 for profiling a function entry. */
1589 #define FUNCTION_PROFILER(FILE, LABELNO) \
1590 output_function_profiler ((FILE), (LABELNO));
1592 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1593 the stack pointer does not matter. No definition is equivalent to
1596 On the RS/6000, this is nonzero because we can restore the stack from
1597 its backpointer, which we maintain. */
1598 #define EXIT_IGNORE_STACK 1
1600 /* Define this macro as a C expression that is nonzero for registers
1601 that are used by the epilogue or the return' pattern. The stack
1602 and frame pointer registers are already be assumed to be used as
1605 #define EPILOGUE_USES(REGNO) \
1606 ((reload_completed && (REGNO) == LR_REGNO) \
1607 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1608 || (crtl->calls_eh_return \
1613 /* TRAMPOLINE_TEMPLATE deleted */
1615 /* Length in units of the trampoline for entering a nested function. */
1617 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1619 /* Emit RTL insns to initialize the variable parts of a trampoline.
1620 FNADDR is an RTX for the address of the function's pure code.
1621 CXT is an RTX for the static chain value for the function. */
1623 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1624 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1626 /* Definitions for __builtin_return_address and __builtin_frame_address.
1627 __builtin_return_address (0) should give link register (65), enable
1629 /* This should be uncommented, so that the link register is used, but
1630 currently this would result in unmatched insns and spilling fixed
1631 registers so we'll leave it for another day. When these problems are
1632 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1634 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1636 /* Number of bytes into the frame return addresses can be found. See
1637 rs6000_stack_info in rs6000.c for more information on how the different
1638 abi's store the return address. */
1639 #define RETURN_ADDRESS_OFFSET \
1640 ((DEFAULT_ABI == ABI_AIX \
1641 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1642 (DEFAULT_ABI == ABI_V4) ? 4 : \
1643 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1645 /* The current return address is in link register (65). The return address
1646 of anything farther back is accessed normally at an offset of 8 from the
1648 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1649 (rs6000_return_addr (COUNT, FRAME))
1652 /* Definitions for register eliminations.
1654 We have two registers that can be eliminated on the RS/6000. First, the
1655 frame pointer register can often be eliminated in favor of the stack
1656 pointer register. Secondly, the argument pointer register can always be
1657 eliminated; it is replaced with either the stack or frame pointer.
1659 In addition, we use the elimination mechanism to see if r30 is needed
1660 Initially we assume that it isn't. If it is, we spill it. This is done
1661 by making it an eliminable register. We replace it with itself so that
1662 if it isn't needed, then existing uses won't be modified. */
1664 /* This is an array of structures. Each structure initializes one pair
1665 of eliminable registers. The "from" register number is given first,
1666 followed by "to". Eliminations of the same "from" register are listed
1667 in order of preference. */
1668 #define ELIMINABLE_REGS \
1669 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1670 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1671 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1672 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1673 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1674 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1676 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1677 Frame pointer elimination is automatically handled.
1679 For the RS/6000, if frame pointer elimination is being done, we would like
1680 to convert ap into fp, not sp.
1682 We need r30 if -mminimal-toc was specified, and there are constant pool
1685 #define CAN_ELIMINATE(FROM, TO) \
1686 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1687 ? ! frame_pointer_needed \
1688 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1689 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1692 /* Define the offset between two registers, one to be eliminated, and the other
1693 its replacement, at the start of a routine. */
1694 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1695 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1697 /* Addressing modes, and classification of registers for them. */
1699 #define HAVE_PRE_DECREMENT 1
1700 #define HAVE_PRE_INCREMENT 1
1701 #define HAVE_PRE_MODIFY_DISP 1
1702 #define HAVE_PRE_MODIFY_REG 1
1704 /* Macros to check register numbers against specific register classes. */
1706 /* These assume that REGNO is a hard or pseudo reg number.
1707 They give nonzero only if REGNO is a hard reg of the suitable class
1708 or a pseudo reg currently allocated to a suitable hard reg.
1709 Since they use reg_renumber, they are safe only once reg_renumber
1710 has been allocated, which happens in local-alloc.c. */
1712 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1713 ((REGNO) < FIRST_PSEUDO_REGISTER \
1714 ? (REGNO) <= 31 || (REGNO) == 67 \
1715 || (REGNO) == FRAME_POINTER_REGNUM \
1716 : (reg_renumber[REGNO] >= 0 \
1717 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1718 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1720 #define REGNO_OK_FOR_BASE_P(REGNO) \
1721 ((REGNO) < FIRST_PSEUDO_REGISTER \
1722 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1723 || (REGNO) == FRAME_POINTER_REGNUM \
1724 : (reg_renumber[REGNO] > 0 \
1725 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1726 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1728 /* Maximum number of registers that can appear in a valid memory address. */
1730 #define MAX_REGS_PER_ADDRESS 2
1732 /* Recognize any constant value that is a valid address. */
1734 #define CONSTANT_ADDRESS_P(X) \
1735 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1736 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1737 || GET_CODE (X) == HIGH)
1739 /* Nonzero if the constant value X is a legitimate general operand.
1740 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1742 On the RS/6000, all integer constants are acceptable, most won't be valid
1743 for particular insns, though. Only easy FP constants are
1746 #define LEGITIMATE_CONSTANT_P(X) \
1747 (((GET_CODE (X) != CONST_DOUBLE \
1748 && GET_CODE (X) != CONST_VECTOR) \
1749 || GET_MODE (X) == VOIDmode \
1750 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1751 || easy_fp_constant (X, GET_MODE (X)) \
1752 || easy_vector_constant (X, GET_MODE (X))) \
1753 && !rs6000_tls_referenced_p (X))
1755 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1756 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1757 && EASY_VECTOR_15((n) >> 1) \
1760 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1761 and check its validity for a certain class.
1762 We have two alternate definitions for each of them.
1763 The usual definition accepts all pseudo regs; the other rejects
1764 them unless they have been allocated suitable hard regs.
1765 The symbol REG_OK_STRICT causes the latter definition to be used.
1767 Most source files want to accept pseudo regs in the hope that
1768 they will get allocated to the class that the insn wants them to be in.
1769 Source files for reload pass need to be strict.
1770 After reload, it makes no difference, since pseudo regs have
1771 been eliminated by then. */
1773 #ifdef REG_OK_STRICT
1774 # define REG_OK_STRICT_FLAG 1
1776 # define REG_OK_STRICT_FLAG 0
1779 /* Nonzero if X is a hard reg that can be used as an index
1780 or if it is a pseudo reg in the non-strict case. */
1781 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1782 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1783 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1785 /* Nonzero if X is a hard reg that can be used as a base reg
1786 or if it is a pseudo reg in the non-strict case. */
1787 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1788 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1789 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1791 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1792 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1794 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1795 that is a valid memory address for an instruction.
1796 The MODE argument is the machine mode for the MEM expression
1797 that wants to use this address.
1799 On the RS/6000, there are four valid addresses: a SYMBOL_REF that
1800 refers to a constant pool entry of an address (or the sum of it
1801 plus a constant), a short (16-bit signed) constant plus a register,
1802 the sum of two registers, or a register indirect, possibly with an
1803 auto-increment. For DFmode, DDmode and DImode with a constant plus
1804 register, we must ensure that both words are addressable or PowerPC64
1805 with offset word aligned.
1807 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
1808 32-bit DImode, TImode), indexed addressing cannot be used because
1809 adjacent memory cells are accessed by adding word-sized offsets
1810 during assembly output. */
1812 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1813 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1817 /* Try machine-dependent ways of modifying an illegitimate address
1818 to be legitimate. If we find one, return the new, valid address.
1819 This macro is used in only one place: `memory_address' in explow.c.
1821 OLDX is the address as it was before break_out_memory_refs was called.
1822 In some cases it is useful to look at this to decide what needs to be done.
1824 MODE and WIN are passed so that this macro can use
1825 GO_IF_LEGITIMATE_ADDRESS.
1827 It is always safe for this macro to do nothing. It exists to recognize
1828 opportunities to optimize the output.
1830 On RS/6000, first check for the sum of a register with a constant
1831 integer that is out of range. If so, generate code to add the
1832 constant with the low-order 16 bits masked to the register and force
1833 this result into another register (this can be done with `cau').
1834 Then generate an address of REG+(CONST&0xffff), allowing for the
1835 possibility of bit 16 being a one.
1837 Then check for the sum of a register and something not constant, try to
1838 load the other things into a register and return the sum. */
1840 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1841 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1842 if (result != NULL_RTX) \
1849 /* Try a machine-dependent way of reloading an illegitimate address
1850 operand. If we find one, push the reload and jump to WIN. This
1851 macro is used in only one place: `find_reloads_address' in reload.c.
1853 Implemented on rs6000 by rs6000_legitimize_reload_address.
1854 Note that (X) is evaluated twice; this is safe in current usage. */
1856 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1859 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1860 (int)(TYPE), (IND_LEVELS), &win); \
1865 /* Go to LABEL if ADDR (a legitimate address expression)
1866 has an effect that depends on the machine mode it is used for. */
1868 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1870 if (rs6000_mode_dependent_address (ADDR)) \
1874 #define FIND_BASE_TERM rs6000_find_base_term
1876 /* The register number of the register used to address a table of
1877 static data addresses in memory. In some cases this register is
1878 defined by a processor's "application binary interface" (ABI).
1879 When this macro is defined, RTL is generated for this register
1880 once, as with the stack pointer and frame pointer registers. If
1881 this macro is not defined, it is up to the machine-dependent files
1882 to allocate such a register (if necessary). */
1884 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1885 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1887 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1889 /* Define this macro if the register defined by
1890 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1891 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1893 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1895 /* A C expression that is nonzero if X is a legitimate immediate
1896 operand on the target machine when generating position independent
1897 code. You can assume that X satisfies `CONSTANT_P', so you need
1898 not check this. You can also assume FLAG_PIC is true, so you need
1899 not check it either. You need not define this macro if all
1900 constants (including `SYMBOL_REF') can be immediate operands when
1901 generating position independent code. */
1903 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1905 /* Define this if some processing needs to be done immediately before
1906 emitting code for an insn. */
1908 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1910 /* Specify the machine mode that this machine uses
1911 for the index in the tablejump instruction. */
1912 #define CASE_VECTOR_MODE SImode
1914 /* Define as C expression which evaluates to nonzero if the tablejump
1915 instruction expects the table to contain offsets from the address of the
1917 Do not define this if the table should contain absolute addresses. */
1918 #define CASE_VECTOR_PC_RELATIVE 1
1920 /* Define this as 1 if `char' should by default be signed; else as 0. */
1921 #define DEFAULT_SIGNED_CHAR 0
1923 /* This flag, if defined, says the same insns that convert to a signed fixnum
1924 also convert validly to an unsigned one. */
1926 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1928 /* An integer expression for the size in bits of the largest integer machine
1929 mode that should actually be used. */
1931 /* Allow pairs of registers to be used, which is the intent of the default. */
1932 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1934 /* Max number of bytes we can move from memory to memory
1935 in one reasonably fast instruction. */
1936 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1937 #define MAX_MOVE_MAX 8
1939 /* Nonzero if access to memory by bytes is no faster than for words.
1940 Also nonzero if doing byte operations (specifically shifts) in registers
1942 #define SLOW_BYTE_ACCESS 1
1944 /* Define if operations between registers always perform the operation
1945 on the full register even if a narrower mode is specified. */
1946 #define WORD_REGISTER_OPERATIONS
1948 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1949 will either zero-extend or sign-extend. The value of this macro should
1950 be the code that says which one of the two operations is implicitly
1951 done, UNKNOWN if none. */
1952 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1954 /* Define if loading short immediate values into registers sign extends. */
1955 #define SHORT_IMMEDIATES_SIGN_EXTEND
1957 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1958 is done just by pretending it is already truncated. */
1959 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1961 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1962 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1963 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1965 /* The CTZ patterns return -1 for input of zero. */
1966 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1968 /* Specify the machine mode that pointers have.
1969 After generation of rtl, the compiler makes no further distinction
1970 between pointers and any other objects of this machine mode. */
1971 #define Pmode (TARGET_32BIT ? SImode : DImode)
1973 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1974 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1976 /* Mode of a function address in a call instruction (for indexing purposes).
1977 Doesn't matter on RS/6000. */
1978 #define FUNCTION_MODE SImode
1980 /* Define this if addresses of constant functions
1981 shouldn't be put through pseudo regs where they can be cse'd.
1982 Desirable on machines where ordinary constants are expensive
1983 but a CALL with constant address is cheap. */
1984 #define NO_FUNCTION_CSE
1986 /* Define this to be nonzero if shift instructions ignore all but the low-order
1989 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1990 have been dropped from the PowerPC architecture. */
1992 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1994 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1995 should be adjusted to reflect any required changes. This macro is used when
1996 there is some systematic length adjustment required that would be difficult
1997 to express in the length attribute. */
1999 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2001 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2002 COMPARE, return the mode to be used for the comparison. For
2003 floating-point, CCFPmode should be used. CCUNSmode should be used
2004 for unsigned comparisons. CCEQmode should be used when we are
2005 doing an inequality comparison on the result of a
2006 comparison. CCmode should be used in all other cases. */
2008 #define SELECT_CC_MODE(OP,X,Y) \
2009 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2010 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2011 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2012 ? CCEQmode : CCmode))
2014 /* Can the condition code MODE be safely reversed? This is safe in
2015 all cases on this port, because at present it doesn't use the
2016 trapping FP comparisons (fcmpo). */
2017 #define REVERSIBLE_CC_MODE(MODE) 1
2019 /* Given a condition code and a mode, return the inverse condition. */
2020 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2022 /* Define the information needed to generate branch and scc insns. This is
2023 stored from the compare operation. */
2025 extern GTY(()) rtx rs6000_compare_op0;
2026 extern GTY(()) rtx rs6000_compare_op1;
2027 extern int rs6000_compare_fp_p;
2029 /* Control the assembler format that we output. */
2031 /* A C string constant describing how to begin a comment in the target
2032 assembler language. The compiler assumes that the comment will end at
2033 the end of the line. */
2034 #define ASM_COMMENT_START " #"
2036 /* Flag to say the TOC is initialized */
2037 extern int toc_initialized;
2039 /* Macro to output a special constant pool entry. Go to WIN if we output
2040 it. Otherwise, it is written the usual way.
2042 On the RS/6000, toc entries are handled this way. */
2044 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2045 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2047 output_toc (FILE, X, LABELNO, MODE); \
2052 #ifdef HAVE_GAS_WEAK
2053 #define RS6000_WEAK 1
2055 #define RS6000_WEAK 0
2059 /* Used in lieu of ASM_WEAKEN_LABEL. */
2060 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2063 fputs ("\t.weak\t", (FILE)); \
2064 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2065 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2066 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2069 fputs ("[DS]", (FILE)); \
2070 fputs ("\n\t.weak\t.", (FILE)); \
2071 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2073 fputc ('\n', (FILE)); \
2076 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2077 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2078 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2080 fputs ("\t.set\t.", (FILE)); \
2081 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2082 fputs (",.", (FILE)); \
2083 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2084 fputc ('\n', (FILE)); \
2091 #if HAVE_GAS_WEAKREF
2092 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2095 fputs ("\t.weakref\t", (FILE)); \
2096 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2097 fputs (", ", (FILE)); \
2098 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2099 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2100 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2102 fputs ("\n\t.weakref\t.", (FILE)); \
2103 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2104 fputs (", .", (FILE)); \
2105 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2107 fputc ('\n', (FILE)); \
2111 /* This implements the `alias' attribute. */
2112 #undef ASM_OUTPUT_DEF_FROM_DECLS
2113 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2116 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2117 const char *name = IDENTIFIER_POINTER (TARGET); \
2118 if (TREE_CODE (DECL) == FUNCTION_DECL \
2119 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2121 if (TREE_PUBLIC (DECL)) \
2123 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2125 fputs ("\t.globl\t.", FILE); \
2126 RS6000_OUTPUT_BASENAME (FILE, alias); \
2127 putc ('\n', FILE); \
2130 else if (TARGET_XCOFF) \
2132 fputs ("\t.lglobl\t.", FILE); \
2133 RS6000_OUTPUT_BASENAME (FILE, alias); \
2134 putc ('\n', FILE); \
2136 fputs ("\t.set\t.", FILE); \
2137 RS6000_OUTPUT_BASENAME (FILE, alias); \
2138 fputs (",.", FILE); \
2139 RS6000_OUTPUT_BASENAME (FILE, name); \
2140 fputc ('\n', FILE); \
2142 ASM_OUTPUT_DEF (FILE, alias, name); \
2146 #define TARGET_ASM_FILE_START rs6000_file_start
2148 /* Output to assembler file text saying following lines
2149 may contain character constants, extra white space, comments, etc. */
2151 #define ASM_APP_ON ""
2153 /* Output to assembler file text saying following lines
2154 no longer contain unusual constructs. */
2156 #define ASM_APP_OFF ""
2158 /* How to refer to registers in assembler output.
2159 This sequence is indexed by compiler's hard-register-number (see above). */
2161 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2163 #define REGISTER_NAMES \
2165 &rs6000_reg_names[ 0][0], /* r0 */ \
2166 &rs6000_reg_names[ 1][0], /* r1 */ \
2167 &rs6000_reg_names[ 2][0], /* r2 */ \
2168 &rs6000_reg_names[ 3][0], /* r3 */ \
2169 &rs6000_reg_names[ 4][0], /* r4 */ \
2170 &rs6000_reg_names[ 5][0], /* r5 */ \
2171 &rs6000_reg_names[ 6][0], /* r6 */ \
2172 &rs6000_reg_names[ 7][0], /* r7 */ \
2173 &rs6000_reg_names[ 8][0], /* r8 */ \
2174 &rs6000_reg_names[ 9][0], /* r9 */ \
2175 &rs6000_reg_names[10][0], /* r10 */ \
2176 &rs6000_reg_names[11][0], /* r11 */ \
2177 &rs6000_reg_names[12][0], /* r12 */ \
2178 &rs6000_reg_names[13][0], /* r13 */ \
2179 &rs6000_reg_names[14][0], /* r14 */ \
2180 &rs6000_reg_names[15][0], /* r15 */ \
2181 &rs6000_reg_names[16][0], /* r16 */ \
2182 &rs6000_reg_names[17][0], /* r17 */ \
2183 &rs6000_reg_names[18][0], /* r18 */ \
2184 &rs6000_reg_names[19][0], /* r19 */ \
2185 &rs6000_reg_names[20][0], /* r20 */ \
2186 &rs6000_reg_names[21][0], /* r21 */ \
2187 &rs6000_reg_names[22][0], /* r22 */ \
2188 &rs6000_reg_names[23][0], /* r23 */ \
2189 &rs6000_reg_names[24][0], /* r24 */ \
2190 &rs6000_reg_names[25][0], /* r25 */ \
2191 &rs6000_reg_names[26][0], /* r26 */ \
2192 &rs6000_reg_names[27][0], /* r27 */ \
2193 &rs6000_reg_names[28][0], /* r28 */ \
2194 &rs6000_reg_names[29][0], /* r29 */ \
2195 &rs6000_reg_names[30][0], /* r30 */ \
2196 &rs6000_reg_names[31][0], /* r31 */ \
2198 &rs6000_reg_names[32][0], /* fr0 */ \
2199 &rs6000_reg_names[33][0], /* fr1 */ \
2200 &rs6000_reg_names[34][0], /* fr2 */ \
2201 &rs6000_reg_names[35][0], /* fr3 */ \
2202 &rs6000_reg_names[36][0], /* fr4 */ \
2203 &rs6000_reg_names[37][0], /* fr5 */ \
2204 &rs6000_reg_names[38][0], /* fr6 */ \
2205 &rs6000_reg_names[39][0], /* fr7 */ \
2206 &rs6000_reg_names[40][0], /* fr8 */ \
2207 &rs6000_reg_names[41][0], /* fr9 */ \
2208 &rs6000_reg_names[42][0], /* fr10 */ \
2209 &rs6000_reg_names[43][0], /* fr11 */ \
2210 &rs6000_reg_names[44][0], /* fr12 */ \
2211 &rs6000_reg_names[45][0], /* fr13 */ \
2212 &rs6000_reg_names[46][0], /* fr14 */ \
2213 &rs6000_reg_names[47][0], /* fr15 */ \
2214 &rs6000_reg_names[48][0], /* fr16 */ \
2215 &rs6000_reg_names[49][0], /* fr17 */ \
2216 &rs6000_reg_names[50][0], /* fr18 */ \
2217 &rs6000_reg_names[51][0], /* fr19 */ \
2218 &rs6000_reg_names[52][0], /* fr20 */ \
2219 &rs6000_reg_names[53][0], /* fr21 */ \
2220 &rs6000_reg_names[54][0], /* fr22 */ \
2221 &rs6000_reg_names[55][0], /* fr23 */ \
2222 &rs6000_reg_names[56][0], /* fr24 */ \
2223 &rs6000_reg_names[57][0], /* fr25 */ \
2224 &rs6000_reg_names[58][0], /* fr26 */ \
2225 &rs6000_reg_names[59][0], /* fr27 */ \
2226 &rs6000_reg_names[60][0], /* fr28 */ \
2227 &rs6000_reg_names[61][0], /* fr29 */ \
2228 &rs6000_reg_names[62][0], /* fr30 */ \
2229 &rs6000_reg_names[63][0], /* fr31 */ \
2231 &rs6000_reg_names[64][0], /* mq */ \
2232 &rs6000_reg_names[65][0], /* lr */ \
2233 &rs6000_reg_names[66][0], /* ctr */ \
2234 &rs6000_reg_names[67][0], /* ap */ \
2236 &rs6000_reg_names[68][0], /* cr0 */ \
2237 &rs6000_reg_names[69][0], /* cr1 */ \
2238 &rs6000_reg_names[70][0], /* cr2 */ \
2239 &rs6000_reg_names[71][0], /* cr3 */ \
2240 &rs6000_reg_names[72][0], /* cr4 */ \
2241 &rs6000_reg_names[73][0], /* cr5 */ \
2242 &rs6000_reg_names[74][0], /* cr6 */ \
2243 &rs6000_reg_names[75][0], /* cr7 */ \
2245 &rs6000_reg_names[76][0], /* xer */ \
2247 &rs6000_reg_names[77][0], /* v0 */ \
2248 &rs6000_reg_names[78][0], /* v1 */ \
2249 &rs6000_reg_names[79][0], /* v2 */ \
2250 &rs6000_reg_names[80][0], /* v3 */ \
2251 &rs6000_reg_names[81][0], /* v4 */ \
2252 &rs6000_reg_names[82][0], /* v5 */ \
2253 &rs6000_reg_names[83][0], /* v6 */ \
2254 &rs6000_reg_names[84][0], /* v7 */ \
2255 &rs6000_reg_names[85][0], /* v8 */ \
2256 &rs6000_reg_names[86][0], /* v9 */ \
2257 &rs6000_reg_names[87][0], /* v10 */ \
2258 &rs6000_reg_names[88][0], /* v11 */ \
2259 &rs6000_reg_names[89][0], /* v12 */ \
2260 &rs6000_reg_names[90][0], /* v13 */ \
2261 &rs6000_reg_names[91][0], /* v14 */ \
2262 &rs6000_reg_names[92][0], /* v15 */ \
2263 &rs6000_reg_names[93][0], /* v16 */ \
2264 &rs6000_reg_names[94][0], /* v17 */ \
2265 &rs6000_reg_names[95][0], /* v18 */ \
2266 &rs6000_reg_names[96][0], /* v19 */ \
2267 &rs6000_reg_names[97][0], /* v20 */ \
2268 &rs6000_reg_names[98][0], /* v21 */ \
2269 &rs6000_reg_names[99][0], /* v22 */ \
2270 &rs6000_reg_names[100][0], /* v23 */ \
2271 &rs6000_reg_names[101][0], /* v24 */ \
2272 &rs6000_reg_names[102][0], /* v25 */ \
2273 &rs6000_reg_names[103][0], /* v26 */ \
2274 &rs6000_reg_names[104][0], /* v27 */ \
2275 &rs6000_reg_names[105][0], /* v28 */ \
2276 &rs6000_reg_names[106][0], /* v29 */ \
2277 &rs6000_reg_names[107][0], /* v30 */ \
2278 &rs6000_reg_names[108][0], /* v31 */ \
2279 &rs6000_reg_names[109][0], /* vrsave */ \
2280 &rs6000_reg_names[110][0], /* vscr */ \
2281 &rs6000_reg_names[111][0], /* spe_acc */ \
2282 &rs6000_reg_names[112][0], /* spefscr */ \
2283 &rs6000_reg_names[113][0], /* sfp */ \
2286 /* Table of additional register names to use in user input. */
2288 #define ADDITIONAL_REGISTER_NAMES \
2289 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2290 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2291 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2292 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2293 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2294 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2295 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2296 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2297 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2298 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2299 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2300 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2301 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2302 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2303 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2304 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2305 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2306 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2307 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2308 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2309 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2310 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2311 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2312 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2313 {"vrsave", 109}, {"vscr", 110}, \
2314 {"spe_acc", 111}, {"spefscr", 112}, \
2315 /* no additional names for: mq, lr, ctr, ap */ \
2316 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2317 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2318 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2320 /* Text to write out after a CALL that may be replaced by glue code by
2321 the loader. This depends on the AIX version. */
2322 #define RS6000_CALL_GLUE "cror 31,31,31"
2324 /* This is how to output an element of a case-vector that is relative. */
2326 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2327 do { char buf[100]; \
2328 fputs ("\t.long ", FILE); \
2329 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2330 assemble_name (FILE, buf); \
2332 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2333 assemble_name (FILE, buf); \
2334 putc ('\n', FILE); \
2337 /* This is how to output an assembler line
2338 that says to advance the location counter
2339 to a multiple of 2**LOG bytes. */
2341 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2343 fprintf (FILE, "\t.align %d\n", (LOG))
2345 /* Pick up the return address upon entry to a procedure. Used for
2346 dwarf2 unwind information. This also enables the table driven
2349 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2350 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2352 /* Describe how we implement __builtin_eh_return. */
2353 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2354 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2356 /* Print operand X (an rtx) in assembler syntax to file FILE.
2357 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2358 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2360 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2362 /* Define which CODE values are valid. */
2364 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2365 ((CODE) == '.' || (CODE) == '&')
2367 /* Print a memory address as an operand to reference that memory location. */
2369 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2371 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2373 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2377 /* uncomment for disabling the corresponding default options */
2378 /* #define MACHINE_no_sched_interblock */
2379 /* #define MACHINE_no_sched_speculative */
2380 /* #define MACHINE_no_sched_speculative_load */
2382 /* General flags. */
2383 extern int flag_pic;
2384 extern int optimize;
2385 extern int flag_expensive_optimizations;
2386 extern int frame_pointer_needed;
2388 enum rs6000_builtins
2390 /* AltiVec builtins. */
2391 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2392 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2393 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2394 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2395 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2396 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2397 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2398 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2399 ALTIVEC_BUILTIN_VADDUBM,
2400 ALTIVEC_BUILTIN_VADDUHM,
2401 ALTIVEC_BUILTIN_VADDUWM,
2402 ALTIVEC_BUILTIN_VADDFP,
2403 ALTIVEC_BUILTIN_VADDCUW,
2404 ALTIVEC_BUILTIN_VADDUBS,
2405 ALTIVEC_BUILTIN_VADDSBS,
2406 ALTIVEC_BUILTIN_VADDUHS,
2407 ALTIVEC_BUILTIN_VADDSHS,
2408 ALTIVEC_BUILTIN_VADDUWS,
2409 ALTIVEC_BUILTIN_VADDSWS,
2410 ALTIVEC_BUILTIN_VAND,
2411 ALTIVEC_BUILTIN_VANDC,
2412 ALTIVEC_BUILTIN_VAVGUB,
2413 ALTIVEC_BUILTIN_VAVGSB,
2414 ALTIVEC_BUILTIN_VAVGUH,
2415 ALTIVEC_BUILTIN_VAVGSH,
2416 ALTIVEC_BUILTIN_VAVGUW,
2417 ALTIVEC_BUILTIN_VAVGSW,
2418 ALTIVEC_BUILTIN_VCFUX,
2419 ALTIVEC_BUILTIN_VCFSX,
2420 ALTIVEC_BUILTIN_VCTSXS,
2421 ALTIVEC_BUILTIN_VCTUXS,
2422 ALTIVEC_BUILTIN_VCMPBFP,
2423 ALTIVEC_BUILTIN_VCMPEQUB,
2424 ALTIVEC_BUILTIN_VCMPEQUH,
2425 ALTIVEC_BUILTIN_VCMPEQUW,
2426 ALTIVEC_BUILTIN_VCMPEQFP,
2427 ALTIVEC_BUILTIN_VCMPGEFP,
2428 ALTIVEC_BUILTIN_VCMPGTUB,
2429 ALTIVEC_BUILTIN_VCMPGTSB,
2430 ALTIVEC_BUILTIN_VCMPGTUH,
2431 ALTIVEC_BUILTIN_VCMPGTSH,
2432 ALTIVEC_BUILTIN_VCMPGTUW,
2433 ALTIVEC_BUILTIN_VCMPGTSW,
2434 ALTIVEC_BUILTIN_VCMPGTFP,
2435 ALTIVEC_BUILTIN_VEXPTEFP,
2436 ALTIVEC_BUILTIN_VLOGEFP,
2437 ALTIVEC_BUILTIN_VMADDFP,
2438 ALTIVEC_BUILTIN_VMAXUB,
2439 ALTIVEC_BUILTIN_VMAXSB,
2440 ALTIVEC_BUILTIN_VMAXUH,
2441 ALTIVEC_BUILTIN_VMAXSH,
2442 ALTIVEC_BUILTIN_VMAXUW,
2443 ALTIVEC_BUILTIN_VMAXSW,
2444 ALTIVEC_BUILTIN_VMAXFP,
2445 ALTIVEC_BUILTIN_VMHADDSHS,
2446 ALTIVEC_BUILTIN_VMHRADDSHS,
2447 ALTIVEC_BUILTIN_VMLADDUHM,
2448 ALTIVEC_BUILTIN_VMRGHB,
2449 ALTIVEC_BUILTIN_VMRGHH,
2450 ALTIVEC_BUILTIN_VMRGHW,
2451 ALTIVEC_BUILTIN_VMRGLB,
2452 ALTIVEC_BUILTIN_VMRGLH,
2453 ALTIVEC_BUILTIN_VMRGLW,
2454 ALTIVEC_BUILTIN_VMSUMUBM,
2455 ALTIVEC_BUILTIN_VMSUMMBM,
2456 ALTIVEC_BUILTIN_VMSUMUHM,
2457 ALTIVEC_BUILTIN_VMSUMSHM,
2458 ALTIVEC_BUILTIN_VMSUMUHS,
2459 ALTIVEC_BUILTIN_VMSUMSHS,
2460 ALTIVEC_BUILTIN_VMINUB,
2461 ALTIVEC_BUILTIN_VMINSB,
2462 ALTIVEC_BUILTIN_VMINUH,
2463 ALTIVEC_BUILTIN_VMINSH,
2464 ALTIVEC_BUILTIN_VMINUW,
2465 ALTIVEC_BUILTIN_VMINSW,
2466 ALTIVEC_BUILTIN_VMINFP,
2467 ALTIVEC_BUILTIN_VMULEUB,
2468 ALTIVEC_BUILTIN_VMULESB,
2469 ALTIVEC_BUILTIN_VMULEUH,
2470 ALTIVEC_BUILTIN_VMULESH,
2471 ALTIVEC_BUILTIN_VMULOUB,
2472 ALTIVEC_BUILTIN_VMULOSB,
2473 ALTIVEC_BUILTIN_VMULOUH,
2474 ALTIVEC_BUILTIN_VMULOSH,
2475 ALTIVEC_BUILTIN_VNMSUBFP,
2476 ALTIVEC_BUILTIN_VNOR,
2477 ALTIVEC_BUILTIN_VOR,
2478 ALTIVEC_BUILTIN_VSEL_4SI,
2479 ALTIVEC_BUILTIN_VSEL_4SF,
2480 ALTIVEC_BUILTIN_VSEL_8HI,
2481 ALTIVEC_BUILTIN_VSEL_16QI,
2482 ALTIVEC_BUILTIN_VPERM_4SI,
2483 ALTIVEC_BUILTIN_VPERM_4SF,
2484 ALTIVEC_BUILTIN_VPERM_8HI,
2485 ALTIVEC_BUILTIN_VPERM_16QI,
2486 ALTIVEC_BUILTIN_VPKUHUM,
2487 ALTIVEC_BUILTIN_VPKUWUM,
2488 ALTIVEC_BUILTIN_VPKPX,
2489 ALTIVEC_BUILTIN_VPKUHSS,
2490 ALTIVEC_BUILTIN_VPKSHSS,
2491 ALTIVEC_BUILTIN_VPKUWSS,
2492 ALTIVEC_BUILTIN_VPKSWSS,
2493 ALTIVEC_BUILTIN_VPKUHUS,
2494 ALTIVEC_BUILTIN_VPKSHUS,
2495 ALTIVEC_BUILTIN_VPKUWUS,
2496 ALTIVEC_BUILTIN_VPKSWUS,
2497 ALTIVEC_BUILTIN_VREFP,
2498 ALTIVEC_BUILTIN_VRFIM,
2499 ALTIVEC_BUILTIN_VRFIN,
2500 ALTIVEC_BUILTIN_VRFIP,
2501 ALTIVEC_BUILTIN_VRFIZ,
2502 ALTIVEC_BUILTIN_VRLB,
2503 ALTIVEC_BUILTIN_VRLH,
2504 ALTIVEC_BUILTIN_VRLW,
2505 ALTIVEC_BUILTIN_VRSQRTEFP,
2506 ALTIVEC_BUILTIN_VSLB,
2507 ALTIVEC_BUILTIN_VSLH,
2508 ALTIVEC_BUILTIN_VSLW,
2509 ALTIVEC_BUILTIN_VSL,
2510 ALTIVEC_BUILTIN_VSLO,
2511 ALTIVEC_BUILTIN_VSPLTB,
2512 ALTIVEC_BUILTIN_VSPLTH,
2513 ALTIVEC_BUILTIN_VSPLTW,
2514 ALTIVEC_BUILTIN_VSPLTISB,
2515 ALTIVEC_BUILTIN_VSPLTISH,
2516 ALTIVEC_BUILTIN_VSPLTISW,
2517 ALTIVEC_BUILTIN_VSRB,
2518 ALTIVEC_BUILTIN_VSRH,
2519 ALTIVEC_BUILTIN_VSRW,
2520 ALTIVEC_BUILTIN_VSRAB,
2521 ALTIVEC_BUILTIN_VSRAH,
2522 ALTIVEC_BUILTIN_VSRAW,
2523 ALTIVEC_BUILTIN_VSR,
2524 ALTIVEC_BUILTIN_VSRO,
2525 ALTIVEC_BUILTIN_VSUBUBM,
2526 ALTIVEC_BUILTIN_VSUBUHM,
2527 ALTIVEC_BUILTIN_VSUBUWM,
2528 ALTIVEC_BUILTIN_VSUBFP,
2529 ALTIVEC_BUILTIN_VSUBCUW,
2530 ALTIVEC_BUILTIN_VSUBUBS,
2531 ALTIVEC_BUILTIN_VSUBSBS,
2532 ALTIVEC_BUILTIN_VSUBUHS,
2533 ALTIVEC_BUILTIN_VSUBSHS,
2534 ALTIVEC_BUILTIN_VSUBUWS,
2535 ALTIVEC_BUILTIN_VSUBSWS,
2536 ALTIVEC_BUILTIN_VSUM4UBS,
2537 ALTIVEC_BUILTIN_VSUM4SBS,
2538 ALTIVEC_BUILTIN_VSUM4SHS,
2539 ALTIVEC_BUILTIN_VSUM2SWS,
2540 ALTIVEC_BUILTIN_VSUMSWS,
2541 ALTIVEC_BUILTIN_VXOR,
2542 ALTIVEC_BUILTIN_VSLDOI_16QI,
2543 ALTIVEC_BUILTIN_VSLDOI_8HI,
2544 ALTIVEC_BUILTIN_VSLDOI_4SI,
2545 ALTIVEC_BUILTIN_VSLDOI_4SF,
2546 ALTIVEC_BUILTIN_VUPKHSB,
2547 ALTIVEC_BUILTIN_VUPKHPX,
2548 ALTIVEC_BUILTIN_VUPKHSH,
2549 ALTIVEC_BUILTIN_VUPKLSB,
2550 ALTIVEC_BUILTIN_VUPKLPX,
2551 ALTIVEC_BUILTIN_VUPKLSH,
2552 ALTIVEC_BUILTIN_MTVSCR,
2553 ALTIVEC_BUILTIN_MFVSCR,
2554 ALTIVEC_BUILTIN_DSSALL,
2555 ALTIVEC_BUILTIN_DSS,
2556 ALTIVEC_BUILTIN_LVSL,
2557 ALTIVEC_BUILTIN_LVSR,
2558 ALTIVEC_BUILTIN_DSTT,
2559 ALTIVEC_BUILTIN_DSTST,
2560 ALTIVEC_BUILTIN_DSTSTT,
2561 ALTIVEC_BUILTIN_DST,
2562 ALTIVEC_BUILTIN_LVEBX,
2563 ALTIVEC_BUILTIN_LVEHX,
2564 ALTIVEC_BUILTIN_LVEWX,
2565 ALTIVEC_BUILTIN_LVXL,
2566 ALTIVEC_BUILTIN_LVX,
2567 ALTIVEC_BUILTIN_STVX,
2568 ALTIVEC_BUILTIN_LVLX,
2569 ALTIVEC_BUILTIN_LVLXL,
2570 ALTIVEC_BUILTIN_LVRX,
2571 ALTIVEC_BUILTIN_LVRXL,
2572 ALTIVEC_BUILTIN_STVEBX,
2573 ALTIVEC_BUILTIN_STVEHX,
2574 ALTIVEC_BUILTIN_STVEWX,
2575 ALTIVEC_BUILTIN_STVXL,
2576 ALTIVEC_BUILTIN_STVLX,
2577 ALTIVEC_BUILTIN_STVLXL,
2578 ALTIVEC_BUILTIN_STVRX,
2579 ALTIVEC_BUILTIN_STVRXL,
2580 ALTIVEC_BUILTIN_VCMPBFP_P,
2581 ALTIVEC_BUILTIN_VCMPEQFP_P,
2582 ALTIVEC_BUILTIN_VCMPEQUB_P,
2583 ALTIVEC_BUILTIN_VCMPEQUH_P,
2584 ALTIVEC_BUILTIN_VCMPEQUW_P,
2585 ALTIVEC_BUILTIN_VCMPGEFP_P,
2586 ALTIVEC_BUILTIN_VCMPGTFP_P,
2587 ALTIVEC_BUILTIN_VCMPGTSB_P,
2588 ALTIVEC_BUILTIN_VCMPGTSH_P,
2589 ALTIVEC_BUILTIN_VCMPGTSW_P,
2590 ALTIVEC_BUILTIN_VCMPGTUB_P,
2591 ALTIVEC_BUILTIN_VCMPGTUH_P,
2592 ALTIVEC_BUILTIN_VCMPGTUW_P,
2593 ALTIVEC_BUILTIN_ABSS_V4SI,
2594 ALTIVEC_BUILTIN_ABSS_V8HI,
2595 ALTIVEC_BUILTIN_ABSS_V16QI,
2596 ALTIVEC_BUILTIN_ABS_V4SI,
2597 ALTIVEC_BUILTIN_ABS_V4SF,
2598 ALTIVEC_BUILTIN_ABS_V8HI,
2599 ALTIVEC_BUILTIN_ABS_V16QI,
2600 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2601 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2602 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2603 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2604 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2605 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2606 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2607 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2608 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2609 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2610 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2611 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2612 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2613 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2615 /* Altivec overloaded builtins. */
2616 ALTIVEC_BUILTIN_VCMPEQ_P,
2617 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2618 ALTIVEC_BUILTIN_VCMPGT_P,
2619 ALTIVEC_BUILTIN_VCMPGE_P,
2620 ALTIVEC_BUILTIN_VEC_ABS,
2621 ALTIVEC_BUILTIN_VEC_ABSS,
2622 ALTIVEC_BUILTIN_VEC_ADD,
2623 ALTIVEC_BUILTIN_VEC_ADDC,
2624 ALTIVEC_BUILTIN_VEC_ADDS,
2625 ALTIVEC_BUILTIN_VEC_AND,
2626 ALTIVEC_BUILTIN_VEC_ANDC,
2627 ALTIVEC_BUILTIN_VEC_AVG,
2628 ALTIVEC_BUILTIN_VEC_EXTRACT,
2629 ALTIVEC_BUILTIN_VEC_CEIL,
2630 ALTIVEC_BUILTIN_VEC_CMPB,
2631 ALTIVEC_BUILTIN_VEC_CMPEQ,
2632 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2633 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2634 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2635 ALTIVEC_BUILTIN_VEC_CMPGE,
2636 ALTIVEC_BUILTIN_VEC_CMPGT,
2637 ALTIVEC_BUILTIN_VEC_CMPLE,
2638 ALTIVEC_BUILTIN_VEC_CMPLT,
2639 ALTIVEC_BUILTIN_VEC_CTF,
2640 ALTIVEC_BUILTIN_VEC_CTS,
2641 ALTIVEC_BUILTIN_VEC_CTU,
2642 ALTIVEC_BUILTIN_VEC_DST,
2643 ALTIVEC_BUILTIN_VEC_DSTST,
2644 ALTIVEC_BUILTIN_VEC_DSTSTT,
2645 ALTIVEC_BUILTIN_VEC_DSTT,
2646 ALTIVEC_BUILTIN_VEC_EXPTE,
2647 ALTIVEC_BUILTIN_VEC_FLOOR,
2648 ALTIVEC_BUILTIN_VEC_LD,
2649 ALTIVEC_BUILTIN_VEC_LDE,
2650 ALTIVEC_BUILTIN_VEC_LDL,
2651 ALTIVEC_BUILTIN_VEC_LOGE,
2652 ALTIVEC_BUILTIN_VEC_LVEBX,
2653 ALTIVEC_BUILTIN_VEC_LVEHX,
2654 ALTIVEC_BUILTIN_VEC_LVEWX,
2655 ALTIVEC_BUILTIN_VEC_LVLX,
2656 ALTIVEC_BUILTIN_VEC_LVLXL,
2657 ALTIVEC_BUILTIN_VEC_LVRX,
2658 ALTIVEC_BUILTIN_VEC_LVRXL,
2659 ALTIVEC_BUILTIN_VEC_LVSL,
2660 ALTIVEC_BUILTIN_VEC_LVSR,
2661 ALTIVEC_BUILTIN_VEC_MADD,
2662 ALTIVEC_BUILTIN_VEC_MADDS,
2663 ALTIVEC_BUILTIN_VEC_MAX,
2664 ALTIVEC_BUILTIN_VEC_MERGEH,
2665 ALTIVEC_BUILTIN_VEC_MERGEL,
2666 ALTIVEC_BUILTIN_VEC_MIN,
2667 ALTIVEC_BUILTIN_VEC_MLADD,
2668 ALTIVEC_BUILTIN_VEC_MPERM,
2669 ALTIVEC_BUILTIN_VEC_MRADDS,
2670 ALTIVEC_BUILTIN_VEC_MRGHB,
2671 ALTIVEC_BUILTIN_VEC_MRGHH,
2672 ALTIVEC_BUILTIN_VEC_MRGHW,
2673 ALTIVEC_BUILTIN_VEC_MRGLB,
2674 ALTIVEC_BUILTIN_VEC_MRGLH,
2675 ALTIVEC_BUILTIN_VEC_MRGLW,
2676 ALTIVEC_BUILTIN_VEC_MSUM,
2677 ALTIVEC_BUILTIN_VEC_MSUMS,
2678 ALTIVEC_BUILTIN_VEC_MTVSCR,
2679 ALTIVEC_BUILTIN_VEC_MULE,
2680 ALTIVEC_BUILTIN_VEC_MULO,
2681 ALTIVEC_BUILTIN_VEC_NMSUB,
2682 ALTIVEC_BUILTIN_VEC_NOR,
2683 ALTIVEC_BUILTIN_VEC_OR,
2684 ALTIVEC_BUILTIN_VEC_PACK,
2685 ALTIVEC_BUILTIN_VEC_PACKPX,
2686 ALTIVEC_BUILTIN_VEC_PACKS,
2687 ALTIVEC_BUILTIN_VEC_PACKSU,
2688 ALTIVEC_BUILTIN_VEC_PERM,
2689 ALTIVEC_BUILTIN_VEC_RE,
2690 ALTIVEC_BUILTIN_VEC_RL,
2691 ALTIVEC_BUILTIN_VEC_ROUND,
2692 ALTIVEC_BUILTIN_VEC_RSQRTE,
2693 ALTIVEC_BUILTIN_VEC_SEL,
2694 ALTIVEC_BUILTIN_VEC_SL,
2695 ALTIVEC_BUILTIN_VEC_SLD,
2696 ALTIVEC_BUILTIN_VEC_SLL,
2697 ALTIVEC_BUILTIN_VEC_SLO,
2698 ALTIVEC_BUILTIN_VEC_SPLAT,
2699 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2700 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2701 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2702 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2703 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2704 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2705 ALTIVEC_BUILTIN_VEC_SPLTB,
2706 ALTIVEC_BUILTIN_VEC_SPLTH,
2707 ALTIVEC_BUILTIN_VEC_SPLTW,
2708 ALTIVEC_BUILTIN_VEC_SR,
2709 ALTIVEC_BUILTIN_VEC_SRA,
2710 ALTIVEC_BUILTIN_VEC_SRL,
2711 ALTIVEC_BUILTIN_VEC_SRO,
2712 ALTIVEC_BUILTIN_VEC_ST,
2713 ALTIVEC_BUILTIN_VEC_STE,
2714 ALTIVEC_BUILTIN_VEC_STL,
2715 ALTIVEC_BUILTIN_VEC_STVEBX,
2716 ALTIVEC_BUILTIN_VEC_STVEHX,
2717 ALTIVEC_BUILTIN_VEC_STVEWX,
2718 ALTIVEC_BUILTIN_VEC_STVLX,
2719 ALTIVEC_BUILTIN_VEC_STVLXL,
2720 ALTIVEC_BUILTIN_VEC_STVRX,
2721 ALTIVEC_BUILTIN_VEC_STVRXL,
2722 ALTIVEC_BUILTIN_VEC_SUB,
2723 ALTIVEC_BUILTIN_VEC_SUBC,
2724 ALTIVEC_BUILTIN_VEC_SUBS,
2725 ALTIVEC_BUILTIN_VEC_SUM2S,
2726 ALTIVEC_BUILTIN_VEC_SUM4S,
2727 ALTIVEC_BUILTIN_VEC_SUMS,
2728 ALTIVEC_BUILTIN_VEC_TRUNC,
2729 ALTIVEC_BUILTIN_VEC_UNPACKH,
2730 ALTIVEC_BUILTIN_VEC_UNPACKL,
2731 ALTIVEC_BUILTIN_VEC_VADDFP,
2732 ALTIVEC_BUILTIN_VEC_VADDSBS,
2733 ALTIVEC_BUILTIN_VEC_VADDSHS,
2734 ALTIVEC_BUILTIN_VEC_VADDSWS,
2735 ALTIVEC_BUILTIN_VEC_VADDUBM,
2736 ALTIVEC_BUILTIN_VEC_VADDUBS,
2737 ALTIVEC_BUILTIN_VEC_VADDUHM,
2738 ALTIVEC_BUILTIN_VEC_VADDUHS,
2739 ALTIVEC_BUILTIN_VEC_VADDUWM,
2740 ALTIVEC_BUILTIN_VEC_VADDUWS,
2741 ALTIVEC_BUILTIN_VEC_VAVGSB,
2742 ALTIVEC_BUILTIN_VEC_VAVGSH,
2743 ALTIVEC_BUILTIN_VEC_VAVGSW,
2744 ALTIVEC_BUILTIN_VEC_VAVGUB,
2745 ALTIVEC_BUILTIN_VEC_VAVGUH,
2746 ALTIVEC_BUILTIN_VEC_VAVGUW,
2747 ALTIVEC_BUILTIN_VEC_VCFSX,
2748 ALTIVEC_BUILTIN_VEC_VCFUX,
2749 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2750 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2751 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2752 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2753 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2754 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2755 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2756 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2757 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2758 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2759 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2760 ALTIVEC_BUILTIN_VEC_VMAXFP,
2761 ALTIVEC_BUILTIN_VEC_VMAXSB,
2762 ALTIVEC_BUILTIN_VEC_VMAXSH,
2763 ALTIVEC_BUILTIN_VEC_VMAXSW,
2764 ALTIVEC_BUILTIN_VEC_VMAXUB,
2765 ALTIVEC_BUILTIN_VEC_VMAXUH,
2766 ALTIVEC_BUILTIN_VEC_VMAXUW,
2767 ALTIVEC_BUILTIN_VEC_VMINFP,
2768 ALTIVEC_BUILTIN_VEC_VMINSB,
2769 ALTIVEC_BUILTIN_VEC_VMINSH,
2770 ALTIVEC_BUILTIN_VEC_VMINSW,
2771 ALTIVEC_BUILTIN_VEC_VMINUB,
2772 ALTIVEC_BUILTIN_VEC_VMINUH,
2773 ALTIVEC_BUILTIN_VEC_VMINUW,
2774 ALTIVEC_BUILTIN_VEC_VMRGHB,
2775 ALTIVEC_BUILTIN_VEC_VMRGHH,
2776 ALTIVEC_BUILTIN_VEC_VMRGHW,
2777 ALTIVEC_BUILTIN_VEC_VMRGLB,
2778 ALTIVEC_BUILTIN_VEC_VMRGLH,
2779 ALTIVEC_BUILTIN_VEC_VMRGLW,
2780 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2781 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2782 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2783 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2784 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2785 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2786 ALTIVEC_BUILTIN_VEC_VMULESB,
2787 ALTIVEC_BUILTIN_VEC_VMULESH,
2788 ALTIVEC_BUILTIN_VEC_VMULEUB,
2789 ALTIVEC_BUILTIN_VEC_VMULEUH,
2790 ALTIVEC_BUILTIN_VEC_VMULOSB,
2791 ALTIVEC_BUILTIN_VEC_VMULOSH,
2792 ALTIVEC_BUILTIN_VEC_VMULOUB,
2793 ALTIVEC_BUILTIN_VEC_VMULOUH,
2794 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2795 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2796 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2797 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2798 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2799 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2800 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2801 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2802 ALTIVEC_BUILTIN_VEC_VRLB,
2803 ALTIVEC_BUILTIN_VEC_VRLH,
2804 ALTIVEC_BUILTIN_VEC_VRLW,
2805 ALTIVEC_BUILTIN_VEC_VSLB,
2806 ALTIVEC_BUILTIN_VEC_VSLH,
2807 ALTIVEC_BUILTIN_VEC_VSLW,
2808 ALTIVEC_BUILTIN_VEC_VSPLTB,
2809 ALTIVEC_BUILTIN_VEC_VSPLTH,
2810 ALTIVEC_BUILTIN_VEC_VSPLTW,
2811 ALTIVEC_BUILTIN_VEC_VSRAB,
2812 ALTIVEC_BUILTIN_VEC_VSRAH,
2813 ALTIVEC_BUILTIN_VEC_VSRAW,
2814 ALTIVEC_BUILTIN_VEC_VSRB,
2815 ALTIVEC_BUILTIN_VEC_VSRH,
2816 ALTIVEC_BUILTIN_VEC_VSRW,
2817 ALTIVEC_BUILTIN_VEC_VSUBFP,
2818 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2819 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2820 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2821 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2822 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2823 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2824 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2825 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2826 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2827 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2828 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2829 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2830 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2831 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2832 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2833 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2834 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2835 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2836 ALTIVEC_BUILTIN_VEC_XOR,
2837 ALTIVEC_BUILTIN_VEC_STEP,
2838 ALTIVEC_BUILTIN_VEC_PROMOTE,
2839 ALTIVEC_BUILTIN_VEC_INSERT,
2840 ALTIVEC_BUILTIN_VEC_SPLATS,
2841 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
2847 SPE_BUILTIN_EVDIVWS,
2848 SPE_BUILTIN_EVDIVWU,
2850 SPE_BUILTIN_EVFSADD,
2851 SPE_BUILTIN_EVFSDIV,
2852 SPE_BUILTIN_EVFSMUL,
2853 SPE_BUILTIN_EVFSSUB,
2857 SPE_BUILTIN_EVLHHESPLATX,
2858 SPE_BUILTIN_EVLHHOSSPLATX,
2859 SPE_BUILTIN_EVLHHOUSPLATX,
2860 SPE_BUILTIN_EVLWHEX,
2861 SPE_BUILTIN_EVLWHOSX,
2862 SPE_BUILTIN_EVLWHOUX,
2863 SPE_BUILTIN_EVLWHSPLATX,
2864 SPE_BUILTIN_EVLWWSPLATX,
2865 SPE_BUILTIN_EVMERGEHI,
2866 SPE_BUILTIN_EVMERGEHILO,
2867 SPE_BUILTIN_EVMERGELO,
2868 SPE_BUILTIN_EVMERGELOHI,
2869 SPE_BUILTIN_EVMHEGSMFAA,
2870 SPE_BUILTIN_EVMHEGSMFAN,
2871 SPE_BUILTIN_EVMHEGSMIAA,
2872 SPE_BUILTIN_EVMHEGSMIAN,
2873 SPE_BUILTIN_EVMHEGUMIAA,
2874 SPE_BUILTIN_EVMHEGUMIAN,
2875 SPE_BUILTIN_EVMHESMF,
2876 SPE_BUILTIN_EVMHESMFA,
2877 SPE_BUILTIN_EVMHESMFAAW,
2878 SPE_BUILTIN_EVMHESMFANW,
2879 SPE_BUILTIN_EVMHESMI,
2880 SPE_BUILTIN_EVMHESMIA,
2881 SPE_BUILTIN_EVMHESMIAAW,
2882 SPE_BUILTIN_EVMHESMIANW,
2883 SPE_BUILTIN_EVMHESSF,
2884 SPE_BUILTIN_EVMHESSFA,
2885 SPE_BUILTIN_EVMHESSFAAW,
2886 SPE_BUILTIN_EVMHESSFANW,
2887 SPE_BUILTIN_EVMHESSIAAW,
2888 SPE_BUILTIN_EVMHESSIANW,
2889 SPE_BUILTIN_EVMHEUMI,
2890 SPE_BUILTIN_EVMHEUMIA,
2891 SPE_BUILTIN_EVMHEUMIAAW,
2892 SPE_BUILTIN_EVMHEUMIANW,
2893 SPE_BUILTIN_EVMHEUSIAAW,
2894 SPE_BUILTIN_EVMHEUSIANW,
2895 SPE_BUILTIN_EVMHOGSMFAA,
2896 SPE_BUILTIN_EVMHOGSMFAN,
2897 SPE_BUILTIN_EVMHOGSMIAA,
2898 SPE_BUILTIN_EVMHOGSMIAN,
2899 SPE_BUILTIN_EVMHOGUMIAA,
2900 SPE_BUILTIN_EVMHOGUMIAN,
2901 SPE_BUILTIN_EVMHOSMF,
2902 SPE_BUILTIN_EVMHOSMFA,
2903 SPE_BUILTIN_EVMHOSMFAAW,
2904 SPE_BUILTIN_EVMHOSMFANW,
2905 SPE_BUILTIN_EVMHOSMI,
2906 SPE_BUILTIN_EVMHOSMIA,
2907 SPE_BUILTIN_EVMHOSMIAAW,
2908 SPE_BUILTIN_EVMHOSMIANW,
2909 SPE_BUILTIN_EVMHOSSF,
2910 SPE_BUILTIN_EVMHOSSFA,
2911 SPE_BUILTIN_EVMHOSSFAAW,
2912 SPE_BUILTIN_EVMHOSSFANW,
2913 SPE_BUILTIN_EVMHOSSIAAW,
2914 SPE_BUILTIN_EVMHOSSIANW,
2915 SPE_BUILTIN_EVMHOUMI,
2916 SPE_BUILTIN_EVMHOUMIA,
2917 SPE_BUILTIN_EVMHOUMIAAW,
2918 SPE_BUILTIN_EVMHOUMIANW,
2919 SPE_BUILTIN_EVMHOUSIAAW,
2920 SPE_BUILTIN_EVMHOUSIANW,
2921 SPE_BUILTIN_EVMWHSMF,
2922 SPE_BUILTIN_EVMWHSMFA,
2923 SPE_BUILTIN_EVMWHSMI,
2924 SPE_BUILTIN_EVMWHSMIA,
2925 SPE_BUILTIN_EVMWHSSF,
2926 SPE_BUILTIN_EVMWHSSFA,
2927 SPE_BUILTIN_EVMWHUMI,
2928 SPE_BUILTIN_EVMWHUMIA,
2929 SPE_BUILTIN_EVMWLSMIAAW,
2930 SPE_BUILTIN_EVMWLSMIANW,
2931 SPE_BUILTIN_EVMWLSSIAAW,
2932 SPE_BUILTIN_EVMWLSSIANW,
2933 SPE_BUILTIN_EVMWLUMI,
2934 SPE_BUILTIN_EVMWLUMIA,
2935 SPE_BUILTIN_EVMWLUMIAAW,
2936 SPE_BUILTIN_EVMWLUMIANW,
2937 SPE_BUILTIN_EVMWLUSIAAW,
2938 SPE_BUILTIN_EVMWLUSIANW,
2939 SPE_BUILTIN_EVMWSMF,
2940 SPE_BUILTIN_EVMWSMFA,
2941 SPE_BUILTIN_EVMWSMFAA,
2942 SPE_BUILTIN_EVMWSMFAN,
2943 SPE_BUILTIN_EVMWSMI,
2944 SPE_BUILTIN_EVMWSMIA,
2945 SPE_BUILTIN_EVMWSMIAA,
2946 SPE_BUILTIN_EVMWSMIAN,
2947 SPE_BUILTIN_EVMWHSSFAA,
2948 SPE_BUILTIN_EVMWSSF,
2949 SPE_BUILTIN_EVMWSSFA,
2950 SPE_BUILTIN_EVMWSSFAA,
2951 SPE_BUILTIN_EVMWSSFAN,
2952 SPE_BUILTIN_EVMWUMI,
2953 SPE_BUILTIN_EVMWUMIA,
2954 SPE_BUILTIN_EVMWUMIAA,
2955 SPE_BUILTIN_EVMWUMIAN,
2964 SPE_BUILTIN_EVSTDDX,
2965 SPE_BUILTIN_EVSTDHX,
2966 SPE_BUILTIN_EVSTDWX,
2967 SPE_BUILTIN_EVSTWHEX,
2968 SPE_BUILTIN_EVSTWHOX,
2969 SPE_BUILTIN_EVSTWWEX,
2970 SPE_BUILTIN_EVSTWWOX,
2971 SPE_BUILTIN_EVSUBFW,
2974 SPE_BUILTIN_EVADDSMIAAW,
2975 SPE_BUILTIN_EVADDSSIAAW,
2976 SPE_BUILTIN_EVADDUMIAAW,
2977 SPE_BUILTIN_EVADDUSIAAW,
2978 SPE_BUILTIN_EVCNTLSW,
2979 SPE_BUILTIN_EVCNTLZW,
2980 SPE_BUILTIN_EVEXTSB,
2981 SPE_BUILTIN_EVEXTSH,
2982 SPE_BUILTIN_EVFSABS,
2983 SPE_BUILTIN_EVFSCFSF,
2984 SPE_BUILTIN_EVFSCFSI,
2985 SPE_BUILTIN_EVFSCFUF,
2986 SPE_BUILTIN_EVFSCFUI,
2987 SPE_BUILTIN_EVFSCTSF,
2988 SPE_BUILTIN_EVFSCTSI,
2989 SPE_BUILTIN_EVFSCTSIZ,
2990 SPE_BUILTIN_EVFSCTUF,
2991 SPE_BUILTIN_EVFSCTUI,
2992 SPE_BUILTIN_EVFSCTUIZ,
2993 SPE_BUILTIN_EVFSNABS,
2994 SPE_BUILTIN_EVFSNEG,
2998 SPE_BUILTIN_EVSUBFSMIAAW,
2999 SPE_BUILTIN_EVSUBFSSIAAW,
3000 SPE_BUILTIN_EVSUBFUMIAAW,
3001 SPE_BUILTIN_EVSUBFUSIAAW,
3002 SPE_BUILTIN_EVADDIW,
3006 SPE_BUILTIN_EVLHHESPLAT,
3007 SPE_BUILTIN_EVLHHOSSPLAT,
3008 SPE_BUILTIN_EVLHHOUSPLAT,
3010 SPE_BUILTIN_EVLWHOS,
3011 SPE_BUILTIN_EVLWHOU,
3012 SPE_BUILTIN_EVLWHSPLAT,
3013 SPE_BUILTIN_EVLWWSPLAT,
3016 SPE_BUILTIN_EVSRWIS,
3017 SPE_BUILTIN_EVSRWIU,
3021 SPE_BUILTIN_EVSTWHE,
3022 SPE_BUILTIN_EVSTWHO,
3023 SPE_BUILTIN_EVSTWWE,
3024 SPE_BUILTIN_EVSTWWO,
3025 SPE_BUILTIN_EVSUBIFW,
3028 SPE_BUILTIN_EVCMPEQ,
3029 SPE_BUILTIN_EVCMPGTS,
3030 SPE_BUILTIN_EVCMPGTU,
3031 SPE_BUILTIN_EVCMPLTS,
3032 SPE_BUILTIN_EVCMPLTU,
3033 SPE_BUILTIN_EVFSCMPEQ,
3034 SPE_BUILTIN_EVFSCMPGT,
3035 SPE_BUILTIN_EVFSCMPLT,
3036 SPE_BUILTIN_EVFSTSTEQ,
3037 SPE_BUILTIN_EVFSTSTGT,
3038 SPE_BUILTIN_EVFSTSTLT,
3040 /* EVSEL compares. */
3041 SPE_BUILTIN_EVSEL_CMPEQ,
3042 SPE_BUILTIN_EVSEL_CMPGTS,
3043 SPE_BUILTIN_EVSEL_CMPGTU,
3044 SPE_BUILTIN_EVSEL_CMPLTS,
3045 SPE_BUILTIN_EVSEL_CMPLTU,
3046 SPE_BUILTIN_EVSEL_FSCMPEQ,
3047 SPE_BUILTIN_EVSEL_FSCMPGT,
3048 SPE_BUILTIN_EVSEL_FSCMPLT,
3049 SPE_BUILTIN_EVSEL_FSTSTEQ,
3050 SPE_BUILTIN_EVSEL_FSTSTGT,
3051 SPE_BUILTIN_EVSEL_FSTSTLT,
3053 SPE_BUILTIN_EVSPLATFI,
3054 SPE_BUILTIN_EVSPLATI,
3055 SPE_BUILTIN_EVMWHSSMAA,
3056 SPE_BUILTIN_EVMWHSMFAA,
3057 SPE_BUILTIN_EVMWHSMIAA,
3058 SPE_BUILTIN_EVMWHUSIAA,
3059 SPE_BUILTIN_EVMWHUMIAA,
3060 SPE_BUILTIN_EVMWHSSFAN,
3061 SPE_BUILTIN_EVMWHSSIAN,
3062 SPE_BUILTIN_EVMWHSMFAN,
3063 SPE_BUILTIN_EVMWHSMIAN,
3064 SPE_BUILTIN_EVMWHUSIAN,
3065 SPE_BUILTIN_EVMWHUMIAN,
3066 SPE_BUILTIN_EVMWHGSSFAA,
3067 SPE_BUILTIN_EVMWHGSMFAA,
3068 SPE_BUILTIN_EVMWHGSMIAA,
3069 SPE_BUILTIN_EVMWHGUMIAA,
3070 SPE_BUILTIN_EVMWHGSSFAN,
3071 SPE_BUILTIN_EVMWHGSMFAN,
3072 SPE_BUILTIN_EVMWHGSMIAN,
3073 SPE_BUILTIN_EVMWHGUMIAN,
3074 SPE_BUILTIN_MTSPEFSCR,
3075 SPE_BUILTIN_MFSPEFSCR,
3078 /* PAIRED builtins. */
3079 PAIRED_BUILTIN_DIVV2SF3,
3080 PAIRED_BUILTIN_ABSV2SF2,
3081 PAIRED_BUILTIN_NEGV2SF2,
3082 PAIRED_BUILTIN_SQRTV2SF2,
3083 PAIRED_BUILTIN_ADDV2SF3,
3084 PAIRED_BUILTIN_SUBV2SF3,
3085 PAIRED_BUILTIN_RESV2SF2,
3086 PAIRED_BUILTIN_MULV2SF3,
3087 PAIRED_BUILTIN_MSUB,
3088 PAIRED_BUILTIN_MADD,
3089 PAIRED_BUILTIN_NMSUB,
3090 PAIRED_BUILTIN_NMADD,
3091 PAIRED_BUILTIN_NABSV2SF2,
3092 PAIRED_BUILTIN_SUM0,
3093 PAIRED_BUILTIN_SUM1,
3094 PAIRED_BUILTIN_MULS0,
3095 PAIRED_BUILTIN_MULS1,
3096 PAIRED_BUILTIN_MERGE00,
3097 PAIRED_BUILTIN_MERGE01,
3098 PAIRED_BUILTIN_MERGE10,
3099 PAIRED_BUILTIN_MERGE11,
3100 PAIRED_BUILTIN_MADDS0,
3101 PAIRED_BUILTIN_MADDS1,
3104 PAIRED_BUILTIN_SELV2SF4,
3105 PAIRED_BUILTIN_CMPU0,
3106 PAIRED_BUILTIN_CMPU1,
3108 RS6000_BUILTIN_RECIP,
3109 RS6000_BUILTIN_RECIPF,
3110 RS6000_BUILTIN_RSQRTF,
3112 RS6000_BUILTIN_COUNT
3115 enum rs6000_builtin_type_index
3117 RS6000_BTI_NOT_OPAQUE,
3118 RS6000_BTI_opaque_V2SI,
3119 RS6000_BTI_opaque_V2SF,
3120 RS6000_BTI_opaque_p_V2SI,
3121 RS6000_BTI_opaque_V4SI,
3129 RS6000_BTI_unsigned_V16QI,
3130 RS6000_BTI_unsigned_V8HI,
3131 RS6000_BTI_unsigned_V4SI,
3132 RS6000_BTI_bool_char, /* __bool char */
3133 RS6000_BTI_bool_short, /* __bool short */
3134 RS6000_BTI_bool_int, /* __bool int */
3135 RS6000_BTI_pixel, /* __pixel */
3136 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3137 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3138 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3139 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3140 RS6000_BTI_long, /* long_integer_type_node */
3141 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3142 RS6000_BTI_INTQI, /* intQI_type_node */
3143 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3144 RS6000_BTI_INTHI, /* intHI_type_node */
3145 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3146 RS6000_BTI_INTSI, /* intSI_type_node */
3147 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3148 RS6000_BTI_float, /* float_type_node */
3149 RS6000_BTI_void, /* void_type_node */
3154 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3155 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3156 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3157 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3158 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3159 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3160 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3161 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3162 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3163 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3164 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3165 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3166 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3167 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3168 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3169 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3170 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3171 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3172 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3173 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3174 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3175 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3177 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3178 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3179 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3180 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3181 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3182 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3183 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3184 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3185 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3186 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3188 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3189 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];