1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 #ifndef TARGET_PAIRED_FLOAT
60 #define TARGET_PAIRED_FLOAT 0
63 #ifdef HAVE_AS_POPCNTB
64 #define ASM_CPU_POWER5_SPEC "-mpower5"
66 #define ASM_CPU_POWER5_SPEC "-mpower4"
70 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
72 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
75 /* Common ASM definitions used by ASM_SPEC among the various targets
76 for handling -mcpu=xxx switches. */
77 #define ASM_CPU_SPEC \
79 %{mpower: %{!mpower2: -mpwr}} \
81 %{mpowerpc64*: -mppc64} \
82 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
83 %{mno-power: %{!mpowerpc*: -mcom}} \
84 %{!mno-power: %{!mpower*: %(asm_default)}}} \
85 %{mcpu=common: -mcom} \
86 %{mcpu=cell: -mcell} \
87 %{mcpu=power: -mpwr} \
88 %{mcpu=power2: -mpwrx} \
89 %{mcpu=power3: -mppc64} \
90 %{mcpu=power4: -mpower4} \
91 %{mcpu=power5: %(asm_cpu_power5)} \
92 %{mcpu=power5+: %(asm_cpu_power5)} \
93 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
94 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
95 %{mcpu=powerpc: -mppc} \
97 %{mcpu=rios1: -mpwr} \
98 %{mcpu=rios2: -mpwrx} \
100 %{mcpu=rsc1: -mpwr} \
101 %{mcpu=rs64a: -mppc64} \
105 %{mcpu=405fp: -m405} \
107 %{mcpu=440fp: -m440} \
109 %{mcpu=464fp: -m440} \
114 %{mcpu=603e: -mppc} \
115 %{mcpu=ec603e: -mppc} \
117 %{mcpu=604e: -mppc} \
118 %{mcpu=620: -mppc64} \
119 %{mcpu=630: -mppc64} \
123 %{mcpu=7400: -mppc -maltivec} \
124 %{mcpu=7450: -mppc -maltivec} \
125 %{mcpu=G4: -mppc -maltivec} \
130 %{mcpu=970: -mpower4 -maltivec} \
131 %{mcpu=G5: -mpower4 -maltivec} \
132 %{mcpu=8540: -me500} \
133 %{mcpu=8548: -me500} \
134 %{mcpu=e300c2: -me300} \
135 %{mcpu=e300c3: -me300} \
136 %{mcpu=e500mc: -me500mc} \
137 %{maltivec: -maltivec} \
140 #define CPP_DEFAULT_SPEC ""
142 #define ASM_DEFAULT_SPEC ""
144 /* This macro defines names of additional specifications to put in the specs
145 that can be used in various specifications like CC1_SPEC. Its definition
146 is an initializer with a subgrouping for each command option.
148 Each subgrouping contains a string constant, that defines the
149 specification name, and a string constant that used by the GCC driver
152 Do not define this macro if it does not need to do anything. */
154 #define SUBTARGET_EXTRA_SPECS
156 #define EXTRA_SPECS \
157 { "cpp_default", CPP_DEFAULT_SPEC }, \
158 { "asm_cpu", ASM_CPU_SPEC }, \
159 { "asm_default", ASM_DEFAULT_SPEC }, \
160 { "cc1_cpu", CC1_CPU_SPEC }, \
161 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
162 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
163 SUBTARGET_EXTRA_SPECS
165 /* -mcpu=native handling only makes sense with compiler running on
166 an PowerPC chip. If changing this condition, also change
167 the condition in driver-rs6000.c. */
168 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
169 /* In driver-rs6000.c. */
170 extern const char *host_detect_local_cpu (int argc, const char **argv);
171 #define EXTRA_SPEC_FUNCTIONS \
172 { "local_cpu_detect", host_detect_local_cpu },
173 #define HAVE_LOCAL_CPU_DETECT
177 #ifdef HAVE_LOCAL_CPU_DETECT
178 #define CC1_CPU_SPEC \
179 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
180 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
182 #define CC1_CPU_SPEC ""
186 /* Architecture type. */
188 /* Define TARGET_MFCRF if the target assembler does not support the
189 optional field operand for mfcr. */
191 #ifndef HAVE_AS_MFCRF
193 #define TARGET_MFCRF 0
196 /* Define TARGET_POPCNTB if the target assembler does not support the
197 popcount byte instruction. */
199 #ifndef HAVE_AS_POPCNTB
200 #undef TARGET_POPCNTB
201 #define TARGET_POPCNTB 0
204 /* Define TARGET_FPRND if the target assembler does not support the
205 fp rounding instructions. */
207 #ifndef HAVE_AS_FPRND
209 #define TARGET_FPRND 0
212 /* Define TARGET_CMPB if the target assembler does not support the
217 #define TARGET_CMPB 0
220 /* Define TARGET_MFPGPR if the target assembler does not support the
221 mffpr and mftgpr instructions. */
223 #ifndef HAVE_AS_MFPGPR
225 #define TARGET_MFPGPR 0
228 /* Define TARGET_DFP if the target assembler does not support decimal
229 floating point instructions. */
235 #ifndef TARGET_SECURE_PLT
236 #define TARGET_SECURE_PLT 0
239 #define TARGET_32BIT (! TARGET_64BIT)
242 #define HAVE_AS_TLS 0
245 /* Return 1 for a symbol ref for a thread-local storage symbol. */
246 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
247 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
250 /* For libgcc2 we make sure this is a compile time constant */
251 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
252 #undef TARGET_POWERPC64
253 #define TARGET_POWERPC64 1
255 #undef TARGET_POWERPC64
256 #define TARGET_POWERPC64 0
259 /* The option machinery will define this. */
262 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
264 /* Processor type. Order must match cpu attribute in MD file. */
293 extern enum processor_type rs6000_cpu;
295 /* Recast the processor type to the cpu attribute. */
296 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
298 /* Define generic processor types based upon current deployment. */
299 #define PROCESSOR_COMMON PROCESSOR_PPC601
300 #define PROCESSOR_POWER PROCESSOR_RIOS1
301 #define PROCESSOR_POWERPC PROCESSOR_PPC604
302 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
304 /* Define the default processor. This is overridden by other tm.h files. */
305 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
306 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
308 /* Specify the dialect of assembler to use. New mnemonics is dialect one
309 and the old mnemonics are dialect zero. */
310 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
312 /* Types of costly dependences. */
313 enum rs6000_dependence_cost
315 max_dep_latency = 1000,
318 true_store_to_load_dep_costly,
319 store_to_load_dep_costly
322 /* Types of nop insertion schemes in sched target hook sched_finish. */
323 enum rs6000_nop_insertion
325 sched_finish_regroup_exact = 1000,
326 sched_finish_pad_groups,
330 /* Dispatch group termination caused by an insn. */
331 enum group_termination
337 /* Support for a compile-time default CPU, et cetera. The rules are:
338 --with-cpu is ignored if -mcpu is specified.
339 --with-tune is ignored if -mtune is specified.
340 --with-float is ignored if -mhard-float or -msoft-float are
342 #define OPTION_DEFAULT_SPECS \
343 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
344 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
345 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
347 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
348 struct rs6000_cpu_select
356 extern struct rs6000_cpu_select rs6000_select[];
359 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
360 extern int rs6000_debug_stack; /* debug stack applications */
361 extern int rs6000_debug_arg; /* debug argument handling */
363 #define TARGET_DEBUG_STACK rs6000_debug_stack
364 #define TARGET_DEBUG_ARG rs6000_debug_arg
366 extern const char *rs6000_traceback_name; /* Type of traceback table. */
368 /* These are separate from target_flags because we've run out of bits
370 extern int rs6000_long_double_type_size;
371 extern int rs6000_ieeequad;
372 extern int rs6000_altivec_abi;
373 extern int rs6000_spe_abi;
374 extern int rs6000_spe;
375 extern int rs6000_isel;
376 extern int rs6000_float_gprs;
377 extern int rs6000_alignment_flags;
378 extern const char *rs6000_sched_insert_nops_str;
379 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
381 /* Alignment options for fields in structures for sub-targets following
383 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
384 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
386 Override the macro definitions when compiling libobjc to avoid undefined
387 reference to rs6000_alignment_flags due to library's use of GCC alignment
388 macros which use the macros below. */
390 #ifndef IN_TARGET_LIBS
391 #define MASK_ALIGN_POWER 0x00000000
392 #define MASK_ALIGN_NATURAL 0x00000001
393 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
395 #define TARGET_ALIGN_NATURAL 0
398 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
399 #define TARGET_IEEEQUAD rs6000_ieeequad
400 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
402 #define TARGET_SPE_ABI 0
404 #define TARGET_E500 0
405 #define TARGET_ISEL rs6000_isel
406 #define TARGET_FPRS 1
407 #define TARGET_E500_SINGLE 0
408 #define TARGET_E500_DOUBLE 0
409 #define CHECK_E500_OPTIONS do { } while (0)
411 /* E500 processors only support plain "sync", not lwsync. */
412 #define TARGET_NO_LWSYNC TARGET_E500
414 /* Sometimes certain combinations of command options do not make sense
415 on a particular target machine. You can define a macro
416 `OVERRIDE_OPTIONS' to take account of this. This macro, if
417 defined, is executed once just after all the command options have
420 Do not use this macro to turn on various extra optimizations for
421 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
423 On the RS/6000 this is used to define the target cpu type. */
425 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
427 /* Define this to change the optimizations performed by default. */
428 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
430 /* Show we can debug even without a frame pointer. */
431 #define CAN_DEBUG_WITHOUT_FP
434 #define REGISTER_TARGET_PRAGMAS() do { \
435 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
436 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
439 /* Target #defines. */
440 #define TARGET_CPU_CPP_BUILTINS() \
441 rs6000_cpu_cpp_builtins (pfile)
443 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
444 we're compiling for. Some configurations may need to override it. */
445 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
448 if (BYTES_BIG_ENDIAN) \
450 builtin_define ("__BIG_ENDIAN__"); \
451 builtin_define ("_BIG_ENDIAN"); \
452 builtin_assert ("machine=bigendian"); \
456 builtin_define ("__LITTLE_ENDIAN__"); \
457 builtin_define ("_LITTLE_ENDIAN"); \
458 builtin_assert ("machine=littleendian"); \
463 /* Target machine storage layout. */
465 /* Define this macro if it is advisable to hold scalars in registers
466 in a wider mode than that declared by the program. In such cases,
467 the value is constrained to be within the bounds of the declared
468 type, but kept valid in the wider mode. The signedness of the
469 extension may differ from that of the type. */
471 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
472 if (GET_MODE_CLASS (MODE) == MODE_INT \
473 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
474 (MODE) = TARGET_32BIT ? SImode : DImode;
476 /* Define this if most significant bit is lowest numbered
477 in instructions that operate on numbered bit-fields. */
478 /* That is true on RS/6000. */
479 #define BITS_BIG_ENDIAN 1
481 /* Define this if most significant byte of a word is the lowest numbered. */
482 /* That is true on RS/6000. */
483 #define BYTES_BIG_ENDIAN 1
485 /* Define this if most significant word of a multiword number is lowest
488 For RS/6000 we can decide arbitrarily since there are no machine
489 instructions for them. Might as well be consistent with bits and bytes. */
490 #define WORDS_BIG_ENDIAN 1
492 #define MAX_BITS_PER_WORD 64
494 /* Width of a word, in units (bytes). */
495 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
497 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
499 #define MIN_UNITS_PER_WORD 4
501 #define UNITS_PER_FP_WORD 8
502 #define UNITS_PER_ALTIVEC_WORD 16
503 #define UNITS_PER_SPE_WORD 8
504 #define UNITS_PER_PAIRED_WORD 8
506 /* Type used for ptrdiff_t, as a string used in a declaration. */
507 #define PTRDIFF_TYPE "int"
509 /* Type used for size_t, as a string used in a declaration. */
510 #define SIZE_TYPE "long unsigned int"
512 /* Type used for wchar_t, as a string used in a declaration. */
513 #define WCHAR_TYPE "short unsigned int"
515 /* Width of wchar_t in bits. */
516 #define WCHAR_TYPE_SIZE 16
518 /* A C expression for the size in bits of the type `short' on the
519 target machine. If you don't define this, the default is half a
520 word. (If this would be less than one storage unit, it is
521 rounded up to one unit.) */
522 #define SHORT_TYPE_SIZE 16
524 /* A C expression for the size in bits of the type `int' on the
525 target machine. If you don't define this, the default is one
527 #define INT_TYPE_SIZE 32
529 /* A C expression for the size in bits of the type `long' on the
530 target machine. If you don't define this, the default is one
532 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
534 /* A C expression for the size in bits of the type `long long' on the
535 target machine. If you don't define this, the default is two
537 #define LONG_LONG_TYPE_SIZE 64
539 /* A C expression for the size in bits of the type `float' on the
540 target machine. If you don't define this, the default is one
542 #define FLOAT_TYPE_SIZE 32
544 /* A C expression for the size in bits of the type `double' on the
545 target machine. If you don't define this, the default is two
547 #define DOUBLE_TYPE_SIZE 64
549 /* A C expression for the size in bits of the type `long double' on
550 the target machine. If you don't define this, the default is two
552 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
554 /* Define this to set long double type size to use in libgcc2.c, which can
555 not depend on target_flags. */
556 #ifdef __LONG_DOUBLE_128__
557 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
559 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
562 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
563 #define WIDEST_HARDWARE_FP_SIZE 64
565 /* Width in bits of a pointer.
566 See also the macro `Pmode' defined below. */
567 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
569 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
570 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
572 /* Boundary (in *bits*) on which stack pointer should be aligned. */
573 #define STACK_BOUNDARY \
574 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
576 /* Allocation boundary (in *bits*) for the code of a function. */
577 #define FUNCTION_BOUNDARY 32
579 /* No data type wants to be aligned rounder than this. */
580 #define BIGGEST_ALIGNMENT 128
582 /* A C expression to compute the alignment for a variables in the
583 local store. TYPE is the data type, and ALIGN is the alignment
584 that the object would ordinarily have. */
585 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
586 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
587 (TARGET_E500_DOUBLE \
588 && TYPE_MODE (TYPE) == DFmode) ? 64 : \
589 ((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
590 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
591 && TREE_CODE (TYPE) == VECTOR_TYPE \
592 && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) ? 64 : ALIGN)
594 /* Alignment of field after `int : 0' in a structure. */
595 #define EMPTY_FIELD_BOUNDARY 32
597 /* Every structure's size must be a multiple of this. */
598 #define STRUCTURE_SIZE_BOUNDARY 8
600 /* Return 1 if a structure or array containing FIELD should be
601 accessed using `BLKMODE'.
603 For the SPE, simd types are V2SI, and gcc can be tempted to put the
604 entire thing in a DI and use subregs to access the internals.
605 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
606 back-end. Because a single GPR can hold a V2SI, but not a DI, the
607 best thing to do is set structs to BLKmode and avoid Severe Tire
610 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
611 fit into 1, whereas DI still needs two. */
612 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
613 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
614 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
616 /* A bit-field declared as `int' forces `int' alignment for the struct. */
617 #define PCC_BITFIELD_TYPE_MATTERS 1
619 /* Make strings word-aligned so strcpy from constants will be faster.
620 Make vector constants quadword aligned. */
621 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
622 (TREE_CODE (EXP) == STRING_CST \
623 && (STRICT_ALIGNMENT || !optimize_size) \
624 && (ALIGN) < BITS_PER_WORD \
628 /* Make arrays of chars word-aligned for the same reasons.
629 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
631 #define DATA_ALIGNMENT(TYPE, ALIGN) \
632 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
633 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
634 : (TARGET_E500_DOUBLE \
635 && TYPE_MODE (TYPE) == DFmode) ? 64 \
636 : TREE_CODE (TYPE) == ARRAY_TYPE \
637 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
638 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
640 /* Nonzero if move instructions will actually fail to work
641 when given unaligned data. */
642 #define STRICT_ALIGNMENT 0
644 /* Define this macro to be the value 1 if unaligned accesses have a cost
645 many times greater than aligned accesses, for example if they are
646 emulated in a trap handler. */
647 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
649 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
650 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
651 || (MODE) == DImode) \
654 /* Standard register usage. */
656 /* Number of actual hardware registers.
657 The hardware registers are assigned numbers for the compiler
658 from 0 to just below FIRST_PSEUDO_REGISTER.
659 All registers that the compiler knows about must be given numbers,
660 even those that are not normally considered general registers.
662 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
663 an MQ register, a count register, a link register, and 8 condition
664 register fields, which we view here as separate registers. AltiVec
665 adds 32 vector registers and a VRsave register.
667 In addition, the difference between the frame and argument pointers is
668 a function of the number of registers saved, so we need to have a
669 register for AP that will later be eliminated in favor of SP or FP.
670 This is a normal register, but it is fixed.
672 We also create a pseudo register for float/int conversions, that will
673 really represent the memory location used. It is represented here as
674 a register, in order to work around problems in allocating stack storage
677 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
678 pointer, which is eventually eliminated in favor of SP or FP. */
680 #define FIRST_PSEUDO_REGISTER 114
682 /* This must be included for pre gcc 3.0 glibc compatibility. */
683 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
685 /* Add 32 dwarf columns for synthetic SPE registers. */
686 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
688 /* The SPE has an additional 32 synthetic registers, with DWARF debug
689 info numbering for these registers starting at 1200. While eh_frame
690 register numbering need not be the same as the debug info numbering,
691 we choose to number these regs for eh_frame at 1200 too. This allows
692 future versions of the rs6000 backend to add hard registers and
693 continue to use the gcc hard register numbering for eh_frame. If the
694 extra SPE registers in eh_frame were numbered starting from the
695 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
696 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
697 avoid invalidating older SPE eh_frame info.
699 We must map them here to avoid huge unwinder tables mostly consisting
701 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
702 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
704 /* Use standard DWARF numbering for DWARF debugging information. */
705 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
707 /* Use gcc hard register numbering for eh_frame. */
708 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
710 /* Map register numbers held in the call frame info that gcc has
711 collected using DWARF_FRAME_REGNUM to those that should be output in
712 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
713 for .eh_frame, but use the numbers mandated by the various ABIs for
714 .debug_frame. rs6000_emit_prologue has translated any combination of
715 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
716 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
717 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
718 ((FOR_EH) ? (REGNO) \
719 : (REGNO) == CR2_REGNO ? 64 \
720 : DBX_REGISTER_NUMBER (REGNO))
722 /* 1 for registers that have pervasive standard uses
723 and are not available for the register allocator.
725 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
726 as a local register; for all other OS's r2 is the TOC pointer.
728 cr5 is not supposed to be used.
730 On System V implementations, r13 is fixed and not available for use. */
732 #define FIXED_REGISTERS \
733 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
735 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
736 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
737 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
738 /* AltiVec registers. */ \
739 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
745 /* 1 for registers not available across function calls.
746 These must include the FIXED_REGISTERS and also any
747 registers that can be used without being saved.
748 The latter must include the registers where values are returned
749 and the register where structure-value addresses are passed.
750 Aside from that, you can include as many other registers as you like. */
752 #define CALL_USED_REGISTERS \
753 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
754 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
755 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
756 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
757 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
758 /* AltiVec registers. */ \
759 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
765 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
766 the entire set of `FIXED_REGISTERS' be included.
767 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
768 This macro is optional. If not specified, it defaults to the value
769 of `CALL_USED_REGISTERS'. */
771 #define CALL_REALLY_USED_REGISTERS \
772 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
774 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
776 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
777 /* AltiVec registers. */ \
778 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
779 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
784 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
786 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
787 #define FIRST_SAVED_FP_REGNO (14+32)
788 #define FIRST_SAVED_GP_REGNO 13
790 /* List the order in which to allocate registers. Each register must be
791 listed once, even those in FIXED_REGISTERS.
793 We allocate in the following order:
794 fp0 (not saved or used for anything)
795 fp13 - fp2 (not saved; incoming fp arg registers)
796 fp1 (not saved; return value)
797 fp31 - fp14 (saved; order given to save least number)
798 cr7, cr6 (not saved or special)
799 cr1 (not saved, but used for FP operations)
800 cr0 (not saved, but used for arithmetic operations)
801 cr4, cr3, cr2 (saved)
802 r0 (not saved; cannot be base reg)
803 r9 (not saved; best for TImode)
804 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
805 r3 (not saved; return value register)
806 r31 - r13 (saved; order given to save least number)
807 r12 (not saved; if used for DImode or DFmode would use r13)
808 mq (not saved; best to use it if we can)
809 ctr (not saved; when we have the choice ctr is better)
811 cr5, r1, r2, ap, xer (fixed)
812 v0 - v1 (not saved or used for anything)
813 v13 - v3 (not saved; incoming vector arg registers)
814 v2 (not saved; incoming vector arg reg; return value)
815 v19 - v14 (not saved or used for anything)
816 v31 - v20 (saved; order given to save least number)
818 spe_acc, spefscr (fixed)
823 #define MAYBE_R2_AVAILABLE
824 #define MAYBE_R2_FIXED 2,
826 #define MAYBE_R2_AVAILABLE 2,
827 #define MAYBE_R2_FIXED
830 #define REG_ALLOC_ORDER \
832 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
834 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
835 50, 49, 48, 47, 46, \
836 75, 74, 69, 68, 72, 71, 70, \
837 0, MAYBE_R2_AVAILABLE \
838 9, 11, 10, 8, 7, 6, 5, 4, \
840 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
841 18, 17, 16, 15, 14, 13, 12, \
843 73, 1, MAYBE_R2_FIXED 67, 76, \
844 /* AltiVec registers. */ \
846 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
848 96, 95, 94, 93, 92, 91, \
849 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
854 /* True if register is floating-point. */
855 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
857 /* True if register is a condition register. */
858 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
860 /* True if register is a condition register, but not cr0. */
861 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
863 /* True if register is an integer register. */
864 #define INT_REGNO_P(N) \
865 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
867 /* SPE SIMD registers are just the GPRs. */
868 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
870 /* PAIRED SIMD registers are just the FPRs. */
871 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
873 /* True if register is the XER register. */
874 #define XER_REGNO_P(N) ((N) == XER_REGNO)
876 /* True if register is an AltiVec register. */
877 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
879 /* Return number of consecutive hard regs needed starting at reg REGNO
880 to hold something of mode MODE. */
882 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
884 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
885 ((TARGET_32BIT && TARGET_POWERPC64 \
886 && (GET_MODE_SIZE (MODE) > 4) \
887 && INT_REGNO_P (REGNO)) ? 1 : 0)
889 #define ALTIVEC_VECTOR_MODE(MODE) \
890 ((MODE) == V16QImode \
891 || (MODE) == V8HImode \
892 || (MODE) == V4SFmode \
893 || (MODE) == V4SImode)
895 #define SPE_VECTOR_MODE(MODE) \
896 ((MODE) == V4HImode \
897 || (MODE) == V2SFmode \
898 || (MODE) == V1DImode \
899 || (MODE) == V2SImode)
901 #define PAIRED_VECTOR_MODE(MODE) \
904 #define UNITS_PER_SIMD_WORD(MODE) \
905 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
906 : (TARGET_SPE ? UNITS_PER_SPE_WORD : (TARGET_PAIRED_FLOAT ? \
907 UNITS_PER_PAIRED_WORD : UNITS_PER_WORD)))
909 /* Value is TRUE if hard register REGNO can hold a value of
910 machine-mode MODE. */
911 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
912 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
914 /* Value is 1 if it is a good idea to tie two pseudo registers
915 when one has mode MODE1 and one has mode MODE2.
916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
917 for any hard reg, then this must be 0 for correct output. */
918 #define MODES_TIEABLE_P(MODE1, MODE2) \
919 (SCALAR_FLOAT_MODE_P (MODE1) \
920 ? SCALAR_FLOAT_MODE_P (MODE2) \
921 : SCALAR_FLOAT_MODE_P (MODE2) \
922 ? SCALAR_FLOAT_MODE_P (MODE1) \
923 : GET_MODE_CLASS (MODE1) == MODE_CC \
924 ? GET_MODE_CLASS (MODE2) == MODE_CC \
925 : GET_MODE_CLASS (MODE2) == MODE_CC \
926 ? GET_MODE_CLASS (MODE1) == MODE_CC \
927 : SPE_VECTOR_MODE (MODE1) \
928 ? SPE_VECTOR_MODE (MODE2) \
929 : SPE_VECTOR_MODE (MODE2) \
930 ? SPE_VECTOR_MODE (MODE1) \
931 : ALTIVEC_VECTOR_MODE (MODE1) \
932 ? ALTIVEC_VECTOR_MODE (MODE2) \
933 : ALTIVEC_VECTOR_MODE (MODE2) \
934 ? ALTIVEC_VECTOR_MODE (MODE1) \
937 /* Post-reload, we can't use any new AltiVec registers, as we already
938 emitted the vrsave mask. */
940 #define HARD_REGNO_RENAME_OK(SRC, DST) \
941 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
943 /* A C expression returning the cost of moving data from a register of class
944 CLASS1 to one of CLASS2. */
946 #define REGISTER_MOVE_COST rs6000_register_move_cost
948 /* A C expressions returning the cost of moving data of MODE from a register to
951 #define MEMORY_MOVE_COST rs6000_memory_move_cost
953 /* Specify the cost of a branch insn; roughly the number of extra insns that
954 should be added to avoid a branch.
956 Set this to 3 on the RS/6000 since that is roughly the average cost of an
957 unscheduled conditional branch. */
959 #define BRANCH_COST 3
961 /* Override BRANCH_COST heuristic which empirically produces worse
962 performance for removing short circuiting from the logical ops. */
964 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
966 /* A fixed register used at epilogue generation to address SPE registers
967 with negative offsets. The 64-bit load/store instructions on the SPE
968 only take positive offsets (and small ones at that), so we need to
969 reserve a register for consing up negative offsets. */
971 #define FIXED_SCRATCH 0
973 /* Define this macro to change register usage conditional on target
976 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
978 /* Specify the registers used for certain standard purposes.
979 The values of these macros are register numbers. */
981 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
982 /* #define PC_REGNUM */
984 /* Register to use for pushing function arguments. */
985 #define STACK_POINTER_REGNUM 1
987 /* Base register for access to local variables of the function. */
988 #define HARD_FRAME_POINTER_REGNUM 31
990 /* Base register for access to local variables of the function. */
991 #define FRAME_POINTER_REGNUM 113
993 /* Value should be nonzero if functions must have frame pointers.
994 Zero means the frame pointer need not be set up (and parms
995 may be accessed via the stack pointer) in functions that seem suitable.
996 This is computed in `reload', in reload1.c. */
997 #define FRAME_POINTER_REQUIRED 0
999 /* Base register for access to arguments of the function. */
1000 #define ARG_POINTER_REGNUM 67
1002 /* Place to put static chain when calling a function that requires it. */
1003 #define STATIC_CHAIN_REGNUM 11
1006 /* Define the classes of registers for register constraints in the
1007 machine description. Also define ranges of constants.
1009 One of the classes must always be named ALL_REGS and include all hard regs.
1010 If there is more than one class, another class must be named NO_REGS
1011 and contain no registers.
1013 The name GENERAL_REGS must be the name of a class (or an alias for
1014 another name such as ALL_REGS). This is the class of registers
1015 that is allowed by "g" or "r" in a register constraint.
1016 Also, registers outside this class are allocated only when
1017 instructions express preferences for them.
1019 The classes must be numbered in nondecreasing order; that is,
1020 a larger-numbered class must never be contained completely
1021 in a smaller-numbered class.
1023 For any two classes, it is very desirable that there be another
1024 class that represents their union. */
1026 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1027 and condition registers, plus three special registers, MQ, CTR, and the
1028 link register. AltiVec adds a vector register class.
1030 However, r0 is special in that it cannot be used as a base register.
1031 So make a class for registers valid as base registers.
1033 Also, cr0 is the only condition code register that can be used in
1034 arithmetic insns, so make a separate class for it. */
1062 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1064 /* Give names of register classes as strings for dump file. */
1066 #define REG_CLASS_NAMES \
1077 "NON_SPECIAL_REGS", \
1081 "LINK_OR_CTR_REGS", \
1083 "SPEC_OR_GEN_REGS", \
1091 /* Define which registers fit in which classes.
1092 This is an initializer for a vector of HARD_REG_SET
1093 of length N_REG_CLASSES. */
1095 #define REG_CLASS_CONTENTS \
1097 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1098 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1099 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1100 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1101 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1102 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1103 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1104 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1105 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1106 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1107 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1108 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1109 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1110 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1111 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1112 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1113 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1114 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1115 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1116 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1117 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1120 /* The same information, inverted:
1121 Return the class number of the smallest class containing
1122 reg number REGNO. This could be a conditional expression
1123 or could index an array. */
1125 #define REGNO_REG_CLASS(REGNO) \
1126 ((REGNO) == 0 ? GENERAL_REGS \
1127 : (REGNO) < 32 ? BASE_REGS \
1128 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1129 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1130 : (REGNO) == CR0_REGNO ? CR0_REGS \
1131 : CR_REGNO_P (REGNO) ? CR_REGS \
1132 : (REGNO) == MQ_REGNO ? MQ_REGS \
1133 : (REGNO) == LR_REGNO ? LINK_REGS \
1134 : (REGNO) == CTR_REGNO ? CTR_REGS \
1135 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1136 : (REGNO) == XER_REGNO ? XER_REGS \
1137 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1138 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1139 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1140 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1141 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1144 /* The class value for index registers, and the one for base regs. */
1145 #define INDEX_REG_CLASS GENERAL_REGS
1146 #define BASE_REG_CLASS BASE_REGS
1148 /* Given an rtx X being reloaded into a reg required to be
1149 in class CLASS, return the class of reg to actually use.
1150 In general this is just CLASS; but on some machines
1151 in some cases it is preferable to use a more restrictive class.
1153 On the RS/6000, we have to return NO_REGS when we want to reload a
1154 floating-point CONST_DOUBLE to force it to be copied to memory.
1156 We also don't want to reload integer values into floating-point
1157 registers if we can at all help it. In fact, this can
1158 cause reload to die, if it tries to generate a reload of CTR
1159 into a FP register and discovers it doesn't have the memory location
1162 ??? Would it be a good idea to have reload do the converse, that is
1163 try to reload floating modes into FP registers if possible?
1166 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1168 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1170 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1171 && (CLASS) == NON_SPECIAL_REGS) \
1175 /* Return the register class of a scratch register needed to copy IN into
1176 or out of a register in CLASS in MODE. If it can be done directly,
1177 NO_REGS is returned. */
1179 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1180 rs6000_secondary_reload_class (CLASS, MODE, IN)
1182 /* If we are copying between FP or AltiVec registers and anything
1183 else, we need a memory location. The exception is when we are
1184 targeting ppc64 and the move to/from fpr to gpr instructions
1187 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1188 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1189 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1190 || ((MODE != DFmode) \
1191 && (MODE != DDmode) \
1192 && (MODE != DImode)))) \
1193 || ((CLASS2) == FLOAT_REGS \
1194 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1195 || ((MODE != DFmode) \
1196 && (MODE != DDmode) \
1197 && (MODE != DImode)))) \
1198 || (CLASS1) == ALTIVEC_REGS \
1199 || (CLASS2) == ALTIVEC_REGS))
1201 /* For cpus that cannot load/store SDmode values from the 64-bit
1202 FP registers without using a full 64-bit load/store, we need
1203 to allocate a full 64-bit stack slot for them. */
1205 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1206 rs6000_secondary_memory_needed_rtx (MODE)
1208 /* Return the maximum number of consecutive registers
1209 needed to represent mode MODE in a register of class CLASS.
1211 On RS/6000, this is the size of MODE in words,
1212 except in the FP regs, where a single reg is enough for two words. */
1213 #define CLASS_MAX_NREGS(CLASS, MODE) \
1214 (((CLASS) == FLOAT_REGS) \
1215 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1216 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS \
1217 && (MODE) == DFmode) \
1219 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1221 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1223 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1224 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1225 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1226 || TARGET_IEEEQUAD) \
1227 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1228 : (((TARGET_E500_DOUBLE \
1229 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
1230 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
1231 || (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
1232 || (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
1233 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1235 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1236 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
1238 /* Stack layout; function entry, exit and calling. */
1240 /* Enumeration to give which calling sequence to use. */
1243 ABI_AIX, /* IBM's AIX */
1244 ABI_V4, /* System V.4/eabi */
1245 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1248 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1250 /* Define this if pushing a word on the stack
1251 makes the stack pointer a smaller address. */
1252 #define STACK_GROWS_DOWNWARD
1254 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1255 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1257 /* Define this to nonzero if the nominal address of the stack frame
1258 is at the high-address end of the local variables;
1259 that is, each additional local variable allocated
1260 goes at a more negative offset in the frame.
1262 On the RS/6000, we grow upwards, from the area after the outgoing
1264 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1266 /* Size of the outgoing register save area */
1267 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1268 || DEFAULT_ABI == ABI_DARWIN) \
1269 ? (TARGET_64BIT ? 64 : 32) \
1272 /* Size of the fixed area on the stack */
1273 #define RS6000_SAVE_AREA \
1274 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1275 << (TARGET_64BIT ? 1 : 0))
1277 /* MEM representing address to save the TOC register */
1278 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1279 plus_constant (stack_pointer_rtx, \
1280 (TARGET_32BIT ? 20 : 40)))
1282 /* Align an address */
1283 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1285 /* Offset within stack frame to start allocating local variables at.
1286 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1287 first local allocated. Otherwise, it is the offset to the BEGINNING
1288 of the first local allocated.
1290 On the RS/6000, the frame pointer is the same as the stack pointer,
1291 except for dynamic allocations. So we start after the fixed area and
1292 outgoing parameter area. */
1294 #define STARTING_FRAME_OFFSET \
1295 (FRAME_GROWS_DOWNWARD \
1297 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1298 TARGET_ALTIVEC ? 16 : 8) \
1299 + RS6000_SAVE_AREA))
1301 /* Offset from the stack pointer register to an item dynamically
1302 allocated on the stack, e.g., by `alloca'.
1304 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1305 length of the outgoing arguments. The default is correct for most
1306 machines. See `function.c' for details. */
1307 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1308 (RS6000_ALIGN (crtl->outgoing_args_size, \
1309 TARGET_ALTIVEC ? 16 : 8) \
1310 + (STACK_POINTER_OFFSET))
1312 /* If we generate an insn to push BYTES bytes,
1313 this says how many the stack pointer really advances by.
1314 On RS/6000, don't define this because there are no push insns. */
1315 /* #define PUSH_ROUNDING(BYTES) */
1317 /* Offset of first parameter from the argument pointer register value.
1318 On the RS/6000, we define the argument pointer to the start of the fixed
1320 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1322 /* Offset from the argument pointer register value to the top of
1323 stack. This is different from FIRST_PARM_OFFSET because of the
1324 register save area. */
1325 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1327 /* Define this if stack space is still allocated for a parameter passed
1328 in a register. The value is the number of bytes allocated to this
1330 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1332 /* Define this if the above stack space is to be considered part of the
1333 space allocated by the caller. */
1334 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1336 /* This is the difference between the logical top of stack and the actual sp.
1338 For the RS/6000, sp points past the fixed area. */
1339 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1341 /* Define this if the maximum size of all the outgoing args is to be
1342 accumulated and pushed during the prologue. The amount can be
1343 found in the variable crtl->outgoing_args_size. */
1344 #define ACCUMULATE_OUTGOING_ARGS 1
1346 /* Value is the number of bytes of arguments automatically
1347 popped when returning from a subroutine call.
1348 FUNDECL is the declaration node of the function (as a tree),
1349 FUNTYPE is the data type of the function (as a tree),
1350 or for a library call it is an identifier node for the subroutine name.
1351 SIZE is the number of bytes of arguments passed on the stack. */
1353 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1355 /* Define how to find the value returned by a function.
1356 VALTYPE is the data type of the value (as a tree).
1357 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1358 otherwise, FUNC is 0. */
1360 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1362 /* Define how to find the value returned by a library function
1363 assuming the value has mode MODE. */
1365 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1367 /* DRAFT_V4_STRUCT_RET defaults off. */
1368 #define DRAFT_V4_STRUCT_RET 0
1370 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1371 #define DEFAULT_PCC_STRUCT_RETURN 0
1373 /* Mode of stack savearea.
1374 FUNCTION is VOIDmode because calling convention maintains SP.
1375 BLOCK needs Pmode for SP.
1376 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1377 #define STACK_SAVEAREA_MODE(LEVEL) \
1378 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1379 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1381 /* Minimum and maximum general purpose registers used to hold arguments. */
1382 #define GP_ARG_MIN_REG 3
1383 #define GP_ARG_MAX_REG 10
1384 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1386 /* Minimum and maximum floating point registers used to hold arguments. */
1387 #define FP_ARG_MIN_REG 33
1388 #define FP_ARG_AIX_MAX_REG 45
1389 #define FP_ARG_V4_MAX_REG 40
1390 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1391 || DEFAULT_ABI == ABI_DARWIN) \
1392 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1393 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1395 /* Minimum and maximum AltiVec registers used to hold arguments. */
1396 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1397 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1398 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1400 /* Return registers */
1401 #define GP_ARG_RETURN GP_ARG_MIN_REG
1402 #define FP_ARG_RETURN FP_ARG_MIN_REG
1403 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1405 /* Flags for the call/call_value rtl operations set up by function_arg */
1406 #define CALL_NORMAL 0x00000000 /* no special processing */
1407 /* Bits in 0x00000001 are unused. */
1408 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1409 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1410 #define CALL_LONG 0x00000008 /* always call indirect */
1411 #define CALL_LIBCALL 0x00000010 /* libcall */
1413 /* We don't have prologue and epilogue functions to save/restore
1414 everything for most ABIs. */
1415 #define WORLD_SAVE_P(INFO) 0
1417 /* 1 if N is a possible register number for a function value
1418 as seen by the caller.
1420 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1421 #define FUNCTION_VALUE_REGNO_P(N) \
1422 ((N) == GP_ARG_RETURN \
1423 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1424 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1426 /* 1 if N is a possible register number for function argument passing.
1427 On RS/6000, these are r3-r10 and fp1-fp13.
1428 On AltiVec, v2 - v13 are used for passing vectors. */
1429 #define FUNCTION_ARG_REGNO_P(N) \
1430 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1431 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1432 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1433 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1434 && TARGET_HARD_FLOAT && TARGET_FPRS))
1436 /* Define a data type for recording info about an argument list
1437 during the scan of that argument list. This data type should
1438 hold all necessary information about the function itself
1439 and about the args processed so far, enough to enable macros
1440 such as FUNCTION_ARG to determine where the next arg should go.
1442 On the RS/6000, this is a structure. The first element is the number of
1443 total argument words, the second is used to store the next
1444 floating-point register number, and the third says how many more args we
1445 have prototype types for.
1447 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1448 the next available GP register, `fregno' is the next available FP
1449 register, and `words' is the number of words used on the stack.
1451 The varargs/stdarg support requires that this structure's size
1452 be a multiple of sizeof(int). */
1454 typedef struct rs6000_args
1456 int words; /* # words used for passing GP registers */
1457 int fregno; /* next available FP register */
1458 int vregno; /* next available AltiVec register */
1459 int nargs_prototype; /* # args left in the current prototype */
1460 int prototype; /* Whether a prototype was defined */
1461 int stdarg; /* Whether function is a stdarg function. */
1462 int call_cookie; /* Do special things for this call */
1463 int sysv_gregno; /* next available GP register */
1464 int intoffset; /* running offset in struct (darwin64) */
1465 int use_stack; /* any part of struct on stack (darwin64) */
1466 int named; /* false for varargs params */
1469 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1470 for a call to a function whose data type is FNTYPE.
1471 For a library call, FNTYPE is 0. */
1473 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1474 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1476 /* Similar, but when scanning the definition of a procedure. We always
1477 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1479 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1480 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1482 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1484 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1485 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1487 /* Update the data in CUM to advance over an argument
1488 of mode MODE and data type TYPE.
1489 (TYPE is null for libcalls where that information may not be available.) */
1491 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1492 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1494 /* Determine where to put an argument to a function.
1495 Value is zero to push the argument on the stack,
1496 or a hard register in which to store the argument.
1498 MODE is the argument's machine mode.
1499 TYPE is the data type of the argument (as a tree).
1500 This is null for libcalls where that information may
1502 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1503 the preceding args and about the function being called.
1504 NAMED is nonzero if this argument is a named parameter
1505 (otherwise it is an extra parameter matching an ellipsis).
1507 On RS/6000 the first eight words of non-FP are normally in registers
1508 and the rest are pushed. The first 13 FP args are in registers.
1510 If this is floating-point and no prototype is specified, we use
1511 both an FP and integer register (or possibly FP reg and stack). Library
1512 functions (when TYPE is zero) always have the proper types for args,
1513 so we can pass the FP value just in one register. emit_library_function
1514 doesn't support EXPR_LIST anyway. */
1516 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1517 function_arg (&CUM, MODE, TYPE, NAMED)
1519 /* If defined, a C expression which determines whether, and in which
1520 direction, to pad out an argument with extra space. The value
1521 should be of type `enum direction': either `upward' to pad above
1522 the argument, `downward' to pad below, or `none' to inhibit
1525 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1527 /* If defined, a C expression that gives the alignment boundary, in bits,
1528 of an argument with the specified mode and type. If it is not defined,
1529 PARM_BOUNDARY is used for all arguments. */
1531 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1532 function_arg_boundary (MODE, TYPE)
1534 #define PAD_VARARGS_DOWN \
1535 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1537 /* Output assembler code to FILE to increment profiler label # LABELNO
1538 for profiling a function entry. */
1540 #define FUNCTION_PROFILER(FILE, LABELNO) \
1541 output_function_profiler ((FILE), (LABELNO));
1543 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1544 the stack pointer does not matter. No definition is equivalent to
1547 On the RS/6000, this is nonzero because we can restore the stack from
1548 its backpointer, which we maintain. */
1549 #define EXIT_IGNORE_STACK 1
1551 /* Define this macro as a C expression that is nonzero for registers
1552 that are used by the epilogue or the return' pattern. The stack
1553 and frame pointer registers are already be assumed to be used as
1556 #define EPILOGUE_USES(REGNO) \
1557 ((reload_completed && (REGNO) == LR_REGNO) \
1558 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1559 || (crtl->calls_eh_return \
1564 /* TRAMPOLINE_TEMPLATE deleted */
1566 /* Length in units of the trampoline for entering a nested function. */
1568 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1570 /* Emit RTL insns to initialize the variable parts of a trampoline.
1571 FNADDR is an RTX for the address of the function's pure code.
1572 CXT is an RTX for the static chain value for the function. */
1574 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1575 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1577 /* Definitions for __builtin_return_address and __builtin_frame_address.
1578 __builtin_return_address (0) should give link register (65), enable
1580 /* This should be uncommented, so that the link register is used, but
1581 currently this would result in unmatched insns and spilling fixed
1582 registers so we'll leave it for another day. When these problems are
1583 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1585 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1587 /* Number of bytes into the frame return addresses can be found. See
1588 rs6000_stack_info in rs6000.c for more information on how the different
1589 abi's store the return address. */
1590 #define RETURN_ADDRESS_OFFSET \
1591 ((DEFAULT_ABI == ABI_AIX \
1592 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1593 (DEFAULT_ABI == ABI_V4) ? 4 : \
1594 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1596 /* The current return address is in link register (65). The return address
1597 of anything farther back is accessed normally at an offset of 8 from the
1599 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1600 (rs6000_return_addr (COUNT, FRAME))
1603 /* Definitions for register eliminations.
1605 We have two registers that can be eliminated on the RS/6000. First, the
1606 frame pointer register can often be eliminated in favor of the stack
1607 pointer register. Secondly, the argument pointer register can always be
1608 eliminated; it is replaced with either the stack or frame pointer.
1610 In addition, we use the elimination mechanism to see if r30 is needed
1611 Initially we assume that it isn't. If it is, we spill it. This is done
1612 by making it an eliminable register. We replace it with itself so that
1613 if it isn't needed, then existing uses won't be modified. */
1615 /* This is an array of structures. Each structure initializes one pair
1616 of eliminable registers. The "from" register number is given first,
1617 followed by "to". Eliminations of the same "from" register are listed
1618 in order of preference. */
1619 #define ELIMINABLE_REGS \
1620 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1621 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1622 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1623 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1624 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1625 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1627 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1628 Frame pointer elimination is automatically handled.
1630 For the RS/6000, if frame pointer elimination is being done, we would like
1631 to convert ap into fp, not sp.
1633 We need r30 if -mminimal-toc was specified, and there are constant pool
1636 #define CAN_ELIMINATE(FROM, TO) \
1637 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1638 ? ! frame_pointer_needed \
1639 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1640 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1643 /* Define the offset between two registers, one to be eliminated, and the other
1644 its replacement, at the start of a routine. */
1645 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1646 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1648 /* Addressing modes, and classification of registers for them. */
1650 #define HAVE_PRE_DECREMENT 1
1651 #define HAVE_PRE_INCREMENT 1
1652 #define HAVE_PRE_MODIFY_DISP 1
1653 #define HAVE_PRE_MODIFY_REG 1
1655 /* Macros to check register numbers against specific register classes. */
1657 /* These assume that REGNO is a hard or pseudo reg number.
1658 They give nonzero only if REGNO is a hard reg of the suitable class
1659 or a pseudo reg currently allocated to a suitable hard reg.
1660 Since they use reg_renumber, they are safe only once reg_renumber
1661 has been allocated, which happens in local-alloc.c. */
1663 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1664 ((REGNO) < FIRST_PSEUDO_REGISTER \
1665 ? (REGNO) <= 31 || (REGNO) == 67 \
1666 || (REGNO) == FRAME_POINTER_REGNUM \
1667 : (reg_renumber[REGNO] >= 0 \
1668 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1669 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1671 #define REGNO_OK_FOR_BASE_P(REGNO) \
1672 ((REGNO) < FIRST_PSEUDO_REGISTER \
1673 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1674 || (REGNO) == FRAME_POINTER_REGNUM \
1675 : (reg_renumber[REGNO] > 0 \
1676 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1677 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1679 /* Maximum number of registers that can appear in a valid memory address. */
1681 #define MAX_REGS_PER_ADDRESS 2
1683 /* Recognize any constant value that is a valid address. */
1685 #define CONSTANT_ADDRESS_P(X) \
1686 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1687 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1688 || GET_CODE (X) == HIGH)
1690 /* Nonzero if the constant value X is a legitimate general operand.
1691 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1693 On the RS/6000, all integer constants are acceptable, most won't be valid
1694 for particular insns, though. Only easy FP constants are
1697 #define LEGITIMATE_CONSTANT_P(X) \
1698 (((GET_CODE (X) != CONST_DOUBLE \
1699 && GET_CODE (X) != CONST_VECTOR) \
1700 || GET_MODE (X) == VOIDmode \
1701 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1702 || easy_fp_constant (X, GET_MODE (X)) \
1703 || easy_vector_constant (X, GET_MODE (X))) \
1704 && !rs6000_tls_referenced_p (X))
1706 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1707 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1708 && EASY_VECTOR_15((n) >> 1) \
1711 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1712 and check its validity for a certain class.
1713 We have two alternate definitions for each of them.
1714 The usual definition accepts all pseudo regs; the other rejects
1715 them unless they have been allocated suitable hard regs.
1716 The symbol REG_OK_STRICT causes the latter definition to be used.
1718 Most source files want to accept pseudo regs in the hope that
1719 they will get allocated to the class that the insn wants them to be in.
1720 Source files for reload pass need to be strict.
1721 After reload, it makes no difference, since pseudo regs have
1722 been eliminated by then. */
1724 #ifdef REG_OK_STRICT
1725 # define REG_OK_STRICT_FLAG 1
1727 # define REG_OK_STRICT_FLAG 0
1730 /* Nonzero if X is a hard reg that can be used as an index
1731 or if it is a pseudo reg in the non-strict case. */
1732 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1733 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1734 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1736 /* Nonzero if X is a hard reg that can be used as a base reg
1737 or if it is a pseudo reg in the non-strict case. */
1738 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1739 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1740 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1742 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1743 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1745 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1746 that is a valid memory address for an instruction.
1747 The MODE argument is the machine mode for the MEM expression
1748 that wants to use this address.
1750 On the RS/6000, there are four valid addresses: a SYMBOL_REF that
1751 refers to a constant pool entry of an address (or the sum of it
1752 plus a constant), a short (16-bit signed) constant plus a register,
1753 the sum of two registers, or a register indirect, possibly with an
1754 auto-increment. For DFmode, DDmode and DImode with a constant plus
1755 register, we must ensure that both words are addressable or PowerPC64
1756 with offset word aligned.
1758 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
1759 32-bit DImode, TImode), indexed addressing cannot be used because
1760 adjacent memory cells are accessed by adding word-sized offsets
1761 during assembly output. */
1763 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1764 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1768 /* Try machine-dependent ways of modifying an illegitimate address
1769 to be legitimate. If we find one, return the new, valid address.
1770 This macro is used in only one place: `memory_address' in explow.c.
1772 OLDX is the address as it was before break_out_memory_refs was called.
1773 In some cases it is useful to look at this to decide what needs to be done.
1775 MODE and WIN are passed so that this macro can use
1776 GO_IF_LEGITIMATE_ADDRESS.
1778 It is always safe for this macro to do nothing. It exists to recognize
1779 opportunities to optimize the output.
1781 On RS/6000, first check for the sum of a register with a constant
1782 integer that is out of range. If so, generate code to add the
1783 constant with the low-order 16 bits masked to the register and force
1784 this result into another register (this can be done with `cau').
1785 Then generate an address of REG+(CONST&0xffff), allowing for the
1786 possibility of bit 16 being a one.
1788 Then check for the sum of a register and something not constant, try to
1789 load the other things into a register and return the sum. */
1791 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1792 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1793 if (result != NULL_RTX) \
1800 /* Try a machine-dependent way of reloading an illegitimate address
1801 operand. If we find one, push the reload and jump to WIN. This
1802 macro is used in only one place: `find_reloads_address' in reload.c.
1804 Implemented on rs6000 by rs6000_legitimize_reload_address.
1805 Note that (X) is evaluated twice; this is safe in current usage. */
1807 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1810 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1811 (int)(TYPE), (IND_LEVELS), &win); \
1816 /* Go to LABEL if ADDR (a legitimate address expression)
1817 has an effect that depends on the machine mode it is used for. */
1819 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1821 if (rs6000_mode_dependent_address (ADDR)) \
1825 /* The register number of the register used to address a table of
1826 static data addresses in memory. In some cases this register is
1827 defined by a processor's "application binary interface" (ABI).
1828 When this macro is defined, RTL is generated for this register
1829 once, as with the stack pointer and frame pointer registers. If
1830 this macro is not defined, it is up to the machine-dependent files
1831 to allocate such a register (if necessary). */
1833 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1834 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1836 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1838 /* Define this macro if the register defined by
1839 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1840 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1842 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1844 /* A C expression that is nonzero if X is a legitimate immediate
1845 operand on the target machine when generating position independent
1846 code. You can assume that X satisfies `CONSTANT_P', so you need
1847 not check this. You can also assume FLAG_PIC is true, so you need
1848 not check it either. You need not define this macro if all
1849 constants (including `SYMBOL_REF') can be immediate operands when
1850 generating position independent code. */
1852 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1854 /* Define this if some processing needs to be done immediately before
1855 emitting code for an insn. */
1857 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1859 /* Specify the machine mode that this machine uses
1860 for the index in the tablejump instruction. */
1861 #define CASE_VECTOR_MODE SImode
1863 /* Define as C expression which evaluates to nonzero if the tablejump
1864 instruction expects the table to contain offsets from the address of the
1866 Do not define this if the table should contain absolute addresses. */
1867 #define CASE_VECTOR_PC_RELATIVE 1
1869 /* Define this as 1 if `char' should by default be signed; else as 0. */
1870 #define DEFAULT_SIGNED_CHAR 0
1872 /* This flag, if defined, says the same insns that convert to a signed fixnum
1873 also convert validly to an unsigned one. */
1875 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1877 /* An integer expression for the size in bits of the largest integer machine
1878 mode that should actually be used. */
1880 /* Allow pairs of registers to be used, which is the intent of the default. */
1881 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1883 /* Max number of bytes we can move from memory to memory
1884 in one reasonably fast instruction. */
1885 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1886 #define MAX_MOVE_MAX 8
1888 /* Nonzero if access to memory by bytes is no faster than for words.
1889 Also nonzero if doing byte operations (specifically shifts) in registers
1891 #define SLOW_BYTE_ACCESS 1
1893 /* Define if operations between registers always perform the operation
1894 on the full register even if a narrower mode is specified. */
1895 #define WORD_REGISTER_OPERATIONS
1897 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1898 will either zero-extend or sign-extend. The value of this macro should
1899 be the code that says which one of the two operations is implicitly
1900 done, UNKNOWN if none. */
1901 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1903 /* Define if loading short immediate values into registers sign extends. */
1904 #define SHORT_IMMEDIATES_SIGN_EXTEND
1906 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1907 is done just by pretending it is already truncated. */
1908 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1910 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1911 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1912 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1914 /* The CTZ patterns return -1 for input of zero. */
1915 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1917 /* Specify the machine mode that pointers have.
1918 After generation of rtl, the compiler makes no further distinction
1919 between pointers and any other objects of this machine mode. */
1920 #define Pmode (TARGET_32BIT ? SImode : DImode)
1922 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1923 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1925 /* Mode of a function address in a call instruction (for indexing purposes).
1926 Doesn't matter on RS/6000. */
1927 #define FUNCTION_MODE SImode
1929 /* Define this if addresses of constant functions
1930 shouldn't be put through pseudo regs where they can be cse'd.
1931 Desirable on machines where ordinary constants are expensive
1932 but a CALL with constant address is cheap. */
1933 #define NO_FUNCTION_CSE
1935 /* Define this to be nonzero if shift instructions ignore all but the low-order
1938 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1939 have been dropped from the PowerPC architecture. */
1941 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1943 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1944 should be adjusted to reflect any required changes. This macro is used when
1945 there is some systematic length adjustment required that would be difficult
1946 to express in the length attribute. */
1948 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1950 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1951 COMPARE, return the mode to be used for the comparison. For
1952 floating-point, CCFPmode should be used. CCUNSmode should be used
1953 for unsigned comparisons. CCEQmode should be used when we are
1954 doing an inequality comparison on the result of a
1955 comparison. CCmode should be used in all other cases. */
1957 #define SELECT_CC_MODE(OP,X,Y) \
1958 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1959 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1960 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1961 ? CCEQmode : CCmode))
1963 /* Can the condition code MODE be safely reversed? This is safe in
1964 all cases on this port, because at present it doesn't use the
1965 trapping FP comparisons (fcmpo). */
1966 #define REVERSIBLE_CC_MODE(MODE) 1
1968 /* Given a condition code and a mode, return the inverse condition. */
1969 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1971 /* Define the information needed to generate branch and scc insns. This is
1972 stored from the compare operation. */
1974 extern GTY(()) rtx rs6000_compare_op0;
1975 extern GTY(()) rtx rs6000_compare_op1;
1976 extern int rs6000_compare_fp_p;
1978 /* Control the assembler format that we output. */
1980 /* A C string constant describing how to begin a comment in the target
1981 assembler language. The compiler assumes that the comment will end at
1982 the end of the line. */
1983 #define ASM_COMMENT_START " #"
1985 /* Flag to say the TOC is initialized */
1986 extern int toc_initialized;
1988 /* Macro to output a special constant pool entry. Go to WIN if we output
1989 it. Otherwise, it is written the usual way.
1991 On the RS/6000, toc entries are handled this way. */
1993 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1994 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1996 output_toc (FILE, X, LABELNO, MODE); \
2001 #ifdef HAVE_GAS_WEAK
2002 #define RS6000_WEAK 1
2004 #define RS6000_WEAK 0
2008 /* Used in lieu of ASM_WEAKEN_LABEL. */
2009 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2012 fputs ("\t.weak\t", (FILE)); \
2013 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2014 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2015 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2018 fputs ("[DS]", (FILE)); \
2019 fputs ("\n\t.weak\t.", (FILE)); \
2020 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2022 fputc ('\n', (FILE)); \
2025 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2026 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2027 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2029 fputs ("\t.set\t.", (FILE)); \
2030 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2031 fputs (",.", (FILE)); \
2032 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2033 fputc ('\n', (FILE)); \
2040 #if HAVE_GAS_WEAKREF
2041 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2044 fputs ("\t.weakref\t", (FILE)); \
2045 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2046 fputs (", ", (FILE)); \
2047 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2048 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2049 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2051 fputs ("\n\t.weakref\t.", (FILE)); \
2052 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2053 fputs (", .", (FILE)); \
2054 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2056 fputc ('\n', (FILE)); \
2060 /* This implements the `alias' attribute. */
2061 #undef ASM_OUTPUT_DEF_FROM_DECLS
2062 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2065 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2066 const char *name = IDENTIFIER_POINTER (TARGET); \
2067 if (TREE_CODE (DECL) == FUNCTION_DECL \
2068 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2070 if (TREE_PUBLIC (DECL)) \
2072 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2074 fputs ("\t.globl\t.", FILE); \
2075 RS6000_OUTPUT_BASENAME (FILE, alias); \
2076 putc ('\n', FILE); \
2079 else if (TARGET_XCOFF) \
2081 fputs ("\t.lglobl\t.", FILE); \
2082 RS6000_OUTPUT_BASENAME (FILE, alias); \
2083 putc ('\n', FILE); \
2085 fputs ("\t.set\t.", FILE); \
2086 RS6000_OUTPUT_BASENAME (FILE, alias); \
2087 fputs (",.", FILE); \
2088 RS6000_OUTPUT_BASENAME (FILE, name); \
2089 fputc ('\n', FILE); \
2091 ASM_OUTPUT_DEF (FILE, alias, name); \
2095 #define TARGET_ASM_FILE_START rs6000_file_start
2097 /* Output to assembler file text saying following lines
2098 may contain character constants, extra white space, comments, etc. */
2100 #define ASM_APP_ON ""
2102 /* Output to assembler file text saying following lines
2103 no longer contain unusual constructs. */
2105 #define ASM_APP_OFF ""
2107 /* How to refer to registers in assembler output.
2108 This sequence is indexed by compiler's hard-register-number (see above). */
2110 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2112 #define REGISTER_NAMES \
2114 &rs6000_reg_names[ 0][0], /* r0 */ \
2115 &rs6000_reg_names[ 1][0], /* r1 */ \
2116 &rs6000_reg_names[ 2][0], /* r2 */ \
2117 &rs6000_reg_names[ 3][0], /* r3 */ \
2118 &rs6000_reg_names[ 4][0], /* r4 */ \
2119 &rs6000_reg_names[ 5][0], /* r5 */ \
2120 &rs6000_reg_names[ 6][0], /* r6 */ \
2121 &rs6000_reg_names[ 7][0], /* r7 */ \
2122 &rs6000_reg_names[ 8][0], /* r8 */ \
2123 &rs6000_reg_names[ 9][0], /* r9 */ \
2124 &rs6000_reg_names[10][0], /* r10 */ \
2125 &rs6000_reg_names[11][0], /* r11 */ \
2126 &rs6000_reg_names[12][0], /* r12 */ \
2127 &rs6000_reg_names[13][0], /* r13 */ \
2128 &rs6000_reg_names[14][0], /* r14 */ \
2129 &rs6000_reg_names[15][0], /* r15 */ \
2130 &rs6000_reg_names[16][0], /* r16 */ \
2131 &rs6000_reg_names[17][0], /* r17 */ \
2132 &rs6000_reg_names[18][0], /* r18 */ \
2133 &rs6000_reg_names[19][0], /* r19 */ \
2134 &rs6000_reg_names[20][0], /* r20 */ \
2135 &rs6000_reg_names[21][0], /* r21 */ \
2136 &rs6000_reg_names[22][0], /* r22 */ \
2137 &rs6000_reg_names[23][0], /* r23 */ \
2138 &rs6000_reg_names[24][0], /* r24 */ \
2139 &rs6000_reg_names[25][0], /* r25 */ \
2140 &rs6000_reg_names[26][0], /* r26 */ \
2141 &rs6000_reg_names[27][0], /* r27 */ \
2142 &rs6000_reg_names[28][0], /* r28 */ \
2143 &rs6000_reg_names[29][0], /* r29 */ \
2144 &rs6000_reg_names[30][0], /* r30 */ \
2145 &rs6000_reg_names[31][0], /* r31 */ \
2147 &rs6000_reg_names[32][0], /* fr0 */ \
2148 &rs6000_reg_names[33][0], /* fr1 */ \
2149 &rs6000_reg_names[34][0], /* fr2 */ \
2150 &rs6000_reg_names[35][0], /* fr3 */ \
2151 &rs6000_reg_names[36][0], /* fr4 */ \
2152 &rs6000_reg_names[37][0], /* fr5 */ \
2153 &rs6000_reg_names[38][0], /* fr6 */ \
2154 &rs6000_reg_names[39][0], /* fr7 */ \
2155 &rs6000_reg_names[40][0], /* fr8 */ \
2156 &rs6000_reg_names[41][0], /* fr9 */ \
2157 &rs6000_reg_names[42][0], /* fr10 */ \
2158 &rs6000_reg_names[43][0], /* fr11 */ \
2159 &rs6000_reg_names[44][0], /* fr12 */ \
2160 &rs6000_reg_names[45][0], /* fr13 */ \
2161 &rs6000_reg_names[46][0], /* fr14 */ \
2162 &rs6000_reg_names[47][0], /* fr15 */ \
2163 &rs6000_reg_names[48][0], /* fr16 */ \
2164 &rs6000_reg_names[49][0], /* fr17 */ \
2165 &rs6000_reg_names[50][0], /* fr18 */ \
2166 &rs6000_reg_names[51][0], /* fr19 */ \
2167 &rs6000_reg_names[52][0], /* fr20 */ \
2168 &rs6000_reg_names[53][0], /* fr21 */ \
2169 &rs6000_reg_names[54][0], /* fr22 */ \
2170 &rs6000_reg_names[55][0], /* fr23 */ \
2171 &rs6000_reg_names[56][0], /* fr24 */ \
2172 &rs6000_reg_names[57][0], /* fr25 */ \
2173 &rs6000_reg_names[58][0], /* fr26 */ \
2174 &rs6000_reg_names[59][0], /* fr27 */ \
2175 &rs6000_reg_names[60][0], /* fr28 */ \
2176 &rs6000_reg_names[61][0], /* fr29 */ \
2177 &rs6000_reg_names[62][0], /* fr30 */ \
2178 &rs6000_reg_names[63][0], /* fr31 */ \
2180 &rs6000_reg_names[64][0], /* mq */ \
2181 &rs6000_reg_names[65][0], /* lr */ \
2182 &rs6000_reg_names[66][0], /* ctr */ \
2183 &rs6000_reg_names[67][0], /* ap */ \
2185 &rs6000_reg_names[68][0], /* cr0 */ \
2186 &rs6000_reg_names[69][0], /* cr1 */ \
2187 &rs6000_reg_names[70][0], /* cr2 */ \
2188 &rs6000_reg_names[71][0], /* cr3 */ \
2189 &rs6000_reg_names[72][0], /* cr4 */ \
2190 &rs6000_reg_names[73][0], /* cr5 */ \
2191 &rs6000_reg_names[74][0], /* cr6 */ \
2192 &rs6000_reg_names[75][0], /* cr7 */ \
2194 &rs6000_reg_names[76][0], /* xer */ \
2196 &rs6000_reg_names[77][0], /* v0 */ \
2197 &rs6000_reg_names[78][0], /* v1 */ \
2198 &rs6000_reg_names[79][0], /* v2 */ \
2199 &rs6000_reg_names[80][0], /* v3 */ \
2200 &rs6000_reg_names[81][0], /* v4 */ \
2201 &rs6000_reg_names[82][0], /* v5 */ \
2202 &rs6000_reg_names[83][0], /* v6 */ \
2203 &rs6000_reg_names[84][0], /* v7 */ \
2204 &rs6000_reg_names[85][0], /* v8 */ \
2205 &rs6000_reg_names[86][0], /* v9 */ \
2206 &rs6000_reg_names[87][0], /* v10 */ \
2207 &rs6000_reg_names[88][0], /* v11 */ \
2208 &rs6000_reg_names[89][0], /* v12 */ \
2209 &rs6000_reg_names[90][0], /* v13 */ \
2210 &rs6000_reg_names[91][0], /* v14 */ \
2211 &rs6000_reg_names[92][0], /* v15 */ \
2212 &rs6000_reg_names[93][0], /* v16 */ \
2213 &rs6000_reg_names[94][0], /* v17 */ \
2214 &rs6000_reg_names[95][0], /* v18 */ \
2215 &rs6000_reg_names[96][0], /* v19 */ \
2216 &rs6000_reg_names[97][0], /* v20 */ \
2217 &rs6000_reg_names[98][0], /* v21 */ \
2218 &rs6000_reg_names[99][0], /* v22 */ \
2219 &rs6000_reg_names[100][0], /* v23 */ \
2220 &rs6000_reg_names[101][0], /* v24 */ \
2221 &rs6000_reg_names[102][0], /* v25 */ \
2222 &rs6000_reg_names[103][0], /* v26 */ \
2223 &rs6000_reg_names[104][0], /* v27 */ \
2224 &rs6000_reg_names[105][0], /* v28 */ \
2225 &rs6000_reg_names[106][0], /* v29 */ \
2226 &rs6000_reg_names[107][0], /* v30 */ \
2227 &rs6000_reg_names[108][0], /* v31 */ \
2228 &rs6000_reg_names[109][0], /* vrsave */ \
2229 &rs6000_reg_names[110][0], /* vscr */ \
2230 &rs6000_reg_names[111][0], /* spe_acc */ \
2231 &rs6000_reg_names[112][0], /* spefscr */ \
2232 &rs6000_reg_names[113][0], /* sfp */ \
2235 /* Table of additional register names to use in user input. */
2237 #define ADDITIONAL_REGISTER_NAMES \
2238 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2239 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2240 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2241 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2242 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2243 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2244 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2245 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2246 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2247 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2248 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2249 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2250 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2251 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2252 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2253 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2254 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2255 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2256 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2257 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2258 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2259 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2260 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2261 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2262 {"vrsave", 109}, {"vscr", 110}, \
2263 {"spe_acc", 111}, {"spefscr", 112}, \
2264 /* no additional names for: mq, lr, ctr, ap */ \
2265 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2266 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2267 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2269 /* Text to write out after a CALL that may be replaced by glue code by
2270 the loader. This depends on the AIX version. */
2271 #define RS6000_CALL_GLUE "cror 31,31,31"
2273 /* This is how to output an element of a case-vector that is relative. */
2275 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2276 do { char buf[100]; \
2277 fputs ("\t.long ", FILE); \
2278 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2279 assemble_name (FILE, buf); \
2281 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2282 assemble_name (FILE, buf); \
2283 putc ('\n', FILE); \
2286 /* This is how to output an assembler line
2287 that says to advance the location counter
2288 to a multiple of 2**LOG bytes. */
2290 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2292 fprintf (FILE, "\t.align %d\n", (LOG))
2294 /* Pick up the return address upon entry to a procedure. Used for
2295 dwarf2 unwind information. This also enables the table driven
2298 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2299 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2301 /* Describe how we implement __builtin_eh_return. */
2302 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2303 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2305 /* Print operand X (an rtx) in assembler syntax to file FILE.
2306 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2307 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2309 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2311 /* Define which CODE values are valid. */
2313 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2314 ((CODE) == '.' || (CODE) == '&')
2316 /* Print a memory address as an operand to reference that memory location. */
2318 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2320 /* uncomment for disabling the corresponding default options */
2321 /* #define MACHINE_no_sched_interblock */
2322 /* #define MACHINE_no_sched_speculative */
2323 /* #define MACHINE_no_sched_speculative_load */
2325 /* General flags. */
2326 extern int flag_pic;
2327 extern int optimize;
2328 extern int flag_expensive_optimizations;
2329 extern int frame_pointer_needed;
2331 enum rs6000_builtins
2333 /* AltiVec builtins. */
2334 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2335 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2336 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2337 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2338 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2339 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2340 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2341 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2342 ALTIVEC_BUILTIN_VADDUBM,
2343 ALTIVEC_BUILTIN_VADDUHM,
2344 ALTIVEC_BUILTIN_VADDUWM,
2345 ALTIVEC_BUILTIN_VADDFP,
2346 ALTIVEC_BUILTIN_VADDCUW,
2347 ALTIVEC_BUILTIN_VADDUBS,
2348 ALTIVEC_BUILTIN_VADDSBS,
2349 ALTIVEC_BUILTIN_VADDUHS,
2350 ALTIVEC_BUILTIN_VADDSHS,
2351 ALTIVEC_BUILTIN_VADDUWS,
2352 ALTIVEC_BUILTIN_VADDSWS,
2353 ALTIVEC_BUILTIN_VAND,
2354 ALTIVEC_BUILTIN_VANDC,
2355 ALTIVEC_BUILTIN_VAVGUB,
2356 ALTIVEC_BUILTIN_VAVGSB,
2357 ALTIVEC_BUILTIN_VAVGUH,
2358 ALTIVEC_BUILTIN_VAVGSH,
2359 ALTIVEC_BUILTIN_VAVGUW,
2360 ALTIVEC_BUILTIN_VAVGSW,
2361 ALTIVEC_BUILTIN_VCFUX,
2362 ALTIVEC_BUILTIN_VCFSX,
2363 ALTIVEC_BUILTIN_VCTSXS,
2364 ALTIVEC_BUILTIN_VCTUXS,
2365 ALTIVEC_BUILTIN_VCMPBFP,
2366 ALTIVEC_BUILTIN_VCMPEQUB,
2367 ALTIVEC_BUILTIN_VCMPEQUH,
2368 ALTIVEC_BUILTIN_VCMPEQUW,
2369 ALTIVEC_BUILTIN_VCMPEQFP,
2370 ALTIVEC_BUILTIN_VCMPGEFP,
2371 ALTIVEC_BUILTIN_VCMPGTUB,
2372 ALTIVEC_BUILTIN_VCMPGTSB,
2373 ALTIVEC_BUILTIN_VCMPGTUH,
2374 ALTIVEC_BUILTIN_VCMPGTSH,
2375 ALTIVEC_BUILTIN_VCMPGTUW,
2376 ALTIVEC_BUILTIN_VCMPGTSW,
2377 ALTIVEC_BUILTIN_VCMPGTFP,
2378 ALTIVEC_BUILTIN_VEXPTEFP,
2379 ALTIVEC_BUILTIN_VLOGEFP,
2380 ALTIVEC_BUILTIN_VMADDFP,
2381 ALTIVEC_BUILTIN_VMAXUB,
2382 ALTIVEC_BUILTIN_VMAXSB,
2383 ALTIVEC_BUILTIN_VMAXUH,
2384 ALTIVEC_BUILTIN_VMAXSH,
2385 ALTIVEC_BUILTIN_VMAXUW,
2386 ALTIVEC_BUILTIN_VMAXSW,
2387 ALTIVEC_BUILTIN_VMAXFP,
2388 ALTIVEC_BUILTIN_VMHADDSHS,
2389 ALTIVEC_BUILTIN_VMHRADDSHS,
2390 ALTIVEC_BUILTIN_VMLADDUHM,
2391 ALTIVEC_BUILTIN_VMRGHB,
2392 ALTIVEC_BUILTIN_VMRGHH,
2393 ALTIVEC_BUILTIN_VMRGHW,
2394 ALTIVEC_BUILTIN_VMRGLB,
2395 ALTIVEC_BUILTIN_VMRGLH,
2396 ALTIVEC_BUILTIN_VMRGLW,
2397 ALTIVEC_BUILTIN_VMSUMUBM,
2398 ALTIVEC_BUILTIN_VMSUMMBM,
2399 ALTIVEC_BUILTIN_VMSUMUHM,
2400 ALTIVEC_BUILTIN_VMSUMSHM,
2401 ALTIVEC_BUILTIN_VMSUMUHS,
2402 ALTIVEC_BUILTIN_VMSUMSHS,
2403 ALTIVEC_BUILTIN_VMINUB,
2404 ALTIVEC_BUILTIN_VMINSB,
2405 ALTIVEC_BUILTIN_VMINUH,
2406 ALTIVEC_BUILTIN_VMINSH,
2407 ALTIVEC_BUILTIN_VMINUW,
2408 ALTIVEC_BUILTIN_VMINSW,
2409 ALTIVEC_BUILTIN_VMINFP,
2410 ALTIVEC_BUILTIN_VMULEUB,
2411 ALTIVEC_BUILTIN_VMULESB,
2412 ALTIVEC_BUILTIN_VMULEUH,
2413 ALTIVEC_BUILTIN_VMULESH,
2414 ALTIVEC_BUILTIN_VMULOUB,
2415 ALTIVEC_BUILTIN_VMULOSB,
2416 ALTIVEC_BUILTIN_VMULOUH,
2417 ALTIVEC_BUILTIN_VMULOSH,
2418 ALTIVEC_BUILTIN_VNMSUBFP,
2419 ALTIVEC_BUILTIN_VNOR,
2420 ALTIVEC_BUILTIN_VOR,
2421 ALTIVEC_BUILTIN_VSEL_4SI,
2422 ALTIVEC_BUILTIN_VSEL_4SF,
2423 ALTIVEC_BUILTIN_VSEL_8HI,
2424 ALTIVEC_BUILTIN_VSEL_16QI,
2425 ALTIVEC_BUILTIN_VPERM_4SI,
2426 ALTIVEC_BUILTIN_VPERM_4SF,
2427 ALTIVEC_BUILTIN_VPERM_8HI,
2428 ALTIVEC_BUILTIN_VPERM_16QI,
2429 ALTIVEC_BUILTIN_VPKUHUM,
2430 ALTIVEC_BUILTIN_VPKUWUM,
2431 ALTIVEC_BUILTIN_VPKPX,
2432 ALTIVEC_BUILTIN_VPKUHSS,
2433 ALTIVEC_BUILTIN_VPKSHSS,
2434 ALTIVEC_BUILTIN_VPKUWSS,
2435 ALTIVEC_BUILTIN_VPKSWSS,
2436 ALTIVEC_BUILTIN_VPKUHUS,
2437 ALTIVEC_BUILTIN_VPKSHUS,
2438 ALTIVEC_BUILTIN_VPKUWUS,
2439 ALTIVEC_BUILTIN_VPKSWUS,
2440 ALTIVEC_BUILTIN_VREFP,
2441 ALTIVEC_BUILTIN_VRFIM,
2442 ALTIVEC_BUILTIN_VRFIN,
2443 ALTIVEC_BUILTIN_VRFIP,
2444 ALTIVEC_BUILTIN_VRFIZ,
2445 ALTIVEC_BUILTIN_VRLB,
2446 ALTIVEC_BUILTIN_VRLH,
2447 ALTIVEC_BUILTIN_VRLW,
2448 ALTIVEC_BUILTIN_VRSQRTEFP,
2449 ALTIVEC_BUILTIN_VSLB,
2450 ALTIVEC_BUILTIN_VSLH,
2451 ALTIVEC_BUILTIN_VSLW,
2452 ALTIVEC_BUILTIN_VSL,
2453 ALTIVEC_BUILTIN_VSLO,
2454 ALTIVEC_BUILTIN_VSPLTB,
2455 ALTIVEC_BUILTIN_VSPLTH,
2456 ALTIVEC_BUILTIN_VSPLTW,
2457 ALTIVEC_BUILTIN_VSPLTISB,
2458 ALTIVEC_BUILTIN_VSPLTISH,
2459 ALTIVEC_BUILTIN_VSPLTISW,
2460 ALTIVEC_BUILTIN_VSRB,
2461 ALTIVEC_BUILTIN_VSRH,
2462 ALTIVEC_BUILTIN_VSRW,
2463 ALTIVEC_BUILTIN_VSRAB,
2464 ALTIVEC_BUILTIN_VSRAH,
2465 ALTIVEC_BUILTIN_VSRAW,
2466 ALTIVEC_BUILTIN_VSR,
2467 ALTIVEC_BUILTIN_VSRO,
2468 ALTIVEC_BUILTIN_VSUBUBM,
2469 ALTIVEC_BUILTIN_VSUBUHM,
2470 ALTIVEC_BUILTIN_VSUBUWM,
2471 ALTIVEC_BUILTIN_VSUBFP,
2472 ALTIVEC_BUILTIN_VSUBCUW,
2473 ALTIVEC_BUILTIN_VSUBUBS,
2474 ALTIVEC_BUILTIN_VSUBSBS,
2475 ALTIVEC_BUILTIN_VSUBUHS,
2476 ALTIVEC_BUILTIN_VSUBSHS,
2477 ALTIVEC_BUILTIN_VSUBUWS,
2478 ALTIVEC_BUILTIN_VSUBSWS,
2479 ALTIVEC_BUILTIN_VSUM4UBS,
2480 ALTIVEC_BUILTIN_VSUM4SBS,
2481 ALTIVEC_BUILTIN_VSUM4SHS,
2482 ALTIVEC_BUILTIN_VSUM2SWS,
2483 ALTIVEC_BUILTIN_VSUMSWS,
2484 ALTIVEC_BUILTIN_VXOR,
2485 ALTIVEC_BUILTIN_VSLDOI_16QI,
2486 ALTIVEC_BUILTIN_VSLDOI_8HI,
2487 ALTIVEC_BUILTIN_VSLDOI_4SI,
2488 ALTIVEC_BUILTIN_VSLDOI_4SF,
2489 ALTIVEC_BUILTIN_VUPKHSB,
2490 ALTIVEC_BUILTIN_VUPKHPX,
2491 ALTIVEC_BUILTIN_VUPKHSH,
2492 ALTIVEC_BUILTIN_VUPKLSB,
2493 ALTIVEC_BUILTIN_VUPKLPX,
2494 ALTIVEC_BUILTIN_VUPKLSH,
2495 ALTIVEC_BUILTIN_MTVSCR,
2496 ALTIVEC_BUILTIN_MFVSCR,
2497 ALTIVEC_BUILTIN_DSSALL,
2498 ALTIVEC_BUILTIN_DSS,
2499 ALTIVEC_BUILTIN_LVSL,
2500 ALTIVEC_BUILTIN_LVSR,
2501 ALTIVEC_BUILTIN_DSTT,
2502 ALTIVEC_BUILTIN_DSTST,
2503 ALTIVEC_BUILTIN_DSTSTT,
2504 ALTIVEC_BUILTIN_DST,
2505 ALTIVEC_BUILTIN_LVEBX,
2506 ALTIVEC_BUILTIN_LVEHX,
2507 ALTIVEC_BUILTIN_LVEWX,
2508 ALTIVEC_BUILTIN_LVXL,
2509 ALTIVEC_BUILTIN_LVX,
2510 ALTIVEC_BUILTIN_STVX,
2511 ALTIVEC_BUILTIN_STVEBX,
2512 ALTIVEC_BUILTIN_STVEHX,
2513 ALTIVEC_BUILTIN_STVEWX,
2514 ALTIVEC_BUILTIN_STVXL,
2515 ALTIVEC_BUILTIN_VCMPBFP_P,
2516 ALTIVEC_BUILTIN_VCMPEQFP_P,
2517 ALTIVEC_BUILTIN_VCMPEQUB_P,
2518 ALTIVEC_BUILTIN_VCMPEQUH_P,
2519 ALTIVEC_BUILTIN_VCMPEQUW_P,
2520 ALTIVEC_BUILTIN_VCMPGEFP_P,
2521 ALTIVEC_BUILTIN_VCMPGTFP_P,
2522 ALTIVEC_BUILTIN_VCMPGTSB_P,
2523 ALTIVEC_BUILTIN_VCMPGTSH_P,
2524 ALTIVEC_BUILTIN_VCMPGTSW_P,
2525 ALTIVEC_BUILTIN_VCMPGTUB_P,
2526 ALTIVEC_BUILTIN_VCMPGTUH_P,
2527 ALTIVEC_BUILTIN_VCMPGTUW_P,
2528 ALTIVEC_BUILTIN_ABSS_V4SI,
2529 ALTIVEC_BUILTIN_ABSS_V8HI,
2530 ALTIVEC_BUILTIN_ABSS_V16QI,
2531 ALTIVEC_BUILTIN_ABS_V4SI,
2532 ALTIVEC_BUILTIN_ABS_V4SF,
2533 ALTIVEC_BUILTIN_ABS_V8HI,
2534 ALTIVEC_BUILTIN_ABS_V16QI,
2535 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2536 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2537 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2538 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2539 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2540 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2541 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2542 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2543 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2544 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2545 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2546 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2547 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2548 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2550 /* Altivec overloaded builtins. */
2551 ALTIVEC_BUILTIN_VCMPEQ_P,
2552 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2553 ALTIVEC_BUILTIN_VCMPGT_P,
2554 ALTIVEC_BUILTIN_VCMPGE_P,
2555 ALTIVEC_BUILTIN_VEC_ABS,
2556 ALTIVEC_BUILTIN_VEC_ABSS,
2557 ALTIVEC_BUILTIN_VEC_ADD,
2558 ALTIVEC_BUILTIN_VEC_ADDC,
2559 ALTIVEC_BUILTIN_VEC_ADDS,
2560 ALTIVEC_BUILTIN_VEC_AND,
2561 ALTIVEC_BUILTIN_VEC_ANDC,
2562 ALTIVEC_BUILTIN_VEC_AVG,
2563 ALTIVEC_BUILTIN_VEC_CEIL,
2564 ALTIVEC_BUILTIN_VEC_CMPB,
2565 ALTIVEC_BUILTIN_VEC_CMPEQ,
2566 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2567 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2568 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2569 ALTIVEC_BUILTIN_VEC_CMPGE,
2570 ALTIVEC_BUILTIN_VEC_CMPGT,
2571 ALTIVEC_BUILTIN_VEC_CMPLE,
2572 ALTIVEC_BUILTIN_VEC_CMPLT,
2573 ALTIVEC_BUILTIN_VEC_CTF,
2574 ALTIVEC_BUILTIN_VEC_CTS,
2575 ALTIVEC_BUILTIN_VEC_CTU,
2576 ALTIVEC_BUILTIN_VEC_DST,
2577 ALTIVEC_BUILTIN_VEC_DSTST,
2578 ALTIVEC_BUILTIN_VEC_DSTSTT,
2579 ALTIVEC_BUILTIN_VEC_DSTT,
2580 ALTIVEC_BUILTIN_VEC_EXPTE,
2581 ALTIVEC_BUILTIN_VEC_FLOOR,
2582 ALTIVEC_BUILTIN_VEC_LD,
2583 ALTIVEC_BUILTIN_VEC_LDE,
2584 ALTIVEC_BUILTIN_VEC_LDL,
2585 ALTIVEC_BUILTIN_VEC_LOGE,
2586 ALTIVEC_BUILTIN_VEC_LVEBX,
2587 ALTIVEC_BUILTIN_VEC_LVEHX,
2588 ALTIVEC_BUILTIN_VEC_LVEWX,
2589 ALTIVEC_BUILTIN_VEC_LVSL,
2590 ALTIVEC_BUILTIN_VEC_LVSR,
2591 ALTIVEC_BUILTIN_VEC_MADD,
2592 ALTIVEC_BUILTIN_VEC_MADDS,
2593 ALTIVEC_BUILTIN_VEC_MAX,
2594 ALTIVEC_BUILTIN_VEC_MERGEH,
2595 ALTIVEC_BUILTIN_VEC_MERGEL,
2596 ALTIVEC_BUILTIN_VEC_MIN,
2597 ALTIVEC_BUILTIN_VEC_MLADD,
2598 ALTIVEC_BUILTIN_VEC_MPERM,
2599 ALTIVEC_BUILTIN_VEC_MRADDS,
2600 ALTIVEC_BUILTIN_VEC_MRGHB,
2601 ALTIVEC_BUILTIN_VEC_MRGHH,
2602 ALTIVEC_BUILTIN_VEC_MRGHW,
2603 ALTIVEC_BUILTIN_VEC_MRGLB,
2604 ALTIVEC_BUILTIN_VEC_MRGLH,
2605 ALTIVEC_BUILTIN_VEC_MRGLW,
2606 ALTIVEC_BUILTIN_VEC_MSUM,
2607 ALTIVEC_BUILTIN_VEC_MSUMS,
2608 ALTIVEC_BUILTIN_VEC_MTVSCR,
2609 ALTIVEC_BUILTIN_VEC_MULE,
2610 ALTIVEC_BUILTIN_VEC_MULO,
2611 ALTIVEC_BUILTIN_VEC_NMSUB,
2612 ALTIVEC_BUILTIN_VEC_NOR,
2613 ALTIVEC_BUILTIN_VEC_OR,
2614 ALTIVEC_BUILTIN_VEC_PACK,
2615 ALTIVEC_BUILTIN_VEC_PACKPX,
2616 ALTIVEC_BUILTIN_VEC_PACKS,
2617 ALTIVEC_BUILTIN_VEC_PACKSU,
2618 ALTIVEC_BUILTIN_VEC_PERM,
2619 ALTIVEC_BUILTIN_VEC_RE,
2620 ALTIVEC_BUILTIN_VEC_RL,
2621 ALTIVEC_BUILTIN_VEC_ROUND,
2622 ALTIVEC_BUILTIN_VEC_RSQRTE,
2623 ALTIVEC_BUILTIN_VEC_SEL,
2624 ALTIVEC_BUILTIN_VEC_SL,
2625 ALTIVEC_BUILTIN_VEC_SLD,
2626 ALTIVEC_BUILTIN_VEC_SLL,
2627 ALTIVEC_BUILTIN_VEC_SLO,
2628 ALTIVEC_BUILTIN_VEC_SPLAT,
2629 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2630 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2631 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2632 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2633 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2634 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2635 ALTIVEC_BUILTIN_VEC_SPLTB,
2636 ALTIVEC_BUILTIN_VEC_SPLTH,
2637 ALTIVEC_BUILTIN_VEC_SPLTW,
2638 ALTIVEC_BUILTIN_VEC_SR,
2639 ALTIVEC_BUILTIN_VEC_SRA,
2640 ALTIVEC_BUILTIN_VEC_SRL,
2641 ALTIVEC_BUILTIN_VEC_SRO,
2642 ALTIVEC_BUILTIN_VEC_ST,
2643 ALTIVEC_BUILTIN_VEC_STE,
2644 ALTIVEC_BUILTIN_VEC_STL,
2645 ALTIVEC_BUILTIN_VEC_STVEBX,
2646 ALTIVEC_BUILTIN_VEC_STVEHX,
2647 ALTIVEC_BUILTIN_VEC_STVEWX,
2648 ALTIVEC_BUILTIN_VEC_SUB,
2649 ALTIVEC_BUILTIN_VEC_SUBC,
2650 ALTIVEC_BUILTIN_VEC_SUBS,
2651 ALTIVEC_BUILTIN_VEC_SUM2S,
2652 ALTIVEC_BUILTIN_VEC_SUM4S,
2653 ALTIVEC_BUILTIN_VEC_SUMS,
2654 ALTIVEC_BUILTIN_VEC_TRUNC,
2655 ALTIVEC_BUILTIN_VEC_UNPACKH,
2656 ALTIVEC_BUILTIN_VEC_UNPACKL,
2657 ALTIVEC_BUILTIN_VEC_VADDFP,
2658 ALTIVEC_BUILTIN_VEC_VADDSBS,
2659 ALTIVEC_BUILTIN_VEC_VADDSHS,
2660 ALTIVEC_BUILTIN_VEC_VADDSWS,
2661 ALTIVEC_BUILTIN_VEC_VADDUBM,
2662 ALTIVEC_BUILTIN_VEC_VADDUBS,
2663 ALTIVEC_BUILTIN_VEC_VADDUHM,
2664 ALTIVEC_BUILTIN_VEC_VADDUHS,
2665 ALTIVEC_BUILTIN_VEC_VADDUWM,
2666 ALTIVEC_BUILTIN_VEC_VADDUWS,
2667 ALTIVEC_BUILTIN_VEC_VAVGSB,
2668 ALTIVEC_BUILTIN_VEC_VAVGSH,
2669 ALTIVEC_BUILTIN_VEC_VAVGSW,
2670 ALTIVEC_BUILTIN_VEC_VAVGUB,
2671 ALTIVEC_BUILTIN_VEC_VAVGUH,
2672 ALTIVEC_BUILTIN_VEC_VAVGUW,
2673 ALTIVEC_BUILTIN_VEC_VCFSX,
2674 ALTIVEC_BUILTIN_VEC_VCFUX,
2675 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2676 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2677 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2678 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2679 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2680 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2681 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2682 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2683 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2684 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2685 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2686 ALTIVEC_BUILTIN_VEC_VMAXFP,
2687 ALTIVEC_BUILTIN_VEC_VMAXSB,
2688 ALTIVEC_BUILTIN_VEC_VMAXSH,
2689 ALTIVEC_BUILTIN_VEC_VMAXSW,
2690 ALTIVEC_BUILTIN_VEC_VMAXUB,
2691 ALTIVEC_BUILTIN_VEC_VMAXUH,
2692 ALTIVEC_BUILTIN_VEC_VMAXUW,
2693 ALTIVEC_BUILTIN_VEC_VMINFP,
2694 ALTIVEC_BUILTIN_VEC_VMINSB,
2695 ALTIVEC_BUILTIN_VEC_VMINSH,
2696 ALTIVEC_BUILTIN_VEC_VMINSW,
2697 ALTIVEC_BUILTIN_VEC_VMINUB,
2698 ALTIVEC_BUILTIN_VEC_VMINUH,
2699 ALTIVEC_BUILTIN_VEC_VMINUW,
2700 ALTIVEC_BUILTIN_VEC_VMRGHB,
2701 ALTIVEC_BUILTIN_VEC_VMRGHH,
2702 ALTIVEC_BUILTIN_VEC_VMRGHW,
2703 ALTIVEC_BUILTIN_VEC_VMRGLB,
2704 ALTIVEC_BUILTIN_VEC_VMRGLH,
2705 ALTIVEC_BUILTIN_VEC_VMRGLW,
2706 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2707 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2708 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2709 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2710 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2711 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2712 ALTIVEC_BUILTIN_VEC_VMULESB,
2713 ALTIVEC_BUILTIN_VEC_VMULESH,
2714 ALTIVEC_BUILTIN_VEC_VMULEUB,
2715 ALTIVEC_BUILTIN_VEC_VMULEUH,
2716 ALTIVEC_BUILTIN_VEC_VMULOSB,
2717 ALTIVEC_BUILTIN_VEC_VMULOSH,
2718 ALTIVEC_BUILTIN_VEC_VMULOUB,
2719 ALTIVEC_BUILTIN_VEC_VMULOUH,
2720 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2721 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2722 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2723 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2724 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2725 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2726 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2727 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2728 ALTIVEC_BUILTIN_VEC_VRLB,
2729 ALTIVEC_BUILTIN_VEC_VRLH,
2730 ALTIVEC_BUILTIN_VEC_VRLW,
2731 ALTIVEC_BUILTIN_VEC_VSLB,
2732 ALTIVEC_BUILTIN_VEC_VSLH,
2733 ALTIVEC_BUILTIN_VEC_VSLW,
2734 ALTIVEC_BUILTIN_VEC_VSPLTB,
2735 ALTIVEC_BUILTIN_VEC_VSPLTH,
2736 ALTIVEC_BUILTIN_VEC_VSPLTW,
2737 ALTIVEC_BUILTIN_VEC_VSRAB,
2738 ALTIVEC_BUILTIN_VEC_VSRAH,
2739 ALTIVEC_BUILTIN_VEC_VSRAW,
2740 ALTIVEC_BUILTIN_VEC_VSRB,
2741 ALTIVEC_BUILTIN_VEC_VSRH,
2742 ALTIVEC_BUILTIN_VEC_VSRW,
2743 ALTIVEC_BUILTIN_VEC_VSUBFP,
2744 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2745 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2746 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2747 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2748 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2749 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2750 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2751 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2752 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2753 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2754 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2755 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2756 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2757 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2758 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2759 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2760 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2761 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2762 ALTIVEC_BUILTIN_VEC_XOR,
2763 ALTIVEC_BUILTIN_VEC_STEP,
2764 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP,
2770 SPE_BUILTIN_EVDIVWS,
2771 SPE_BUILTIN_EVDIVWU,
2773 SPE_BUILTIN_EVFSADD,
2774 SPE_BUILTIN_EVFSDIV,
2775 SPE_BUILTIN_EVFSMUL,
2776 SPE_BUILTIN_EVFSSUB,
2780 SPE_BUILTIN_EVLHHESPLATX,
2781 SPE_BUILTIN_EVLHHOSSPLATX,
2782 SPE_BUILTIN_EVLHHOUSPLATX,
2783 SPE_BUILTIN_EVLWHEX,
2784 SPE_BUILTIN_EVLWHOSX,
2785 SPE_BUILTIN_EVLWHOUX,
2786 SPE_BUILTIN_EVLWHSPLATX,
2787 SPE_BUILTIN_EVLWWSPLATX,
2788 SPE_BUILTIN_EVMERGEHI,
2789 SPE_BUILTIN_EVMERGEHILO,
2790 SPE_BUILTIN_EVMERGELO,
2791 SPE_BUILTIN_EVMERGELOHI,
2792 SPE_BUILTIN_EVMHEGSMFAA,
2793 SPE_BUILTIN_EVMHEGSMFAN,
2794 SPE_BUILTIN_EVMHEGSMIAA,
2795 SPE_BUILTIN_EVMHEGSMIAN,
2796 SPE_BUILTIN_EVMHEGUMIAA,
2797 SPE_BUILTIN_EVMHEGUMIAN,
2798 SPE_BUILTIN_EVMHESMF,
2799 SPE_BUILTIN_EVMHESMFA,
2800 SPE_BUILTIN_EVMHESMFAAW,
2801 SPE_BUILTIN_EVMHESMFANW,
2802 SPE_BUILTIN_EVMHESMI,
2803 SPE_BUILTIN_EVMHESMIA,
2804 SPE_BUILTIN_EVMHESMIAAW,
2805 SPE_BUILTIN_EVMHESMIANW,
2806 SPE_BUILTIN_EVMHESSF,
2807 SPE_BUILTIN_EVMHESSFA,
2808 SPE_BUILTIN_EVMHESSFAAW,
2809 SPE_BUILTIN_EVMHESSFANW,
2810 SPE_BUILTIN_EVMHESSIAAW,
2811 SPE_BUILTIN_EVMHESSIANW,
2812 SPE_BUILTIN_EVMHEUMI,
2813 SPE_BUILTIN_EVMHEUMIA,
2814 SPE_BUILTIN_EVMHEUMIAAW,
2815 SPE_BUILTIN_EVMHEUMIANW,
2816 SPE_BUILTIN_EVMHEUSIAAW,
2817 SPE_BUILTIN_EVMHEUSIANW,
2818 SPE_BUILTIN_EVMHOGSMFAA,
2819 SPE_BUILTIN_EVMHOGSMFAN,
2820 SPE_BUILTIN_EVMHOGSMIAA,
2821 SPE_BUILTIN_EVMHOGSMIAN,
2822 SPE_BUILTIN_EVMHOGUMIAA,
2823 SPE_BUILTIN_EVMHOGUMIAN,
2824 SPE_BUILTIN_EVMHOSMF,
2825 SPE_BUILTIN_EVMHOSMFA,
2826 SPE_BUILTIN_EVMHOSMFAAW,
2827 SPE_BUILTIN_EVMHOSMFANW,
2828 SPE_BUILTIN_EVMHOSMI,
2829 SPE_BUILTIN_EVMHOSMIA,
2830 SPE_BUILTIN_EVMHOSMIAAW,
2831 SPE_BUILTIN_EVMHOSMIANW,
2832 SPE_BUILTIN_EVMHOSSF,
2833 SPE_BUILTIN_EVMHOSSFA,
2834 SPE_BUILTIN_EVMHOSSFAAW,
2835 SPE_BUILTIN_EVMHOSSFANW,
2836 SPE_BUILTIN_EVMHOSSIAAW,
2837 SPE_BUILTIN_EVMHOSSIANW,
2838 SPE_BUILTIN_EVMHOUMI,
2839 SPE_BUILTIN_EVMHOUMIA,
2840 SPE_BUILTIN_EVMHOUMIAAW,
2841 SPE_BUILTIN_EVMHOUMIANW,
2842 SPE_BUILTIN_EVMHOUSIAAW,
2843 SPE_BUILTIN_EVMHOUSIANW,
2844 SPE_BUILTIN_EVMWHSMF,
2845 SPE_BUILTIN_EVMWHSMFA,
2846 SPE_BUILTIN_EVMWHSMI,
2847 SPE_BUILTIN_EVMWHSMIA,
2848 SPE_BUILTIN_EVMWHSSF,
2849 SPE_BUILTIN_EVMWHSSFA,
2850 SPE_BUILTIN_EVMWHUMI,
2851 SPE_BUILTIN_EVMWHUMIA,
2852 SPE_BUILTIN_EVMWLSMIAAW,
2853 SPE_BUILTIN_EVMWLSMIANW,
2854 SPE_BUILTIN_EVMWLSSIAAW,
2855 SPE_BUILTIN_EVMWLSSIANW,
2856 SPE_BUILTIN_EVMWLUMI,
2857 SPE_BUILTIN_EVMWLUMIA,
2858 SPE_BUILTIN_EVMWLUMIAAW,
2859 SPE_BUILTIN_EVMWLUMIANW,
2860 SPE_BUILTIN_EVMWLUSIAAW,
2861 SPE_BUILTIN_EVMWLUSIANW,
2862 SPE_BUILTIN_EVMWSMF,
2863 SPE_BUILTIN_EVMWSMFA,
2864 SPE_BUILTIN_EVMWSMFAA,
2865 SPE_BUILTIN_EVMWSMFAN,
2866 SPE_BUILTIN_EVMWSMI,
2867 SPE_BUILTIN_EVMWSMIA,
2868 SPE_BUILTIN_EVMWSMIAA,
2869 SPE_BUILTIN_EVMWSMIAN,
2870 SPE_BUILTIN_EVMWHSSFAA,
2871 SPE_BUILTIN_EVMWSSF,
2872 SPE_BUILTIN_EVMWSSFA,
2873 SPE_BUILTIN_EVMWSSFAA,
2874 SPE_BUILTIN_EVMWSSFAN,
2875 SPE_BUILTIN_EVMWUMI,
2876 SPE_BUILTIN_EVMWUMIA,
2877 SPE_BUILTIN_EVMWUMIAA,
2878 SPE_BUILTIN_EVMWUMIAN,
2887 SPE_BUILTIN_EVSTDDX,
2888 SPE_BUILTIN_EVSTDHX,
2889 SPE_BUILTIN_EVSTDWX,
2890 SPE_BUILTIN_EVSTWHEX,
2891 SPE_BUILTIN_EVSTWHOX,
2892 SPE_BUILTIN_EVSTWWEX,
2893 SPE_BUILTIN_EVSTWWOX,
2894 SPE_BUILTIN_EVSUBFW,
2897 SPE_BUILTIN_EVADDSMIAAW,
2898 SPE_BUILTIN_EVADDSSIAAW,
2899 SPE_BUILTIN_EVADDUMIAAW,
2900 SPE_BUILTIN_EVADDUSIAAW,
2901 SPE_BUILTIN_EVCNTLSW,
2902 SPE_BUILTIN_EVCNTLZW,
2903 SPE_BUILTIN_EVEXTSB,
2904 SPE_BUILTIN_EVEXTSH,
2905 SPE_BUILTIN_EVFSABS,
2906 SPE_BUILTIN_EVFSCFSF,
2907 SPE_BUILTIN_EVFSCFSI,
2908 SPE_BUILTIN_EVFSCFUF,
2909 SPE_BUILTIN_EVFSCFUI,
2910 SPE_BUILTIN_EVFSCTSF,
2911 SPE_BUILTIN_EVFSCTSI,
2912 SPE_BUILTIN_EVFSCTSIZ,
2913 SPE_BUILTIN_EVFSCTUF,
2914 SPE_BUILTIN_EVFSCTUI,
2915 SPE_BUILTIN_EVFSCTUIZ,
2916 SPE_BUILTIN_EVFSNABS,
2917 SPE_BUILTIN_EVFSNEG,
2921 SPE_BUILTIN_EVSUBFSMIAAW,
2922 SPE_BUILTIN_EVSUBFSSIAAW,
2923 SPE_BUILTIN_EVSUBFUMIAAW,
2924 SPE_BUILTIN_EVSUBFUSIAAW,
2925 SPE_BUILTIN_EVADDIW,
2929 SPE_BUILTIN_EVLHHESPLAT,
2930 SPE_BUILTIN_EVLHHOSSPLAT,
2931 SPE_BUILTIN_EVLHHOUSPLAT,
2933 SPE_BUILTIN_EVLWHOS,
2934 SPE_BUILTIN_EVLWHOU,
2935 SPE_BUILTIN_EVLWHSPLAT,
2936 SPE_BUILTIN_EVLWWSPLAT,
2939 SPE_BUILTIN_EVSRWIS,
2940 SPE_BUILTIN_EVSRWIU,
2944 SPE_BUILTIN_EVSTWHE,
2945 SPE_BUILTIN_EVSTWHO,
2946 SPE_BUILTIN_EVSTWWE,
2947 SPE_BUILTIN_EVSTWWO,
2948 SPE_BUILTIN_EVSUBIFW,
2951 SPE_BUILTIN_EVCMPEQ,
2952 SPE_BUILTIN_EVCMPGTS,
2953 SPE_BUILTIN_EVCMPGTU,
2954 SPE_BUILTIN_EVCMPLTS,
2955 SPE_BUILTIN_EVCMPLTU,
2956 SPE_BUILTIN_EVFSCMPEQ,
2957 SPE_BUILTIN_EVFSCMPGT,
2958 SPE_BUILTIN_EVFSCMPLT,
2959 SPE_BUILTIN_EVFSTSTEQ,
2960 SPE_BUILTIN_EVFSTSTGT,
2961 SPE_BUILTIN_EVFSTSTLT,
2963 /* EVSEL compares. */
2964 SPE_BUILTIN_EVSEL_CMPEQ,
2965 SPE_BUILTIN_EVSEL_CMPGTS,
2966 SPE_BUILTIN_EVSEL_CMPGTU,
2967 SPE_BUILTIN_EVSEL_CMPLTS,
2968 SPE_BUILTIN_EVSEL_CMPLTU,
2969 SPE_BUILTIN_EVSEL_FSCMPEQ,
2970 SPE_BUILTIN_EVSEL_FSCMPGT,
2971 SPE_BUILTIN_EVSEL_FSCMPLT,
2972 SPE_BUILTIN_EVSEL_FSTSTEQ,
2973 SPE_BUILTIN_EVSEL_FSTSTGT,
2974 SPE_BUILTIN_EVSEL_FSTSTLT,
2976 SPE_BUILTIN_EVSPLATFI,
2977 SPE_BUILTIN_EVSPLATI,
2978 SPE_BUILTIN_EVMWHSSMAA,
2979 SPE_BUILTIN_EVMWHSMFAA,
2980 SPE_BUILTIN_EVMWHSMIAA,
2981 SPE_BUILTIN_EVMWHUSIAA,
2982 SPE_BUILTIN_EVMWHUMIAA,
2983 SPE_BUILTIN_EVMWHSSFAN,
2984 SPE_BUILTIN_EVMWHSSIAN,
2985 SPE_BUILTIN_EVMWHSMFAN,
2986 SPE_BUILTIN_EVMWHSMIAN,
2987 SPE_BUILTIN_EVMWHUSIAN,
2988 SPE_BUILTIN_EVMWHUMIAN,
2989 SPE_BUILTIN_EVMWHGSSFAA,
2990 SPE_BUILTIN_EVMWHGSMFAA,
2991 SPE_BUILTIN_EVMWHGSMIAA,
2992 SPE_BUILTIN_EVMWHGUMIAA,
2993 SPE_BUILTIN_EVMWHGSSFAN,
2994 SPE_BUILTIN_EVMWHGSMFAN,
2995 SPE_BUILTIN_EVMWHGSMIAN,
2996 SPE_BUILTIN_EVMWHGUMIAN,
2997 SPE_BUILTIN_MTSPEFSCR,
2998 SPE_BUILTIN_MFSPEFSCR,
3001 /* PAIRED builtins. */
3002 PAIRED_BUILTIN_DIVV2SF3,
3003 PAIRED_BUILTIN_ABSV2SF2,
3004 PAIRED_BUILTIN_NEGV2SF2,
3005 PAIRED_BUILTIN_SQRTV2SF2,
3006 PAIRED_BUILTIN_ADDV2SF3,
3007 PAIRED_BUILTIN_SUBV2SF3,
3008 PAIRED_BUILTIN_RESV2SF2,
3009 PAIRED_BUILTIN_MULV2SF3,
3010 PAIRED_BUILTIN_MSUB,
3011 PAIRED_BUILTIN_MADD,
3012 PAIRED_BUILTIN_NMSUB,
3013 PAIRED_BUILTIN_NMADD,
3014 PAIRED_BUILTIN_NABSV2SF2,
3015 PAIRED_BUILTIN_SUM0,
3016 PAIRED_BUILTIN_SUM1,
3017 PAIRED_BUILTIN_MULS0,
3018 PAIRED_BUILTIN_MULS1,
3019 PAIRED_BUILTIN_MERGE00,
3020 PAIRED_BUILTIN_MERGE01,
3021 PAIRED_BUILTIN_MERGE10,
3022 PAIRED_BUILTIN_MERGE11,
3023 PAIRED_BUILTIN_MADDS0,
3024 PAIRED_BUILTIN_MADDS1,
3027 PAIRED_BUILTIN_SELV2SF4,
3028 PAIRED_BUILTIN_CMPU0,
3029 PAIRED_BUILTIN_CMPU1,
3031 RS6000_BUILTIN_RECIP,
3032 RS6000_BUILTIN_RECIPF,
3033 RS6000_BUILTIN_RSQRTF,
3035 RS6000_BUILTIN_COUNT
3038 enum rs6000_builtin_type_index
3040 RS6000_BTI_NOT_OPAQUE,
3041 RS6000_BTI_opaque_V2SI,
3042 RS6000_BTI_opaque_V2SF,
3043 RS6000_BTI_opaque_p_V2SI,
3044 RS6000_BTI_opaque_V4SI,
3052 RS6000_BTI_unsigned_V16QI,
3053 RS6000_BTI_unsigned_V8HI,
3054 RS6000_BTI_unsigned_V4SI,
3055 RS6000_BTI_bool_char, /* __bool char */
3056 RS6000_BTI_bool_short, /* __bool short */
3057 RS6000_BTI_bool_int, /* __bool int */
3058 RS6000_BTI_pixel, /* __pixel */
3059 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3060 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3061 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3062 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3063 RS6000_BTI_long, /* long_integer_type_node */
3064 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3065 RS6000_BTI_INTQI, /* intQI_type_node */
3066 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3067 RS6000_BTI_INTHI, /* intHI_type_node */
3068 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3069 RS6000_BTI_INTSI, /* intSI_type_node */
3070 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3071 RS6000_BTI_float, /* float_type_node */
3072 RS6000_BTI_void, /* void_type_node */
3077 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3078 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3079 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3080 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3081 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3082 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3083 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3084 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3085 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3086 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3087 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3088 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3089 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3090 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3091 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3092 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3093 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3094 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3095 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3096 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3097 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3098 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3100 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3101 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3102 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3103 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3104 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3105 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3106 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3107 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3108 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3109 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3111 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3112 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];