1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 #ifndef TARGET_PAIRED_FLOAT
60 #define TARGET_PAIRED_FLOAT 0
63 /* Common ASM definitions used by ASM_SPEC among the various targets
64 for handling -mcpu=xxx switches. */
65 #define ASM_CPU_SPEC \
67 %{mpower: %{!mpower2: -mpwr}} \
69 %{mpowerpc64*: -mppc64} \
70 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
71 %{mno-power: %{!mpowerpc*: -mcom}} \
72 %{!mno-power: %{!mpower*: %(asm_default)}}} \
73 %{mcpu=common: -mcom} \
74 %{mcpu=cell: -mcell} \
75 %{mcpu=power: -mpwr} \
76 %{mcpu=power2: -mpwrx} \
77 %{mcpu=power3: -mppc64} \
78 %{mcpu=power4: -mpower4} \
79 %{mcpu=power5: -mpower4} \
80 %{mcpu=power5+: -mpower4} \
81 %{mcpu=power6: -mpower4 -maltivec} \
82 %{mcpu=power6x: -mpower4 -maltivec} \
83 %{mcpu=powerpc: -mppc} \
85 %{mcpu=rios1: -mpwr} \
86 %{mcpu=rios2: -mpwrx} \
89 %{mcpu=rs64a: -mppc64} \
93 %{mcpu=405fp: -m405} \
95 %{mcpu=440fp: -m440} \
100 %{mcpu=603e: -mppc} \
101 %{mcpu=ec603e: -mppc} \
103 %{mcpu=604e: -mppc} \
104 %{mcpu=620: -mppc64} \
105 %{mcpu=630: -mppc64} \
109 %{mcpu=7400: -mppc -maltivec} \
110 %{mcpu=7450: -mppc -maltivec} \
111 %{mcpu=G4: -mppc -maltivec} \
116 %{mcpu=970: -mpower4 -maltivec} \
117 %{mcpu=G5: -mpower4 -maltivec} \
118 %{mcpu=8540: -me500} \
119 %{mcpu=8548: -me500} \
120 %{maltivec: -maltivec} \
123 #define CPP_DEFAULT_SPEC ""
125 #define ASM_DEFAULT_SPEC ""
127 /* This macro defines names of additional specifications to put in the specs
128 that can be used in various specifications like CC1_SPEC. Its definition
129 is an initializer with a subgrouping for each command option.
131 Each subgrouping contains a string constant, that defines the
132 specification name, and a string constant that used by the GCC driver
135 Do not define this macro if it does not need to do anything. */
137 #define SUBTARGET_EXTRA_SPECS
139 #define EXTRA_SPECS \
140 { "cpp_default", CPP_DEFAULT_SPEC }, \
141 { "asm_cpu", ASM_CPU_SPEC }, \
142 { "asm_default", ASM_DEFAULT_SPEC }, \
143 { "cc1_cpu", CC1_CPU_SPEC }, \
144 SUBTARGET_EXTRA_SPECS
146 /* -mcpu=native handling only makes sense with compiler running on
147 an PowerPC chip. If changing this condition, also change
148 the condition in driver-rs6000.c. */
149 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
150 /* In driver-rs6000.c. */
151 extern const char *host_detect_local_cpu (int argc, const char **argv);
152 #define EXTRA_SPEC_FUNCTIONS \
153 { "local_cpu_detect", host_detect_local_cpu },
154 #define HAVE_LOCAL_CPU_DETECT
158 #ifdef HAVE_LOCAL_CPU_DETECT
159 #define CC1_CPU_SPEC \
160 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
161 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
163 #define CC1_CPU_SPEC ""
167 /* Architecture type. */
169 /* Define TARGET_MFCRF if the target assembler does not support the
170 optional field operand for mfcr. */
172 #ifndef HAVE_AS_MFCRF
174 #define TARGET_MFCRF 0
177 /* Define TARGET_POPCNTB if the target assembler does not support the
178 popcount byte instruction. */
180 #ifndef HAVE_AS_POPCNTB
181 #undef TARGET_POPCNTB
182 #define TARGET_POPCNTB 0
185 /* Define TARGET_FPRND if the target assembler does not support the
186 fp rounding instructions. */
188 #ifndef HAVE_AS_FPRND
190 #define TARGET_FPRND 0
193 /* Define TARGET_CMPB if the target assembler does not support the
198 #define TARGET_CMPB 0
201 /* Define TARGET_MFPGPR if the target assembler does not support the
202 mffpr and mftgpr instructions. */
204 #ifndef HAVE_AS_MFPGPR
206 #define TARGET_MFPGPR 0
209 /* Define TARGET_DFP if the target assembler does not support decimal
210 floating point instructions. */
216 #ifndef TARGET_SECURE_PLT
217 #define TARGET_SECURE_PLT 0
220 #define TARGET_32BIT (! TARGET_64BIT)
223 #define HAVE_AS_TLS 0
226 /* Return 1 for a symbol ref for a thread-local storage symbol. */
227 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
228 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
231 /* For libgcc2 we make sure this is a compile time constant */
232 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
233 #undef TARGET_POWERPC64
234 #define TARGET_POWERPC64 1
236 #undef TARGET_POWERPC64
237 #define TARGET_POWERPC64 0
240 /* The option machinery will define this. */
243 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
245 /* Processor type. Order must match cpu attribute in MD file. */
271 extern enum processor_type rs6000_cpu;
273 /* Recast the processor type to the cpu attribute. */
274 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
276 /* Define generic processor types based upon current deployment. */
277 #define PROCESSOR_COMMON PROCESSOR_PPC601
278 #define PROCESSOR_POWER PROCESSOR_RIOS1
279 #define PROCESSOR_POWERPC PROCESSOR_PPC604
280 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
282 /* Define the default processor. This is overridden by other tm.h files. */
283 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
284 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
286 /* Specify the dialect of assembler to use. New mnemonics is dialect one
287 and the old mnemonics are dialect zero. */
288 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
290 /* Types of costly dependences. */
291 enum rs6000_dependence_cost
293 max_dep_latency = 1000,
296 true_store_to_load_dep_costly,
297 store_to_load_dep_costly
300 /* Types of nop insertion schemes in sched target hook sched_finish. */
301 enum rs6000_nop_insertion
303 sched_finish_regroup_exact = 1000,
304 sched_finish_pad_groups,
308 /* Dispatch group termination caused by an insn. */
309 enum group_termination
315 /* Support for a compile-time default CPU, et cetera. The rules are:
316 --with-cpu is ignored if -mcpu is specified.
317 --with-tune is ignored if -mtune is specified.
318 --with-float is ignored if -mhard-float or -msoft-float are
320 #define OPTION_DEFAULT_SPECS \
321 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
322 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
323 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
325 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
326 struct rs6000_cpu_select
334 extern struct rs6000_cpu_select rs6000_select[];
337 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
338 extern int rs6000_debug_stack; /* debug stack applications */
339 extern int rs6000_debug_arg; /* debug argument handling */
341 #define TARGET_DEBUG_STACK rs6000_debug_stack
342 #define TARGET_DEBUG_ARG rs6000_debug_arg
344 extern const char *rs6000_traceback_name; /* Type of traceback table. */
346 /* These are separate from target_flags because we've run out of bits
348 extern int rs6000_long_double_type_size;
349 extern int rs6000_ieeequad;
350 extern int rs6000_altivec_abi;
351 extern int rs6000_spe_abi;
352 extern int rs6000_float_gprs;
353 extern int rs6000_alignment_flags;
354 extern const char *rs6000_sched_insert_nops_str;
355 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
357 /* Alignment options for fields in structures for sub-targets following
359 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
360 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
362 Override the macro definitions when compiling libobjc to avoid undefined
363 reference to rs6000_alignment_flags due to library's use of GCC alignment
364 macros which use the macros below. */
366 #ifndef IN_TARGET_LIBS
367 #define MASK_ALIGN_POWER 0x00000000
368 #define MASK_ALIGN_NATURAL 0x00000001
369 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
371 #define TARGET_ALIGN_NATURAL 0
374 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
375 #define TARGET_IEEEQUAD rs6000_ieeequad
376 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
378 #define TARGET_SPE_ABI 0
380 #define TARGET_E500 0
381 #define TARGET_ISEL 0
382 #define TARGET_FPRS 1
383 #define TARGET_E500_SINGLE 0
384 #define TARGET_E500_DOUBLE 0
385 #define CHECK_E500_OPTIONS do { } while (0)
387 /* E500 processors only support plain "sync", not lwsync. */
388 #define TARGET_NO_LWSYNC TARGET_E500
390 /* Sometimes certain combinations of command options do not make sense
391 on a particular target machine. You can define a macro
392 `OVERRIDE_OPTIONS' to take account of this. This macro, if
393 defined, is executed once just after all the command options have
396 Do not use this macro to turn on various extra optimizations for
397 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
399 On the RS/6000 this is used to define the target cpu type. */
401 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
403 /* Define this to change the optimizations performed by default. */
404 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
406 /* Show we can debug even without a frame pointer. */
407 #define CAN_DEBUG_WITHOUT_FP
410 #define REGISTER_TARGET_PRAGMAS() do { \
411 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
412 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
415 /* Target #defines. */
416 #define TARGET_CPU_CPP_BUILTINS() \
417 rs6000_cpu_cpp_builtins (pfile)
419 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
420 we're compiling for. Some configurations may need to override it. */
421 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
424 if (BYTES_BIG_ENDIAN) \
426 builtin_define ("__BIG_ENDIAN__"); \
427 builtin_define ("_BIG_ENDIAN"); \
428 builtin_assert ("machine=bigendian"); \
432 builtin_define ("__LITTLE_ENDIAN__"); \
433 builtin_define ("_LITTLE_ENDIAN"); \
434 builtin_assert ("machine=littleendian"); \
439 /* Target machine storage layout. */
441 /* Define this macro if it is advisable to hold scalars in registers
442 in a wider mode than that declared by the program. In such cases,
443 the value is constrained to be within the bounds of the declared
444 type, but kept valid in the wider mode. The signedness of the
445 extension may differ from that of the type. */
447 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
448 if (GET_MODE_CLASS (MODE) == MODE_INT \
449 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
450 (MODE) = TARGET_32BIT ? SImode : DImode;
452 /* Define this if most significant bit is lowest numbered
453 in instructions that operate on numbered bit-fields. */
454 /* That is true on RS/6000. */
455 #define BITS_BIG_ENDIAN 1
457 /* Define this if most significant byte of a word is the lowest numbered. */
458 /* That is true on RS/6000. */
459 #define BYTES_BIG_ENDIAN 1
461 /* Define this if most significant word of a multiword number is lowest
464 For RS/6000 we can decide arbitrarily since there are no machine
465 instructions for them. Might as well be consistent with bits and bytes. */
466 #define WORDS_BIG_ENDIAN 1
468 #define MAX_BITS_PER_WORD 64
470 /* Width of a word, in units (bytes). */
471 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
473 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
475 #define MIN_UNITS_PER_WORD 4
477 #define UNITS_PER_FP_WORD 8
478 #define UNITS_PER_ALTIVEC_WORD 16
479 #define UNITS_PER_SPE_WORD 8
480 #define UNITS_PER_PAIRED_WORD 8
482 /* Type used for ptrdiff_t, as a string used in a declaration. */
483 #define PTRDIFF_TYPE "int"
485 /* Type used for size_t, as a string used in a declaration. */
486 #define SIZE_TYPE "long unsigned int"
488 /* Type used for wchar_t, as a string used in a declaration. */
489 #define WCHAR_TYPE "short unsigned int"
491 /* Width of wchar_t in bits. */
492 #define WCHAR_TYPE_SIZE 16
494 /* A C expression for the size in bits of the type `short' on the
495 target machine. If you don't define this, the default is half a
496 word. (If this would be less than one storage unit, it is
497 rounded up to one unit.) */
498 #define SHORT_TYPE_SIZE 16
500 /* A C expression for the size in bits of the type `int' on the
501 target machine. If you don't define this, the default is one
503 #define INT_TYPE_SIZE 32
505 /* A C expression for the size in bits of the type `long' on the
506 target machine. If you don't define this, the default is one
508 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
510 /* A C expression for the size in bits of the type `long long' on the
511 target machine. If you don't define this, the default is two
513 #define LONG_LONG_TYPE_SIZE 64
515 /* A C expression for the size in bits of the type `float' on the
516 target machine. If you don't define this, the default is one
518 #define FLOAT_TYPE_SIZE 32
520 /* A C expression for the size in bits of the type `double' on the
521 target machine. If you don't define this, the default is two
523 #define DOUBLE_TYPE_SIZE 64
525 /* A C expression for the size in bits of the type `long double' on
526 the target machine. If you don't define this, the default is two
528 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
530 /* Define this to set long double type size to use in libgcc2.c, which can
531 not depend on target_flags. */
532 #ifdef __LONG_DOUBLE_128__
533 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
535 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
538 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
539 #define WIDEST_HARDWARE_FP_SIZE 64
541 /* Width in bits of a pointer.
542 See also the macro `Pmode' defined below. */
543 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
545 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
546 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
548 /* Boundary (in *bits*) on which stack pointer should be aligned. */
549 #define STACK_BOUNDARY \
550 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
552 /* Allocation boundary (in *bits*) for the code of a function. */
553 #define FUNCTION_BOUNDARY 32
555 /* No data type wants to be aligned rounder than this. */
556 #define BIGGEST_ALIGNMENT 128
558 /* A C expression to compute the alignment for a variables in the
559 local store. TYPE is the data type, and ALIGN is the alignment
560 that the object would ordinarily have. */
561 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
562 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
563 (TARGET_E500_DOUBLE \
564 && (TYPE_MODE (TYPE) == DFmode || TYPE_MODE (TYPE) == DDmode)) ? 64 : \
565 ((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
566 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
567 && TREE_CODE (TYPE) == VECTOR_TYPE \
568 && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) ? 64 : ALIGN)
570 /* Alignment of field after `int : 0' in a structure. */
571 #define EMPTY_FIELD_BOUNDARY 32
573 /* Every structure's size must be a multiple of this. */
574 #define STRUCTURE_SIZE_BOUNDARY 8
576 /* Return 1 if a structure or array containing FIELD should be
577 accessed using `BLKMODE'.
579 For the SPE, simd types are V2SI, and gcc can be tempted to put the
580 entire thing in a DI and use subregs to access the internals.
581 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
582 back-end. Because a single GPR can hold a V2SI, but not a DI, the
583 best thing to do is set structs to BLKmode and avoid Severe Tire
586 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
587 fit into 1, whereas DI still needs two. */
588 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
589 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
590 || (TARGET_E500_DOUBLE && ((MODE) == DFmode || (MODE) == DDmode)))
592 /* A bit-field declared as `int' forces `int' alignment for the struct. */
593 #define PCC_BITFIELD_TYPE_MATTERS 1
595 /* Make strings word-aligned so strcpy from constants will be faster.
596 Make vector constants quadword aligned. */
597 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
598 (TREE_CODE (EXP) == STRING_CST \
599 && (ALIGN) < BITS_PER_WORD \
603 /* Make arrays of chars word-aligned for the same reasons.
604 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
606 #define DATA_ALIGNMENT(TYPE, ALIGN) \
607 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
608 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
609 : (TARGET_E500_DOUBLE \
610 && (TYPE_MODE (TYPE) == DFmode || TYPE_MODE (TYPE) == DDmode)) ? 64 \
611 : TREE_CODE (TYPE) == ARRAY_TYPE \
612 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
613 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
615 /* Nonzero if move instructions will actually fail to work
616 when given unaligned data. */
617 #define STRICT_ALIGNMENT 0
619 /* Define this macro to be the value 1 if unaligned accesses have a cost
620 many times greater than aligned accesses, for example if they are
621 emulated in a trap handler. */
622 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
624 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
625 || (MODE) == DDmode || (MODE) == TDmode \
626 || (MODE) == DImode) \
629 /* Standard register usage. */
631 /* Number of actual hardware registers.
632 The hardware registers are assigned numbers for the compiler
633 from 0 to just below FIRST_PSEUDO_REGISTER.
634 All registers that the compiler knows about must be given numbers,
635 even those that are not normally considered general registers.
637 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
638 an MQ register, a count register, a link register, and 8 condition
639 register fields, which we view here as separate registers. AltiVec
640 adds 32 vector registers and a VRsave register.
642 In addition, the difference between the frame and argument pointers is
643 a function of the number of registers saved, so we need to have a
644 register for AP that will later be eliminated in favor of SP or FP.
645 This is a normal register, but it is fixed.
647 We also create a pseudo register for float/int conversions, that will
648 really represent the memory location used. It is represented here as
649 a register, in order to work around problems in allocating stack storage
652 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
653 pointer, which is eventually eliminated in favor of SP or FP. */
655 #define FIRST_PSEUDO_REGISTER 114
657 /* This must be included for pre gcc 3.0 glibc compatibility. */
658 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
660 /* Add 32 dwarf columns for synthetic SPE registers. */
661 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
663 /* The SPE has an additional 32 synthetic registers, with DWARF debug
664 info numbering for these registers starting at 1200. While eh_frame
665 register numbering need not be the same as the debug info numbering,
666 we choose to number these regs for eh_frame at 1200 too. This allows
667 future versions of the rs6000 backend to add hard registers and
668 continue to use the gcc hard register numbering for eh_frame. If the
669 extra SPE registers in eh_frame were numbered starting from the
670 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
671 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
672 avoid invalidating older SPE eh_frame info.
674 We must map them here to avoid huge unwinder tables mostly consisting
676 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
677 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
679 /* Use standard DWARF numbering for DWARF debugging information. */
680 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
682 /* Use gcc hard register numbering for eh_frame. */
683 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
685 /* Map register numbers held in the call frame info that gcc has
686 collected using DWARF_FRAME_REGNUM to those that should be output in
687 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
688 for .eh_frame, but use the numbers mandated by the various ABIs for
689 .debug_frame. rs6000_emit_prologue has translated any combination of
690 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
691 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
692 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
693 ((FOR_EH) ? (REGNO) \
694 : (REGNO) == CR2_REGNO ? 64 \
695 : DBX_REGISTER_NUMBER (REGNO))
697 /* 1 for registers that have pervasive standard uses
698 and are not available for the register allocator.
700 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
701 as a local register; for all other OS's r2 is the TOC pointer.
703 cr5 is not supposed to be used.
705 On System V implementations, r13 is fixed and not available for use. */
707 #define FIXED_REGISTERS \
708 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
712 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
713 /* AltiVec registers. */ \
714 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
720 /* 1 for registers not available across function calls.
721 These must include the FIXED_REGISTERS and also any
722 registers that can be used without being saved.
723 The latter must include the registers where values are returned
724 and the register where structure-value addresses are passed.
725 Aside from that, you can include as many other registers as you like. */
727 #define CALL_USED_REGISTERS \
728 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
729 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
730 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
732 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
733 /* AltiVec registers. */ \
734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
735 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
740 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
741 the entire set of `FIXED_REGISTERS' be included.
742 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
743 This macro is optional. If not specified, it defaults to the value
744 of `CALL_USED_REGISTERS'. */
746 #define CALL_REALLY_USED_REGISTERS \
747 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
748 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
749 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
751 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
752 /* AltiVec registers. */ \
753 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
754 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
759 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
761 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
762 #define FIRST_SAVED_FP_REGNO (14+32)
763 #define FIRST_SAVED_GP_REGNO 13
765 /* List the order in which to allocate registers. Each register must be
766 listed once, even those in FIXED_REGISTERS.
768 We allocate in the following order:
769 fp0 (not saved or used for anything)
770 fp13 - fp2 (not saved; incoming fp arg registers)
771 fp1 (not saved; return value)
772 fp31 - fp14 (saved; order given to save least number)
773 cr7, cr6 (not saved or special)
774 cr1 (not saved, but used for FP operations)
775 cr0 (not saved, but used for arithmetic operations)
776 cr4, cr3, cr2 (saved)
777 r0 (not saved; cannot be base reg)
778 r9 (not saved; best for TImode)
779 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
780 r3 (not saved; return value register)
781 r31 - r13 (saved; order given to save least number)
782 r12 (not saved; if used for DImode or DFmode would use r13)
783 mq (not saved; best to use it if we can)
784 ctr (not saved; when we have the choice ctr is better)
786 cr5, r1, r2, ap, xer (fixed)
787 v0 - v1 (not saved or used for anything)
788 v13 - v3 (not saved; incoming vector arg registers)
789 v2 (not saved; incoming vector arg reg; return value)
790 v19 - v14 (not saved or used for anything)
791 v31 - v20 (saved; order given to save least number)
793 spe_acc, spefscr (fixed)
798 #define MAYBE_R2_AVAILABLE
799 #define MAYBE_R2_FIXED 2,
801 #define MAYBE_R2_AVAILABLE 2,
802 #define MAYBE_R2_FIXED
805 #define REG_ALLOC_ORDER \
807 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
809 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
810 50, 49, 48, 47, 46, \
811 75, 74, 69, 68, 72, 71, 70, \
812 0, MAYBE_R2_AVAILABLE \
813 9, 11, 10, 8, 7, 6, 5, 4, \
815 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
816 18, 17, 16, 15, 14, 13, 12, \
818 73, 1, MAYBE_R2_FIXED 67, 76, \
819 /* AltiVec registers. */ \
821 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
823 96, 95, 94, 93, 92, 91, \
824 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
829 /* True if register is floating-point. */
830 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
832 /* True if register is a condition register. */
833 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
835 /* True if register is a condition register, but not cr0. */
836 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
838 /* True if register is an integer register. */
839 #define INT_REGNO_P(N) \
840 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
842 /* SPE SIMD registers are just the GPRs. */
843 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
845 /* PAIRED SIMD registers are just the FPRs. */
846 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
848 /* True if register is the XER register. */
849 #define XER_REGNO_P(N) ((N) == XER_REGNO)
851 /* True if register is an AltiVec register. */
852 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
854 /* Return number of consecutive hard regs needed starting at reg REGNO
855 to hold something of mode MODE. */
857 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
859 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
860 ((TARGET_32BIT && TARGET_POWERPC64 \
861 && (GET_MODE_SIZE (MODE) > 4) \
862 && INT_REGNO_P (REGNO)) ? 1 : 0)
864 #define ALTIVEC_VECTOR_MODE(MODE) \
865 ((MODE) == V16QImode \
866 || (MODE) == V8HImode \
867 || (MODE) == V4SFmode \
868 || (MODE) == V4SImode)
870 #define SPE_VECTOR_MODE(MODE) \
871 ((MODE) == V4HImode \
872 || (MODE) == V2SFmode \
873 || (MODE) == V1DImode \
874 || (MODE) == V2SImode)
876 #define PAIRED_VECTOR_MODE(MODE) \
879 #define UNITS_PER_SIMD_WORD \
880 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
881 : (TARGET_SPE ? UNITS_PER_SPE_WORD : (TARGET_PAIRED_FLOAT ? \
882 UNITS_PER_PAIRED_WORD : UNITS_PER_WORD)))
884 /* Value is TRUE if hard register REGNO can hold a value of
885 machine-mode MODE. */
886 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
887 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
889 /* Value is 1 if it is a good idea to tie two pseudo registers
890 when one has mode MODE1 and one has mode MODE2.
891 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
892 for any hard reg, then this must be 0 for correct output. */
893 #define MODES_TIEABLE_P(MODE1, MODE2) \
894 (SCALAR_FLOAT_MODE_P (MODE1) \
895 ? SCALAR_FLOAT_MODE_P (MODE2) \
896 : SCALAR_FLOAT_MODE_P (MODE2) \
897 ? SCALAR_FLOAT_MODE_P (MODE1) \
898 : GET_MODE_CLASS (MODE1) == MODE_CC \
899 ? GET_MODE_CLASS (MODE2) == MODE_CC \
900 : GET_MODE_CLASS (MODE2) == MODE_CC \
901 ? GET_MODE_CLASS (MODE1) == MODE_CC \
902 : SPE_VECTOR_MODE (MODE1) \
903 ? SPE_VECTOR_MODE (MODE2) \
904 : SPE_VECTOR_MODE (MODE2) \
905 ? SPE_VECTOR_MODE (MODE1) \
906 : ALTIVEC_VECTOR_MODE (MODE1) \
907 ? ALTIVEC_VECTOR_MODE (MODE2) \
908 : ALTIVEC_VECTOR_MODE (MODE2) \
909 ? ALTIVEC_VECTOR_MODE (MODE1) \
912 /* Post-reload, we can't use any new AltiVec registers, as we already
913 emitted the vrsave mask. */
915 #define HARD_REGNO_RENAME_OK(SRC, DST) \
916 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
918 /* A C expression returning the cost of moving data from a register of class
919 CLASS1 to one of CLASS2. */
921 #define REGISTER_MOVE_COST rs6000_register_move_cost
923 /* A C expressions returning the cost of moving data of MODE from a register to
926 #define MEMORY_MOVE_COST rs6000_memory_move_cost
928 /* Specify the cost of a branch insn; roughly the number of extra insns that
929 should be added to avoid a branch.
931 Set this to 3 on the RS/6000 since that is roughly the average cost of an
932 unscheduled conditional branch. */
934 #define BRANCH_COST 3
936 /* Override BRANCH_COST heuristic which empirically produces worse
937 performance for removing short circuiting from the logical ops. */
939 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
941 /* A fixed register used at epilogue generation to address SPE registers
942 with negative offsets. The 64-bit load/store instructions on the SPE
943 only take positive offsets (and small ones at that), so we need to
944 reserve a register for consing up negative offsets. */
946 #define FIXED_SCRATCH 0
948 /* Define this macro to change register usage conditional on target
951 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
953 /* Specify the registers used for certain standard purposes.
954 The values of these macros are register numbers. */
956 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
957 /* #define PC_REGNUM */
959 /* Register to use for pushing function arguments. */
960 #define STACK_POINTER_REGNUM 1
962 /* Base register for access to local variables of the function. */
963 #define HARD_FRAME_POINTER_REGNUM 31
965 /* Base register for access to local variables of the function. */
966 #define FRAME_POINTER_REGNUM 113
968 /* Value should be nonzero if functions must have frame pointers.
969 Zero means the frame pointer need not be set up (and parms
970 may be accessed via the stack pointer) in functions that seem suitable.
971 This is computed in `reload', in reload1.c. */
972 #define FRAME_POINTER_REQUIRED 0
974 /* Base register for access to arguments of the function. */
975 #define ARG_POINTER_REGNUM 67
977 /* Place to put static chain when calling a function that requires it. */
978 #define STATIC_CHAIN_REGNUM 11
981 /* Define the classes of registers for register constraints in the
982 machine description. Also define ranges of constants.
984 One of the classes must always be named ALL_REGS and include all hard regs.
985 If there is more than one class, another class must be named NO_REGS
986 and contain no registers.
988 The name GENERAL_REGS must be the name of a class (or an alias for
989 another name such as ALL_REGS). This is the class of registers
990 that is allowed by "g" or "r" in a register constraint.
991 Also, registers outside this class are allocated only when
992 instructions express preferences for them.
994 The classes must be numbered in nondecreasing order; that is,
995 a larger-numbered class must never be contained completely
996 in a smaller-numbered class.
998 For any two classes, it is very desirable that there be another
999 class that represents their union. */
1001 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1002 and condition registers, plus three special registers, MQ, CTR, and the
1003 link register. AltiVec adds a vector register class.
1005 However, r0 is special in that it cannot be used as a base register.
1006 So make a class for registers valid as base registers.
1008 Also, cr0 is the only condition code register that can be used in
1009 arithmetic insns, so make a separate class for it. */
1037 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1039 /* Give names of register classes as strings for dump file. */
1041 #define REG_CLASS_NAMES \
1052 "NON_SPECIAL_REGS", \
1056 "LINK_OR_CTR_REGS", \
1058 "SPEC_OR_GEN_REGS", \
1066 /* Define which registers fit in which classes.
1067 This is an initializer for a vector of HARD_REG_SET
1068 of length N_REG_CLASSES. */
1070 #define REG_CLASS_CONTENTS \
1072 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1073 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1074 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1075 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1076 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1077 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1078 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1079 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1080 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1081 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1082 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1083 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1084 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1085 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1086 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1087 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1088 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1089 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1090 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1091 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1092 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1095 /* The same information, inverted:
1096 Return the class number of the smallest class containing
1097 reg number REGNO. This could be a conditional expression
1098 or could index an array. */
1100 #define REGNO_REG_CLASS(REGNO) \
1101 ((REGNO) == 0 ? GENERAL_REGS \
1102 : (REGNO) < 32 ? BASE_REGS \
1103 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1104 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1105 : (REGNO) == CR0_REGNO ? CR0_REGS \
1106 : CR_REGNO_P (REGNO) ? CR_REGS \
1107 : (REGNO) == MQ_REGNO ? MQ_REGS \
1108 : (REGNO) == LR_REGNO ? LINK_REGS \
1109 : (REGNO) == CTR_REGNO ? CTR_REGS \
1110 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1111 : (REGNO) == XER_REGNO ? XER_REGS \
1112 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1113 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1114 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1115 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1116 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1119 /* The class value for index registers, and the one for base regs. */
1120 #define INDEX_REG_CLASS GENERAL_REGS
1121 #define BASE_REG_CLASS BASE_REGS
1123 /* Given an rtx X being reloaded into a reg required to be
1124 in class CLASS, return the class of reg to actually use.
1125 In general this is just CLASS; but on some machines
1126 in some cases it is preferable to use a more restrictive class.
1128 On the RS/6000, we have to return NO_REGS when we want to reload a
1129 floating-point CONST_DOUBLE to force it to be copied to memory.
1131 We also don't want to reload integer values into floating-point
1132 registers if we can at all help it. In fact, this can
1133 cause reload to die, if it tries to generate a reload of CTR
1134 into a FP register and discovers it doesn't have the memory location
1137 ??? Would it be a good idea to have reload do the converse, that is
1138 try to reload floating modes into FP registers if possible?
1141 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1143 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1145 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1146 && (CLASS) == NON_SPECIAL_REGS) \
1150 /* Return the register class of a scratch register needed to copy IN into
1151 or out of a register in CLASS in MODE. If it can be done directly,
1152 NO_REGS is returned. */
1154 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1155 rs6000_secondary_reload_class (CLASS, MODE, IN)
1157 /* If we are copying between FP or AltiVec registers and anything
1158 else, we need a memory location. The exception is when we are
1159 targeting ppc64 and the move to/from fpr to gpr instructions
1162 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1163 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1164 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1165 || ((MODE != DFmode) \
1166 && (MODE != DDmode) \
1167 && (MODE != DImode)))) \
1168 || ((CLASS2) == FLOAT_REGS \
1169 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1170 || ((MODE != DFmode) \
1171 && (MODE != DDmode) \
1172 && (MODE != DImode)))) \
1173 || (CLASS1) == ALTIVEC_REGS \
1174 || (CLASS2) == ALTIVEC_REGS))
1176 /* Return the maximum number of consecutive registers
1177 needed to represent mode MODE in a register of class CLASS.
1179 On RS/6000, this is the size of MODE in words,
1180 except in the FP regs, where a single reg is enough for two words. */
1181 #define CLASS_MAX_NREGS(CLASS, MODE) \
1182 (((CLASS) == FLOAT_REGS) \
1183 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1184 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS \
1185 && ((MODE) == DFmode || (MODE) == DDmode)) \
1187 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1189 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1191 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1192 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1193 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1194 || TARGET_IEEEQUAD) \
1195 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1196 : (((TARGET_E500_DOUBLE \
1197 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
1198 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
1199 || (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
1200 || (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
1201 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1203 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1204 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
1206 /* Stack layout; function entry, exit and calling. */
1208 /* Enumeration to give which calling sequence to use. */
1211 ABI_AIX, /* IBM's AIX */
1212 ABI_V4, /* System V.4/eabi */
1213 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1216 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1218 /* Define this if pushing a word on the stack
1219 makes the stack pointer a smaller address. */
1220 #define STACK_GROWS_DOWNWARD
1222 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1223 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1225 /* Define this to nonzero if the nominal address of the stack frame
1226 is at the high-address end of the local variables;
1227 that is, each additional local variable allocated
1228 goes at a more negative offset in the frame.
1230 On the RS/6000, we grow upwards, from the area after the outgoing
1232 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1234 /* Size of the outgoing register save area */
1235 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1236 || DEFAULT_ABI == ABI_DARWIN) \
1237 ? (TARGET_64BIT ? 64 : 32) \
1240 /* Size of the fixed area on the stack */
1241 #define RS6000_SAVE_AREA \
1242 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1243 << (TARGET_64BIT ? 1 : 0))
1245 /* MEM representing address to save the TOC register */
1246 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1247 plus_constant (stack_pointer_rtx, \
1248 (TARGET_32BIT ? 20 : 40)))
1250 /* Align an address */
1251 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1253 /* Offset within stack frame to start allocating local variables at.
1254 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1255 first local allocated. Otherwise, it is the offset to the BEGINNING
1256 of the first local allocated.
1258 On the RS/6000, the frame pointer is the same as the stack pointer,
1259 except for dynamic allocations. So we start after the fixed area and
1260 outgoing parameter area. */
1262 #define STARTING_FRAME_OFFSET \
1263 (FRAME_GROWS_DOWNWARD \
1265 : (RS6000_ALIGN (current_function_outgoing_args_size, \
1266 TARGET_ALTIVEC ? 16 : 8) \
1267 + RS6000_SAVE_AREA))
1269 /* Offset from the stack pointer register to an item dynamically
1270 allocated on the stack, e.g., by `alloca'.
1272 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1273 length of the outgoing arguments. The default is correct for most
1274 machines. See `function.c' for details. */
1275 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1276 (RS6000_ALIGN (current_function_outgoing_args_size, \
1277 TARGET_ALTIVEC ? 16 : 8) \
1278 + (STACK_POINTER_OFFSET))
1280 /* If we generate an insn to push BYTES bytes,
1281 this says how many the stack pointer really advances by.
1282 On RS/6000, don't define this because there are no push insns. */
1283 /* #define PUSH_ROUNDING(BYTES) */
1285 /* Offset of first parameter from the argument pointer register value.
1286 On the RS/6000, we define the argument pointer to the start of the fixed
1288 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1290 /* Offset from the argument pointer register value to the top of
1291 stack. This is different from FIRST_PARM_OFFSET because of the
1292 register save area. */
1293 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1295 /* Define this if stack space is still allocated for a parameter passed
1296 in a register. The value is the number of bytes allocated to this
1298 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1300 /* Define this if the above stack space is to be considered part of the
1301 space allocated by the caller. */
1302 #define OUTGOING_REG_PARM_STACK_SPACE 1
1304 /* This is the difference between the logical top of stack and the actual sp.
1306 For the RS/6000, sp points past the fixed area. */
1307 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1309 /* Define this if the maximum size of all the outgoing args is to be
1310 accumulated and pushed during the prologue. The amount can be
1311 found in the variable current_function_outgoing_args_size. */
1312 #define ACCUMULATE_OUTGOING_ARGS 1
1314 /* Value is the number of bytes of arguments automatically
1315 popped when returning from a subroutine call.
1316 FUNDECL is the declaration node of the function (as a tree),
1317 FUNTYPE is the data type of the function (as a tree),
1318 or for a library call it is an identifier node for the subroutine name.
1319 SIZE is the number of bytes of arguments passed on the stack. */
1321 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1323 /* Define how to find the value returned by a function.
1324 VALTYPE is the data type of the value (as a tree).
1325 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1326 otherwise, FUNC is 0. */
1328 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1330 /* Define how to find the value returned by a library function
1331 assuming the value has mode MODE. */
1333 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1335 /* DRAFT_V4_STRUCT_RET defaults off. */
1336 #define DRAFT_V4_STRUCT_RET 0
1338 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1339 #define DEFAULT_PCC_STRUCT_RETURN 0
1341 /* Mode of stack savearea.
1342 FUNCTION is VOIDmode because calling convention maintains SP.
1343 BLOCK needs Pmode for SP.
1344 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1345 #define STACK_SAVEAREA_MODE(LEVEL) \
1346 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1347 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1349 /* Minimum and maximum general purpose registers used to hold arguments. */
1350 #define GP_ARG_MIN_REG 3
1351 #define GP_ARG_MAX_REG 10
1352 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1354 /* Minimum and maximum floating point registers used to hold arguments. */
1355 #define FP_ARG_MIN_REG 33
1356 #define FP_ARG_AIX_MAX_REG 45
1357 #define FP_ARG_V4_MAX_REG 40
1358 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1359 || DEFAULT_ABI == ABI_DARWIN) \
1360 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1361 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1363 /* Minimum and maximum AltiVec registers used to hold arguments. */
1364 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1365 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1366 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1368 /* Return registers */
1369 #define GP_ARG_RETURN GP_ARG_MIN_REG
1370 #define FP_ARG_RETURN FP_ARG_MIN_REG
1371 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1373 /* Flags for the call/call_value rtl operations set up by function_arg */
1374 #define CALL_NORMAL 0x00000000 /* no special processing */
1375 /* Bits in 0x00000001 are unused. */
1376 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1377 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1378 #define CALL_LONG 0x00000008 /* always call indirect */
1379 #define CALL_LIBCALL 0x00000010 /* libcall */
1381 /* We don't have prologue and epilogue functions to save/restore
1382 everything for most ABIs. */
1383 #define WORLD_SAVE_P(INFO) 0
1385 /* 1 if N is a possible register number for a function value
1386 as seen by the caller.
1388 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1389 #define FUNCTION_VALUE_REGNO_P(N) \
1390 ((N) == GP_ARG_RETURN \
1391 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1392 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1394 /* 1 if N is a possible register number for function argument passing.
1395 On RS/6000, these are r3-r10 and fp1-fp13.
1396 On AltiVec, v2 - v13 are used for passing vectors. */
1397 #define FUNCTION_ARG_REGNO_P(N) \
1398 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1399 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1400 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1401 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1402 && TARGET_HARD_FLOAT && TARGET_FPRS))
1404 /* Define a data type for recording info about an argument list
1405 during the scan of that argument list. This data type should
1406 hold all necessary information about the function itself
1407 and about the args processed so far, enough to enable macros
1408 such as FUNCTION_ARG to determine where the next arg should go.
1410 On the RS/6000, this is a structure. The first element is the number of
1411 total argument words, the second is used to store the next
1412 floating-point register number, and the third says how many more args we
1413 have prototype types for.
1415 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1416 the next available GP register, `fregno' is the next available FP
1417 register, and `words' is the number of words used on the stack.
1419 The varargs/stdarg support requires that this structure's size
1420 be a multiple of sizeof(int). */
1422 typedef struct rs6000_args
1424 int words; /* # words used for passing GP registers */
1425 int fregno; /* next available FP register */
1426 int vregno; /* next available AltiVec register */
1427 int nargs_prototype; /* # args left in the current prototype */
1428 int prototype; /* Whether a prototype was defined */
1429 int stdarg; /* Whether function is a stdarg function. */
1430 int call_cookie; /* Do special things for this call */
1431 int sysv_gregno; /* next available GP register */
1432 int intoffset; /* running offset in struct (darwin64) */
1433 int use_stack; /* any part of struct on stack (darwin64) */
1434 int named; /* false for varargs params */
1437 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1438 for a call to a function whose data type is FNTYPE.
1439 For a library call, FNTYPE is 0. */
1441 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1442 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1444 /* Similar, but when scanning the definition of a procedure. We always
1445 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1447 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1448 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1450 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1452 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1453 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1455 /* Update the data in CUM to advance over an argument
1456 of mode MODE and data type TYPE.
1457 (TYPE is null for libcalls where that information may not be available.) */
1459 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1460 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1462 /* Determine where to put an argument to a function.
1463 Value is zero to push the argument on the stack,
1464 or a hard register in which to store the argument.
1466 MODE is the argument's machine mode.
1467 TYPE is the data type of the argument (as a tree).
1468 This is null for libcalls where that information may
1470 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1471 the preceding args and about the function being called.
1472 NAMED is nonzero if this argument is a named parameter
1473 (otherwise it is an extra parameter matching an ellipsis).
1475 On RS/6000 the first eight words of non-FP are normally in registers
1476 and the rest are pushed. The first 13 FP args are in registers.
1478 If this is floating-point and no prototype is specified, we use
1479 both an FP and integer register (or possibly FP reg and stack). Library
1480 functions (when TYPE is zero) always have the proper types for args,
1481 so we can pass the FP value just in one register. emit_library_function
1482 doesn't support EXPR_LIST anyway. */
1484 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1485 function_arg (&CUM, MODE, TYPE, NAMED)
1487 /* If defined, a C expression which determines whether, and in which
1488 direction, to pad out an argument with extra space. The value
1489 should be of type `enum direction': either `upward' to pad above
1490 the argument, `downward' to pad below, or `none' to inhibit
1493 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1495 /* If defined, a C expression that gives the alignment boundary, in bits,
1496 of an argument with the specified mode and type. If it is not defined,
1497 PARM_BOUNDARY is used for all arguments. */
1499 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1500 function_arg_boundary (MODE, TYPE)
1502 #define PAD_VARARGS_DOWN \
1503 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1505 /* Output assembler code to FILE to increment profiler label # LABELNO
1506 for profiling a function entry. */
1508 #define FUNCTION_PROFILER(FILE, LABELNO) \
1509 output_function_profiler ((FILE), (LABELNO));
1511 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1512 the stack pointer does not matter. No definition is equivalent to
1515 On the RS/6000, this is nonzero because we can restore the stack from
1516 its backpointer, which we maintain. */
1517 #define EXIT_IGNORE_STACK 1
1519 /* Define this macro as a C expression that is nonzero for registers
1520 that are used by the epilogue or the return' pattern. The stack
1521 and frame pointer registers are already be assumed to be used as
1524 #define EPILOGUE_USES(REGNO) \
1525 ((reload_completed && (REGNO) == LR_REGNO) \
1526 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1527 || (current_function_calls_eh_return \
1532 /* TRAMPOLINE_TEMPLATE deleted */
1534 /* Length in units of the trampoline for entering a nested function. */
1536 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1538 /* Emit RTL insns to initialize the variable parts of a trampoline.
1539 FNADDR is an RTX for the address of the function's pure code.
1540 CXT is an RTX for the static chain value for the function. */
1542 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1543 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1545 /* Definitions for __builtin_return_address and __builtin_frame_address.
1546 __builtin_return_address (0) should give link register (65), enable
1548 /* This should be uncommented, so that the link register is used, but
1549 currently this would result in unmatched insns and spilling fixed
1550 registers so we'll leave it for another day. When these problems are
1551 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1553 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1555 /* Number of bytes into the frame return addresses can be found. See
1556 rs6000_stack_info in rs6000.c for more information on how the different
1557 abi's store the return address. */
1558 #define RETURN_ADDRESS_OFFSET \
1559 ((DEFAULT_ABI == ABI_AIX \
1560 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1561 (DEFAULT_ABI == ABI_V4) ? 4 : \
1562 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1564 /* The current return address is in link register (65). The return address
1565 of anything farther back is accessed normally at an offset of 8 from the
1567 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1568 (rs6000_return_addr (COUNT, FRAME))
1571 /* Definitions for register eliminations.
1573 We have two registers that can be eliminated on the RS/6000. First, the
1574 frame pointer register can often be eliminated in favor of the stack
1575 pointer register. Secondly, the argument pointer register can always be
1576 eliminated; it is replaced with either the stack or frame pointer.
1578 In addition, we use the elimination mechanism to see if r30 is needed
1579 Initially we assume that it isn't. If it is, we spill it. This is done
1580 by making it an eliminable register. We replace it with itself so that
1581 if it isn't needed, then existing uses won't be modified. */
1583 /* This is an array of structures. Each structure initializes one pair
1584 of eliminable registers. The "from" register number is given first,
1585 followed by "to". Eliminations of the same "from" register are listed
1586 in order of preference. */
1587 #define ELIMINABLE_REGS \
1588 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1589 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1590 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1591 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1592 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1593 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1595 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1596 Frame pointer elimination is automatically handled.
1598 For the RS/6000, if frame pointer elimination is being done, we would like
1599 to convert ap into fp, not sp.
1601 We need r30 if -mminimal-toc was specified, and there are constant pool
1604 #define CAN_ELIMINATE(FROM, TO) \
1605 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1606 ? ! frame_pointer_needed \
1607 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1608 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1611 /* Define the offset between two registers, one to be eliminated, and the other
1612 its replacement, at the start of a routine. */
1613 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1614 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1616 /* Addressing modes, and classification of registers for them. */
1618 #define HAVE_PRE_DECREMENT 1
1619 #define HAVE_PRE_INCREMENT 1
1620 #define HAVE_PRE_MODIFY_DISP 1
1621 #define HAVE_PRE_MODIFY_REG 1
1623 /* Macros to check register numbers against specific register classes. */
1625 /* These assume that REGNO is a hard or pseudo reg number.
1626 They give nonzero only if REGNO is a hard reg of the suitable class
1627 or a pseudo reg currently allocated to a suitable hard reg.
1628 Since they use reg_renumber, they are safe only once reg_renumber
1629 has been allocated, which happens in local-alloc.c. */
1631 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1632 ((REGNO) < FIRST_PSEUDO_REGISTER \
1633 ? (REGNO) <= 31 || (REGNO) == 67 \
1634 || (REGNO) == FRAME_POINTER_REGNUM \
1635 : (reg_renumber[REGNO] >= 0 \
1636 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1637 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1639 #define REGNO_OK_FOR_BASE_P(REGNO) \
1640 ((REGNO) < FIRST_PSEUDO_REGISTER \
1641 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1642 || (REGNO) == FRAME_POINTER_REGNUM \
1643 : (reg_renumber[REGNO] > 0 \
1644 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1645 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1647 /* Maximum number of registers that can appear in a valid memory address. */
1649 #define MAX_REGS_PER_ADDRESS 2
1651 /* Recognize any constant value that is a valid address. */
1653 #define CONSTANT_ADDRESS_P(X) \
1654 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1655 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1656 || GET_CODE (X) == HIGH)
1658 /* Nonzero if the constant value X is a legitimate general operand.
1659 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1661 On the RS/6000, all integer constants are acceptable, most won't be valid
1662 for particular insns, though. Only easy FP constants are
1665 #define LEGITIMATE_CONSTANT_P(X) \
1666 (((GET_CODE (X) != CONST_DOUBLE \
1667 && GET_CODE (X) != CONST_VECTOR) \
1668 || GET_MODE (X) == VOIDmode \
1669 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1670 || easy_fp_constant (X, GET_MODE (X)) \
1671 || easy_vector_constant (X, GET_MODE (X))) \
1672 && !rs6000_tls_referenced_p (X))
1674 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1675 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1676 && EASY_VECTOR_15((n) >> 1) \
1679 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1680 and check its validity for a certain class.
1681 We have two alternate definitions for each of them.
1682 The usual definition accepts all pseudo regs; the other rejects
1683 them unless they have been allocated suitable hard regs.
1684 The symbol REG_OK_STRICT causes the latter definition to be used.
1686 Most source files want to accept pseudo regs in the hope that
1687 they will get allocated to the class that the insn wants them to be in.
1688 Source files for reload pass need to be strict.
1689 After reload, it makes no difference, since pseudo regs have
1690 been eliminated by then. */
1692 #ifdef REG_OK_STRICT
1693 # define REG_OK_STRICT_FLAG 1
1695 # define REG_OK_STRICT_FLAG 0
1698 /* Nonzero if X is a hard reg that can be used as an index
1699 or if it is a pseudo reg in the non-strict case. */
1700 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1701 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1702 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1704 /* Nonzero if X is a hard reg that can be used as a base reg
1705 or if it is a pseudo reg in the non-strict case. */
1706 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1707 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1708 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1710 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1711 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1713 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1714 that is a valid memory address for an instruction.
1715 The MODE argument is the machine mode for the MEM expression
1716 that wants to use this address.
1718 On the RS/6000, there are four valid addresses: a SYMBOL_REF that
1719 refers to a constant pool entry of an address (or the sum of it
1720 plus a constant), a short (16-bit signed) constant plus a register,
1721 the sum of two registers, or a register indirect, possibly with an
1722 auto-increment. For DFmode, DDmode and DImode with a constant plus
1723 register, we must ensure that both words are addressable or PowerPC64
1724 with offset word aligned.
1726 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
1727 32-bit DImode, TImode), indexed addressing cannot be used because
1728 adjacent memory cells are accessed by adding word-sized offsets
1729 during assembly output. */
1731 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1732 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1736 /* Try machine-dependent ways of modifying an illegitimate address
1737 to be legitimate. If we find one, return the new, valid address.
1738 This macro is used in only one place: `memory_address' in explow.c.
1740 OLDX is the address as it was before break_out_memory_refs was called.
1741 In some cases it is useful to look at this to decide what needs to be done.
1743 MODE and WIN are passed so that this macro can use
1744 GO_IF_LEGITIMATE_ADDRESS.
1746 It is always safe for this macro to do nothing. It exists to recognize
1747 opportunities to optimize the output.
1749 On RS/6000, first check for the sum of a register with a constant
1750 integer that is out of range. If so, generate code to add the
1751 constant with the low-order 16 bits masked to the register and force
1752 this result into another register (this can be done with `cau').
1753 Then generate an address of REG+(CONST&0xffff), allowing for the
1754 possibility of bit 16 being a one.
1756 Then check for the sum of a register and something not constant, try to
1757 load the other things into a register and return the sum. */
1759 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1760 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1761 if (result != NULL_RTX) \
1768 /* Try a machine-dependent way of reloading an illegitimate address
1769 operand. If we find one, push the reload and jump to WIN. This
1770 macro is used in only one place: `find_reloads_address' in reload.c.
1772 Implemented on rs6000 by rs6000_legitimize_reload_address.
1773 Note that (X) is evaluated twice; this is safe in current usage. */
1775 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1778 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1779 (int)(TYPE), (IND_LEVELS), &win); \
1784 /* Go to LABEL if ADDR (a legitimate address expression)
1785 has an effect that depends on the machine mode it is used for. */
1787 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1789 if (rs6000_mode_dependent_address (ADDR)) \
1793 /* The register number of the register used to address a table of
1794 static data addresses in memory. In some cases this register is
1795 defined by a processor's "application binary interface" (ABI).
1796 When this macro is defined, RTL is generated for this register
1797 once, as with the stack pointer and frame pointer registers. If
1798 this macro is not defined, it is up to the machine-dependent files
1799 to allocate such a register (if necessary). */
1801 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1802 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1804 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1806 /* Define this macro if the register defined by
1807 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1808 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1810 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1812 /* A C expression that is nonzero if X is a legitimate immediate
1813 operand on the target machine when generating position independent
1814 code. You can assume that X satisfies `CONSTANT_P', so you need
1815 not check this. You can also assume FLAG_PIC is true, so you need
1816 not check it either. You need not define this macro if all
1817 constants (including `SYMBOL_REF') can be immediate operands when
1818 generating position independent code. */
1820 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1822 /* Define this if some processing needs to be done immediately before
1823 emitting code for an insn. */
1825 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1827 /* Specify the machine mode that this machine uses
1828 for the index in the tablejump instruction. */
1829 #define CASE_VECTOR_MODE SImode
1831 /* Define as C expression which evaluates to nonzero if the tablejump
1832 instruction expects the table to contain offsets from the address of the
1834 Do not define this if the table should contain absolute addresses. */
1835 #define CASE_VECTOR_PC_RELATIVE 1
1837 /* Define this as 1 if `char' should by default be signed; else as 0. */
1838 #define DEFAULT_SIGNED_CHAR 0
1840 /* This flag, if defined, says the same insns that convert to a signed fixnum
1841 also convert validly to an unsigned one. */
1843 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1845 /* An integer expression for the size in bits of the largest integer machine
1846 mode that should actually be used. */
1848 /* Allow pairs of registers to be used, which is the intent of the default. */
1849 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1851 /* Max number of bytes we can move from memory to memory
1852 in one reasonably fast instruction. */
1853 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1854 #define MAX_MOVE_MAX 8
1856 /* Nonzero if access to memory by bytes is no faster than for words.
1857 Also nonzero if doing byte operations (specifically shifts) in registers
1859 #define SLOW_BYTE_ACCESS 1
1861 /* Define if operations between registers always perform the operation
1862 on the full register even if a narrower mode is specified. */
1863 #define WORD_REGISTER_OPERATIONS
1865 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1866 will either zero-extend or sign-extend. The value of this macro should
1867 be the code that says which one of the two operations is implicitly
1868 done, UNKNOWN if none. */
1869 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1871 /* Define if loading short immediate values into registers sign extends. */
1872 #define SHORT_IMMEDIATES_SIGN_EXTEND
1874 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1875 is done just by pretending it is already truncated. */
1876 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1878 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1879 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1880 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1882 /* The CTZ patterns return -1 for input of zero. */
1883 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1885 /* Specify the machine mode that pointers have.
1886 After generation of rtl, the compiler makes no further distinction
1887 between pointers and any other objects of this machine mode. */
1888 #define Pmode (TARGET_32BIT ? SImode : DImode)
1890 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1891 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1893 /* Mode of a function address in a call instruction (for indexing purposes).
1894 Doesn't matter on RS/6000. */
1895 #define FUNCTION_MODE SImode
1897 /* Define this if addresses of constant functions
1898 shouldn't be put through pseudo regs where they can be cse'd.
1899 Desirable on machines where ordinary constants are expensive
1900 but a CALL with constant address is cheap. */
1901 #define NO_FUNCTION_CSE
1903 /* Define this to be nonzero if shift instructions ignore all but the low-order
1906 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1907 have been dropped from the PowerPC architecture. */
1909 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1911 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1912 should be adjusted to reflect any required changes. This macro is used when
1913 there is some systematic length adjustment required that would be difficult
1914 to express in the length attribute. */
1916 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1918 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1919 COMPARE, return the mode to be used for the comparison. For
1920 floating-point, CCFPmode should be used. CCUNSmode should be used
1921 for unsigned comparisons. CCEQmode should be used when we are
1922 doing an inequality comparison on the result of a
1923 comparison. CCmode should be used in all other cases. */
1925 #define SELECT_CC_MODE(OP,X,Y) \
1926 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1927 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1928 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1929 ? CCEQmode : CCmode))
1931 /* Can the condition code MODE be safely reversed? This is safe in
1932 all cases on this port, because at present it doesn't use the
1933 trapping FP comparisons (fcmpo). */
1934 #define REVERSIBLE_CC_MODE(MODE) 1
1936 /* Given a condition code and a mode, return the inverse condition. */
1937 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1939 /* Define the information needed to generate branch and scc insns. This is
1940 stored from the compare operation. */
1942 extern GTY(()) rtx rs6000_compare_op0;
1943 extern GTY(()) rtx rs6000_compare_op1;
1944 extern int rs6000_compare_fp_p;
1946 /* Control the assembler format that we output. */
1948 /* A C string constant describing how to begin a comment in the target
1949 assembler language. The compiler assumes that the comment will end at
1950 the end of the line. */
1951 #define ASM_COMMENT_START " #"
1953 /* Flag to say the TOC is initialized */
1954 extern int toc_initialized;
1956 /* Macro to output a special constant pool entry. Go to WIN if we output
1957 it. Otherwise, it is written the usual way.
1959 On the RS/6000, toc entries are handled this way. */
1961 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1962 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1964 output_toc (FILE, X, LABELNO, MODE); \
1969 #ifdef HAVE_GAS_WEAK
1970 #define RS6000_WEAK 1
1972 #define RS6000_WEAK 0
1976 /* Used in lieu of ASM_WEAKEN_LABEL. */
1977 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1980 fputs ("\t.weak\t", (FILE)); \
1981 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1982 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1983 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1986 fputs ("[DS]", (FILE)); \
1987 fputs ("\n\t.weak\t.", (FILE)); \
1988 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1990 fputc ('\n', (FILE)); \
1993 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1994 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1995 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1997 fputs ("\t.set\t.", (FILE)); \
1998 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1999 fputs (",.", (FILE)); \
2000 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2001 fputc ('\n', (FILE)); \
2008 #if HAVE_GAS_WEAKREF
2009 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2012 fputs ("\t.weakref\t", (FILE)); \
2013 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2014 fputs (", ", (FILE)); \
2015 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2016 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2017 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2019 fputs ("\n\t.weakref\t.", (FILE)); \
2020 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2021 fputs (", .", (FILE)); \
2022 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2024 fputc ('\n', (FILE)); \
2028 /* This implements the `alias' attribute. */
2029 #undef ASM_OUTPUT_DEF_FROM_DECLS
2030 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2033 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2034 const char *name = IDENTIFIER_POINTER (TARGET); \
2035 if (TREE_CODE (DECL) == FUNCTION_DECL \
2036 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2038 if (TREE_PUBLIC (DECL)) \
2040 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2042 fputs ("\t.globl\t.", FILE); \
2043 RS6000_OUTPUT_BASENAME (FILE, alias); \
2044 putc ('\n', FILE); \
2047 else if (TARGET_XCOFF) \
2049 fputs ("\t.lglobl\t.", FILE); \
2050 RS6000_OUTPUT_BASENAME (FILE, alias); \
2051 putc ('\n', FILE); \
2053 fputs ("\t.set\t.", FILE); \
2054 RS6000_OUTPUT_BASENAME (FILE, alias); \
2055 fputs (",.", FILE); \
2056 RS6000_OUTPUT_BASENAME (FILE, name); \
2057 fputc ('\n', FILE); \
2059 ASM_OUTPUT_DEF (FILE, alias, name); \
2063 #define TARGET_ASM_FILE_START rs6000_file_start
2065 /* Output to assembler file text saying following lines
2066 may contain character constants, extra white space, comments, etc. */
2068 #define ASM_APP_ON ""
2070 /* Output to assembler file text saying following lines
2071 no longer contain unusual constructs. */
2073 #define ASM_APP_OFF ""
2075 /* How to refer to registers in assembler output.
2076 This sequence is indexed by compiler's hard-register-number (see above). */
2078 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2080 #define REGISTER_NAMES \
2082 &rs6000_reg_names[ 0][0], /* r0 */ \
2083 &rs6000_reg_names[ 1][0], /* r1 */ \
2084 &rs6000_reg_names[ 2][0], /* r2 */ \
2085 &rs6000_reg_names[ 3][0], /* r3 */ \
2086 &rs6000_reg_names[ 4][0], /* r4 */ \
2087 &rs6000_reg_names[ 5][0], /* r5 */ \
2088 &rs6000_reg_names[ 6][0], /* r6 */ \
2089 &rs6000_reg_names[ 7][0], /* r7 */ \
2090 &rs6000_reg_names[ 8][0], /* r8 */ \
2091 &rs6000_reg_names[ 9][0], /* r9 */ \
2092 &rs6000_reg_names[10][0], /* r10 */ \
2093 &rs6000_reg_names[11][0], /* r11 */ \
2094 &rs6000_reg_names[12][0], /* r12 */ \
2095 &rs6000_reg_names[13][0], /* r13 */ \
2096 &rs6000_reg_names[14][0], /* r14 */ \
2097 &rs6000_reg_names[15][0], /* r15 */ \
2098 &rs6000_reg_names[16][0], /* r16 */ \
2099 &rs6000_reg_names[17][0], /* r17 */ \
2100 &rs6000_reg_names[18][0], /* r18 */ \
2101 &rs6000_reg_names[19][0], /* r19 */ \
2102 &rs6000_reg_names[20][0], /* r20 */ \
2103 &rs6000_reg_names[21][0], /* r21 */ \
2104 &rs6000_reg_names[22][0], /* r22 */ \
2105 &rs6000_reg_names[23][0], /* r23 */ \
2106 &rs6000_reg_names[24][0], /* r24 */ \
2107 &rs6000_reg_names[25][0], /* r25 */ \
2108 &rs6000_reg_names[26][0], /* r26 */ \
2109 &rs6000_reg_names[27][0], /* r27 */ \
2110 &rs6000_reg_names[28][0], /* r28 */ \
2111 &rs6000_reg_names[29][0], /* r29 */ \
2112 &rs6000_reg_names[30][0], /* r30 */ \
2113 &rs6000_reg_names[31][0], /* r31 */ \
2115 &rs6000_reg_names[32][0], /* fr0 */ \
2116 &rs6000_reg_names[33][0], /* fr1 */ \
2117 &rs6000_reg_names[34][0], /* fr2 */ \
2118 &rs6000_reg_names[35][0], /* fr3 */ \
2119 &rs6000_reg_names[36][0], /* fr4 */ \
2120 &rs6000_reg_names[37][0], /* fr5 */ \
2121 &rs6000_reg_names[38][0], /* fr6 */ \
2122 &rs6000_reg_names[39][0], /* fr7 */ \
2123 &rs6000_reg_names[40][0], /* fr8 */ \
2124 &rs6000_reg_names[41][0], /* fr9 */ \
2125 &rs6000_reg_names[42][0], /* fr10 */ \
2126 &rs6000_reg_names[43][0], /* fr11 */ \
2127 &rs6000_reg_names[44][0], /* fr12 */ \
2128 &rs6000_reg_names[45][0], /* fr13 */ \
2129 &rs6000_reg_names[46][0], /* fr14 */ \
2130 &rs6000_reg_names[47][0], /* fr15 */ \
2131 &rs6000_reg_names[48][0], /* fr16 */ \
2132 &rs6000_reg_names[49][0], /* fr17 */ \
2133 &rs6000_reg_names[50][0], /* fr18 */ \
2134 &rs6000_reg_names[51][0], /* fr19 */ \
2135 &rs6000_reg_names[52][0], /* fr20 */ \
2136 &rs6000_reg_names[53][0], /* fr21 */ \
2137 &rs6000_reg_names[54][0], /* fr22 */ \
2138 &rs6000_reg_names[55][0], /* fr23 */ \
2139 &rs6000_reg_names[56][0], /* fr24 */ \
2140 &rs6000_reg_names[57][0], /* fr25 */ \
2141 &rs6000_reg_names[58][0], /* fr26 */ \
2142 &rs6000_reg_names[59][0], /* fr27 */ \
2143 &rs6000_reg_names[60][0], /* fr28 */ \
2144 &rs6000_reg_names[61][0], /* fr29 */ \
2145 &rs6000_reg_names[62][0], /* fr30 */ \
2146 &rs6000_reg_names[63][0], /* fr31 */ \
2148 &rs6000_reg_names[64][0], /* mq */ \
2149 &rs6000_reg_names[65][0], /* lr */ \
2150 &rs6000_reg_names[66][0], /* ctr */ \
2151 &rs6000_reg_names[67][0], /* ap */ \
2153 &rs6000_reg_names[68][0], /* cr0 */ \
2154 &rs6000_reg_names[69][0], /* cr1 */ \
2155 &rs6000_reg_names[70][0], /* cr2 */ \
2156 &rs6000_reg_names[71][0], /* cr3 */ \
2157 &rs6000_reg_names[72][0], /* cr4 */ \
2158 &rs6000_reg_names[73][0], /* cr5 */ \
2159 &rs6000_reg_names[74][0], /* cr6 */ \
2160 &rs6000_reg_names[75][0], /* cr7 */ \
2162 &rs6000_reg_names[76][0], /* xer */ \
2164 &rs6000_reg_names[77][0], /* v0 */ \
2165 &rs6000_reg_names[78][0], /* v1 */ \
2166 &rs6000_reg_names[79][0], /* v2 */ \
2167 &rs6000_reg_names[80][0], /* v3 */ \
2168 &rs6000_reg_names[81][0], /* v4 */ \
2169 &rs6000_reg_names[82][0], /* v5 */ \
2170 &rs6000_reg_names[83][0], /* v6 */ \
2171 &rs6000_reg_names[84][0], /* v7 */ \
2172 &rs6000_reg_names[85][0], /* v8 */ \
2173 &rs6000_reg_names[86][0], /* v9 */ \
2174 &rs6000_reg_names[87][0], /* v10 */ \
2175 &rs6000_reg_names[88][0], /* v11 */ \
2176 &rs6000_reg_names[89][0], /* v12 */ \
2177 &rs6000_reg_names[90][0], /* v13 */ \
2178 &rs6000_reg_names[91][0], /* v14 */ \
2179 &rs6000_reg_names[92][0], /* v15 */ \
2180 &rs6000_reg_names[93][0], /* v16 */ \
2181 &rs6000_reg_names[94][0], /* v17 */ \
2182 &rs6000_reg_names[95][0], /* v18 */ \
2183 &rs6000_reg_names[96][0], /* v19 */ \
2184 &rs6000_reg_names[97][0], /* v20 */ \
2185 &rs6000_reg_names[98][0], /* v21 */ \
2186 &rs6000_reg_names[99][0], /* v22 */ \
2187 &rs6000_reg_names[100][0], /* v23 */ \
2188 &rs6000_reg_names[101][0], /* v24 */ \
2189 &rs6000_reg_names[102][0], /* v25 */ \
2190 &rs6000_reg_names[103][0], /* v26 */ \
2191 &rs6000_reg_names[104][0], /* v27 */ \
2192 &rs6000_reg_names[105][0], /* v28 */ \
2193 &rs6000_reg_names[106][0], /* v29 */ \
2194 &rs6000_reg_names[107][0], /* v30 */ \
2195 &rs6000_reg_names[108][0], /* v31 */ \
2196 &rs6000_reg_names[109][0], /* vrsave */ \
2197 &rs6000_reg_names[110][0], /* vscr */ \
2198 &rs6000_reg_names[111][0], /* spe_acc */ \
2199 &rs6000_reg_names[112][0], /* spefscr */ \
2200 &rs6000_reg_names[113][0], /* sfp */ \
2203 /* Table of additional register names to use in user input. */
2205 #define ADDITIONAL_REGISTER_NAMES \
2206 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2207 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2208 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2209 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2210 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2211 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2212 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2213 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2214 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2215 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2216 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2217 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2218 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2219 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2220 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2221 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2222 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2223 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2224 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2225 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2226 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2227 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2228 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2229 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2230 {"vrsave", 109}, {"vscr", 110}, \
2231 {"spe_acc", 111}, {"spefscr", 112}, \
2232 /* no additional names for: mq, lr, ctr, ap */ \
2233 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2234 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2235 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2237 /* Text to write out after a CALL that may be replaced by glue code by
2238 the loader. This depends on the AIX version. */
2239 #define RS6000_CALL_GLUE "cror 31,31,31"
2241 /* This is how to output an element of a case-vector that is relative. */
2243 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2244 do { char buf[100]; \
2245 fputs ("\t.long ", FILE); \
2246 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2247 assemble_name (FILE, buf); \
2249 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2250 assemble_name (FILE, buf); \
2251 putc ('\n', FILE); \
2254 /* This is how to output an assembler line
2255 that says to advance the location counter
2256 to a multiple of 2**LOG bytes. */
2258 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2260 fprintf (FILE, "\t.align %d\n", (LOG))
2262 /* Pick up the return address upon entry to a procedure. Used for
2263 dwarf2 unwind information. This also enables the table driven
2266 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2267 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2269 /* Describe how we implement __builtin_eh_return. */
2270 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2271 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2273 /* Print operand X (an rtx) in assembler syntax to file FILE.
2274 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2275 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2277 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2279 /* Define which CODE values are valid. */
2281 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2282 ((CODE) == '.' || (CODE) == '&')
2284 /* Print a memory address as an operand to reference that memory location. */
2286 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2288 /* uncomment for disabling the corresponding default options */
2289 /* #define MACHINE_no_sched_interblock */
2290 /* #define MACHINE_no_sched_speculative */
2291 /* #define MACHINE_no_sched_speculative_load */
2293 /* General flags. */
2294 extern int flag_pic;
2295 extern int optimize;
2296 extern int flag_expensive_optimizations;
2297 extern int frame_pointer_needed;
2299 enum rs6000_builtins
2301 /* AltiVec builtins. */
2302 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2303 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2304 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2305 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2306 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2307 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2308 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2309 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2310 ALTIVEC_BUILTIN_VADDUBM,
2311 ALTIVEC_BUILTIN_VADDUHM,
2312 ALTIVEC_BUILTIN_VADDUWM,
2313 ALTIVEC_BUILTIN_VADDFP,
2314 ALTIVEC_BUILTIN_VADDCUW,
2315 ALTIVEC_BUILTIN_VADDUBS,
2316 ALTIVEC_BUILTIN_VADDSBS,
2317 ALTIVEC_BUILTIN_VADDUHS,
2318 ALTIVEC_BUILTIN_VADDSHS,
2319 ALTIVEC_BUILTIN_VADDUWS,
2320 ALTIVEC_BUILTIN_VADDSWS,
2321 ALTIVEC_BUILTIN_VAND,
2322 ALTIVEC_BUILTIN_VANDC,
2323 ALTIVEC_BUILTIN_VAVGUB,
2324 ALTIVEC_BUILTIN_VAVGSB,
2325 ALTIVEC_BUILTIN_VAVGUH,
2326 ALTIVEC_BUILTIN_VAVGSH,
2327 ALTIVEC_BUILTIN_VAVGUW,
2328 ALTIVEC_BUILTIN_VAVGSW,
2329 ALTIVEC_BUILTIN_VCFUX,
2330 ALTIVEC_BUILTIN_VCFSX,
2331 ALTIVEC_BUILTIN_VCTSXS,
2332 ALTIVEC_BUILTIN_VCTUXS,
2333 ALTIVEC_BUILTIN_VCMPBFP,
2334 ALTIVEC_BUILTIN_VCMPEQUB,
2335 ALTIVEC_BUILTIN_VCMPEQUH,
2336 ALTIVEC_BUILTIN_VCMPEQUW,
2337 ALTIVEC_BUILTIN_VCMPEQFP,
2338 ALTIVEC_BUILTIN_VCMPGEFP,
2339 ALTIVEC_BUILTIN_VCMPGTUB,
2340 ALTIVEC_BUILTIN_VCMPGTSB,
2341 ALTIVEC_BUILTIN_VCMPGTUH,
2342 ALTIVEC_BUILTIN_VCMPGTSH,
2343 ALTIVEC_BUILTIN_VCMPGTUW,
2344 ALTIVEC_BUILTIN_VCMPGTSW,
2345 ALTIVEC_BUILTIN_VCMPGTFP,
2346 ALTIVEC_BUILTIN_VEXPTEFP,
2347 ALTIVEC_BUILTIN_VLOGEFP,
2348 ALTIVEC_BUILTIN_VMADDFP,
2349 ALTIVEC_BUILTIN_VMAXUB,
2350 ALTIVEC_BUILTIN_VMAXSB,
2351 ALTIVEC_BUILTIN_VMAXUH,
2352 ALTIVEC_BUILTIN_VMAXSH,
2353 ALTIVEC_BUILTIN_VMAXUW,
2354 ALTIVEC_BUILTIN_VMAXSW,
2355 ALTIVEC_BUILTIN_VMAXFP,
2356 ALTIVEC_BUILTIN_VMHADDSHS,
2357 ALTIVEC_BUILTIN_VMHRADDSHS,
2358 ALTIVEC_BUILTIN_VMLADDUHM,
2359 ALTIVEC_BUILTIN_VMRGHB,
2360 ALTIVEC_BUILTIN_VMRGHH,
2361 ALTIVEC_BUILTIN_VMRGHW,
2362 ALTIVEC_BUILTIN_VMRGLB,
2363 ALTIVEC_BUILTIN_VMRGLH,
2364 ALTIVEC_BUILTIN_VMRGLW,
2365 ALTIVEC_BUILTIN_VMSUMUBM,
2366 ALTIVEC_BUILTIN_VMSUMMBM,
2367 ALTIVEC_BUILTIN_VMSUMUHM,
2368 ALTIVEC_BUILTIN_VMSUMSHM,
2369 ALTIVEC_BUILTIN_VMSUMUHS,
2370 ALTIVEC_BUILTIN_VMSUMSHS,
2371 ALTIVEC_BUILTIN_VMINUB,
2372 ALTIVEC_BUILTIN_VMINSB,
2373 ALTIVEC_BUILTIN_VMINUH,
2374 ALTIVEC_BUILTIN_VMINSH,
2375 ALTIVEC_BUILTIN_VMINUW,
2376 ALTIVEC_BUILTIN_VMINSW,
2377 ALTIVEC_BUILTIN_VMINFP,
2378 ALTIVEC_BUILTIN_VMULEUB,
2379 ALTIVEC_BUILTIN_VMULESB,
2380 ALTIVEC_BUILTIN_VMULEUH,
2381 ALTIVEC_BUILTIN_VMULESH,
2382 ALTIVEC_BUILTIN_VMULOUB,
2383 ALTIVEC_BUILTIN_VMULOSB,
2384 ALTIVEC_BUILTIN_VMULOUH,
2385 ALTIVEC_BUILTIN_VMULOSH,
2386 ALTIVEC_BUILTIN_VNMSUBFP,
2387 ALTIVEC_BUILTIN_VNOR,
2388 ALTIVEC_BUILTIN_VOR,
2389 ALTIVEC_BUILTIN_VSEL_4SI,
2390 ALTIVEC_BUILTIN_VSEL_4SF,
2391 ALTIVEC_BUILTIN_VSEL_8HI,
2392 ALTIVEC_BUILTIN_VSEL_16QI,
2393 ALTIVEC_BUILTIN_VPERM_4SI,
2394 ALTIVEC_BUILTIN_VPERM_4SF,
2395 ALTIVEC_BUILTIN_VPERM_8HI,
2396 ALTIVEC_BUILTIN_VPERM_16QI,
2397 ALTIVEC_BUILTIN_VPKUHUM,
2398 ALTIVEC_BUILTIN_VPKUWUM,
2399 ALTIVEC_BUILTIN_VPKPX,
2400 ALTIVEC_BUILTIN_VPKUHSS,
2401 ALTIVEC_BUILTIN_VPKSHSS,
2402 ALTIVEC_BUILTIN_VPKUWSS,
2403 ALTIVEC_BUILTIN_VPKSWSS,
2404 ALTIVEC_BUILTIN_VPKUHUS,
2405 ALTIVEC_BUILTIN_VPKSHUS,
2406 ALTIVEC_BUILTIN_VPKUWUS,
2407 ALTIVEC_BUILTIN_VPKSWUS,
2408 ALTIVEC_BUILTIN_VREFP,
2409 ALTIVEC_BUILTIN_VRFIM,
2410 ALTIVEC_BUILTIN_VRFIN,
2411 ALTIVEC_BUILTIN_VRFIP,
2412 ALTIVEC_BUILTIN_VRFIZ,
2413 ALTIVEC_BUILTIN_VRLB,
2414 ALTIVEC_BUILTIN_VRLH,
2415 ALTIVEC_BUILTIN_VRLW,
2416 ALTIVEC_BUILTIN_VRSQRTEFP,
2417 ALTIVEC_BUILTIN_VSLB,
2418 ALTIVEC_BUILTIN_VSLH,
2419 ALTIVEC_BUILTIN_VSLW,
2420 ALTIVEC_BUILTIN_VSL,
2421 ALTIVEC_BUILTIN_VSLO,
2422 ALTIVEC_BUILTIN_VSPLTB,
2423 ALTIVEC_BUILTIN_VSPLTH,
2424 ALTIVEC_BUILTIN_VSPLTW,
2425 ALTIVEC_BUILTIN_VSPLTISB,
2426 ALTIVEC_BUILTIN_VSPLTISH,
2427 ALTIVEC_BUILTIN_VSPLTISW,
2428 ALTIVEC_BUILTIN_VSRB,
2429 ALTIVEC_BUILTIN_VSRH,
2430 ALTIVEC_BUILTIN_VSRW,
2431 ALTIVEC_BUILTIN_VSRAB,
2432 ALTIVEC_BUILTIN_VSRAH,
2433 ALTIVEC_BUILTIN_VSRAW,
2434 ALTIVEC_BUILTIN_VSR,
2435 ALTIVEC_BUILTIN_VSRO,
2436 ALTIVEC_BUILTIN_VSUBUBM,
2437 ALTIVEC_BUILTIN_VSUBUHM,
2438 ALTIVEC_BUILTIN_VSUBUWM,
2439 ALTIVEC_BUILTIN_VSUBFP,
2440 ALTIVEC_BUILTIN_VSUBCUW,
2441 ALTIVEC_BUILTIN_VSUBUBS,
2442 ALTIVEC_BUILTIN_VSUBSBS,
2443 ALTIVEC_BUILTIN_VSUBUHS,
2444 ALTIVEC_BUILTIN_VSUBSHS,
2445 ALTIVEC_BUILTIN_VSUBUWS,
2446 ALTIVEC_BUILTIN_VSUBSWS,
2447 ALTIVEC_BUILTIN_VSUM4UBS,
2448 ALTIVEC_BUILTIN_VSUM4SBS,
2449 ALTIVEC_BUILTIN_VSUM4SHS,
2450 ALTIVEC_BUILTIN_VSUM2SWS,
2451 ALTIVEC_BUILTIN_VSUMSWS,
2452 ALTIVEC_BUILTIN_VXOR,
2453 ALTIVEC_BUILTIN_VSLDOI_16QI,
2454 ALTIVEC_BUILTIN_VSLDOI_8HI,
2455 ALTIVEC_BUILTIN_VSLDOI_4SI,
2456 ALTIVEC_BUILTIN_VSLDOI_4SF,
2457 ALTIVEC_BUILTIN_VUPKHSB,
2458 ALTIVEC_BUILTIN_VUPKHPX,
2459 ALTIVEC_BUILTIN_VUPKHSH,
2460 ALTIVEC_BUILTIN_VUPKLSB,
2461 ALTIVEC_BUILTIN_VUPKLPX,
2462 ALTIVEC_BUILTIN_VUPKLSH,
2463 ALTIVEC_BUILTIN_MTVSCR,
2464 ALTIVEC_BUILTIN_MFVSCR,
2465 ALTIVEC_BUILTIN_DSSALL,
2466 ALTIVEC_BUILTIN_DSS,
2467 ALTIVEC_BUILTIN_LVSL,
2468 ALTIVEC_BUILTIN_LVSR,
2469 ALTIVEC_BUILTIN_DSTT,
2470 ALTIVEC_BUILTIN_DSTST,
2471 ALTIVEC_BUILTIN_DSTSTT,
2472 ALTIVEC_BUILTIN_DST,
2473 ALTIVEC_BUILTIN_LVEBX,
2474 ALTIVEC_BUILTIN_LVEHX,
2475 ALTIVEC_BUILTIN_LVEWX,
2476 ALTIVEC_BUILTIN_LVXL,
2477 ALTIVEC_BUILTIN_LVX,
2478 ALTIVEC_BUILTIN_STVX,
2479 ALTIVEC_BUILTIN_STVEBX,
2480 ALTIVEC_BUILTIN_STVEHX,
2481 ALTIVEC_BUILTIN_STVEWX,
2482 ALTIVEC_BUILTIN_STVXL,
2483 ALTIVEC_BUILTIN_VCMPBFP_P,
2484 ALTIVEC_BUILTIN_VCMPEQFP_P,
2485 ALTIVEC_BUILTIN_VCMPEQUB_P,
2486 ALTIVEC_BUILTIN_VCMPEQUH_P,
2487 ALTIVEC_BUILTIN_VCMPEQUW_P,
2488 ALTIVEC_BUILTIN_VCMPGEFP_P,
2489 ALTIVEC_BUILTIN_VCMPGTFP_P,
2490 ALTIVEC_BUILTIN_VCMPGTSB_P,
2491 ALTIVEC_BUILTIN_VCMPGTSH_P,
2492 ALTIVEC_BUILTIN_VCMPGTSW_P,
2493 ALTIVEC_BUILTIN_VCMPGTUB_P,
2494 ALTIVEC_BUILTIN_VCMPGTUH_P,
2495 ALTIVEC_BUILTIN_VCMPGTUW_P,
2496 ALTIVEC_BUILTIN_ABSS_V4SI,
2497 ALTIVEC_BUILTIN_ABSS_V8HI,
2498 ALTIVEC_BUILTIN_ABSS_V16QI,
2499 ALTIVEC_BUILTIN_ABS_V4SI,
2500 ALTIVEC_BUILTIN_ABS_V4SF,
2501 ALTIVEC_BUILTIN_ABS_V8HI,
2502 ALTIVEC_BUILTIN_ABS_V16QI,
2503 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2504 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2505 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2506 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2507 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2508 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2509 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2510 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2511 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2512 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2513 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2514 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2515 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2516 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2518 /* Altivec overloaded builtins. */
2519 ALTIVEC_BUILTIN_VCMPEQ_P,
2520 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2521 ALTIVEC_BUILTIN_VCMPGT_P,
2522 ALTIVEC_BUILTIN_VCMPGE_P,
2523 ALTIVEC_BUILTIN_VEC_ABS,
2524 ALTIVEC_BUILTIN_VEC_ABSS,
2525 ALTIVEC_BUILTIN_VEC_ADD,
2526 ALTIVEC_BUILTIN_VEC_ADDC,
2527 ALTIVEC_BUILTIN_VEC_ADDS,
2528 ALTIVEC_BUILTIN_VEC_AND,
2529 ALTIVEC_BUILTIN_VEC_ANDC,
2530 ALTIVEC_BUILTIN_VEC_AVG,
2531 ALTIVEC_BUILTIN_VEC_CEIL,
2532 ALTIVEC_BUILTIN_VEC_CMPB,
2533 ALTIVEC_BUILTIN_VEC_CMPEQ,
2534 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2535 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2536 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2537 ALTIVEC_BUILTIN_VEC_CMPGE,
2538 ALTIVEC_BUILTIN_VEC_CMPGT,
2539 ALTIVEC_BUILTIN_VEC_CMPLE,
2540 ALTIVEC_BUILTIN_VEC_CMPLT,
2541 ALTIVEC_BUILTIN_VEC_CTF,
2542 ALTIVEC_BUILTIN_VEC_CTS,
2543 ALTIVEC_BUILTIN_VEC_CTU,
2544 ALTIVEC_BUILTIN_VEC_DST,
2545 ALTIVEC_BUILTIN_VEC_DSTST,
2546 ALTIVEC_BUILTIN_VEC_DSTSTT,
2547 ALTIVEC_BUILTIN_VEC_DSTT,
2548 ALTIVEC_BUILTIN_VEC_EXPTE,
2549 ALTIVEC_BUILTIN_VEC_FLOOR,
2550 ALTIVEC_BUILTIN_VEC_LD,
2551 ALTIVEC_BUILTIN_VEC_LDE,
2552 ALTIVEC_BUILTIN_VEC_LDL,
2553 ALTIVEC_BUILTIN_VEC_LOGE,
2554 ALTIVEC_BUILTIN_VEC_LVEBX,
2555 ALTIVEC_BUILTIN_VEC_LVEHX,
2556 ALTIVEC_BUILTIN_VEC_LVEWX,
2557 ALTIVEC_BUILTIN_VEC_LVSL,
2558 ALTIVEC_BUILTIN_VEC_LVSR,
2559 ALTIVEC_BUILTIN_VEC_MADD,
2560 ALTIVEC_BUILTIN_VEC_MADDS,
2561 ALTIVEC_BUILTIN_VEC_MAX,
2562 ALTIVEC_BUILTIN_VEC_MERGEH,
2563 ALTIVEC_BUILTIN_VEC_MERGEL,
2564 ALTIVEC_BUILTIN_VEC_MIN,
2565 ALTIVEC_BUILTIN_VEC_MLADD,
2566 ALTIVEC_BUILTIN_VEC_MPERM,
2567 ALTIVEC_BUILTIN_VEC_MRADDS,
2568 ALTIVEC_BUILTIN_VEC_MRGHB,
2569 ALTIVEC_BUILTIN_VEC_MRGHH,
2570 ALTIVEC_BUILTIN_VEC_MRGHW,
2571 ALTIVEC_BUILTIN_VEC_MRGLB,
2572 ALTIVEC_BUILTIN_VEC_MRGLH,
2573 ALTIVEC_BUILTIN_VEC_MRGLW,
2574 ALTIVEC_BUILTIN_VEC_MSUM,
2575 ALTIVEC_BUILTIN_VEC_MSUMS,
2576 ALTIVEC_BUILTIN_VEC_MTVSCR,
2577 ALTIVEC_BUILTIN_VEC_MULE,
2578 ALTIVEC_BUILTIN_VEC_MULO,
2579 ALTIVEC_BUILTIN_VEC_NMSUB,
2580 ALTIVEC_BUILTIN_VEC_NOR,
2581 ALTIVEC_BUILTIN_VEC_OR,
2582 ALTIVEC_BUILTIN_VEC_PACK,
2583 ALTIVEC_BUILTIN_VEC_PACKPX,
2584 ALTIVEC_BUILTIN_VEC_PACKS,
2585 ALTIVEC_BUILTIN_VEC_PACKSU,
2586 ALTIVEC_BUILTIN_VEC_PERM,
2587 ALTIVEC_BUILTIN_VEC_RE,
2588 ALTIVEC_BUILTIN_VEC_RL,
2589 ALTIVEC_BUILTIN_VEC_ROUND,
2590 ALTIVEC_BUILTIN_VEC_RSQRTE,
2591 ALTIVEC_BUILTIN_VEC_SEL,
2592 ALTIVEC_BUILTIN_VEC_SL,
2593 ALTIVEC_BUILTIN_VEC_SLD,
2594 ALTIVEC_BUILTIN_VEC_SLL,
2595 ALTIVEC_BUILTIN_VEC_SLO,
2596 ALTIVEC_BUILTIN_VEC_SPLAT,
2597 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2598 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2599 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2600 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2601 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2602 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2603 ALTIVEC_BUILTIN_VEC_SPLTB,
2604 ALTIVEC_BUILTIN_VEC_SPLTH,
2605 ALTIVEC_BUILTIN_VEC_SPLTW,
2606 ALTIVEC_BUILTIN_VEC_SR,
2607 ALTIVEC_BUILTIN_VEC_SRA,
2608 ALTIVEC_BUILTIN_VEC_SRL,
2609 ALTIVEC_BUILTIN_VEC_SRO,
2610 ALTIVEC_BUILTIN_VEC_ST,
2611 ALTIVEC_BUILTIN_VEC_STE,
2612 ALTIVEC_BUILTIN_VEC_STL,
2613 ALTIVEC_BUILTIN_VEC_STVEBX,
2614 ALTIVEC_BUILTIN_VEC_STVEHX,
2615 ALTIVEC_BUILTIN_VEC_STVEWX,
2616 ALTIVEC_BUILTIN_VEC_SUB,
2617 ALTIVEC_BUILTIN_VEC_SUBC,
2618 ALTIVEC_BUILTIN_VEC_SUBS,
2619 ALTIVEC_BUILTIN_VEC_SUM2S,
2620 ALTIVEC_BUILTIN_VEC_SUM4S,
2621 ALTIVEC_BUILTIN_VEC_SUMS,
2622 ALTIVEC_BUILTIN_VEC_TRUNC,
2623 ALTIVEC_BUILTIN_VEC_UNPACKH,
2624 ALTIVEC_BUILTIN_VEC_UNPACKL,
2625 ALTIVEC_BUILTIN_VEC_VADDFP,
2626 ALTIVEC_BUILTIN_VEC_VADDSBS,
2627 ALTIVEC_BUILTIN_VEC_VADDSHS,
2628 ALTIVEC_BUILTIN_VEC_VADDSWS,
2629 ALTIVEC_BUILTIN_VEC_VADDUBM,
2630 ALTIVEC_BUILTIN_VEC_VADDUBS,
2631 ALTIVEC_BUILTIN_VEC_VADDUHM,
2632 ALTIVEC_BUILTIN_VEC_VADDUHS,
2633 ALTIVEC_BUILTIN_VEC_VADDUWM,
2634 ALTIVEC_BUILTIN_VEC_VADDUWS,
2635 ALTIVEC_BUILTIN_VEC_VAVGSB,
2636 ALTIVEC_BUILTIN_VEC_VAVGSH,
2637 ALTIVEC_BUILTIN_VEC_VAVGSW,
2638 ALTIVEC_BUILTIN_VEC_VAVGUB,
2639 ALTIVEC_BUILTIN_VEC_VAVGUH,
2640 ALTIVEC_BUILTIN_VEC_VAVGUW,
2641 ALTIVEC_BUILTIN_VEC_VCFSX,
2642 ALTIVEC_BUILTIN_VEC_VCFUX,
2643 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2644 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2645 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2646 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2647 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2648 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2649 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2650 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2651 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2652 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2653 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2654 ALTIVEC_BUILTIN_VEC_VMAXFP,
2655 ALTIVEC_BUILTIN_VEC_VMAXSB,
2656 ALTIVEC_BUILTIN_VEC_VMAXSH,
2657 ALTIVEC_BUILTIN_VEC_VMAXSW,
2658 ALTIVEC_BUILTIN_VEC_VMAXUB,
2659 ALTIVEC_BUILTIN_VEC_VMAXUH,
2660 ALTIVEC_BUILTIN_VEC_VMAXUW,
2661 ALTIVEC_BUILTIN_VEC_VMINFP,
2662 ALTIVEC_BUILTIN_VEC_VMINSB,
2663 ALTIVEC_BUILTIN_VEC_VMINSH,
2664 ALTIVEC_BUILTIN_VEC_VMINSW,
2665 ALTIVEC_BUILTIN_VEC_VMINUB,
2666 ALTIVEC_BUILTIN_VEC_VMINUH,
2667 ALTIVEC_BUILTIN_VEC_VMINUW,
2668 ALTIVEC_BUILTIN_VEC_VMRGHB,
2669 ALTIVEC_BUILTIN_VEC_VMRGHH,
2670 ALTIVEC_BUILTIN_VEC_VMRGHW,
2671 ALTIVEC_BUILTIN_VEC_VMRGLB,
2672 ALTIVEC_BUILTIN_VEC_VMRGLH,
2673 ALTIVEC_BUILTIN_VEC_VMRGLW,
2674 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2675 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2676 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2677 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2678 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2679 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2680 ALTIVEC_BUILTIN_VEC_VMULESB,
2681 ALTIVEC_BUILTIN_VEC_VMULESH,
2682 ALTIVEC_BUILTIN_VEC_VMULEUB,
2683 ALTIVEC_BUILTIN_VEC_VMULEUH,
2684 ALTIVEC_BUILTIN_VEC_VMULOSB,
2685 ALTIVEC_BUILTIN_VEC_VMULOSH,
2686 ALTIVEC_BUILTIN_VEC_VMULOUB,
2687 ALTIVEC_BUILTIN_VEC_VMULOUH,
2688 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2689 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2690 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2691 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2692 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2693 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2694 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2695 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2696 ALTIVEC_BUILTIN_VEC_VRLB,
2697 ALTIVEC_BUILTIN_VEC_VRLH,
2698 ALTIVEC_BUILTIN_VEC_VRLW,
2699 ALTIVEC_BUILTIN_VEC_VSLB,
2700 ALTIVEC_BUILTIN_VEC_VSLH,
2701 ALTIVEC_BUILTIN_VEC_VSLW,
2702 ALTIVEC_BUILTIN_VEC_VSPLTB,
2703 ALTIVEC_BUILTIN_VEC_VSPLTH,
2704 ALTIVEC_BUILTIN_VEC_VSPLTW,
2705 ALTIVEC_BUILTIN_VEC_VSRAB,
2706 ALTIVEC_BUILTIN_VEC_VSRAH,
2707 ALTIVEC_BUILTIN_VEC_VSRAW,
2708 ALTIVEC_BUILTIN_VEC_VSRB,
2709 ALTIVEC_BUILTIN_VEC_VSRH,
2710 ALTIVEC_BUILTIN_VEC_VSRW,
2711 ALTIVEC_BUILTIN_VEC_VSUBFP,
2712 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2713 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2714 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2715 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2716 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2717 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2718 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2719 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2720 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2721 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2722 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2723 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2724 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2725 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2726 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2727 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2728 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2729 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2730 ALTIVEC_BUILTIN_VEC_XOR,
2731 ALTIVEC_BUILTIN_VEC_STEP,
2732 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP,
2738 SPE_BUILTIN_EVDIVWS,
2739 SPE_BUILTIN_EVDIVWU,
2741 SPE_BUILTIN_EVFSADD,
2742 SPE_BUILTIN_EVFSDIV,
2743 SPE_BUILTIN_EVFSMUL,
2744 SPE_BUILTIN_EVFSSUB,
2748 SPE_BUILTIN_EVLHHESPLATX,
2749 SPE_BUILTIN_EVLHHOSSPLATX,
2750 SPE_BUILTIN_EVLHHOUSPLATX,
2751 SPE_BUILTIN_EVLWHEX,
2752 SPE_BUILTIN_EVLWHOSX,
2753 SPE_BUILTIN_EVLWHOUX,
2754 SPE_BUILTIN_EVLWHSPLATX,
2755 SPE_BUILTIN_EVLWWSPLATX,
2756 SPE_BUILTIN_EVMERGEHI,
2757 SPE_BUILTIN_EVMERGEHILO,
2758 SPE_BUILTIN_EVMERGELO,
2759 SPE_BUILTIN_EVMERGELOHI,
2760 SPE_BUILTIN_EVMHEGSMFAA,
2761 SPE_BUILTIN_EVMHEGSMFAN,
2762 SPE_BUILTIN_EVMHEGSMIAA,
2763 SPE_BUILTIN_EVMHEGSMIAN,
2764 SPE_BUILTIN_EVMHEGUMIAA,
2765 SPE_BUILTIN_EVMHEGUMIAN,
2766 SPE_BUILTIN_EVMHESMF,
2767 SPE_BUILTIN_EVMHESMFA,
2768 SPE_BUILTIN_EVMHESMFAAW,
2769 SPE_BUILTIN_EVMHESMFANW,
2770 SPE_BUILTIN_EVMHESMI,
2771 SPE_BUILTIN_EVMHESMIA,
2772 SPE_BUILTIN_EVMHESMIAAW,
2773 SPE_BUILTIN_EVMHESMIANW,
2774 SPE_BUILTIN_EVMHESSF,
2775 SPE_BUILTIN_EVMHESSFA,
2776 SPE_BUILTIN_EVMHESSFAAW,
2777 SPE_BUILTIN_EVMHESSFANW,
2778 SPE_BUILTIN_EVMHESSIAAW,
2779 SPE_BUILTIN_EVMHESSIANW,
2780 SPE_BUILTIN_EVMHEUMI,
2781 SPE_BUILTIN_EVMHEUMIA,
2782 SPE_BUILTIN_EVMHEUMIAAW,
2783 SPE_BUILTIN_EVMHEUMIANW,
2784 SPE_BUILTIN_EVMHEUSIAAW,
2785 SPE_BUILTIN_EVMHEUSIANW,
2786 SPE_BUILTIN_EVMHOGSMFAA,
2787 SPE_BUILTIN_EVMHOGSMFAN,
2788 SPE_BUILTIN_EVMHOGSMIAA,
2789 SPE_BUILTIN_EVMHOGSMIAN,
2790 SPE_BUILTIN_EVMHOGUMIAA,
2791 SPE_BUILTIN_EVMHOGUMIAN,
2792 SPE_BUILTIN_EVMHOSMF,
2793 SPE_BUILTIN_EVMHOSMFA,
2794 SPE_BUILTIN_EVMHOSMFAAW,
2795 SPE_BUILTIN_EVMHOSMFANW,
2796 SPE_BUILTIN_EVMHOSMI,
2797 SPE_BUILTIN_EVMHOSMIA,
2798 SPE_BUILTIN_EVMHOSMIAAW,
2799 SPE_BUILTIN_EVMHOSMIANW,
2800 SPE_BUILTIN_EVMHOSSF,
2801 SPE_BUILTIN_EVMHOSSFA,
2802 SPE_BUILTIN_EVMHOSSFAAW,
2803 SPE_BUILTIN_EVMHOSSFANW,
2804 SPE_BUILTIN_EVMHOSSIAAW,
2805 SPE_BUILTIN_EVMHOSSIANW,
2806 SPE_BUILTIN_EVMHOUMI,
2807 SPE_BUILTIN_EVMHOUMIA,
2808 SPE_BUILTIN_EVMHOUMIAAW,
2809 SPE_BUILTIN_EVMHOUMIANW,
2810 SPE_BUILTIN_EVMHOUSIAAW,
2811 SPE_BUILTIN_EVMHOUSIANW,
2812 SPE_BUILTIN_EVMWHSMF,
2813 SPE_BUILTIN_EVMWHSMFA,
2814 SPE_BUILTIN_EVMWHSMI,
2815 SPE_BUILTIN_EVMWHSMIA,
2816 SPE_BUILTIN_EVMWHSSF,
2817 SPE_BUILTIN_EVMWHSSFA,
2818 SPE_BUILTIN_EVMWHUMI,
2819 SPE_BUILTIN_EVMWHUMIA,
2820 SPE_BUILTIN_EVMWLSMIAAW,
2821 SPE_BUILTIN_EVMWLSMIANW,
2822 SPE_BUILTIN_EVMWLSSIAAW,
2823 SPE_BUILTIN_EVMWLSSIANW,
2824 SPE_BUILTIN_EVMWLUMI,
2825 SPE_BUILTIN_EVMWLUMIA,
2826 SPE_BUILTIN_EVMWLUMIAAW,
2827 SPE_BUILTIN_EVMWLUMIANW,
2828 SPE_BUILTIN_EVMWLUSIAAW,
2829 SPE_BUILTIN_EVMWLUSIANW,
2830 SPE_BUILTIN_EVMWSMF,
2831 SPE_BUILTIN_EVMWSMFA,
2832 SPE_BUILTIN_EVMWSMFAA,
2833 SPE_BUILTIN_EVMWSMFAN,
2834 SPE_BUILTIN_EVMWSMI,
2835 SPE_BUILTIN_EVMWSMIA,
2836 SPE_BUILTIN_EVMWSMIAA,
2837 SPE_BUILTIN_EVMWSMIAN,
2838 SPE_BUILTIN_EVMWHSSFAA,
2839 SPE_BUILTIN_EVMWSSF,
2840 SPE_BUILTIN_EVMWSSFA,
2841 SPE_BUILTIN_EVMWSSFAA,
2842 SPE_BUILTIN_EVMWSSFAN,
2843 SPE_BUILTIN_EVMWUMI,
2844 SPE_BUILTIN_EVMWUMIA,
2845 SPE_BUILTIN_EVMWUMIAA,
2846 SPE_BUILTIN_EVMWUMIAN,
2855 SPE_BUILTIN_EVSTDDX,
2856 SPE_BUILTIN_EVSTDHX,
2857 SPE_BUILTIN_EVSTDWX,
2858 SPE_BUILTIN_EVSTWHEX,
2859 SPE_BUILTIN_EVSTWHOX,
2860 SPE_BUILTIN_EVSTWWEX,
2861 SPE_BUILTIN_EVSTWWOX,
2862 SPE_BUILTIN_EVSUBFW,
2865 SPE_BUILTIN_EVADDSMIAAW,
2866 SPE_BUILTIN_EVADDSSIAAW,
2867 SPE_BUILTIN_EVADDUMIAAW,
2868 SPE_BUILTIN_EVADDUSIAAW,
2869 SPE_BUILTIN_EVCNTLSW,
2870 SPE_BUILTIN_EVCNTLZW,
2871 SPE_BUILTIN_EVEXTSB,
2872 SPE_BUILTIN_EVEXTSH,
2873 SPE_BUILTIN_EVFSABS,
2874 SPE_BUILTIN_EVFSCFSF,
2875 SPE_BUILTIN_EVFSCFSI,
2876 SPE_BUILTIN_EVFSCFUF,
2877 SPE_BUILTIN_EVFSCFUI,
2878 SPE_BUILTIN_EVFSCTSF,
2879 SPE_BUILTIN_EVFSCTSI,
2880 SPE_BUILTIN_EVFSCTSIZ,
2881 SPE_BUILTIN_EVFSCTUF,
2882 SPE_BUILTIN_EVFSCTUI,
2883 SPE_BUILTIN_EVFSCTUIZ,
2884 SPE_BUILTIN_EVFSNABS,
2885 SPE_BUILTIN_EVFSNEG,
2889 SPE_BUILTIN_EVSUBFSMIAAW,
2890 SPE_BUILTIN_EVSUBFSSIAAW,
2891 SPE_BUILTIN_EVSUBFUMIAAW,
2892 SPE_BUILTIN_EVSUBFUSIAAW,
2893 SPE_BUILTIN_EVADDIW,
2897 SPE_BUILTIN_EVLHHESPLAT,
2898 SPE_BUILTIN_EVLHHOSSPLAT,
2899 SPE_BUILTIN_EVLHHOUSPLAT,
2901 SPE_BUILTIN_EVLWHOS,
2902 SPE_BUILTIN_EVLWHOU,
2903 SPE_BUILTIN_EVLWHSPLAT,
2904 SPE_BUILTIN_EVLWWSPLAT,
2907 SPE_BUILTIN_EVSRWIS,
2908 SPE_BUILTIN_EVSRWIU,
2912 SPE_BUILTIN_EVSTWHE,
2913 SPE_BUILTIN_EVSTWHO,
2914 SPE_BUILTIN_EVSTWWE,
2915 SPE_BUILTIN_EVSTWWO,
2916 SPE_BUILTIN_EVSUBIFW,
2919 SPE_BUILTIN_EVCMPEQ,
2920 SPE_BUILTIN_EVCMPGTS,
2921 SPE_BUILTIN_EVCMPGTU,
2922 SPE_BUILTIN_EVCMPLTS,
2923 SPE_BUILTIN_EVCMPLTU,
2924 SPE_BUILTIN_EVFSCMPEQ,
2925 SPE_BUILTIN_EVFSCMPGT,
2926 SPE_BUILTIN_EVFSCMPLT,
2927 SPE_BUILTIN_EVFSTSTEQ,
2928 SPE_BUILTIN_EVFSTSTGT,
2929 SPE_BUILTIN_EVFSTSTLT,
2931 /* EVSEL compares. */
2932 SPE_BUILTIN_EVSEL_CMPEQ,
2933 SPE_BUILTIN_EVSEL_CMPGTS,
2934 SPE_BUILTIN_EVSEL_CMPGTU,
2935 SPE_BUILTIN_EVSEL_CMPLTS,
2936 SPE_BUILTIN_EVSEL_CMPLTU,
2937 SPE_BUILTIN_EVSEL_FSCMPEQ,
2938 SPE_BUILTIN_EVSEL_FSCMPGT,
2939 SPE_BUILTIN_EVSEL_FSCMPLT,
2940 SPE_BUILTIN_EVSEL_FSTSTEQ,
2941 SPE_BUILTIN_EVSEL_FSTSTGT,
2942 SPE_BUILTIN_EVSEL_FSTSTLT,
2944 SPE_BUILTIN_EVSPLATFI,
2945 SPE_BUILTIN_EVSPLATI,
2946 SPE_BUILTIN_EVMWHSSMAA,
2947 SPE_BUILTIN_EVMWHSMFAA,
2948 SPE_BUILTIN_EVMWHSMIAA,
2949 SPE_BUILTIN_EVMWHUSIAA,
2950 SPE_BUILTIN_EVMWHUMIAA,
2951 SPE_BUILTIN_EVMWHSSFAN,
2952 SPE_BUILTIN_EVMWHSSIAN,
2953 SPE_BUILTIN_EVMWHSMFAN,
2954 SPE_BUILTIN_EVMWHSMIAN,
2955 SPE_BUILTIN_EVMWHUSIAN,
2956 SPE_BUILTIN_EVMWHUMIAN,
2957 SPE_BUILTIN_EVMWHGSSFAA,
2958 SPE_BUILTIN_EVMWHGSMFAA,
2959 SPE_BUILTIN_EVMWHGSMIAA,
2960 SPE_BUILTIN_EVMWHGUMIAA,
2961 SPE_BUILTIN_EVMWHGSSFAN,
2962 SPE_BUILTIN_EVMWHGSMFAN,
2963 SPE_BUILTIN_EVMWHGSMIAN,
2964 SPE_BUILTIN_EVMWHGUMIAN,
2965 SPE_BUILTIN_MTSPEFSCR,
2966 SPE_BUILTIN_MFSPEFSCR,
2969 /* PAIRED builtins. */
2970 PAIRED_BUILTIN_DIVV2SF3,
2971 PAIRED_BUILTIN_ABSV2SF2,
2972 PAIRED_BUILTIN_NEGV2SF2,
2973 PAIRED_BUILTIN_SQRTV2SF2,
2974 PAIRED_BUILTIN_ADDV2SF3,
2975 PAIRED_BUILTIN_SUBV2SF3,
2976 PAIRED_BUILTIN_RESV2SF2,
2977 PAIRED_BUILTIN_MULV2SF3,
2978 PAIRED_BUILTIN_MSUB,
2979 PAIRED_BUILTIN_MADD,
2980 PAIRED_BUILTIN_NMSUB,
2981 PAIRED_BUILTIN_NMADD,
2982 PAIRED_BUILTIN_NABSV2SF2,
2983 PAIRED_BUILTIN_SUM0,
2984 PAIRED_BUILTIN_SUM1,
2985 PAIRED_BUILTIN_MULS0,
2986 PAIRED_BUILTIN_MULS1,
2987 PAIRED_BUILTIN_MERGE00,
2988 PAIRED_BUILTIN_MERGE01,
2989 PAIRED_BUILTIN_MERGE10,
2990 PAIRED_BUILTIN_MERGE11,
2991 PAIRED_BUILTIN_MADDS0,
2992 PAIRED_BUILTIN_MADDS1,
2995 PAIRED_BUILTIN_SELV2SF4,
2996 PAIRED_BUILTIN_CMPU0,
2997 PAIRED_BUILTIN_CMPU1,
2999 RS6000_BUILTIN_RECIP,
3000 RS6000_BUILTIN_RECIPF,
3001 RS6000_BUILTIN_RSQRTF,
3003 RS6000_BUILTIN_COUNT
3006 enum rs6000_builtin_type_index
3008 RS6000_BTI_NOT_OPAQUE,
3009 RS6000_BTI_opaque_V2SI,
3010 RS6000_BTI_opaque_V2SF,
3011 RS6000_BTI_opaque_p_V2SI,
3012 RS6000_BTI_opaque_V4SI,
3020 RS6000_BTI_unsigned_V16QI,
3021 RS6000_BTI_unsigned_V8HI,
3022 RS6000_BTI_unsigned_V4SI,
3023 RS6000_BTI_bool_char, /* __bool char */
3024 RS6000_BTI_bool_short, /* __bool short */
3025 RS6000_BTI_bool_int, /* __bool int */
3026 RS6000_BTI_pixel, /* __pixel */
3027 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3028 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3029 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3030 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3031 RS6000_BTI_long, /* long_integer_type_node */
3032 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3033 RS6000_BTI_INTQI, /* intQI_type_node */
3034 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3035 RS6000_BTI_INTHI, /* intHI_type_node */
3036 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3037 RS6000_BTI_INTSI, /* intSI_type_node */
3038 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3039 RS6000_BTI_float, /* float_type_node */
3040 RS6000_BTI_void, /* void_type_node */
3045 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3046 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3047 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3048 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3049 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3050 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3051 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3052 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3053 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3054 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3055 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3056 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3057 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3058 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3059 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3060 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3061 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3062 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3063 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3064 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3065 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3066 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3068 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3069 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3070 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3071 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3072 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3073 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3074 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3075 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3076 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3077 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3079 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3080 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];