1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common ASM definitions used by ASM_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define ASM_CPU_SPEC \
53 %{mpower: %{!mpower2: -mpwr}} \
56 %{mno-power: %{!mpowerpc*: -mcom}} \
57 %{!mno-power: %{!mpower2: %(asm_default)}}} \
58 %{mcpu=common: -mcom} \
59 %{mcpu=power: -mpwr} \
60 %{mcpu=power2: -mpwrx} \
61 %{mcpu=power3: -m604} \
62 %{mcpu=power4: -mpower4} \
63 %{mcpu=powerpc: -mppc} \
65 %{mcpu=rios1: -mpwr} \
66 %{mcpu=rios2: -mpwrx} \
78 %{mcpu=ec603e: -mppc} \
91 %{mcpu=8540: -me500} \
92 %{maltivec: -maltivec}"
94 #define CPP_DEFAULT_SPEC ""
96 #define ASM_DEFAULT_SPEC ""
98 /* This macro defines names of additional specifications to put in the specs
99 that can be used in various specifications like CC1_SPEC. Its definition
100 is an initializer with a subgrouping for each command option.
102 Each subgrouping contains a string constant, that defines the
103 specification name, and a string constant that used by the GNU CC driver
106 Do not define this macro if it does not need to do anything. */
108 #define SUBTARGET_EXTRA_SPECS
110 #define EXTRA_SPECS \
111 { "cpp_default", CPP_DEFAULT_SPEC }, \
112 { "asm_cpu", ASM_CPU_SPEC }, \
113 { "asm_default", ASM_DEFAULT_SPEC }, \
114 SUBTARGET_EXTRA_SPECS
116 /* Architecture type. */
118 extern int target_flags;
120 /* Use POWER architecture instructions and MQ register. */
121 #define MASK_POWER 0x00000001
123 /* Use POWER2 extensions to POWER architecture. */
124 #define MASK_POWER2 0x00000002
126 /* Use PowerPC architecture instructions. */
127 #define MASK_POWERPC 0x00000004
129 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
130 #define MASK_PPC_GPOPT 0x00000008
132 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
133 #define MASK_PPC_GFXOPT 0x00000010
135 /* Use PowerPC-64 architecture instructions. */
136 #define MASK_POWERPC64 0x00000020
138 /* Use revised mnemonic names defined for PowerPC architecture. */
139 #define MASK_NEW_MNEMONICS 0x00000040
141 /* Disable placing fp constants in the TOC; can be turned on when the
143 #define MASK_NO_FP_IN_TOC 0x00000080
145 /* Disable placing symbol+offset constants in the TOC; can be turned on when
146 the TOC overflows. */
147 #define MASK_NO_SUM_IN_TOC 0x00000100
149 /* Output only one TOC entry per module. Normally linking fails if
150 there are more than 16K unique variables/constants in an executable. With
151 this option, linking fails only if there are more than 16K modules, or
152 if there are more than 16K unique variables/constant in a single module.
154 This is at the cost of having 2 extra loads and one extra store per
155 function, and one less allocable register. */
156 #define MASK_MINIMAL_TOC 0x00000200
158 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
159 #define MASK_64BIT 0x00000400
161 /* Disable use of FPRs. */
162 #define MASK_SOFT_FLOAT 0x00000800
164 /* Enable load/store multiple, even on PowerPC */
165 #define MASK_MULTIPLE 0x00001000
167 /* Use string instructions for block moves */
168 #define MASK_STRING 0x00002000
170 /* Disable update form of load/store */
171 #define MASK_NO_UPDATE 0x00004000
173 /* Disable fused multiply/add operations */
174 #define MASK_NO_FUSED_MADD 0x00008000
176 /* Nonzero if we need to schedule the prolog and epilog. */
177 #define MASK_SCHED_PROLOG 0x00010000
179 /* Use AltiVec instructions. */
180 #define MASK_ALTIVEC 0x00020000
182 /* Return small structures in memory (as the AIX ABI requires). */
183 #define MASK_AIX_STRUCT_RET 0x00040000
185 /* The only remaining free bits are 0x00780000. sysv4.h uses
186 0x00800000 -> 0x40000000, and 0x80000000 is not available
187 because target_flags is signed. */
189 #define TARGET_POWER (target_flags & MASK_POWER)
190 #define TARGET_POWER2 (target_flags & MASK_POWER2)
191 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
192 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
193 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
194 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
195 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
196 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
197 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
198 #define TARGET_64BIT (target_flags & MASK_64BIT)
199 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
200 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
201 #define TARGET_STRING (target_flags & MASK_STRING)
202 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
203 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
204 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
205 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
206 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
208 #define TARGET_32BIT (! TARGET_64BIT)
209 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
210 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
211 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
214 /* For libgcc2 we make sure this is a compile time constant */
215 #if defined (__64BIT__) || defined (__powerpc64__)
216 #define TARGET_POWERPC64 1
218 #define TARGET_POWERPC64 0
221 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
224 #define TARGET_XL_CALL 0
226 /* Run-time compilation parameters selecting different hardware subsets.
228 Macro to define tables used to set the flags.
229 This is a list in braces of pairs in braces,
230 each pair being { "NAME", VALUE }
231 where VALUE is the bits to set or minus the bits to clear.
232 An empty string NAME is used to identify the default VALUE. */
234 #define TARGET_SWITCHES \
235 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
236 N_("Use POWER instruction set")}, \
237 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
239 N_("Use POWER2 instruction set")}, \
240 {"no-power2", - MASK_POWER2, \
241 N_("Do not use POWER2 instruction set")}, \
242 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
244 N_("Do not use POWER instruction set")}, \
245 {"powerpc", MASK_POWERPC, \
246 N_("Use PowerPC instruction set")}, \
247 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
248 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
249 N_("Do not use PowerPC instruction set")}, \
250 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
251 N_("Use PowerPC General Purpose group optional instructions")},\
252 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
253 N_("Don't use PowerPC General Purpose group optional instructions")},\
254 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
255 N_("Use PowerPC Graphics group optional instructions")},\
256 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
257 N_("Don't use PowerPC Graphics group optional instructions")},\
258 {"powerpc64", MASK_POWERPC64, \
259 N_("Use PowerPC-64 instruction set")}, \
260 {"no-powerpc64", - MASK_POWERPC64, \
261 N_("Don't use PowerPC-64 instruction set")}, \
262 {"altivec", MASK_ALTIVEC , \
263 N_("Use AltiVec instructions")}, \
264 {"no-altivec", - MASK_ALTIVEC , \
265 N_("Don't use AltiVec instructions")}, \
266 {"new-mnemonics", MASK_NEW_MNEMONICS, \
267 N_("Use new mnemonics for PowerPC architecture")},\
268 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
269 N_("Use old mnemonics for PowerPC architecture")},\
270 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
271 | MASK_MINIMAL_TOC), \
272 N_("Put everything in the regular TOC")}, \
273 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
274 N_("Place floating point constants in TOC")}, \
275 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
276 N_("Don't place floating point constants in TOC")},\
277 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
278 N_("Place symbol+offset constants in TOC")}, \
279 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
280 N_("Don't place symbol+offset constants in TOC")},\
281 {"minimal-toc", MASK_MINIMAL_TOC, \
282 "Use only one TOC entry per procedure"}, \
283 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
285 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
286 N_("Place variable addresses in the regular TOC")},\
287 {"hard-float", - MASK_SOFT_FLOAT, \
288 N_("Use hardware fp")}, \
289 {"soft-float", MASK_SOFT_FLOAT, \
290 N_("Do not use hardware fp")}, \
291 {"multiple", MASK_MULTIPLE, \
292 N_("Generate load/store multiple instructions")}, \
293 {"no-multiple", - MASK_MULTIPLE, \
294 N_("Do not generate load/store multiple instructions")},\
295 {"string", MASK_STRING, \
296 N_("Generate string instructions for block moves")},\
297 {"no-string", - MASK_STRING, \
298 N_("Do not generate string instructions for block moves")},\
299 {"update", - MASK_NO_UPDATE, \
300 N_("Generate load/store with update instructions")},\
301 {"no-update", MASK_NO_UPDATE, \
302 N_("Do not generate load/store with update instructions")},\
303 {"fused-madd", - MASK_NO_FUSED_MADD, \
304 N_("Generate fused multiply/add instructions")},\
305 {"no-fused-madd", MASK_NO_FUSED_MADD, \
306 N_("Don't generate fused multiply/add instructions")},\
307 {"sched-prolog", MASK_SCHED_PROLOG, \
309 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
310 N_("Don't schedule the start and end of the procedure")},\
311 {"sched-epilog", MASK_SCHED_PROLOG, \
313 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
315 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
316 N_("Return all structures in memory (AIX default)")},\
317 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
318 N_("Return small structures in registers (SVR4 default)")},\
319 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
321 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
324 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
327 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
329 /* This is meant to be redefined in the host dependent files */
330 #define SUBTARGET_SWITCHES
332 /* Processor type. Order must match cpu attribute in MD file. */
355 extern enum processor_type rs6000_cpu;
357 /* Recast the processor type to the cpu attribute. */
358 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
360 /* Define generic processor types based upon current deployment. */
361 #define PROCESSOR_COMMON PROCESSOR_PPC601
362 #define PROCESSOR_POWER PROCESSOR_RIOS1
363 #define PROCESSOR_POWERPC PROCESSOR_PPC604
364 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
366 /* Define the default processor. This is overridden by other tm.h files. */
367 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
368 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
370 /* Specify the dialect of assembler to use. New mnemonics is dialect one
371 and the old mnemonics are dialect zero. */
372 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
374 /* This is meant to be overridden in target specific files. */
375 #define SUBTARGET_OPTIONS
377 #define TARGET_OPTIONS \
379 {"cpu=", &rs6000_select[1].string, \
380 N_("Use features of and schedule code for given CPU") }, \
381 {"tune=", &rs6000_select[2].string, \
382 N_("Schedule code for given CPU") }, \
383 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
384 {"traceback=", &rs6000_traceback_name, \
385 N_("Select full, part, or no traceback table") }, \
386 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
387 {"long-double-", &rs6000_long_double_size_string, \
388 N_("Specify size of long double (64 or 128 bits)") }, \
389 {"isel=", &rs6000_isel_string, \
390 N_("Specify yes/no if isel instructions should be generated") }, \
391 {"spe=", &rs6000_spe_string, \
392 N_("Specify yes/no if SPE SIMD instructions should be generated") },\
393 {"vrsave=", &rs6000_altivec_vrsave_string, \
394 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
395 {"longcall", &rs6000_longcall_switch, \
396 N_("Avoid all range limits on call instructions") }, \
397 {"no-longcall", &rs6000_longcall_switch, "" }, \
401 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
402 struct rs6000_cpu_select
410 extern struct rs6000_cpu_select rs6000_select[];
413 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
414 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
415 extern int rs6000_debug_stack; /* debug stack applications */
416 extern int rs6000_debug_arg; /* debug argument handling */
418 #define TARGET_DEBUG_STACK rs6000_debug_stack
419 #define TARGET_DEBUG_ARG rs6000_debug_arg
421 extern const char *rs6000_traceback_name; /* Type of traceback table. */
423 /* These are separate from target_flags because we've run out of bits
425 extern const char *rs6000_long_double_size_string;
426 extern int rs6000_long_double_type_size;
427 extern int rs6000_altivec_abi;
428 extern int rs6000_spe_abi;
429 extern int rs6000_isel;
430 extern int rs6000_spe;
431 extern int rs6000_fprs;
432 extern const char *rs6000_isel_string;
433 extern const char *rs6000_spe_string;
434 extern const char *rs6000_altivec_vrsave_string;
435 extern int rs6000_altivec_vrsave;
436 extern const char *rs6000_longcall_switch;
437 extern int rs6000_default_long_calls;
439 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
440 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
441 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
443 #define TARGET_SPE_ABI 0
445 #define TARGET_E500 0
446 #define TARGET_ISEL 0
447 #define TARGET_FPRS 1
449 /* Sometimes certain combinations of command options do not make sense
450 on a particular target machine. You can define a macro
451 `OVERRIDE_OPTIONS' to take account of this. This macro, if
452 defined, is executed once just after all the command options have
455 Don't use this macro to turn on various extra optimizations for
456 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
458 On the RS/6000 this is used to define the target cpu type. */
460 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
462 /* Define this to change the optimizations performed by default. */
463 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
465 /* Show we can debug even without a frame pointer. */
466 #define CAN_DEBUG_WITHOUT_FP
469 #define REGISTER_TARGET_PRAGMAS() do { \
470 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
473 /* Target #defines. */
474 #define TARGET_CPU_CPP_BUILTINS() \
475 rs6000_cpu_cpp_builtins (pfile)
477 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
478 we're compiling for. Some configurations may need to override it. */
479 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
482 if (BYTES_BIG_ENDIAN) \
484 builtin_define ("__BIG_ENDIAN__"); \
485 builtin_define ("_BIG_ENDIAN"); \
486 builtin_assert ("machine=bigendian"); \
490 builtin_define ("__LITTLE_ENDIAN__"); \
491 builtin_define ("_LITTLE_ENDIAN"); \
492 builtin_assert ("machine=littleendian"); \
497 /* Target machine storage layout. */
499 /* Define this macro if it is advisable to hold scalars in registers
500 in a wider mode than that declared by the program. In such cases,
501 the value is constrained to be within the bounds of the declared
502 type, but kept valid in the wider mode. The signedness of the
503 extension may differ from that of the type. */
505 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
506 if (GET_MODE_CLASS (MODE) == MODE_INT \
507 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
510 /* Define this if function arguments should also be promoted using the above
513 #define PROMOTE_FUNCTION_ARGS
515 /* Likewise, if the function return value is promoted. */
517 #define PROMOTE_FUNCTION_RETURN
519 /* Define this if most significant bit is lowest numbered
520 in instructions that operate on numbered bit-fields. */
521 /* That is true on RS/6000. */
522 #define BITS_BIG_ENDIAN 1
524 /* Define this if most significant byte of a word is the lowest numbered. */
525 /* That is true on RS/6000. */
526 #define BYTES_BIG_ENDIAN 1
528 /* Define this if most significant word of a multiword number is lowest
531 For RS/6000 we can decide arbitrarily since there are no machine
532 instructions for them. Might as well be consistent with bits and bytes. */
533 #define WORDS_BIG_ENDIAN 1
535 #define MAX_BITS_PER_WORD 64
537 /* Width of a word, in units (bytes). */
538 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
540 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
542 #define MIN_UNITS_PER_WORD 4
544 #define UNITS_PER_FP_WORD 8
545 #define UNITS_PER_ALTIVEC_WORD 16
546 #define UNITS_PER_SPE_WORD 8
548 /* Type used for ptrdiff_t, as a string used in a declaration. */
549 #define PTRDIFF_TYPE "int"
551 /* Type used for size_t, as a string used in a declaration. */
552 #define SIZE_TYPE "long unsigned int"
554 /* Type used for wchar_t, as a string used in a declaration. */
555 #define WCHAR_TYPE "short unsigned int"
557 /* Width of wchar_t in bits. */
558 #define WCHAR_TYPE_SIZE 16
560 /* A C expression for the size in bits of the type `short' on the
561 target machine. If you don't define this, the default is half a
562 word. (If this would be less than one storage unit, it is
563 rounded up to one unit.) */
564 #define SHORT_TYPE_SIZE 16
566 /* A C expression for the size in bits of the type `int' on the
567 target machine. If you don't define this, the default is one
569 #define INT_TYPE_SIZE 32
571 /* A C expression for the size in bits of the type `long' on the
572 target machine. If you don't define this, the default is one
574 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
575 #define MAX_LONG_TYPE_SIZE 64
577 /* A C expression for the size in bits of the type `long long' on the
578 target machine. If you don't define this, the default is two
580 #define LONG_LONG_TYPE_SIZE 64
582 /* A C expression for the size in bits of the type `float' on the
583 target machine. If you don't define this, the default is one
585 #define FLOAT_TYPE_SIZE 32
587 /* A C expression for the size in bits of the type `double' on the
588 target machine. If you don't define this, the default is two
590 #define DOUBLE_TYPE_SIZE 64
592 /* A C expression for the size in bits of the type `long double' on
593 the target machine. If you don't define this, the default is two
595 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
597 /* Constant which presents upper bound of the above value. */
598 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
600 /* Define this to set long double type size to use in libgcc2.c, which can
601 not depend on target_flags. */
602 #ifdef __LONG_DOUBLE_128__
603 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
605 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
608 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
609 #define WIDEST_HARDWARE_FP_SIZE 64
611 /* Width in bits of a pointer.
612 See also the macro `Pmode' defined below. */
613 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
615 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
616 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
618 /* Boundary (in *bits*) on which stack pointer should be aligned. */
619 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
621 /* Allocation boundary (in *bits*) for the code of a function. */
622 #define FUNCTION_BOUNDARY 32
624 /* No data type wants to be aligned rounder than this. */
625 #define BIGGEST_ALIGNMENT 128
627 /* A C expression to compute the alignment for a variables in the
628 local store. TYPE is the data type, and ALIGN is the alignment
629 that the object would ordinarily have. */
630 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
631 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
632 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
634 /* Alignment of field after `int : 0' in a structure. */
635 #define EMPTY_FIELD_BOUNDARY 32
637 /* Every structure's size must be a multiple of this. */
638 #define STRUCTURE_SIZE_BOUNDARY 8
640 /* Return 1 if a structure or array containing FIELD should be
641 accessed using `BLKMODE'.
643 For the SPE, simd types are V2SI, and gcc can be tempted to put the
644 entire thing in a DI and use subregs to access the internals.
645 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
646 back-end. Because a single GPR can hold a V2SI, but not a DI, the
647 best thing to do is set structs to BLKmode and avoid Severe Tire
649 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
650 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
652 /* A bit-field declared as `int' forces `int' alignment for the struct. */
653 #define PCC_BITFIELD_TYPE_MATTERS 1
655 /* Make strings word-aligned so strcpy from constants will be faster.
656 Make vector constants quadword aligned. */
657 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
658 (TREE_CODE (EXP) == STRING_CST \
659 && (ALIGN) < BITS_PER_WORD \
663 /* Make arrays of chars word-aligned for the same reasons.
664 Align vectors to 128 bits. */
665 #define DATA_ALIGNMENT(TYPE, ALIGN) \
666 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
667 : TREE_CODE (TYPE) == ARRAY_TYPE \
668 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
669 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
671 /* Nonzero if move instructions will actually fail to work
672 when given unaligned data. */
673 #define STRICT_ALIGNMENT 0
675 /* Define this macro to be the value 1 if unaligned accesses have a cost
676 many times greater than aligned accesses, for example if they are
677 emulated in a trap handler. */
678 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
680 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
681 || (MODE) == DImode) \
684 /* Standard register usage. */
686 /* Number of actual hardware registers.
687 The hardware registers are assigned numbers for the compiler
688 from 0 to just below FIRST_PSEUDO_REGISTER.
689 All registers that the compiler knows about must be given numbers,
690 even those that are not normally considered general registers.
692 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
693 an MQ register, a count register, a link register, and 8 condition
694 register fields, which we view here as separate registers. AltiVec
695 adds 32 vector registers and a VRsave register.
697 In addition, the difference between the frame and argument pointers is
698 a function of the number of registers saved, so we need to have a
699 register for AP that will later be eliminated in favor of SP or FP.
700 This is a normal register, but it is fixed.
702 We also create a pseudo register for float/int conversions, that will
703 really represent the memory location used. It is represented here as
704 a register, in order to work around problems in allocating stack storage
705 in inline functions. */
707 #define FIRST_PSEUDO_REGISTER 113
709 /* This must be included for pre gcc 3.0 glibc compatibility. */
710 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
712 /* Add 32 dwarf columns for synthetic SPE registers. The SPE
713 synthetic registers are 113 through 145. */
714 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
716 /* The SPE has an additional 32 synthetic registers starting at 1200.
717 We must map them here to sane values in the unwinder to avoid a
718 huge hole in the unwind tables.
720 FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
721 the VRSAVE SPR (SPR256) assigned to register 356. When AltiVec EH
722 is verified to be working, this macro should be changed
724 #define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
726 /* 1 for registers that have pervasive standard uses
727 and are not available for the register allocator.
729 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
730 as a local register; for all other OS's r2 is the TOC pointer.
732 cr5 is not supposed to be used.
734 On System V implementations, r13 is fixed and not available for use. */
736 #define FIXED_REGISTERS \
737 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
739 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
741 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
742 /* AltiVec registers. */ \
743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
749 /* 1 for registers not available across function calls.
750 These must include the FIXED_REGISTERS and also any
751 registers that can be used without being saved.
752 The latter must include the registers where values are returned
753 and the register where structure-value addresses are passed.
754 Aside from that, you can include as many other registers as you like. */
756 #define CALL_USED_REGISTERS \
757 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
758 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
759 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
761 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
762 /* AltiVec registers. */ \
763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
769 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
770 the entire set of `FIXED_REGISTERS' be included.
771 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
772 This macro is optional. If not specified, it defaults to the value
773 of `CALL_USED_REGISTERS'. */
775 #define CALL_REALLY_USED_REGISTERS \
776 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
777 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
778 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
779 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
780 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
781 /* AltiVec registers. */ \
782 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
783 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
794 #define MAX_CR_REGNO 75
796 #define FIRST_ALTIVEC_REGNO 77
797 #define LAST_ALTIVEC_REGNO 108
798 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
799 #define VRSAVE_REGNO 109
800 #define VSCR_REGNO 110
801 #define SPE_ACC_REGNO 111
802 #define SPEFSCR_REGNO 112
804 /* List the order in which to allocate registers. Each register must be
805 listed once, even those in FIXED_REGISTERS.
807 We allocate in the following order:
808 fp0 (not saved or used for anything)
809 fp13 - fp2 (not saved; incoming fp arg registers)
810 fp1 (not saved; return value)
811 fp31 - fp14 (saved; order given to save least number)
812 cr7, cr6 (not saved or special)
813 cr1 (not saved, but used for FP operations)
814 cr0 (not saved, but used for arithmetic operations)
815 cr4, cr3, cr2 (saved)
816 r0 (not saved; cannot be base reg)
817 r9 (not saved; best for TImode)
818 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
819 r3 (not saved; return value register)
820 r31 - r13 (saved; order given to save least number)
821 r12 (not saved; if used for DImode or DFmode would use r13)
822 mq (not saved; best to use it if we can)
823 ctr (not saved; when we have the choice ctr is better)
825 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
826 spe_acc, spefscr (fixed)
829 v0 - v1 (not saved or used for anything)
830 v13 - v3 (not saved; incoming vector arg registers)
831 v2 (not saved; incoming vector arg reg; return value)
832 v19 - v14 (not saved or used for anything)
833 v31 - v20 (saved; order given to save least number)
837 #define MAYBE_R2_AVAILABLE
838 #define MAYBE_R2_FIXED 2,
840 #define MAYBE_R2_AVAILABLE 2,
841 #define MAYBE_R2_FIXED
844 #define REG_ALLOC_ORDER \
846 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
848 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
849 50, 49, 48, 47, 46, \
850 75, 74, 69, 68, 72, 71, 70, \
851 0, MAYBE_R2_AVAILABLE \
852 9, 11, 10, 8, 7, 6, 5, 4, \
854 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
855 18, 17, 16, 15, 14, 13, 12, \
857 73, 1, MAYBE_R2_FIXED 67, 76, \
858 /* AltiVec registers. */ \
860 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
862 96, 95, 94, 93, 92, 91, \
863 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
868 /* True if register is floating-point. */
869 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
871 /* True if register is a condition register. */
872 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
874 /* True if register is a condition register, but not cr0. */
875 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
877 /* True if register is an integer register. */
878 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
880 /* SPE SIMD registers are just the GPRs. */
881 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
883 /* True if register is the XER register. */
884 #define XER_REGNO_P(N) ((N) == XER_REGNO)
886 /* True if register is an AltiVec register. */
887 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
889 /* Return number of consecutive hard regs needed starting at reg REGNO
890 to hold something of mode MODE.
891 This is ordinarily the length in words of a value of mode MODE
892 but can be less for certain modes in special long registers.
894 For the SPE, GPRs are 64 bits but only 32 bits are visible in
895 scalar instructions. The upper 32 bits are only available to the
898 POWER and PowerPC GPRs hold 32 bits worth;
899 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
901 #define HARD_REGNO_NREGS(REGNO, MODE) \
902 (FP_REGNO_P (REGNO) \
903 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
904 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
905 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
906 : ALTIVEC_REGNO_P (REGNO) \
907 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
908 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
910 #define ALTIVEC_VECTOR_MODE(MODE) \
911 ((MODE) == V16QImode \
912 || (MODE) == V8HImode \
913 || (MODE) == V4SFmode \
914 || (MODE) == V4SImode)
916 #define SPE_VECTOR_MODE(MODE) \
917 ((MODE) == V4HImode \
918 || (MODE) == V2SFmode \
919 || (MODE) == V1DImode \
920 || (MODE) == V2SImode)
922 /* Define this macro to be nonzero if the port is prepared to handle
923 insns involving vector mode MODE. At the very least, it must have
924 move patterns for this mode. */
926 #define VECTOR_MODE_SUPPORTED_P(MODE) \
927 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
928 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
930 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
931 For POWER and PowerPC, the GPRs can hold any mode, but values bigger
932 than one register cannot go past R31. The float
933 registers only can hold floating modes and DImode, and CR register only
934 can hold CC modes. We cannot put TImode anywhere except general
935 register and it must be able to fit within the register set. */
937 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
938 (INT_REGNO_P (REGNO) ? \
939 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
940 : FP_REGNO_P (REGNO) ? \
941 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
942 || (GET_MODE_CLASS (MODE) == MODE_INT \
943 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
944 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
945 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
946 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
947 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
948 : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
950 /* Value is 1 if it is a good idea to tie two pseudo registers
951 when one has mode MODE1 and one has mode MODE2.
952 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
953 for any hard reg, then this must be 0 for correct output. */
954 #define MODES_TIEABLE_P(MODE1, MODE2) \
955 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
956 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
957 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
958 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
959 : GET_MODE_CLASS (MODE1) == MODE_CC \
960 ? GET_MODE_CLASS (MODE2) == MODE_CC \
961 : GET_MODE_CLASS (MODE2) == MODE_CC \
962 ? GET_MODE_CLASS (MODE1) == MODE_CC \
963 : ALTIVEC_VECTOR_MODE (MODE1) \
964 ? ALTIVEC_VECTOR_MODE (MODE2) \
965 : ALTIVEC_VECTOR_MODE (MODE2) \
966 ? ALTIVEC_VECTOR_MODE (MODE1) \
969 /* Post-reload, we can't use any new AltiVec registers, as we already
970 emitted the vrsave mask. */
972 #define HARD_REGNO_RENAME_OK(SRC, DST) \
973 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
975 /* A C expression returning the cost of moving data from a register of class
976 CLASS1 to one of CLASS2. */
978 #define REGISTER_MOVE_COST rs6000_register_move_cost
980 /* A C expressions returning the cost of moving data of MODE from a register to
983 #define MEMORY_MOVE_COST rs6000_memory_move_cost
985 /* Specify the cost of a branch insn; roughly the number of extra insns that
986 should be added to avoid a branch.
988 Set this to 3 on the RS/6000 since that is roughly the average cost of an
989 unscheduled conditional branch. */
991 #define BRANCH_COST 3
994 /* A fixed register used at prologue and epilogue generation to fix
995 addressing modes. The SPE needs heavy addressing fixes at the last
996 minute, and it's best to save a register for it.
998 AltiVec also needs fixes, but we've gotten around using r11, which
999 is actually wrong because when use_backchain_to_restore_sp is true,
1000 we end up clobbering r11.
1002 The AltiVec case needs to be fixed. Dunno if we should break ABI
1003 compatibility and reserve a register for it as well.. */
1005 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1007 /* Define this macro to change register usage conditional on target flags.
1008 Set MQ register fixed (already call_used) if not POWER architecture
1009 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
1010 64-bit AIX reserves GPR13 for thread-private data.
1011 Conditionally disable FPRs. */
1013 #define CONDITIONAL_REGISTER_USAGE \
1016 if (! TARGET_POWER) \
1017 fixed_regs[64] = 1; \
1019 fixed_regs[13] = call_used_regs[13] \
1020 = call_really_used_regs[13] = 1; \
1021 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
1022 for (i = 32; i < 64; i++) \
1023 fixed_regs[i] = call_used_regs[i] \
1024 = call_really_used_regs[i] = 1; \
1025 if (DEFAULT_ABI == ABI_V4 \
1026 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1028 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1029 if (DEFAULT_ABI == ABI_V4 \
1030 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1032 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1033 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1034 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1035 if (DEFAULT_ABI == ABI_DARWIN \
1036 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1037 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1038 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1039 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1040 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1041 if (TARGET_ALTIVEC) \
1042 global_regs[VSCR_REGNO] = 1; \
1045 global_regs[SPEFSCR_REGNO] = 1; \
1046 fixed_regs[FIXED_SCRATCH] \
1047 = call_used_regs[FIXED_SCRATCH] \
1048 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1050 if (! TARGET_ALTIVEC) \
1052 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1053 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1054 call_really_used_regs[VRSAVE_REGNO] = 1; \
1056 if (TARGET_ALTIVEC_ABI) \
1057 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1058 call_used_regs[i] = call_really_used_regs[i] = 1; \
1061 /* Specify the registers used for certain standard purposes.
1062 The values of these macros are register numbers. */
1064 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1065 /* #define PC_REGNUM */
1067 /* Register to use for pushing function arguments. */
1068 #define STACK_POINTER_REGNUM 1
1070 /* Base register for access to local variables of the function. */
1071 #define FRAME_POINTER_REGNUM 31
1073 /* Value should be nonzero if functions must have frame pointers.
1074 Zero means the frame pointer need not be set up (and parms
1075 may be accessed via the stack pointer) in functions that seem suitable.
1076 This is computed in `reload', in reload1.c. */
1077 #define FRAME_POINTER_REQUIRED 0
1079 /* Base register for access to arguments of the function. */
1080 #define ARG_POINTER_REGNUM 67
1082 /* Place to put static chain when calling a function that requires it. */
1083 #define STATIC_CHAIN_REGNUM 11
1085 /* Link register number. */
1086 #define LINK_REGISTER_REGNUM 65
1088 /* Count register number. */
1089 #define COUNT_REGISTER_REGNUM 66
1091 /* Place that structure value return address is placed.
1093 On the RS/6000, it is passed as an extra parameter. */
1094 #define STRUCT_VALUE 0
1096 /* Define the classes of registers for register constraints in the
1097 machine description. Also define ranges of constants.
1099 One of the classes must always be named ALL_REGS and include all hard regs.
1100 If there is more than one class, another class must be named NO_REGS
1101 and contain no registers.
1103 The name GENERAL_REGS must be the name of a class (or an alias for
1104 another name such as ALL_REGS). This is the class of registers
1105 that is allowed by "g" or "r" in a register constraint.
1106 Also, registers outside this class are allocated only when
1107 instructions express preferences for them.
1109 The classes must be numbered in nondecreasing order; that is,
1110 a larger-numbered class must never be contained completely
1111 in a smaller-numbered class.
1113 For any two classes, it is very desirable that there be another
1114 class that represents their union. */
1116 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1117 and condition registers, plus three special registers, MQ, CTR, and the
1118 link register. AltiVec adds a vector register class.
1120 However, r0 is special in that it cannot be used as a base register.
1121 So make a class for registers valid as base registers.
1123 Also, cr0 is the only condition code register that can be used in
1124 arithmetic insns, so make a separate class for it. */
1152 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1154 /* Give names of register classes as strings for dump file. */
1156 #define REG_CLASS_NAMES \
1167 "NON_SPECIAL_REGS", \
1171 "LINK_OR_CTR_REGS", \
1173 "SPEC_OR_GEN_REGS", \
1181 /* Define which registers fit in which classes.
1182 This is an initializer for a vector of HARD_REG_SET
1183 of length N_REG_CLASSES. */
1185 #define REG_CLASS_CONTENTS \
1187 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1188 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1189 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1190 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1191 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1192 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1193 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1194 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1195 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1196 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1197 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1198 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1199 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1200 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1201 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1202 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1203 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1204 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1205 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1206 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1207 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1210 /* The same information, inverted:
1211 Return the class number of the smallest class containing
1212 reg number REGNO. This could be a conditional expression
1213 or could index an array. */
1215 #define REGNO_REG_CLASS(REGNO) \
1216 ((REGNO) == 0 ? GENERAL_REGS \
1217 : (REGNO) < 32 ? BASE_REGS \
1218 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1219 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1220 : (REGNO) == CR0_REGNO ? CR0_REGS \
1221 : CR_REGNO_P (REGNO) ? CR_REGS \
1222 : (REGNO) == MQ_REGNO ? MQ_REGS \
1223 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1224 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1225 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1226 : (REGNO) == XER_REGNO ? XER_REGS \
1227 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1228 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1229 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1230 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1233 /* The class value for index registers, and the one for base regs. */
1234 #define INDEX_REG_CLASS GENERAL_REGS
1235 #define BASE_REG_CLASS BASE_REGS
1237 /* Get reg_class from a letter such as appears in the machine description. */
1239 #define REG_CLASS_FROM_LETTER(C) \
1240 ((C) == 'f' ? FLOAT_REGS \
1241 : (C) == 'b' ? BASE_REGS \
1242 : (C) == 'h' ? SPECIAL_REGS \
1243 : (C) == 'q' ? MQ_REGS \
1244 : (C) == 'c' ? CTR_REGS \
1245 : (C) == 'l' ? LINK_REGS \
1246 : (C) == 'v' ? ALTIVEC_REGS \
1247 : (C) == 'x' ? CR0_REGS \
1248 : (C) == 'y' ? CR_REGS \
1249 : (C) == 'z' ? XER_REGS \
1252 /* The letters I, J, K, L, M, N, and P in a register constraint string
1253 can be used to stand for particular ranges of immediate operands.
1254 This macro defines what the ranges are.
1255 C is the letter, and VALUE is a constant value.
1256 Return 1 if VALUE is in the range specified by C.
1258 `I' is a signed 16-bit constant
1259 `J' is a constant with only the high-order 16 bits nonzero
1260 `K' is a constant with only the low-order 16 bits nonzero
1261 `L' is a signed 16-bit constant shifted left 16 bits
1262 `M' is a constant that is greater than 31
1263 `N' is a positive constant that is an exact power of two
1264 `O' is the constant zero
1265 `P' is a constant whose negation is a signed 16-bit constant */
1267 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1268 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1269 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1270 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1271 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1272 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1273 : (C) == 'M' ? (VALUE) > 31 \
1274 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1275 : (C) == 'O' ? (VALUE) == 0 \
1276 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1279 /* Similar, but for floating constants, and defining letters G and H.
1280 Here VALUE is the CONST_DOUBLE rtx itself.
1282 We flag for special constants when we can copy the constant into
1283 a general register in two insns for DF/DI and one insn for SF.
1285 'H' is used for DI/DF constants that take 3 insns. */
1287 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1288 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1289 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1290 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1293 /* Optional extra constraints for this machine.
1295 'Q' means that is a memory operand that is just an offset from a reg.
1296 'R' is for AIX TOC entries.
1297 'S' is a constant that can be placed into a 64-bit mask operand
1298 'T' is a constant that can be placed into a 32-bit mask operand
1299 'U' is for V.4 small data references.
1300 'W' is a vector constant that can be easily generated (no mem refs).
1301 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1303 #define EXTRA_CONSTRAINT(OP, C) \
1304 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1305 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1306 : (C) == 'S' ? mask64_operand (OP, DImode) \
1307 : (C) == 'T' ? mask_operand (OP, SImode) \
1308 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1309 && small_data_operand (OP, GET_MODE (OP))) \
1310 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1311 && (fixed_regs[CR0_REGNO] \
1312 || !logical_operand (OP, DImode)) \
1313 && !mask64_operand (OP, DImode)) \
1314 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1317 /* Given an rtx X being reloaded into a reg required to be
1318 in class CLASS, return the class of reg to actually use.
1319 In general this is just CLASS; but on some machines
1320 in some cases it is preferable to use a more restrictive class.
1322 On the RS/6000, we have to return NO_REGS when we want to reload a
1323 floating-point CONST_DOUBLE to force it to be copied to memory.
1325 We also don't want to reload integer values into floating-point
1326 registers if we can at all help it. In fact, this can
1327 cause reload to abort, if it tries to generate a reload of CTR
1328 into a FP register and discovers it doesn't have the memory location
1331 ??? Would it be a good idea to have reload do the converse, that is
1332 try to reload floating modes into FP registers if possible?
1335 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1336 (((GET_CODE (X) == CONST_DOUBLE \
1337 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1339 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1340 && (CLASS) == NON_SPECIAL_REGS) \
1344 /* Return the register class of a scratch register needed to copy IN into
1345 or out of a register in CLASS in MODE. If it can be done directly,
1346 NO_REGS is returned. */
1348 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1349 secondary_reload_class (CLASS, MODE, IN)
1351 /* If we are copying between FP or AltiVec registers and anything
1352 else, we need a memory location. */
1354 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1355 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1356 || (CLASS2) == FLOAT_REGS \
1357 || (CLASS1) == ALTIVEC_REGS \
1358 || (CLASS2) == ALTIVEC_REGS))
1360 /* Return the maximum number of consecutive registers
1361 needed to represent mode MODE in a register of class CLASS.
1363 On RS/6000, this is the size of MODE in words,
1364 except in the FP regs, where a single reg is enough for two words. */
1365 #define CLASS_MAX_NREGS(CLASS, MODE) \
1366 (((CLASS) == FLOAT_REGS) \
1367 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1368 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1371 /* Return a class of registers that cannot change FROM mode to TO mode. */
1373 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1374 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1375 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1376 : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \
1377 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1380 /* Stack layout; function entry, exit and calling. */
1382 /* Enumeration to give which calling sequence to use. */
1385 ABI_AIX, /* IBM's AIX */
1386 ABI_AIX_NODESC, /* AIX calling sequence minus
1387 function descriptors */
1388 ABI_V4, /* System V.4/eabi */
1389 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1392 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1394 /* Structure used to define the rs6000 stack */
1395 typedef struct rs6000_stack {
1396 int first_gp_reg_save; /* first callee saved GP register used */
1397 int first_fp_reg_save; /* first callee saved FP register used */
1398 int first_altivec_reg_save; /* first callee saved AltiVec register used */
1399 int lr_save_p; /* true if the link reg needs to be saved */
1400 int cr_save_p; /* true if the CR reg needs to be saved */
1401 unsigned int vrsave_mask; /* mask of vec registers to save */
1402 int toc_save_p; /* true if the TOC needs to be saved */
1403 int push_p; /* true if we need to allocate stack space */
1404 int calls_p; /* true if the function makes any calls */
1405 enum rs6000_abi abi; /* which ABI to use */
1406 int gp_save_offset; /* offset to save GP regs from initial SP */
1407 int fp_save_offset; /* offset to save FP regs from initial SP */
1408 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
1409 int lr_save_offset; /* offset to save LR from initial SP */
1410 int cr_save_offset; /* offset to save CR from initial SP */
1411 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
1412 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
1413 int toc_save_offset; /* offset to save the TOC pointer */
1414 int varargs_save_offset; /* offset to save the varargs registers */
1415 int ehrd_offset; /* offset to EH return data */
1416 int reg_size; /* register size (4 or 8) */
1417 int varargs_size; /* size to hold V.4 args passed in regs */
1418 int vars_size; /* variable save area size */
1419 int parm_size; /* outgoing parameter size */
1420 int save_size; /* save area size */
1421 int fixed_size; /* fixed size of stack frame */
1422 int gp_size; /* size of saved GP registers */
1423 int fp_size; /* size of saved FP registers */
1424 int altivec_size; /* size of saved AltiVec registers */
1425 int cr_size; /* size to hold CR if not in save_size */
1426 int lr_size; /* size to hold LR if not in save_size */
1427 int vrsave_size; /* size to hold VRSAVE if not in save_size */
1428 int altivec_padding_size; /* size of altivec alignment padding if
1430 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
1431 int spe_padding_size;
1432 int toc_size; /* size to hold TOC if not in save_size */
1433 int total_size; /* total bytes allocated for stack */
1434 int spe_64bit_regs_used;
1437 /* Define this if pushing a word on the stack
1438 makes the stack pointer a smaller address. */
1439 #define STACK_GROWS_DOWNWARD
1441 /* Define this if the nominal address of the stack frame
1442 is at the high-address end of the local variables;
1443 that is, each additional local variable allocated
1444 goes at a more negative offset in the frame.
1446 On the RS/6000, we grow upwards, from the area after the outgoing
1448 /* #define FRAME_GROWS_DOWNWARD */
1450 /* Size of the outgoing register save area */
1451 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1452 || DEFAULT_ABI == ABI_AIX_NODESC \
1453 || DEFAULT_ABI == ABI_DARWIN) \
1454 ? (TARGET_64BIT ? 64 : 32) \
1457 /* Size of the fixed area on the stack */
1458 #define RS6000_SAVE_AREA \
1459 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1460 << (TARGET_64BIT ? 1 : 0))
1462 /* MEM representing address to save the TOC register */
1463 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1464 plus_constant (stack_pointer_rtx, \
1465 (TARGET_32BIT ? 20 : 40)))
1467 /* Size of the V.4 varargs area if needed */
1468 #define RS6000_VARARGS_AREA 0
1470 /* Align an address */
1471 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1473 /* Size of V.4 varargs area in bytes */
1474 #define RS6000_VARARGS_SIZE \
1475 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1477 /* Offset within stack frame to start allocating local variables at.
1478 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1479 first local allocated. Otherwise, it is the offset to the BEGINNING
1480 of the first local allocated.
1482 On the RS/6000, the frame pointer is the same as the stack pointer,
1483 except for dynamic allocations. So we start after the fixed area and
1484 outgoing parameter area. */
1486 #define STARTING_FRAME_OFFSET \
1487 (RS6000_ALIGN (current_function_outgoing_args_size, \
1488 TARGET_ALTIVEC ? 16 : 8) \
1489 + RS6000_VARARGS_AREA \
1492 /* Offset from the stack pointer register to an item dynamically
1493 allocated on the stack, e.g., by `alloca'.
1495 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1496 length of the outgoing arguments. The default is correct for most
1497 machines. See `function.c' for details. */
1498 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1499 (RS6000_ALIGN (current_function_outgoing_args_size, \
1500 TARGET_ALTIVEC ? 16 : 8) \
1501 + (STACK_POINTER_OFFSET))
1503 /* If we generate an insn to push BYTES bytes,
1504 this says how many the stack pointer really advances by.
1505 On RS/6000, don't define this because there are no push insns. */
1506 /* #define PUSH_ROUNDING(BYTES) */
1508 /* Offset of first parameter from the argument pointer register value.
1509 On the RS/6000, we define the argument pointer to the start of the fixed
1511 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1513 /* Offset from the argument pointer register value to the top of
1514 stack. This is different from FIRST_PARM_OFFSET because of the
1515 register save area. */
1516 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1518 /* Define this if stack space is still allocated for a parameter passed
1519 in a register. The value is the number of bytes allocated to this
1521 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1523 /* Define this if the above stack space is to be considered part of the
1524 space allocated by the caller. */
1525 #define OUTGOING_REG_PARM_STACK_SPACE
1527 /* This is the difference between the logical top of stack and the actual sp.
1529 For the RS/6000, sp points past the fixed area. */
1530 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1532 /* Define this if the maximum size of all the outgoing args is to be
1533 accumulated and pushed during the prologue. The amount can be
1534 found in the variable current_function_outgoing_args_size. */
1535 #define ACCUMULATE_OUTGOING_ARGS 1
1537 /* Value is the number of bytes of arguments automatically
1538 popped when returning from a subroutine call.
1539 FUNDECL is the declaration node of the function (as a tree),
1540 FUNTYPE is the data type of the function (as a tree),
1541 or for a library call it is an identifier node for the subroutine name.
1542 SIZE is the number of bytes of arguments passed on the stack. */
1544 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1546 /* Define how to find the value returned by a function.
1547 VALTYPE is the data type of the value (as a tree).
1548 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1549 otherwise, FUNC is 0.
1551 On the SPE, both FPs and vectors are returned in r3.
1553 On RS/6000 an integer value is in r3 and a floating-point value is in
1554 fp1, unless -msoft-float. */
1556 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1557 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1558 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1559 || POINTER_TYPE_P (VALTYPE) \
1560 ? word_mode : TYPE_MODE (VALTYPE), \
1561 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1562 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1563 : TREE_CODE (VALTYPE) == REAL_TYPE \
1564 && TARGET_SPE_ABI && !TARGET_FPRS \
1566 : TREE_CODE (VALTYPE) == REAL_TYPE \
1567 && TARGET_HARD_FLOAT && TARGET_FPRS \
1568 ? FP_ARG_RETURN : GP_ARG_RETURN)
1570 /* Define how to find the value returned by a library function
1571 assuming the value has mode MODE. */
1573 #define LIBCALL_VALUE(MODE) \
1574 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1575 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1576 && TARGET_HARD_FLOAT && TARGET_FPRS \
1577 ? FP_ARG_RETURN : GP_ARG_RETURN)
1579 /* The AIX ABI for the RS/6000 specifies that all structures are
1580 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1581 specifies that structures <= 8 bytes are returned in r3/r4, but a
1582 draft put them in memory, and GCC used to implement the draft
1583 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1584 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1585 compatibility can change DRAFT_V4_STRUCT_RET to override the
1586 default, and -m switches get the final word. See
1587 rs6000_override_options for more details.
1589 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
1590 long double support is enabled. These values are returned in memory.
1592 int_size_in_bytes returns -1 for variable size objects, which go in
1593 memory always. The cast to unsigned makes -1 > 8. */
1595 #define RETURN_IN_MEMORY(TYPE) \
1596 ((AGGREGATE_TYPE_P (TYPE) \
1597 && (TARGET_AIX_STRUCT_RET \
1598 || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \
1599 || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode))
1601 /* DRAFT_V4_STRUCT_RET defaults off. */
1602 #define DRAFT_V4_STRUCT_RET 0
1604 /* Let RETURN_IN_MEMORY control what happens. */
1605 #define DEFAULT_PCC_STRUCT_RETURN 0
1607 /* Mode of stack savearea.
1608 FUNCTION is VOIDmode because calling convention maintains SP.
1609 BLOCK needs Pmode for SP.
1610 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1611 #define STACK_SAVEAREA_MODE(LEVEL) \
1612 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1613 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1615 /* Minimum and maximum general purpose registers used to hold arguments. */
1616 #define GP_ARG_MIN_REG 3
1617 #define GP_ARG_MAX_REG 10
1618 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1620 /* Minimum and maximum floating point registers used to hold arguments. */
1621 #define FP_ARG_MIN_REG 33
1622 #define FP_ARG_AIX_MAX_REG 45
1623 #define FP_ARG_V4_MAX_REG 40
1624 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1625 || DEFAULT_ABI == ABI_AIX_NODESC \
1626 || DEFAULT_ABI == ABI_DARWIN) \
1627 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1628 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1630 /* Minimum and maximum AltiVec registers used to hold arguments. */
1631 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1632 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1633 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1635 /* Return registers */
1636 #define GP_ARG_RETURN GP_ARG_MIN_REG
1637 #define FP_ARG_RETURN FP_ARG_MIN_REG
1638 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1640 /* Flags for the call/call_value rtl operations set up by function_arg */
1641 #define CALL_NORMAL 0x00000000 /* no special processing */
1642 /* Bits in 0x00000001 are unused. */
1643 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1644 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1645 #define CALL_LONG 0x00000008 /* always call indirect */
1647 /* 1 if N is a possible register number for a function value
1648 as seen by the caller.
1650 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1651 #define FUNCTION_VALUE_REGNO_P(N) \
1652 ((N) == GP_ARG_RETURN \
1653 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1654 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
1656 /* 1 if N is a possible register number for function argument passing.
1657 On RS/6000, these are r3-r10 and fp1-fp13.
1658 On AltiVec, v2 - v13 are used for passing vectors. */
1659 #define FUNCTION_ARG_REGNO_P(N) \
1660 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1661 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1662 && TARGET_ALTIVEC) \
1663 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1664 && TARGET_HARD_FLOAT))
1666 /* A C structure for machine-specific, per-function data.
1667 This is added to the cfun structure. */
1668 typedef struct machine_function GTY(())
1670 /* Whether a System V.4 varargs area was created. */
1672 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1673 int ra_needs_full_frame;
1674 /* Whether the instruction chain has been scanned already. */
1675 int insn_chain_scanned_p;
1678 /* Define a data type for recording info about an argument list
1679 during the scan of that argument list. This data type should
1680 hold all necessary information about the function itself
1681 and about the args processed so far, enough to enable macros
1682 such as FUNCTION_ARG to determine where the next arg should go.
1684 On the RS/6000, this is a structure. The first element is the number of
1685 total argument words, the second is used to store the next
1686 floating-point register number, and the third says how many more args we
1687 have prototype types for.
1689 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1690 the next available GP register, `fregno' is the next available FP
1691 register, and `words' is the number of words used on the stack.
1693 The varargs/stdarg support requires that this structure's size
1694 be a multiple of sizeof(int). */
1696 typedef struct rs6000_args
1698 int words; /* # words used for passing GP registers */
1699 int fregno; /* next available FP register */
1700 int vregno; /* next available AltiVec register */
1701 int nargs_prototype; /* # args left in the current prototype */
1702 int orig_nargs; /* Original value of nargs_prototype */
1703 int prototype; /* Whether a prototype was defined */
1704 int call_cookie; /* Do special things for this call */
1705 int sysv_gregno; /* next available GP register */
1708 /* Define intermediate macro to compute the size (in registers) of an argument
1711 #define RS6000_ARG_SIZE(MODE, TYPE) \
1712 ((MODE) != BLKmode \
1713 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1714 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1716 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1717 for a call to a function whose data type is FNTYPE.
1718 For a library call, FNTYPE is 0. */
1720 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1721 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1723 /* Similar, but when scanning the definition of a procedure. We always
1724 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1726 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1727 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1729 /* Update the data in CUM to advance over an argument
1730 of mode MODE and data type TYPE.
1731 (TYPE is null for libcalls where that information may not be available.) */
1733 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1734 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1736 /* Nonzero if we can use a floating-point register to pass this arg. */
1737 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1738 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1739 && (CUM).fregno <= FP_ARG_MAX_REG \
1740 && TARGET_HARD_FLOAT && TARGET_FPRS)
1742 /* Nonzero if we can use an AltiVec register to pass this arg. */
1743 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1744 (ALTIVEC_VECTOR_MODE (MODE) \
1745 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1746 && TARGET_ALTIVEC_ABI)
1748 /* Determine where to put an argument to a function.
1749 Value is zero to push the argument on the stack,
1750 or a hard register in which to store the argument.
1752 MODE is the argument's machine mode.
1753 TYPE is the data type of the argument (as a tree).
1754 This is null for libcalls where that information may
1756 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1757 the preceding args and about the function being called.
1758 NAMED is nonzero if this argument is a named parameter
1759 (otherwise it is an extra parameter matching an ellipsis).
1761 On RS/6000 the first eight words of non-FP are normally in registers
1762 and the rest are pushed. The first 13 FP args are in registers.
1764 If this is floating-point and no prototype is specified, we use
1765 both an FP and integer register (or possibly FP reg and stack). Library
1766 functions (when TYPE is zero) always have the proper types for args,
1767 so we can pass the FP value just in one register. emit_library_function
1768 doesn't support EXPR_LIST anyway. */
1770 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1771 function_arg (&CUM, MODE, TYPE, NAMED)
1773 /* For an arg passed partly in registers and partly in memory,
1774 this is the number of registers used.
1775 For args passed entirely in registers or entirely in memory, zero. */
1777 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1778 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1780 /* A C expression that indicates when an argument must be passed by
1781 reference. If nonzero for an argument, a copy of that argument is
1782 made in memory and a pointer to the argument is passed instead of
1783 the argument itself. The pointer is passed in whatever way is
1784 appropriate for passing a pointer to that type. */
1786 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1787 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1789 /* If defined, a C expression which determines whether, and in which
1790 direction, to pad out an argument with extra space. The value
1791 should be of type `enum direction': either `upward' to pad above
1792 the argument, `downward' to pad below, or `none' to inhibit
1795 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1797 /* If defined, a C expression that gives the alignment boundary, in bits,
1798 of an argument with the specified mode and type. If it is not defined,
1799 PARM_BOUNDARY is used for all arguments. */
1801 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1802 function_arg_boundary (MODE, TYPE)
1804 /* Perform any needed actions needed for a function that is receiving a
1805 variable number of arguments.
1809 MODE and TYPE are the mode and type of the current parameter.
1811 PRETEND_SIZE is a variable that should be set to the amount of stack
1812 that must be pushed by the prolog to pretend that our caller pushed
1815 Normally, this macro will push all remaining incoming registers on the
1816 stack and set PRETEND_SIZE to the length of the registers pushed. */
1818 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1819 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1821 /* Define the `__builtin_va_list' type for the ABI. */
1822 #define BUILD_VA_LIST_TYPE(VALIST) \
1823 (VALIST) = rs6000_build_va_list ()
1825 /* Implement `va_start' for varargs and stdarg. */
1826 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1827 rs6000_va_start (valist, nextarg)
1829 /* Implement `va_arg'. */
1830 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1831 rs6000_va_arg (valist, type)
1833 /* For AIX, the rule is that structures are passed left-aligned in
1834 their stack slot. However, GCC does not presently do this:
1835 structures which are the same size as integer types are passed
1836 right-aligned, as if they were in fact integers. This only
1837 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1838 ABI_V4 does not use std_expand_builtin_va_arg. */
1839 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1841 /* Define this macro to be a nonzero value if the location where a function
1842 argument is passed depends on whether or not it is a named argument. */
1843 #define STRICT_ARGUMENT_NAMING 1
1845 /* Output assembler code to FILE to increment profiler label # LABELNO
1846 for profiling a function entry. */
1848 #define FUNCTION_PROFILER(FILE, LABELNO) \
1849 output_function_profiler ((FILE), (LABELNO));
1851 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1852 the stack pointer does not matter. No definition is equivalent to
1855 On the RS/6000, this is nonzero because we can restore the stack from
1856 its backpointer, which we maintain. */
1857 #define EXIT_IGNORE_STACK 1
1859 /* Define this macro as a C expression that is nonzero for registers
1860 that are used by the epilogue or the return' pattern. The stack
1861 and frame pointer registers are already be assumed to be used as
1864 #define EPILOGUE_USES(REGNO) \
1865 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1866 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1867 || (current_function_calls_eh_return \
1869 && (REGNO) == TOC_REGISTER))
1872 /* TRAMPOLINE_TEMPLATE deleted */
1874 /* Length in units of the trampoline for entering a nested function. */
1876 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1878 /* Emit RTL insns to initialize the variable parts of a trampoline.
1879 FNADDR is an RTX for the address of the function's pure code.
1880 CXT is an RTX for the static chain value for the function. */
1882 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1883 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1885 /* Definitions for __builtin_return_address and __builtin_frame_address.
1886 __builtin_return_address (0) should give link register (65), enable
1888 /* This should be uncommented, so that the link register is used, but
1889 currently this would result in unmatched insns and spilling fixed
1890 registers so we'll leave it for another day. When these problems are
1891 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1893 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1895 /* Number of bytes into the frame return addresses can be found. See
1896 rs6000_stack_info in rs6000.c for more information on how the different
1897 abi's store the return address. */
1898 #define RETURN_ADDRESS_OFFSET \
1899 ((DEFAULT_ABI == ABI_AIX \
1900 || DEFAULT_ABI == ABI_DARWIN \
1901 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1902 (DEFAULT_ABI == ABI_V4) ? 4 : \
1903 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1905 /* The current return address is in link register (65). The return address
1906 of anything farther back is accessed normally at an offset of 8 from the
1908 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1909 (rs6000_return_addr (COUNT, FRAME))
1912 /* Definitions for register eliminations.
1914 We have two registers that can be eliminated on the RS/6000. First, the
1915 frame pointer register can often be eliminated in favor of the stack
1916 pointer register. Secondly, the argument pointer register can always be
1917 eliminated; it is replaced with either the stack or frame pointer.
1919 In addition, we use the elimination mechanism to see if r30 is needed
1920 Initially we assume that it isn't. If it is, we spill it. This is done
1921 by making it an eliminable register. We replace it with itself so that
1922 if it isn't needed, then existing uses won't be modified. */
1924 /* This is an array of structures. Each structure initializes one pair
1925 of eliminable registers. The "from" register number is given first,
1926 followed by "to". Eliminations of the same "from" register are listed
1927 in order of preference. */
1928 #define ELIMINABLE_REGS \
1929 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1930 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1931 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1932 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1934 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1935 Frame pointer elimination is automatically handled.
1937 For the RS/6000, if frame pointer elimination is being done, we would like
1938 to convert ap into fp, not sp.
1940 We need r30 if -mminimal-toc was specified, and there are constant pool
1943 #define CAN_ELIMINATE(FROM, TO) \
1944 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1945 ? ! frame_pointer_needed \
1946 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1947 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1950 /* Define the offset between two registers, one to be eliminated, and the other
1951 its replacement, at the start of a routine. */
1952 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1954 rs6000_stack_t *info = rs6000_stack_info (); \
1956 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1957 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1958 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1959 (OFFSET) = info->total_size; \
1960 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1961 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1962 else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \
1968 /* Addressing modes, and classification of registers for them. */
1970 #define HAVE_PRE_DECREMENT 1
1971 #define HAVE_PRE_INCREMENT 1
1973 /* Macros to check register numbers against specific register classes. */
1975 /* These assume that REGNO is a hard or pseudo reg number.
1976 They give nonzero only if REGNO is a hard reg of the suitable class
1977 or a pseudo reg currently allocated to a suitable hard reg.
1978 Since they use reg_renumber, they are safe only once reg_renumber
1979 has been allocated, which happens in local-alloc.c. */
1981 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1982 ((REGNO) < FIRST_PSEUDO_REGISTER \
1983 ? (REGNO) <= 31 || (REGNO) == 67 \
1984 : (reg_renumber[REGNO] >= 0 \
1985 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1987 #define REGNO_OK_FOR_BASE_P(REGNO) \
1988 ((REGNO) < FIRST_PSEUDO_REGISTER \
1989 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1990 : (reg_renumber[REGNO] > 0 \
1991 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1993 /* Maximum number of registers that can appear in a valid memory address. */
1995 #define MAX_REGS_PER_ADDRESS 2
1997 /* Recognize any constant value that is a valid address. */
1999 #define CONSTANT_ADDRESS_P(X) \
2000 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2001 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2002 || GET_CODE (X) == HIGH)
2004 /* Nonzero if the constant value X is a legitimate general operand.
2005 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2007 On the RS/6000, all integer constants are acceptable, most won't be valid
2008 for particular insns, though. Only easy FP constants are
2011 #define LEGITIMATE_CONSTANT_P(X) \
2012 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
2013 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
2014 || easy_fp_constant (X, GET_MODE (X)))
2016 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2017 and check its validity for a certain class.
2018 We have two alternate definitions for each of them.
2019 The usual definition accepts all pseudo regs; the other rejects
2020 them unless they have been allocated suitable hard regs.
2021 The symbol REG_OK_STRICT causes the latter definition to be used.
2023 Most source files want to accept pseudo regs in the hope that
2024 they will get allocated to the class that the insn wants them to be in.
2025 Source files for reload pass need to be strict.
2026 After reload, it makes no difference, since pseudo regs have
2027 been eliminated by then. */
2029 #ifdef REG_OK_STRICT
2030 # define REG_OK_STRICT_FLAG 1
2032 # define REG_OK_STRICT_FLAG 0
2035 /* Nonzero if X is a hard reg that can be used as an index
2036 or if it is a pseudo reg in the non-strict case. */
2037 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2039 && (REGNO (X) <= 31 \
2040 || REGNO (X) == ARG_POINTER_REGNUM \
2041 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2042 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2044 /* Nonzero if X is a hard reg that can be used as a base reg
2045 or if it is a pseudo reg in the non-strict case. */
2046 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2047 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2049 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2050 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2052 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2053 that is a valid memory address for an instruction.
2054 The MODE argument is the machine mode for the MEM expression
2055 that wants to use this address.
2057 On the RS/6000, there are four valid address: a SYMBOL_REF that
2058 refers to a constant pool entry of an address (or the sum of it
2059 plus a constant), a short (16-bit signed) constant plus a register,
2060 the sum of two registers, or a register indirect, possibly with an
2061 auto-increment. For DFmode and DImode with a constant plus register,
2062 we must ensure that both words are addressable or PowerPC64 with offset
2065 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2066 32-bit DImode, TImode), indexed addressing cannot be used because
2067 adjacent memory cells are accessed by adding word-sized offsets
2068 during assembly output. */
2070 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
2072 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
2074 /* SPE offset addressing is limited to 5-bits worth of double words. */
2075 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2077 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
2079 && GET_CODE (X) == PLUS \
2080 && GET_CODE (XEXP (X, 0)) == REG \
2081 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
2082 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
2084 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
2085 (DEFAULT_ABI == ABI_V4 \
2086 && !flag_pic && !TARGET_TOC \
2087 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
2088 && small_data_operand (X, MODE))
2090 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
2091 (GET_CODE (X) == CONST_INT \
2092 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
2094 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
2095 (GET_CODE (X) == PLUS \
2096 && GET_CODE (XEXP (X, 0)) == REG \
2097 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2098 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
2099 && (! ALTIVEC_VECTOR_MODE (MODE) \
2100 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
2101 && (! SPE_VECTOR_MODE (MODE) \
2102 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
2103 && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \
2104 && (((MODE) != DFmode && (MODE) != DImode) \
2106 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
2107 : ! (INTVAL (XEXP (X, 1)) & 3))) \
2108 && (((MODE) != TFmode && (MODE) != TImode) \
2110 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
2111 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2112 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2114 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2115 (GET_CODE (X) == PLUS \
2116 && GET_CODE (XEXP (X, 0)) == REG \
2117 && GET_CODE (XEXP (X, 1)) == REG \
2118 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2119 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2120 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2121 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2123 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2124 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2126 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2128 && (DEFAULT_ABI == ABI_AIX || ! flag_pic) \
2130 && GET_MODE_NUNITS (MODE) == 1 \
2131 && (GET_MODE_BITSIZE (MODE) <= 32 \
2132 || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \
2133 && GET_CODE (X) == LO_SUM \
2134 && GET_CODE (XEXP (X, 0)) == REG \
2135 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2136 && CONSTANT_P (XEXP (X, 1)))
2138 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2139 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2143 /* Try machine-dependent ways of modifying an illegitimate address
2144 to be legitimate. If we find one, return the new, valid address.
2145 This macro is used in only one place: `memory_address' in explow.c.
2147 OLDX is the address as it was before break_out_memory_refs was called.
2148 In some cases it is useful to look at this to decide what needs to be done.
2150 MODE and WIN are passed so that this macro can use
2151 GO_IF_LEGITIMATE_ADDRESS.
2153 It is always safe for this macro to do nothing. It exists to recognize
2154 opportunities to optimize the output.
2156 On RS/6000, first check for the sum of a register with a constant
2157 integer that is out of range. If so, generate code to add the
2158 constant with the low-order 16 bits masked to the register and force
2159 this result into another register (this can be done with `cau').
2160 Then generate an address of REG+(CONST&0xffff), allowing for the
2161 possibility of bit 16 being a one.
2163 Then check for the sum of a register and something not constant, try to
2164 load the other things into a register and return the sum. */
2166 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2167 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2168 if (result != NULL_RTX) \
2175 /* Try a machine-dependent way of reloading an illegitimate address
2176 operand. If we find one, push the reload and jump to WIN. This
2177 macro is used in only one place: `find_reloads_address' in reload.c.
2179 Implemented on rs6000 by rs6000_legitimize_reload_address.
2180 Note that (X) is evaluated twice; this is safe in current usage. */
2182 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2185 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2186 (int)(TYPE), (IND_LEVELS), &win); \
2191 /* Go to LABEL if ADDR (a legitimate address expression)
2192 has an effect that depends on the machine mode it is used for.
2194 On the RS/6000 this is true if the address is valid with a zero offset
2195 but not with an offset of four (this means it cannot be used as an
2196 address for DImode or DFmode) or is a pre-increment or decrement. Since
2197 we know it is valid, we just check for an address that is not valid with
2198 an offset of four. */
2200 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2201 { if (GET_CODE (ADDR) == PLUS \
2202 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2203 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2204 (TARGET_32BIT ? 4 : 8))) \
2206 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2208 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2210 if (GET_CODE (ADDR) == LO_SUM) \
2214 /* The register number of the register used to address a table of
2215 static data addresses in memory. In some cases this register is
2216 defined by a processor's "application binary interface" (ABI).
2217 When this macro is defined, RTL is generated for this register
2218 once, as with the stack pointer and frame pointer registers. If
2219 this macro is not defined, it is up to the machine-dependent files
2220 to allocate such a register (if necessary). */
2222 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2223 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2225 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2227 /* Define this macro if the register defined by
2228 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2229 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2231 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2233 /* By generating position-independent code, when two different
2234 programs (A and B) share a common library (libC.a), the text of
2235 the library can be shared whether or not the library is linked at
2236 the same address for both programs. In some of these
2237 environments, position-independent code requires not only the use
2238 of different addressing modes, but also special code to enable the
2239 use of these addressing modes.
2241 The `FINALIZE_PIC' macro serves as a hook to emit these special
2242 codes once the function is being compiled into assembly code, but
2243 not before. (It is not done before, because in the case of
2244 compiling an inline function, it would lead to multiple PIC
2245 prologues being included in functions which used inline functions
2246 and were compiled to assembly language.) */
2248 /* #define FINALIZE_PIC */
2250 /* A C expression that is nonzero if X is a legitimate immediate
2251 operand on the target machine when generating position independent
2252 code. You can assume that X satisfies `CONSTANT_P', so you need
2253 not check this. You can also assume FLAG_PIC is true, so you need
2254 not check it either. You need not define this macro if all
2255 constants (including `SYMBOL_REF') can be immediate operands when
2256 generating position independent code. */
2258 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2260 /* In rare cases, correct code generation requires extra machine
2261 dependent processing between the second jump optimization pass and
2262 delayed branch scheduling. On those machines, define this macro
2263 as a C statement to act on the code starting at INSN. */
2265 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2268 /* Define this if some processing needs to be done immediately before
2269 emitting code for an insn. */
2271 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2273 /* Specify the machine mode that this machine uses
2274 for the index in the tablejump instruction. */
2275 #define CASE_VECTOR_MODE SImode
2277 /* Define as C expression which evaluates to nonzero if the tablejump
2278 instruction expects the table to contain offsets from the address of the
2280 Do not define this if the table should contain absolute addresses. */
2281 #define CASE_VECTOR_PC_RELATIVE 1
2283 /* Define this as 1 if `char' should by default be signed; else as 0. */
2284 #define DEFAULT_SIGNED_CHAR 0
2286 /* This flag, if defined, says the same insns that convert to a signed fixnum
2287 also convert validly to an unsigned one. */
2289 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2291 /* Max number of bytes we can move from memory to memory
2292 in one reasonably fast instruction. */
2293 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2294 #define MAX_MOVE_MAX 8
2296 /* Nonzero if access to memory by bytes is no faster than for words.
2297 Also nonzero if doing byte operations (specifically shifts) in registers
2299 #define SLOW_BYTE_ACCESS 1
2301 /* Define if operations between registers always perform the operation
2302 on the full register even if a narrower mode is specified. */
2303 #define WORD_REGISTER_OPERATIONS
2305 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2306 will either zero-extend or sign-extend. The value of this macro should
2307 be the code that says which one of the two operations is implicitly
2308 done, NIL if none. */
2309 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2311 /* Define if loading short immediate values into registers sign extends. */
2312 #define SHORT_IMMEDIATES_SIGN_EXTEND
2314 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2315 is done just by pretending it is already truncated. */
2316 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2318 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2319 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2320 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2322 /* The CTZ patterns return -1 for input of zero. */
2323 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2325 /* Specify the machine mode that pointers have.
2326 After generation of rtl, the compiler makes no further distinction
2327 between pointers and any other objects of this machine mode. */
2328 #define Pmode (TARGET_32BIT ? SImode : DImode)
2330 /* Mode of a function address in a call instruction (for indexing purposes).
2331 Doesn't matter on RS/6000. */
2332 #define FUNCTION_MODE SImode
2334 /* Define this if addresses of constant functions
2335 shouldn't be put through pseudo regs where they can be cse'd.
2336 Desirable on machines where ordinary constants are expensive
2337 but a CALL with constant address is cheap. */
2338 #define NO_FUNCTION_CSE
2340 /* Define this to be nonzero if shift instructions ignore all but the low-order
2343 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2344 have been dropped from the PowerPC architecture. */
2346 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2348 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2349 should be adjusted to reflect any required changes. This macro is used when
2350 there is some systematic length adjustment required that would be difficult
2351 to express in the length attribute. */
2353 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2355 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2356 COMPARE, return the mode to be used for the comparison. For
2357 floating-point, CCFPmode should be used. CCUNSmode should be used
2358 for unsigned comparisons. CCEQmode should be used when we are
2359 doing an inequality comparison on the result of a
2360 comparison. CCmode should be used in all other cases. */
2362 #define SELECT_CC_MODE(OP,X,Y) \
2363 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2364 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2365 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2366 ? CCEQmode : CCmode))
2368 /* Define the information needed to generate branch and scc insns. This is
2369 stored from the compare operation. Note that we can't use "rtx" here
2370 since it hasn't been defined! */
2372 extern GTY(()) rtx rs6000_compare_op0;
2373 extern GTY(()) rtx rs6000_compare_op1;
2374 extern int rs6000_compare_fp_p;
2376 /* Control the assembler format that we output. */
2378 /* A C string constant describing how to begin a comment in the target
2379 assembler language. The compiler assumes that the comment will end at
2380 the end of the line. */
2381 #define ASM_COMMENT_START " #"
2383 /* Implicit library calls should use memcpy, not bcopy, etc. */
2385 #define TARGET_MEM_FUNCTIONS
2387 /* Flag to say the TOC is initialized */
2388 extern int toc_initialized;
2390 /* Macro to output a special constant pool entry. Go to WIN if we output
2391 it. Otherwise, it is written the usual way.
2393 On the RS/6000, toc entries are handled this way. */
2395 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2396 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2398 output_toc (FILE, X, LABELNO, MODE); \
2403 #ifdef HAVE_GAS_WEAK
2404 #define RS6000_WEAK 1
2406 #define RS6000_WEAK 0
2410 /* Used in lieu of ASM_WEAKEN_LABEL. */
2411 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2414 fputs ("\t.weak\t", (FILE)); \
2415 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2416 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2417 && DEFAULT_ABI == ABI_AIX) \
2420 fputs ("[DS]", (FILE)); \
2421 fputs ("\n\t.weak\t.", (FILE)); \
2422 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2424 fputc ('\n', (FILE)); \
2427 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2428 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2429 && DEFAULT_ABI == ABI_AIX) \
2431 fputs ("\t.set\t.", (FILE)); \
2432 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2433 fputs (",.", (FILE)); \
2434 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2435 fputc ('\n', (FILE)); \
2442 /* This implements the `alias' attribute. */
2443 #undef ASM_OUTPUT_DEF_FROM_DECLS
2444 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2447 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2448 const char *name = IDENTIFIER_POINTER (TARGET); \
2449 if (TREE_CODE (DECL) == FUNCTION_DECL \
2450 && DEFAULT_ABI == ABI_AIX) \
2452 if (TREE_PUBLIC (DECL)) \
2454 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2456 fputs ("\t.globl\t.", FILE); \
2457 RS6000_OUTPUT_BASENAME (FILE, alias); \
2458 putc ('\n', FILE); \
2461 else if (TARGET_XCOFF) \
2463 fputs ("\t.lglobl\t.", FILE); \
2464 RS6000_OUTPUT_BASENAME (FILE, alias); \
2465 putc ('\n', FILE); \
2467 fputs ("\t.set\t.", FILE); \
2468 RS6000_OUTPUT_BASENAME (FILE, alias); \
2469 fputs (",.", FILE); \
2470 RS6000_OUTPUT_BASENAME (FILE, name); \
2471 fputc ('\n', FILE); \
2473 ASM_OUTPUT_DEF (FILE, alias, name); \
2477 /* Output to assembler file text saying following lines
2478 may contain character constants, extra white space, comments, etc. */
2480 #define ASM_APP_ON ""
2482 /* Output to assembler file text saying following lines
2483 no longer contain unusual constructs. */
2485 #define ASM_APP_OFF ""
2487 /* How to refer to registers in assembler output.
2488 This sequence is indexed by compiler's hard-register-number (see above). */
2490 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2492 #define REGISTER_NAMES \
2494 &rs6000_reg_names[ 0][0], /* r0 */ \
2495 &rs6000_reg_names[ 1][0], /* r1 */ \
2496 &rs6000_reg_names[ 2][0], /* r2 */ \
2497 &rs6000_reg_names[ 3][0], /* r3 */ \
2498 &rs6000_reg_names[ 4][0], /* r4 */ \
2499 &rs6000_reg_names[ 5][0], /* r5 */ \
2500 &rs6000_reg_names[ 6][0], /* r6 */ \
2501 &rs6000_reg_names[ 7][0], /* r7 */ \
2502 &rs6000_reg_names[ 8][0], /* r8 */ \
2503 &rs6000_reg_names[ 9][0], /* r9 */ \
2504 &rs6000_reg_names[10][0], /* r10 */ \
2505 &rs6000_reg_names[11][0], /* r11 */ \
2506 &rs6000_reg_names[12][0], /* r12 */ \
2507 &rs6000_reg_names[13][0], /* r13 */ \
2508 &rs6000_reg_names[14][0], /* r14 */ \
2509 &rs6000_reg_names[15][0], /* r15 */ \
2510 &rs6000_reg_names[16][0], /* r16 */ \
2511 &rs6000_reg_names[17][0], /* r17 */ \
2512 &rs6000_reg_names[18][0], /* r18 */ \
2513 &rs6000_reg_names[19][0], /* r19 */ \
2514 &rs6000_reg_names[20][0], /* r20 */ \
2515 &rs6000_reg_names[21][0], /* r21 */ \
2516 &rs6000_reg_names[22][0], /* r22 */ \
2517 &rs6000_reg_names[23][0], /* r23 */ \
2518 &rs6000_reg_names[24][0], /* r24 */ \
2519 &rs6000_reg_names[25][0], /* r25 */ \
2520 &rs6000_reg_names[26][0], /* r26 */ \
2521 &rs6000_reg_names[27][0], /* r27 */ \
2522 &rs6000_reg_names[28][0], /* r28 */ \
2523 &rs6000_reg_names[29][0], /* r29 */ \
2524 &rs6000_reg_names[30][0], /* r30 */ \
2525 &rs6000_reg_names[31][0], /* r31 */ \
2527 &rs6000_reg_names[32][0], /* fr0 */ \
2528 &rs6000_reg_names[33][0], /* fr1 */ \
2529 &rs6000_reg_names[34][0], /* fr2 */ \
2530 &rs6000_reg_names[35][0], /* fr3 */ \
2531 &rs6000_reg_names[36][0], /* fr4 */ \
2532 &rs6000_reg_names[37][0], /* fr5 */ \
2533 &rs6000_reg_names[38][0], /* fr6 */ \
2534 &rs6000_reg_names[39][0], /* fr7 */ \
2535 &rs6000_reg_names[40][0], /* fr8 */ \
2536 &rs6000_reg_names[41][0], /* fr9 */ \
2537 &rs6000_reg_names[42][0], /* fr10 */ \
2538 &rs6000_reg_names[43][0], /* fr11 */ \
2539 &rs6000_reg_names[44][0], /* fr12 */ \
2540 &rs6000_reg_names[45][0], /* fr13 */ \
2541 &rs6000_reg_names[46][0], /* fr14 */ \
2542 &rs6000_reg_names[47][0], /* fr15 */ \
2543 &rs6000_reg_names[48][0], /* fr16 */ \
2544 &rs6000_reg_names[49][0], /* fr17 */ \
2545 &rs6000_reg_names[50][0], /* fr18 */ \
2546 &rs6000_reg_names[51][0], /* fr19 */ \
2547 &rs6000_reg_names[52][0], /* fr20 */ \
2548 &rs6000_reg_names[53][0], /* fr21 */ \
2549 &rs6000_reg_names[54][0], /* fr22 */ \
2550 &rs6000_reg_names[55][0], /* fr23 */ \
2551 &rs6000_reg_names[56][0], /* fr24 */ \
2552 &rs6000_reg_names[57][0], /* fr25 */ \
2553 &rs6000_reg_names[58][0], /* fr26 */ \
2554 &rs6000_reg_names[59][0], /* fr27 */ \
2555 &rs6000_reg_names[60][0], /* fr28 */ \
2556 &rs6000_reg_names[61][0], /* fr29 */ \
2557 &rs6000_reg_names[62][0], /* fr30 */ \
2558 &rs6000_reg_names[63][0], /* fr31 */ \
2560 &rs6000_reg_names[64][0], /* mq */ \
2561 &rs6000_reg_names[65][0], /* lr */ \
2562 &rs6000_reg_names[66][0], /* ctr */ \
2563 &rs6000_reg_names[67][0], /* ap */ \
2565 &rs6000_reg_names[68][0], /* cr0 */ \
2566 &rs6000_reg_names[69][0], /* cr1 */ \
2567 &rs6000_reg_names[70][0], /* cr2 */ \
2568 &rs6000_reg_names[71][0], /* cr3 */ \
2569 &rs6000_reg_names[72][0], /* cr4 */ \
2570 &rs6000_reg_names[73][0], /* cr5 */ \
2571 &rs6000_reg_names[74][0], /* cr6 */ \
2572 &rs6000_reg_names[75][0], /* cr7 */ \
2574 &rs6000_reg_names[76][0], /* xer */ \
2576 &rs6000_reg_names[77][0], /* v0 */ \
2577 &rs6000_reg_names[78][0], /* v1 */ \
2578 &rs6000_reg_names[79][0], /* v2 */ \
2579 &rs6000_reg_names[80][0], /* v3 */ \
2580 &rs6000_reg_names[81][0], /* v4 */ \
2581 &rs6000_reg_names[82][0], /* v5 */ \
2582 &rs6000_reg_names[83][0], /* v6 */ \
2583 &rs6000_reg_names[84][0], /* v7 */ \
2584 &rs6000_reg_names[85][0], /* v8 */ \
2585 &rs6000_reg_names[86][0], /* v9 */ \
2586 &rs6000_reg_names[87][0], /* v10 */ \
2587 &rs6000_reg_names[88][0], /* v11 */ \
2588 &rs6000_reg_names[89][0], /* v12 */ \
2589 &rs6000_reg_names[90][0], /* v13 */ \
2590 &rs6000_reg_names[91][0], /* v14 */ \
2591 &rs6000_reg_names[92][0], /* v15 */ \
2592 &rs6000_reg_names[93][0], /* v16 */ \
2593 &rs6000_reg_names[94][0], /* v17 */ \
2594 &rs6000_reg_names[95][0], /* v18 */ \
2595 &rs6000_reg_names[96][0], /* v19 */ \
2596 &rs6000_reg_names[97][0], /* v20 */ \
2597 &rs6000_reg_names[98][0], /* v21 */ \
2598 &rs6000_reg_names[99][0], /* v22 */ \
2599 &rs6000_reg_names[100][0], /* v23 */ \
2600 &rs6000_reg_names[101][0], /* v24 */ \
2601 &rs6000_reg_names[102][0], /* v25 */ \
2602 &rs6000_reg_names[103][0], /* v26 */ \
2603 &rs6000_reg_names[104][0], /* v27 */ \
2604 &rs6000_reg_names[105][0], /* v28 */ \
2605 &rs6000_reg_names[106][0], /* v29 */ \
2606 &rs6000_reg_names[107][0], /* v30 */ \
2607 &rs6000_reg_names[108][0], /* v31 */ \
2608 &rs6000_reg_names[109][0], /* vrsave */ \
2609 &rs6000_reg_names[110][0], /* vscr */ \
2610 &rs6000_reg_names[111][0], /* spe_acc */ \
2611 &rs6000_reg_names[112][0], /* spefscr */ \
2614 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2615 following for it. Switch to use the alternate names since
2616 they are more mnemonic. */
2618 #define DEBUG_REGISTER_NAMES \
2620 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2621 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2622 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2623 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2624 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2625 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2626 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2627 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2628 "mq", "lr", "ctr", "ap", \
2629 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2631 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2632 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2633 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2634 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2636 "spe_acc", "spefscr" \
2639 /* Table of additional register names to use in user input. */
2641 #define ADDITIONAL_REGISTER_NAMES \
2642 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2643 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2644 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2645 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2646 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2647 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2648 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2649 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2650 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2651 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2652 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2653 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2654 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2655 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2656 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2657 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2658 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2659 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2660 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2661 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2662 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2663 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2664 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2665 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2666 {"vrsave", 109}, {"vscr", 110}, \
2667 {"spe_acc", 111}, {"spefscr", 112}, \
2668 /* no additional names for: mq, lr, ctr, ap */ \
2669 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2670 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2671 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2673 /* Text to write out after a CALL that may be replaced by glue code by
2674 the loader. This depends on the AIX version. */
2675 #define RS6000_CALL_GLUE "cror 31,31,31"
2677 /* This is how to output an element of a case-vector that is relative. */
2679 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2680 do { char buf[100]; \
2681 fputs ("\t.long ", FILE); \
2682 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2683 assemble_name (FILE, buf); \
2685 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2686 assemble_name (FILE, buf); \
2687 putc ('\n', FILE); \
2690 /* This is how to output an assembler line
2691 that says to advance the location counter
2692 to a multiple of 2**LOG bytes. */
2694 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2696 fprintf (FILE, "\t.align %d\n", (LOG))
2698 /* Pick up the return address upon entry to a procedure. Used for
2699 dwarf2 unwind information. This also enables the table driven
2702 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2703 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2705 /* Describe how we implement __builtin_eh_return. */
2706 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2707 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2709 /* Print operand X (an rtx) in assembler syntax to file FILE.
2710 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2711 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2713 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2715 /* Define which CODE values are valid. */
2717 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2720 /* Print a memory address as an operand to reference that memory location. */
2722 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2724 /* Define the codes that are matched by predicates in rs6000.c. */
2726 #define PREDICATE_CODES \
2727 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2728 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2729 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2730 LABEL_REF, SUBREG, REG, MEM}}, \
2731 {"short_cint_operand", {CONST_INT}}, \
2732 {"u_short_cint_operand", {CONST_INT}}, \
2733 {"non_short_cint_operand", {CONST_INT}}, \
2734 {"exact_log2_cint_operand", {CONST_INT}}, \
2735 {"gpc_reg_operand", {SUBREG, REG}}, \
2736 {"cc_reg_operand", {SUBREG, REG}}, \
2737 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2738 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2739 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2740 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2741 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2742 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2743 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2744 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2745 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2746 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2747 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2748 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2749 {"easy_fp_constant", {CONST_DOUBLE}}, \
2750 {"easy_vector_constant", {CONST_VECTOR}}, \
2751 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2752 {"zero_fp_constant", {CONST_DOUBLE}}, \
2753 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2754 {"lwa_operand", {SUBREG, MEM, REG}}, \
2755 {"volatile_mem_operand", {MEM}}, \
2756 {"offsettable_mem_operand", {MEM}}, \
2757 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2758 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2759 {"non_add_cint_operand", {CONST_INT}}, \
2760 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2761 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2762 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2763 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2764 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2765 {"mask_operand", {CONST_INT}}, \
2766 {"mask_operand_wrap", {CONST_INT}}, \
2767 {"mask64_operand", {CONST_INT}}, \
2768 {"mask64_2_operand", {CONST_INT}}, \
2769 {"count_register_operand", {REG}}, \
2770 {"xer_operand", {REG}}, \
2771 {"symbol_ref_operand", {SYMBOL_REF}}, \
2772 {"call_operand", {SYMBOL_REF, REG}}, \
2773 {"current_file_function_operand", {SYMBOL_REF}}, \
2774 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2775 CONST_DOUBLE, SYMBOL_REF}}, \
2776 {"load_multiple_operation", {PARALLEL}}, \
2777 {"store_multiple_operation", {PARALLEL}}, \
2778 {"vrsave_operation", {PARALLEL}}, \
2779 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2780 GT, LEU, LTU, GEU, GTU, \
2781 UNORDERED, ORDERED, \
2783 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2785 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2786 GT, LEU, LTU, GEU, GTU, \
2787 UNORDERED, ORDERED, \
2789 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2790 GT, LEU, LTU, GEU, GTU}}, \
2791 {"boolean_operator", {AND, IOR, XOR}}, \
2792 {"boolean_or_operator", {IOR, XOR}}, \
2793 {"altivec_register_operand", {REG}}, \
2794 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2796 /* uncomment for disabling the corresponding default options */
2797 /* #define MACHINE_no_sched_interblock */
2798 /* #define MACHINE_no_sched_speculative */
2799 /* #define MACHINE_no_sched_speculative_load */
2801 /* General flags. */
2802 extern int flag_pic;
2803 extern int optimize;
2804 extern int flag_expensive_optimizations;
2805 extern int frame_pointer_needed;
2807 enum rs6000_builtins
2809 /* AltiVec builtins. */
2810 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2811 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2812 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2813 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2814 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2815 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2816 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2817 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2818 ALTIVEC_BUILTIN_VADDUBM,
2819 ALTIVEC_BUILTIN_VADDUHM,
2820 ALTIVEC_BUILTIN_VADDUWM,
2821 ALTIVEC_BUILTIN_VADDFP,
2822 ALTIVEC_BUILTIN_VADDCUW,
2823 ALTIVEC_BUILTIN_VADDUBS,
2824 ALTIVEC_BUILTIN_VADDSBS,
2825 ALTIVEC_BUILTIN_VADDUHS,
2826 ALTIVEC_BUILTIN_VADDSHS,
2827 ALTIVEC_BUILTIN_VADDUWS,
2828 ALTIVEC_BUILTIN_VADDSWS,
2829 ALTIVEC_BUILTIN_VAND,
2830 ALTIVEC_BUILTIN_VANDC,
2831 ALTIVEC_BUILTIN_VAVGUB,
2832 ALTIVEC_BUILTIN_VAVGSB,
2833 ALTIVEC_BUILTIN_VAVGUH,
2834 ALTIVEC_BUILTIN_VAVGSH,
2835 ALTIVEC_BUILTIN_VAVGUW,
2836 ALTIVEC_BUILTIN_VAVGSW,
2837 ALTIVEC_BUILTIN_VCFUX,
2838 ALTIVEC_BUILTIN_VCFSX,
2839 ALTIVEC_BUILTIN_VCTSXS,
2840 ALTIVEC_BUILTIN_VCTUXS,
2841 ALTIVEC_BUILTIN_VCMPBFP,
2842 ALTIVEC_BUILTIN_VCMPEQUB,
2843 ALTIVEC_BUILTIN_VCMPEQUH,
2844 ALTIVEC_BUILTIN_VCMPEQUW,
2845 ALTIVEC_BUILTIN_VCMPEQFP,
2846 ALTIVEC_BUILTIN_VCMPGEFP,
2847 ALTIVEC_BUILTIN_VCMPGTUB,
2848 ALTIVEC_BUILTIN_VCMPGTSB,
2849 ALTIVEC_BUILTIN_VCMPGTUH,
2850 ALTIVEC_BUILTIN_VCMPGTSH,
2851 ALTIVEC_BUILTIN_VCMPGTUW,
2852 ALTIVEC_BUILTIN_VCMPGTSW,
2853 ALTIVEC_BUILTIN_VCMPGTFP,
2854 ALTIVEC_BUILTIN_VEXPTEFP,
2855 ALTIVEC_BUILTIN_VLOGEFP,
2856 ALTIVEC_BUILTIN_VMADDFP,
2857 ALTIVEC_BUILTIN_VMAXUB,
2858 ALTIVEC_BUILTIN_VMAXSB,
2859 ALTIVEC_BUILTIN_VMAXUH,
2860 ALTIVEC_BUILTIN_VMAXSH,
2861 ALTIVEC_BUILTIN_VMAXUW,
2862 ALTIVEC_BUILTIN_VMAXSW,
2863 ALTIVEC_BUILTIN_VMAXFP,
2864 ALTIVEC_BUILTIN_VMHADDSHS,
2865 ALTIVEC_BUILTIN_VMHRADDSHS,
2866 ALTIVEC_BUILTIN_VMLADDUHM,
2867 ALTIVEC_BUILTIN_VMRGHB,
2868 ALTIVEC_BUILTIN_VMRGHH,
2869 ALTIVEC_BUILTIN_VMRGHW,
2870 ALTIVEC_BUILTIN_VMRGLB,
2871 ALTIVEC_BUILTIN_VMRGLH,
2872 ALTIVEC_BUILTIN_VMRGLW,
2873 ALTIVEC_BUILTIN_VMSUMUBM,
2874 ALTIVEC_BUILTIN_VMSUMMBM,
2875 ALTIVEC_BUILTIN_VMSUMUHM,
2876 ALTIVEC_BUILTIN_VMSUMSHM,
2877 ALTIVEC_BUILTIN_VMSUMUHS,
2878 ALTIVEC_BUILTIN_VMSUMSHS,
2879 ALTIVEC_BUILTIN_VMINUB,
2880 ALTIVEC_BUILTIN_VMINSB,
2881 ALTIVEC_BUILTIN_VMINUH,
2882 ALTIVEC_BUILTIN_VMINSH,
2883 ALTIVEC_BUILTIN_VMINUW,
2884 ALTIVEC_BUILTIN_VMINSW,
2885 ALTIVEC_BUILTIN_VMINFP,
2886 ALTIVEC_BUILTIN_VMULEUB,
2887 ALTIVEC_BUILTIN_VMULESB,
2888 ALTIVEC_BUILTIN_VMULEUH,
2889 ALTIVEC_BUILTIN_VMULESH,
2890 ALTIVEC_BUILTIN_VMULOUB,
2891 ALTIVEC_BUILTIN_VMULOSB,
2892 ALTIVEC_BUILTIN_VMULOUH,
2893 ALTIVEC_BUILTIN_VMULOSH,
2894 ALTIVEC_BUILTIN_VNMSUBFP,
2895 ALTIVEC_BUILTIN_VNOR,
2896 ALTIVEC_BUILTIN_VOR,
2897 ALTIVEC_BUILTIN_VSEL_4SI,
2898 ALTIVEC_BUILTIN_VSEL_4SF,
2899 ALTIVEC_BUILTIN_VSEL_8HI,
2900 ALTIVEC_BUILTIN_VSEL_16QI,
2901 ALTIVEC_BUILTIN_VPERM_4SI,
2902 ALTIVEC_BUILTIN_VPERM_4SF,
2903 ALTIVEC_BUILTIN_VPERM_8HI,
2904 ALTIVEC_BUILTIN_VPERM_16QI,
2905 ALTIVEC_BUILTIN_VPKUHUM,
2906 ALTIVEC_BUILTIN_VPKUWUM,
2907 ALTIVEC_BUILTIN_VPKPX,
2908 ALTIVEC_BUILTIN_VPKUHSS,
2909 ALTIVEC_BUILTIN_VPKSHSS,
2910 ALTIVEC_BUILTIN_VPKUWSS,
2911 ALTIVEC_BUILTIN_VPKSWSS,
2912 ALTIVEC_BUILTIN_VPKUHUS,
2913 ALTIVEC_BUILTIN_VPKSHUS,
2914 ALTIVEC_BUILTIN_VPKUWUS,
2915 ALTIVEC_BUILTIN_VPKSWUS,
2916 ALTIVEC_BUILTIN_VREFP,
2917 ALTIVEC_BUILTIN_VRFIM,
2918 ALTIVEC_BUILTIN_VRFIN,
2919 ALTIVEC_BUILTIN_VRFIP,
2920 ALTIVEC_BUILTIN_VRFIZ,
2921 ALTIVEC_BUILTIN_VRLB,
2922 ALTIVEC_BUILTIN_VRLH,
2923 ALTIVEC_BUILTIN_VRLW,
2924 ALTIVEC_BUILTIN_VRSQRTEFP,
2925 ALTIVEC_BUILTIN_VSLB,
2926 ALTIVEC_BUILTIN_VSLH,
2927 ALTIVEC_BUILTIN_VSLW,
2928 ALTIVEC_BUILTIN_VSL,
2929 ALTIVEC_BUILTIN_VSLO,
2930 ALTIVEC_BUILTIN_VSPLTB,
2931 ALTIVEC_BUILTIN_VSPLTH,
2932 ALTIVEC_BUILTIN_VSPLTW,
2933 ALTIVEC_BUILTIN_VSPLTISB,
2934 ALTIVEC_BUILTIN_VSPLTISH,
2935 ALTIVEC_BUILTIN_VSPLTISW,
2936 ALTIVEC_BUILTIN_VSRB,
2937 ALTIVEC_BUILTIN_VSRH,
2938 ALTIVEC_BUILTIN_VSRW,
2939 ALTIVEC_BUILTIN_VSRAB,
2940 ALTIVEC_BUILTIN_VSRAH,
2941 ALTIVEC_BUILTIN_VSRAW,
2942 ALTIVEC_BUILTIN_VSR,
2943 ALTIVEC_BUILTIN_VSRO,
2944 ALTIVEC_BUILTIN_VSUBUBM,
2945 ALTIVEC_BUILTIN_VSUBUHM,
2946 ALTIVEC_BUILTIN_VSUBUWM,
2947 ALTIVEC_BUILTIN_VSUBFP,
2948 ALTIVEC_BUILTIN_VSUBCUW,
2949 ALTIVEC_BUILTIN_VSUBUBS,
2950 ALTIVEC_BUILTIN_VSUBSBS,
2951 ALTIVEC_BUILTIN_VSUBUHS,
2952 ALTIVEC_BUILTIN_VSUBSHS,
2953 ALTIVEC_BUILTIN_VSUBUWS,
2954 ALTIVEC_BUILTIN_VSUBSWS,
2955 ALTIVEC_BUILTIN_VSUM4UBS,
2956 ALTIVEC_BUILTIN_VSUM4SBS,
2957 ALTIVEC_BUILTIN_VSUM4SHS,
2958 ALTIVEC_BUILTIN_VSUM2SWS,
2959 ALTIVEC_BUILTIN_VSUMSWS,
2960 ALTIVEC_BUILTIN_VXOR,
2961 ALTIVEC_BUILTIN_VSLDOI_16QI,
2962 ALTIVEC_BUILTIN_VSLDOI_8HI,
2963 ALTIVEC_BUILTIN_VSLDOI_4SI,
2964 ALTIVEC_BUILTIN_VSLDOI_4SF,
2965 ALTIVEC_BUILTIN_VUPKHSB,
2966 ALTIVEC_BUILTIN_VUPKHPX,
2967 ALTIVEC_BUILTIN_VUPKHSH,
2968 ALTIVEC_BUILTIN_VUPKLSB,
2969 ALTIVEC_BUILTIN_VUPKLPX,
2970 ALTIVEC_BUILTIN_VUPKLSH,
2971 ALTIVEC_BUILTIN_MTVSCR,
2972 ALTIVEC_BUILTIN_MFVSCR,
2973 ALTIVEC_BUILTIN_DSSALL,
2974 ALTIVEC_BUILTIN_DSS,
2975 ALTIVEC_BUILTIN_LVSL,
2976 ALTIVEC_BUILTIN_LVSR,
2977 ALTIVEC_BUILTIN_DSTT,
2978 ALTIVEC_BUILTIN_DSTST,
2979 ALTIVEC_BUILTIN_DSTSTT,
2980 ALTIVEC_BUILTIN_DST,
2981 ALTIVEC_BUILTIN_LVEBX,
2982 ALTIVEC_BUILTIN_LVEHX,
2983 ALTIVEC_BUILTIN_LVEWX,
2984 ALTIVEC_BUILTIN_LVXL,
2985 ALTIVEC_BUILTIN_LVX,
2986 ALTIVEC_BUILTIN_STVX,
2987 ALTIVEC_BUILTIN_STVEBX,
2988 ALTIVEC_BUILTIN_STVEHX,
2989 ALTIVEC_BUILTIN_STVEWX,
2990 ALTIVEC_BUILTIN_STVXL,
2991 ALTIVEC_BUILTIN_VCMPBFP_P,
2992 ALTIVEC_BUILTIN_VCMPEQFP_P,
2993 ALTIVEC_BUILTIN_VCMPEQUB_P,
2994 ALTIVEC_BUILTIN_VCMPEQUH_P,
2995 ALTIVEC_BUILTIN_VCMPEQUW_P,
2996 ALTIVEC_BUILTIN_VCMPGEFP_P,
2997 ALTIVEC_BUILTIN_VCMPGTFP_P,
2998 ALTIVEC_BUILTIN_VCMPGTSB_P,
2999 ALTIVEC_BUILTIN_VCMPGTSH_P,
3000 ALTIVEC_BUILTIN_VCMPGTSW_P,
3001 ALTIVEC_BUILTIN_VCMPGTUB_P,
3002 ALTIVEC_BUILTIN_VCMPGTUH_P,
3003 ALTIVEC_BUILTIN_VCMPGTUW_P,
3004 ALTIVEC_BUILTIN_ABSS_V4SI,
3005 ALTIVEC_BUILTIN_ABSS_V8HI,
3006 ALTIVEC_BUILTIN_ABSS_V16QI,
3007 ALTIVEC_BUILTIN_ABS_V4SI,
3008 ALTIVEC_BUILTIN_ABS_V4SF,
3009 ALTIVEC_BUILTIN_ABS_V8HI,
3010 ALTIVEC_BUILTIN_ABS_V16QI
3012 , SPE_BUILTIN_EVADDW,
3015 SPE_BUILTIN_EVDIVWS,
3016 SPE_BUILTIN_EVDIVWU,
3018 SPE_BUILTIN_EVFSADD,
3019 SPE_BUILTIN_EVFSDIV,
3020 SPE_BUILTIN_EVFSMUL,
3021 SPE_BUILTIN_EVFSSUB,
3025 SPE_BUILTIN_EVLHHESPLATX,
3026 SPE_BUILTIN_EVLHHOSSPLATX,
3027 SPE_BUILTIN_EVLHHOUSPLATX,
3028 SPE_BUILTIN_EVLWHEX,
3029 SPE_BUILTIN_EVLWHOSX,
3030 SPE_BUILTIN_EVLWHOUX,
3031 SPE_BUILTIN_EVLWHSPLATX,
3032 SPE_BUILTIN_EVLWWSPLATX,
3033 SPE_BUILTIN_EVMERGEHI,
3034 SPE_BUILTIN_EVMERGEHILO,
3035 SPE_BUILTIN_EVMERGELO,
3036 SPE_BUILTIN_EVMERGELOHI,
3037 SPE_BUILTIN_EVMHEGSMFAA,
3038 SPE_BUILTIN_EVMHEGSMFAN,
3039 SPE_BUILTIN_EVMHEGSMIAA,
3040 SPE_BUILTIN_EVMHEGSMIAN,
3041 SPE_BUILTIN_EVMHEGUMIAA,
3042 SPE_BUILTIN_EVMHEGUMIAN,
3043 SPE_BUILTIN_EVMHESMF,
3044 SPE_BUILTIN_EVMHESMFA,
3045 SPE_BUILTIN_EVMHESMFAAW,
3046 SPE_BUILTIN_EVMHESMFANW,
3047 SPE_BUILTIN_EVMHESMI,
3048 SPE_BUILTIN_EVMHESMIA,
3049 SPE_BUILTIN_EVMHESMIAAW,
3050 SPE_BUILTIN_EVMHESMIANW,
3051 SPE_BUILTIN_EVMHESSF,
3052 SPE_BUILTIN_EVMHESSFA,
3053 SPE_BUILTIN_EVMHESSFAAW,
3054 SPE_BUILTIN_EVMHESSFANW,
3055 SPE_BUILTIN_EVMHESSIAAW,
3056 SPE_BUILTIN_EVMHESSIANW,
3057 SPE_BUILTIN_EVMHEUMI,
3058 SPE_BUILTIN_EVMHEUMIA,
3059 SPE_BUILTIN_EVMHEUMIAAW,
3060 SPE_BUILTIN_EVMHEUMIANW,
3061 SPE_BUILTIN_EVMHEUSIAAW,
3062 SPE_BUILTIN_EVMHEUSIANW,
3063 SPE_BUILTIN_EVMHOGSMFAA,
3064 SPE_BUILTIN_EVMHOGSMFAN,
3065 SPE_BUILTIN_EVMHOGSMIAA,
3066 SPE_BUILTIN_EVMHOGSMIAN,
3067 SPE_BUILTIN_EVMHOGUMIAA,
3068 SPE_BUILTIN_EVMHOGUMIAN,
3069 SPE_BUILTIN_EVMHOSMF,
3070 SPE_BUILTIN_EVMHOSMFA,
3071 SPE_BUILTIN_EVMHOSMFAAW,
3072 SPE_BUILTIN_EVMHOSMFANW,
3073 SPE_BUILTIN_EVMHOSMI,
3074 SPE_BUILTIN_EVMHOSMIA,
3075 SPE_BUILTIN_EVMHOSMIAAW,
3076 SPE_BUILTIN_EVMHOSMIANW,
3077 SPE_BUILTIN_EVMHOSSF,
3078 SPE_BUILTIN_EVMHOSSFA,
3079 SPE_BUILTIN_EVMHOSSFAAW,
3080 SPE_BUILTIN_EVMHOSSFANW,
3081 SPE_BUILTIN_EVMHOSSIAAW,
3082 SPE_BUILTIN_EVMHOSSIANW,
3083 SPE_BUILTIN_EVMHOUMI,
3084 SPE_BUILTIN_EVMHOUMIA,
3085 SPE_BUILTIN_EVMHOUMIAAW,
3086 SPE_BUILTIN_EVMHOUMIANW,
3087 SPE_BUILTIN_EVMHOUSIAAW,
3088 SPE_BUILTIN_EVMHOUSIANW,
3089 SPE_BUILTIN_EVMWHSMF,
3090 SPE_BUILTIN_EVMWHSMFA,
3091 SPE_BUILTIN_EVMWHSMI,
3092 SPE_BUILTIN_EVMWHSMIA,
3093 SPE_BUILTIN_EVMWHSSF,
3094 SPE_BUILTIN_EVMWHSSFA,
3095 SPE_BUILTIN_EVMWHUMI,
3096 SPE_BUILTIN_EVMWHUMIA,
3097 SPE_BUILTIN_EVMWLSMIAAW,
3098 SPE_BUILTIN_EVMWLSMIANW,
3099 SPE_BUILTIN_EVMWLSSIAAW,
3100 SPE_BUILTIN_EVMWLSSIANW,
3101 SPE_BUILTIN_EVMWLUMI,
3102 SPE_BUILTIN_EVMWLUMIA,
3103 SPE_BUILTIN_EVMWLUMIAAW,
3104 SPE_BUILTIN_EVMWLUMIANW,
3105 SPE_BUILTIN_EVMWLUSIAAW,
3106 SPE_BUILTIN_EVMWLUSIANW,
3107 SPE_BUILTIN_EVMWSMF,
3108 SPE_BUILTIN_EVMWSMFA,
3109 SPE_BUILTIN_EVMWSMFAA,
3110 SPE_BUILTIN_EVMWSMFAN,
3111 SPE_BUILTIN_EVMWSMI,
3112 SPE_BUILTIN_EVMWSMIA,
3113 SPE_BUILTIN_EVMWSMIAA,
3114 SPE_BUILTIN_EVMWSMIAN,
3115 SPE_BUILTIN_EVMWHSSFAA,
3116 SPE_BUILTIN_EVMWSSF,
3117 SPE_BUILTIN_EVMWSSFA,
3118 SPE_BUILTIN_EVMWSSFAA,
3119 SPE_BUILTIN_EVMWSSFAN,
3120 SPE_BUILTIN_EVMWUMI,
3121 SPE_BUILTIN_EVMWUMIA,
3122 SPE_BUILTIN_EVMWUMIAA,
3123 SPE_BUILTIN_EVMWUMIAN,
3132 SPE_BUILTIN_EVSTDDX,
3133 SPE_BUILTIN_EVSTDHX,
3134 SPE_BUILTIN_EVSTDWX,
3135 SPE_BUILTIN_EVSTWHEX,
3136 SPE_BUILTIN_EVSTWHOX,
3137 SPE_BUILTIN_EVSTWWEX,
3138 SPE_BUILTIN_EVSTWWOX,
3139 SPE_BUILTIN_EVSUBFW,
3142 SPE_BUILTIN_EVADDSMIAAW,
3143 SPE_BUILTIN_EVADDSSIAAW,
3144 SPE_BUILTIN_EVADDUMIAAW,
3145 SPE_BUILTIN_EVADDUSIAAW,
3146 SPE_BUILTIN_EVCNTLSW,
3147 SPE_BUILTIN_EVCNTLZW,
3148 SPE_BUILTIN_EVEXTSB,
3149 SPE_BUILTIN_EVEXTSH,
3150 SPE_BUILTIN_EVFSABS,
3151 SPE_BUILTIN_EVFSCFSF,
3152 SPE_BUILTIN_EVFSCFSI,
3153 SPE_BUILTIN_EVFSCFUF,
3154 SPE_BUILTIN_EVFSCFUI,
3155 SPE_BUILTIN_EVFSCTSF,
3156 SPE_BUILTIN_EVFSCTSI,
3157 SPE_BUILTIN_EVFSCTSIZ,
3158 SPE_BUILTIN_EVFSCTUF,
3159 SPE_BUILTIN_EVFSCTUI,
3160 SPE_BUILTIN_EVFSCTUIZ,
3161 SPE_BUILTIN_EVFSNABS,
3162 SPE_BUILTIN_EVFSNEG,
3166 SPE_BUILTIN_EVSUBFSMIAAW,
3167 SPE_BUILTIN_EVSUBFSSIAAW,
3168 SPE_BUILTIN_EVSUBFUMIAAW,
3169 SPE_BUILTIN_EVSUBFUSIAAW,
3170 SPE_BUILTIN_EVADDIW,
3174 SPE_BUILTIN_EVLHHESPLAT,
3175 SPE_BUILTIN_EVLHHOSSPLAT,
3176 SPE_BUILTIN_EVLHHOUSPLAT,
3178 SPE_BUILTIN_EVLWHOS,
3179 SPE_BUILTIN_EVLWHOU,
3180 SPE_BUILTIN_EVLWHSPLAT,
3181 SPE_BUILTIN_EVLWWSPLAT,
3184 SPE_BUILTIN_EVSRWIS,
3185 SPE_BUILTIN_EVSRWIU,
3189 SPE_BUILTIN_EVSTWHE,
3190 SPE_BUILTIN_EVSTWHO,
3191 SPE_BUILTIN_EVSTWWE,
3192 SPE_BUILTIN_EVSTWWO,
3193 SPE_BUILTIN_EVSUBIFW,
3196 SPE_BUILTIN_EVCMPEQ,
3197 SPE_BUILTIN_EVCMPGTS,
3198 SPE_BUILTIN_EVCMPGTU,
3199 SPE_BUILTIN_EVCMPLTS,
3200 SPE_BUILTIN_EVCMPLTU,
3201 SPE_BUILTIN_EVFSCMPEQ,
3202 SPE_BUILTIN_EVFSCMPGT,
3203 SPE_BUILTIN_EVFSCMPLT,
3204 SPE_BUILTIN_EVFSTSTEQ,
3205 SPE_BUILTIN_EVFSTSTGT,
3206 SPE_BUILTIN_EVFSTSTLT,
3208 /* EVSEL compares. */
3209 SPE_BUILTIN_EVSEL_CMPEQ,
3210 SPE_BUILTIN_EVSEL_CMPGTS,
3211 SPE_BUILTIN_EVSEL_CMPGTU,
3212 SPE_BUILTIN_EVSEL_CMPLTS,
3213 SPE_BUILTIN_EVSEL_CMPLTU,
3214 SPE_BUILTIN_EVSEL_FSCMPEQ,
3215 SPE_BUILTIN_EVSEL_FSCMPGT,
3216 SPE_BUILTIN_EVSEL_FSCMPLT,
3217 SPE_BUILTIN_EVSEL_FSTSTEQ,
3218 SPE_BUILTIN_EVSEL_FSTSTGT,
3219 SPE_BUILTIN_EVSEL_FSTSTLT,
3221 SPE_BUILTIN_EVSPLATFI,
3222 SPE_BUILTIN_EVSPLATI,
3223 SPE_BUILTIN_EVMWHSSMAA,
3224 SPE_BUILTIN_EVMWHSMFAA,
3225 SPE_BUILTIN_EVMWHSMIAA,
3226 SPE_BUILTIN_EVMWHUSIAA,
3227 SPE_BUILTIN_EVMWHUMIAA,
3228 SPE_BUILTIN_EVMWHSSFAN,
3229 SPE_BUILTIN_EVMWHSSIAN,
3230 SPE_BUILTIN_EVMWHSMFAN,
3231 SPE_BUILTIN_EVMWHSMIAN,
3232 SPE_BUILTIN_EVMWHUSIAN,
3233 SPE_BUILTIN_EVMWHUMIAN,
3234 SPE_BUILTIN_EVMWHGSSFAA,
3235 SPE_BUILTIN_EVMWHGSMFAA,
3236 SPE_BUILTIN_EVMWHGSMIAA,
3237 SPE_BUILTIN_EVMWHGUMIAA,
3238 SPE_BUILTIN_EVMWHGSSFAN,
3239 SPE_BUILTIN_EVMWHGSMFAN,
3240 SPE_BUILTIN_EVMWHGSMIAN,
3241 SPE_BUILTIN_EVMWHGUMIAN,
3242 SPE_BUILTIN_MTSPEFSCR,
3243 SPE_BUILTIN_MFSPEFSCR,
OSDN Git Service
