1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 /* Common ASM definitions used by ASM_SPEC among the various targets
60 for handling -mcpu=xxx switches. */
61 #define ASM_CPU_SPEC \
63 %{mpower: %{!mpower2: -mpwr}} \
65 %{mpowerpc64*: -mppc64} \
66 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
67 %{mno-power: %{!mpowerpc*: -mcom}} \
68 %{!mno-power: %{!mpower*: %(asm_default)}}} \
69 %{mcpu=common: -mcom} \
70 %{mcpu=cell: -mcell} \
71 %{mcpu=power: -mpwr} \
72 %{mcpu=power2: -mpwrx} \
73 %{mcpu=power3: -mppc64} \
74 %{mcpu=power4: -mpower4} \
75 %{mcpu=power5: -mpower4} \
76 %{mcpu=power5+: -mpower4} \
77 %{mcpu=power6: -mpower4 -maltivec} \
78 %{mcpu=power6x: -mpower4 -maltivec} \
79 %{mcpu=powerpc: -mppc} \
81 %{mcpu=rios1: -mpwr} \
82 %{mcpu=rios2: -mpwrx} \
85 %{mcpu=rs64a: -mppc64} \
89 %{mcpu=405fp: -m405} \
91 %{mcpu=440fp: -m440} \
97 %{mcpu=ec603e: -mppc} \
100 %{mcpu=620: -mppc64} \
101 %{mcpu=630: -mppc64} \
105 %{mcpu=7400: -mppc -maltivec} \
106 %{mcpu=7450: -mppc -maltivec} \
107 %{mcpu=G4: -mppc -maltivec} \
112 %{mcpu=970: -mpower4 -maltivec} \
113 %{mcpu=G5: -mpower4 -maltivec} \
114 %{mcpu=8540: -me500} \
115 %{maltivec: -maltivec} \
118 #define CPP_DEFAULT_SPEC ""
120 #define ASM_DEFAULT_SPEC ""
122 /* This macro defines names of additional specifications to put in the specs
123 that can be used in various specifications like CC1_SPEC. Its definition
124 is an initializer with a subgrouping for each command option.
126 Each subgrouping contains a string constant, that defines the
127 specification name, and a string constant that used by the GCC driver
130 Do not define this macro if it does not need to do anything. */
132 #define SUBTARGET_EXTRA_SPECS
134 #define EXTRA_SPECS \
135 { "cpp_default", CPP_DEFAULT_SPEC }, \
136 { "asm_cpu", ASM_CPU_SPEC }, \
137 { "asm_default", ASM_DEFAULT_SPEC }, \
138 SUBTARGET_EXTRA_SPECS
140 /* Architecture type. */
142 /* Define TARGET_MFCRF if the target assembler does not support the
143 optional field operand for mfcr. */
145 #ifndef HAVE_AS_MFCRF
147 #define TARGET_MFCRF 0
150 /* Define TARGET_POPCNTB if the target assembler does not support the
151 popcount byte instruction. */
153 #ifndef HAVE_AS_POPCNTB
154 #undef TARGET_POPCNTB
155 #define TARGET_POPCNTB 0
158 /* Define TARGET_FPRND if the target assembler does not support the
159 fp rounding instructions. */
161 #ifndef HAVE_AS_FPRND
163 #define TARGET_FPRND 0
166 /* Define TARGET_CMPB if the target assembler does not support the
171 #define TARGET_CMPB 0
174 /* Define TARGET_MFPGPR if the target assembler does not support the
175 mffpr and mftgpr instructions. */
177 #ifndef HAVE_AS_MFPGPR
179 #define TARGET_MFPGPR 0
182 /* Define TARGET_DFP if the target assembler does not support decimal
183 floating point instructions. */
189 #ifndef TARGET_SECURE_PLT
190 #define TARGET_SECURE_PLT 0
193 #define TARGET_32BIT (! TARGET_64BIT)
196 #define HAVE_AS_TLS 0
199 /* Return 1 for a symbol ref for a thread-local storage symbol. */
200 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
201 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
204 /* For libgcc2 we make sure this is a compile time constant */
205 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
206 #undef TARGET_POWERPC64
207 #define TARGET_POWERPC64 1
209 #undef TARGET_POWERPC64
210 #define TARGET_POWERPC64 0
213 /* The option machinery will define this. */
216 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
218 /* Processor type. Order must match cpu attribute in MD file. */
244 extern enum processor_type rs6000_cpu;
246 /* Recast the processor type to the cpu attribute. */
247 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
249 /* Define generic processor types based upon current deployment. */
250 #define PROCESSOR_COMMON PROCESSOR_PPC601
251 #define PROCESSOR_POWER PROCESSOR_RIOS1
252 #define PROCESSOR_POWERPC PROCESSOR_PPC604
253 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
255 /* Define the default processor. This is overridden by other tm.h files. */
256 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
257 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
259 /* Specify the dialect of assembler to use. New mnemonics is dialect one
260 and the old mnemonics are dialect zero. */
261 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
263 /* Types of costly dependences. */
264 enum rs6000_dependence_cost
266 max_dep_latency = 1000,
269 true_store_to_load_dep_costly,
270 store_to_load_dep_costly
273 /* Types of nop insertion schemes in sched target hook sched_finish. */
274 enum rs6000_nop_insertion
276 sched_finish_regroup_exact = 1000,
277 sched_finish_pad_groups,
281 /* Dispatch group termination caused by an insn. */
282 enum group_termination
288 /* Support for a compile-time default CPU, et cetera. The rules are:
289 --with-cpu is ignored if -mcpu is specified.
290 --with-tune is ignored if -mtune is specified.
291 --with-float is ignored if -mhard-float or -msoft-float are
293 #define OPTION_DEFAULT_SPECS \
294 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
295 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
296 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
298 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
299 struct rs6000_cpu_select
307 extern struct rs6000_cpu_select rs6000_select[];
310 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
311 extern int rs6000_debug_stack; /* debug stack applications */
312 extern int rs6000_debug_arg; /* debug argument handling */
314 #define TARGET_DEBUG_STACK rs6000_debug_stack
315 #define TARGET_DEBUG_ARG rs6000_debug_arg
317 extern const char *rs6000_traceback_name; /* Type of traceback table. */
319 /* These are separate from target_flags because we've run out of bits
321 extern int rs6000_long_double_type_size;
322 extern int rs6000_ieeequad;
323 extern int rs6000_altivec_abi;
324 extern int rs6000_spe_abi;
325 extern int rs6000_float_gprs;
326 extern int rs6000_alignment_flags;
327 extern const char *rs6000_sched_insert_nops_str;
328 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
330 /* Alignment options for fields in structures for sub-targets following
332 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
333 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
335 Override the macro definitions when compiling libobjc to avoid undefined
336 reference to rs6000_alignment_flags due to library's use of GCC alignment
337 macros which use the macros below. */
339 #ifndef IN_TARGET_LIBS
340 #define MASK_ALIGN_POWER 0x00000000
341 #define MASK_ALIGN_NATURAL 0x00000001
342 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
344 #define TARGET_ALIGN_NATURAL 0
347 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
348 #define TARGET_IEEEQUAD rs6000_ieeequad
349 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
351 #define TARGET_SPE_ABI 0
353 #define TARGET_E500 0
354 #define TARGET_ISEL 0
355 #define TARGET_FPRS 1
356 #define TARGET_E500_SINGLE 0
357 #define TARGET_E500_DOUBLE 0
358 #define CHECK_E500_OPTIONS do { } while (0)
360 /* E500 processors only support plain "sync", not lwsync. */
361 #define TARGET_NO_LWSYNC TARGET_E500
363 /* Sometimes certain combinations of command options do not make sense
364 on a particular target machine. You can define a macro
365 `OVERRIDE_OPTIONS' to take account of this. This macro, if
366 defined, is executed once just after all the command options have
369 Do not use this macro to turn on various extra optimizations for
370 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
372 On the RS/6000 this is used to define the target cpu type. */
374 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
376 /* Define this to change the optimizations performed by default. */
377 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
379 /* Show we can debug even without a frame pointer. */
380 #define CAN_DEBUG_WITHOUT_FP
383 #define REGISTER_TARGET_PRAGMAS() do { \
384 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
385 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
388 /* Target #defines. */
389 #define TARGET_CPU_CPP_BUILTINS() \
390 rs6000_cpu_cpp_builtins (pfile)
392 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
393 we're compiling for. Some configurations may need to override it. */
394 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
397 if (BYTES_BIG_ENDIAN) \
399 builtin_define ("__BIG_ENDIAN__"); \
400 builtin_define ("_BIG_ENDIAN"); \
401 builtin_assert ("machine=bigendian"); \
405 builtin_define ("__LITTLE_ENDIAN__"); \
406 builtin_define ("_LITTLE_ENDIAN"); \
407 builtin_assert ("machine=littleendian"); \
412 /* Target machine storage layout. */
414 /* Define this macro if it is advisable to hold scalars in registers
415 in a wider mode than that declared by the program. In such cases,
416 the value is constrained to be within the bounds of the declared
417 type, but kept valid in the wider mode. The signedness of the
418 extension may differ from that of the type. */
420 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
421 if (GET_MODE_CLASS (MODE) == MODE_INT \
422 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
423 (MODE) = TARGET_32BIT ? SImode : DImode;
425 /* Define this if most significant bit is lowest numbered
426 in instructions that operate on numbered bit-fields. */
427 /* That is true on RS/6000. */
428 #define BITS_BIG_ENDIAN 1
430 /* Define this if most significant byte of a word is the lowest numbered. */
431 /* That is true on RS/6000. */
432 #define BYTES_BIG_ENDIAN 1
434 /* Define this if most significant word of a multiword number is lowest
437 For RS/6000 we can decide arbitrarily since there are no machine
438 instructions for them. Might as well be consistent with bits and bytes. */
439 #define WORDS_BIG_ENDIAN 1
441 #define MAX_BITS_PER_WORD 64
443 /* Width of a word, in units (bytes). */
444 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
446 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
448 #define MIN_UNITS_PER_WORD 4
450 #define UNITS_PER_FP_WORD 8
451 #define UNITS_PER_ALTIVEC_WORD 16
452 #define UNITS_PER_SPE_WORD 8
454 /* Type used for ptrdiff_t, as a string used in a declaration. */
455 #define PTRDIFF_TYPE "int"
457 /* Type used for size_t, as a string used in a declaration. */
458 #define SIZE_TYPE "long unsigned int"
460 /* Type used for wchar_t, as a string used in a declaration. */
461 #define WCHAR_TYPE "short unsigned int"
463 /* Width of wchar_t in bits. */
464 #define WCHAR_TYPE_SIZE 16
466 /* A C expression for the size in bits of the type `short' on the
467 target machine. If you don't define this, the default is half a
468 word. (If this would be less than one storage unit, it is
469 rounded up to one unit.) */
470 #define SHORT_TYPE_SIZE 16
472 /* A C expression for the size in bits of the type `int' on the
473 target machine. If you don't define this, the default is one
475 #define INT_TYPE_SIZE 32
477 /* A C expression for the size in bits of the type `long' on the
478 target machine. If you don't define this, the default is one
480 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
482 /* A C expression for the size in bits of the type `long long' on the
483 target machine. If you don't define this, the default is two
485 #define LONG_LONG_TYPE_SIZE 64
487 /* A C expression for the size in bits of the type `float' on the
488 target machine. If you don't define this, the default is one
490 #define FLOAT_TYPE_SIZE 32
492 /* A C expression for the size in bits of the type `double' on the
493 target machine. If you don't define this, the default is two
495 #define DOUBLE_TYPE_SIZE 64
497 /* A C expression for the size in bits of the type `long double' on
498 the target machine. If you don't define this, the default is two
500 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
502 /* Define this to set long double type size to use in libgcc2.c, which can
503 not depend on target_flags. */
504 #ifdef __LONG_DOUBLE_128__
505 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
507 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
510 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
511 #define WIDEST_HARDWARE_FP_SIZE 64
513 /* Width in bits of a pointer.
514 See also the macro `Pmode' defined below. */
515 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
517 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
518 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
520 /* Boundary (in *bits*) on which stack pointer should be aligned. */
521 #define STACK_BOUNDARY \
522 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
524 /* Allocation boundary (in *bits*) for the code of a function. */
525 #define FUNCTION_BOUNDARY 32
527 /* No data type wants to be aligned rounder than this. */
528 #define BIGGEST_ALIGNMENT 128
530 /* A C expression to compute the alignment for a variables in the
531 local store. TYPE is the data type, and ALIGN is the alignment
532 that the object would ordinarily have. */
533 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
534 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
535 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
536 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
537 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) ? 64 : ALIGN)
539 /* Alignment of field after `int : 0' in a structure. */
540 #define EMPTY_FIELD_BOUNDARY 32
542 /* Every structure's size must be a multiple of this. */
543 #define STRUCTURE_SIZE_BOUNDARY 8
545 /* Return 1 if a structure or array containing FIELD should be
546 accessed using `BLKMODE'.
548 For the SPE, simd types are V2SI, and gcc can be tempted to put the
549 entire thing in a DI and use subregs to access the internals.
550 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
551 back-end. Because a single GPR can hold a V2SI, but not a DI, the
552 best thing to do is set structs to BLKmode and avoid Severe Tire
555 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
556 fit into 1, whereas DI still needs two. */
557 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
558 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
559 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
561 /* A bit-field declared as `int' forces `int' alignment for the struct. */
562 #define PCC_BITFIELD_TYPE_MATTERS 1
564 /* Make strings word-aligned so strcpy from constants will be faster.
565 Make vector constants quadword aligned. */
566 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
567 (TREE_CODE (EXP) == STRING_CST \
568 && (ALIGN) < BITS_PER_WORD \
572 /* Make arrays of chars word-aligned for the same reasons.
573 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
575 #define DATA_ALIGNMENT(TYPE, ALIGN) \
576 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
577 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
578 : TREE_CODE (TYPE) == ARRAY_TYPE \
579 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
580 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
582 /* Nonzero if move instructions will actually fail to work
583 when given unaligned data. */
584 #define STRICT_ALIGNMENT 0
586 /* Define this macro to be the value 1 if unaligned accesses have a cost
587 many times greater than aligned accesses, for example if they are
588 emulated in a trap handler. */
589 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
591 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
592 || (MODE) == DDmode || (MODE) == TDmode \
593 || (MODE) == DImode) \
596 /* Standard register usage. */
598 /* Number of actual hardware registers.
599 The hardware registers are assigned numbers for the compiler
600 from 0 to just below FIRST_PSEUDO_REGISTER.
601 All registers that the compiler knows about must be given numbers,
602 even those that are not normally considered general registers.
604 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
605 an MQ register, a count register, a link register, and 8 condition
606 register fields, which we view here as separate registers. AltiVec
607 adds 32 vector registers and a VRsave register.
609 In addition, the difference between the frame and argument pointers is
610 a function of the number of registers saved, so we need to have a
611 register for AP that will later be eliminated in favor of SP or FP.
612 This is a normal register, but it is fixed.
614 We also create a pseudo register for float/int conversions, that will
615 really represent the memory location used. It is represented here as
616 a register, in order to work around problems in allocating stack storage
619 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
620 pointer, which is eventually eliminated in favor of SP or FP. */
622 #define FIRST_PSEUDO_REGISTER 114
624 /* This must be included for pre gcc 3.0 glibc compatibility. */
625 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
627 /* Add 32 dwarf columns for synthetic SPE registers. */
628 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
630 /* The SPE has an additional 32 synthetic registers, with DWARF debug
631 info numbering for these registers starting at 1200. While eh_frame
632 register numbering need not be the same as the debug info numbering,
633 we choose to number these regs for eh_frame at 1200 too. This allows
634 future versions of the rs6000 backend to add hard registers and
635 continue to use the gcc hard register numbering for eh_frame. If the
636 extra SPE registers in eh_frame were numbered starting from the
637 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
638 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
639 avoid invalidating older SPE eh_frame info.
641 We must map them here to avoid huge unwinder tables mostly consisting
643 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
644 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
646 /* Use standard DWARF numbering for DWARF debugging information. */
647 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
649 /* Use gcc hard register numbering for eh_frame. */
650 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
652 /* Map register numbers held in the call frame info that gcc has
653 collected using DWARF_FRAME_REGNUM to those that should be output in
654 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
655 for .eh_frame, but use the numbers mandated by the various ABIs for
656 .debug_frame. rs6000_emit_prologue has translated any combination of
657 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
658 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
659 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
660 ((FOR_EH) ? (REGNO) \
661 : (REGNO) == CR2_REGNO ? 64 \
662 : DBX_REGISTER_NUMBER (REGNO))
664 /* 1 for registers that have pervasive standard uses
665 and are not available for the register allocator.
667 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
668 as a local register; for all other OS's r2 is the TOC pointer.
670 cr5 is not supposed to be used.
672 On System V implementations, r13 is fixed and not available for use. */
674 #define FIXED_REGISTERS \
675 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
676 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
677 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
678 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
679 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
680 /* AltiVec registers. */ \
681 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
687 /* 1 for registers not available across function calls.
688 These must include the FIXED_REGISTERS and also any
689 registers that can be used without being saved.
690 The latter must include the registers where values are returned
691 and the register where structure-value addresses are passed.
692 Aside from that, you can include as many other registers as you like. */
694 #define CALL_USED_REGISTERS \
695 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
696 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
697 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
698 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
699 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
700 /* AltiVec registers. */ \
701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
707 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
708 the entire set of `FIXED_REGISTERS' be included.
709 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
710 This macro is optional. If not specified, it defaults to the value
711 of `CALL_USED_REGISTERS'. */
713 #define CALL_REALLY_USED_REGISTERS \
714 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
716 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
718 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
719 /* AltiVec registers. */ \
720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
726 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
728 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
729 #define FIRST_SAVED_FP_REGNO (14+32)
730 #define FIRST_SAVED_GP_REGNO 13
732 /* List the order in which to allocate registers. Each register must be
733 listed once, even those in FIXED_REGISTERS.
735 We allocate in the following order:
736 fp0 (not saved or used for anything)
737 fp13 - fp2 (not saved; incoming fp arg registers)
738 fp1 (not saved; return value)
739 fp31 - fp14 (saved; order given to save least number)
740 cr7, cr6 (not saved or special)
741 cr1 (not saved, but used for FP operations)
742 cr0 (not saved, but used for arithmetic operations)
743 cr4, cr3, cr2 (saved)
744 r0 (not saved; cannot be base reg)
745 r9 (not saved; best for TImode)
746 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
747 r3 (not saved; return value register)
748 r31 - r13 (saved; order given to save least number)
749 r12 (not saved; if used for DImode or DFmode would use r13)
750 mq (not saved; best to use it if we can)
751 ctr (not saved; when we have the choice ctr is better)
753 cr5, r1, r2, ap, xer (fixed)
754 v0 - v1 (not saved or used for anything)
755 v13 - v3 (not saved; incoming vector arg registers)
756 v2 (not saved; incoming vector arg reg; return value)
757 v19 - v14 (not saved or used for anything)
758 v31 - v20 (saved; order given to save least number)
760 spe_acc, spefscr (fixed)
765 #define MAYBE_R2_AVAILABLE
766 #define MAYBE_R2_FIXED 2,
768 #define MAYBE_R2_AVAILABLE 2,
769 #define MAYBE_R2_FIXED
772 #define REG_ALLOC_ORDER \
774 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
776 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
777 50, 49, 48, 47, 46, \
778 75, 74, 69, 68, 72, 71, 70, \
779 0, MAYBE_R2_AVAILABLE \
780 9, 11, 10, 8, 7, 6, 5, 4, \
782 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
783 18, 17, 16, 15, 14, 13, 12, \
785 73, 1, MAYBE_R2_FIXED 67, 76, \
786 /* AltiVec registers. */ \
788 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
790 96, 95, 94, 93, 92, 91, \
791 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
796 /* True if register is floating-point. */
797 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
799 /* True if register is a condition register. */
800 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
802 /* True if register is a condition register, but not cr0. */
803 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
805 /* True if register is an integer register. */
806 #define INT_REGNO_P(N) \
807 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
809 /* SPE SIMD registers are just the GPRs. */
810 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
812 /* True if register is the XER register. */
813 #define XER_REGNO_P(N) ((N) == XER_REGNO)
815 /* True if register is an AltiVec register. */
816 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
818 /* Return number of consecutive hard regs needed starting at reg REGNO
819 to hold something of mode MODE. */
821 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
823 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
824 ((TARGET_32BIT && TARGET_POWERPC64 \
825 && (GET_MODE_SIZE (MODE) > 4) \
826 && INT_REGNO_P (REGNO)) ? 1 : 0)
828 #define ALTIVEC_VECTOR_MODE(MODE) \
829 ((MODE) == V16QImode \
830 || (MODE) == V8HImode \
831 || (MODE) == V4SFmode \
832 || (MODE) == V4SImode)
834 #define SPE_VECTOR_MODE(MODE) \
835 ((MODE) == V4HImode \
836 || (MODE) == V2SFmode \
837 || (MODE) == V1DImode \
838 || (MODE) == V2SImode)
840 #define UNITS_PER_SIMD_WORD \
841 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
842 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD))
844 /* Value is TRUE if hard register REGNO can hold a value of
845 machine-mode MODE. */
846 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
847 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
849 /* Value is 1 if it is a good idea to tie two pseudo registers
850 when one has mode MODE1 and one has mode MODE2.
851 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
852 for any hard reg, then this must be 0 for correct output. */
853 #define MODES_TIEABLE_P(MODE1, MODE2) \
854 (SCALAR_FLOAT_MODE_P (MODE1) \
855 ? SCALAR_FLOAT_MODE_P (MODE2) \
856 : SCALAR_FLOAT_MODE_P (MODE2) \
857 ? SCALAR_FLOAT_MODE_P (MODE1) \
858 : GET_MODE_CLASS (MODE1) == MODE_CC \
859 ? GET_MODE_CLASS (MODE2) == MODE_CC \
860 : GET_MODE_CLASS (MODE2) == MODE_CC \
861 ? GET_MODE_CLASS (MODE1) == MODE_CC \
862 : SPE_VECTOR_MODE (MODE1) \
863 ? SPE_VECTOR_MODE (MODE2) \
864 : SPE_VECTOR_MODE (MODE2) \
865 ? SPE_VECTOR_MODE (MODE1) \
866 : ALTIVEC_VECTOR_MODE (MODE1) \
867 ? ALTIVEC_VECTOR_MODE (MODE2) \
868 : ALTIVEC_VECTOR_MODE (MODE2) \
869 ? ALTIVEC_VECTOR_MODE (MODE1) \
872 /* Post-reload, we can't use any new AltiVec registers, as we already
873 emitted the vrsave mask. */
875 #define HARD_REGNO_RENAME_OK(SRC, DST) \
876 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
878 /* A C expression returning the cost of moving data from a register of class
879 CLASS1 to one of CLASS2. */
881 #define REGISTER_MOVE_COST rs6000_register_move_cost
883 /* A C expressions returning the cost of moving data of MODE from a register to
886 #define MEMORY_MOVE_COST rs6000_memory_move_cost
888 /* Specify the cost of a branch insn; roughly the number of extra insns that
889 should be added to avoid a branch.
891 Set this to 3 on the RS/6000 since that is roughly the average cost of an
892 unscheduled conditional branch. */
894 #define BRANCH_COST 3
896 /* Override BRANCH_COST heuristic which empirically produces worse
897 performance for removing short circuiting from the logical ops. */
899 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
901 /* A fixed register used at epilogue generation to address SPE registers
902 with negative offsets. The 64-bit load/store instructions on the SPE
903 only take positive offsets (and small ones at that), so we need to
904 reserve a register for consing up negative offsets. */
906 #define FIXED_SCRATCH 0
908 /* Define this macro to change register usage conditional on target
911 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
913 /* Specify the registers used for certain standard purposes.
914 The values of these macros are register numbers. */
916 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
917 /* #define PC_REGNUM */
919 /* Register to use for pushing function arguments. */
920 #define STACK_POINTER_REGNUM 1
922 /* Base register for access to local variables of the function. */
923 #define HARD_FRAME_POINTER_REGNUM 31
925 /* Base register for access to local variables of the function. */
926 #define FRAME_POINTER_REGNUM 113
928 /* Value should be nonzero if functions must have frame pointers.
929 Zero means the frame pointer need not be set up (and parms
930 may be accessed via the stack pointer) in functions that seem suitable.
931 This is computed in `reload', in reload1.c. */
932 #define FRAME_POINTER_REQUIRED 0
934 /* Base register for access to arguments of the function. */
935 #define ARG_POINTER_REGNUM 67
937 /* Place to put static chain when calling a function that requires it. */
938 #define STATIC_CHAIN_REGNUM 11
941 /* Define the classes of registers for register constraints in the
942 machine description. Also define ranges of constants.
944 One of the classes must always be named ALL_REGS and include all hard regs.
945 If there is more than one class, another class must be named NO_REGS
946 and contain no registers.
948 The name GENERAL_REGS must be the name of a class (or an alias for
949 another name such as ALL_REGS). This is the class of registers
950 that is allowed by "g" or "r" in a register constraint.
951 Also, registers outside this class are allocated only when
952 instructions express preferences for them.
954 The classes must be numbered in nondecreasing order; that is,
955 a larger-numbered class must never be contained completely
956 in a smaller-numbered class.
958 For any two classes, it is very desirable that there be another
959 class that represents their union. */
961 /* The RS/6000 has three types of registers, fixed-point, floating-point,
962 and condition registers, plus three special registers, MQ, CTR, and the
963 link register. AltiVec adds a vector register class.
965 However, r0 is special in that it cannot be used as a base register.
966 So make a class for registers valid as base registers.
968 Also, cr0 is the only condition code register that can be used in
969 arithmetic insns, so make a separate class for it. */
997 #define N_REG_CLASSES (int) LIM_REG_CLASSES
999 /* Give names of register classes as strings for dump file. */
1001 #define REG_CLASS_NAMES \
1012 "NON_SPECIAL_REGS", \
1016 "LINK_OR_CTR_REGS", \
1018 "SPEC_OR_GEN_REGS", \
1026 /* Define which registers fit in which classes.
1027 This is an initializer for a vector of HARD_REG_SET
1028 of length N_REG_CLASSES. */
1030 #define REG_CLASS_CONTENTS \
1032 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1033 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1034 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1035 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1036 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1037 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1038 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1039 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1040 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1041 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1042 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1043 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1044 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1045 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1046 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1047 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1048 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1049 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1050 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1051 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1052 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1055 /* The same information, inverted:
1056 Return the class number of the smallest class containing
1057 reg number REGNO. This could be a conditional expression
1058 or could index an array. */
1060 #define REGNO_REG_CLASS(REGNO) \
1061 ((REGNO) == 0 ? GENERAL_REGS \
1062 : (REGNO) < 32 ? BASE_REGS \
1063 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1064 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1065 : (REGNO) == CR0_REGNO ? CR0_REGS \
1066 : CR_REGNO_P (REGNO) ? CR_REGS \
1067 : (REGNO) == MQ_REGNO ? MQ_REGS \
1068 : (REGNO) == LR_REGNO ? LINK_REGS \
1069 : (REGNO) == CTR_REGNO ? CTR_REGS \
1070 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1071 : (REGNO) == XER_REGNO ? XER_REGS \
1072 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1073 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1074 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1075 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1076 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1079 /* The class value for index registers, and the one for base regs. */
1080 #define INDEX_REG_CLASS GENERAL_REGS
1081 #define BASE_REG_CLASS BASE_REGS
1083 /* Given an rtx X being reloaded into a reg required to be
1084 in class CLASS, return the class of reg to actually use.
1085 In general this is just CLASS; but on some machines
1086 in some cases it is preferable to use a more restrictive class.
1088 On the RS/6000, we have to return NO_REGS when we want to reload a
1089 floating-point CONST_DOUBLE to force it to be copied to memory.
1091 We also don't want to reload integer values into floating-point
1092 registers if we can at all help it. In fact, this can
1093 cause reload to die, if it tries to generate a reload of CTR
1094 into a FP register and discovers it doesn't have the memory location
1097 ??? Would it be a good idea to have reload do the converse, that is
1098 try to reload floating modes into FP registers if possible?
1101 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1103 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1105 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1106 && (CLASS) == NON_SPECIAL_REGS) \
1110 /* Return the register class of a scratch register needed to copy IN into
1111 or out of a register in CLASS in MODE. If it can be done directly,
1112 NO_REGS is returned. */
1114 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1115 rs6000_secondary_reload_class (CLASS, MODE, IN)
1117 /* If we are copying between FP or AltiVec registers and anything
1118 else, we need a memory location. The exception is when we are
1119 targeting ppc64 and the move to/from fpr to gpr instructions
1122 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1123 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1124 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1125 || ((MODE != DFmode) \
1126 && (MODE != DDmode) \
1127 && (MODE != DImode)))) \
1128 || ((CLASS2) == FLOAT_REGS \
1129 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
1130 || ((MODE != DFmode) \
1131 && (MODE != DDmode) \
1132 && (MODE != DImode)))) \
1133 || (CLASS1) == ALTIVEC_REGS \
1134 || (CLASS2) == ALTIVEC_REGS))
1136 /* Return the maximum number of consecutive registers
1137 needed to represent mode MODE in a register of class CLASS.
1139 On RS/6000, this is the size of MODE in words,
1140 except in the FP regs, where a single reg is enough for two words. */
1141 #define CLASS_MAX_NREGS(CLASS, MODE) \
1142 (((CLASS) == FLOAT_REGS) \
1143 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1144 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
1146 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1148 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1150 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1151 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1152 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1153 || TARGET_IEEEQUAD) \
1154 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1155 : (((TARGET_E500_DOUBLE \
1156 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
1157 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
1158 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1160 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1161 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
1163 /* Stack layout; function entry, exit and calling. */
1165 /* Enumeration to give which calling sequence to use. */
1168 ABI_AIX, /* IBM's AIX */
1169 ABI_V4, /* System V.4/eabi */
1170 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1173 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1175 /* Define this if pushing a word on the stack
1176 makes the stack pointer a smaller address. */
1177 #define STACK_GROWS_DOWNWARD
1179 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1180 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1182 /* Define this to nonzero if the nominal address of the stack frame
1183 is at the high-address end of the local variables;
1184 that is, each additional local variable allocated
1185 goes at a more negative offset in the frame.
1187 On the RS/6000, we grow upwards, from the area after the outgoing
1189 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1191 /* Size of the outgoing register save area */
1192 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1193 || DEFAULT_ABI == ABI_DARWIN) \
1194 ? (TARGET_64BIT ? 64 : 32) \
1197 /* Size of the fixed area on the stack */
1198 #define RS6000_SAVE_AREA \
1199 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1200 << (TARGET_64BIT ? 1 : 0))
1202 /* MEM representing address to save the TOC register */
1203 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1204 plus_constant (stack_pointer_rtx, \
1205 (TARGET_32BIT ? 20 : 40)))
1207 /* Align an address */
1208 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1210 /* Offset within stack frame to start allocating local variables at.
1211 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1212 first local allocated. Otherwise, it is the offset to the BEGINNING
1213 of the first local allocated.
1215 On the RS/6000, the frame pointer is the same as the stack pointer,
1216 except for dynamic allocations. So we start after the fixed area and
1217 outgoing parameter area. */
1219 #define STARTING_FRAME_OFFSET \
1220 (FRAME_GROWS_DOWNWARD \
1222 : (RS6000_ALIGN (current_function_outgoing_args_size, \
1223 TARGET_ALTIVEC ? 16 : 8) \
1224 + RS6000_SAVE_AREA))
1226 /* Offset from the stack pointer register to an item dynamically
1227 allocated on the stack, e.g., by `alloca'.
1229 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1230 length of the outgoing arguments. The default is correct for most
1231 machines. See `function.c' for details. */
1232 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1233 (RS6000_ALIGN (current_function_outgoing_args_size, \
1234 TARGET_ALTIVEC ? 16 : 8) \
1235 + (STACK_POINTER_OFFSET))
1237 /* If we generate an insn to push BYTES bytes,
1238 this says how many the stack pointer really advances by.
1239 On RS/6000, don't define this because there are no push insns. */
1240 /* #define PUSH_ROUNDING(BYTES) */
1242 /* Offset of first parameter from the argument pointer register value.
1243 On the RS/6000, we define the argument pointer to the start of the fixed
1245 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1247 /* Offset from the argument pointer register value to the top of
1248 stack. This is different from FIRST_PARM_OFFSET because of the
1249 register save area. */
1250 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1252 /* Define this if stack space is still allocated for a parameter passed
1253 in a register. The value is the number of bytes allocated to this
1255 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1257 /* Define this if the above stack space is to be considered part of the
1258 space allocated by the caller. */
1259 #define OUTGOING_REG_PARM_STACK_SPACE 1
1261 /* This is the difference between the logical top of stack and the actual sp.
1263 For the RS/6000, sp points past the fixed area. */
1264 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1266 /* Define this if the maximum size of all the outgoing args is to be
1267 accumulated and pushed during the prologue. The amount can be
1268 found in the variable current_function_outgoing_args_size. */
1269 #define ACCUMULATE_OUTGOING_ARGS 1
1271 /* Value is the number of bytes of arguments automatically
1272 popped when returning from a subroutine call.
1273 FUNDECL is the declaration node of the function (as a tree),
1274 FUNTYPE is the data type of the function (as a tree),
1275 or for a library call it is an identifier node for the subroutine name.
1276 SIZE is the number of bytes of arguments passed on the stack. */
1278 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1280 /* Define how to find the value returned by a function.
1281 VALTYPE is the data type of the value (as a tree).
1282 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1283 otherwise, FUNC is 0. */
1285 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1287 /* Define how to find the value returned by a library function
1288 assuming the value has mode MODE. */
1290 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1292 /* DRAFT_V4_STRUCT_RET defaults off. */
1293 #define DRAFT_V4_STRUCT_RET 0
1295 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1296 #define DEFAULT_PCC_STRUCT_RETURN 0
1298 /* Mode of stack savearea.
1299 FUNCTION is VOIDmode because calling convention maintains SP.
1300 BLOCK needs Pmode for SP.
1301 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1302 #define STACK_SAVEAREA_MODE(LEVEL) \
1303 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1304 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1306 /* Minimum and maximum general purpose registers used to hold arguments. */
1307 #define GP_ARG_MIN_REG 3
1308 #define GP_ARG_MAX_REG 10
1309 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1311 /* Minimum and maximum floating point registers used to hold arguments. */
1312 #define FP_ARG_MIN_REG 33
1313 #define FP_ARG_AIX_MAX_REG 45
1314 #define FP_ARG_V4_MAX_REG 40
1315 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1316 || DEFAULT_ABI == ABI_DARWIN) \
1317 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1318 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1320 /* Minimum and maximum AltiVec registers used to hold arguments. */
1321 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1322 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1323 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1325 /* Return registers */
1326 #define GP_ARG_RETURN GP_ARG_MIN_REG
1327 #define FP_ARG_RETURN FP_ARG_MIN_REG
1328 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1330 /* Flags for the call/call_value rtl operations set up by function_arg */
1331 #define CALL_NORMAL 0x00000000 /* no special processing */
1332 /* Bits in 0x00000001 are unused. */
1333 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1334 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1335 #define CALL_LONG 0x00000008 /* always call indirect */
1336 #define CALL_LIBCALL 0x00000010 /* libcall */
1338 /* We don't have prologue and epilogue functions to save/restore
1339 everything for most ABIs. */
1340 #define WORLD_SAVE_P(INFO) 0
1342 /* 1 if N is a possible register number for a function value
1343 as seen by the caller.
1345 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1346 #define FUNCTION_VALUE_REGNO_P(N) \
1347 ((N) == GP_ARG_RETURN \
1348 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1349 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1351 /* 1 if N is a possible register number for function argument passing.
1352 On RS/6000, these are r3-r10 and fp1-fp13.
1353 On AltiVec, v2 - v13 are used for passing vectors. */
1354 #define FUNCTION_ARG_REGNO_P(N) \
1355 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1356 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1357 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1358 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1359 && TARGET_HARD_FLOAT && TARGET_FPRS))
1361 /* Define a data type for recording info about an argument list
1362 during the scan of that argument list. This data type should
1363 hold all necessary information about the function itself
1364 and about the args processed so far, enough to enable macros
1365 such as FUNCTION_ARG to determine where the next arg should go.
1367 On the RS/6000, this is a structure. The first element is the number of
1368 total argument words, the second is used to store the next
1369 floating-point register number, and the third says how many more args we
1370 have prototype types for.
1372 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1373 the next available GP register, `fregno' is the next available FP
1374 register, and `words' is the number of words used on the stack.
1376 The varargs/stdarg support requires that this structure's size
1377 be a multiple of sizeof(int). */
1379 typedef struct rs6000_args
1381 int words; /* # words used for passing GP registers */
1382 int fregno; /* next available FP register */
1383 int vregno; /* next available AltiVec register */
1384 int nargs_prototype; /* # args left in the current prototype */
1385 int prototype; /* Whether a prototype was defined */
1386 int stdarg; /* Whether function is a stdarg function. */
1387 int call_cookie; /* Do special things for this call */
1388 int sysv_gregno; /* next available GP register */
1389 int intoffset; /* running offset in struct (darwin64) */
1390 int use_stack; /* any part of struct on stack (darwin64) */
1391 int named; /* false for varargs params */
1394 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1395 for a call to a function whose data type is FNTYPE.
1396 For a library call, FNTYPE is 0. */
1398 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1399 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1401 /* Similar, but when scanning the definition of a procedure. We always
1402 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1404 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1405 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1407 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1409 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1410 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1412 /* Update the data in CUM to advance over an argument
1413 of mode MODE and data type TYPE.
1414 (TYPE is null for libcalls where that information may not be available.) */
1416 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1417 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1419 /* Determine where to put an argument to a function.
1420 Value is zero to push the argument on the stack,
1421 or a hard register in which to store the argument.
1423 MODE is the argument's machine mode.
1424 TYPE is the data type of the argument (as a tree).
1425 This is null for libcalls where that information may
1427 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1428 the preceding args and about the function being called.
1429 NAMED is nonzero if this argument is a named parameter
1430 (otherwise it is an extra parameter matching an ellipsis).
1432 On RS/6000 the first eight words of non-FP are normally in registers
1433 and the rest are pushed. The first 13 FP args are in registers.
1435 If this is floating-point and no prototype is specified, we use
1436 both an FP and integer register (or possibly FP reg and stack). Library
1437 functions (when TYPE is zero) always have the proper types for args,
1438 so we can pass the FP value just in one register. emit_library_function
1439 doesn't support EXPR_LIST anyway. */
1441 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1442 function_arg (&CUM, MODE, TYPE, NAMED)
1444 /* If defined, a C expression which determines whether, and in which
1445 direction, to pad out an argument with extra space. The value
1446 should be of type `enum direction': either `upward' to pad above
1447 the argument, `downward' to pad below, or `none' to inhibit
1450 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1452 /* If defined, a C expression that gives the alignment boundary, in bits,
1453 of an argument with the specified mode and type. If it is not defined,
1454 PARM_BOUNDARY is used for all arguments. */
1456 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1457 function_arg_boundary (MODE, TYPE)
1459 /* Implement `va_start' for varargs and stdarg. */
1460 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1461 rs6000_va_start (valist, nextarg)
1463 #define PAD_VARARGS_DOWN \
1464 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1466 /* Output assembler code to FILE to increment profiler label # LABELNO
1467 for profiling a function entry. */
1469 #define FUNCTION_PROFILER(FILE, LABELNO) \
1470 output_function_profiler ((FILE), (LABELNO));
1472 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1473 the stack pointer does not matter. No definition is equivalent to
1476 On the RS/6000, this is nonzero because we can restore the stack from
1477 its backpointer, which we maintain. */
1478 #define EXIT_IGNORE_STACK 1
1480 /* Define this macro as a C expression that is nonzero for registers
1481 that are used by the epilogue or the return' pattern. The stack
1482 and frame pointer registers are already be assumed to be used as
1485 #define EPILOGUE_USES(REGNO) \
1486 ((reload_completed && (REGNO) == LR_REGNO) \
1487 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1488 || (current_function_calls_eh_return \
1493 /* TRAMPOLINE_TEMPLATE deleted */
1495 /* Length in units of the trampoline for entering a nested function. */
1497 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1499 /* Emit RTL insns to initialize the variable parts of a trampoline.
1500 FNADDR is an RTX for the address of the function's pure code.
1501 CXT is an RTX for the static chain value for the function. */
1503 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1504 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1506 /* Definitions for __builtin_return_address and __builtin_frame_address.
1507 __builtin_return_address (0) should give link register (65), enable
1509 /* This should be uncommented, so that the link register is used, but
1510 currently this would result in unmatched insns and spilling fixed
1511 registers so we'll leave it for another day. When these problems are
1512 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1514 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1516 /* Number of bytes into the frame return addresses can be found. See
1517 rs6000_stack_info in rs6000.c for more information on how the different
1518 abi's store the return address. */
1519 #define RETURN_ADDRESS_OFFSET \
1520 ((DEFAULT_ABI == ABI_AIX \
1521 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1522 (DEFAULT_ABI == ABI_V4) ? 4 : \
1523 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1525 /* The current return address is in link register (65). The return address
1526 of anything farther back is accessed normally at an offset of 8 from the
1528 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1529 (rs6000_return_addr (COUNT, FRAME))
1532 /* Definitions for register eliminations.
1534 We have two registers that can be eliminated on the RS/6000. First, the
1535 frame pointer register can often be eliminated in favor of the stack
1536 pointer register. Secondly, the argument pointer register can always be
1537 eliminated; it is replaced with either the stack or frame pointer.
1539 In addition, we use the elimination mechanism to see if r30 is needed
1540 Initially we assume that it isn't. If it is, we spill it. This is done
1541 by making it an eliminable register. We replace it with itself so that
1542 if it isn't needed, then existing uses won't be modified. */
1544 /* This is an array of structures. Each structure initializes one pair
1545 of eliminable registers. The "from" register number is given first,
1546 followed by "to". Eliminations of the same "from" register are listed
1547 in order of preference. */
1548 #define ELIMINABLE_REGS \
1549 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1550 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1551 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1552 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1553 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1554 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1556 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1557 Frame pointer elimination is automatically handled.
1559 For the RS/6000, if frame pointer elimination is being done, we would like
1560 to convert ap into fp, not sp.
1562 We need r30 if -mminimal-toc was specified, and there are constant pool
1565 #define CAN_ELIMINATE(FROM, TO) \
1566 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1567 ? ! frame_pointer_needed \
1568 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1569 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1572 /* Define the offset between two registers, one to be eliminated, and the other
1573 its replacement, at the start of a routine. */
1574 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1575 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1577 /* Addressing modes, and classification of registers for them. */
1579 #define HAVE_PRE_DECREMENT 1
1580 #define HAVE_PRE_INCREMENT 1
1581 #define HAVE_PRE_MODIFY_DISP 1
1582 #define HAVE_PRE_MODIFY_REG 1
1584 /* Macros to check register numbers against specific register classes. */
1586 /* These assume that REGNO is a hard or pseudo reg number.
1587 They give nonzero only if REGNO is a hard reg of the suitable class
1588 or a pseudo reg currently allocated to a suitable hard reg.
1589 Since they use reg_renumber, they are safe only once reg_renumber
1590 has been allocated, which happens in local-alloc.c. */
1592 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1593 ((REGNO) < FIRST_PSEUDO_REGISTER \
1594 ? (REGNO) <= 31 || (REGNO) == 67 \
1595 || (REGNO) == FRAME_POINTER_REGNUM \
1596 : (reg_renumber[REGNO] >= 0 \
1597 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1598 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1600 #define REGNO_OK_FOR_BASE_P(REGNO) \
1601 ((REGNO) < FIRST_PSEUDO_REGISTER \
1602 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1603 || (REGNO) == FRAME_POINTER_REGNUM \
1604 : (reg_renumber[REGNO] > 0 \
1605 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1606 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1608 /* Maximum number of registers that can appear in a valid memory address. */
1610 #define MAX_REGS_PER_ADDRESS 2
1612 /* Recognize any constant value that is a valid address. */
1614 #define CONSTANT_ADDRESS_P(X) \
1615 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1616 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1617 || GET_CODE (X) == HIGH)
1619 /* Nonzero if the constant value X is a legitimate general operand.
1620 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1622 On the RS/6000, all integer constants are acceptable, most won't be valid
1623 for particular insns, though. Only easy FP constants are
1626 #define LEGITIMATE_CONSTANT_P(X) \
1627 (((GET_CODE (X) != CONST_DOUBLE \
1628 && GET_CODE (X) != CONST_VECTOR) \
1629 || GET_MODE (X) == VOIDmode \
1630 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1631 || easy_fp_constant (X, GET_MODE (X)) \
1632 || easy_vector_constant (X, GET_MODE (X))) \
1633 && !rs6000_tls_referenced_p (X))
1635 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1636 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1637 && EASY_VECTOR_15((n) >> 1) \
1640 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1641 and check its validity for a certain class.
1642 We have two alternate definitions for each of them.
1643 The usual definition accepts all pseudo regs; the other rejects
1644 them unless they have been allocated suitable hard regs.
1645 The symbol REG_OK_STRICT causes the latter definition to be used.
1647 Most source files want to accept pseudo regs in the hope that
1648 they will get allocated to the class that the insn wants them to be in.
1649 Source files for reload pass need to be strict.
1650 After reload, it makes no difference, since pseudo regs have
1651 been eliminated by then. */
1653 #ifdef REG_OK_STRICT
1654 # define REG_OK_STRICT_FLAG 1
1656 # define REG_OK_STRICT_FLAG 0
1659 /* Nonzero if X is a hard reg that can be used as an index
1660 or if it is a pseudo reg in the non-strict case. */
1661 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1662 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1663 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1665 /* Nonzero if X is a hard reg that can be used as a base reg
1666 or if it is a pseudo reg in the non-strict case. */
1667 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1668 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1669 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1671 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1672 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1674 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1675 that is a valid memory address for an instruction.
1676 The MODE argument is the machine mode for the MEM expression
1677 that wants to use this address.
1679 On the RS/6000, there are four valid addresses: a SYMBOL_REF that
1680 refers to a constant pool entry of an address (or the sum of it
1681 plus a constant), a short (16-bit signed) constant plus a register,
1682 the sum of two registers, or a register indirect, possibly with an
1683 auto-increment. For DFmode and DImode with a constant plus register,
1684 we must ensure that both words are addressable or PowerPC64 with offset
1687 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1688 32-bit DImode, TImode), indexed addressing cannot be used because
1689 adjacent memory cells are accessed by adding word-sized offsets
1690 during assembly output. */
1692 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1693 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1697 /* Try machine-dependent ways of modifying an illegitimate address
1698 to be legitimate. If we find one, return the new, valid address.
1699 This macro is used in only one place: `memory_address' in explow.c.
1701 OLDX is the address as it was before break_out_memory_refs was called.
1702 In some cases it is useful to look at this to decide what needs to be done.
1704 MODE and WIN are passed so that this macro can use
1705 GO_IF_LEGITIMATE_ADDRESS.
1707 It is always safe for this macro to do nothing. It exists to recognize
1708 opportunities to optimize the output.
1710 On RS/6000, first check for the sum of a register with a constant
1711 integer that is out of range. If so, generate code to add the
1712 constant with the low-order 16 bits masked to the register and force
1713 this result into another register (this can be done with `cau').
1714 Then generate an address of REG+(CONST&0xffff), allowing for the
1715 possibility of bit 16 being a one.
1717 Then check for the sum of a register and something not constant, try to
1718 load the other things into a register and return the sum. */
1720 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1721 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1722 if (result != NULL_RTX) \
1729 /* Try a machine-dependent way of reloading an illegitimate address
1730 operand. If we find one, push the reload and jump to WIN. This
1731 macro is used in only one place: `find_reloads_address' in reload.c.
1733 Implemented on rs6000 by rs6000_legitimize_reload_address.
1734 Note that (X) is evaluated twice; this is safe in current usage. */
1736 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1739 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1740 (int)(TYPE), (IND_LEVELS), &win); \
1745 /* Go to LABEL if ADDR (a legitimate address expression)
1746 has an effect that depends on the machine mode it is used for. */
1748 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1750 if (rs6000_mode_dependent_address (ADDR)) \
1754 /* The register number of the register used to address a table of
1755 static data addresses in memory. In some cases this register is
1756 defined by a processor's "application binary interface" (ABI).
1757 When this macro is defined, RTL is generated for this register
1758 once, as with the stack pointer and frame pointer registers. If
1759 this macro is not defined, it is up to the machine-dependent files
1760 to allocate such a register (if necessary). */
1762 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1763 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1765 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1767 /* Define this macro if the register defined by
1768 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1769 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1771 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1773 /* A C expression that is nonzero if X is a legitimate immediate
1774 operand on the target machine when generating position independent
1775 code. You can assume that X satisfies `CONSTANT_P', so you need
1776 not check this. You can also assume FLAG_PIC is true, so you need
1777 not check it either. You need not define this macro if all
1778 constants (including `SYMBOL_REF') can be immediate operands when
1779 generating position independent code. */
1781 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1783 /* Define this if some processing needs to be done immediately before
1784 emitting code for an insn. */
1786 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1788 /* Specify the machine mode that this machine uses
1789 for the index in the tablejump instruction. */
1790 #define CASE_VECTOR_MODE SImode
1792 /* Define as C expression which evaluates to nonzero if the tablejump
1793 instruction expects the table to contain offsets from the address of the
1795 Do not define this if the table should contain absolute addresses. */
1796 #define CASE_VECTOR_PC_RELATIVE 1
1798 /* Define this as 1 if `char' should by default be signed; else as 0. */
1799 #define DEFAULT_SIGNED_CHAR 0
1801 /* This flag, if defined, says the same insns that convert to a signed fixnum
1802 also convert validly to an unsigned one. */
1804 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1806 /* An integer expression for the size in bits of the largest integer machine
1807 mode that should actually be used. */
1809 /* Allow pairs of registers to be used, which is the intent of the default. */
1810 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1812 /* Max number of bytes we can move from memory to memory
1813 in one reasonably fast instruction. */
1814 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1815 #define MAX_MOVE_MAX 8
1817 /* Nonzero if access to memory by bytes is no faster than for words.
1818 Also nonzero if doing byte operations (specifically shifts) in registers
1820 #define SLOW_BYTE_ACCESS 1
1822 /* Define if operations between registers always perform the operation
1823 on the full register even if a narrower mode is specified. */
1824 #define WORD_REGISTER_OPERATIONS
1826 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1827 will either zero-extend or sign-extend. The value of this macro should
1828 be the code that says which one of the two operations is implicitly
1829 done, UNKNOWN if none. */
1830 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1832 /* Define if loading short immediate values into registers sign extends. */
1833 #define SHORT_IMMEDIATES_SIGN_EXTEND
1835 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1836 is done just by pretending it is already truncated. */
1837 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1839 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1840 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1841 ((VALUE) = ((MODE) == SImode ? 32 : 64))
1843 /* The CTZ patterns return -1 for input of zero. */
1844 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
1846 /* Specify the machine mode that pointers have.
1847 After generation of rtl, the compiler makes no further distinction
1848 between pointers and any other objects of this machine mode. */
1849 #define Pmode (TARGET_32BIT ? SImode : DImode)
1851 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1852 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1854 /* Mode of a function address in a call instruction (for indexing purposes).
1855 Doesn't matter on RS/6000. */
1856 #define FUNCTION_MODE SImode
1858 /* Define this if addresses of constant functions
1859 shouldn't be put through pseudo regs where they can be cse'd.
1860 Desirable on machines where ordinary constants are expensive
1861 but a CALL with constant address is cheap. */
1862 #define NO_FUNCTION_CSE
1864 /* Define this to be nonzero if shift instructions ignore all but the low-order
1867 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1868 have been dropped from the PowerPC architecture. */
1870 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1872 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1873 should be adjusted to reflect any required changes. This macro is used when
1874 there is some systematic length adjustment required that would be difficult
1875 to express in the length attribute. */
1877 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1879 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1880 COMPARE, return the mode to be used for the comparison. For
1881 floating-point, CCFPmode should be used. CCUNSmode should be used
1882 for unsigned comparisons. CCEQmode should be used when we are
1883 doing an inequality comparison on the result of a
1884 comparison. CCmode should be used in all other cases. */
1886 #define SELECT_CC_MODE(OP,X,Y) \
1887 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1888 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1889 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1890 ? CCEQmode : CCmode))
1892 /* Can the condition code MODE be safely reversed? This is safe in
1893 all cases on this port, because at present it doesn't use the
1894 trapping FP comparisons (fcmpo). */
1895 #define REVERSIBLE_CC_MODE(MODE) 1
1897 /* Given a condition code and a mode, return the inverse condition. */
1898 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1900 /* Define the information needed to generate branch and scc insns. This is
1901 stored from the compare operation. */
1903 extern GTY(()) rtx rs6000_compare_op0;
1904 extern GTY(()) rtx rs6000_compare_op1;
1905 extern int rs6000_compare_fp_p;
1907 /* Control the assembler format that we output. */
1909 /* A C string constant describing how to begin a comment in the target
1910 assembler language. The compiler assumes that the comment will end at
1911 the end of the line. */
1912 #define ASM_COMMENT_START " #"
1914 /* Flag to say the TOC is initialized */
1915 extern int toc_initialized;
1917 /* Macro to output a special constant pool entry. Go to WIN if we output
1918 it. Otherwise, it is written the usual way.
1920 On the RS/6000, toc entries are handled this way. */
1922 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1923 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1925 output_toc (FILE, X, LABELNO, MODE); \
1930 #ifdef HAVE_GAS_WEAK
1931 #define RS6000_WEAK 1
1933 #define RS6000_WEAK 0
1937 /* Used in lieu of ASM_WEAKEN_LABEL. */
1938 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1941 fputs ("\t.weak\t", (FILE)); \
1942 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1943 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1944 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1947 fputs ("[DS]", (FILE)); \
1948 fputs ("\n\t.weak\t.", (FILE)); \
1949 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1951 fputc ('\n', (FILE)); \
1954 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1955 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1956 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1958 fputs ("\t.set\t.", (FILE)); \
1959 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1960 fputs (",.", (FILE)); \
1961 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
1962 fputc ('\n', (FILE)); \
1969 #if HAVE_GAS_WEAKREF
1970 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1973 fputs ("\t.weakref\t", (FILE)); \
1974 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1975 fputs (", ", (FILE)); \
1976 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1977 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1978 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1980 fputs ("\n\t.weakref\t.", (FILE)); \
1981 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1982 fputs (", .", (FILE)); \
1983 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1985 fputc ('\n', (FILE)); \
1989 /* This implements the `alias' attribute. */
1990 #undef ASM_OUTPUT_DEF_FROM_DECLS
1991 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1994 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1995 const char *name = IDENTIFIER_POINTER (TARGET); \
1996 if (TREE_CODE (DECL) == FUNCTION_DECL \
1997 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1999 if (TREE_PUBLIC (DECL)) \
2001 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2003 fputs ("\t.globl\t.", FILE); \
2004 RS6000_OUTPUT_BASENAME (FILE, alias); \
2005 putc ('\n', FILE); \
2008 else if (TARGET_XCOFF) \
2010 fputs ("\t.lglobl\t.", FILE); \
2011 RS6000_OUTPUT_BASENAME (FILE, alias); \
2012 putc ('\n', FILE); \
2014 fputs ("\t.set\t.", FILE); \
2015 RS6000_OUTPUT_BASENAME (FILE, alias); \
2016 fputs (",.", FILE); \
2017 RS6000_OUTPUT_BASENAME (FILE, name); \
2018 fputc ('\n', FILE); \
2020 ASM_OUTPUT_DEF (FILE, alias, name); \
2024 #define TARGET_ASM_FILE_START rs6000_file_start
2026 /* Output to assembler file text saying following lines
2027 may contain character constants, extra white space, comments, etc. */
2029 #define ASM_APP_ON ""
2031 /* Output to assembler file text saying following lines
2032 no longer contain unusual constructs. */
2034 #define ASM_APP_OFF ""
2036 /* How to refer to registers in assembler output.
2037 This sequence is indexed by compiler's hard-register-number (see above). */
2039 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2041 #define REGISTER_NAMES \
2043 &rs6000_reg_names[ 0][0], /* r0 */ \
2044 &rs6000_reg_names[ 1][0], /* r1 */ \
2045 &rs6000_reg_names[ 2][0], /* r2 */ \
2046 &rs6000_reg_names[ 3][0], /* r3 */ \
2047 &rs6000_reg_names[ 4][0], /* r4 */ \
2048 &rs6000_reg_names[ 5][0], /* r5 */ \
2049 &rs6000_reg_names[ 6][0], /* r6 */ \
2050 &rs6000_reg_names[ 7][0], /* r7 */ \
2051 &rs6000_reg_names[ 8][0], /* r8 */ \
2052 &rs6000_reg_names[ 9][0], /* r9 */ \
2053 &rs6000_reg_names[10][0], /* r10 */ \
2054 &rs6000_reg_names[11][0], /* r11 */ \
2055 &rs6000_reg_names[12][0], /* r12 */ \
2056 &rs6000_reg_names[13][0], /* r13 */ \
2057 &rs6000_reg_names[14][0], /* r14 */ \
2058 &rs6000_reg_names[15][0], /* r15 */ \
2059 &rs6000_reg_names[16][0], /* r16 */ \
2060 &rs6000_reg_names[17][0], /* r17 */ \
2061 &rs6000_reg_names[18][0], /* r18 */ \
2062 &rs6000_reg_names[19][0], /* r19 */ \
2063 &rs6000_reg_names[20][0], /* r20 */ \
2064 &rs6000_reg_names[21][0], /* r21 */ \
2065 &rs6000_reg_names[22][0], /* r22 */ \
2066 &rs6000_reg_names[23][0], /* r23 */ \
2067 &rs6000_reg_names[24][0], /* r24 */ \
2068 &rs6000_reg_names[25][0], /* r25 */ \
2069 &rs6000_reg_names[26][0], /* r26 */ \
2070 &rs6000_reg_names[27][0], /* r27 */ \
2071 &rs6000_reg_names[28][0], /* r28 */ \
2072 &rs6000_reg_names[29][0], /* r29 */ \
2073 &rs6000_reg_names[30][0], /* r30 */ \
2074 &rs6000_reg_names[31][0], /* r31 */ \
2076 &rs6000_reg_names[32][0], /* fr0 */ \
2077 &rs6000_reg_names[33][0], /* fr1 */ \
2078 &rs6000_reg_names[34][0], /* fr2 */ \
2079 &rs6000_reg_names[35][0], /* fr3 */ \
2080 &rs6000_reg_names[36][0], /* fr4 */ \
2081 &rs6000_reg_names[37][0], /* fr5 */ \
2082 &rs6000_reg_names[38][0], /* fr6 */ \
2083 &rs6000_reg_names[39][0], /* fr7 */ \
2084 &rs6000_reg_names[40][0], /* fr8 */ \
2085 &rs6000_reg_names[41][0], /* fr9 */ \
2086 &rs6000_reg_names[42][0], /* fr10 */ \
2087 &rs6000_reg_names[43][0], /* fr11 */ \
2088 &rs6000_reg_names[44][0], /* fr12 */ \
2089 &rs6000_reg_names[45][0], /* fr13 */ \
2090 &rs6000_reg_names[46][0], /* fr14 */ \
2091 &rs6000_reg_names[47][0], /* fr15 */ \
2092 &rs6000_reg_names[48][0], /* fr16 */ \
2093 &rs6000_reg_names[49][0], /* fr17 */ \
2094 &rs6000_reg_names[50][0], /* fr18 */ \
2095 &rs6000_reg_names[51][0], /* fr19 */ \
2096 &rs6000_reg_names[52][0], /* fr20 */ \
2097 &rs6000_reg_names[53][0], /* fr21 */ \
2098 &rs6000_reg_names[54][0], /* fr22 */ \
2099 &rs6000_reg_names[55][0], /* fr23 */ \
2100 &rs6000_reg_names[56][0], /* fr24 */ \
2101 &rs6000_reg_names[57][0], /* fr25 */ \
2102 &rs6000_reg_names[58][0], /* fr26 */ \
2103 &rs6000_reg_names[59][0], /* fr27 */ \
2104 &rs6000_reg_names[60][0], /* fr28 */ \
2105 &rs6000_reg_names[61][0], /* fr29 */ \
2106 &rs6000_reg_names[62][0], /* fr30 */ \
2107 &rs6000_reg_names[63][0], /* fr31 */ \
2109 &rs6000_reg_names[64][0], /* mq */ \
2110 &rs6000_reg_names[65][0], /* lr */ \
2111 &rs6000_reg_names[66][0], /* ctr */ \
2112 &rs6000_reg_names[67][0], /* ap */ \
2114 &rs6000_reg_names[68][0], /* cr0 */ \
2115 &rs6000_reg_names[69][0], /* cr1 */ \
2116 &rs6000_reg_names[70][0], /* cr2 */ \
2117 &rs6000_reg_names[71][0], /* cr3 */ \
2118 &rs6000_reg_names[72][0], /* cr4 */ \
2119 &rs6000_reg_names[73][0], /* cr5 */ \
2120 &rs6000_reg_names[74][0], /* cr6 */ \
2121 &rs6000_reg_names[75][0], /* cr7 */ \
2123 &rs6000_reg_names[76][0], /* xer */ \
2125 &rs6000_reg_names[77][0], /* v0 */ \
2126 &rs6000_reg_names[78][0], /* v1 */ \
2127 &rs6000_reg_names[79][0], /* v2 */ \
2128 &rs6000_reg_names[80][0], /* v3 */ \
2129 &rs6000_reg_names[81][0], /* v4 */ \
2130 &rs6000_reg_names[82][0], /* v5 */ \
2131 &rs6000_reg_names[83][0], /* v6 */ \
2132 &rs6000_reg_names[84][0], /* v7 */ \
2133 &rs6000_reg_names[85][0], /* v8 */ \
2134 &rs6000_reg_names[86][0], /* v9 */ \
2135 &rs6000_reg_names[87][0], /* v10 */ \
2136 &rs6000_reg_names[88][0], /* v11 */ \
2137 &rs6000_reg_names[89][0], /* v12 */ \
2138 &rs6000_reg_names[90][0], /* v13 */ \
2139 &rs6000_reg_names[91][0], /* v14 */ \
2140 &rs6000_reg_names[92][0], /* v15 */ \
2141 &rs6000_reg_names[93][0], /* v16 */ \
2142 &rs6000_reg_names[94][0], /* v17 */ \
2143 &rs6000_reg_names[95][0], /* v18 */ \
2144 &rs6000_reg_names[96][0], /* v19 */ \
2145 &rs6000_reg_names[97][0], /* v20 */ \
2146 &rs6000_reg_names[98][0], /* v21 */ \
2147 &rs6000_reg_names[99][0], /* v22 */ \
2148 &rs6000_reg_names[100][0], /* v23 */ \
2149 &rs6000_reg_names[101][0], /* v24 */ \
2150 &rs6000_reg_names[102][0], /* v25 */ \
2151 &rs6000_reg_names[103][0], /* v26 */ \
2152 &rs6000_reg_names[104][0], /* v27 */ \
2153 &rs6000_reg_names[105][0], /* v28 */ \
2154 &rs6000_reg_names[106][0], /* v29 */ \
2155 &rs6000_reg_names[107][0], /* v30 */ \
2156 &rs6000_reg_names[108][0], /* v31 */ \
2157 &rs6000_reg_names[109][0], /* vrsave */ \
2158 &rs6000_reg_names[110][0], /* vscr */ \
2159 &rs6000_reg_names[111][0], /* spe_acc */ \
2160 &rs6000_reg_names[112][0], /* spefscr */ \
2161 &rs6000_reg_names[113][0], /* sfp */ \
2164 /* Table of additional register names to use in user input. */
2166 #define ADDITIONAL_REGISTER_NAMES \
2167 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2168 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2169 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2170 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2171 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2172 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2173 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2174 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2175 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2176 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2177 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2178 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2179 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2180 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2181 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2182 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2183 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2184 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2185 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2186 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2187 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2188 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2189 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2190 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2191 {"vrsave", 109}, {"vscr", 110}, \
2192 {"spe_acc", 111}, {"spefscr", 112}, \
2193 /* no additional names for: mq, lr, ctr, ap */ \
2194 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2195 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2196 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2198 /* Text to write out after a CALL that may be replaced by glue code by
2199 the loader. This depends on the AIX version. */
2200 #define RS6000_CALL_GLUE "cror 31,31,31"
2202 /* This is how to output an element of a case-vector that is relative. */
2204 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2205 do { char buf[100]; \
2206 fputs ("\t.long ", FILE); \
2207 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2208 assemble_name (FILE, buf); \
2210 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2211 assemble_name (FILE, buf); \
2212 putc ('\n', FILE); \
2215 /* This is how to output an assembler line
2216 that says to advance the location counter
2217 to a multiple of 2**LOG bytes. */
2219 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2221 fprintf (FILE, "\t.align %d\n", (LOG))
2223 /* Pick up the return address upon entry to a procedure. Used for
2224 dwarf2 unwind information. This also enables the table driven
2227 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2228 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2230 /* Describe how we implement __builtin_eh_return. */
2231 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2232 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2234 /* Print operand X (an rtx) in assembler syntax to file FILE.
2235 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2236 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2238 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2240 /* Define which CODE values are valid. */
2242 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2243 ((CODE) == '.' || (CODE) == '&')
2245 /* Print a memory address as an operand to reference that memory location. */
2247 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2249 /* uncomment for disabling the corresponding default options */
2250 /* #define MACHINE_no_sched_interblock */
2251 /* #define MACHINE_no_sched_speculative */
2252 /* #define MACHINE_no_sched_speculative_load */
2254 /* General flags. */
2255 extern int flag_pic;
2256 extern int optimize;
2257 extern int flag_expensive_optimizations;
2258 extern int frame_pointer_needed;
2260 enum rs6000_builtins
2262 /* AltiVec builtins. */
2263 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2264 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2265 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2266 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2267 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2268 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2269 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2270 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2271 ALTIVEC_BUILTIN_VADDUBM,
2272 ALTIVEC_BUILTIN_VADDUHM,
2273 ALTIVEC_BUILTIN_VADDUWM,
2274 ALTIVEC_BUILTIN_VADDFP,
2275 ALTIVEC_BUILTIN_VADDCUW,
2276 ALTIVEC_BUILTIN_VADDUBS,
2277 ALTIVEC_BUILTIN_VADDSBS,
2278 ALTIVEC_BUILTIN_VADDUHS,
2279 ALTIVEC_BUILTIN_VADDSHS,
2280 ALTIVEC_BUILTIN_VADDUWS,
2281 ALTIVEC_BUILTIN_VADDSWS,
2282 ALTIVEC_BUILTIN_VAND,
2283 ALTIVEC_BUILTIN_VANDC,
2284 ALTIVEC_BUILTIN_VAVGUB,
2285 ALTIVEC_BUILTIN_VAVGSB,
2286 ALTIVEC_BUILTIN_VAVGUH,
2287 ALTIVEC_BUILTIN_VAVGSH,
2288 ALTIVEC_BUILTIN_VAVGUW,
2289 ALTIVEC_BUILTIN_VAVGSW,
2290 ALTIVEC_BUILTIN_VCFUX,
2291 ALTIVEC_BUILTIN_VCFSX,
2292 ALTIVEC_BUILTIN_VCTSXS,
2293 ALTIVEC_BUILTIN_VCTUXS,
2294 ALTIVEC_BUILTIN_VCMPBFP,
2295 ALTIVEC_BUILTIN_VCMPEQUB,
2296 ALTIVEC_BUILTIN_VCMPEQUH,
2297 ALTIVEC_BUILTIN_VCMPEQUW,
2298 ALTIVEC_BUILTIN_VCMPEQFP,
2299 ALTIVEC_BUILTIN_VCMPGEFP,
2300 ALTIVEC_BUILTIN_VCMPGTUB,
2301 ALTIVEC_BUILTIN_VCMPGTSB,
2302 ALTIVEC_BUILTIN_VCMPGTUH,
2303 ALTIVEC_BUILTIN_VCMPGTSH,
2304 ALTIVEC_BUILTIN_VCMPGTUW,
2305 ALTIVEC_BUILTIN_VCMPGTSW,
2306 ALTIVEC_BUILTIN_VCMPGTFP,
2307 ALTIVEC_BUILTIN_VEXPTEFP,
2308 ALTIVEC_BUILTIN_VLOGEFP,
2309 ALTIVEC_BUILTIN_VMADDFP,
2310 ALTIVEC_BUILTIN_VMAXUB,
2311 ALTIVEC_BUILTIN_VMAXSB,
2312 ALTIVEC_BUILTIN_VMAXUH,
2313 ALTIVEC_BUILTIN_VMAXSH,
2314 ALTIVEC_BUILTIN_VMAXUW,
2315 ALTIVEC_BUILTIN_VMAXSW,
2316 ALTIVEC_BUILTIN_VMAXFP,
2317 ALTIVEC_BUILTIN_VMHADDSHS,
2318 ALTIVEC_BUILTIN_VMHRADDSHS,
2319 ALTIVEC_BUILTIN_VMLADDUHM,
2320 ALTIVEC_BUILTIN_VMRGHB,
2321 ALTIVEC_BUILTIN_VMRGHH,
2322 ALTIVEC_BUILTIN_VMRGHW,
2323 ALTIVEC_BUILTIN_VMRGLB,
2324 ALTIVEC_BUILTIN_VMRGLH,
2325 ALTIVEC_BUILTIN_VMRGLW,
2326 ALTIVEC_BUILTIN_VMSUMUBM,
2327 ALTIVEC_BUILTIN_VMSUMMBM,
2328 ALTIVEC_BUILTIN_VMSUMUHM,
2329 ALTIVEC_BUILTIN_VMSUMSHM,
2330 ALTIVEC_BUILTIN_VMSUMUHS,
2331 ALTIVEC_BUILTIN_VMSUMSHS,
2332 ALTIVEC_BUILTIN_VMINUB,
2333 ALTIVEC_BUILTIN_VMINSB,
2334 ALTIVEC_BUILTIN_VMINUH,
2335 ALTIVEC_BUILTIN_VMINSH,
2336 ALTIVEC_BUILTIN_VMINUW,
2337 ALTIVEC_BUILTIN_VMINSW,
2338 ALTIVEC_BUILTIN_VMINFP,
2339 ALTIVEC_BUILTIN_VMULEUB,
2340 ALTIVEC_BUILTIN_VMULESB,
2341 ALTIVEC_BUILTIN_VMULEUH,
2342 ALTIVEC_BUILTIN_VMULESH,
2343 ALTIVEC_BUILTIN_VMULOUB,
2344 ALTIVEC_BUILTIN_VMULOSB,
2345 ALTIVEC_BUILTIN_VMULOUH,
2346 ALTIVEC_BUILTIN_VMULOSH,
2347 ALTIVEC_BUILTIN_VNMSUBFP,
2348 ALTIVEC_BUILTIN_VNOR,
2349 ALTIVEC_BUILTIN_VOR,
2350 ALTIVEC_BUILTIN_VSEL_4SI,
2351 ALTIVEC_BUILTIN_VSEL_4SF,
2352 ALTIVEC_BUILTIN_VSEL_8HI,
2353 ALTIVEC_BUILTIN_VSEL_16QI,
2354 ALTIVEC_BUILTIN_VPERM_4SI,
2355 ALTIVEC_BUILTIN_VPERM_4SF,
2356 ALTIVEC_BUILTIN_VPERM_8HI,
2357 ALTIVEC_BUILTIN_VPERM_16QI,
2358 ALTIVEC_BUILTIN_VPKUHUM,
2359 ALTIVEC_BUILTIN_VPKUWUM,
2360 ALTIVEC_BUILTIN_VPKPX,
2361 ALTIVEC_BUILTIN_VPKUHSS,
2362 ALTIVEC_BUILTIN_VPKSHSS,
2363 ALTIVEC_BUILTIN_VPKUWSS,
2364 ALTIVEC_BUILTIN_VPKSWSS,
2365 ALTIVEC_BUILTIN_VPKUHUS,
2366 ALTIVEC_BUILTIN_VPKSHUS,
2367 ALTIVEC_BUILTIN_VPKUWUS,
2368 ALTIVEC_BUILTIN_VPKSWUS,
2369 ALTIVEC_BUILTIN_VREFP,
2370 ALTIVEC_BUILTIN_VRFIM,
2371 ALTIVEC_BUILTIN_VRFIN,
2372 ALTIVEC_BUILTIN_VRFIP,
2373 ALTIVEC_BUILTIN_VRFIZ,
2374 ALTIVEC_BUILTIN_VRLB,
2375 ALTIVEC_BUILTIN_VRLH,
2376 ALTIVEC_BUILTIN_VRLW,
2377 ALTIVEC_BUILTIN_VRSQRTEFP,
2378 ALTIVEC_BUILTIN_VSLB,
2379 ALTIVEC_BUILTIN_VSLH,
2380 ALTIVEC_BUILTIN_VSLW,
2381 ALTIVEC_BUILTIN_VSL,
2382 ALTIVEC_BUILTIN_VSLO,
2383 ALTIVEC_BUILTIN_VSPLTB,
2384 ALTIVEC_BUILTIN_VSPLTH,
2385 ALTIVEC_BUILTIN_VSPLTW,
2386 ALTIVEC_BUILTIN_VSPLTISB,
2387 ALTIVEC_BUILTIN_VSPLTISH,
2388 ALTIVEC_BUILTIN_VSPLTISW,
2389 ALTIVEC_BUILTIN_VSRB,
2390 ALTIVEC_BUILTIN_VSRH,
2391 ALTIVEC_BUILTIN_VSRW,
2392 ALTIVEC_BUILTIN_VSRAB,
2393 ALTIVEC_BUILTIN_VSRAH,
2394 ALTIVEC_BUILTIN_VSRAW,
2395 ALTIVEC_BUILTIN_VSR,
2396 ALTIVEC_BUILTIN_VSRO,
2397 ALTIVEC_BUILTIN_VSUBUBM,
2398 ALTIVEC_BUILTIN_VSUBUHM,
2399 ALTIVEC_BUILTIN_VSUBUWM,
2400 ALTIVEC_BUILTIN_VSUBFP,
2401 ALTIVEC_BUILTIN_VSUBCUW,
2402 ALTIVEC_BUILTIN_VSUBUBS,
2403 ALTIVEC_BUILTIN_VSUBSBS,
2404 ALTIVEC_BUILTIN_VSUBUHS,
2405 ALTIVEC_BUILTIN_VSUBSHS,
2406 ALTIVEC_BUILTIN_VSUBUWS,
2407 ALTIVEC_BUILTIN_VSUBSWS,
2408 ALTIVEC_BUILTIN_VSUM4UBS,
2409 ALTIVEC_BUILTIN_VSUM4SBS,
2410 ALTIVEC_BUILTIN_VSUM4SHS,
2411 ALTIVEC_BUILTIN_VSUM2SWS,
2412 ALTIVEC_BUILTIN_VSUMSWS,
2413 ALTIVEC_BUILTIN_VXOR,
2414 ALTIVEC_BUILTIN_VSLDOI_16QI,
2415 ALTIVEC_BUILTIN_VSLDOI_8HI,
2416 ALTIVEC_BUILTIN_VSLDOI_4SI,
2417 ALTIVEC_BUILTIN_VSLDOI_4SF,
2418 ALTIVEC_BUILTIN_VUPKHSB,
2419 ALTIVEC_BUILTIN_VUPKHPX,
2420 ALTIVEC_BUILTIN_VUPKHSH,
2421 ALTIVEC_BUILTIN_VUPKLSB,
2422 ALTIVEC_BUILTIN_VUPKLPX,
2423 ALTIVEC_BUILTIN_VUPKLSH,
2424 ALTIVEC_BUILTIN_MTVSCR,
2425 ALTIVEC_BUILTIN_MFVSCR,
2426 ALTIVEC_BUILTIN_DSSALL,
2427 ALTIVEC_BUILTIN_DSS,
2428 ALTIVEC_BUILTIN_LVSL,
2429 ALTIVEC_BUILTIN_LVSR,
2430 ALTIVEC_BUILTIN_DSTT,
2431 ALTIVEC_BUILTIN_DSTST,
2432 ALTIVEC_BUILTIN_DSTSTT,
2433 ALTIVEC_BUILTIN_DST,
2434 ALTIVEC_BUILTIN_LVEBX,
2435 ALTIVEC_BUILTIN_LVEHX,
2436 ALTIVEC_BUILTIN_LVEWX,
2437 ALTIVEC_BUILTIN_LVXL,
2438 ALTIVEC_BUILTIN_LVX,
2439 ALTIVEC_BUILTIN_STVX,
2440 ALTIVEC_BUILTIN_STVEBX,
2441 ALTIVEC_BUILTIN_STVEHX,
2442 ALTIVEC_BUILTIN_STVEWX,
2443 ALTIVEC_BUILTIN_STVXL,
2444 ALTIVEC_BUILTIN_VCMPBFP_P,
2445 ALTIVEC_BUILTIN_VCMPEQFP_P,
2446 ALTIVEC_BUILTIN_VCMPEQUB_P,
2447 ALTIVEC_BUILTIN_VCMPEQUH_P,
2448 ALTIVEC_BUILTIN_VCMPEQUW_P,
2449 ALTIVEC_BUILTIN_VCMPGEFP_P,
2450 ALTIVEC_BUILTIN_VCMPGTFP_P,
2451 ALTIVEC_BUILTIN_VCMPGTSB_P,
2452 ALTIVEC_BUILTIN_VCMPGTSH_P,
2453 ALTIVEC_BUILTIN_VCMPGTSW_P,
2454 ALTIVEC_BUILTIN_VCMPGTUB_P,
2455 ALTIVEC_BUILTIN_VCMPGTUH_P,
2456 ALTIVEC_BUILTIN_VCMPGTUW_P,
2457 ALTIVEC_BUILTIN_ABSS_V4SI,
2458 ALTIVEC_BUILTIN_ABSS_V8HI,
2459 ALTIVEC_BUILTIN_ABSS_V16QI,
2460 ALTIVEC_BUILTIN_ABS_V4SI,
2461 ALTIVEC_BUILTIN_ABS_V4SF,
2462 ALTIVEC_BUILTIN_ABS_V8HI,
2463 ALTIVEC_BUILTIN_ABS_V16QI,
2464 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2465 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2466 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2467 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2468 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2469 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2470 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2471 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2472 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2473 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2474 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2475 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2476 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2477 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2479 /* Altivec overloaded builtins. */
2480 ALTIVEC_BUILTIN_VCMPEQ_P,
2481 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2482 ALTIVEC_BUILTIN_VCMPGT_P,
2483 ALTIVEC_BUILTIN_VCMPGE_P,
2484 ALTIVEC_BUILTIN_VEC_ABS,
2485 ALTIVEC_BUILTIN_VEC_ABSS,
2486 ALTIVEC_BUILTIN_VEC_ADD,
2487 ALTIVEC_BUILTIN_VEC_ADDC,
2488 ALTIVEC_BUILTIN_VEC_ADDS,
2489 ALTIVEC_BUILTIN_VEC_AND,
2490 ALTIVEC_BUILTIN_VEC_ANDC,
2491 ALTIVEC_BUILTIN_VEC_AVG,
2492 ALTIVEC_BUILTIN_VEC_CEIL,
2493 ALTIVEC_BUILTIN_VEC_CMPB,
2494 ALTIVEC_BUILTIN_VEC_CMPEQ,
2495 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2496 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2497 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2498 ALTIVEC_BUILTIN_VEC_CMPGE,
2499 ALTIVEC_BUILTIN_VEC_CMPGT,
2500 ALTIVEC_BUILTIN_VEC_CMPLE,
2501 ALTIVEC_BUILTIN_VEC_CMPLT,
2502 ALTIVEC_BUILTIN_VEC_CTF,
2503 ALTIVEC_BUILTIN_VEC_CTS,
2504 ALTIVEC_BUILTIN_VEC_CTU,
2505 ALTIVEC_BUILTIN_VEC_DST,
2506 ALTIVEC_BUILTIN_VEC_DSTST,
2507 ALTIVEC_BUILTIN_VEC_DSTSTT,
2508 ALTIVEC_BUILTIN_VEC_DSTT,
2509 ALTIVEC_BUILTIN_VEC_EXPTE,
2510 ALTIVEC_BUILTIN_VEC_FLOOR,
2511 ALTIVEC_BUILTIN_VEC_LD,
2512 ALTIVEC_BUILTIN_VEC_LDE,
2513 ALTIVEC_BUILTIN_VEC_LDL,
2514 ALTIVEC_BUILTIN_VEC_LOGE,
2515 ALTIVEC_BUILTIN_VEC_LVEBX,
2516 ALTIVEC_BUILTIN_VEC_LVEHX,
2517 ALTIVEC_BUILTIN_VEC_LVEWX,
2518 ALTIVEC_BUILTIN_VEC_LVSL,
2519 ALTIVEC_BUILTIN_VEC_LVSR,
2520 ALTIVEC_BUILTIN_VEC_MADD,
2521 ALTIVEC_BUILTIN_VEC_MADDS,
2522 ALTIVEC_BUILTIN_VEC_MAX,
2523 ALTIVEC_BUILTIN_VEC_MERGEH,
2524 ALTIVEC_BUILTIN_VEC_MERGEL,
2525 ALTIVEC_BUILTIN_VEC_MIN,
2526 ALTIVEC_BUILTIN_VEC_MLADD,
2527 ALTIVEC_BUILTIN_VEC_MPERM,
2528 ALTIVEC_BUILTIN_VEC_MRADDS,
2529 ALTIVEC_BUILTIN_VEC_MRGHB,
2530 ALTIVEC_BUILTIN_VEC_MRGHH,
2531 ALTIVEC_BUILTIN_VEC_MRGHW,
2532 ALTIVEC_BUILTIN_VEC_MRGLB,
2533 ALTIVEC_BUILTIN_VEC_MRGLH,
2534 ALTIVEC_BUILTIN_VEC_MRGLW,
2535 ALTIVEC_BUILTIN_VEC_MSUM,
2536 ALTIVEC_BUILTIN_VEC_MSUMS,
2537 ALTIVEC_BUILTIN_VEC_MTVSCR,
2538 ALTIVEC_BUILTIN_VEC_MULE,
2539 ALTIVEC_BUILTIN_VEC_MULO,
2540 ALTIVEC_BUILTIN_VEC_NMSUB,
2541 ALTIVEC_BUILTIN_VEC_NOR,
2542 ALTIVEC_BUILTIN_VEC_OR,
2543 ALTIVEC_BUILTIN_VEC_PACK,
2544 ALTIVEC_BUILTIN_VEC_PACKPX,
2545 ALTIVEC_BUILTIN_VEC_PACKS,
2546 ALTIVEC_BUILTIN_VEC_PACKSU,
2547 ALTIVEC_BUILTIN_VEC_PERM,
2548 ALTIVEC_BUILTIN_VEC_RE,
2549 ALTIVEC_BUILTIN_VEC_RL,
2550 ALTIVEC_BUILTIN_VEC_ROUND,
2551 ALTIVEC_BUILTIN_VEC_RSQRTE,
2552 ALTIVEC_BUILTIN_VEC_SEL,
2553 ALTIVEC_BUILTIN_VEC_SL,
2554 ALTIVEC_BUILTIN_VEC_SLD,
2555 ALTIVEC_BUILTIN_VEC_SLL,
2556 ALTIVEC_BUILTIN_VEC_SLO,
2557 ALTIVEC_BUILTIN_VEC_SPLAT,
2558 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2559 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2560 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2561 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2562 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2563 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2564 ALTIVEC_BUILTIN_VEC_SPLTB,
2565 ALTIVEC_BUILTIN_VEC_SPLTH,
2566 ALTIVEC_BUILTIN_VEC_SPLTW,
2567 ALTIVEC_BUILTIN_VEC_SR,
2568 ALTIVEC_BUILTIN_VEC_SRA,
2569 ALTIVEC_BUILTIN_VEC_SRL,
2570 ALTIVEC_BUILTIN_VEC_SRO,
2571 ALTIVEC_BUILTIN_VEC_ST,
2572 ALTIVEC_BUILTIN_VEC_STE,
2573 ALTIVEC_BUILTIN_VEC_STL,
2574 ALTIVEC_BUILTIN_VEC_STVEBX,
2575 ALTIVEC_BUILTIN_VEC_STVEHX,
2576 ALTIVEC_BUILTIN_VEC_STVEWX,
2577 ALTIVEC_BUILTIN_VEC_SUB,
2578 ALTIVEC_BUILTIN_VEC_SUBC,
2579 ALTIVEC_BUILTIN_VEC_SUBS,
2580 ALTIVEC_BUILTIN_VEC_SUM2S,
2581 ALTIVEC_BUILTIN_VEC_SUM4S,
2582 ALTIVEC_BUILTIN_VEC_SUMS,
2583 ALTIVEC_BUILTIN_VEC_TRUNC,
2584 ALTIVEC_BUILTIN_VEC_UNPACKH,
2585 ALTIVEC_BUILTIN_VEC_UNPACKL,
2586 ALTIVEC_BUILTIN_VEC_VADDFP,
2587 ALTIVEC_BUILTIN_VEC_VADDSBS,
2588 ALTIVEC_BUILTIN_VEC_VADDSHS,
2589 ALTIVEC_BUILTIN_VEC_VADDSWS,
2590 ALTIVEC_BUILTIN_VEC_VADDUBM,
2591 ALTIVEC_BUILTIN_VEC_VADDUBS,
2592 ALTIVEC_BUILTIN_VEC_VADDUHM,
2593 ALTIVEC_BUILTIN_VEC_VADDUHS,
2594 ALTIVEC_BUILTIN_VEC_VADDUWM,
2595 ALTIVEC_BUILTIN_VEC_VADDUWS,
2596 ALTIVEC_BUILTIN_VEC_VAVGSB,
2597 ALTIVEC_BUILTIN_VEC_VAVGSH,
2598 ALTIVEC_BUILTIN_VEC_VAVGSW,
2599 ALTIVEC_BUILTIN_VEC_VAVGUB,
2600 ALTIVEC_BUILTIN_VEC_VAVGUH,
2601 ALTIVEC_BUILTIN_VEC_VAVGUW,
2602 ALTIVEC_BUILTIN_VEC_VCFSX,
2603 ALTIVEC_BUILTIN_VEC_VCFUX,
2604 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2605 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2606 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2607 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2608 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2609 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2610 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2611 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2612 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2613 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2614 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2615 ALTIVEC_BUILTIN_VEC_VMAXFP,
2616 ALTIVEC_BUILTIN_VEC_VMAXSB,
2617 ALTIVEC_BUILTIN_VEC_VMAXSH,
2618 ALTIVEC_BUILTIN_VEC_VMAXSW,
2619 ALTIVEC_BUILTIN_VEC_VMAXUB,
2620 ALTIVEC_BUILTIN_VEC_VMAXUH,
2621 ALTIVEC_BUILTIN_VEC_VMAXUW,
2622 ALTIVEC_BUILTIN_VEC_VMINFP,
2623 ALTIVEC_BUILTIN_VEC_VMINSB,
2624 ALTIVEC_BUILTIN_VEC_VMINSH,
2625 ALTIVEC_BUILTIN_VEC_VMINSW,
2626 ALTIVEC_BUILTIN_VEC_VMINUB,
2627 ALTIVEC_BUILTIN_VEC_VMINUH,
2628 ALTIVEC_BUILTIN_VEC_VMINUW,
2629 ALTIVEC_BUILTIN_VEC_VMRGHB,
2630 ALTIVEC_BUILTIN_VEC_VMRGHH,
2631 ALTIVEC_BUILTIN_VEC_VMRGHW,
2632 ALTIVEC_BUILTIN_VEC_VMRGLB,
2633 ALTIVEC_BUILTIN_VEC_VMRGLH,
2634 ALTIVEC_BUILTIN_VEC_VMRGLW,
2635 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2636 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2637 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2638 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2639 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2640 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2641 ALTIVEC_BUILTIN_VEC_VMULESB,
2642 ALTIVEC_BUILTIN_VEC_VMULESH,
2643 ALTIVEC_BUILTIN_VEC_VMULEUB,
2644 ALTIVEC_BUILTIN_VEC_VMULEUH,
2645 ALTIVEC_BUILTIN_VEC_VMULOSB,
2646 ALTIVEC_BUILTIN_VEC_VMULOSH,
2647 ALTIVEC_BUILTIN_VEC_VMULOUB,
2648 ALTIVEC_BUILTIN_VEC_VMULOUH,
2649 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2650 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2651 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2652 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2653 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2654 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2655 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2656 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2657 ALTIVEC_BUILTIN_VEC_VRLB,
2658 ALTIVEC_BUILTIN_VEC_VRLH,
2659 ALTIVEC_BUILTIN_VEC_VRLW,
2660 ALTIVEC_BUILTIN_VEC_VSLB,
2661 ALTIVEC_BUILTIN_VEC_VSLH,
2662 ALTIVEC_BUILTIN_VEC_VSLW,
2663 ALTIVEC_BUILTIN_VEC_VSPLTB,
2664 ALTIVEC_BUILTIN_VEC_VSPLTH,
2665 ALTIVEC_BUILTIN_VEC_VSPLTW,
2666 ALTIVEC_BUILTIN_VEC_VSRAB,
2667 ALTIVEC_BUILTIN_VEC_VSRAH,
2668 ALTIVEC_BUILTIN_VEC_VSRAW,
2669 ALTIVEC_BUILTIN_VEC_VSRB,
2670 ALTIVEC_BUILTIN_VEC_VSRH,
2671 ALTIVEC_BUILTIN_VEC_VSRW,
2672 ALTIVEC_BUILTIN_VEC_VSUBFP,
2673 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2674 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2675 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2676 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2677 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2678 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2679 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2680 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2681 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2682 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2683 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2684 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2685 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2686 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2687 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2688 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2689 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2690 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2691 ALTIVEC_BUILTIN_VEC_XOR,
2692 ALTIVEC_BUILTIN_VEC_STEP,
2693 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP,
2699 SPE_BUILTIN_EVDIVWS,
2700 SPE_BUILTIN_EVDIVWU,
2702 SPE_BUILTIN_EVFSADD,
2703 SPE_BUILTIN_EVFSDIV,
2704 SPE_BUILTIN_EVFSMUL,
2705 SPE_BUILTIN_EVFSSUB,
2709 SPE_BUILTIN_EVLHHESPLATX,
2710 SPE_BUILTIN_EVLHHOSSPLATX,
2711 SPE_BUILTIN_EVLHHOUSPLATX,
2712 SPE_BUILTIN_EVLWHEX,
2713 SPE_BUILTIN_EVLWHOSX,
2714 SPE_BUILTIN_EVLWHOUX,
2715 SPE_BUILTIN_EVLWHSPLATX,
2716 SPE_BUILTIN_EVLWWSPLATX,
2717 SPE_BUILTIN_EVMERGEHI,
2718 SPE_BUILTIN_EVMERGEHILO,
2719 SPE_BUILTIN_EVMERGELO,
2720 SPE_BUILTIN_EVMERGELOHI,
2721 SPE_BUILTIN_EVMHEGSMFAA,
2722 SPE_BUILTIN_EVMHEGSMFAN,
2723 SPE_BUILTIN_EVMHEGSMIAA,
2724 SPE_BUILTIN_EVMHEGSMIAN,
2725 SPE_BUILTIN_EVMHEGUMIAA,
2726 SPE_BUILTIN_EVMHEGUMIAN,
2727 SPE_BUILTIN_EVMHESMF,
2728 SPE_BUILTIN_EVMHESMFA,
2729 SPE_BUILTIN_EVMHESMFAAW,
2730 SPE_BUILTIN_EVMHESMFANW,
2731 SPE_BUILTIN_EVMHESMI,
2732 SPE_BUILTIN_EVMHESMIA,
2733 SPE_BUILTIN_EVMHESMIAAW,
2734 SPE_BUILTIN_EVMHESMIANW,
2735 SPE_BUILTIN_EVMHESSF,
2736 SPE_BUILTIN_EVMHESSFA,
2737 SPE_BUILTIN_EVMHESSFAAW,
2738 SPE_BUILTIN_EVMHESSFANW,
2739 SPE_BUILTIN_EVMHESSIAAW,
2740 SPE_BUILTIN_EVMHESSIANW,
2741 SPE_BUILTIN_EVMHEUMI,
2742 SPE_BUILTIN_EVMHEUMIA,
2743 SPE_BUILTIN_EVMHEUMIAAW,
2744 SPE_BUILTIN_EVMHEUMIANW,
2745 SPE_BUILTIN_EVMHEUSIAAW,
2746 SPE_BUILTIN_EVMHEUSIANW,
2747 SPE_BUILTIN_EVMHOGSMFAA,
2748 SPE_BUILTIN_EVMHOGSMFAN,
2749 SPE_BUILTIN_EVMHOGSMIAA,
2750 SPE_BUILTIN_EVMHOGSMIAN,
2751 SPE_BUILTIN_EVMHOGUMIAA,
2752 SPE_BUILTIN_EVMHOGUMIAN,
2753 SPE_BUILTIN_EVMHOSMF,
2754 SPE_BUILTIN_EVMHOSMFA,
2755 SPE_BUILTIN_EVMHOSMFAAW,
2756 SPE_BUILTIN_EVMHOSMFANW,
2757 SPE_BUILTIN_EVMHOSMI,
2758 SPE_BUILTIN_EVMHOSMIA,
2759 SPE_BUILTIN_EVMHOSMIAAW,
2760 SPE_BUILTIN_EVMHOSMIANW,
2761 SPE_BUILTIN_EVMHOSSF,
2762 SPE_BUILTIN_EVMHOSSFA,
2763 SPE_BUILTIN_EVMHOSSFAAW,
2764 SPE_BUILTIN_EVMHOSSFANW,
2765 SPE_BUILTIN_EVMHOSSIAAW,
2766 SPE_BUILTIN_EVMHOSSIANW,
2767 SPE_BUILTIN_EVMHOUMI,
2768 SPE_BUILTIN_EVMHOUMIA,
2769 SPE_BUILTIN_EVMHOUMIAAW,
2770 SPE_BUILTIN_EVMHOUMIANW,
2771 SPE_BUILTIN_EVMHOUSIAAW,
2772 SPE_BUILTIN_EVMHOUSIANW,
2773 SPE_BUILTIN_EVMWHSMF,
2774 SPE_BUILTIN_EVMWHSMFA,
2775 SPE_BUILTIN_EVMWHSMI,
2776 SPE_BUILTIN_EVMWHSMIA,
2777 SPE_BUILTIN_EVMWHSSF,
2778 SPE_BUILTIN_EVMWHSSFA,
2779 SPE_BUILTIN_EVMWHUMI,
2780 SPE_BUILTIN_EVMWHUMIA,
2781 SPE_BUILTIN_EVMWLSMIAAW,
2782 SPE_BUILTIN_EVMWLSMIANW,
2783 SPE_BUILTIN_EVMWLSSIAAW,
2784 SPE_BUILTIN_EVMWLSSIANW,
2785 SPE_BUILTIN_EVMWLUMI,
2786 SPE_BUILTIN_EVMWLUMIA,
2787 SPE_BUILTIN_EVMWLUMIAAW,
2788 SPE_BUILTIN_EVMWLUMIANW,
2789 SPE_BUILTIN_EVMWLUSIAAW,
2790 SPE_BUILTIN_EVMWLUSIANW,
2791 SPE_BUILTIN_EVMWSMF,
2792 SPE_BUILTIN_EVMWSMFA,
2793 SPE_BUILTIN_EVMWSMFAA,
2794 SPE_BUILTIN_EVMWSMFAN,
2795 SPE_BUILTIN_EVMWSMI,
2796 SPE_BUILTIN_EVMWSMIA,
2797 SPE_BUILTIN_EVMWSMIAA,
2798 SPE_BUILTIN_EVMWSMIAN,
2799 SPE_BUILTIN_EVMWHSSFAA,
2800 SPE_BUILTIN_EVMWSSF,
2801 SPE_BUILTIN_EVMWSSFA,
2802 SPE_BUILTIN_EVMWSSFAA,
2803 SPE_BUILTIN_EVMWSSFAN,
2804 SPE_BUILTIN_EVMWUMI,
2805 SPE_BUILTIN_EVMWUMIA,
2806 SPE_BUILTIN_EVMWUMIAA,
2807 SPE_BUILTIN_EVMWUMIAN,
2816 SPE_BUILTIN_EVSTDDX,
2817 SPE_BUILTIN_EVSTDHX,
2818 SPE_BUILTIN_EVSTDWX,
2819 SPE_BUILTIN_EVSTWHEX,
2820 SPE_BUILTIN_EVSTWHOX,
2821 SPE_BUILTIN_EVSTWWEX,
2822 SPE_BUILTIN_EVSTWWOX,
2823 SPE_BUILTIN_EVSUBFW,
2826 SPE_BUILTIN_EVADDSMIAAW,
2827 SPE_BUILTIN_EVADDSSIAAW,
2828 SPE_BUILTIN_EVADDUMIAAW,
2829 SPE_BUILTIN_EVADDUSIAAW,
2830 SPE_BUILTIN_EVCNTLSW,
2831 SPE_BUILTIN_EVCNTLZW,
2832 SPE_BUILTIN_EVEXTSB,
2833 SPE_BUILTIN_EVEXTSH,
2834 SPE_BUILTIN_EVFSABS,
2835 SPE_BUILTIN_EVFSCFSF,
2836 SPE_BUILTIN_EVFSCFSI,
2837 SPE_BUILTIN_EVFSCFUF,
2838 SPE_BUILTIN_EVFSCFUI,
2839 SPE_BUILTIN_EVFSCTSF,
2840 SPE_BUILTIN_EVFSCTSI,
2841 SPE_BUILTIN_EVFSCTSIZ,
2842 SPE_BUILTIN_EVFSCTUF,
2843 SPE_BUILTIN_EVFSCTUI,
2844 SPE_BUILTIN_EVFSCTUIZ,
2845 SPE_BUILTIN_EVFSNABS,
2846 SPE_BUILTIN_EVFSNEG,
2850 SPE_BUILTIN_EVSUBFSMIAAW,
2851 SPE_BUILTIN_EVSUBFSSIAAW,
2852 SPE_BUILTIN_EVSUBFUMIAAW,
2853 SPE_BUILTIN_EVSUBFUSIAAW,
2854 SPE_BUILTIN_EVADDIW,
2858 SPE_BUILTIN_EVLHHESPLAT,
2859 SPE_BUILTIN_EVLHHOSSPLAT,
2860 SPE_BUILTIN_EVLHHOUSPLAT,
2862 SPE_BUILTIN_EVLWHOS,
2863 SPE_BUILTIN_EVLWHOU,
2864 SPE_BUILTIN_EVLWHSPLAT,
2865 SPE_BUILTIN_EVLWWSPLAT,
2868 SPE_BUILTIN_EVSRWIS,
2869 SPE_BUILTIN_EVSRWIU,
2873 SPE_BUILTIN_EVSTWHE,
2874 SPE_BUILTIN_EVSTWHO,
2875 SPE_BUILTIN_EVSTWWE,
2876 SPE_BUILTIN_EVSTWWO,
2877 SPE_BUILTIN_EVSUBIFW,
2880 SPE_BUILTIN_EVCMPEQ,
2881 SPE_BUILTIN_EVCMPGTS,
2882 SPE_BUILTIN_EVCMPGTU,
2883 SPE_BUILTIN_EVCMPLTS,
2884 SPE_BUILTIN_EVCMPLTU,
2885 SPE_BUILTIN_EVFSCMPEQ,
2886 SPE_BUILTIN_EVFSCMPGT,
2887 SPE_BUILTIN_EVFSCMPLT,
2888 SPE_BUILTIN_EVFSTSTEQ,
2889 SPE_BUILTIN_EVFSTSTGT,
2890 SPE_BUILTIN_EVFSTSTLT,
2892 /* EVSEL compares. */
2893 SPE_BUILTIN_EVSEL_CMPEQ,
2894 SPE_BUILTIN_EVSEL_CMPGTS,
2895 SPE_BUILTIN_EVSEL_CMPGTU,
2896 SPE_BUILTIN_EVSEL_CMPLTS,
2897 SPE_BUILTIN_EVSEL_CMPLTU,
2898 SPE_BUILTIN_EVSEL_FSCMPEQ,
2899 SPE_BUILTIN_EVSEL_FSCMPGT,
2900 SPE_BUILTIN_EVSEL_FSCMPLT,
2901 SPE_BUILTIN_EVSEL_FSTSTEQ,
2902 SPE_BUILTIN_EVSEL_FSTSTGT,
2903 SPE_BUILTIN_EVSEL_FSTSTLT,
2905 SPE_BUILTIN_EVSPLATFI,
2906 SPE_BUILTIN_EVSPLATI,
2907 SPE_BUILTIN_EVMWHSSMAA,
2908 SPE_BUILTIN_EVMWHSMFAA,
2909 SPE_BUILTIN_EVMWHSMIAA,
2910 SPE_BUILTIN_EVMWHUSIAA,
2911 SPE_BUILTIN_EVMWHUMIAA,
2912 SPE_BUILTIN_EVMWHSSFAN,
2913 SPE_BUILTIN_EVMWHSSIAN,
2914 SPE_BUILTIN_EVMWHSMFAN,
2915 SPE_BUILTIN_EVMWHSMIAN,
2916 SPE_BUILTIN_EVMWHUSIAN,
2917 SPE_BUILTIN_EVMWHUMIAN,
2918 SPE_BUILTIN_EVMWHGSSFAA,
2919 SPE_BUILTIN_EVMWHGSMFAA,
2920 SPE_BUILTIN_EVMWHGSMIAA,
2921 SPE_BUILTIN_EVMWHGUMIAA,
2922 SPE_BUILTIN_EVMWHGSSFAN,
2923 SPE_BUILTIN_EVMWHGSMFAN,
2924 SPE_BUILTIN_EVMWHGSMIAN,
2925 SPE_BUILTIN_EVMWHGUMIAN,
2926 SPE_BUILTIN_MTSPEFSCR,
2927 SPE_BUILTIN_MFSPEFSCR,
2930 RS6000_BUILTIN_COUNT
2933 enum rs6000_builtin_type_index
2935 RS6000_BTI_NOT_OPAQUE,
2936 RS6000_BTI_opaque_V2SI,
2937 RS6000_BTI_opaque_V2SF,
2938 RS6000_BTI_opaque_p_V2SI,
2939 RS6000_BTI_opaque_V4SI,
2947 RS6000_BTI_unsigned_V16QI,
2948 RS6000_BTI_unsigned_V8HI,
2949 RS6000_BTI_unsigned_V4SI,
2950 RS6000_BTI_bool_char, /* __bool char */
2951 RS6000_BTI_bool_short, /* __bool short */
2952 RS6000_BTI_bool_int, /* __bool int */
2953 RS6000_BTI_pixel, /* __pixel */
2954 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2955 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2956 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2957 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2958 RS6000_BTI_long, /* long_integer_type_node */
2959 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2960 RS6000_BTI_INTQI, /* intQI_type_node */
2961 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2962 RS6000_BTI_INTHI, /* intHI_type_node */
2963 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2964 RS6000_BTI_INTSI, /* intSI_type_node */
2965 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2966 RS6000_BTI_float, /* float_type_node */
2967 RS6000_BTI_void, /* void_type_node */
2972 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2973 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2974 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2975 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2976 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2977 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2978 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2979 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2980 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2981 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2982 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2983 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2984 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2985 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2986 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2987 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2988 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2989 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2990 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2991 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2992 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2993 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2995 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2996 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2997 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2998 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2999 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3000 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3001 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3002 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3003 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3004 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3006 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3007 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];