1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_AIX (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
40 /* Print subsidiary information on the compiler version in use. */
41 #define TARGET_VERSION ;
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common CPP definitions used by CPP_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define CPP_CPU_SPEC \
52 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
53 %{mpower2: -D_ARCH_PWR2} \
54 %{mpowerpc*: -D_ARCH_PPC} \
55 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
56 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
57 %{mcpu=common: -D_ARCH_COM} \
58 %{mcpu=power: -D_ARCH_PWR} \
59 %{mcpu=power2: -D_ARCH_PWR2} \
60 %{mcpu=powerpc: -D_ARCH_PPC} \
61 %{mcpu=rios: -D_ARCH_PWR} \
62 %{mcpu=rios1: -D_ARCH_PWR} \
63 %{mcpu=rios2: -D_ARCH_PWR2} \
64 %{mcpu=rsc: -D_ARCH_PWR} \
65 %{mcpu=rsc1: -D_ARCH_PWR} \
66 %{mcpu=401: -D_ARCH_PPC} \
67 %{mcpu=403: -D_ARCH_PPC} \
68 %{mcpu=505: -D_ARCH_PPC} \
69 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
70 %{mcpu=602: -D_ARCH_PPC} \
71 %{mcpu=603: -D_ARCH_PPC} \
72 %{mcpu=603e: -D_ARCH_PPC} \
73 %{mcpu=ec603e: -D_ARCH_PPC} \
74 %{mcpu=604: -D_ARCH_PPC} \
75 %{mcpu=604e: -D_ARCH_PPC} \
76 %{mcpu=620: -D_ARCH_PPC} \
77 %{mcpu=740: -D_ARCH_PPC} \
78 %{mcpu=750: -D_ARCH_PPC} \
79 %{mcpu=801: -D_ARCH_PPC} \
80 %{mcpu=821: -D_ARCH_PPC} \
81 %{mcpu=823: -D_ARCH_PPC} \
82 %{mcpu=860: -D_ARCH_PPC}"
84 #define CPP_DEFAULT_SPEC "-D_ARCH_PWR"
86 /* Common ASM definitions used by ASM_SPEC among the various targets
87 for handling -mcpu=xxx switches. */
88 #define ASM_CPU_SPEC \
90 %{mpower: %{!mpower2: -mpwr}} \
93 %{mno-power: %{!mpowerpc*: -mcom}} \
94 %{!mno-power: %{!mpower2: %(asm_default)}}} \
95 %{mcpu=common: -mcom} \
96 %{mcpu=power: -mpwr} \
97 %{mcpu=power2: -mpwrx} \
98 %{mcpu=powerpc: -mppc} \
100 %{mcpu=rios1: -mpwr} \
101 %{mcpu=rios2: -mpwrx} \
103 %{mcpu=rsc1: -mpwr} \
110 %{mcpu=603e: -mppc} \
111 %{mcpu=ec603e: -mppc} \
113 %{mcpu=604e: -mppc} \
122 #define ASM_DEFAULT_SPEC ""
124 /* This macro defines names of additional specifications to put in the specs
125 that can be used in various specifications like CC1_SPEC. Its definition
126 is an initializer with a subgrouping for each command option.
128 Each subgrouping contains a string constant, that defines the
129 specification name, and a string constant that used by the GNU CC driver
132 Do not define this macro if it does not need to do anything. */
134 #define SUBTARGET_EXTRA_SPECS
136 #define EXTRA_SPECS \
137 { "cpp_cpu", CPP_CPU_SPEC }, \
138 { "cpp_default", CPP_DEFAULT_SPEC }, \
139 { "asm_cpu", ASM_CPU_SPEC }, \
140 { "asm_default", ASM_DEFAULT_SPEC }, \
141 SUBTARGET_EXTRA_SPECS
143 /* Architecture type. */
145 extern int target_flags;
147 /* Use POWER architecture instructions and MQ register. */
148 #define MASK_POWER 0x00000001
150 /* Use POWER2 extensions to POWER architecture. */
151 #define MASK_POWER2 0x00000002
153 /* Use PowerPC architecture instructions. */
154 #define MASK_POWERPC 0x00000004
156 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
157 #define MASK_PPC_GPOPT 0x00000008
159 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
160 #define MASK_PPC_GFXOPT 0x00000010
162 /* Use PowerPC-64 architecture instructions. */
163 #define MASK_POWERPC64 0x00000020
165 /* Use revised mnemonic names defined for PowerPC architecture. */
166 #define MASK_NEW_MNEMONICS 0x00000040
168 /* Disable placing fp constants in the TOC; can be turned on when the
170 #define MASK_NO_FP_IN_TOC 0x00000080
172 /* Disable placing symbol+offset constants in the TOC; can be turned on when
173 the TOC overflows. */
174 #define MASK_NO_SUM_IN_TOC 0x00000100
176 /* Output only one TOC entry per module. Normally linking fails if
177 there are more than 16K unique variables/constants in an executable. With
178 this option, linking fails only if there are more than 16K modules, or
179 if there are more than 16K unique variables/constant in a single module.
181 This is at the cost of having 2 extra loads and one extra store per
182 function, and one less allocable register. */
183 #define MASK_MINIMAL_TOC 0x00000200
185 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
186 #define MASK_64BIT 0x00000400
188 /* Disable use of FPRs. */
189 #define MASK_SOFT_FLOAT 0x00000800
191 /* Enable load/store multiple, even on powerpc */
192 #define MASK_MULTIPLE 0x00001000
193 #define MASK_MULTIPLE_SET 0x00002000
195 /* Use string instructions for block moves */
196 #define MASK_STRING 0x00004000
197 #define MASK_STRING_SET 0x00008000
199 /* Disable update form of load/store */
200 #define MASK_NO_UPDATE 0x00010000
202 /* Disable fused multiply/add operations */
203 #define MASK_NO_FUSED_MADD 0x00020000
205 /* Nonzero if we need to schedule the prolog and epilog. */
206 #define MASK_SCHED_PROLOG 0x00040000
208 #define TARGET_POWER (target_flags & MASK_POWER)
209 #define TARGET_POWER2 (target_flags & MASK_POWER2)
210 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
211 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
212 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
213 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
214 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
215 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
216 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
217 #define TARGET_64BIT (target_flags & MASK_64BIT)
218 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
219 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
220 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
221 #define TARGET_STRING (target_flags & MASK_STRING)
222 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
223 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
224 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
225 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
227 #define TARGET_32BIT (! TARGET_64BIT)
228 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
229 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
230 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
233 /* For libgcc2 we make sure this is a compile time constant */
235 #define TARGET_POWERPC64 1
237 #define TARGET_POWERPC64 0
240 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
243 #define TARGET_XL_CALL 0
245 /* Run-time compilation parameters selecting different hardware subsets.
247 Macro to define tables used to set the flags.
248 This is a list in braces of pairs in braces,
249 each pair being { "NAME", VALUE }
250 where VALUE is the bits to set or minus the bits to clear.
251 An empty string NAME is used to identify the default VALUE. */
253 #define TARGET_SWITCHES \
254 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
255 N_("Use POWER instruction set")}, \
256 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
258 N_("Use POWER2 instruction set")}, \
259 {"no-power2", - MASK_POWER2, \
260 N_("Do not use POWER2 instruction set")}, \
261 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
263 N_("Do not use POWER instruction set")}, \
264 {"powerpc", MASK_POWERPC, \
265 N_("Use PowerPC instruction set")}, \
266 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
267 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
268 N_("Do not use PowerPC instruction set")}, \
269 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
270 N_("Use PowerPC General Purpose group optional instructions")},\
271 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
272 N_("Don't use PowerPC General Purpose group optional instructions")},\
273 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
274 N_("Use PowerPC Graphics group optional instructions")},\
275 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
276 N_("Don't use PowerPC Graphics group optional instructions")},\
277 {"powerpc64", MASK_POWERPC64, \
278 N_("Use PowerPC-64 instruction set")}, \
279 {"no-powerpc64", - MASK_POWERPC64, \
280 N_("Don't use PowerPC-64 instruction set")}, \
281 {"new-mnemonics", MASK_NEW_MNEMONICS, \
282 N_("Use new mnemonics for PowerPC architecture")},\
283 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
284 N_("Use old mnemonics for PowerPC architecture")},\
285 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
286 | MASK_MINIMAL_TOC), \
287 N_("Put everything in the regular TOC")}, \
288 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
289 N_("Place floating point constants in TOC")}, \
290 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
291 N_("Don't place floating point constants in TOC")},\
292 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
293 N_("Place symbol+offset constants in TOC")}, \
294 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
295 N_("Don't place symbol+offset constants in TOC")},\
296 {"minimal-toc", MASK_MINIMAL_TOC, \
297 "Use only one TOC entry per procedure"}, \
298 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
300 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
301 N_("Place variable addresses in the regular TOC")},\
302 {"hard-float", - MASK_SOFT_FLOAT, \
303 N_("Use hardware fp")}, \
304 {"soft-float", MASK_SOFT_FLOAT, \
305 N_("Do not use hardware fp")}, \
306 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
307 N_("Generate load/store multiple instructions")}, \
308 {"no-multiple", - MASK_MULTIPLE, \
309 N_("Do not generate load/store multiple instructions")},\
310 {"no-multiple", MASK_MULTIPLE_SET, \
312 {"string", MASK_STRING | MASK_STRING_SET, \
313 N_("Generate string instructions for block moves")},\
314 {"no-string", - MASK_STRING, \
315 N_("Do not generate string instructions for block moves")},\
316 {"no-string", MASK_STRING_SET, \
318 {"update", - MASK_NO_UPDATE, \
319 N_("Generate load/store with update instructions")},\
320 {"no-update", MASK_NO_UPDATE, \
321 N_("Do not generate load/store with update instructions")},\
322 {"fused-madd", - MASK_NO_FUSED_MADD, \
323 N_("Generate fused multiply/add instructions")},\
324 {"no-fused-madd", MASK_NO_FUSED_MADD, \
325 N_("Don't generate fused multiply/add instructions")},\
326 {"sched-prolog", MASK_SCHED_PROLOG, \
328 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
329 N_("Don't schedule the start and end of the procedure")},\
330 {"sched-epilog", MASK_SCHED_PROLOG, \
332 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
335 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
338 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
340 /* This is meant to be redefined in the host dependent files */
341 #define SUBTARGET_SWITCHES
343 /* Processor type. Order must match cpu attribute in MD file. */
360 extern enum processor_type rs6000_cpu;
362 /* Recast the processor type to the cpu attribute. */
363 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
365 /* Define generic processor types based upon current deployment. */
366 #define PROCESSOR_COMMON PROCESSOR_PPC601
367 #define PROCESSOR_POWER PROCESSOR_RIOS1
368 #define PROCESSOR_POWERPC PROCESSOR_PPC604
369 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
371 /* Define the default processor. This is overridden by other tm.h files. */
372 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
373 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
375 /* Specify the dialect of assembler to use. New mnemonics is dialect one
376 and the old mnemonics are dialect zero. */
377 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
379 /* This macro is similar to `TARGET_SWITCHES' but defines names of
380 command options that have values. Its definition is an
381 initializer with a subgrouping for each command option.
383 Each subgrouping contains a string constant, that defines the
384 fixed part of the option name, and the address of a variable.
385 The variable, type `char *', is set to the variable part of the
386 given option if the fixed part matches. The actual option name
387 is made by appending `-m' to the specified name.
389 Here is an example which defines `-mshort-data-NUMBER'. If the
390 given option is `-mshort-data-512', the variable `m88k_short_data'
391 will be set to the string `"512"'.
393 extern char *m88k_short_data;
394 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
396 /* This is meant to be overridden in target specific files. */
397 #define SUBTARGET_OPTIONS
399 #define TARGET_OPTIONS \
401 {"cpu=", &rs6000_select[1].string, \
402 N_("Use features of and schedule code for given CPU") }, \
403 {"tune=", &rs6000_select[2].string, \
404 N_("Schedule code for given CPU") }, \
405 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
409 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
410 struct rs6000_cpu_select
418 extern struct rs6000_cpu_select rs6000_select[];
421 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
422 extern int rs6000_debug_stack; /* debug stack applications */
423 extern int rs6000_debug_arg; /* debug argument handling */
425 #define TARGET_DEBUG_STACK rs6000_debug_stack
426 #define TARGET_DEBUG_ARG rs6000_debug_arg
428 /* Sometimes certain combinations of command options do not make sense
429 on a particular target machine. You can define a macro
430 `OVERRIDE_OPTIONS' to take account of this. This macro, if
431 defined, is executed once just after all the command options have
434 Don't use this macro to turn on various extra optimizations for
435 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
437 On the RS/6000 this is used to define the target cpu type. */
439 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
441 /* Define this to change the optimizations performed by default. */
442 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
444 /* Show we can debug even without a frame pointer. */
445 #define CAN_DEBUG_WITHOUT_FP
447 /* target machine storage layout */
449 /* Define to support cross compilation to an RS6000 target. */
450 #define REAL_ARITHMETIC
452 /* Define this macro if it is advisable to hold scalars in registers
453 in a wider mode than that declared by the program. In such cases,
454 the value is constrained to be within the bounds of the declared
455 type, but kept valid in the wider mode. The signedness of the
456 extension may differ from that of the type. */
458 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
459 if (GET_MODE_CLASS (MODE) == MODE_INT \
460 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
463 /* Define this if function arguments should also be promoted using the above
466 #define PROMOTE_FUNCTION_ARGS
468 /* Likewise, if the function return value is promoted. */
470 #define PROMOTE_FUNCTION_RETURN
472 /* Define this if most significant bit is lowest numbered
473 in instructions that operate on numbered bit-fields. */
474 /* That is true on RS/6000. */
475 #define BITS_BIG_ENDIAN 1
477 /* Define this if most significant byte of a word is the lowest numbered. */
478 /* That is true on RS/6000. */
479 #define BYTES_BIG_ENDIAN 1
481 /* Define this if most significant word of a multiword number is lowest
484 For RS/6000 we can decide arbitrarily since there are no machine
485 instructions for them. Might as well be consistent with bits and bytes. */
486 #define WORDS_BIG_ENDIAN 1
488 /* number of bits in an addressable storage unit */
489 #define BITS_PER_UNIT 8
491 /* Width in bits of a "word", which is the contents of a machine register.
492 Note that this is not necessarily the width of data type `int';
493 if using 16-bit ints on a 68000, this would still be 32.
494 But on a machine with 16-bit registers, this would be 16. */
495 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
496 #define MAX_BITS_PER_WORD 64
498 /* Width of a word, in units (bytes). */
499 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
500 #define MIN_UNITS_PER_WORD 4
501 #define UNITS_PER_FP_WORD 8
503 /* Type used for ptrdiff_t, as a string used in a declaration. */
504 #define PTRDIFF_TYPE "int"
506 /* Type used for size_t, as a string used in a declaration. */
507 #define SIZE_TYPE "long unsigned int"
509 /* Type used for wchar_t, as a string used in a declaration. */
510 #define WCHAR_TYPE "short unsigned int"
512 /* Width of wchar_t in bits. */
513 #define WCHAR_TYPE_SIZE 16
515 /* A C expression for the size in bits of the type `short' on the
516 target machine. If you don't define this, the default is half a
517 word. (If this would be less than one storage unit, it is
518 rounded up to one unit.) */
519 #define SHORT_TYPE_SIZE 16
521 /* A C expression for the size in bits of the type `int' on the
522 target machine. If you don't define this, the default is one
524 #define INT_TYPE_SIZE 32
526 /* A C expression for the size in bits of the type `long' on the
527 target machine. If you don't define this, the default is one
529 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
530 #define MAX_LONG_TYPE_SIZE 64
532 /* A C expression for the size in bits of the type `long long' on the
533 target machine. If you don't define this, the default is two
535 #define LONG_LONG_TYPE_SIZE 64
537 /* A C expression for the size in bits of the type `char' on the
538 target machine. If you don't define this, the default is one
539 quarter of a word. (If this would be less than one storage unit,
540 it is rounded up to one unit.) */
541 #define CHAR_TYPE_SIZE BITS_PER_UNIT
543 /* A C expression for the size in bits of the type `float' on the
544 target machine. If you don't define this, the default is one
546 #define FLOAT_TYPE_SIZE 32
548 /* A C expression for the size in bits of the type `double' on the
549 target machine. If you don't define this, the default is two
551 #define DOUBLE_TYPE_SIZE 64
553 /* A C expression for the size in bits of the type `long double' on
554 the target machine. If you don't define this, the default is two
556 #define LONG_DOUBLE_TYPE_SIZE 64
558 /* Width in bits of a pointer.
559 See also the macro `Pmode' defined below. */
560 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
562 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
563 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
565 /* Boundary (in *bits*) on which stack pointer should be aligned. */
566 #define STACK_BOUNDARY (TARGET_32BIT ? 64 : 128)
568 /* Allocation boundary (in *bits*) for the code of a function. */
569 #define FUNCTION_BOUNDARY 32
571 /* No data type wants to be aligned rounder than this. */
572 #define BIGGEST_ALIGNMENT 64
574 /* Handle #pragma pack. */
575 #define HANDLE_PRAGMA_PACK 1
577 /* AIX word-aligns FP doubles but doubleword-aligns 64-bit ints. */
578 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
579 (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \
580 ? get_inner_array_type (FIELD) \
581 : TREE_TYPE (FIELD)) == DFmode \
582 ? MIN ((COMPUTED), 32) : (COMPUTED))
584 /* Alignment of field after `int : 0' in a structure. */
585 #define EMPTY_FIELD_BOUNDARY 32
587 /* Every structure's size must be a multiple of this. */
588 #define STRUCTURE_SIZE_BOUNDARY 8
590 /* A bitfield declared as `int' forces `int' alignment for the struct. */
591 #define PCC_BITFIELD_TYPE_MATTERS 1
593 /* AIX increases natural record alignment to doubleword if the first
594 field is an FP double while the FP fields remain word aligned. */
595 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
596 ((TREE_CODE (STRUCT) == RECORD_TYPE \
597 || TREE_CODE (STRUCT) == UNION_TYPE \
598 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
599 && TYPE_FIELDS (STRUCT) != 0 \
600 && DECL_MODE (TYPE_FIELDS (STRUCT)) == DFmode \
601 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
602 : MAX ((COMPUTED), (SPECIFIED)))
604 /* Make strings word-aligned so strcpy from constants will be faster. */
605 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
606 (TREE_CODE (EXP) == STRING_CST \
607 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
609 /* Make arrays of chars word-aligned for the same reasons. */
610 #define DATA_ALIGNMENT(TYPE, ALIGN) \
611 (TREE_CODE (TYPE) == ARRAY_TYPE \
612 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
613 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
615 /* Non-zero if move instructions will actually fail to work
616 when given unaligned data. */
617 #define STRICT_ALIGNMENT 0
619 /* Define this macro to be the value 1 if unaligned accesses have a cost
620 many times greater than aligned accesses, for example if they are
621 emulated in a trap handler. */
622 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
624 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
625 && (ALIGN) < 32)) ? 1 : 0)
627 /* Standard register usage. */
629 /* Number of actual hardware registers.
630 The hardware registers are assigned numbers for the compiler
631 from 0 to just below FIRST_PSEUDO_REGISTER.
632 All registers that the compiler knows about must be given numbers,
633 even those that are not normally considered general registers.
635 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
636 an MQ register, a count register, a link register, and 8 condition
637 register fields, which we view here as separate registers.
639 In addition, the difference between the frame and argument pointers is
640 a function of the number of registers saved, so we need to have a
641 register for AP that will later be eliminated in favor of SP or FP.
642 This is a normal register, but it is fixed.
644 We also create a pseudo register for float/int conversions, that will
645 really represent the memory location used. It is represented here as
646 a register, in order to work around problems in allocating stack storage
647 in inline functions. */
649 #define FIRST_PSEUDO_REGISTER 77
651 /* This must not decrease, for backwards compatibility. If
652 FIRST_PSEUDO_REGISTER increases, this should as well. */
653 #define DWARF_FRAME_REGISTERS 77
655 /* 1 for registers that have pervasive standard uses
656 and are not available for the register allocator.
658 On RS/6000, r1 is used for the stack and r2 is used as the TOC pointer.
660 cr5 is not supposed to be used.
662 On System V implementations, r13 is fixed and not available for use. */
664 #define FIXED_REGISTERS \
665 {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
669 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1}
671 /* 1 for registers not available across function calls.
672 These must include the FIXED_REGISTERS and also any
673 registers that can be used without being saved.
674 The latter must include the registers where values are returned
675 and the register where structure-value addresses are passed.
676 Aside from that, you can include as many other registers as you like. */
678 #define CALL_USED_REGISTERS \
679 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
680 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
683 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1}
691 #define MAX_CR_REGNO 75
694 /* List the order in which to allocate registers. Each register must be
695 listed once, even those in FIXED_REGISTERS.
697 We allocate in the following order:
698 fp0 (not saved or used for anything)
699 fp13 - fp2 (not saved; incoming fp arg registers)
700 fp1 (not saved; return value)
701 fp31 - fp14 (saved; order given to save least number)
702 cr7, cr6 (not saved or special)
703 cr1 (not saved, but used for FP operations)
704 cr0 (not saved, but used for arithmetic operations)
705 cr4, cr3, cr2 (saved)
706 r0 (not saved; cannot be base reg)
707 r9 (not saved; best for TImode)
708 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
709 r3 (not saved; return value register)
710 r31 - r13 (saved; order given to save least number)
711 r12 (not saved; if used for DImode or DFmode would use r13)
712 mq (not saved; best to use it if we can)
713 ctr (not saved; when we have the choice ctr is better)
715 cr5, r1, r2, ap, xer (fixed) */
717 #define REG_ALLOC_ORDER \
719 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
721 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
722 50, 49, 48, 47, 46, \
723 75, 74, 69, 68, 72, 71, 70, \
725 9, 11, 10, 8, 7, 6, 5, 4, \
727 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
728 18, 17, 16, 15, 14, 13, 12, \
732 /* True if register is floating-point. */
733 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
735 /* True if register is a condition register. */
736 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
738 /* True if register is a condition register, but not cr0. */
739 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
741 /* True if register is an integer register. */
742 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
744 /* True if register is the XER register. */
745 #define XER_REGNO_P(N) ((N) == XER_REGNO)
747 /* Return number of consecutive hard regs needed starting at reg REGNO
748 to hold something of mode MODE.
749 This is ordinarily the length in words of a value of mode MODE
750 but can be less for certain modes in special long registers.
752 POWER and PowerPC GPRs hold 32 bits worth;
753 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
755 #define HARD_REGNO_NREGS(REGNO, MODE) \
756 (FP_REGNO_P (REGNO) \
757 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
758 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
760 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
761 For POWER and PowerPC, the GPRs can hold any mode, but the float
762 registers only can hold floating modes and DImode, and CR register only
763 can hold CC modes. We cannot put TImode anywhere except general
764 register and it must be able to fit within the register set. */
766 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
767 (FP_REGNO_P (REGNO) ? \
768 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
769 || (GET_MODE_CLASS (MODE) == MODE_INT \
770 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
771 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
772 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
773 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
774 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
777 /* Value is 1 if it is a good idea to tie two pseudo registers
778 when one has mode MODE1 and one has mode MODE2.
779 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
780 for any hard reg, then this must be 0 for correct output. */
781 #define MODES_TIEABLE_P(MODE1, MODE2) \
782 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
783 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
784 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
785 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
786 : GET_MODE_CLASS (MODE1) == MODE_CC \
787 ? GET_MODE_CLASS (MODE2) == MODE_CC \
788 : GET_MODE_CLASS (MODE2) == MODE_CC \
789 ? GET_MODE_CLASS (MODE1) == MODE_CC \
792 /* A C expression returning the cost of moving data from a register of class
793 CLASS1 to one of CLASS2.
795 On the RS/6000, copying between floating-point and fixed-point
796 registers is expensive. */
798 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
799 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
800 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
801 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
802 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
803 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
804 || (CLASS1) == LINK_OR_CTR_REGS) \
805 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
806 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
807 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
810 /* A C expressions returning the cost of moving data of MODE from a register to
813 On the RS/6000, bump this up a bit. */
815 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
816 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
817 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
821 /* Specify the cost of a branch insn; roughly the number of extra insns that
822 should be added to avoid a branch.
824 Set this to 3 on the RS/6000 since that is roughly the average cost of an
825 unscheduled conditional branch. */
827 #define BRANCH_COST 3
829 /* A C statement (sans semicolon) to update the integer variable COST
830 based on the relationship between INSN that is dependent on
831 DEP_INSN through the dependence LINK. The default is to make no
832 adjustment to COST. On the RS/6000, ignore the cost of anti- and
833 output-dependencies. In fact, output dependencies on the CR do have
834 a cost, but it is probably not worthwhile to track it. */
836 #define ADJUST_COST(INSN, LINK, DEP_INSN, COST) \
837 (COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST)
839 /* A C statement (sans semicolon) to update the integer scheduling priority
840 INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
841 increase the priority to execute INSN later. Do not define this macro if
842 you do not need to adjust the scheduling priorities of insns. */
844 #define ADJUST_PRIORITY(INSN) \
845 INSN_PRIORITY (INSN) = rs6000_adjust_priority (INSN, INSN_PRIORITY (INSN))
847 /* Define this macro to change register usage conditional on target flags.
848 Set MQ register fixed (already call_used) if not POWER architecture
849 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
850 64-bit AIX reserves GPR13 for thread-private data.
851 Conditionally disable FPRs. */
853 #define CONDITIONAL_REGISTER_USAGE \
855 if (! TARGET_POWER) \
856 fixed_regs[64] = 1; \
858 fixed_regs[13] = call_used_regs[13] = 1; \
859 if (TARGET_SOFT_FLOAT) \
860 for (i = 32; i < 64; i++) \
861 fixed_regs[i] = call_used_regs[i] = 1; \
862 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
864 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
865 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
866 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
867 global_regs[PIC_OFFSET_TABLE_REGNUM] \
868 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
869 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
872 /* Specify the registers used for certain standard purposes.
873 The values of these macros are register numbers. */
875 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
876 /* #define PC_REGNUM */
878 /* Register to use for pushing function arguments. */
879 #define STACK_POINTER_REGNUM 1
881 /* Base register for access to local variables of the function. */
882 #define FRAME_POINTER_REGNUM 31
884 /* Value should be nonzero if functions must have frame pointers.
885 Zero means the frame pointer need not be set up (and parms
886 may be accessed via the stack pointer) in functions that seem suitable.
887 This is computed in `reload', in reload1.c. */
888 #define FRAME_POINTER_REQUIRED 0
890 /* Base register for access to arguments of the function. */
891 #define ARG_POINTER_REGNUM 67
893 /* Place to put static chain when calling a function that requires it. */
894 #define STATIC_CHAIN_REGNUM 11
896 /* Link register number. */
897 #define LINK_REGISTER_REGNUM 65
899 /* Count register number. */
900 #define COUNT_REGISTER_REGNUM 66
902 /* Place that structure value return address is placed.
904 On the RS/6000, it is passed as an extra parameter. */
905 #define STRUCT_VALUE 0
907 /* Define the classes of registers for register constraints in the
908 machine description. Also define ranges of constants.
910 One of the classes must always be named ALL_REGS and include all hard regs.
911 If there is more than one class, another class must be named NO_REGS
912 and contain no registers.
914 The name GENERAL_REGS must be the name of a class (or an alias for
915 another name such as ALL_REGS). This is the class of registers
916 that is allowed by "g" or "r" in a register constraint.
917 Also, registers outside this class are allocated only when
918 instructions express preferences for them.
920 The classes must be numbered in nondecreasing order; that is,
921 a larger-numbered class must never be contained completely
922 in a smaller-numbered class.
924 For any two classes, it is very desirable that there be another
925 class that represents their union. */
927 /* The RS/6000 has three types of registers, fixed-point, floating-point,
928 and condition registers, plus three special registers, MQ, CTR, and the
931 However, r0 is special in that it cannot be used as a base register.
932 So make a class for registers valid as base registers.
934 Also, cr0 is the only condition code register that can be used in
935 arithmetic insns, so make a separate class for it. */
958 #define N_REG_CLASSES (int) LIM_REG_CLASSES
960 /* Give names of register classes as strings for dump file. */
962 #define REG_CLASS_NAMES \
968 "NON_SPECIAL_REGS", \
972 "LINK_OR_CTR_REGS", \
974 "SPEC_OR_GEN_REGS", \
982 /* Define which registers fit in which classes.
983 This is an initializer for a vector of HARD_REG_SET
984 of length N_REG_CLASSES. */
986 #define REG_CLASS_CONTENTS \
988 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
989 { 0xfffffffe, 0x00000000, 0x00000008 }, /* BASE_REGS */ \
990 { 0xffffffff, 0x00000000, 0x00000008 }, /* GENERAL_REGS */ \
991 { 0x00000000, 0xffffffff, 0x00000000 }, /* FLOAT_REGS */ \
992 { 0xffffffff, 0xffffffff, 0x00000008 }, /* NON_SPECIAL_REGS */ \
993 { 0x00000000, 0x00000000, 0x00000001 }, /* MQ_REGS */ \
994 { 0x00000000, 0x00000000, 0x00000002 }, /* LINK_REGS */ \
995 { 0x00000000, 0x00000000, 0x00000004 }, /* CTR_REGS */ \
996 { 0x00000000, 0x00000000, 0x00000006 }, /* LINK_OR_CTR_REGS */ \
997 { 0x00000000, 0x00000000, 0x00000007 }, /* SPECIAL_REGS */ \
998 { 0xffffffff, 0x00000000, 0x0000000f }, /* SPEC_OR_GEN_REGS */ \
999 { 0x00000000, 0x00000000, 0x00000010 }, /* CR0_REGS */ \
1000 { 0x00000000, 0x00000000, 0x00000ff0 }, /* CR_REGS */ \
1001 { 0xffffffff, 0x00000000, 0x0000ffff }, /* NON_FLOAT_REGS */ \
1002 { 0x00000000, 0x00000000, 0x00010000 }, /* XER_REGS */ \
1003 { 0xffffffff, 0xffffffff, 0x0001ffff } /* ALL_REGS */ \
1006 /* The same information, inverted:
1007 Return the class number of the smallest class containing
1008 reg number REGNO. This could be a conditional expression
1009 or could index an array. */
1011 #define REGNO_REG_CLASS(REGNO) \
1012 ((REGNO) == 0 ? GENERAL_REGS \
1013 : (REGNO) < 32 ? BASE_REGS \
1014 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1015 : (REGNO) == CR0_REGNO ? CR0_REGS \
1016 : CR_REGNO_P (REGNO) ? CR_REGS \
1017 : (REGNO) == MQ_REGNO ? MQ_REGS \
1018 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1019 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1020 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1021 : (REGNO) == XER_REGNO ? XER_REGS \
1024 /* The class value for index registers, and the one for base regs. */
1025 #define INDEX_REG_CLASS GENERAL_REGS
1026 #define BASE_REG_CLASS BASE_REGS
1028 /* Get reg_class from a letter such as appears in the machine description. */
1030 #define REG_CLASS_FROM_LETTER(C) \
1031 ((C) == 'f' ? FLOAT_REGS \
1032 : (C) == 'b' ? BASE_REGS \
1033 : (C) == 'h' ? SPECIAL_REGS \
1034 : (C) == 'q' ? MQ_REGS \
1035 : (C) == 'c' ? CTR_REGS \
1036 : (C) == 'l' ? LINK_REGS \
1037 : (C) == 'x' ? CR0_REGS \
1038 : (C) == 'y' ? CR_REGS \
1039 : (C) == 'z' ? XER_REGS \
1042 /* The letters I, J, K, L, M, N, and P in a register constraint string
1043 can be used to stand for particular ranges of immediate operands.
1044 This macro defines what the ranges are.
1045 C is the letter, and VALUE is a constant value.
1046 Return 1 if VALUE is in the range specified by C.
1048 `I' is a signed 16-bit constant
1049 `J' is a constant with only the high-order 16 bits non-zero
1050 `K' is a constant with only the low-order 16 bits non-zero
1051 `L' is a signed 16-bit constant shifted left 16 bits
1052 `M' is a constant that is greater than 31
1053 `N' is a constant that is an exact power of two
1054 `O' is the constant zero
1055 `P' is a constant whose negation is a signed 16-bit constant */
1057 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1058 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1059 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1060 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1061 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1062 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1063 : (C) == 'M' ? (VALUE) > 31 \
1064 : (C) == 'N' ? exact_log2 (VALUE) >= 0 \
1065 : (C) == 'O' ? (VALUE) == 0 \
1066 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1069 /* Similar, but for floating constants, and defining letters G and H.
1070 Here VALUE is the CONST_DOUBLE rtx itself.
1072 We flag for special constants when we can copy the constant into
1073 a general register in two insns for DF/DI and one insn for SF.
1075 'H' is used for DI/DF constants that take 3 insns. */
1077 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1078 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1079 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1080 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1083 /* Optional extra constraints for this machine.
1085 'Q' means that is a memory operand that is just an offset from a reg.
1086 'R' is for AIX TOC entries.
1087 'S' is a constant that can be placed into a 64-bit mask operand
1088 'T' is a consatnt that can be placed into a 32-bit mask operand
1089 'U' is for V.4 small data references. */
1091 #define EXTRA_CONSTRAINT(OP, C) \
1092 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1093 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1094 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1095 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1096 : (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1097 && small_data_operand (OP, GET_MODE (OP))) \
1100 /* Given an rtx X being reloaded into a reg required to be
1101 in class CLASS, return the class of reg to actually use.
1102 In general this is just CLASS; but on some machines
1103 in some cases it is preferable to use a more restrictive class.
1105 On the RS/6000, we have to return NO_REGS when we want to reload a
1106 floating-point CONST_DOUBLE to force it to be copied to memory.
1108 We also don't want to reload integer values into floating-point
1109 registers if we can at all help it. In fact, this can
1110 cause reload to abort, if it tries to generate a reload of CTR
1111 into a FP register and discovers it doesn't have the memory location
1114 ??? Would it be a good idea to have reload do the converse, that is
1115 try to reload floating modes into FP registers if possible?
1118 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1119 (((GET_CODE (X) == CONST_DOUBLE \
1120 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1122 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1123 && (CLASS) == NON_SPECIAL_REGS) \
1127 /* Return the register class of a scratch register needed to copy IN into
1128 or out of a register in CLASS in MODE. If it can be done directly,
1129 NO_REGS is returned. */
1131 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1132 secondary_reload_class (CLASS, MODE, IN)
1134 /* If we are copying between FP registers and anything else, we need a memory
1137 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1138 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS || (CLASS2) == FLOAT_REGS))
1140 /* Return the maximum number of consecutive registers
1141 needed to represent mode MODE in a register of class CLASS.
1143 On RS/6000, this is the size of MODE in words,
1144 except in the FP regs, where a single reg is enough for two words. */
1145 #define CLASS_MAX_NREGS(CLASS, MODE) \
1146 (((CLASS) == FLOAT_REGS) \
1147 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1148 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1150 /* If defined, gives a class of registers that cannot be used as the
1151 operand of a SUBREG that changes the mode of the object illegally. */
1153 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1155 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1157 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1158 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1160 /* Stack layout; function entry, exit and calling. */
1162 /* Enumeration to give which calling sequence to use. */
1165 ABI_AIX, /* IBM's AIX */
1166 ABI_AIX_NODESC, /* AIX calling sequence minus function descriptors */
1167 ABI_V4, /* System V.4/eabi */
1168 ABI_SOLARIS, /* Solaris */
1169 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1172 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1174 /* Structure used to define the rs6000 stack */
1175 typedef struct rs6000_stack {
1176 int first_gp_reg_save; /* first callee saved GP register used */
1177 int first_fp_reg_save; /* first callee saved FP register used */
1178 int lr_save_p; /* true if the link reg needs to be saved */
1179 int cr_save_p; /* true if the CR reg needs to be saved */
1180 int toc_save_p; /* true if the TOC needs to be saved */
1181 int push_p; /* true if we need to allocate stack space */
1182 int calls_p; /* true if the function makes any calls */
1183 enum rs6000_abi abi; /* which ABI to use */
1184 int gp_save_offset; /* offset to save GP regs from initial SP */
1185 int fp_save_offset; /* offset to save FP regs from initial SP */
1186 int lr_save_offset; /* offset to save LR from initial SP */
1187 int cr_save_offset; /* offset to save CR from initial SP */
1188 int toc_save_offset; /* offset to save the TOC pointer */
1189 int varargs_save_offset; /* offset to save the varargs registers */
1190 int ehrd_offset; /* offset to EH return data */
1191 int reg_size; /* register size (4 or 8) */
1192 int varargs_size; /* size to hold V.4 args passed in regs */
1193 int vars_size; /* variable save area size */
1194 int parm_size; /* outgoing parameter size */
1195 int save_size; /* save area size */
1196 int fixed_size; /* fixed size of stack frame */
1197 int gp_size; /* size of saved GP registers */
1198 int fp_size; /* size of saved FP registers */
1199 int cr_size; /* size to hold CR if not in save_size */
1200 int lr_size; /* size to hold LR if not in save_size */
1201 int toc_size; /* size to hold TOC if not in save_size */
1202 int total_size; /* total bytes allocated for stack */
1205 /* Define this if pushing a word on the stack
1206 makes the stack pointer a smaller address. */
1207 #define STACK_GROWS_DOWNWARD
1209 /* Define this if the nominal address of the stack frame
1210 is at the high-address end of the local variables;
1211 that is, each additional local variable allocated
1212 goes at a more negative offset in the frame.
1214 On the RS/6000, we grow upwards, from the area after the outgoing
1216 /* #define FRAME_GROWS_DOWNWARD */
1218 /* Size of the outgoing register save area */
1219 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1220 || DEFAULT_ABI == ABI_AIX_NODESC \
1221 || DEFAULT_ABI == ABI_DARWIN) \
1222 ? (TARGET_64BIT ? 64 : 32) \
1225 /* Size of the fixed area on the stack */
1226 #define RS6000_SAVE_AREA \
1227 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1228 << (TARGET_64BIT ? 1 : 0))
1230 /* MEM representing address to save the TOC register */
1231 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1232 plus_constant (stack_pointer_rtx, \
1233 (TARGET_32BIT ? 20 : 40)))
1235 /* Size of the V.4 varargs area if needed */
1236 #define RS6000_VARARGS_AREA 0
1238 /* Align an address */
1239 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1241 /* Size of V.4 varargs area in bytes */
1242 #define RS6000_VARARGS_SIZE \
1243 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1245 /* Offset within stack frame to start allocating local variables at.
1246 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1247 first local allocated. Otherwise, it is the offset to the BEGINNING
1248 of the first local allocated.
1250 On the RS/6000, the frame pointer is the same as the stack pointer,
1251 except for dynamic allocations. So we start after the fixed area and
1252 outgoing parameter area. */
1254 #define STARTING_FRAME_OFFSET \
1255 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1256 + RS6000_VARARGS_AREA \
1259 /* Offset from the stack pointer register to an item dynamically
1260 allocated on the stack, e.g., by `alloca'.
1262 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1263 length of the outgoing arguments. The default is correct for most
1264 machines. See `function.c' for details. */
1265 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1266 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1267 + (STACK_POINTER_OFFSET))
1269 /* If we generate an insn to push BYTES bytes,
1270 this says how many the stack pointer really advances by.
1271 On RS/6000, don't define this because there are no push insns. */
1272 /* #define PUSH_ROUNDING(BYTES) */
1274 /* Offset of first parameter from the argument pointer register value.
1275 On the RS/6000, we define the argument pointer to the start of the fixed
1277 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1279 /* Offset from the argument pointer register value to the top of
1280 stack. This is different from FIRST_PARM_OFFSET because of the
1281 register save area. */
1282 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1284 /* Define this if stack space is still allocated for a parameter passed
1285 in a register. The value is the number of bytes allocated to this
1287 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1289 /* Define this if the above stack space is to be considered part of the
1290 space allocated by the caller. */
1291 #define OUTGOING_REG_PARM_STACK_SPACE
1293 /* This is the difference between the logical top of stack and the actual sp.
1295 For the RS/6000, sp points past the fixed area. */
1296 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1298 /* Define this if the maximum size of all the outgoing args is to be
1299 accumulated and pushed during the prologue. The amount can be
1300 found in the variable current_function_outgoing_args_size. */
1301 #define ACCUMULATE_OUTGOING_ARGS 1
1303 /* Value is the number of bytes of arguments automatically
1304 popped when returning from a subroutine call.
1305 FUNDECL is the declaration node of the function (as a tree),
1306 FUNTYPE is the data type of the function (as a tree),
1307 or for a library call it is an identifier node for the subroutine name.
1308 SIZE is the number of bytes of arguments passed on the stack. */
1310 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1312 /* Define how to find the value returned by a function.
1313 VALTYPE is the data type of the value (as a tree).
1314 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1315 otherwise, FUNC is 0.
1317 On RS/6000 an integer value is in r3 and a floating-point value is in
1318 fp1, unless -msoft-float. */
1320 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1321 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1322 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1323 || POINTER_TYPE_P (VALTYPE) \
1324 ? word_mode : TYPE_MODE (VALTYPE), \
1325 TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 33 : 3)
1327 /* Define how to find the value returned by a library function
1328 assuming the value has mode MODE. */
1330 #define LIBCALL_VALUE(MODE) \
1331 gen_rtx_REG (MODE, (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1332 && TARGET_HARD_FLOAT ? 33 : 3))
1334 /* The definition of this macro implies that there are cases where
1335 a scalar value cannot be returned in registers.
1337 For the RS/6000, any structure or union type is returned in memory, except for
1338 Solaris, which returns structures <= 8 bytes in registers. */
1340 #define RETURN_IN_MEMORY(TYPE) \
1341 (TYPE_MODE (TYPE) == BLKmode \
1342 && (DEFAULT_ABI != ABI_SOLARIS || int_size_in_bytes (TYPE) > 8))
1344 /* Mode of stack savearea.
1345 FUNCTION is VOIDmode because calling convention maintains SP.
1346 BLOCK needs Pmode for SP.
1347 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1348 #define STACK_SAVEAREA_MODE(LEVEL) \
1349 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1350 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1352 /* Minimum and maximum general purpose registers used to hold arguments. */
1353 #define GP_ARG_MIN_REG 3
1354 #define GP_ARG_MAX_REG 10
1355 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1357 /* Minimum and maximum floating point registers used to hold arguments. */
1358 #define FP_ARG_MIN_REG 33
1359 #define FP_ARG_AIX_MAX_REG 45
1360 #define FP_ARG_V4_MAX_REG 40
1361 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1362 || DEFAULT_ABI == ABI_AIX_NODESC \
1363 || DEFAULT_ABI == ABI_DARWIN) \
1364 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1365 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1367 /* Return registers */
1368 #define GP_ARG_RETURN GP_ARG_MIN_REG
1369 #define FP_ARG_RETURN FP_ARG_MIN_REG
1371 /* Flags for the call/call_value rtl operations set up by function_arg */
1372 #define CALL_NORMAL 0x00000000 /* no special processing */
1373 /* Bits in 0x00000001 are unused. */
1374 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1375 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1376 #define CALL_LONG 0x00000008 /* always call indirect */
1378 /* 1 if N is a possible register number for a function value
1379 as seen by the caller.
1381 On RS/6000, this is r3 and fp1. */
1382 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN || ((N) == FP_ARG_RETURN))
1384 /* 1 if N is a possible register number for function argument passing.
1385 On RS/6000, these are r3-r10 and fp1-fp13. */
1386 #define FUNCTION_ARG_REGNO_P(N) \
1387 (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1388 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1391 /* A C structure for machine-specific, per-function data.
1392 This is added to the cfun structure. */
1393 typedef struct machine_function
1395 /* Whether a System V.4 varargs area was created. */
1397 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1398 int ra_needs_full_frame;
1401 /* Define a data type for recording info about an argument list
1402 during the scan of that argument list. This data type should
1403 hold all necessary information about the function itself
1404 and about the args processed so far, enough to enable macros
1405 such as FUNCTION_ARG to determine where the next arg should go.
1407 On the RS/6000, this is a structure. The first element is the number of
1408 total argument words, the second is used to store the next
1409 floating-point register number, and the third says how many more args we
1410 have prototype types for.
1412 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1413 the next availible GP register, `fregno' is the next available FP
1414 register, and `words' is the number of words used on the stack.
1416 The varargs/stdarg support requires that this structure's size
1417 be a multiple of sizeof(int). */
1419 typedef struct rs6000_args
1421 int words; /* # words used for passing GP registers */
1422 int fregno; /* next available FP register */
1423 int nargs_prototype; /* # args left in the current prototype */
1424 int orig_nargs; /* Original value of nargs_prototype */
1425 int prototype; /* Whether a prototype was defined */
1426 int call_cookie; /* Do special things for this call */
1427 int sysv_gregno; /* next available GP register */
1430 /* Define intermediate macro to compute the size (in registers) of an argument
1433 #define RS6000_ARG_SIZE(MODE, TYPE) \
1434 ((MODE) != BLKmode \
1435 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1436 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1437 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1439 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1440 for a call to a function whose data type is FNTYPE.
1441 For a library call, FNTYPE is 0. */
1443 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1444 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1446 /* Similar, but when scanning the definition of a procedure. We always
1447 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1449 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1450 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1452 /* Update the data in CUM to advance over an argument
1453 of mode MODE and data type TYPE.
1454 (TYPE is null for libcalls where that information may not be available.) */
1456 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1457 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1459 /* Non-zero if we can use a floating-point register to pass this arg. */
1460 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1461 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1462 && (CUM).fregno <= FP_ARG_MAX_REG \
1463 && TARGET_HARD_FLOAT)
1465 /* Determine where to put an argument to a function.
1466 Value is zero to push the argument on the stack,
1467 or a hard register in which to store the argument.
1469 MODE is the argument's machine mode.
1470 TYPE is the data type of the argument (as a tree).
1471 This is null for libcalls where that information may
1473 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1474 the preceding args and about the function being called.
1475 NAMED is nonzero if this argument is a named parameter
1476 (otherwise it is an extra parameter matching an ellipsis).
1478 On RS/6000 the first eight words of non-FP are normally in registers
1479 and the rest are pushed. The first 13 FP args are in registers.
1481 If this is floating-point and no prototype is specified, we use
1482 both an FP and integer register (or possibly FP reg and stack). Library
1483 functions (when TYPE is zero) always have the proper types for args,
1484 so we can pass the FP value just in one register. emit_library_function
1485 doesn't support EXPR_LIST anyway. */
1487 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1488 function_arg (&CUM, MODE, TYPE, NAMED)
1490 /* For an arg passed partly in registers and partly in memory,
1491 this is the number of registers used.
1492 For args passed entirely in registers or entirely in memory, zero. */
1494 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1495 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1497 /* A C expression that indicates when an argument must be passed by
1498 reference. If nonzero for an argument, a copy of that argument is
1499 made in memory and a pointer to the argument is passed instead of
1500 the argument itself. The pointer is passed in whatever way is
1501 appropriate for passing a pointer to that type. */
1503 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1504 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1506 /* If defined, a C expression which determines whether, and in which
1507 direction, to pad out an argument with extra space. The value
1508 should be of type `enum direction': either `upward' to pad above
1509 the argument, `downward' to pad below, or `none' to inhibit
1512 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1514 /* If defined, a C expression that gives the alignment boundary, in bits,
1515 of an argument with the specified mode and type. If it is not defined,
1516 PARM_BOUNDARY is used for all arguments. */
1518 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1519 function_arg_boundary (MODE, TYPE)
1521 /* Perform any needed actions needed for a function that is receiving a
1522 variable number of arguments.
1526 MODE and TYPE are the mode and type of the current parameter.
1528 PRETEND_SIZE is a variable that should be set to the amount of stack
1529 that must be pushed by the prolog to pretend that our caller pushed
1532 Normally, this macro will push all remaining incoming registers on the
1533 stack and set PRETEND_SIZE to the length of the registers pushed. */
1535 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1536 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1538 /* Define the `__builtin_va_list' type for the ABI. */
1539 #define BUILD_VA_LIST_TYPE(VALIST) \
1540 (VALIST) = rs6000_build_va_list ()
1542 /* Implement `va_start' for varargs and stdarg. */
1543 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1544 rs6000_va_start (stdarg, valist, nextarg)
1546 /* Implement `va_arg'. */
1547 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1548 rs6000_va_arg (valist, type)
1550 /* Define this macro to be a nonzero value if the location where a function
1551 argument is passed depends on whether or not it is a named argument. */
1552 #define STRICT_ARGUMENT_NAMING 1
1554 /* Output assembler code to FILE to increment profiler label # LABELNO
1555 for profiling a function entry. */
1557 #define FUNCTION_PROFILER(FILE, LABELNO) \
1558 output_function_profiler ((FILE), (LABELNO));
1560 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1561 the stack pointer does not matter. No definition is equivalent to
1564 On the RS/6000, this is non-zero because we can restore the stack from
1565 its backpointer, which we maintain. */
1566 #define EXIT_IGNORE_STACK 1
1568 /* Define this macro as a C expression that is nonzero for registers
1569 that are used by the epilogue or the return' pattern. The stack
1570 and frame pointer registers are already be assumed to be used as
1573 #define EPILOGUE_USES(REGNO) \
1574 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1575 || (current_function_calls_eh_return \
1577 && (REGNO) == TOC_REGISTER))
1579 /* TRAMPOLINE_TEMPLATE deleted */
1581 /* Length in units of the trampoline for entering a nested function. */
1583 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1585 /* Emit RTL insns to initialize the variable parts of a trampoline.
1586 FNADDR is an RTX for the address of the function's pure code.
1587 CXT is an RTX for the static chain value for the function. */
1589 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1590 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1592 /* Definitions for __builtin_return_address and __builtin_frame_address.
1593 __builtin_return_address (0) should give link register (65), enable
1595 /* This should be uncommented, so that the link register is used, but
1596 currently this would result in unmatched insns and spilling fixed
1597 registers so we'll leave it for another day. When these problems are
1598 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1600 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1602 /* Number of bytes into the frame return addresses can be found. See
1603 rs6000_stack_info in rs6000.c for more information on how the different
1604 abi's store the return address. */
1605 #define RETURN_ADDRESS_OFFSET \
1606 ((DEFAULT_ABI == ABI_AIX \
1607 || DEFAULT_ABI == ABI_DARWIN \
1608 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1609 (DEFAULT_ABI == ABI_V4 \
1610 || DEFAULT_ABI == ABI_SOLARIS) ? (TARGET_32BIT ? 4 : 8) : \
1611 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1613 /* The current return address is in link register (65). The return address
1614 of anything farther back is accessed normally at an offset of 8 from the
1616 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1617 (rs6000_return_addr (COUNT, FRAME))
1620 /* Definitions for register eliminations.
1622 We have two registers that can be eliminated on the RS/6000. First, the
1623 frame pointer register can often be eliminated in favor of the stack
1624 pointer register. Secondly, the argument pointer register can always be
1625 eliminated; it is replaced with either the stack or frame pointer.
1627 In addition, we use the elimination mechanism to see if r30 is needed
1628 Initially we assume that it isn't. If it is, we spill it. This is done
1629 by making it an eliminable register. We replace it with itself so that
1630 if it isn't needed, then existing uses won't be modified. */
1632 /* This is an array of structures. Each structure initializes one pair
1633 of eliminable registers. The "from" register number is given first,
1634 followed by "to". Eliminations of the same "from" register are listed
1635 in order of preference. */
1636 #define ELIMINABLE_REGS \
1637 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1638 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1639 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1642 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1643 Frame pointer elimination is automatically handled.
1645 For the RS/6000, if frame pointer elimination is being done, we would like
1646 to convert ap into fp, not sp.
1648 We need r30 if -mminimal-toc was specified, and there are constant pool
1651 #define CAN_ELIMINATE(FROM, TO) \
1652 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1653 ? ! frame_pointer_needed \
1654 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1657 /* Define the offset between two registers, one to be eliminated, and the other
1658 its replacement, at the start of a routine. */
1659 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1661 rs6000_stack_t *info = rs6000_stack_info (); \
1663 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1664 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1665 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1666 (OFFSET) = info->total_size; \
1667 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1668 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1669 else if ((FROM) == 30) \
1675 /* Addressing modes, and classification of registers for them. */
1677 /* #define HAVE_POST_INCREMENT 0 */
1678 /* #define HAVE_POST_DECREMENT 0 */
1680 #define HAVE_PRE_DECREMENT 1
1681 #define HAVE_PRE_INCREMENT 1
1683 /* Macros to check register numbers against specific register classes. */
1685 /* These assume that REGNO is a hard or pseudo reg number.
1686 They give nonzero only if REGNO is a hard reg of the suitable class
1687 or a pseudo reg currently allocated to a suitable hard reg.
1688 Since they use reg_renumber, they are safe only once reg_renumber
1689 has been allocated, which happens in local-alloc.c. */
1691 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1692 ((REGNO) < FIRST_PSEUDO_REGISTER \
1693 ? (REGNO) <= 31 || (REGNO) == 67 \
1694 : (reg_renumber[REGNO] >= 0 \
1695 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1697 #define REGNO_OK_FOR_BASE_P(REGNO) \
1698 ((REGNO) < FIRST_PSEUDO_REGISTER \
1699 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1700 : (reg_renumber[REGNO] > 0 \
1701 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1703 /* Maximum number of registers that can appear in a valid memory address. */
1705 #define MAX_REGS_PER_ADDRESS 2
1707 /* Recognize any constant value that is a valid address. */
1709 #define CONSTANT_ADDRESS_P(X) \
1710 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1711 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1712 || GET_CODE (X) == HIGH)
1714 /* Nonzero if the constant value X is a legitimate general operand.
1715 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1717 On the RS/6000, all integer constants are acceptable, most won't be valid
1718 for particular insns, though. Only easy FP constants are
1721 #define LEGITIMATE_CONSTANT_P(X) \
1722 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1723 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1724 || easy_fp_constant (X, GET_MODE (X)))
1726 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1727 and check its validity for a certain class.
1728 We have two alternate definitions for each of them.
1729 The usual definition accepts all pseudo regs; the other rejects
1730 them unless they have been allocated suitable hard regs.
1731 The symbol REG_OK_STRICT causes the latter definition to be used.
1733 Most source files want to accept pseudo regs in the hope that
1734 they will get allocated to the class that the insn wants them to be in.
1735 Source files for reload pass need to be strict.
1736 After reload, it makes no difference, since pseudo regs have
1737 been eliminated by then. */
1739 #ifdef REG_OK_STRICT
1740 # define REG_OK_STRICT_FLAG 1
1742 # define REG_OK_STRICT_FLAG 0
1745 /* Nonzero if X is a hard reg that can be used as an index
1746 or if it is a pseudo reg in the non-strict case. */
1747 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1749 && (REGNO (X) <= 31 \
1750 || REGNO (X) == ARG_POINTER_REGNUM \
1751 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1752 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1754 /* Nonzero if X is a hard reg that can be used as a base reg
1755 or if it is a pseudo reg in the non-strict case. */
1756 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1757 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1759 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1760 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1762 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1763 that is a valid memory address for an instruction.
1764 The MODE argument is the machine mode for the MEM expression
1765 that wants to use this address.
1767 On the RS/6000, there are four valid address: a SYMBOL_REF that
1768 refers to a constant pool entry of an address (or the sum of it
1769 plus a constant), a short (16-bit signed) constant plus a register,
1770 the sum of two registers, or a register indirect, possibly with an
1771 auto-increment. For DFmode and DImode with an constant plus register,
1772 we must ensure that both words are addressable or PowerPC64 with offset
1775 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1776 32-bit DImode, TImode), indexed addressing cannot be used because
1777 adjacent memory cells are accessed by adding word-sized offsets
1778 during assembly output. */
1780 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1782 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1784 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1786 && GET_CODE (X) == PLUS \
1787 && GET_CODE (XEXP (X, 0)) == REG \
1788 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1789 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1791 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1792 ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1793 && !flag_pic && !TARGET_TOC \
1794 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1795 && small_data_operand (X, MODE))
1797 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1798 (GET_CODE (X) == CONST_INT \
1799 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1801 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1802 (GET_CODE (X) == PLUS \
1803 && GET_CODE (XEXP (X, 0)) == REG \
1804 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1805 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1806 && (((MODE) != DFmode && (MODE) != DImode) \
1808 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1809 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1810 && ((MODE) != TImode \
1812 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1813 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1814 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1816 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1817 (GET_CODE (X) == PLUS \
1818 && GET_CODE (XEXP (X, 0)) == REG \
1819 && GET_CODE (XEXP (X, 1)) == REG \
1820 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1821 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
1822 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
1823 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
1825 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
1826 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
1828 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
1830 && ! flag_pic && ! TARGET_TOC \
1831 && (MODE) != DImode \
1832 && (MODE) != TImode \
1833 && (TARGET_HARD_FLOAT || (MODE) != DFmode) \
1834 && GET_CODE (X) == LO_SUM \
1835 && GET_CODE (XEXP (X, 0)) == REG \
1836 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1837 && CONSTANT_P (XEXP (X, 1)))
1839 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1840 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1844 /* Try machine-dependent ways of modifying an illegitimate address
1845 to be legitimate. If we find one, return the new, valid address.
1846 This macro is used in only one place: `memory_address' in explow.c.
1848 OLDX is the address as it was before break_out_memory_refs was called.
1849 In some cases it is useful to look at this to decide what needs to be done.
1851 MODE and WIN are passed so that this macro can use
1852 GO_IF_LEGITIMATE_ADDRESS.
1854 It is always safe for this macro to do nothing. It exists to recognize
1855 opportunities to optimize the output.
1857 On RS/6000, first check for the sum of a register with a constant
1858 integer that is out of range. If so, generate code to add the
1859 constant with the low-order 16 bits masked to the register and force
1860 this result into another register (this can be done with `cau').
1861 Then generate an address of REG+(CONST&0xffff), allowing for the
1862 possibility of bit 16 being a one.
1864 Then check for the sum of a register and something not constant, try to
1865 load the other things into a register and return the sum. */
1867 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1868 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1869 if (result != NULL_RTX) \
1876 /* Try a machine-dependent way of reloading an illegitimate address
1877 operand. If we find one, push the reload and jump to WIN. This
1878 macro is used in only one place: `find_reloads_address' in reload.c.
1880 For RS/6000, we wish to handle large displacements off a base
1881 register by splitting the addend across an addiu/addis and the mem insn.
1882 This cuts number of extra insns needed from 3 to 1. */
1884 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1886 /* We must recognize output that we have already generated ourselves. */ \
1887 if (GET_CODE (X) == PLUS \
1888 && GET_CODE (XEXP (X, 0)) == PLUS \
1889 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1890 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1891 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1893 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1894 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1898 if (GET_CODE (X) == PLUS \
1899 && GET_CODE (XEXP (X, 0)) == REG \
1900 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1901 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1902 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1904 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1905 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1906 HOST_WIDE_INT high \
1907 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1909 /* Check for 32-bit overflow. */ \
1910 if (high + low != val) \
1913 /* Reload the high part into a base reg; leave the low part \
1914 in the mem directly. */ \
1916 X = gen_rtx_PLUS (GET_MODE (X), \
1917 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1921 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1922 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1926 else if (TARGET_TOC \
1927 && CONSTANT_POOL_EXPR_P (X) \
1928 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \
1930 (X) = create_TOC_reference (X); \
1935 /* Go to LABEL if ADDR (a legitimate address expression)
1936 has an effect that depends on the machine mode it is used for.
1938 On the RS/6000 this is true if the address is valid with a zero offset
1939 but not with an offset of four (this means it cannot be used as an
1940 address for DImode or DFmode) or is a pre-increment or decrement. Since
1941 we know it is valid, we just check for an address that is not valid with
1942 an offset of four. */
1944 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1945 { if (GET_CODE (ADDR) == PLUS \
1946 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
1947 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
1948 (TARGET_32BIT ? 4 : 8))) \
1950 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
1952 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
1954 if (GET_CODE (ADDR) == LO_SUM) \
1958 /* The register number of the register used to address a table of
1959 static data addresses in memory. In some cases this register is
1960 defined by a processor's "application binary interface" (ABI).
1961 When this macro is defined, RTL is generated for this register
1962 once, as with the stack pointer and frame pointer registers. If
1963 this macro is not defined, it is up to the machine-dependent files
1964 to allocate such a register (if necessary). */
1966 #define PIC_OFFSET_TABLE_REGNUM 30
1968 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
1970 /* Define this macro if the register defined by
1971 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1972 this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */
1974 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1976 /* By generating position-independent code, when two different
1977 programs (A and B) share a common library (libC.a), the text of
1978 the library can be shared whether or not the library is linked at
1979 the same address for both programs. In some of these
1980 environments, position-independent code requires not only the use
1981 of different addressing modes, but also special code to enable the
1982 use of these addressing modes.
1984 The `FINALIZE_PIC' macro serves as a hook to emit these special
1985 codes once the function is being compiled into assembly code, but
1986 not before. (It is not done before, because in the case of
1987 compiling an inline function, it would lead to multiple PIC
1988 prologues being included in functions which used inline functions
1989 and were compiled to assembly language.) */
1991 /* #define FINALIZE_PIC */
1993 /* A C expression that is nonzero if X is a legitimate immediate
1994 operand on the target machine when generating position independent
1995 code. You can assume that X satisfies `CONSTANT_P', so you need
1996 not check this. You can also assume FLAG_PIC is true, so you need
1997 not check it either. You need not define this macro if all
1998 constants (including `SYMBOL_REF') can be immediate operands when
1999 generating position independent code. */
2001 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2003 /* In rare cases, correct code generation requires extra machine
2004 dependent processing between the second jump optimization pass and
2005 delayed branch scheduling. On those machines, define this macro
2006 as a C statement to act on the code starting at INSN. */
2008 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2011 /* Define this if some processing needs to be done immediately before
2012 emitting code for an insn. */
2014 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2016 /* Specify the machine mode that this machine uses
2017 for the index in the tablejump instruction. */
2018 #define CASE_VECTOR_MODE SImode
2020 /* Define as C expression which evaluates to nonzero if the tablejump
2021 instruction expects the table to contain offsets from the address of the
2023 Do not define this if the table should contain absolute addresses. */
2024 #define CASE_VECTOR_PC_RELATIVE 1
2026 /* Specify the tree operation to be used to convert reals to integers. */
2027 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2029 /* This is the kind of divide that is easiest to do in the general case. */
2030 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2032 /* Define this as 1 if `char' should by default be signed; else as 0. */
2033 #define DEFAULT_SIGNED_CHAR 0
2035 /* This flag, if defined, says the same insns that convert to a signed fixnum
2036 also convert validly to an unsigned one. */
2038 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2040 /* Max number of bytes we can move from memory to memory
2041 in one reasonably fast instruction. */
2042 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2043 #define MAX_MOVE_MAX 8
2045 /* Nonzero if access to memory by bytes is no faster than for words.
2046 Also non-zero if doing byte operations (specifically shifts) in registers
2048 #define SLOW_BYTE_ACCESS 1
2050 /* Define if operations between registers always perform the operation
2051 on the full register even if a narrower mode is specified. */
2052 #define WORD_REGISTER_OPERATIONS
2054 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2055 will either zero-extend or sign-extend. The value of this macro should
2056 be the code that says which one of the two operations is implicitly
2057 done, NIL if none. */
2058 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2060 /* Define if loading short immediate values into registers sign extends. */
2061 #define SHORT_IMMEDIATES_SIGN_EXTEND
2063 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2064 is done just by pretending it is already truncated. */
2065 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2067 /* Specify the machine mode that pointers have.
2068 After generation of rtl, the compiler makes no further distinction
2069 between pointers and any other objects of this machine mode. */
2070 #define Pmode (TARGET_32BIT ? SImode : DImode)
2072 /* Mode of a function address in a call instruction (for indexing purposes).
2073 Doesn't matter on RS/6000. */
2074 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2076 /* Define this if addresses of constant functions
2077 shouldn't be put through pseudo regs where they can be cse'd.
2078 Desirable on machines where ordinary constants are expensive
2079 but a CALL with constant address is cheap. */
2080 #define NO_FUNCTION_CSE
2082 /* Define this to be nonzero if shift instructions ignore all but the low-order
2085 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2086 have been dropped from the PowerPC architecture. */
2088 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2090 /* Compute the cost of computing a constant rtl expression RTX
2091 whose rtx-code is CODE. The body of this macro is a portion
2092 of a switch statement. If the code is computed here,
2093 return it with a return statement. Otherwise, break from the switch.
2095 On the RS/6000, if it is valid in the insn, it is free. So this
2096 always returns 0. */
2098 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2103 case CONST_DOUBLE: \
2107 /* Provide the costs of a rtl expression. This is in the body of a
2110 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2112 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2113 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2114 + 0x8000) >= 0x10000) \
2115 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2116 ? COSTS_N_INSNS (2) \
2117 : COSTS_N_INSNS (1)); \
2121 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2122 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2123 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2124 ? COSTS_N_INSNS (2) \
2125 : COSTS_N_INSNS (1)); \
2127 switch (rs6000_cpu) \
2129 case PROCESSOR_RIOS1: \
2130 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2131 ? COSTS_N_INSNS (5) \
2132 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2133 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2134 case PROCESSOR_RS64A: \
2135 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2136 ? GET_MODE (XEXP (X, 1)) != DImode \
2137 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2138 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2139 ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
2140 case PROCESSOR_RIOS2: \
2141 case PROCESSOR_MPCCORE: \
2142 case PROCESSOR_PPC604e: \
2143 return COSTS_N_INSNS (2); \
2144 case PROCESSOR_PPC601: \
2145 return COSTS_N_INSNS (5); \
2146 case PROCESSOR_PPC603: \
2147 case PROCESSOR_PPC750: \
2148 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2149 ? COSTS_N_INSNS (5) \
2150 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2151 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2152 case PROCESSOR_PPC403: \
2153 case PROCESSOR_PPC604: \
2154 return COSTS_N_INSNS (4); \
2155 case PROCESSOR_PPC620: \
2156 case PROCESSOR_PPC630: \
2157 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2158 ? GET_MODE (XEXP (X, 1)) != DImode \
2159 ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
2160 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2161 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2165 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2166 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2167 return COSTS_N_INSNS (2); \
2168 /* otherwise fall through to normal divide. */ \
2171 switch (rs6000_cpu) \
2173 case PROCESSOR_RIOS1: \
2174 return COSTS_N_INSNS (19); \
2175 case PROCESSOR_RIOS2: \
2176 return COSTS_N_INSNS (13); \
2177 case PROCESSOR_RS64A: \
2178 return (GET_MODE (XEXP (X, 1)) != DImode \
2179 ? COSTS_N_INSNS (65) \
2180 : COSTS_N_INSNS (67)); \
2181 case PROCESSOR_MPCCORE: \
2182 return COSTS_N_INSNS (6); \
2183 case PROCESSOR_PPC403: \
2184 return COSTS_N_INSNS (33); \
2185 case PROCESSOR_PPC601: \
2186 return COSTS_N_INSNS (36); \
2187 case PROCESSOR_PPC603: \
2188 return COSTS_N_INSNS (37); \
2189 case PROCESSOR_PPC604: \
2190 case PROCESSOR_PPC604e: \
2191 return COSTS_N_INSNS (20); \
2192 case PROCESSOR_PPC620: \
2193 case PROCESSOR_PPC630: \
2194 return (GET_MODE (XEXP (X, 1)) != DImode \
2195 ? COSTS_N_INSNS (21) \
2196 : COSTS_N_INSNS (37)); \
2197 case PROCESSOR_PPC750: \
2198 return COSTS_N_INSNS (19); \
2201 return COSTS_N_INSNS (4); \
2203 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2206 /* Compute the cost of an address. This is meant to approximate the size
2207 and/or execution delay of an insn using that address. If the cost is
2208 approximated by the RTL complexity, including CONST_COSTS above, as
2209 is usually the case for CISC machines, this macro should not be defined.
2210 For aggressively RISCy machines, only one insn format is allowed, so
2211 this macro should be a constant. The value of this macro only matters
2212 for valid addresses.
2214 For the RS/6000, everything is cost 0. */
2216 #define ADDRESS_COST(RTX) 0
2218 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2219 should be adjusted to reflect any required changes. This macro is used when
2220 there is some systematic length adjustment required that would be difficult
2221 to express in the length attribute. */
2223 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2225 /* Add any extra modes needed to represent the condition code.
2227 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2228 are being done and we need a separate mode for floating-point. We also
2229 use a mode for the case when we are comparing the results of two
2230 comparisons, as then only the EQ bit is valid in the register. */
2232 #define EXTRA_CC_MODES \
2233 CC(CCUNSmode, "CCUNS") \
2234 CC(CCFPmode, "CCFP") \
2235 CC(CCEQmode, "CCEQ")
2237 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2238 COMPARE, return the mode to be used for the comparison. For
2239 floating-point, CCFPmode should be used. CCUNSmode should be used
2240 for unsigned comparisons. CCEQmode should be used when we are
2241 doing an inequality comparison on the result of a
2242 comparison. CCmode should be used in all other cases. */
2244 #define SELECT_CC_MODE(OP,X,Y) \
2245 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2246 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2247 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2248 ? CCEQmode : CCmode))
2250 /* Define the information needed to generate branch and scc insns. This is
2251 stored from the compare operation. Note that we can't use "rtx" here
2252 since it hasn't been defined! */
2254 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2255 extern int rs6000_compare_fp_p;
2257 /* Control the assembler format that we output. */
2259 /* A C string constant describing how to begin a comment in the target
2260 assembler language. The compiler assumes that the comment will end at
2261 the end of the line. */
2262 #define ASM_COMMENT_START " #"
2264 /* Implicit library calls should use memcpy, not bcopy, etc. */
2266 #define TARGET_MEM_FUNCTIONS
2268 /* Flag to say the TOC is initialized */
2269 extern int toc_initialized;
2271 /* Macro to output a special constant pool entry. Go to WIN if we output
2272 it. Otherwise, it is written the usual way.
2274 On the RS/6000, toc entries are handled this way. */
2276 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2277 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2279 output_toc (FILE, X, LABELNO, MODE); \
2284 /* This is how we tell the assembler that two symbols have the same value. */
2286 #define SET_ASM_OP "\t.set\t"
2288 /* This implementes the `alias' attribute. */
2290 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2292 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2293 char * name = IDENTIFIER_POINTER (target); \
2294 if (TREE_CODE (decl) == FUNCTION_DECL \
2295 && DEFAULT_ABI == ABI_AIX) \
2297 if (TREE_PUBLIC (decl)) \
2299 fputs ("\t.globl .", FILE); \
2300 assemble_name (FILE, alias); \
2301 putc ('\n', FILE); \
2305 fputs ("\t.lglobl .", FILE); \
2306 assemble_name (FILE, alias); \
2307 putc ('\n', FILE); \
2309 fputs ("\t.set .", FILE); \
2310 assemble_name (FILE, alias); \
2311 fputs (",.", FILE); \
2312 assemble_name (FILE, name); \
2313 fputc ('\n', FILE); \
2315 ASM_OUTPUT_DEF (FILE, alias, name); \
2318 /* Output to assembler file text saying following lines
2319 may contain character constants, extra white space, comments, etc. */
2321 #define ASM_APP_ON ""
2323 /* Output to assembler file text saying following lines
2324 no longer contain unusual constructs. */
2326 #define ASM_APP_OFF ""
2328 /* How to refer to registers in assembler output.
2329 This sequence is indexed by compiler's hard-register-number (see above). */
2331 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2333 #define REGISTER_NAMES \
2335 &rs6000_reg_names[ 0][0], /* r0 */ \
2336 &rs6000_reg_names[ 1][0], /* r1 */ \
2337 &rs6000_reg_names[ 2][0], /* r2 */ \
2338 &rs6000_reg_names[ 3][0], /* r3 */ \
2339 &rs6000_reg_names[ 4][0], /* r4 */ \
2340 &rs6000_reg_names[ 5][0], /* r5 */ \
2341 &rs6000_reg_names[ 6][0], /* r6 */ \
2342 &rs6000_reg_names[ 7][0], /* r7 */ \
2343 &rs6000_reg_names[ 8][0], /* r8 */ \
2344 &rs6000_reg_names[ 9][0], /* r9 */ \
2345 &rs6000_reg_names[10][0], /* r10 */ \
2346 &rs6000_reg_names[11][0], /* r11 */ \
2347 &rs6000_reg_names[12][0], /* r12 */ \
2348 &rs6000_reg_names[13][0], /* r13 */ \
2349 &rs6000_reg_names[14][0], /* r14 */ \
2350 &rs6000_reg_names[15][0], /* r15 */ \
2351 &rs6000_reg_names[16][0], /* r16 */ \
2352 &rs6000_reg_names[17][0], /* r17 */ \
2353 &rs6000_reg_names[18][0], /* r18 */ \
2354 &rs6000_reg_names[19][0], /* r19 */ \
2355 &rs6000_reg_names[20][0], /* r20 */ \
2356 &rs6000_reg_names[21][0], /* r21 */ \
2357 &rs6000_reg_names[22][0], /* r22 */ \
2358 &rs6000_reg_names[23][0], /* r23 */ \
2359 &rs6000_reg_names[24][0], /* r24 */ \
2360 &rs6000_reg_names[25][0], /* r25 */ \
2361 &rs6000_reg_names[26][0], /* r26 */ \
2362 &rs6000_reg_names[27][0], /* r27 */ \
2363 &rs6000_reg_names[28][0], /* r28 */ \
2364 &rs6000_reg_names[29][0], /* r29 */ \
2365 &rs6000_reg_names[30][0], /* r30 */ \
2366 &rs6000_reg_names[31][0], /* r31 */ \
2368 &rs6000_reg_names[32][0], /* fr0 */ \
2369 &rs6000_reg_names[33][0], /* fr1 */ \
2370 &rs6000_reg_names[34][0], /* fr2 */ \
2371 &rs6000_reg_names[35][0], /* fr3 */ \
2372 &rs6000_reg_names[36][0], /* fr4 */ \
2373 &rs6000_reg_names[37][0], /* fr5 */ \
2374 &rs6000_reg_names[38][0], /* fr6 */ \
2375 &rs6000_reg_names[39][0], /* fr7 */ \
2376 &rs6000_reg_names[40][0], /* fr8 */ \
2377 &rs6000_reg_names[41][0], /* fr9 */ \
2378 &rs6000_reg_names[42][0], /* fr10 */ \
2379 &rs6000_reg_names[43][0], /* fr11 */ \
2380 &rs6000_reg_names[44][0], /* fr12 */ \
2381 &rs6000_reg_names[45][0], /* fr13 */ \
2382 &rs6000_reg_names[46][0], /* fr14 */ \
2383 &rs6000_reg_names[47][0], /* fr15 */ \
2384 &rs6000_reg_names[48][0], /* fr16 */ \
2385 &rs6000_reg_names[49][0], /* fr17 */ \
2386 &rs6000_reg_names[50][0], /* fr18 */ \
2387 &rs6000_reg_names[51][0], /* fr19 */ \
2388 &rs6000_reg_names[52][0], /* fr20 */ \
2389 &rs6000_reg_names[53][0], /* fr21 */ \
2390 &rs6000_reg_names[54][0], /* fr22 */ \
2391 &rs6000_reg_names[55][0], /* fr23 */ \
2392 &rs6000_reg_names[56][0], /* fr24 */ \
2393 &rs6000_reg_names[57][0], /* fr25 */ \
2394 &rs6000_reg_names[58][0], /* fr26 */ \
2395 &rs6000_reg_names[59][0], /* fr27 */ \
2396 &rs6000_reg_names[60][0], /* fr28 */ \
2397 &rs6000_reg_names[61][0], /* fr29 */ \
2398 &rs6000_reg_names[62][0], /* fr30 */ \
2399 &rs6000_reg_names[63][0], /* fr31 */ \
2401 &rs6000_reg_names[64][0], /* mq */ \
2402 &rs6000_reg_names[65][0], /* lr */ \
2403 &rs6000_reg_names[66][0], /* ctr */ \
2404 &rs6000_reg_names[67][0], /* ap */ \
2406 &rs6000_reg_names[68][0], /* cr0 */ \
2407 &rs6000_reg_names[69][0], /* cr1 */ \
2408 &rs6000_reg_names[70][0], /* cr2 */ \
2409 &rs6000_reg_names[71][0], /* cr3 */ \
2410 &rs6000_reg_names[72][0], /* cr4 */ \
2411 &rs6000_reg_names[73][0], /* cr5 */ \
2412 &rs6000_reg_names[74][0], /* cr6 */ \
2413 &rs6000_reg_names[75][0], /* cr7 */ \
2415 &rs6000_reg_names[76][0], /* xer */ \
2418 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2419 following for it. Switch to use the alternate names since
2420 they are more mnemonic. */
2422 #define DEBUG_REGISTER_NAMES \
2424 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2425 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2426 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2427 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2432 "mq", "lr", "ctr", "ap", \
2433 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2437 /* Table of additional register names to use in user input. */
2439 #define ADDITIONAL_REGISTER_NAMES \
2440 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2441 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2442 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2443 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2444 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2445 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2446 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2447 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2448 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2449 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2450 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2451 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2452 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2453 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2454 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2455 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2456 /* no additional names for: mq, lr, ctr, ap */ \
2457 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2458 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2459 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2461 /* How to renumber registers for dbx and gdb. */
2463 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2465 /* Text to write out after a CALL that may be replaced by glue code by
2466 the loader. This depends on the AIX version. */
2467 #define RS6000_CALL_GLUE "cror 31,31,31"
2469 /* This is how to output an assembler line defining a `double' constant. */
2471 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
2474 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2475 fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \
2476 t[0] & 0xffffffff, t[1] & 0xffffffff); \
2479 /* This is how to output an assembler line defining a `float' constant. */
2481 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
2484 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2485 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2488 /* This is how to output an assembler line defining an `int' constant. */
2490 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2494 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
2495 UNITS_PER_WORD, 1); \
2496 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
2497 UNITS_PER_WORD, 1); \
2501 fputs ("\t.llong ", FILE); \
2502 output_addr_const (FILE, (VALUE)); \
2503 putc ('\n', FILE); \
2507 #define ASM_OUTPUT_INT(FILE,VALUE) \
2508 ( fputs ("\t.long ", FILE), \
2509 output_addr_const (FILE, (VALUE)), \
2512 /* Likewise for `char' and `short' constants. */
2514 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2515 ( fputs ("\t.short ", FILE), \
2516 output_addr_const (FILE, (VALUE)), \
2519 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2520 ( fputs ("\t.byte ", FILE), \
2521 output_addr_const (FILE, (VALUE)), \
2524 /* This is how to output an assembler line for a numeric constant byte. */
2526 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2527 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
2529 /* This is used by the definition of ASM_OUTPUT_ADDR_ELT in defaults.h. */
2530 #define ASM_LONG (TARGET_32BIT ? ".long" : ".quad")
2532 /* This is how to output an element of a case-vector that is relative. */
2534 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2535 do { char buf[100]; \
2536 fputs ("\t.long ", FILE); \
2537 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2538 assemble_name (FILE, buf); \
2540 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2541 assemble_name (FILE, buf); \
2542 putc ('\n', FILE); \
2545 /* This is how to output an assembler line
2546 that says to advance the location counter
2547 to a multiple of 2**LOG bytes. */
2549 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2551 fprintf (FILE, "\t.align %d\n", (LOG))
2553 /* This says how to output an assembler line
2554 to define a local common symbol.
2555 Alignment cannot be specified, but we can try to maintain
2556 alignment after preceding TOC section if it was aligned
2559 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2560 do { fputs (".lcomm ", (FILE)); \
2561 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2562 fprintf ((FILE), ",%d,%s\n", (TARGET_32BIT ? (SIZE) : (ROUNDED)), \
2563 xcoff_bss_section_name); \
2566 /* Store in OUTPUT a string (made with alloca) containing
2567 an assembler-name for a local static variable named NAME.
2568 LABELNO is an integer which is different for each call. */
2570 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2571 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2572 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2574 /* Define the parentheses used to group arithmetic operations
2575 in assembler code. */
2577 #define ASM_OPEN_PAREN "("
2578 #define ASM_CLOSE_PAREN ")"
2580 /* Pick up the return address upon entry to a procedure. Used for
2581 dwarf2 unwind information. This also enables the table driven
2584 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2585 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2587 /* Describe how we implement __builtin_eh_return. */
2588 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2589 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2591 /* Print operand X (an rtx) in assembler syntax to file FILE.
2592 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2593 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2595 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2597 /* Define which CODE values are valid. */
2599 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2600 ((CODE) == '.' || (CODE) == '*' || (CODE) == '$')
2602 /* Print a memory address as an operand to reference that memory location. */
2604 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2606 /* Define the codes that are matched by predicates in rs6000.c. */
2608 #define PREDICATE_CODES \
2609 {"short_cint_operand", {CONST_INT}}, \
2610 {"u_short_cint_operand", {CONST_INT}}, \
2611 {"non_short_cint_operand", {CONST_INT}}, \
2612 {"gpc_reg_operand", {SUBREG, REG}}, \
2613 {"cc_reg_operand", {SUBREG, REG}}, \
2614 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2615 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2616 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2617 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2618 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2619 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2620 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2621 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2622 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2623 {"easy_fp_constant", {CONST_DOUBLE}}, \
2624 {"zero_fp_constant", {CONST_DOUBLE}}, \
2625 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2626 {"lwa_operand", {SUBREG, MEM, REG}}, \
2627 {"volatile_mem_operand", {MEM}}, \
2628 {"offsettable_mem_operand", {MEM}}, \
2629 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2630 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2631 {"non_add_cint_operand", {CONST_INT}}, \
2632 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2633 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2634 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2635 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2636 {"mask_operand", {CONST_INT}}, \
2637 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2638 {"rldic_operand", {CONST_INT, CONST_DOUBLE}}, \
2639 {"count_register_operand", {REG}}, \
2640 {"xer_operand", {REG}}, \
2641 {"call_operand", {SYMBOL_REF, REG}}, \
2642 {"current_file_function_operand", {SYMBOL_REF}}, \
2643 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2644 CONST_DOUBLE, SYMBOL_REF}}, \
2645 {"load_multiple_operation", {PARALLEL}}, \
2646 {"store_multiple_operation", {PARALLEL}}, \
2647 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2648 GT, LEU, LTU, GEU, GTU, \
2649 UNORDERED, ORDERED, \
2651 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2653 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2654 GT, LEU, LTU, GEU, GTU, \
2655 UNORDERED, ORDERED, \
2657 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2658 GT, LEU, LTU, GEU, GTU}}, \
2659 {"boolean_operator", {AND, IOR, XOR}}, \
2660 {"boolean_or_operator", {IOR, XOR}}, \
2661 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2663 /* uncomment for disabling the corresponding default options */
2664 /* #define MACHINE_no_sched_interblock */
2665 /* #define MACHINE_no_sched_speculative */
2666 /* #define MACHINE_no_sched_speculative_load */
2668 /* indicate that issue rate is defined for this machine
2669 (no need to use the default) */
2670 #define ISSUE_RATE get_issue_rate ()
2672 /* General flags. */
2673 extern int flag_pic;
2674 extern int optimize;
2675 extern int flag_expensive_optimizations;
2676 extern int frame_pointer_needed;
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