1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2012 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* Definitions for the object file format. These are set at
36 #define OBJECT_XCOFF 1
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
51 #define TARGET_AIX_OS 0
54 /* Control whether function entry points use a "dot" symbol when
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
67 #define PPC405_ERRATUM77 0
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
74 #ifdef HAVE_AS_POPCNTB
75 #define ASM_CPU_POWER5_SPEC "-mpower5"
77 #define ASM_CPU_POWER5_SPEC "-mpower4"
81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
86 #ifdef HAVE_AS_POPCNTD
87 #define ASM_CPU_POWER7_SPEC "-mpower7"
89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
93 #define ASM_CPU_476_SPEC "-m476"
95 #define ASM_CPU_476_SPEC "-mpower4"
98 /* Common ASM definitions used by ASM_SPEC among the various targets for
99 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
100 provide the default assembler options if the user uses -mcpu=native, so if
101 you make changes here, make them also there. */
102 #define ASM_CPU_SPEC \
104 %{mpowerpc64*: -mppc64} \
105 %{!mpowerpc64*: %(asm_default)}} \
106 %{mcpu=native: %(asm_cpu_native)} \
107 %{mcpu=cell: -mcell} \
108 %{mcpu=power3: -mppc64} \
109 %{mcpu=power4: -mpower4} \
110 %{mcpu=power5: %(asm_cpu_power5)} \
111 %{mcpu=power5+: %(asm_cpu_power5)} \
112 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
113 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
114 %{mcpu=power7: %(asm_cpu_power7)} \
116 %{mcpu=powerpc: -mppc} \
117 %{mcpu=rs64a: -mppc64} \
121 %{mcpu=405fp: -m405} \
123 %{mcpu=440fp: -m440} \
125 %{mcpu=464fp: -m440} \
126 %{mcpu=476: %(asm_cpu_476)} \
127 %{mcpu=476fp: %(asm_cpu_476)} \
132 %{mcpu=603e: -mppc} \
133 %{mcpu=ec603e: -mppc} \
135 %{mcpu=604e: -mppc} \
136 %{mcpu=620: -mppc64} \
137 %{mcpu=630: -mppc64} \
141 %{mcpu=7400: -mppc -maltivec} \
142 %{mcpu=7450: -mppc -maltivec} \
143 %{mcpu=G4: -mppc -maltivec} \
148 %{mcpu=970: -mpower4 -maltivec} \
149 %{mcpu=G5: -mpower4 -maltivec} \
150 %{mcpu=8540: -me500} \
151 %{mcpu=8548: -me500} \
152 %{mcpu=e300c2: -me300} \
153 %{mcpu=e300c3: -me300} \
154 %{mcpu=e500mc: -me500mc} \
155 %{mcpu=e500mc64: -me500mc64} \
156 %{mcpu=e5500: -me5500} \
157 %{mcpu=e6500: -me6500} \
158 %{maltivec: -maltivec} \
159 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
162 #define CPP_DEFAULT_SPEC ""
164 #define ASM_DEFAULT_SPEC ""
166 /* This macro defines names of additional specifications to put in the specs
167 that can be used in various specifications like CC1_SPEC. Its definition
168 is an initializer with a subgrouping for each command option.
170 Each subgrouping contains a string constant, that defines the
171 specification name, and a string constant that used by the GCC driver
174 Do not define this macro if it does not need to do anything. */
176 #define SUBTARGET_EXTRA_SPECS
178 #define EXTRA_SPECS \
179 { "cpp_default", CPP_DEFAULT_SPEC }, \
180 { "asm_cpu", ASM_CPU_SPEC }, \
181 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
182 { "asm_default", ASM_DEFAULT_SPEC }, \
183 { "cc1_cpu", CC1_CPU_SPEC }, \
184 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
185 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
186 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
187 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
188 SUBTARGET_EXTRA_SPECS
190 /* -mcpu=native handling only makes sense with compiler running on
191 an PowerPC chip. If changing this condition, also change
192 the condition in driver-rs6000.c. */
193 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
194 /* In driver-rs6000.c. */
195 extern const char *host_detect_local_cpu (int argc, const char **argv);
196 #define EXTRA_SPEC_FUNCTIONS \
197 { "local_cpu_detect", host_detect_local_cpu },
198 #define HAVE_LOCAL_CPU_DETECT
199 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
202 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
206 #ifdef HAVE_LOCAL_CPU_DETECT
207 #define CC1_CPU_SPEC \
208 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
209 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
211 #define CC1_CPU_SPEC ""
215 /* Architecture type. */
217 /* Define TARGET_MFCRF if the target assembler does not support the
218 optional field operand for mfcr. */
220 #ifndef HAVE_AS_MFCRF
222 #define TARGET_MFCRF 0
225 /* Define TARGET_POPCNTB if the target assembler does not support the
226 popcount byte instruction. */
228 #ifndef HAVE_AS_POPCNTB
229 #undef TARGET_POPCNTB
230 #define TARGET_POPCNTB 0
233 /* Define TARGET_FPRND if the target assembler does not support the
234 fp rounding instructions. */
236 #ifndef HAVE_AS_FPRND
238 #define TARGET_FPRND 0
241 /* Define TARGET_CMPB if the target assembler does not support the
246 #define TARGET_CMPB 0
249 /* Define TARGET_MFPGPR if the target assembler does not support the
250 mffpr and mftgpr instructions. */
252 #ifndef HAVE_AS_MFPGPR
254 #define TARGET_MFPGPR 0
257 /* Define TARGET_DFP if the target assembler does not support decimal
258 floating point instructions. */
264 /* Define TARGET_POPCNTD if the target assembler does not support the
265 popcount word and double word instructions. */
267 #ifndef HAVE_AS_POPCNTD
268 #undef TARGET_POPCNTD
269 #define TARGET_POPCNTD 0
272 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
273 not, generate the lwsync code as an integer constant. */
274 #ifdef HAVE_AS_LWSYNC
275 #define TARGET_LWSYNC_INSTRUCTION 1
277 #define TARGET_LWSYNC_INSTRUCTION 0
280 /* Define TARGET_TLS_MARKERS if the target assembler does not support
281 arg markers for __tls_get_addr calls. */
282 #ifndef HAVE_AS_TLS_MARKERS
283 #undef TARGET_TLS_MARKERS
284 #define TARGET_TLS_MARKERS 0
286 #define TARGET_TLS_MARKERS tls_markers
289 #ifndef TARGET_SECURE_PLT
290 #define TARGET_SECURE_PLT 0
293 #ifndef TARGET_CMODEL
294 #define TARGET_CMODEL CMODEL_SMALL
297 #define TARGET_32BIT (! TARGET_64BIT)
300 #define HAVE_AS_TLS 0
303 #ifndef TARGET_LINK_STACK
304 #define TARGET_LINK_STACK 0
307 #ifndef SET_TARGET_LINK_STACK
308 #define SET_TARGET_LINK_STACK(X) do { } while (0)
311 /* Return 1 for a symbol ref for a thread-local storage symbol. */
312 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
313 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
316 /* For libgcc2 we make sure this is a compile time constant */
317 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
318 #undef TARGET_POWERPC64
319 #define TARGET_POWERPC64 1
321 #undef TARGET_POWERPC64
322 #define TARGET_POWERPC64 0
325 /* The option machinery will define this. */
328 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
330 /* FPU operations supported.
331 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
332 also test TARGET_HARD_FLOAT. */
333 #define TARGET_SINGLE_FLOAT 1
334 #define TARGET_DOUBLE_FLOAT 1
335 #define TARGET_SINGLE_FPU 0
336 #define TARGET_SIMPLE_FPU 0
337 #define TARGET_XILINX_FPU 0
339 /* Recast the processor type to the cpu attribute. */
340 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
342 /* Define generic processor types based upon current deployment. */
343 #define PROCESSOR_COMMON PROCESSOR_PPC601
344 #define PROCESSOR_POWERPC PROCESSOR_PPC604
345 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
347 /* Define the default processor. This is overridden by other tm.h files. */
348 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
349 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
352 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
353 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
354 #define MASK_DEBUG_REG 0x04 /* debug register handling */
355 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
356 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
357 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
358 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
359 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
364 | MASK_DEBUG_TARGET \
365 | MASK_DEBUG_BUILTIN)
367 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
368 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
369 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
370 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
371 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
372 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
373 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
375 extern enum rs6000_vector rs6000_vector_unit[];
377 #define VECTOR_UNIT_NONE_P(MODE) \
378 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
380 #define VECTOR_UNIT_VSX_P(MODE) \
381 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
383 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
384 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
386 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
387 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
388 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
390 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
391 same unit as the vector unit we are using, but we may want to migrate to
392 using VSX style loads even for types handled by altivec. */
393 extern enum rs6000_vector rs6000_vector_mem[];
395 #define VECTOR_MEM_NONE_P(MODE) \
396 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
398 #define VECTOR_MEM_VSX_P(MODE) \
399 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
401 #define VECTOR_MEM_ALTIVEC_P(MODE) \
402 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
404 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
405 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
406 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
408 /* Return the alignment of a given vector type, which is set based on the
409 vector unit use. VSX for instance can load 32 or 64 bit aligned words
410 without problems, while Altivec requires 128-bit aligned vectors. */
411 extern int rs6000_vector_align[];
413 #define VECTOR_ALIGN(MODE) \
414 ((rs6000_vector_align[(MODE)] != 0) \
415 ? rs6000_vector_align[(MODE)] \
416 : (int)GET_MODE_BITSIZE ((MODE)))
418 /* Alignment options for fields in structures for sub-targets following
420 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
421 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
423 Override the macro definitions when compiling libobjc to avoid undefined
424 reference to rs6000_alignment_flags due to library's use of GCC alignment
425 macros which use the macros below. */
427 #ifndef IN_TARGET_LIBS
428 #define MASK_ALIGN_POWER 0x00000000
429 #define MASK_ALIGN_NATURAL 0x00000001
430 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
432 #define TARGET_ALIGN_NATURAL 0
435 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
436 #define TARGET_IEEEQUAD rs6000_ieeequad
437 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
438 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
440 #define TARGET_SPE_ABI 0
442 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
443 #define TARGET_FPRS 1
444 #define TARGET_E500_SINGLE 0
445 #define TARGET_E500_DOUBLE 0
446 #define CHECK_E500_OPTIONS do { } while (0)
448 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
449 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
451 #define TARGET_FCFID (TARGET_POWERPC64 \
452 || TARGET_PPC_GPOPT /* 970/power4 */ \
453 || TARGET_POPCNTB /* ISA 2.02 */ \
454 || TARGET_CMPB /* ISA 2.05 */ \
455 || TARGET_POPCNTD /* ISA 2.06 */ \
456 || TARGET_XILINX_FPU)
458 #define TARGET_FCTIDZ TARGET_FCFID
459 #define TARGET_STFIWX TARGET_PPC_GFXOPT
460 #define TARGET_LFIWAX TARGET_CMPB
461 #define TARGET_LFIWZX TARGET_POPCNTD
462 #define TARGET_FCFIDS TARGET_POPCNTD
463 #define TARGET_FCFIDU TARGET_POPCNTD
464 #define TARGET_FCFIDUS TARGET_POPCNTD
465 #define TARGET_FCTIDUZ TARGET_POPCNTD
466 #define TARGET_FCTIWUZ TARGET_POPCNTD
468 /* For power systems, we want to enable Altivec and VSX builtins even if the
469 user did not use -maltivec or -mvsx to allow the builtins to be used inside
470 of #pragma GCC target or the target attribute to change the code level for a
471 given system. The SPE and Paired builtins are only enabled if you configure
472 the compiler for those builtins, and those machines don't support altivec or
475 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
476 && ((TARGET_POWERPC64 \
477 || TARGET_PPC_GPOPT /* 970/power4 */ \
478 || TARGET_POPCNTB /* ISA 2.02 */ \
479 || TARGET_CMPB /* ISA 2.05 */ \
480 || TARGET_POPCNTD /* ISA 2.06 */ \
484 /* E500 cores only support plain "sync", not lwsync. */
485 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
486 || rs6000_cpu == PROCESSOR_PPC8548)
489 /* Which machine supports the various reciprocal estimate instructions. */
490 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
491 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
493 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
494 && TARGET_DOUBLE_FLOAT \
495 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
497 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
498 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
500 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
501 && TARGET_DOUBLE_FLOAT \
502 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
504 /* Whether the various reciprocal divide/square root estimate instructions
505 exist, and whether we should automatically generate code for the instruction
507 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
508 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
509 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
510 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
512 extern unsigned char rs6000_recip_bits[];
514 #define RS6000_RECIP_HAVE_RE_P(MODE) \
515 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
517 #define RS6000_RECIP_AUTO_RE_P(MODE) \
518 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
520 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
521 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
523 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
524 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
526 #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
527 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
529 /* The default CPU for TARGET_OPTION_OVERRIDE. */
530 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
533 #define REGISTER_TARGET_PRAGMAS() do { \
534 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
535 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
536 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
537 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
540 /* Target #defines. */
541 #define TARGET_CPU_CPP_BUILTINS() \
542 rs6000_cpu_cpp_builtins (pfile)
544 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
545 we're compiling for. Some configurations may need to override it. */
546 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
549 if (BYTES_BIG_ENDIAN) \
551 builtin_define ("__BIG_ENDIAN__"); \
552 builtin_define ("_BIG_ENDIAN"); \
553 builtin_assert ("machine=bigendian"); \
557 builtin_define ("__LITTLE_ENDIAN__"); \
558 builtin_define ("_LITTLE_ENDIAN"); \
559 builtin_assert ("machine=littleendian"); \
564 /* Target machine storage layout. */
566 /* Define this macro if it is advisable to hold scalars in registers
567 in a wider mode than that declared by the program. In such cases,
568 the value is constrained to be within the bounds of the declared
569 type, but kept valid in the wider mode. The signedness of the
570 extension may differ from that of the type. */
572 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
573 if (GET_MODE_CLASS (MODE) == MODE_INT \
574 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
575 (MODE) = TARGET_32BIT ? SImode : DImode;
577 /* Define this if most significant bit is lowest numbered
578 in instructions that operate on numbered bit-fields. */
579 /* That is true on RS/6000. */
580 #define BITS_BIG_ENDIAN 1
582 /* Define this if most significant byte of a word is the lowest numbered. */
583 /* That is true on RS/6000. */
584 #define BYTES_BIG_ENDIAN 1
586 /* Define this if most significant word of a multiword number is lowest
589 For RS/6000 we can decide arbitrarily since there are no machine
590 instructions for them. Might as well be consistent with bits and bytes. */
591 #define WORDS_BIG_ENDIAN 1
593 #define MAX_BITS_PER_WORD 64
595 /* Width of a word, in units (bytes). */
596 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
598 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
600 #define MIN_UNITS_PER_WORD 4
602 #define UNITS_PER_FP_WORD 8
603 #define UNITS_PER_ALTIVEC_WORD 16
604 #define UNITS_PER_VSX_WORD 16
605 #define UNITS_PER_SPE_WORD 8
606 #define UNITS_PER_PAIRED_WORD 8
608 /* Type used for ptrdiff_t, as a string used in a declaration. */
609 #define PTRDIFF_TYPE "int"
611 /* Type used for size_t, as a string used in a declaration. */
612 #define SIZE_TYPE "long unsigned int"
614 /* Type used for wchar_t, as a string used in a declaration. */
615 #define WCHAR_TYPE "short unsigned int"
617 /* Width of wchar_t in bits. */
618 #define WCHAR_TYPE_SIZE 16
620 /* A C expression for the size in bits of the type `short' on the
621 target machine. If you don't define this, the default is half a
622 word. (If this would be less than one storage unit, it is
623 rounded up to one unit.) */
624 #define SHORT_TYPE_SIZE 16
626 /* A C expression for the size in bits of the type `int' on the
627 target machine. If you don't define this, the default is one
629 #define INT_TYPE_SIZE 32
631 /* A C expression for the size in bits of the type `long' on the
632 target machine. If you don't define this, the default is one
634 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
636 /* A C expression for the size in bits of the type `long long' on the
637 target machine. If you don't define this, the default is two
639 #define LONG_LONG_TYPE_SIZE 64
641 /* A C expression for the size in bits of the type `float' on the
642 target machine. If you don't define this, the default is one
644 #define FLOAT_TYPE_SIZE 32
646 /* A C expression for the size in bits of the type `double' on the
647 target machine. If you don't define this, the default is two
649 #define DOUBLE_TYPE_SIZE 64
651 /* A C expression for the size in bits of the type `long double' on
652 the target machine. If you don't define this, the default is two
654 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
656 /* Define this to set long double type size to use in libgcc2.c, which can
657 not depend on target_flags. */
658 #ifdef __LONG_DOUBLE_128__
659 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
661 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
664 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
665 #define WIDEST_HARDWARE_FP_SIZE 64
667 /* Width in bits of a pointer.
668 See also the macro `Pmode' defined below. */
669 extern unsigned rs6000_pointer_size;
670 #define POINTER_SIZE rs6000_pointer_size
672 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
673 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
675 /* Boundary (in *bits*) on which stack pointer should be aligned. */
676 #define STACK_BOUNDARY \
677 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
680 /* Allocation boundary (in *bits*) for the code of a function. */
681 #define FUNCTION_BOUNDARY 32
683 /* No data type wants to be aligned rounder than this. */
684 #define BIGGEST_ALIGNMENT 128
686 /* A C expression to compute the alignment for a variables in the
687 local store. TYPE is the data type, and ALIGN is the alignment
688 that the object would ordinarily have. */
689 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
690 DATA_ALIGNMENT (TYPE, ALIGN)
692 /* Alignment of field after `int : 0' in a structure. */
693 #define EMPTY_FIELD_BOUNDARY 32
695 /* Every structure's size must be a multiple of this. */
696 #define STRUCTURE_SIZE_BOUNDARY 8
698 /* Return 1 if a structure or array containing FIELD should be
699 accessed using `BLKMODE'.
701 For the SPE, simd types are V2SI, and gcc can be tempted to put the
702 entire thing in a DI and use subregs to access the internals.
703 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
704 back-end. Because a single GPR can hold a V2SI, but not a DI, the
705 best thing to do is set structs to BLKmode and avoid Severe Tire
708 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
709 fit into 1, whereas DI still needs two. */
710 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
711 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
712 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
714 /* A bit-field declared as `int' forces `int' alignment for the struct. */
715 #define PCC_BITFIELD_TYPE_MATTERS 1
717 /* Make strings word-aligned so strcpy from constants will be faster.
718 Make vector constants quadword aligned. */
719 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
720 (TREE_CODE (EXP) == STRING_CST \
721 && (STRICT_ALIGNMENT || !optimize_size) \
722 && (ALIGN) < BITS_PER_WORD \
726 /* Make arrays of chars word-aligned for the same reasons.
727 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
729 #define DATA_ALIGNMENT(TYPE, ALIGN) \
730 (TREE_CODE (TYPE) == VECTOR_TYPE \
731 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
732 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
734 : ((TARGET_E500_DOUBLE \
735 && TREE_CODE (TYPE) == REAL_TYPE \
736 && TYPE_MODE (TYPE) == DFmode) \
738 : (TREE_CODE (TYPE) == ARRAY_TYPE \
739 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
740 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
742 /* Nonzero if move instructions will actually fail to work
743 when given unaligned data. */
744 #define STRICT_ALIGNMENT 0
746 /* Define this macro to be the value 1 if unaligned accesses have a cost
747 many times greater than aligned accesses, for example if they are
748 emulated in a trap handler. */
749 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
750 memory instructions trap on unaligned accesses; VSX memory instructions are
751 aligned to 4 or 8 bytes. */
752 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
754 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
755 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \
757 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
760 /* Standard register usage. */
762 /* Number of actual hardware registers.
763 The hardware registers are assigned numbers for the compiler
764 from 0 to just below FIRST_PSEUDO_REGISTER.
765 All registers that the compiler knows about must be given numbers,
766 even those that are not normally considered general registers.
768 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
769 a count register, a link register, and 8 condition register fields,
770 which we view here as separate registers. AltiVec adds 32 vector
771 registers and a VRsave register.
773 In addition, the difference between the frame and argument pointers is
774 a function of the number of registers saved, so we need to have a
775 register for AP that will later be eliminated in favor of SP or FP.
776 This is a normal register, but it is fixed.
778 We also create a pseudo register for float/int conversions, that will
779 really represent the memory location used. It is represented here as
780 a register, in order to work around problems in allocating stack storage
783 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
784 pointer, which is eventually eliminated in favor of SP or FP. */
786 #define FIRST_PSEUDO_REGISTER 114
788 /* This must be included for pre gcc 3.0 glibc compatibility. */
789 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
791 /* Add 32 dwarf columns for synthetic SPE registers. */
792 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
794 /* The SPE has an additional 32 synthetic registers, with DWARF debug
795 info numbering for these registers starting at 1200. While eh_frame
796 register numbering need not be the same as the debug info numbering,
797 we choose to number these regs for eh_frame at 1200 too. This allows
798 future versions of the rs6000 backend to add hard registers and
799 continue to use the gcc hard register numbering for eh_frame. If the
800 extra SPE registers in eh_frame were numbered starting from the
801 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
802 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
803 avoid invalidating older SPE eh_frame info.
805 We must map them here to avoid huge unwinder tables mostly consisting
807 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
808 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
810 /* Use standard DWARF numbering for DWARF debugging information. */
811 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
813 /* Use gcc hard register numbering for eh_frame. */
814 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
816 /* Map register numbers held in the call frame info that gcc has
817 collected using DWARF_FRAME_REGNUM to those that should be output in
818 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
819 for .eh_frame, but use the numbers mandated by the various ABIs for
820 .debug_frame. rs6000_emit_prologue has translated any combination of
821 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
822 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
823 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
824 ((FOR_EH) ? (REGNO) \
825 : (REGNO) == CR2_REGNO ? 64 \
826 : DBX_REGISTER_NUMBER (REGNO))
828 /* 1 for registers that have pervasive standard uses
829 and are not available for the register allocator.
831 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
832 as a local register; for all other OS's r2 is the TOC pointer.
834 cr5 is not supposed to be used.
836 On System V implementations, r13 is fixed and not available for use. */
838 #define FIXED_REGISTERS \
839 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
841 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
842 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
843 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
844 /* AltiVec registers. */ \
845 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
851 /* 1 for registers not available across function calls.
852 These must include the FIXED_REGISTERS and also any
853 registers that can be used without being saved.
854 The latter must include the registers where values are returned
855 and the register where structure-value addresses are passed.
856 Aside from that, you can include as many other registers as you like. */
858 #define CALL_USED_REGISTERS \
859 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
861 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
864 /* AltiVec registers. */ \
865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
872 the entire set of `FIXED_REGISTERS' be included.
873 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
874 This macro is optional. If not specified, it defaults to the value
875 of `CALL_USED_REGISTERS'. */
877 #define CALL_REALLY_USED_REGISTERS \
878 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
880 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
882 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
883 /* AltiVec registers. */ \
884 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
890 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
892 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
893 #define FIRST_SAVED_FP_REGNO (14+32)
894 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
896 /* List the order in which to allocate registers. Each register must be
897 listed once, even those in FIXED_REGISTERS.
899 We allocate in the following order:
900 fp0 (not saved or used for anything)
901 fp13 - fp2 (not saved; incoming fp arg registers)
902 fp1 (not saved; return value)
903 fp31 - fp14 (saved; order given to save least number)
904 cr7, cr6 (not saved or special)
905 cr1 (not saved, but used for FP operations)
906 cr0 (not saved, but used for arithmetic operations)
907 cr4, cr3, cr2 (saved)
908 r9 (not saved; best for TImode)
909 r10, r8-r4 (not saved; highest first for less conflict with params)
910 r3 (not saved; return value register)
911 r11 (not saved; later alloc to help shrink-wrap)
912 r0 (not saved; cannot be base reg)
913 r31 - r13 (saved; order given to save least number)
914 r12 (not saved; if used for DImode or DFmode would use r13)
915 ctr (not saved; when we have the choice ctr is better)
917 cr5, r1, r2, ap, ca (fixed)
918 v0 - v1 (not saved or used for anything)
919 v13 - v3 (not saved; incoming vector arg registers)
920 v2 (not saved; incoming vector arg reg; return value)
921 v19 - v14 (not saved or used for anything)
922 v31 - v20 (saved; order given to save least number)
924 spe_acc, spefscr (fixed)
929 #define MAYBE_R2_AVAILABLE
930 #define MAYBE_R2_FIXED 2,
932 #define MAYBE_R2_AVAILABLE 2,
933 #define MAYBE_R2_FIXED
937 #define EARLY_R12 12,
944 #define REG_ALLOC_ORDER \
946 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
948 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
949 50, 49, 48, 47, 46, \
950 75, 74, 69, 68, 72, 71, 70, \
952 9, 10, 8, 7, 6, 5, 4, \
953 3, EARLY_R12 11, 0, \
954 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
955 18, 17, 16, 15, 14, 13, LATE_R12 \
957 73, 1, MAYBE_R2_FIXED 67, 76, \
958 /* AltiVec registers. */ \
960 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
962 96, 95, 94, 93, 92, 91, \
963 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
968 /* True if register is floating-point. */
969 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
971 /* True if register is a condition register. */
972 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
974 /* True if register is a condition register, but not cr0. */
975 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
977 /* True if register is an integer register. */
978 #define INT_REGNO_P(N) \
979 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
981 /* SPE SIMD registers are just the GPRs. */
982 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
984 /* PAIRED SIMD registers are just the FPRs. */
985 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
987 /* True if register is the CA register. */
988 #define CA_REGNO_P(N) ((N) == CA_REGNO)
990 /* True if register is an AltiVec register. */
991 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
993 /* True if register is a VSX register. */
994 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
996 /* Alternate name for any vector register supporting floating point, no matter
997 which instruction set(s) are available. */
998 #define VFLOAT_REGNO_P(N) \
999 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1001 /* Alternate name for any vector register supporting integer, no matter which
1002 instruction set(s) are available. */
1003 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1005 /* Alternate name for any vector register supporting logical operations, no
1006 matter which instruction set(s) are available. */
1007 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1009 /* Return number of consecutive hard regs needed starting at reg REGNO
1010 to hold something of mode MODE. */
1012 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1014 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1015 enough space to account for vectors in FP regs. */
1016 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1018 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1019 && FP_REGNO_P (REGNO) \
1021 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1023 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1024 (((TARGET_32BIT && TARGET_POWERPC64 \
1025 && (GET_MODE_SIZE (MODE) > 4) \
1026 && INT_REGNO_P (REGNO)) ? 1 : 0) \
1027 || (TARGET_VSX && FP_REGNO_P (REGNO) \
1028 && GET_MODE_SIZE (MODE) > 8))
1030 #define VSX_VECTOR_MODE(MODE) \
1031 ((MODE) == V4SFmode \
1032 || (MODE) == V2DFmode) \
1034 #define ALTIVEC_VECTOR_MODE(MODE) \
1035 ((MODE) == V16QImode \
1036 || (MODE) == V8HImode \
1037 || (MODE) == V4SFmode \
1038 || (MODE) == V4SImode)
1040 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1041 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1042 || (MODE) == V2DImode)
1044 #define SPE_VECTOR_MODE(MODE) \
1045 ((MODE) == V4HImode \
1046 || (MODE) == V2SFmode \
1047 || (MODE) == V1DImode \
1048 || (MODE) == V2SImode)
1050 #define PAIRED_VECTOR_MODE(MODE) \
1051 ((MODE) == V2SFmode)
1053 /* Value is TRUE if hard register REGNO can hold a value of
1054 machine-mode MODE. */
1055 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1056 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1058 /* Value is 1 if it is a good idea to tie two pseudo registers
1059 when one has mode MODE1 and one has mode MODE2.
1060 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1061 for any hard reg, then this must be 0 for correct output. */
1062 #define MODES_TIEABLE_P(MODE1, MODE2) \
1063 (SCALAR_FLOAT_MODE_P (MODE1) \
1064 ? SCALAR_FLOAT_MODE_P (MODE2) \
1065 : SCALAR_FLOAT_MODE_P (MODE2) \
1066 ? SCALAR_FLOAT_MODE_P (MODE1) \
1067 : GET_MODE_CLASS (MODE1) == MODE_CC \
1068 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1069 : GET_MODE_CLASS (MODE2) == MODE_CC \
1070 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1071 : SPE_VECTOR_MODE (MODE1) \
1072 ? SPE_VECTOR_MODE (MODE2) \
1073 : SPE_VECTOR_MODE (MODE2) \
1074 ? SPE_VECTOR_MODE (MODE1) \
1075 : ALTIVEC_VECTOR_MODE (MODE1) \
1076 ? ALTIVEC_VECTOR_MODE (MODE2) \
1077 : ALTIVEC_VECTOR_MODE (MODE2) \
1078 ? ALTIVEC_VECTOR_MODE (MODE1) \
1079 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1080 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1081 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1082 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1085 /* Post-reload, we can't use any new AltiVec registers, as we already
1086 emitted the vrsave mask. */
1088 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1089 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1091 /* Specify the cost of a branch insn; roughly the number of extra insns that
1092 should be added to avoid a branch.
1094 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1095 unscheduled conditional branch. */
1097 #define BRANCH_COST(speed_p, predictable_p) 3
1099 /* Override BRANCH_COST heuristic which empirically produces worse
1100 performance for removing short circuiting from the logical ops. */
1102 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1104 /* A fixed register used at epilogue generation to address SPE registers
1105 with negative offsets. The 64-bit load/store instructions on the SPE
1106 only take positive offsets (and small ones at that), so we need to
1107 reserve a register for consing up negative offsets. */
1109 #define FIXED_SCRATCH 0
1111 /* Specify the registers used for certain standard purposes.
1112 The values of these macros are register numbers. */
1114 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1115 /* #define PC_REGNUM */
1117 /* Register to use for pushing function arguments. */
1118 #define STACK_POINTER_REGNUM 1
1120 /* Base register for access to local variables of the function. */
1121 #define HARD_FRAME_POINTER_REGNUM 31
1123 /* Base register for access to local variables of the function. */
1124 #define FRAME_POINTER_REGNUM 113
1126 /* Base register for access to arguments of the function. */
1127 #define ARG_POINTER_REGNUM 67
1129 /* Place to put static chain when calling a function that requires it. */
1130 #define STATIC_CHAIN_REGNUM 11
1133 /* Define the classes of registers for register constraints in the
1134 machine description. Also define ranges of constants.
1136 One of the classes must always be named ALL_REGS and include all hard regs.
1137 If there is more than one class, another class must be named NO_REGS
1138 and contain no registers.
1140 The name GENERAL_REGS must be the name of a class (or an alias for
1141 another name such as ALL_REGS). This is the class of registers
1142 that is allowed by "g" or "r" in a register constraint.
1143 Also, registers outside this class are allocated only when
1144 instructions express preferences for them.
1146 The classes must be numbered in nondecreasing order; that is,
1147 a larger-numbered class must never be contained completely
1148 in a smaller-numbered class.
1150 For any two classes, it is very desirable that there be another
1151 class that represents their union. */
1153 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1154 condition registers, plus three special registers, CTR, and the link
1155 register. AltiVec adds a vector register class. VSX registers overlap the
1156 FPR registers and the Altivec registers.
1158 However, r0 is special in that it cannot be used as a base register.
1159 So make a class for registers valid as base registers.
1161 Also, cr0 is the only condition code register that can be used in
1162 arithmetic insns, so make a separate class for it. */
1190 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1192 /* Give names of register classes as strings for dump file. */
1194 #define REG_CLASS_NAMES \
1206 "NON_SPECIAL_REGS", \
1209 "LINK_OR_CTR_REGS", \
1211 "SPEC_OR_GEN_REGS", \
1219 /* Define which registers fit in which classes.
1220 This is an initializer for a vector of HARD_REG_SET
1221 of length N_REG_CLASSES. */
1223 #define REG_CLASS_CONTENTS \
1225 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1226 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1227 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1228 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1229 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1230 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
1231 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1232 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1234 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1235 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1236 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1237 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1238 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1239 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \
1240 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1241 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1242 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1243 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
1244 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
1245 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \
1248 /* The same information, inverted:
1249 Return the class number of the smallest class containing
1250 reg number REGNO. This could be a conditional expression
1251 or could index an array. */
1253 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1256 #define REGNO_REG_CLASS(REGNO) \
1257 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1258 rs6000_regno_regclass[(REGNO)])
1261 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1264 /* Register classes for various constraints that are based on the target
1266 enum r6000_reg_class_enum {
1267 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1268 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1269 RS6000_CONSTRAINT_v, /* Altivec registers */
1270 RS6000_CONSTRAINT_wa, /* Any VSX register */
1271 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1272 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1273 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1274 RS6000_CONSTRAINT_MAX
1277 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1279 /* The class value for index registers, and the one for base regs. */
1280 #define INDEX_REG_CLASS GENERAL_REGS
1281 #define BASE_REG_CLASS BASE_REGS
1283 /* Return whether a given register class can hold VSX objects. */
1284 #define VSX_REG_CLASS_P(CLASS) \
1285 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1287 /* Given an rtx X being reloaded into a reg required to be
1288 in class CLASS, return the class of reg to actually use.
1289 In general this is just CLASS; but on some machines
1290 in some cases it is preferable to use a more restrictive class.
1292 On the RS/6000, we have to return NO_REGS when we want to reload a
1293 floating-point CONST_DOUBLE to force it to be copied to memory.
1295 We also don't want to reload integer values into floating-point
1296 registers if we can at all help it. In fact, this can
1297 cause reload to die, if it tries to generate a reload of CTR
1298 into a FP register and discovers it doesn't have the memory location
1301 ??? Would it be a good idea to have reload do the converse, that is
1302 try to reload floating modes into FP registers if possible?
1305 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1306 rs6000_preferred_reload_class_ptr (X, CLASS)
1308 /* Return the register class of a scratch register needed to copy IN into
1309 or out of a register in CLASS in MODE. If it can be done directly,
1310 NO_REGS is returned. */
1312 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1313 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1315 /* If we are copying between FP or AltiVec registers and anything
1316 else, we need a memory location. The exception is when we are
1317 targeting ppc64 and the move to/from fpr to gpr instructions
1320 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1321 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1323 /* For cpus that cannot load/store SDmode values from the 64-bit
1324 FP registers without using a full 64-bit load/store, we need
1325 to allocate a full 64-bit stack slot for them. */
1327 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1328 rs6000_secondary_memory_needed_rtx (MODE)
1330 /* Return the maximum number of consecutive registers
1331 needed to represent mode MODE in a register of class CLASS.
1333 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1334 a single reg is enough for two words, unless we have VSX, where the FP
1335 registers can hold 128 bits. */
1336 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1338 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1340 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1341 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1343 /* Stack layout; function entry, exit and calling. */
1345 /* Define this if pushing a word on the stack
1346 makes the stack pointer a smaller address. */
1347 #define STACK_GROWS_DOWNWARD
1349 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1350 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1352 /* Define this to nonzero if the nominal address of the stack frame
1353 is at the high-address end of the local variables;
1354 that is, each additional local variable allocated
1355 goes at a more negative offset in the frame.
1357 On the RS/6000, we grow upwards, from the area after the outgoing
1359 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1361 /* Size of the outgoing register save area */
1362 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1363 || DEFAULT_ABI == ABI_DARWIN) \
1364 ? (TARGET_64BIT ? 64 : 32) \
1367 /* Size of the fixed area on the stack */
1368 #define RS6000_SAVE_AREA \
1369 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1370 << (TARGET_64BIT ? 1 : 0))
1372 /* MEM representing address to save the TOC register */
1373 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1374 plus_constant (Pmode, stack_pointer_rtx, \
1375 (TARGET_32BIT ? 20 : 40)))
1377 /* Align an address */
1378 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1380 /* Offset within stack frame to start allocating local variables at.
1381 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1382 first local allocated. Otherwise, it is the offset to the BEGINNING
1383 of the first local allocated.
1385 On the RS/6000, the frame pointer is the same as the stack pointer,
1386 except for dynamic allocations. So we start after the fixed area and
1387 outgoing parameter area. */
1389 #define STARTING_FRAME_OFFSET \
1390 (FRAME_GROWS_DOWNWARD \
1392 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1393 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1394 + RS6000_SAVE_AREA))
1396 /* Offset from the stack pointer register to an item dynamically
1397 allocated on the stack, e.g., by `alloca'.
1399 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1400 length of the outgoing arguments. The default is correct for most
1401 machines. See `function.c' for details. */
1402 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1403 (RS6000_ALIGN (crtl->outgoing_args_size, \
1404 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1405 + (STACK_POINTER_OFFSET))
1407 /* If we generate an insn to push BYTES bytes,
1408 this says how many the stack pointer really advances by.
1409 On RS/6000, don't define this because there are no push insns. */
1410 /* #define PUSH_ROUNDING(BYTES) */
1412 /* Offset of first parameter from the argument pointer register value.
1413 On the RS/6000, we define the argument pointer to the start of the fixed
1415 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1417 /* Offset from the argument pointer register value to the top of
1418 stack. This is different from FIRST_PARM_OFFSET because of the
1419 register save area. */
1420 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1422 /* Define this if stack space is still allocated for a parameter passed
1423 in a register. The value is the number of bytes allocated to this
1425 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1427 /* Define this if the above stack space is to be considered part of the
1428 space allocated by the caller. */
1429 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1431 /* This is the difference between the logical top of stack and the actual sp.
1433 For the RS/6000, sp points past the fixed area. */
1434 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1436 /* Define this if the maximum size of all the outgoing args is to be
1437 accumulated and pushed during the prologue. The amount can be
1438 found in the variable crtl->outgoing_args_size. */
1439 #define ACCUMULATE_OUTGOING_ARGS 1
1441 /* Define how to find the value returned by a library function
1442 assuming the value has mode MODE. */
1444 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1446 /* DRAFT_V4_STRUCT_RET defaults off. */
1447 #define DRAFT_V4_STRUCT_RET 0
1449 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1450 #define DEFAULT_PCC_STRUCT_RETURN 0
1452 /* Mode of stack savearea.
1453 FUNCTION is VOIDmode because calling convention maintains SP.
1454 BLOCK needs Pmode for SP.
1455 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1456 #define STACK_SAVEAREA_MODE(LEVEL) \
1457 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1458 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1460 /* Minimum and maximum general purpose registers used to hold arguments. */
1461 #define GP_ARG_MIN_REG 3
1462 #define GP_ARG_MAX_REG 10
1463 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1465 /* Minimum and maximum floating point registers used to hold arguments. */
1466 #define FP_ARG_MIN_REG 33
1467 #define FP_ARG_AIX_MAX_REG 45
1468 #define FP_ARG_V4_MAX_REG 40
1469 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1470 || DEFAULT_ABI == ABI_DARWIN) \
1471 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1472 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1474 /* Minimum and maximum AltiVec registers used to hold arguments. */
1475 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1476 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1477 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1479 /* Return registers */
1480 #define GP_ARG_RETURN GP_ARG_MIN_REG
1481 #define FP_ARG_RETURN FP_ARG_MIN_REG
1482 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1484 /* Flags for the call/call_value rtl operations set up by function_arg */
1485 #define CALL_NORMAL 0x00000000 /* no special processing */
1486 /* Bits in 0x00000001 are unused. */
1487 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1488 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1489 #define CALL_LONG 0x00000008 /* always call indirect */
1490 #define CALL_LIBCALL 0x00000010 /* libcall */
1492 /* We don't have prologue and epilogue functions to save/restore
1493 everything for most ABIs. */
1494 #define WORLD_SAVE_P(INFO) 0
1496 /* 1 if N is a possible register number for a function value
1497 as seen by the caller.
1499 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1500 #define FUNCTION_VALUE_REGNO_P(N) \
1501 ((N) == GP_ARG_RETURN \
1502 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1503 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1505 /* 1 if N is a possible register number for function argument passing.
1506 On RS/6000, these are r3-r10 and fp1-fp13.
1507 On AltiVec, v2 - v13 are used for passing vectors. */
1508 #define FUNCTION_ARG_REGNO_P(N) \
1509 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1510 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1511 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1512 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1513 && TARGET_HARD_FLOAT && TARGET_FPRS))
1515 /* Define a data type for recording info about an argument list
1516 during the scan of that argument list. This data type should
1517 hold all necessary information about the function itself
1518 and about the args processed so far, enough to enable macros
1519 such as FUNCTION_ARG to determine where the next arg should go.
1521 On the RS/6000, this is a structure. The first element is the number of
1522 total argument words, the second is used to store the next
1523 floating-point register number, and the third says how many more args we
1524 have prototype types for.
1526 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1527 the next available GP register, `fregno' is the next available FP
1528 register, and `words' is the number of words used on the stack.
1530 The varargs/stdarg support requires that this structure's size
1531 be a multiple of sizeof(int). */
1533 typedef struct rs6000_args
1535 int words; /* # words used for passing GP registers */
1536 int fregno; /* next available FP register */
1537 int vregno; /* next available AltiVec register */
1538 int nargs_prototype; /* # args left in the current prototype */
1539 int prototype; /* Whether a prototype was defined */
1540 int stdarg; /* Whether function is a stdarg function. */
1541 int call_cookie; /* Do special things for this call */
1542 int sysv_gregno; /* next available GP register */
1543 int intoffset; /* running offset in struct (darwin64) */
1544 int use_stack; /* any part of struct on stack (darwin64) */
1545 int floats_in_gpr; /* count of SFmode floats taking up
1546 GPR space (darwin64) */
1547 int named; /* false for varargs params */
1548 int escapes; /* if function visible outside tu */
1551 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1552 for a call to a function whose data type is FNTYPE.
1553 For a library call, FNTYPE is 0. */
1555 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1556 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1557 N_NAMED_ARGS, FNDECL, VOIDmode)
1559 /* Similar, but when scanning the definition of a procedure. We always
1560 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1562 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1563 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1564 1000, current_function_decl, VOIDmode)
1566 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1568 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1569 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1572 /* If defined, a C expression which determines whether, and in which
1573 direction, to pad out an argument with extra space. The value
1574 should be of type `enum direction': either `upward' to pad above
1575 the argument, `downward' to pad below, or `none' to inhibit
1578 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1580 #define PAD_VARARGS_DOWN \
1581 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1583 /* Output assembler code to FILE to increment profiler label # LABELNO
1584 for profiling a function entry. */
1586 #define FUNCTION_PROFILER(FILE, LABELNO) \
1587 output_function_profiler ((FILE), (LABELNO));
1589 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1590 the stack pointer does not matter. No definition is equivalent to
1593 On the RS/6000, this is nonzero because we can restore the stack from
1594 its backpointer, which we maintain. */
1595 #define EXIT_IGNORE_STACK 1
1597 /* Define this macro as a C expression that is nonzero for registers
1598 that are used by the epilogue or the return' pattern. The stack
1599 and frame pointer registers are already be assumed to be used as
1602 #define EPILOGUE_USES(REGNO) \
1603 ((reload_completed && (REGNO) == LR_REGNO) \
1604 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1605 || (crtl->calls_eh_return \
1610 /* Length in units of the trampoline for entering a nested function. */
1612 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1614 /* Definitions for __builtin_return_address and __builtin_frame_address.
1615 __builtin_return_address (0) should give link register (65), enable
1617 /* This should be uncommented, so that the link register is used, but
1618 currently this would result in unmatched insns and spilling fixed
1619 registers so we'll leave it for another day. When these problems are
1620 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1622 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1624 /* Number of bytes into the frame return addresses can be found. See
1625 rs6000_stack_info in rs6000.c for more information on how the different
1626 abi's store the return address. */
1627 #define RETURN_ADDRESS_OFFSET \
1628 ((DEFAULT_ABI == ABI_AIX \
1629 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1630 (DEFAULT_ABI == ABI_V4) ? 4 : \
1631 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1633 /* The current return address is in link register (65). The return address
1634 of anything farther back is accessed normally at an offset of 8 from the
1636 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1637 (rs6000_return_addr (COUNT, FRAME))
1640 /* Definitions for register eliminations.
1642 We have two registers that can be eliminated on the RS/6000. First, the
1643 frame pointer register can often be eliminated in favor of the stack
1644 pointer register. Secondly, the argument pointer register can always be
1645 eliminated; it is replaced with either the stack or frame pointer.
1647 In addition, we use the elimination mechanism to see if r30 is needed
1648 Initially we assume that it isn't. If it is, we spill it. This is done
1649 by making it an eliminable register. We replace it with itself so that
1650 if it isn't needed, then existing uses won't be modified. */
1652 /* This is an array of structures. Each structure initializes one pair
1653 of eliminable registers. The "from" register number is given first,
1654 followed by "to". Eliminations of the same "from" register are listed
1655 in order of preference. */
1656 #define ELIMINABLE_REGS \
1657 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1658 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1659 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1660 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1661 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1662 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1664 /* Define the offset between two registers, one to be eliminated, and the other
1665 its replacement, at the start of a routine. */
1666 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1667 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1669 /* Addressing modes, and classification of registers for them. */
1671 #define HAVE_PRE_DECREMENT 1
1672 #define HAVE_PRE_INCREMENT 1
1673 #define HAVE_PRE_MODIFY_DISP 1
1674 #define HAVE_PRE_MODIFY_REG 1
1676 /* Macros to check register numbers against specific register classes. */
1678 /* These assume that REGNO is a hard or pseudo reg number.
1679 They give nonzero only if REGNO is a hard reg of the suitable class
1680 or a pseudo reg currently allocated to a suitable hard reg.
1681 Since they use reg_renumber, they are safe only once reg_renumber
1682 has been allocated, which happens in local-alloc.c. */
1684 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1685 ((REGNO) < FIRST_PSEUDO_REGISTER \
1686 ? (REGNO) <= 31 || (REGNO) == 67 \
1687 || (REGNO) == FRAME_POINTER_REGNUM \
1688 : (reg_renumber[REGNO] >= 0 \
1689 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1690 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1692 #define REGNO_OK_FOR_BASE_P(REGNO) \
1693 ((REGNO) < FIRST_PSEUDO_REGISTER \
1694 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1695 || (REGNO) == FRAME_POINTER_REGNUM \
1696 : (reg_renumber[REGNO] > 0 \
1697 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1698 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1700 /* Nonzero if X is a hard reg that can be used as an index
1701 or if it is a pseudo reg in the non-strict case. */
1702 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1703 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1704 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1706 /* Nonzero if X is a hard reg that can be used as a base reg
1707 or if it is a pseudo reg in the non-strict case. */
1708 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1709 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1710 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1713 /* Maximum number of registers that can appear in a valid memory address. */
1715 #define MAX_REGS_PER_ADDRESS 2
1717 /* Recognize any constant value that is a valid address. */
1719 #define CONSTANT_ADDRESS_P(X) \
1720 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1721 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1722 || GET_CODE (X) == HIGH)
1724 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1725 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1726 && EASY_VECTOR_15((n) >> 1) \
1729 #define EASY_VECTOR_MSB(n,mode) \
1730 (((unsigned HOST_WIDE_INT)n) == \
1731 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1734 /* Try a machine-dependent way of reloading an illegitimate address
1735 operand. If we find one, push the reload and jump to WIN. This
1736 macro is used in only one place: `find_reloads_address' in reload.c.
1738 Implemented on rs6000 by rs6000_legitimize_reload_address.
1739 Note that (X) is evaluated twice; this is safe in current usage. */
1741 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1744 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1745 (int)(TYPE), (IND_LEVELS), &win); \
1750 #define FIND_BASE_TERM rs6000_find_base_term
1752 /* The register number of the register used to address a table of
1753 static data addresses in memory. In some cases this register is
1754 defined by a processor's "application binary interface" (ABI).
1755 When this macro is defined, RTL is generated for this register
1756 once, as with the stack pointer and frame pointer registers. If
1757 this macro is not defined, it is up to the machine-dependent files
1758 to allocate such a register (if necessary). */
1760 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1761 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1763 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1765 /* Define this macro if the register defined by
1766 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1767 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1769 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1771 /* A C expression that is nonzero if X is a legitimate immediate
1772 operand on the target machine when generating position independent
1773 code. You can assume that X satisfies `CONSTANT_P', so you need
1774 not check this. You can also assume FLAG_PIC is true, so you need
1775 not check it either. You need not define this macro if all
1776 constants (including `SYMBOL_REF') can be immediate operands when
1777 generating position independent code. */
1779 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1781 /* Define this if some processing needs to be done immediately before
1782 emitting code for an insn. */
1784 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1785 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
1787 /* Specify the machine mode that this machine uses
1788 for the index in the tablejump instruction. */
1789 #define CASE_VECTOR_MODE SImode
1791 /* Define as C expression which evaluates to nonzero if the tablejump
1792 instruction expects the table to contain offsets from the address of the
1794 Do not define this if the table should contain absolute addresses. */
1795 #define CASE_VECTOR_PC_RELATIVE 1
1797 /* Define this as 1 if `char' should by default be signed; else as 0. */
1798 #define DEFAULT_SIGNED_CHAR 0
1800 /* An integer expression for the size in bits of the largest integer machine
1801 mode that should actually be used. */
1803 /* Allow pairs of registers to be used, which is the intent of the default. */
1804 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1806 /* Max number of bytes we can move from memory to memory
1807 in one reasonably fast instruction. */
1808 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1809 #define MAX_MOVE_MAX 8
1811 /* Nonzero if access to memory by bytes is no faster than for words.
1812 Also nonzero if doing byte operations (specifically shifts) in registers
1814 #define SLOW_BYTE_ACCESS 1
1816 /* Define if operations between registers always perform the operation
1817 on the full register even if a narrower mode is specified. */
1818 #define WORD_REGISTER_OPERATIONS
1820 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1821 will either zero-extend or sign-extend. The value of this macro should
1822 be the code that says which one of the two operations is implicitly
1823 done, UNKNOWN if none. */
1824 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1826 /* Define if loading short immediate values into registers sign extends. */
1827 #define SHORT_IMMEDIATES_SIGN_EXTEND
1829 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1830 is done just by pretending it is already truncated. */
1831 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1833 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1834 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1835 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1837 /* The CTZ patterns return -1 for input of zero. */
1838 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1840 /* Specify the machine mode that pointers have.
1841 After generation of rtl, the compiler makes no further distinction
1842 between pointers and any other objects of this machine mode. */
1843 extern unsigned rs6000_pmode;
1844 #define Pmode ((enum machine_mode)rs6000_pmode)
1846 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1847 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1849 /* Mode of a function address in a call instruction (for indexing purposes).
1850 Doesn't matter on RS/6000. */
1851 #define FUNCTION_MODE SImode
1853 /* Define this if addresses of constant functions
1854 shouldn't be put through pseudo regs where they can be cse'd.
1855 Desirable on machines where ordinary constants are expensive
1856 but a CALL with constant address is cheap. */
1857 #define NO_FUNCTION_CSE
1859 /* Define this to be nonzero if shift instructions ignore all but the low-order
1862 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1863 have been dropped from the PowerPC architecture. */
1864 #define SHIFT_COUNT_TRUNCATED 0
1866 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1867 should be adjusted to reflect any required changes. This macro is used when
1868 there is some systematic length adjustment required that would be difficult
1869 to express in the length attribute. */
1871 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1873 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1874 COMPARE, return the mode to be used for the comparison. For
1875 floating-point, CCFPmode should be used. CCUNSmode should be used
1876 for unsigned comparisons. CCEQmode should be used when we are
1877 doing an inequality comparison on the result of a
1878 comparison. CCmode should be used in all other cases. */
1880 #define SELECT_CC_MODE(OP,X,Y) \
1881 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1882 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1883 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1884 ? CCEQmode : CCmode))
1886 /* Can the condition code MODE be safely reversed? This is safe in
1887 all cases on this port, because at present it doesn't use the
1888 trapping FP comparisons (fcmpo). */
1889 #define REVERSIBLE_CC_MODE(MODE) 1
1891 /* Given a condition code and a mode, return the inverse condition. */
1892 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1895 /* Control the assembler format that we output. */
1897 /* A C string constant describing how to begin a comment in the target
1898 assembler language. The compiler assumes that the comment will end at
1899 the end of the line. */
1900 #define ASM_COMMENT_START " #"
1902 /* Flag to say the TOC is initialized */
1903 extern int toc_initialized;
1905 /* Macro to output a special constant pool entry. Go to WIN if we output
1906 it. Otherwise, it is written the usual way.
1908 On the RS/6000, toc entries are handled this way. */
1910 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1911 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1913 output_toc (FILE, X, LABELNO, MODE); \
1918 #ifdef HAVE_GAS_WEAK
1919 #define RS6000_WEAK 1
1921 #define RS6000_WEAK 0
1925 /* Used in lieu of ASM_WEAKEN_LABEL. */
1926 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1929 fputs ("\t.weak\t", (FILE)); \
1930 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1931 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1932 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1935 fputs ("[DS]", (FILE)); \
1936 fputs ("\n\t.weak\t.", (FILE)); \
1937 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1939 fputc ('\n', (FILE)); \
1942 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1943 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1944 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1946 fputs ("\t.set\t.", (FILE)); \
1947 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1948 fputs (",.", (FILE)); \
1949 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
1950 fputc ('\n', (FILE)); \
1957 #if HAVE_GAS_WEAKREF
1958 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1961 fputs ("\t.weakref\t", (FILE)); \
1962 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1963 fputs (", ", (FILE)); \
1964 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1965 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1966 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1968 fputs ("\n\t.weakref\t.", (FILE)); \
1969 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1970 fputs (", .", (FILE)); \
1971 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1973 fputc ('\n', (FILE)); \
1977 /* This implements the `alias' attribute. */
1978 #undef ASM_OUTPUT_DEF_FROM_DECLS
1979 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1982 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1983 const char *name = IDENTIFIER_POINTER (TARGET); \
1984 if (TREE_CODE (DECL) == FUNCTION_DECL \
1985 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1987 if (TREE_PUBLIC (DECL)) \
1989 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1991 fputs ("\t.globl\t.", FILE); \
1992 RS6000_OUTPUT_BASENAME (FILE, alias); \
1993 putc ('\n', FILE); \
1996 else if (TARGET_XCOFF) \
1998 fputs ("\t.lglobl\t.", FILE); \
1999 RS6000_OUTPUT_BASENAME (FILE, alias); \
2000 putc ('\n', FILE); \
2002 fputs ("\t.set\t.", FILE); \
2003 RS6000_OUTPUT_BASENAME (FILE, alias); \
2004 fputs (",.", FILE); \
2005 RS6000_OUTPUT_BASENAME (FILE, name); \
2006 fputc ('\n', FILE); \
2008 ASM_OUTPUT_DEF (FILE, alias, name); \
2012 #define TARGET_ASM_FILE_START rs6000_file_start
2014 /* Output to assembler file text saying following lines
2015 may contain character constants, extra white space, comments, etc. */
2017 #define ASM_APP_ON ""
2019 /* Output to assembler file text saying following lines
2020 no longer contain unusual constructs. */
2022 #define ASM_APP_OFF ""
2024 /* How to refer to registers in assembler output.
2025 This sequence is indexed by compiler's hard-register-number (see above). */
2027 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2029 #define REGISTER_NAMES \
2031 &rs6000_reg_names[ 0][0], /* r0 */ \
2032 &rs6000_reg_names[ 1][0], /* r1 */ \
2033 &rs6000_reg_names[ 2][0], /* r2 */ \
2034 &rs6000_reg_names[ 3][0], /* r3 */ \
2035 &rs6000_reg_names[ 4][0], /* r4 */ \
2036 &rs6000_reg_names[ 5][0], /* r5 */ \
2037 &rs6000_reg_names[ 6][0], /* r6 */ \
2038 &rs6000_reg_names[ 7][0], /* r7 */ \
2039 &rs6000_reg_names[ 8][0], /* r8 */ \
2040 &rs6000_reg_names[ 9][0], /* r9 */ \
2041 &rs6000_reg_names[10][0], /* r10 */ \
2042 &rs6000_reg_names[11][0], /* r11 */ \
2043 &rs6000_reg_names[12][0], /* r12 */ \
2044 &rs6000_reg_names[13][0], /* r13 */ \
2045 &rs6000_reg_names[14][0], /* r14 */ \
2046 &rs6000_reg_names[15][0], /* r15 */ \
2047 &rs6000_reg_names[16][0], /* r16 */ \
2048 &rs6000_reg_names[17][0], /* r17 */ \
2049 &rs6000_reg_names[18][0], /* r18 */ \
2050 &rs6000_reg_names[19][0], /* r19 */ \
2051 &rs6000_reg_names[20][0], /* r20 */ \
2052 &rs6000_reg_names[21][0], /* r21 */ \
2053 &rs6000_reg_names[22][0], /* r22 */ \
2054 &rs6000_reg_names[23][0], /* r23 */ \
2055 &rs6000_reg_names[24][0], /* r24 */ \
2056 &rs6000_reg_names[25][0], /* r25 */ \
2057 &rs6000_reg_names[26][0], /* r26 */ \
2058 &rs6000_reg_names[27][0], /* r27 */ \
2059 &rs6000_reg_names[28][0], /* r28 */ \
2060 &rs6000_reg_names[29][0], /* r29 */ \
2061 &rs6000_reg_names[30][0], /* r30 */ \
2062 &rs6000_reg_names[31][0], /* r31 */ \
2064 &rs6000_reg_names[32][0], /* fr0 */ \
2065 &rs6000_reg_names[33][0], /* fr1 */ \
2066 &rs6000_reg_names[34][0], /* fr2 */ \
2067 &rs6000_reg_names[35][0], /* fr3 */ \
2068 &rs6000_reg_names[36][0], /* fr4 */ \
2069 &rs6000_reg_names[37][0], /* fr5 */ \
2070 &rs6000_reg_names[38][0], /* fr6 */ \
2071 &rs6000_reg_names[39][0], /* fr7 */ \
2072 &rs6000_reg_names[40][0], /* fr8 */ \
2073 &rs6000_reg_names[41][0], /* fr9 */ \
2074 &rs6000_reg_names[42][0], /* fr10 */ \
2075 &rs6000_reg_names[43][0], /* fr11 */ \
2076 &rs6000_reg_names[44][0], /* fr12 */ \
2077 &rs6000_reg_names[45][0], /* fr13 */ \
2078 &rs6000_reg_names[46][0], /* fr14 */ \
2079 &rs6000_reg_names[47][0], /* fr15 */ \
2080 &rs6000_reg_names[48][0], /* fr16 */ \
2081 &rs6000_reg_names[49][0], /* fr17 */ \
2082 &rs6000_reg_names[50][0], /* fr18 */ \
2083 &rs6000_reg_names[51][0], /* fr19 */ \
2084 &rs6000_reg_names[52][0], /* fr20 */ \
2085 &rs6000_reg_names[53][0], /* fr21 */ \
2086 &rs6000_reg_names[54][0], /* fr22 */ \
2087 &rs6000_reg_names[55][0], /* fr23 */ \
2088 &rs6000_reg_names[56][0], /* fr24 */ \
2089 &rs6000_reg_names[57][0], /* fr25 */ \
2090 &rs6000_reg_names[58][0], /* fr26 */ \
2091 &rs6000_reg_names[59][0], /* fr27 */ \
2092 &rs6000_reg_names[60][0], /* fr28 */ \
2093 &rs6000_reg_names[61][0], /* fr29 */ \
2094 &rs6000_reg_names[62][0], /* fr30 */ \
2095 &rs6000_reg_names[63][0], /* fr31 */ \
2097 &rs6000_reg_names[64][0], /* was mq */ \
2098 &rs6000_reg_names[65][0], /* lr */ \
2099 &rs6000_reg_names[66][0], /* ctr */ \
2100 &rs6000_reg_names[67][0], /* ap */ \
2102 &rs6000_reg_names[68][0], /* cr0 */ \
2103 &rs6000_reg_names[69][0], /* cr1 */ \
2104 &rs6000_reg_names[70][0], /* cr2 */ \
2105 &rs6000_reg_names[71][0], /* cr3 */ \
2106 &rs6000_reg_names[72][0], /* cr4 */ \
2107 &rs6000_reg_names[73][0], /* cr5 */ \
2108 &rs6000_reg_names[74][0], /* cr6 */ \
2109 &rs6000_reg_names[75][0], /* cr7 */ \
2111 &rs6000_reg_names[76][0], /* ca */ \
2113 &rs6000_reg_names[77][0], /* v0 */ \
2114 &rs6000_reg_names[78][0], /* v1 */ \
2115 &rs6000_reg_names[79][0], /* v2 */ \
2116 &rs6000_reg_names[80][0], /* v3 */ \
2117 &rs6000_reg_names[81][0], /* v4 */ \
2118 &rs6000_reg_names[82][0], /* v5 */ \
2119 &rs6000_reg_names[83][0], /* v6 */ \
2120 &rs6000_reg_names[84][0], /* v7 */ \
2121 &rs6000_reg_names[85][0], /* v8 */ \
2122 &rs6000_reg_names[86][0], /* v9 */ \
2123 &rs6000_reg_names[87][0], /* v10 */ \
2124 &rs6000_reg_names[88][0], /* v11 */ \
2125 &rs6000_reg_names[89][0], /* v12 */ \
2126 &rs6000_reg_names[90][0], /* v13 */ \
2127 &rs6000_reg_names[91][0], /* v14 */ \
2128 &rs6000_reg_names[92][0], /* v15 */ \
2129 &rs6000_reg_names[93][0], /* v16 */ \
2130 &rs6000_reg_names[94][0], /* v17 */ \
2131 &rs6000_reg_names[95][0], /* v18 */ \
2132 &rs6000_reg_names[96][0], /* v19 */ \
2133 &rs6000_reg_names[97][0], /* v20 */ \
2134 &rs6000_reg_names[98][0], /* v21 */ \
2135 &rs6000_reg_names[99][0], /* v22 */ \
2136 &rs6000_reg_names[100][0], /* v23 */ \
2137 &rs6000_reg_names[101][0], /* v24 */ \
2138 &rs6000_reg_names[102][0], /* v25 */ \
2139 &rs6000_reg_names[103][0], /* v26 */ \
2140 &rs6000_reg_names[104][0], /* v27 */ \
2141 &rs6000_reg_names[105][0], /* v28 */ \
2142 &rs6000_reg_names[106][0], /* v29 */ \
2143 &rs6000_reg_names[107][0], /* v30 */ \
2144 &rs6000_reg_names[108][0], /* v31 */ \
2145 &rs6000_reg_names[109][0], /* vrsave */ \
2146 &rs6000_reg_names[110][0], /* vscr */ \
2147 &rs6000_reg_names[111][0], /* spe_acc */ \
2148 &rs6000_reg_names[112][0], /* spefscr */ \
2149 &rs6000_reg_names[113][0], /* sfp */ \
2152 /* Table of additional register names to use in user input. */
2154 #define ADDITIONAL_REGISTER_NAMES \
2155 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2156 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2157 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2158 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2159 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2160 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2161 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2162 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2163 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2164 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2165 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2166 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2167 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2168 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2169 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2170 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2171 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2172 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2173 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2174 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2175 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2176 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2177 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2178 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2179 {"vrsave", 109}, {"vscr", 110}, \
2180 {"spe_acc", 111}, {"spefscr", 112}, \
2181 /* no additional names for: lr, ctr, ap */ \
2182 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2183 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2184 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2185 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2187 /* VSX registers overlaid on top of FR, Altivec registers */ \
2188 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2189 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2190 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2191 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2192 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2193 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2194 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2195 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2196 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2197 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2198 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2199 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2200 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2201 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2202 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2203 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
2205 /* Text to write out after a CALL that may be replaced by glue code by
2206 the loader. This depends on the AIX version. */
2207 #define RS6000_CALL_GLUE "cror 31,31,31"
2209 /* This is how to output an element of a case-vector that is relative. */
2211 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2212 do { char buf[100]; \
2213 fputs ("\t.long ", FILE); \
2214 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2215 assemble_name (FILE, buf); \
2217 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2218 assemble_name (FILE, buf); \
2219 putc ('\n', FILE); \
2222 /* This is how to output an assembler line
2223 that says to advance the location counter
2224 to a multiple of 2**LOG bytes. */
2226 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2228 fprintf (FILE, "\t.align %d\n", (LOG))
2230 /* How to align the given loop. */
2231 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2233 /* Pick up the return address upon entry to a procedure. Used for
2234 dwarf2 unwind information. This also enables the table driven
2237 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2238 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2240 /* Describe how we implement __builtin_eh_return. */
2241 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2242 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2244 /* Print operand X (an rtx) in assembler syntax to file FILE.
2245 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2246 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2248 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2250 /* Define which CODE values are valid. */
2252 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2253 ((CODE) == '.' || (CODE) == '&')
2255 /* Print a memory address as an operand to reference that memory location. */
2257 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2259 /* uncomment for disabling the corresponding default options */
2260 /* #define MACHINE_no_sched_interblock */
2261 /* #define MACHINE_no_sched_speculative */
2262 /* #define MACHINE_no_sched_speculative_load */
2264 /* General flags. */
2265 extern int frame_pointer_needed;
2267 /* Classification of the builtin functions as to which switches enable the
2268 builtin, and what attributes it should have. We used to use the target
2269 flags macros, but we've run out of bits, so we now map the options into new
2270 settings used here. */
2272 /* Builtin attributes. */
2273 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2274 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2275 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2276 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2277 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2278 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2279 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */
2280 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2281 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2283 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2284 #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
2285 #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */
2286 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2287 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2289 /* Miscellaneous information. */
2290 #define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */
2292 /* Convenience macros to document the instruction type. */
2293 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2294 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2296 /* Builtin targets. For now, we reuse the masks for those options that are in
2297 target flags, and pick two random bits for SPE and paired which aren't in
2299 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2300 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2301 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2302 #define RS6000_BTM_SPE MASK_STRING /* E500 */
2303 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
2304 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2305 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2306 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2307 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2308 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2309 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2311 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2315 | RS6000_BTM_FRSQRTE \
2316 | RS6000_BTM_FRSQRTES \
2317 | RS6000_BTM_POPCNTD \
2320 /* Define builtin enum index. */
2322 #undef RS6000_BUILTIN_1
2323 #undef RS6000_BUILTIN_2
2324 #undef RS6000_BUILTIN_3
2325 #undef RS6000_BUILTIN_A
2326 #undef RS6000_BUILTIN_D
2327 #undef RS6000_BUILTIN_E
2328 #undef RS6000_BUILTIN_P
2329 #undef RS6000_BUILTIN_Q
2330 #undef RS6000_BUILTIN_S
2331 #undef RS6000_BUILTIN_X
2333 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2334 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2335 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2336 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2337 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2338 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2339 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2340 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2341 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2342 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2344 enum rs6000_builtins
2346 #include "rs6000-builtin.def"
2348 RS6000_BUILTIN_COUNT
2351 #undef RS6000_BUILTIN_1
2352 #undef RS6000_BUILTIN_2
2353 #undef RS6000_BUILTIN_3
2354 #undef RS6000_BUILTIN_A
2355 #undef RS6000_BUILTIN_D
2356 #undef RS6000_BUILTIN_E
2357 #undef RS6000_BUILTIN_P
2358 #undef RS6000_BUILTIN_Q
2359 #undef RS6000_BUILTIN_S
2360 #undef RS6000_BUILTIN_X
2362 enum rs6000_builtin_type_index
2364 RS6000_BTI_NOT_OPAQUE,
2365 RS6000_BTI_opaque_V2SI,
2366 RS6000_BTI_opaque_V2SF,
2367 RS6000_BTI_opaque_p_V2SI,
2368 RS6000_BTI_opaque_V4SI,
2378 RS6000_BTI_unsigned_V16QI,
2379 RS6000_BTI_unsigned_V8HI,
2380 RS6000_BTI_unsigned_V4SI,
2381 RS6000_BTI_unsigned_V2DI,
2382 RS6000_BTI_bool_char, /* __bool char */
2383 RS6000_BTI_bool_short, /* __bool short */
2384 RS6000_BTI_bool_int, /* __bool int */
2385 RS6000_BTI_bool_long, /* __bool long */
2386 RS6000_BTI_pixel, /* __pixel */
2387 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2388 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2389 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2390 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2391 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2392 RS6000_BTI_long, /* long_integer_type_node */
2393 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2394 RS6000_BTI_long_long, /* long_long_integer_type_node */
2395 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2396 RS6000_BTI_INTQI, /* intQI_type_node */
2397 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2398 RS6000_BTI_INTHI, /* intHI_type_node */
2399 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2400 RS6000_BTI_INTSI, /* intSI_type_node */
2401 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2402 RS6000_BTI_INTDI, /* intDI_type_node */
2403 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2404 RS6000_BTI_float, /* float_type_node */
2405 RS6000_BTI_double, /* double_type_node */
2406 RS6000_BTI_void, /* void_type_node */
2411 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2412 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2413 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2414 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2415 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2416 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2417 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2418 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2419 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2420 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2421 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2422 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2423 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2424 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2425 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2426 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2427 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2428 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2429 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2430 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2431 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2432 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2433 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2434 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2435 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2436 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2437 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2439 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2440 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2441 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2442 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2443 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2444 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2445 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2446 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2447 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2448 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2449 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2450 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2451 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2452 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2453 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2455 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2456 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];