1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Print subsidiary information on the compiler version in use. */
45 #define TARGET_VERSION ;
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* Common CPP definitions used by CPP_SPEC among the various targets
53 for handling -mcpu=xxx switches. */
54 #define CPP_CPU_SPEC \
56 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
57 %{mpower2: -D_ARCH_PWR2} \
58 %{mpowerpc*: -D_ARCH_PPC} \
59 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
60 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
61 %{mcpu=common: -D_ARCH_COM} \
62 %{mcpu=power: -D_ARCH_PWR} \
63 %{mcpu=power2: -D_ARCH_PWR2} \
64 %{mcpu=powerpc: -D_ARCH_PPC} \
65 %{mcpu=rios: -D_ARCH_PWR} \
66 %{mcpu=rios1: -D_ARCH_PWR} \
67 %{mcpu=rios2: -D_ARCH_PWR2} \
68 %{mcpu=rsc: -D_ARCH_PWR} \
69 %{mcpu=rsc1: -D_ARCH_PWR} \
70 %{mcpu=401: -D_ARCH_PPC} \
71 %{mcpu=403: -D_ARCH_PPC} \
72 %{mcpu=505: -D_ARCH_PPC} \
73 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
74 %{mcpu=602: -D_ARCH_PPC} \
75 %{mcpu=603: -D_ARCH_PPC} \
76 %{mcpu=603e: -D_ARCH_PPC} \
77 %{mcpu=ec603e: -D_ARCH_PPC} \
78 %{mcpu=604: -D_ARCH_PPC} \
79 %{mcpu=604e: -D_ARCH_PPC} \
80 %{mcpu=620: -D_ARCH_PPC} \
81 %{mcpu=740: -D_ARCH_PPC} \
82 %{mcpu=750: -D_ARCH_PPC} \
83 %{mcpu=801: -D_ARCH_PPC} \
84 %{mcpu=821: -D_ARCH_PPC} \
85 %{mcpu=823: -D_ARCH_PPC} \
86 %{mcpu=860: -D_ARCH_PPC} \
87 %{maltivec: -D__ALTIVEC__}"
89 /* Common ASM definitions used by ASM_SPEC among the various targets
90 for handling -mcpu=xxx switches. */
91 #define ASM_CPU_SPEC \
93 %{mpower: %{!mpower2: -mpwr}} \
96 %{mno-power: %{!mpowerpc*: -mcom}} \
97 %{!mno-power: %{!mpower2: %(asm_default)}}} \
98 %{mcpu=common: -mcom} \
99 %{mcpu=power: -mpwr} \
100 %{mcpu=power2: -mpwrx} \
101 %{mcpu=powerpc: -mppc} \
102 %{mcpu=rios: -mpwr} \
103 %{mcpu=rios1: -mpwr} \
104 %{mcpu=rios2: -mpwrx} \
106 %{mcpu=rsc1: -mpwr} \
113 %{mcpu=603e: -mppc} \
114 %{mcpu=ec603e: -mppc} \
116 %{mcpu=604e: -mppc} \
125 #define CPP_DEFAULT_SPEC ""
127 #define ASM_DEFAULT_SPEC ""
129 /* This macro defines names of additional specifications to put in the specs
130 that can be used in various specifications like CC1_SPEC. Its definition
131 is an initializer with a subgrouping for each command option.
133 Each subgrouping contains a string constant, that defines the
134 specification name, and a string constant that used by the GNU CC driver
137 Do not define this macro if it does not need to do anything. */
139 #define SUBTARGET_EXTRA_SPECS
141 #define EXTRA_SPECS \
142 { "cpp_cpu", CPP_CPU_SPEC }, \
143 { "cpp_default", CPP_DEFAULT_SPEC }, \
144 { "asm_cpu", ASM_CPU_SPEC }, \
145 { "asm_default", ASM_DEFAULT_SPEC }, \
146 SUBTARGET_EXTRA_SPECS
148 /* Architecture type. */
150 extern int target_flags;
152 /* Use POWER architecture instructions and MQ register. */
153 #define MASK_POWER 0x00000001
155 /* Use POWER2 extensions to POWER architecture. */
156 #define MASK_POWER2 0x00000002
158 /* Use PowerPC architecture instructions. */
159 #define MASK_POWERPC 0x00000004
161 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
162 #define MASK_PPC_GPOPT 0x00000008
164 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
165 #define MASK_PPC_GFXOPT 0x00000010
167 /* Use PowerPC-64 architecture instructions. */
168 #define MASK_POWERPC64 0x00000020
170 /* Use revised mnemonic names defined for PowerPC architecture. */
171 #define MASK_NEW_MNEMONICS 0x00000040
173 /* Disable placing fp constants in the TOC; can be turned on when the
175 #define MASK_NO_FP_IN_TOC 0x00000080
177 /* Disable placing symbol+offset constants in the TOC; can be turned on when
178 the TOC overflows. */
179 #define MASK_NO_SUM_IN_TOC 0x00000100
181 /* Output only one TOC entry per module. Normally linking fails if
182 there are more than 16K unique variables/constants in an executable. With
183 this option, linking fails only if there are more than 16K modules, or
184 if there are more than 16K unique variables/constant in a single module.
186 This is at the cost of having 2 extra loads and one extra store per
187 function, and one less allocable register. */
188 #define MASK_MINIMAL_TOC 0x00000200
190 /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */
191 #define MASK_64BIT 0x00000400
193 /* Disable use of FPRs. */
194 #define MASK_SOFT_FLOAT 0x00000800
196 /* Enable load/store multiple, even on powerpc */
197 #define MASK_MULTIPLE 0x00001000
198 #define MASK_MULTIPLE_SET 0x00002000
200 /* Use string instructions for block moves */
201 #define MASK_STRING 0x00004000
202 #define MASK_STRING_SET 0x00008000
204 /* Disable update form of load/store */
205 #define MASK_NO_UPDATE 0x00010000
207 /* Disable fused multiply/add operations */
208 #define MASK_NO_FUSED_MADD 0x00020000
210 /* Nonzero if we need to schedule the prolog and epilog. */
211 #define MASK_SCHED_PROLOG 0x00040000
213 /* Use AltiVec instructions. */
214 #define MASK_ALTIVEC 0x00080000
216 /* Enhance the current ABI with AltiVec extensions. */
217 #define MASK_ALTIVEC_ABI 0x00100000
219 #define TARGET_POWER (target_flags & MASK_POWER)
220 #define TARGET_POWER2 (target_flags & MASK_POWER2)
221 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
222 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
223 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
224 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
225 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
226 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
227 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
228 #define TARGET_64BIT (target_flags & MASK_64BIT)
229 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
230 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
231 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
232 #define TARGET_STRING (target_flags & MASK_STRING)
233 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
234 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
235 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
236 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
237 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
238 #define TARGET_ALTIVEC_ABI (target_flags & MASK_ALTIVEC_ABI)
240 #define TARGET_32BIT (! TARGET_64BIT)
241 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
242 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
243 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
246 /* For libgcc2 we make sure this is a compile time constant */
248 #define TARGET_POWERPC64 1
250 #define TARGET_POWERPC64 0
253 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
256 #define TARGET_XL_CALL 0
258 /* Run-time compilation parameters selecting different hardware subsets.
260 Macro to define tables used to set the flags.
261 This is a list in braces of pairs in braces,
262 each pair being { "NAME", VALUE }
263 where VALUE is the bits to set or minus the bits to clear.
264 An empty string NAME is used to identify the default VALUE. */
266 #define TARGET_SWITCHES \
267 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
268 N_("Use POWER instruction set")}, \
269 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
271 N_("Use POWER2 instruction set")}, \
272 {"no-power2", - MASK_POWER2, \
273 N_("Do not use POWER2 instruction set")}, \
274 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
276 N_("Do not use POWER instruction set")}, \
277 {"powerpc", MASK_POWERPC, \
278 N_("Use PowerPC instruction set")}, \
279 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
280 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
281 N_("Do not use PowerPC instruction set")}, \
282 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
283 N_("Use PowerPC General Purpose group optional instructions")},\
284 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
285 N_("Don't use PowerPC General Purpose group optional instructions")},\
286 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
287 N_("Use PowerPC Graphics group optional instructions")},\
288 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
289 N_("Don't use PowerPC Graphics group optional instructions")},\
290 {"powerpc64", MASK_POWERPC64, \
291 N_("Use PowerPC-64 instruction set")}, \
292 {"no-powerpc64", - MASK_POWERPC64, \
293 N_("Don't use PowerPC-64 instruction set")}, \
294 {"altivec", MASK_ALTIVEC, \
295 N_("Use AltiVec instructions.")}, \
296 {"no-altivec", - MASK_ALTIVEC, \
297 N_("Don't use AltiVec instructions.")}, \
298 {"new-mnemonics", MASK_NEW_MNEMONICS, \
299 N_("Use new mnemonics for PowerPC architecture")},\
300 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
301 N_("Use old mnemonics for PowerPC architecture")},\
302 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
303 | MASK_MINIMAL_TOC), \
304 N_("Put everything in the regular TOC")}, \
305 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
306 N_("Place floating point constants in TOC")}, \
307 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
308 N_("Don't place floating point constants in TOC")},\
309 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
310 N_("Place symbol+offset constants in TOC")}, \
311 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
312 N_("Don't place symbol+offset constants in TOC")},\
313 {"minimal-toc", MASK_MINIMAL_TOC, \
314 "Use only one TOC entry per procedure"}, \
315 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
317 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
318 N_("Place variable addresses in the regular TOC")},\
319 {"hard-float", - MASK_SOFT_FLOAT, \
320 N_("Use hardware fp")}, \
321 {"soft-float", MASK_SOFT_FLOAT, \
322 N_("Do not use hardware fp")}, \
323 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
324 N_("Generate load/store multiple instructions")}, \
325 {"no-multiple", - MASK_MULTIPLE, \
326 N_("Do not generate load/store multiple instructions")},\
327 {"no-multiple", MASK_MULTIPLE_SET, \
329 {"string", MASK_STRING | MASK_STRING_SET, \
330 N_("Generate string instructions for block moves")},\
331 {"no-string", - MASK_STRING, \
332 N_("Do not generate string instructions for block moves")},\
333 {"no-string", MASK_STRING_SET, \
335 {"update", - MASK_NO_UPDATE, \
336 N_("Generate load/store with update instructions")},\
337 {"no-update", MASK_NO_UPDATE, \
338 N_("Do not generate load/store with update instructions")},\
339 {"fused-madd", - MASK_NO_FUSED_MADD, \
340 N_("Generate fused multiply/add instructions")},\
341 {"no-fused-madd", MASK_NO_FUSED_MADD, \
342 N_("Don't generate fused multiply/add instructions")},\
343 {"sched-prolog", MASK_SCHED_PROLOG, \
345 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
346 N_("Don't schedule the start and end of the procedure")},\
347 {"sched-epilog", MASK_SCHED_PROLOG, \
349 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
352 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
355 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
357 /* This is meant to be redefined in the host dependent files */
358 #define SUBTARGET_SWITCHES
360 /* Processor type. Order must match cpu attribute in MD file. */
379 extern enum processor_type rs6000_cpu;
381 /* Recast the processor type to the cpu attribute. */
382 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
384 /* Define generic processor types based upon current deployment. */
385 #define PROCESSOR_COMMON PROCESSOR_PPC601
386 #define PROCESSOR_POWER PROCESSOR_RIOS1
387 #define PROCESSOR_POWERPC PROCESSOR_PPC604
388 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
390 /* Define the default processor. This is overridden by other tm.h files. */
391 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
392 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
394 /* Specify the dialect of assembler to use. New mnemonics is dialect one
395 and the old mnemonics are dialect zero. */
396 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
398 /* This macro is similar to `TARGET_SWITCHES' but defines names of
399 command options that have values. Its definition is an
400 initializer with a subgrouping for each command option.
402 Each subgrouping contains a string constant, that defines the
403 fixed part of the option name, and the address of a variable.
404 The variable, type `char *', is set to the variable part of the
405 given option if the fixed part matches. The actual option name
406 is made by appending `-m' to the specified name.
408 Here is an example which defines `-mshort-data-NUMBER'. If the
409 given option is `-mshort-data-512', the variable `m88k_short_data'
410 will be set to the string `"512"'.
412 extern char *m88k_short_data;
413 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
415 /* This is meant to be overridden in target specific files. */
416 #define SUBTARGET_OPTIONS
418 #define TARGET_OPTIONS \
420 {"cpu=", &rs6000_select[1].string, \
421 N_("Use features of and schedule code for given CPU") }, \
422 {"tune=", &rs6000_select[2].string, \
423 N_("Schedule code for given CPU") }, \
424 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
425 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
429 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
430 struct rs6000_cpu_select
438 extern struct rs6000_cpu_select rs6000_select[];
441 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
442 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,solaris,eabi,aix,altivec} */
443 extern int rs6000_debug_stack; /* debug stack applications */
444 extern int rs6000_debug_arg; /* debug argument handling */
446 #define TARGET_DEBUG_STACK rs6000_debug_stack
447 #define TARGET_DEBUG_ARG rs6000_debug_arg
449 /* Sometimes certain combinations of command options do not make sense
450 on a particular target machine. You can define a macro
451 `OVERRIDE_OPTIONS' to take account of this. This macro, if
452 defined, is executed once just after all the command options have
455 Don't use this macro to turn on various extra optimizations for
456 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
458 On the RS/6000 this is used to define the target cpu type. */
460 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
462 /* Define this to change the optimizations performed by default. */
463 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
465 /* Show we can debug even without a frame pointer. */
466 #define CAN_DEBUG_WITHOUT_FP
468 /* target machine storage layout */
470 /* Define to support cross compilation to an RS6000 target. */
471 #define REAL_ARITHMETIC
473 /* Define this macro if it is advisable to hold scalars in registers
474 in a wider mode than that declared by the program. In such cases,
475 the value is constrained to be within the bounds of the declared
476 type, but kept valid in the wider mode. The signedness of the
477 extension may differ from that of the type. */
479 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
480 if (GET_MODE_CLASS (MODE) == MODE_INT \
481 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
484 /* Define this if function arguments should also be promoted using the above
487 #define PROMOTE_FUNCTION_ARGS
489 /* Likewise, if the function return value is promoted. */
491 #define PROMOTE_FUNCTION_RETURN
493 /* Define this if most significant bit is lowest numbered
494 in instructions that operate on numbered bit-fields. */
495 /* That is true on RS/6000. */
496 #define BITS_BIG_ENDIAN 1
498 /* Define this if most significant byte of a word is the lowest numbered. */
499 /* That is true on RS/6000. */
500 #define BYTES_BIG_ENDIAN 1
502 /* Define this if most significant word of a multiword number is lowest
505 For RS/6000 we can decide arbitrarily since there are no machine
506 instructions for them. Might as well be consistent with bits and bytes. */
507 #define WORDS_BIG_ENDIAN 1
509 /* number of bits in an addressable storage unit */
510 #define BITS_PER_UNIT 8
512 /* Width in bits of a "word", which is the contents of a machine register.
513 Note that this is not necessarily the width of data type `int';
514 if using 16-bit ints on a 68000, this would still be 32.
515 But on a machine with 16-bit registers, this would be 16. */
516 #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
517 #define MAX_BITS_PER_WORD 64
519 /* Width of a word, in units (bytes). */
520 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
521 #define MIN_UNITS_PER_WORD 4
522 #define UNITS_PER_FP_WORD 8
523 #define UNITS_PER_ALTIVEC_WORD 16
525 /* Type used for ptrdiff_t, as a string used in a declaration. */
526 #define PTRDIFF_TYPE "int"
528 /* Type used for size_t, as a string used in a declaration. */
529 #define SIZE_TYPE "long unsigned int"
531 /* Type used for wchar_t, as a string used in a declaration. */
532 #define WCHAR_TYPE "short unsigned int"
534 /* Width of wchar_t in bits. */
535 #define WCHAR_TYPE_SIZE 16
537 /* A C expression for the size in bits of the type `short' on the
538 target machine. If you don't define this, the default is half a
539 word. (If this would be less than one storage unit, it is
540 rounded up to one unit.) */
541 #define SHORT_TYPE_SIZE 16
543 /* A C expression for the size in bits of the type `int' on the
544 target machine. If you don't define this, the default is one
546 #define INT_TYPE_SIZE 32
548 /* A C expression for the size in bits of the type `long' on the
549 target machine. If you don't define this, the default is one
551 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
552 #define MAX_LONG_TYPE_SIZE 64
554 /* A C expression for the size in bits of the type `long long' on the
555 target machine. If you don't define this, the default is two
557 #define LONG_LONG_TYPE_SIZE 64
559 /* A C expression for the size in bits of the type `char' on the
560 target machine. If you don't define this, the default is one
561 quarter of a word. (If this would be less than one storage unit,
562 it is rounded up to one unit.) */
563 #define CHAR_TYPE_SIZE BITS_PER_UNIT
565 /* A C expression for the size in bits of the type `float' on the
566 target machine. If you don't define this, the default is one
568 #define FLOAT_TYPE_SIZE 32
570 /* A C expression for the size in bits of the type `double' on the
571 target machine. If you don't define this, the default is two
573 #define DOUBLE_TYPE_SIZE 64
575 /* A C expression for the size in bits of the type `long double' on
576 the target machine. If you don't define this, the default is two
578 #define LONG_DOUBLE_TYPE_SIZE 64
580 /* Width in bits of a pointer.
581 See also the macro `Pmode' defined below. */
582 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
584 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
585 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
587 /* Boundary (in *bits*) on which stack pointer should be aligned. */
588 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
590 /* Allocation boundary (in *bits*) for the code of a function. */
591 #define FUNCTION_BOUNDARY 32
593 /* No data type wants to be aligned rounder than this. */
594 #define BIGGEST_ALIGNMENT 128
596 /* A C expression to compute the alignment for a variables in the
597 local store. TYPE is the data type, and ALIGN is the alignment
598 that the object would ordinarily have. */
599 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
601 && TREE_CODE (TYPE)) == VECTOR_TYPE ? 128 : ALIGN)
603 /* Handle #pragma pack. */
604 #define HANDLE_PRAGMA_PACK 1
606 /* Alignment of field after `int : 0' in a structure. */
607 #define EMPTY_FIELD_BOUNDARY 32
609 /* Every structure's size must be a multiple of this. */
610 #define STRUCTURE_SIZE_BOUNDARY 8
612 /* A bitfield declared as `int' forces `int' alignment for the struct. */
613 #define PCC_BITFIELD_TYPE_MATTERS 1
615 /* Make strings word-aligned so strcpy from constants will be faster. */
616 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
617 (TREE_CODE (EXP) == STRING_CST \
618 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
620 /* Make arrays of chars word-aligned for the same reasons.
621 Align vectors to 128 bits. */
622 #define DATA_ALIGNMENT(TYPE, ALIGN) \
623 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
624 : TREE_CODE (TYPE) == ARRAY_TYPE \
625 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
626 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
628 /* Non-zero if move instructions will actually fail to work
629 when given unaligned data. */
630 #define STRICT_ALIGNMENT 0
632 /* Define this macro to be the value 1 if unaligned accesses have a cost
633 many times greater than aligned accesses, for example if they are
634 emulated in a trap handler. */
635 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
637 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
638 && (ALIGN) < 32)) ? 1 : 0)
640 /* Standard register usage. */
642 /* Number of actual hardware registers.
643 The hardware registers are assigned numbers for the compiler
644 from 0 to just below FIRST_PSEUDO_REGISTER.
645 All registers that the compiler knows about must be given numbers,
646 even those that are not normally considered general registers.
648 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
649 an MQ register, a count register, a link register, and 8 condition
650 register fields, which we view here as separate registers.
652 In addition, the difference between the frame and argument pointers is
653 a function of the number of registers saved, so we need to have a
654 register for AP that will later be eliminated in favor of SP or FP.
655 This is a normal register, but it is fixed.
657 We also create a pseudo register for float/int conversions, that will
658 really represent the memory location used. It is represented here as
659 a register, in order to work around problems in allocating stack storage
660 in inline functions. */
662 #define FIRST_PSEUDO_REGISTER 110
664 /* This must not decrease, for backwards compatibility. If
665 FIRST_PSEUDO_REGISTER increases, this should as well. */
666 /* fixme: this needs to be defined to "TARGET_ALTIVEC_ABI ? 110 : 77"
667 and then fix usages of DWARF_FRAME_REGISTERS to work. */
668 #define DWARF_FRAME_REGISTERS 77
670 /* 1 for registers that have pervasive standard uses
671 and are not available for the register allocator.
673 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
674 as a local register; for all other OS's r2 is the TOC pointer.
676 cr5 is not supposed to be used.
678 On System V implementations, r13 is fixed and not available for use. */
680 #define FIXED_REGISTERS \
681 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
683 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
684 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
685 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
686 /* AltiVec registers. */ \
687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
692 /* 1 for registers not available across function calls.
693 These must include the FIXED_REGISTERS and also any
694 registers that can be used without being saved.
695 The latter must include the registers where values are returned
696 and the register where structure-value addresses are passed.
697 Aside from that, you can include as many other registers as you like. */
699 #define CALL_USED_REGISTERS \
700 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
702 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
704 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
705 /* AltiVec registers. */ \
706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
718 #define MAX_CR_REGNO 75
720 #define FIRST_ALTIVEC_REGNO 77
721 #define LAST_ALTIVEC_REGNO 108
722 #define VRSAVE_REGNO 109
724 /* List the order in which to allocate registers. Each register must be
725 listed once, even those in FIXED_REGISTERS.
727 We allocate in the following order:
728 fp0 (not saved or used for anything)
729 fp13 - fp2 (not saved; incoming fp arg registers)
730 fp1 (not saved; return value)
731 fp31 - fp14 (saved; order given to save least number)
732 cr7, cr6 (not saved or special)
733 cr1 (not saved, but used for FP operations)
734 cr0 (not saved, but used for arithmetic operations)
735 cr4, cr3, cr2 (saved)
736 r0 (not saved; cannot be base reg)
737 r9 (not saved; best for TImode)
738 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
739 r3 (not saved; return value register)
740 r31 - r13 (saved; order given to save least number)
741 r12 (not saved; if used for DImode or DFmode would use r13)
742 mq (not saved; best to use it if we can)
743 ctr (not saved; when we have the choice ctr is better)
745 cr5, r1, r2, ap, xer, vrsave (fixed)
748 v0 - v1 (not saved or used for anything)
749 v13 - v3 (not saved; incoming vector arg registers)
750 v2 (not saved; incoming vector arg reg; return value)
751 v19 - v14 (not saved or used for anything)
752 v31 - v20 (saved; order given to save least number)
756 #define REG_ALLOC_ORDER \
758 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
760 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
761 50, 49, 48, 47, 46, \
762 75, 74, 69, 68, 72, 71, 70, \
764 9, 11, 10, 8, 7, 6, 5, 4, \
766 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
767 18, 17, 16, 15, 14, 13, 12, \
770 /* AltiVec registers. */ \
772 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
774 96, 95, 94, 93, 92, 91, \
775 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97 \
778 /* True if register is floating-point. */
779 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
781 /* True if register is a condition register. */
782 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
784 /* True if register is a condition register, but not cr0. */
785 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
787 /* True if register is an integer register. */
788 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
790 /* True if register is the XER register. */
791 #define XER_REGNO_P(N) ((N) == XER_REGNO)
793 /* True if register is an AltiVec register. */
794 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
796 /* Return number of consecutive hard regs needed starting at reg REGNO
797 to hold something of mode MODE.
798 This is ordinarily the length in words of a value of mode MODE
799 but can be less for certain modes in special long registers.
801 POWER and PowerPC GPRs hold 32 bits worth;
802 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
804 #define HARD_REGNO_NREGS(REGNO, MODE) \
805 (FP_REGNO_P (REGNO) \
806 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
807 : ALTIVEC_REGNO_P (REGNO) \
808 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
809 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
811 #define ALTIVEC_VECTOR_MODE(MODE) \
812 ((MODE) == V16QImode \
813 || (MODE) == V8HImode \
814 || (MODE) == V4SFmode \
815 || (MODE) == V4SImode)
817 /* Define this macro to be nonzero if the port is prepared to handle
818 insns involving vector mode MODE. At the very least, it must have
819 move patterns for this mode. */
821 #define VECTOR_MODE_SUPPORTED_P(MODE) \
822 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
824 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
825 For POWER and PowerPC, the GPRs can hold any mode, but the float
826 registers only can hold floating modes and DImode, and CR register only
827 can hold CC modes. We cannot put TImode anywhere except general
828 register and it must be able to fit within the register set. */
830 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
831 (FP_REGNO_P (REGNO) ? \
832 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
833 || (GET_MODE_CLASS (MODE) == MODE_INT \
834 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
835 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
836 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
837 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
838 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
839 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
842 /* Value is 1 if it is a good idea to tie two pseudo registers
843 when one has mode MODE1 and one has mode MODE2.
844 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
845 for any hard reg, then this must be 0 for correct output. */
846 #define MODES_TIEABLE_P(MODE1, MODE2) \
847 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
848 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
849 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
850 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
851 : GET_MODE_CLASS (MODE1) == MODE_CC \
852 ? GET_MODE_CLASS (MODE2) == MODE_CC \
853 : GET_MODE_CLASS (MODE2) == MODE_CC \
854 ? GET_MODE_CLASS (MODE1) == MODE_CC \
855 : ALTIVEC_VECTOR_MODE (MODE1) \
856 ? ALTIVEC_VECTOR_MODE (MODE2) \
857 : ALTIVEC_VECTOR_MODE (MODE2) \
858 ? ALTIVEC_VECTOR_MODE (MODE1) \
861 /* A C expression returning the cost of moving data from a register of class
862 CLASS1 to one of CLASS2.
864 On the RS/6000, copying between floating-point and fixed-point
865 registers is expensive. */
867 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
868 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
869 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
870 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
871 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
872 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
873 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
874 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
875 || (CLASS1) == LINK_OR_CTR_REGS) \
876 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
877 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
878 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
881 /* A C expressions returning the cost of moving data of MODE from a register to
884 On the RS/6000, bump this up a bit. */
886 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
887 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
888 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
892 /* Specify the cost of a branch insn; roughly the number of extra insns that
893 should be added to avoid a branch.
895 Set this to 3 on the RS/6000 since that is roughly the average cost of an
896 unscheduled conditional branch. */
898 #define BRANCH_COST 3
900 /* Define this macro to change register usage conditional on target flags.
901 Set MQ register fixed (already call_used) if not POWER architecture
902 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
903 64-bit AIX reserves GPR13 for thread-private data.
904 Conditionally disable FPRs. */
906 #define CONDITIONAL_REGISTER_USAGE \
909 if (! TARGET_POWER) \
910 fixed_regs[64] = 1; \
912 fixed_regs[13] = call_used_regs[13] = 1; \
913 if (TARGET_SOFT_FLOAT) \
914 for (i = 32; i < 64; i++) \
915 fixed_regs[i] = call_used_regs[i] = 1; \
916 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
918 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
919 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
920 if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \
921 global_regs[PIC_OFFSET_TABLE_REGNUM] \
922 = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
923 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
924 if (TARGET_ALTIVEC_ABI) \
926 fixed_regs[VRSAVE_REGNO] = call_used_regs[VRSAVE_REGNO] = 1; \
927 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
928 call_used_regs[i] = 1; \
932 /* Specify the registers used for certain standard purposes.
933 The values of these macros are register numbers. */
935 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
936 /* #define PC_REGNUM */
938 /* Register to use for pushing function arguments. */
939 #define STACK_POINTER_REGNUM 1
941 /* Base register for access to local variables of the function. */
942 #define FRAME_POINTER_REGNUM 31
944 /* Value should be nonzero if functions must have frame pointers.
945 Zero means the frame pointer need not be set up (and parms
946 may be accessed via the stack pointer) in functions that seem suitable.
947 This is computed in `reload', in reload1.c. */
948 #define FRAME_POINTER_REQUIRED 0
950 /* Base register for access to arguments of the function. */
951 #define ARG_POINTER_REGNUM 67
953 /* Place to put static chain when calling a function that requires it. */
954 #define STATIC_CHAIN_REGNUM 11
956 /* Link register number. */
957 #define LINK_REGISTER_REGNUM 65
959 /* Count register number. */
960 #define COUNT_REGISTER_REGNUM 66
962 /* Place that structure value return address is placed.
964 On the RS/6000, it is passed as an extra parameter. */
965 #define STRUCT_VALUE 0
967 /* Define the classes of registers for register constraints in the
968 machine description. Also define ranges of constants.
970 One of the classes must always be named ALL_REGS and include all hard regs.
971 If there is more than one class, another class must be named NO_REGS
972 and contain no registers.
974 The name GENERAL_REGS must be the name of a class (or an alias for
975 another name such as ALL_REGS). This is the class of registers
976 that is allowed by "g" or "r" in a register constraint.
977 Also, registers outside this class are allocated only when
978 instructions express preferences for them.
980 The classes must be numbered in nondecreasing order; that is,
981 a larger-numbered class must never be contained completely
982 in a smaller-numbered class.
984 For any two classes, it is very desirable that there be another
985 class that represents their union. */
987 /* The RS/6000 has three types of registers, fixed-point, floating-point,
988 and condition registers, plus three special registers, MQ, CTR, and the
991 However, r0 is special in that it cannot be used as a base register.
992 So make a class for registers valid as base registers.
994 Also, cr0 is the only condition code register that can be used in
995 arithmetic insns, so make a separate class for it. */
1020 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1022 /* Give names of register classes as strings for dump file. */
1024 #define REG_CLASS_NAMES \
1032 "NON_SPECIAL_REGS", \
1036 "LINK_OR_CTR_REGS", \
1038 "SPEC_OR_GEN_REGS", \
1046 /* Define which registers fit in which classes.
1047 This is an initializer for a vector of HARD_REG_SET
1048 of length N_REG_CLASSES. */
1050 #define REG_CLASS_CONTENTS \
1052 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1053 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1054 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1055 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1056 { 0x00000000, 0x00000000, 0xffffe000, 0x0001ffff }, /* ALTIVEC_REGS */ \
1057 { 0x00000000, 0x00000000, 0x00000000, 0x00020000 }, /* VRSAVE_REGS */ \
1058 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1059 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1060 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1061 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1062 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1063 { 0x00000000, 0x00000000, 0x00000007, 0x00000000 }, /* SPECIAL_REGS */ \
1064 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1065 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1066 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1067 { 0xffffffff, 0x00000000, 0x0000ffff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1068 { 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, /* XER_REGS */ \
1069 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff } /* ALL_REGS */ \
1072 /* The same information, inverted:
1073 Return the class number of the smallest class containing
1074 reg number REGNO. This could be a conditional expression
1075 or could index an array. */
1077 #define REGNO_REG_CLASS(REGNO) \
1078 ((REGNO) == 0 ? GENERAL_REGS \
1079 : (REGNO) < 32 ? BASE_REGS \
1080 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1081 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1082 : (REGNO) == CR0_REGNO ? CR0_REGS \
1083 : CR_REGNO_P (REGNO) ? CR_REGS \
1084 : (REGNO) == MQ_REGNO ? MQ_REGS \
1085 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1086 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1087 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1088 : (REGNO) == XER_REGNO ? XER_REGS \
1089 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1092 /* The class value for index registers, and the one for base regs. */
1093 #define INDEX_REG_CLASS GENERAL_REGS
1094 #define BASE_REG_CLASS BASE_REGS
1096 /* Get reg_class from a letter such as appears in the machine description. */
1098 #define REG_CLASS_FROM_LETTER(C) \
1099 ((C) == 'f' ? FLOAT_REGS \
1100 : (C) == 'b' ? BASE_REGS \
1101 : (C) == 'h' ? SPECIAL_REGS \
1102 : (C) == 'q' ? MQ_REGS \
1103 : (C) == 'c' ? CTR_REGS \
1104 : (C) == 'l' ? LINK_REGS \
1105 : (C) == 'v' ? ALTIVEC_REGS \
1106 : (C) == 'x' ? CR0_REGS \
1107 : (C) == 'y' ? CR_REGS \
1108 : (C) == 'z' ? XER_REGS \
1111 /* The letters I, J, K, L, M, N, and P in a register constraint string
1112 can be used to stand for particular ranges of immediate operands.
1113 This macro defines what the ranges are.
1114 C is the letter, and VALUE is a constant value.
1115 Return 1 if VALUE is in the range specified by C.
1117 `I' is a signed 16-bit constant
1118 `J' is a constant with only the high-order 16 bits non-zero
1119 `K' is a constant with only the low-order 16 bits non-zero
1120 `L' is a signed 16-bit constant shifted left 16 bits
1121 `M' is a constant that is greater than 31
1122 `N' is a positive constant that is an exact power of two
1123 `O' is the constant zero
1124 `P' is a constant whose negation is a signed 16-bit constant */
1126 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1127 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1128 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1129 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1130 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1131 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1132 : (C) == 'M' ? (VALUE) > 31 \
1133 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1134 : (C) == 'O' ? (VALUE) == 0 \
1135 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1138 /* Similar, but for floating constants, and defining letters G and H.
1139 Here VALUE is the CONST_DOUBLE rtx itself.
1141 We flag for special constants when we can copy the constant into
1142 a general register in two insns for DF/DI and one insn for SF.
1144 'H' is used for DI/DF constants that take 3 insns. */
1146 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1147 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1148 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1149 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1152 /* Optional extra constraints for this machine.
1154 'Q' means that is a memory operand that is just an offset from a reg.
1155 'R' is for AIX TOC entries.
1156 'S' is a constant that can be placed into a 64-bit mask operand
1157 'T' is a consatnt that can be placed into a 32-bit mask operand
1158 'U' is for V.4 small data references. */
1160 #define EXTRA_CONSTRAINT(OP, C) \
1161 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1162 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1163 : (C) == 'S' ? mask64_operand (OP, VOIDmode) \
1164 : (C) == 'T' ? mask_operand (OP, VOIDmode) \
1165 : (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1166 && small_data_operand (OP, GET_MODE (OP))) \
1169 /* Given an rtx X being reloaded into a reg required to be
1170 in class CLASS, return the class of reg to actually use.
1171 In general this is just CLASS; but on some machines
1172 in some cases it is preferable to use a more restrictive class.
1174 On the RS/6000, we have to return NO_REGS when we want to reload a
1175 floating-point CONST_DOUBLE to force it to be copied to memory.
1177 We also don't want to reload integer values into floating-point
1178 registers if we can at all help it. In fact, this can
1179 cause reload to abort, if it tries to generate a reload of CTR
1180 into a FP register and discovers it doesn't have the memory location
1183 ??? Would it be a good idea to have reload do the converse, that is
1184 try to reload floating modes into FP registers if possible?
1187 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1188 (((GET_CODE (X) == CONST_DOUBLE \
1189 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1191 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1192 && (CLASS) == NON_SPECIAL_REGS) \
1196 /* Return the register class of a scratch register needed to copy IN into
1197 or out of a register in CLASS in MODE. If it can be done directly,
1198 NO_REGS is returned. */
1200 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1201 secondary_reload_class (CLASS, MODE, IN)
1203 /* If we are copying between FP or AltiVec registers and anything
1204 else, we need a memory location. */
1206 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1207 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1208 || (CLASS2) == FLOAT_REGS \
1209 || (CLASS1) == ALTIVEC_REGS \
1210 || (CLASS2) == ALTIVEC_REGS))
1212 /* Return the maximum number of consecutive registers
1213 needed to represent mode MODE in a register of class CLASS.
1215 On RS/6000, this is the size of MODE in words,
1216 except in the FP regs, where a single reg is enough for two words. */
1217 #define CLASS_MAX_NREGS(CLASS, MODE) \
1218 (((CLASS) == FLOAT_REGS) \
1219 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1220 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1222 /* If defined, gives a class of registers that cannot be used as the
1223 operand of a SUBREG that changes the mode of the object illegally. */
1225 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1227 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1229 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1230 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1232 /* Stack layout; function entry, exit and calling. */
1234 /* Enumeration to give which calling sequence to use. */
1237 ABI_AIX, /* IBM's AIX */
1238 ABI_AIX_NODESC, /* AIX calling sequence minus function descriptors */
1239 ABI_V4, /* System V.4/eabi */
1240 ABI_SOLARIS, /* Solaris */
1241 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1244 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1246 /* Structure used to define the rs6000 stack */
1247 typedef struct rs6000_stack {
1248 int first_gp_reg_save; /* first callee saved GP register used */
1249 int first_fp_reg_save; /* first callee saved FP register used */
1250 int lr_save_p; /* true if the link reg needs to be saved */
1251 int cr_save_p; /* true if the CR reg needs to be saved */
1252 int toc_save_p; /* true if the TOC needs to be saved */
1253 int push_p; /* true if we need to allocate stack space */
1254 int calls_p; /* true if the function makes any calls */
1255 enum rs6000_abi abi; /* which ABI to use */
1256 int gp_save_offset; /* offset to save GP regs from initial SP */
1257 int fp_save_offset; /* offset to save FP regs from initial SP */
1258 int lr_save_offset; /* offset to save LR from initial SP */
1259 int cr_save_offset; /* offset to save CR from initial SP */
1260 int toc_save_offset; /* offset to save the TOC pointer */
1261 int varargs_save_offset; /* offset to save the varargs registers */
1262 int ehrd_offset; /* offset to EH return data */
1263 int reg_size; /* register size (4 or 8) */
1264 int varargs_size; /* size to hold V.4 args passed in regs */
1265 int vars_size; /* variable save area size */
1266 int parm_size; /* outgoing parameter size */
1267 int save_size; /* save area size */
1268 int fixed_size; /* fixed size of stack frame */
1269 int gp_size; /* size of saved GP registers */
1270 int fp_size; /* size of saved FP registers */
1271 int cr_size; /* size to hold CR if not in save_size */
1272 int lr_size; /* size to hold LR if not in save_size */
1273 int toc_size; /* size to hold TOC if not in save_size */
1274 int total_size; /* total bytes allocated for stack */
1277 /* Define this if pushing a word on the stack
1278 makes the stack pointer a smaller address. */
1279 #define STACK_GROWS_DOWNWARD
1281 /* Define this if the nominal address of the stack frame
1282 is at the high-address end of the local variables;
1283 that is, each additional local variable allocated
1284 goes at a more negative offset in the frame.
1286 On the RS/6000, we grow upwards, from the area after the outgoing
1288 /* #define FRAME_GROWS_DOWNWARD */
1290 /* Size of the outgoing register save area */
1291 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1292 || DEFAULT_ABI == ABI_AIX_NODESC \
1293 || DEFAULT_ABI == ABI_DARWIN) \
1294 ? (TARGET_64BIT ? 64 : 32) \
1297 /* Size of the fixed area on the stack */
1298 #define RS6000_SAVE_AREA \
1299 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1300 << (TARGET_64BIT ? 1 : 0))
1302 /* MEM representing address to save the TOC register */
1303 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1304 plus_constant (stack_pointer_rtx, \
1305 (TARGET_32BIT ? 20 : 40)))
1307 /* Size of the V.4 varargs area if needed */
1308 #define RS6000_VARARGS_AREA 0
1310 /* Align an address */
1311 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1313 /* Size of V.4 varargs area in bytes */
1314 #define RS6000_VARARGS_SIZE \
1315 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1317 /* Offset within stack frame to start allocating local variables at.
1318 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1319 first local allocated. Otherwise, it is the offset to the BEGINNING
1320 of the first local allocated.
1322 On the RS/6000, the frame pointer is the same as the stack pointer,
1323 except for dynamic allocations. So we start after the fixed area and
1324 outgoing parameter area. */
1326 #define STARTING_FRAME_OFFSET \
1327 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1328 + RS6000_VARARGS_AREA \
1331 /* Offset from the stack pointer register to an item dynamically
1332 allocated on the stack, e.g., by `alloca'.
1334 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1335 length of the outgoing arguments. The default is correct for most
1336 machines. See `function.c' for details. */
1337 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1338 (RS6000_ALIGN (current_function_outgoing_args_size, 8) \
1339 + (STACK_POINTER_OFFSET))
1341 /* If we generate an insn to push BYTES bytes,
1342 this says how many the stack pointer really advances by.
1343 On RS/6000, don't define this because there are no push insns. */
1344 /* #define PUSH_ROUNDING(BYTES) */
1346 /* Offset of first parameter from the argument pointer register value.
1347 On the RS/6000, we define the argument pointer to the start of the fixed
1349 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1351 /* Offset from the argument pointer register value to the top of
1352 stack. This is different from FIRST_PARM_OFFSET because of the
1353 register save area. */
1354 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1356 /* Define this if stack space is still allocated for a parameter passed
1357 in a register. The value is the number of bytes allocated to this
1359 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1361 /* Define this if the above stack space is to be considered part of the
1362 space allocated by the caller. */
1363 #define OUTGOING_REG_PARM_STACK_SPACE
1365 /* This is the difference between the logical top of stack and the actual sp.
1367 For the RS/6000, sp points past the fixed area. */
1368 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1370 /* Define this if the maximum size of all the outgoing args is to be
1371 accumulated and pushed during the prologue. The amount can be
1372 found in the variable current_function_outgoing_args_size. */
1373 #define ACCUMULATE_OUTGOING_ARGS 1
1375 /* Value is the number of bytes of arguments automatically
1376 popped when returning from a subroutine call.
1377 FUNDECL is the declaration node of the function (as a tree),
1378 FUNTYPE is the data type of the function (as a tree),
1379 or for a library call it is an identifier node for the subroutine name.
1380 SIZE is the number of bytes of arguments passed on the stack. */
1382 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1384 /* Define how to find the value returned by a function.
1385 VALTYPE is the data type of the value (as a tree).
1386 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1387 otherwise, FUNC is 0.
1389 On RS/6000 an integer value is in r3 and a floating-point value is in
1390 fp1, unless -msoft-float. */
1392 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1393 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1394 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1395 || POINTER_TYPE_P (VALTYPE) \
1396 ? word_mode : TYPE_MODE (VALTYPE), \
1397 TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
1398 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1399 ? FP_ARG_RETURN : GP_ARG_RETURN)
1401 /* Define how to find the value returned by a library function
1402 assuming the value has mode MODE. */
1404 #define LIBCALL_VALUE(MODE) \
1405 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1406 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1407 && TARGET_HARD_FLOAT \
1408 ? FP_ARG_RETURN : GP_ARG_RETURN)
1410 /* The definition of this macro implies that there are cases where
1411 a scalar value cannot be returned in registers.
1413 For the RS/6000, any structure or union type is returned in memory, except for
1414 Solaris, which returns structures <= 8 bytes in registers. */
1416 #define RETURN_IN_MEMORY(TYPE) \
1417 (TYPE_MODE (TYPE) == BLKmode \
1418 && (DEFAULT_ABI != ABI_SOLARIS || int_size_in_bytes (TYPE) > 8))
1420 /* Mode of stack savearea.
1421 FUNCTION is VOIDmode because calling convention maintains SP.
1422 BLOCK needs Pmode for SP.
1423 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1424 #define STACK_SAVEAREA_MODE(LEVEL) \
1425 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1426 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1428 /* Minimum and maximum general purpose registers used to hold arguments. */
1429 #define GP_ARG_MIN_REG 3
1430 #define GP_ARG_MAX_REG 10
1431 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1433 /* Minimum and maximum floating point registers used to hold arguments. */
1434 #define FP_ARG_MIN_REG 33
1435 #define FP_ARG_AIX_MAX_REG 45
1436 #define FP_ARG_V4_MAX_REG 40
1437 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1438 || DEFAULT_ABI == ABI_AIX_NODESC \
1439 || DEFAULT_ABI == ABI_DARWIN) \
1440 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1441 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1443 /* Minimum and maximum AltiVec registers used to hold arguments. */
1444 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1445 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1446 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1448 /* Return registers */
1449 #define GP_ARG_RETURN GP_ARG_MIN_REG
1450 #define FP_ARG_RETURN FP_ARG_MIN_REG
1451 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1453 /* Flags for the call/call_value rtl operations set up by function_arg */
1454 #define CALL_NORMAL 0x00000000 /* no special processing */
1455 /* Bits in 0x00000001 are unused. */
1456 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1457 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1458 #define CALL_LONG 0x00000008 /* always call indirect */
1460 /* 1 if N is a possible register number for a function value
1461 as seen by the caller.
1463 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1464 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1465 || ((N) == FP_ARG_RETURN) \
1466 || (TARGET_ALTIVEC && \
1467 (N) == ALTIVEC_ARG_RETURN))
1469 /* 1 if N is a possible register number for function argument passing.
1470 On RS/6000, these are r3-r10 and fp1-fp13.
1471 On AltiVec, v2 - v13 are used for passing vectors. */
1472 #define FUNCTION_ARG_REGNO_P(N) \
1473 ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1474 || (TARGET_ALTIVEC && \
1475 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_MAX_REG)) \
1476 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1479 /* A C structure for machine-specific, per-function data.
1480 This is added to the cfun structure. */
1481 typedef struct machine_function
1483 /* Whether a System V.4 varargs area was created. */
1485 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1486 int ra_needs_full_frame;
1489 /* Define a data type for recording info about an argument list
1490 during the scan of that argument list. This data type should
1491 hold all necessary information about the function itself
1492 and about the args processed so far, enough to enable macros
1493 such as FUNCTION_ARG to determine where the next arg should go.
1495 On the RS/6000, this is a structure. The first element is the number of
1496 total argument words, the second is used to store the next
1497 floating-point register number, and the third says how many more args we
1498 have prototype types for.
1500 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1501 the next availible GP register, `fregno' is the next available FP
1502 register, and `words' is the number of words used on the stack.
1504 The varargs/stdarg support requires that this structure's size
1505 be a multiple of sizeof(int). */
1507 typedef struct rs6000_args
1509 int words; /* # words used for passing GP registers */
1510 int fregno; /* next available FP register */
1511 int vregno; /* next available AltiVec register */
1512 int nargs_prototype; /* # args left in the current prototype */
1513 int orig_nargs; /* Original value of nargs_prototype */
1514 int prototype; /* Whether a prototype was defined */
1515 int call_cookie; /* Do special things for this call */
1516 int sysv_gregno; /* next available GP register */
1519 /* Define intermediate macro to compute the size (in registers) of an argument
1522 #define RS6000_ARG_SIZE(MODE, TYPE) \
1523 ((MODE) != BLKmode \
1524 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1525 : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1526 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1528 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1529 for a call to a function whose data type is FNTYPE.
1530 For a library call, FNTYPE is 0. */
1532 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1533 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1535 /* Similar, but when scanning the definition of a procedure. We always
1536 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1538 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1539 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1541 /* Update the data in CUM to advance over an argument
1542 of mode MODE and data type TYPE.
1543 (TYPE is null for libcalls where that information may not be available.) */
1545 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1546 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1548 /* Non-zero if we can use a floating-point register to pass this arg. */
1549 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1550 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1551 && (CUM).fregno <= FP_ARG_MAX_REG \
1552 && TARGET_HARD_FLOAT)
1554 /* Non-zero if we can use an AltiVec register to pass this arg. */
1555 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1556 (ALTIVEC_VECTOR_MODE (MODE) \
1557 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1558 && TARGET_ALTIVEC_ABI)
1560 /* Determine where to put an argument to a function.
1561 Value is zero to push the argument on the stack,
1562 or a hard register in which to store the argument.
1564 MODE is the argument's machine mode.
1565 TYPE is the data type of the argument (as a tree).
1566 This is null for libcalls where that information may
1568 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1569 the preceding args and about the function being called.
1570 NAMED is nonzero if this argument is a named parameter
1571 (otherwise it is an extra parameter matching an ellipsis).
1573 On RS/6000 the first eight words of non-FP are normally in registers
1574 and the rest are pushed. The first 13 FP args are in registers.
1576 If this is floating-point and no prototype is specified, we use
1577 both an FP and integer register (or possibly FP reg and stack). Library
1578 functions (when TYPE is zero) always have the proper types for args,
1579 so we can pass the FP value just in one register. emit_library_function
1580 doesn't support EXPR_LIST anyway. */
1582 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1583 function_arg (&CUM, MODE, TYPE, NAMED)
1585 /* For an arg passed partly in registers and partly in memory,
1586 this is the number of registers used.
1587 For args passed entirely in registers or entirely in memory, zero. */
1589 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1590 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1592 /* A C expression that indicates when an argument must be passed by
1593 reference. If nonzero for an argument, a copy of that argument is
1594 made in memory and a pointer to the argument is passed instead of
1595 the argument itself. The pointer is passed in whatever way is
1596 appropriate for passing a pointer to that type. */
1598 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1599 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1601 /* If defined, a C expression which determines whether, and in which
1602 direction, to pad out an argument with extra space. The value
1603 should be of type `enum direction': either `upward' to pad above
1604 the argument, `downward' to pad below, or `none' to inhibit
1607 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1609 /* If defined, a C expression that gives the alignment boundary, in bits,
1610 of an argument with the specified mode and type. If it is not defined,
1611 PARM_BOUNDARY is used for all arguments. */
1613 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1614 function_arg_boundary (MODE, TYPE)
1616 /* Perform any needed actions needed for a function that is receiving a
1617 variable number of arguments.
1621 MODE and TYPE are the mode and type of the current parameter.
1623 PRETEND_SIZE is a variable that should be set to the amount of stack
1624 that must be pushed by the prolog to pretend that our caller pushed
1627 Normally, this macro will push all remaining incoming registers on the
1628 stack and set PRETEND_SIZE to the length of the registers pushed. */
1630 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1631 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1633 /* Define the `__builtin_va_list' type for the ABI. */
1634 #define BUILD_VA_LIST_TYPE(VALIST) \
1635 (VALIST) = rs6000_build_va_list ()
1637 /* Implement `va_start' for varargs and stdarg. */
1638 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1639 rs6000_va_start (stdarg, valist, nextarg)
1641 /* Implement `va_arg'. */
1642 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1643 rs6000_va_arg (valist, type)
1645 /* Define this macro to be a nonzero value if the location where a function
1646 argument is passed depends on whether or not it is a named argument. */
1647 #define STRICT_ARGUMENT_NAMING 1
1649 /* Output assembler code to FILE to increment profiler label # LABELNO
1650 for profiling a function entry. */
1652 #define FUNCTION_PROFILER(FILE, LABELNO) \
1653 output_function_profiler ((FILE), (LABELNO));
1655 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1656 the stack pointer does not matter. No definition is equivalent to
1659 On the RS/6000, this is non-zero because we can restore the stack from
1660 its backpointer, which we maintain. */
1661 #define EXIT_IGNORE_STACK 1
1663 /* Define this macro as a C expression that is nonzero for registers
1664 that are used by the epilogue or the return' pattern. The stack
1665 and frame pointer registers are already be assumed to be used as
1668 #define EPILOGUE_USES(REGNO) \
1669 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1670 || (current_function_calls_eh_return \
1672 && (REGNO) == TOC_REGISTER))
1675 /* TRAMPOLINE_TEMPLATE deleted */
1677 /* Length in units of the trampoline for entering a nested function. */
1679 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1681 /* Emit RTL insns to initialize the variable parts of a trampoline.
1682 FNADDR is an RTX for the address of the function's pure code.
1683 CXT is an RTX for the static chain value for the function. */
1685 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1686 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1688 /* Definitions for __builtin_return_address and __builtin_frame_address.
1689 __builtin_return_address (0) should give link register (65), enable
1691 /* This should be uncommented, so that the link register is used, but
1692 currently this would result in unmatched insns and spilling fixed
1693 registers so we'll leave it for another day. When these problems are
1694 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1696 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1698 /* Number of bytes into the frame return addresses can be found. See
1699 rs6000_stack_info in rs6000.c for more information on how the different
1700 abi's store the return address. */
1701 #define RETURN_ADDRESS_OFFSET \
1702 ((DEFAULT_ABI == ABI_AIX \
1703 || DEFAULT_ABI == ABI_DARWIN \
1704 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1705 (DEFAULT_ABI == ABI_V4 \
1706 || DEFAULT_ABI == ABI_SOLARIS) ? (TARGET_32BIT ? 4 : 8) : \
1707 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1709 /* The current return address is in link register (65). The return address
1710 of anything farther back is accessed normally at an offset of 8 from the
1712 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1713 (rs6000_return_addr (COUNT, FRAME))
1716 /* Definitions for register eliminations.
1718 We have two registers that can be eliminated on the RS/6000. First, the
1719 frame pointer register can often be eliminated in favor of the stack
1720 pointer register. Secondly, the argument pointer register can always be
1721 eliminated; it is replaced with either the stack or frame pointer.
1723 In addition, we use the elimination mechanism to see if r30 is needed
1724 Initially we assume that it isn't. If it is, we spill it. This is done
1725 by making it an eliminable register. We replace it with itself so that
1726 if it isn't needed, then existing uses won't be modified. */
1728 /* This is an array of structures. Each structure initializes one pair
1729 of eliminable registers. The "from" register number is given first,
1730 followed by "to". Eliminations of the same "from" register are listed
1731 in order of preference. */
1732 #define ELIMINABLE_REGS \
1733 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1734 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1735 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1738 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1739 Frame pointer elimination is automatically handled.
1741 For the RS/6000, if frame pointer elimination is being done, we would like
1742 to convert ap into fp, not sp.
1744 We need r30 if -mminimal-toc was specified, and there are constant pool
1747 #define CAN_ELIMINATE(FROM, TO) \
1748 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1749 ? ! frame_pointer_needed \
1750 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1753 /* Define the offset between two registers, one to be eliminated, and the other
1754 its replacement, at the start of a routine. */
1755 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1757 rs6000_stack_t *info = rs6000_stack_info (); \
1759 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1760 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1761 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1762 (OFFSET) = info->total_size; \
1763 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1764 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1765 else if ((FROM) == 30) \
1771 /* Addressing modes, and classification of registers for them. */
1773 /* #define HAVE_POST_INCREMENT 0 */
1774 /* #define HAVE_POST_DECREMENT 0 */
1776 #define HAVE_PRE_DECREMENT 1
1777 #define HAVE_PRE_INCREMENT 1
1779 /* Macros to check register numbers against specific register classes. */
1781 /* These assume that REGNO is a hard or pseudo reg number.
1782 They give nonzero only if REGNO is a hard reg of the suitable class
1783 or a pseudo reg currently allocated to a suitable hard reg.
1784 Since they use reg_renumber, they are safe only once reg_renumber
1785 has been allocated, which happens in local-alloc.c. */
1787 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1788 ((REGNO) < FIRST_PSEUDO_REGISTER \
1789 ? (REGNO) <= 31 || (REGNO) == 67 \
1790 : (reg_renumber[REGNO] >= 0 \
1791 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1793 #define REGNO_OK_FOR_BASE_P(REGNO) \
1794 ((REGNO) < FIRST_PSEUDO_REGISTER \
1795 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1796 : (reg_renumber[REGNO] > 0 \
1797 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1799 /* Maximum number of registers that can appear in a valid memory address. */
1801 #define MAX_REGS_PER_ADDRESS 2
1803 /* Recognize any constant value that is a valid address. */
1805 #define CONSTANT_ADDRESS_P(X) \
1806 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1807 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1808 || GET_CODE (X) == HIGH)
1810 /* Nonzero if the constant value X is a legitimate general operand.
1811 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1813 On the RS/6000, all integer constants are acceptable, most won't be valid
1814 for particular insns, though. Only easy FP constants are
1817 #define LEGITIMATE_CONSTANT_P(X) \
1818 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1819 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1820 || easy_fp_constant (X, GET_MODE (X)))
1822 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1823 and check its validity for a certain class.
1824 We have two alternate definitions for each of them.
1825 The usual definition accepts all pseudo regs; the other rejects
1826 them unless they have been allocated suitable hard regs.
1827 The symbol REG_OK_STRICT causes the latter definition to be used.
1829 Most source files want to accept pseudo regs in the hope that
1830 they will get allocated to the class that the insn wants them to be in.
1831 Source files for reload pass need to be strict.
1832 After reload, it makes no difference, since pseudo regs have
1833 been eliminated by then. */
1835 #ifdef REG_OK_STRICT
1836 # define REG_OK_STRICT_FLAG 1
1838 # define REG_OK_STRICT_FLAG 0
1841 /* Nonzero if X is a hard reg that can be used as an index
1842 or if it is a pseudo reg in the non-strict case. */
1843 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1845 && (REGNO (X) <= 31 \
1846 || REGNO (X) == ARG_POINTER_REGNUM \
1847 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1848 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1850 /* Nonzero if X is a hard reg that can be used as a base reg
1851 or if it is a pseudo reg in the non-strict case. */
1852 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1853 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1855 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1856 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1858 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1859 that is a valid memory address for an instruction.
1860 The MODE argument is the machine mode for the MEM expression
1861 that wants to use this address.
1863 On the RS/6000, there are four valid address: a SYMBOL_REF that
1864 refers to a constant pool entry of an address (or the sum of it
1865 plus a constant), a short (16-bit signed) constant plus a register,
1866 the sum of two registers, or a register indirect, possibly with an
1867 auto-increment. For DFmode and DImode with an constant plus register,
1868 we must ensure that both words are addressable or PowerPC64 with offset
1871 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1872 32-bit DImode, TImode), indexed addressing cannot be used because
1873 adjacent memory cells are accessed by adding word-sized offsets
1874 during assembly output. */
1876 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1878 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1880 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1882 && GET_CODE (X) == PLUS \
1883 && GET_CODE (XEXP (X, 0)) == REG \
1884 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1885 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1887 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1888 ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
1889 && !flag_pic && !TARGET_TOC \
1890 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1891 && small_data_operand (X, MODE))
1893 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1894 (GET_CODE (X) == CONST_INT \
1895 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1897 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1898 (GET_CODE (X) == PLUS \
1899 && GET_CODE (XEXP (X, 0)) == REG \
1900 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1901 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1902 && (! ALTIVEC_VECTOR_MODE (MODE) || INTVAL (X) == 0) \
1903 && (((MODE) != DFmode && (MODE) != DImode) \
1905 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1906 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1907 && ((MODE) != TImode \
1909 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1910 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
1911 && ! (INTVAL (XEXP (X, 1)) & 3)))))
1913 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
1914 (GET_CODE (X) == PLUS \
1915 && GET_CODE (XEXP (X, 0)) == REG \
1916 && GET_CODE (XEXP (X, 1)) == REG \
1917 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1918 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
1919 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
1920 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
1922 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
1923 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
1925 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
1927 && ! flag_pic && ! TARGET_TOC \
1928 && (MODE) != DImode \
1929 && (MODE) != TImode \
1930 && ! ALTIVEC_VECTOR_MODE (MODE) \
1931 && (TARGET_HARD_FLOAT || (MODE) != DFmode) \
1932 && GET_CODE (X) == LO_SUM \
1933 && GET_CODE (XEXP (X, 0)) == REG \
1934 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1935 && CONSTANT_P (XEXP (X, 1)))
1937 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1938 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1942 /* Try machine-dependent ways of modifying an illegitimate address
1943 to be legitimate. If we find one, return the new, valid address.
1944 This macro is used in only one place: `memory_address' in explow.c.
1946 OLDX is the address as it was before break_out_memory_refs was called.
1947 In some cases it is useful to look at this to decide what needs to be done.
1949 MODE and WIN are passed so that this macro can use
1950 GO_IF_LEGITIMATE_ADDRESS.
1952 It is always safe for this macro to do nothing. It exists to recognize
1953 opportunities to optimize the output.
1955 On RS/6000, first check for the sum of a register with a constant
1956 integer that is out of range. If so, generate code to add the
1957 constant with the low-order 16 bits masked to the register and force
1958 this result into another register (this can be done with `cau').
1959 Then generate an address of REG+(CONST&0xffff), allowing for the
1960 possibility of bit 16 being a one.
1962 Then check for the sum of a register and something not constant, try to
1963 load the other things into a register and return the sum. */
1965 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1966 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1967 if (result != NULL_RTX) \
1974 /* Try a machine-dependent way of reloading an illegitimate address
1975 operand. If we find one, push the reload and jump to WIN. This
1976 macro is used in only one place: `find_reloads_address' in reload.c.
1978 For RS/6000, we wish to handle large displacements off a base
1979 register by splitting the addend across an addiu/addis and the mem insn.
1980 This cuts number of extra insns needed from 3 to 1. */
1982 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1984 /* We must recognize output that we have already generated ourselves. */ \
1985 if (GET_CODE (X) == PLUS \
1986 && GET_CODE (XEXP (X, 0)) == PLUS \
1987 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1988 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1989 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1991 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1992 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1996 if (GET_CODE (X) == PLUS \
1997 && GET_CODE (XEXP (X, 0)) == REG \
1998 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1999 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
2000 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2002 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2003 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
2004 HOST_WIDE_INT high \
2005 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
2007 /* Check for 32-bit overflow. */ \
2008 if (high + low != val) \
2011 /* Reload the high part into a base reg; leave the low part \
2012 in the mem directly. */ \
2014 X = gen_rtx_PLUS (GET_MODE (X), \
2015 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
2019 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2020 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2024 else if (TARGET_TOC \
2025 && CONSTANT_POOL_EXPR_P (X) \
2026 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \
2028 (X) = create_TOC_reference (X); \
2033 /* Go to LABEL if ADDR (a legitimate address expression)
2034 has an effect that depends on the machine mode it is used for.
2036 On the RS/6000 this is true if the address is valid with a zero offset
2037 but not with an offset of four (this means it cannot be used as an
2038 address for DImode or DFmode) or is a pre-increment or decrement. Since
2039 we know it is valid, we just check for an address that is not valid with
2040 an offset of four. */
2042 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2043 { if (GET_CODE (ADDR) == PLUS \
2044 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2045 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2046 (TARGET_32BIT ? 4 : 8))) \
2048 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2050 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2052 if (GET_CODE (ADDR) == LO_SUM) \
2056 /* The register number of the register used to address a table of
2057 static data addresses in memory. In some cases this register is
2058 defined by a processor's "application binary interface" (ABI).
2059 When this macro is defined, RTL is generated for this register
2060 once, as with the stack pointer and frame pointer registers. If
2061 this macro is not defined, it is up to the machine-dependent files
2062 to allocate such a register (if necessary). */
2064 #define PIC_OFFSET_TABLE_REGNUM 30
2066 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2068 /* Define this macro if the register defined by
2069 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2070 this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */
2072 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2074 /* By generating position-independent code, when two different
2075 programs (A and B) share a common library (libC.a), the text of
2076 the library can be shared whether or not the library is linked at
2077 the same address for both programs. In some of these
2078 environments, position-independent code requires not only the use
2079 of different addressing modes, but also special code to enable the
2080 use of these addressing modes.
2082 The `FINALIZE_PIC' macro serves as a hook to emit these special
2083 codes once the function is being compiled into assembly code, but
2084 not before. (It is not done before, because in the case of
2085 compiling an inline function, it would lead to multiple PIC
2086 prologues being included in functions which used inline functions
2087 and were compiled to assembly language.) */
2089 /* #define FINALIZE_PIC */
2091 /* A C expression that is nonzero if X is a legitimate immediate
2092 operand on the target machine when generating position independent
2093 code. You can assume that X satisfies `CONSTANT_P', so you need
2094 not check this. You can also assume FLAG_PIC is true, so you need
2095 not check it either. You need not define this macro if all
2096 constants (including `SYMBOL_REF') can be immediate operands when
2097 generating position independent code. */
2099 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2101 /* In rare cases, correct code generation requires extra machine
2102 dependent processing between the second jump optimization pass and
2103 delayed branch scheduling. On those machines, define this macro
2104 as a C statement to act on the code starting at INSN. */
2106 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2109 /* Define this if some processing needs to be done immediately before
2110 emitting code for an insn. */
2112 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2114 /* Specify the machine mode that this machine uses
2115 for the index in the tablejump instruction. */
2116 #define CASE_VECTOR_MODE SImode
2118 /* Define as C expression which evaluates to nonzero if the tablejump
2119 instruction expects the table to contain offsets from the address of the
2121 Do not define this if the table should contain absolute addresses. */
2122 #define CASE_VECTOR_PC_RELATIVE 1
2124 /* Specify the tree operation to be used to convert reals to integers. */
2125 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2127 /* This is the kind of divide that is easiest to do in the general case. */
2128 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2130 /* Define this as 1 if `char' should by default be signed; else as 0. */
2131 #define DEFAULT_SIGNED_CHAR 0
2133 /* This flag, if defined, says the same insns that convert to a signed fixnum
2134 also convert validly to an unsigned one. */
2136 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2138 /* Max number of bytes we can move from memory to memory
2139 in one reasonably fast instruction. */
2140 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2141 #define MAX_MOVE_MAX 8
2143 /* Nonzero if access to memory by bytes is no faster than for words.
2144 Also non-zero if doing byte operations (specifically shifts) in registers
2146 #define SLOW_BYTE_ACCESS 1
2148 /* Define if operations between registers always perform the operation
2149 on the full register even if a narrower mode is specified. */
2150 #define WORD_REGISTER_OPERATIONS
2152 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2153 will either zero-extend or sign-extend. The value of this macro should
2154 be the code that says which one of the two operations is implicitly
2155 done, NIL if none. */
2156 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2158 /* Define if loading short immediate values into registers sign extends. */
2159 #define SHORT_IMMEDIATES_SIGN_EXTEND
2161 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2162 is done just by pretending it is already truncated. */
2163 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2165 /* Specify the machine mode that pointers have.
2166 After generation of rtl, the compiler makes no further distinction
2167 between pointers and any other objects of this machine mode. */
2168 #define Pmode (TARGET_32BIT ? SImode : DImode)
2170 /* Mode of a function address in a call instruction (for indexing purposes).
2171 Doesn't matter on RS/6000. */
2172 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2174 /* Define this if addresses of constant functions
2175 shouldn't be put through pseudo regs where they can be cse'd.
2176 Desirable on machines where ordinary constants are expensive
2177 but a CALL with constant address is cheap. */
2178 #define NO_FUNCTION_CSE
2180 /* Define this to be nonzero if shift instructions ignore all but the low-order
2183 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2184 have been dropped from the PowerPC architecture. */
2186 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2188 /* Compute the cost of computing a constant rtl expression RTX
2189 whose rtx-code is CODE. The body of this macro is a portion
2190 of a switch statement. If the code is computed here,
2191 return it with a return statement. Otherwise, break from the switch.
2193 On the RS/6000, if it is valid in the insn, it is free. So this
2194 always returns 0. */
2196 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2201 case CONST_DOUBLE: \
2205 /* Provide the costs of a rtl expression. This is in the body of a
2208 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2210 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2211 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2212 + 0x8000) >= 0x10000) \
2213 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2214 ? COSTS_N_INSNS (2) \
2215 : COSTS_N_INSNS (1)); \
2219 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2220 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2221 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2222 ? COSTS_N_INSNS (2) \
2223 : COSTS_N_INSNS (1)); \
2225 switch (rs6000_cpu) \
2227 case PROCESSOR_RIOS1: \
2228 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2229 ? COSTS_N_INSNS (5) \
2230 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2231 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2232 case PROCESSOR_RS64A: \
2233 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2234 ? GET_MODE (XEXP (X, 1)) != DImode \
2235 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2236 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2237 ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
2238 case PROCESSOR_RIOS2: \
2239 case PROCESSOR_MPCCORE: \
2240 case PROCESSOR_PPC604e: \
2241 return COSTS_N_INSNS (2); \
2242 case PROCESSOR_PPC601: \
2243 return COSTS_N_INSNS (5); \
2244 case PROCESSOR_PPC7400: \
2245 case PROCESSOR_PPC7450: \
2246 case PROCESSOR_PPC603: \
2247 case PROCESSOR_PPC750: \
2248 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2249 ? COSTS_N_INSNS (5) \
2250 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2251 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2252 case PROCESSOR_PPC403: \
2253 case PROCESSOR_PPC604: \
2254 return COSTS_N_INSNS (4); \
2255 case PROCESSOR_PPC620: \
2256 case PROCESSOR_PPC630: \
2257 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2258 ? GET_MODE (XEXP (X, 1)) != DImode \
2259 ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
2260 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2261 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2265 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2266 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2267 return COSTS_N_INSNS (2); \
2268 /* otherwise fall through to normal divide. */ \
2271 switch (rs6000_cpu) \
2273 case PROCESSOR_RIOS1: \
2274 return COSTS_N_INSNS (19); \
2275 case PROCESSOR_RIOS2: \
2276 return COSTS_N_INSNS (13); \
2277 case PROCESSOR_RS64A: \
2278 return (GET_MODE (XEXP (X, 1)) != DImode \
2279 ? COSTS_N_INSNS (65) \
2280 : COSTS_N_INSNS (67)); \
2281 case PROCESSOR_MPCCORE: \
2282 return COSTS_N_INSNS (6); \
2283 case PROCESSOR_PPC403: \
2284 return COSTS_N_INSNS (33); \
2285 case PROCESSOR_PPC601: \
2286 return COSTS_N_INSNS (36); \
2287 case PROCESSOR_PPC603: \
2288 return COSTS_N_INSNS (37); \
2289 case PROCESSOR_PPC604: \
2290 case PROCESSOR_PPC604e: \
2291 return COSTS_N_INSNS (20); \
2292 case PROCESSOR_PPC620: \
2293 case PROCESSOR_PPC630: \
2294 return (GET_MODE (XEXP (X, 1)) != DImode \
2295 ? COSTS_N_INSNS (21) \
2296 : COSTS_N_INSNS (37)); \
2297 case PROCESSOR_PPC750: \
2298 case PROCESSOR_PPC7400: \
2299 return COSTS_N_INSNS (19); \
2300 case PROCESSOR_PPC7450: \
2301 return COSTS_N_INSNS (23); \
2304 return COSTS_N_INSNS (4); \
2306 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2309 /* Compute the cost of an address. This is meant to approximate the size
2310 and/or execution delay of an insn using that address. If the cost is
2311 approximated by the RTL complexity, including CONST_COSTS above, as
2312 is usually the case for CISC machines, this macro should not be defined.
2313 For aggressively RISCy machines, only one insn format is allowed, so
2314 this macro should be a constant. The value of this macro only matters
2315 for valid addresses.
2317 For the RS/6000, everything is cost 0. */
2319 #define ADDRESS_COST(RTX) 0
2321 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2322 should be adjusted to reflect any required changes. This macro is used when
2323 there is some systematic length adjustment required that would be difficult
2324 to express in the length attribute. */
2326 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2328 /* Add any extra modes needed to represent the condition code.
2330 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2331 are being done and we need a separate mode for floating-point. We also
2332 use a mode for the case when we are comparing the results of two
2333 comparisons, as then only the EQ bit is valid in the register. */
2335 #define EXTRA_CC_MODES \
2336 CC(CCUNSmode, "CCUNS") \
2337 CC(CCFPmode, "CCFP") \
2338 CC(CCEQmode, "CCEQ")
2340 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2341 COMPARE, return the mode to be used for the comparison. For
2342 floating-point, CCFPmode should be used. CCUNSmode should be used
2343 for unsigned comparisons. CCEQmode should be used when we are
2344 doing an inequality comparison on the result of a
2345 comparison. CCmode should be used in all other cases. */
2347 #define SELECT_CC_MODE(OP,X,Y) \
2348 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2349 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2350 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2351 ? CCEQmode : CCmode))
2353 /* Define the information needed to generate branch and scc insns. This is
2354 stored from the compare operation. Note that we can't use "rtx" here
2355 since it hasn't been defined! */
2357 extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
2358 extern int rs6000_compare_fp_p;
2360 /* Control the assembler format that we output. */
2362 /* A C string constant describing how to begin a comment in the target
2363 assembler language. The compiler assumes that the comment will end at
2364 the end of the line. */
2365 #define ASM_COMMENT_START " #"
2367 /* Implicit library calls should use memcpy, not bcopy, etc. */
2369 #define TARGET_MEM_FUNCTIONS
2371 /* Flag to say the TOC is initialized */
2372 extern int toc_initialized;
2374 /* Macro to output a special constant pool entry. Go to WIN if we output
2375 it. Otherwise, it is written the usual way.
2377 On the RS/6000, toc entries are handled this way. */
2379 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2380 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2382 output_toc (FILE, X, LABELNO, MODE); \
2387 /* This implementes the `alias' attribute. */
2389 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \
2391 const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2392 char * name = IDENTIFIER_POINTER (target); \
2393 if (TREE_CODE (decl) == FUNCTION_DECL \
2394 && DEFAULT_ABI == ABI_AIX) \
2396 if (TREE_PUBLIC (decl)) \
2398 fputs ("\t.globl .", FILE); \
2399 assemble_name (FILE, alias); \
2400 putc ('\n', FILE); \
2404 fputs ("\t.lglobl .", FILE); \
2405 assemble_name (FILE, alias); \
2406 putc ('\n', FILE); \
2408 fputs ("\t.set .", FILE); \
2409 assemble_name (FILE, alias); \
2410 fputs (",.", FILE); \
2411 assemble_name (FILE, name); \
2412 fputc ('\n', FILE); \
2414 ASM_OUTPUT_DEF (FILE, alias, name); \
2417 /* Output to assembler file text saying following lines
2418 may contain character constants, extra white space, comments, etc. */
2420 #define ASM_APP_ON ""
2422 /* Output to assembler file text saying following lines
2423 no longer contain unusual constructs. */
2425 #define ASM_APP_OFF ""
2427 /* How to refer to registers in assembler output.
2428 This sequence is indexed by compiler's hard-register-number (see above). */
2430 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2432 #define REGISTER_NAMES \
2434 &rs6000_reg_names[ 0][0], /* r0 */ \
2435 &rs6000_reg_names[ 1][0], /* r1 */ \
2436 &rs6000_reg_names[ 2][0], /* r2 */ \
2437 &rs6000_reg_names[ 3][0], /* r3 */ \
2438 &rs6000_reg_names[ 4][0], /* r4 */ \
2439 &rs6000_reg_names[ 5][0], /* r5 */ \
2440 &rs6000_reg_names[ 6][0], /* r6 */ \
2441 &rs6000_reg_names[ 7][0], /* r7 */ \
2442 &rs6000_reg_names[ 8][0], /* r8 */ \
2443 &rs6000_reg_names[ 9][0], /* r9 */ \
2444 &rs6000_reg_names[10][0], /* r10 */ \
2445 &rs6000_reg_names[11][0], /* r11 */ \
2446 &rs6000_reg_names[12][0], /* r12 */ \
2447 &rs6000_reg_names[13][0], /* r13 */ \
2448 &rs6000_reg_names[14][0], /* r14 */ \
2449 &rs6000_reg_names[15][0], /* r15 */ \
2450 &rs6000_reg_names[16][0], /* r16 */ \
2451 &rs6000_reg_names[17][0], /* r17 */ \
2452 &rs6000_reg_names[18][0], /* r18 */ \
2453 &rs6000_reg_names[19][0], /* r19 */ \
2454 &rs6000_reg_names[20][0], /* r20 */ \
2455 &rs6000_reg_names[21][0], /* r21 */ \
2456 &rs6000_reg_names[22][0], /* r22 */ \
2457 &rs6000_reg_names[23][0], /* r23 */ \
2458 &rs6000_reg_names[24][0], /* r24 */ \
2459 &rs6000_reg_names[25][0], /* r25 */ \
2460 &rs6000_reg_names[26][0], /* r26 */ \
2461 &rs6000_reg_names[27][0], /* r27 */ \
2462 &rs6000_reg_names[28][0], /* r28 */ \
2463 &rs6000_reg_names[29][0], /* r29 */ \
2464 &rs6000_reg_names[30][0], /* r30 */ \
2465 &rs6000_reg_names[31][0], /* r31 */ \
2467 &rs6000_reg_names[32][0], /* fr0 */ \
2468 &rs6000_reg_names[33][0], /* fr1 */ \
2469 &rs6000_reg_names[34][0], /* fr2 */ \
2470 &rs6000_reg_names[35][0], /* fr3 */ \
2471 &rs6000_reg_names[36][0], /* fr4 */ \
2472 &rs6000_reg_names[37][0], /* fr5 */ \
2473 &rs6000_reg_names[38][0], /* fr6 */ \
2474 &rs6000_reg_names[39][0], /* fr7 */ \
2475 &rs6000_reg_names[40][0], /* fr8 */ \
2476 &rs6000_reg_names[41][0], /* fr9 */ \
2477 &rs6000_reg_names[42][0], /* fr10 */ \
2478 &rs6000_reg_names[43][0], /* fr11 */ \
2479 &rs6000_reg_names[44][0], /* fr12 */ \
2480 &rs6000_reg_names[45][0], /* fr13 */ \
2481 &rs6000_reg_names[46][0], /* fr14 */ \
2482 &rs6000_reg_names[47][0], /* fr15 */ \
2483 &rs6000_reg_names[48][0], /* fr16 */ \
2484 &rs6000_reg_names[49][0], /* fr17 */ \
2485 &rs6000_reg_names[50][0], /* fr18 */ \
2486 &rs6000_reg_names[51][0], /* fr19 */ \
2487 &rs6000_reg_names[52][0], /* fr20 */ \
2488 &rs6000_reg_names[53][0], /* fr21 */ \
2489 &rs6000_reg_names[54][0], /* fr22 */ \
2490 &rs6000_reg_names[55][0], /* fr23 */ \
2491 &rs6000_reg_names[56][0], /* fr24 */ \
2492 &rs6000_reg_names[57][0], /* fr25 */ \
2493 &rs6000_reg_names[58][0], /* fr26 */ \
2494 &rs6000_reg_names[59][0], /* fr27 */ \
2495 &rs6000_reg_names[60][0], /* fr28 */ \
2496 &rs6000_reg_names[61][0], /* fr29 */ \
2497 &rs6000_reg_names[62][0], /* fr30 */ \
2498 &rs6000_reg_names[63][0], /* fr31 */ \
2500 &rs6000_reg_names[64][0], /* mq */ \
2501 &rs6000_reg_names[65][0], /* lr */ \
2502 &rs6000_reg_names[66][0], /* ctr */ \
2503 &rs6000_reg_names[67][0], /* ap */ \
2505 &rs6000_reg_names[68][0], /* cr0 */ \
2506 &rs6000_reg_names[69][0], /* cr1 */ \
2507 &rs6000_reg_names[70][0], /* cr2 */ \
2508 &rs6000_reg_names[71][0], /* cr3 */ \
2509 &rs6000_reg_names[72][0], /* cr4 */ \
2510 &rs6000_reg_names[73][0], /* cr5 */ \
2511 &rs6000_reg_names[74][0], /* cr6 */ \
2512 &rs6000_reg_names[75][0], /* cr7 */ \
2514 &rs6000_reg_names[76][0], /* xer */ \
2516 &rs6000_reg_names[77][0], /* v0 */ \
2517 &rs6000_reg_names[78][0], /* v1 */ \
2518 &rs6000_reg_names[79][0], /* v2 */ \
2519 &rs6000_reg_names[80][0], /* v3 */ \
2520 &rs6000_reg_names[81][0], /* v4 */ \
2521 &rs6000_reg_names[82][0], /* v5 */ \
2522 &rs6000_reg_names[83][0], /* v6 */ \
2523 &rs6000_reg_names[84][0], /* v7 */ \
2524 &rs6000_reg_names[85][0], /* v8 */ \
2525 &rs6000_reg_names[86][0], /* v9 */ \
2526 &rs6000_reg_names[87][0], /* v10 */ \
2527 &rs6000_reg_names[88][0], /* v11 */ \
2528 &rs6000_reg_names[89][0], /* v12 */ \
2529 &rs6000_reg_names[90][0], /* v13 */ \
2530 &rs6000_reg_names[91][0], /* v14 */ \
2531 &rs6000_reg_names[92][0], /* v15 */ \
2532 &rs6000_reg_names[93][0], /* v16 */ \
2533 &rs6000_reg_names[94][0], /* v17 */ \
2534 &rs6000_reg_names[95][0], /* v18 */ \
2535 &rs6000_reg_names[96][0], /* v19 */ \
2536 &rs6000_reg_names[97][0], /* v20 */ \
2537 &rs6000_reg_names[98][0], /* v21 */ \
2538 &rs6000_reg_names[99][0], /* v22 */ \
2539 &rs6000_reg_names[100][0], /* v23 */ \
2540 &rs6000_reg_names[101][0], /* v24 */ \
2541 &rs6000_reg_names[102][0], /* v25 */ \
2542 &rs6000_reg_names[103][0], /* v26 */ \
2543 &rs6000_reg_names[104][0], /* v27 */ \
2544 &rs6000_reg_names[105][0], /* v28 */ \
2545 &rs6000_reg_names[106][0], /* v29 */ \
2546 &rs6000_reg_names[107][0], /* v30 */ \
2547 &rs6000_reg_names[108][0], /* v31 */ \
2548 &rs6000_reg_names[109][0], /* vrsave */ \
2551 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2552 following for it. Switch to use the alternate names since
2553 they are more mnemonic. */
2555 #define DEBUG_REGISTER_NAMES \
2557 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2558 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2559 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2560 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2561 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2562 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2563 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2564 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2565 "mq", "lr", "ctr", "ap", \
2566 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2568 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2569 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2570 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2571 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2575 /* Table of additional register names to use in user input. */
2577 #define ADDITIONAL_REGISTER_NAMES \
2578 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2579 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2580 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2581 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2582 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2583 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2584 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2585 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2586 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2587 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2588 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2589 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2590 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2591 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2592 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2593 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2594 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2595 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2596 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2597 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2598 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2599 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2600 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2601 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2603 /* no additional names for: mq, lr, ctr, ap */ \
2604 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2605 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2606 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2608 /* How to renumber registers for dbx and gdb. */
2610 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2612 /* Text to write out after a CALL that may be replaced by glue code by
2613 the loader. This depends on the AIX version. */
2614 #define RS6000_CALL_GLUE "cror 31,31,31"
2616 /* This is how to output an assembler line defining a `double' constant. */
2618 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
2621 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2622 fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \
2623 t[0] & 0xffffffff, t[1] & 0xffffffff); \
2626 /* This is how to output an assembler line defining a `float' constant. */
2628 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
2631 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2632 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2635 /* This is how to output an assembler line defining an `int' constant. */
2637 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2641 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
2642 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2643 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
2644 UNITS_PER_WORD, BITS_PER_WORD, 1); \
2648 fprintf (FILE, "%s", DOUBLE_INT_ASM_OP); \
2649 output_addr_const (FILE, (VALUE)); \
2650 putc ('\n', FILE); \
2654 #define ASM_OUTPUT_INT(FILE,VALUE) \
2655 ( fputs ("\t.long ", FILE), \
2656 output_addr_const (FILE, (VALUE)), \
2659 /* Likewise for `char' and `short' constants. */
2661 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2662 ( fputs ("\t.short ", FILE), \
2663 output_addr_const (FILE, (VALUE)), \
2666 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2667 ( fputs ("\t.byte ", FILE), \
2668 output_addr_const (FILE, (VALUE)), \
2671 /* This is how to output an assembler line for a numeric constant byte. */
2673 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2674 fprintf (FILE, "\t.byte 0x%x\n", (int)(VALUE))
2676 /* This is used by the definition of ASM_OUTPUT_ADDR_ELT in defaults.h. */
2677 #define ASM_LONG (TARGET_32BIT ? ".long" : DOUBLE_INT_ASM_OP)
2679 /* This is how to output an element of a case-vector that is relative. */
2681 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2682 do { char buf[100]; \
2683 fputs ("\t.long ", FILE); \
2684 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2685 assemble_name (FILE, buf); \
2687 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2688 assemble_name (FILE, buf); \
2689 putc ('\n', FILE); \
2692 /* This is how to output an assembler line
2693 that says to advance the location counter
2694 to a multiple of 2**LOG bytes. */
2696 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2698 fprintf (FILE, "\t.align %d\n", (LOG))
2700 /* Store in OUTPUT a string (made with alloca) containing
2701 an assembler-name for a local static variable named NAME.
2702 LABELNO is an integer which is different for each call. */
2704 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2705 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2706 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2708 /* Pick up the return address upon entry to a procedure. Used for
2709 dwarf2 unwind information. This also enables the table driven
2712 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2713 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2715 /* Describe how we implement __builtin_eh_return. */
2716 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2717 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2719 /* Print operand X (an rtx) in assembler syntax to file FILE.
2720 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2721 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2723 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2725 /* Define which CODE values are valid. */
2727 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2728 ((CODE) == '.' || (CODE) == '*' || (CODE) == '$')
2730 /* Print a memory address as an operand to reference that memory location. */
2732 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2734 /* Define the codes that are matched by predicates in rs6000.c. */
2736 #define PREDICATE_CODES \
2737 {"short_cint_operand", {CONST_INT}}, \
2738 {"u_short_cint_operand", {CONST_INT}}, \
2739 {"non_short_cint_operand", {CONST_INT}}, \
2740 {"exact_log2_cint_operand", {CONST_INT}}, \
2741 {"gpc_reg_operand", {SUBREG, REG}}, \
2742 {"cc_reg_operand", {SUBREG, REG}}, \
2743 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2744 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2745 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2746 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2747 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2748 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2749 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2750 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2751 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2752 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2753 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2754 {"easy_fp_constant", {CONST_DOUBLE}}, \
2755 {"zero_fp_constant", {CONST_DOUBLE}}, \
2756 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2757 {"lwa_operand", {SUBREG, MEM, REG}}, \
2758 {"volatile_mem_operand", {MEM}}, \
2759 {"offsettable_mem_operand", {MEM}}, \
2760 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2761 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2762 {"non_add_cint_operand", {CONST_INT}}, \
2763 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2764 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2765 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2766 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2767 {"mask_operand", {CONST_INT}}, \
2768 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2769 {"count_register_operand", {REG}}, \
2770 {"xer_operand", {REG}}, \
2771 {"call_operand", {SYMBOL_REF, REG}}, \
2772 {"current_file_function_operand", {SYMBOL_REF}}, \
2773 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2774 CONST_DOUBLE, SYMBOL_REF}}, \
2775 {"load_multiple_operation", {PARALLEL}}, \
2776 {"store_multiple_operation", {PARALLEL}}, \
2777 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2778 GT, LEU, LTU, GEU, GTU, \
2779 UNORDERED, ORDERED, \
2781 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2783 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2784 GT, LEU, LTU, GEU, GTU, \
2785 UNORDERED, ORDERED, \
2787 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2788 GT, LEU, LTU, GEU, GTU}}, \
2789 {"boolean_operator", {AND, IOR, XOR}}, \
2790 {"boolean_or_operator", {IOR, XOR}}, \
2791 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2793 /* uncomment for disabling the corresponding default options */
2794 /* #define MACHINE_no_sched_interblock */
2795 /* #define MACHINE_no_sched_speculative */
2796 /* #define MACHINE_no_sched_speculative_load */
2798 /* General flags. */
2799 extern int flag_pic;
2800 extern int optimize;
2801 extern int flag_expensive_optimizations;
2802 extern int frame_pointer_needed;
2804 enum rs6000_builtins
2806 /* AltiVec builtins. */
2807 ALTIVEC_BUILTIN_ST_INTERNAL,
2808 ALTIVEC_BUILTIN_LD_INTERNAL,
2809 ALTIVEC_BUILTIN_VADDUBM,
2810 ALTIVEC_BUILTIN_VADDUHM,
2811 ALTIVEC_BUILTIN_VADDUWM,
2812 ALTIVEC_BUILTIN_VADDFP,
2813 ALTIVEC_BUILTIN_VADDCUW,
2814 ALTIVEC_BUILTIN_VADDUBS,
2815 ALTIVEC_BUILTIN_VADDSBS,
2816 ALTIVEC_BUILTIN_VADDUHS,
2817 ALTIVEC_BUILTIN_VADDSHS,
2818 ALTIVEC_BUILTIN_VADDUWS,
2819 ALTIVEC_BUILTIN_VADDSWS,
2820 ALTIVEC_BUILTIN_VAND,
2821 ALTIVEC_BUILTIN_VANDC,
2822 ALTIVEC_BUILTIN_VAVGUB,
2823 ALTIVEC_BUILTIN_VAVGSB,
2824 ALTIVEC_BUILTIN_VAVGUH,
2825 ALTIVEC_BUILTIN_VAVGSH,
2826 ALTIVEC_BUILTIN_VAVGUW,
2827 ALTIVEC_BUILTIN_VAVGSW,
2828 ALTIVEC_BUILTIN_VCMPBFP,
2829 ALTIVEC_BUILTIN_VCMPEQUB,
2830 ALTIVEC_BUILTIN_VCMPEQUH,
2831 ALTIVEC_BUILTIN_VCMPEQUW,
2832 ALTIVEC_BUILTIN_VCMPEQFP,
2833 ALTIVEC_BUILTIN_VCMPGEFP,
2834 ALTIVEC_BUILTIN_VCMPGTUB,
2835 ALTIVEC_BUILTIN_VCMPGTSB,
2836 ALTIVEC_BUILTIN_VCMPGTUH,
2837 ALTIVEC_BUILTIN_VCMPGTSH,
2838 ALTIVEC_BUILTIN_VCMPGTUW,
2839 ALTIVEC_BUILTIN_VCMPGTSW,
2840 ALTIVEC_BUILTIN_VCMPGTFP,
2841 ALTIVEC_BUILTIN_VMAXUB,
2842 ALTIVEC_BUILTIN_VMAXSB,
2843 ALTIVEC_BUILTIN_VMAXUH,
2844 ALTIVEC_BUILTIN_VMAXSH,
2845 ALTIVEC_BUILTIN_VMAXUW,
2846 ALTIVEC_BUILTIN_VMAXSW,
2847 ALTIVEC_BUILTIN_VMAXFP,
2848 ALTIVEC_BUILTIN_VMRGHB,
2849 ALTIVEC_BUILTIN_VMRGHH,
2850 ALTIVEC_BUILTIN_VMRGHW,
2851 ALTIVEC_BUILTIN_VMRGLB,
2852 ALTIVEC_BUILTIN_VMRGLH,
2853 ALTIVEC_BUILTIN_VMRGLW,
2854 ALTIVEC_BUILTIN_VMINUB,
2855 ALTIVEC_BUILTIN_VMINSB,
2856 ALTIVEC_BUILTIN_VMINUH,
2857 ALTIVEC_BUILTIN_VMINSH,
2858 ALTIVEC_BUILTIN_VMINUW,
2859 ALTIVEC_BUILTIN_VMINSW,
2860 ALTIVEC_BUILTIN_VMINFP,
2861 ALTIVEC_BUILTIN_VMULEUB,
2862 ALTIVEC_BUILTIN_VMULESB,
2863 ALTIVEC_BUILTIN_VMULEUH,
2864 ALTIVEC_BUILTIN_VMULESH,
2865 ALTIVEC_BUILTIN_VMULOUB,
2866 ALTIVEC_BUILTIN_VMULOSB,
2867 ALTIVEC_BUILTIN_VMULOUH,
2868 ALTIVEC_BUILTIN_VMULOSH,
2869 ALTIVEC_BUILTIN_VNOR,
2870 ALTIVEC_BUILTIN_VOR,
2871 ALTIVEC_BUILTIN_VPKUHUM,
2872 ALTIVEC_BUILTIN_VPKUWUM,
2873 ALTIVEC_BUILTIN_VPKPX,
2874 ALTIVEC_BUILTIN_VPKUHSS,
2875 ALTIVEC_BUILTIN_VPKSHSS,
2876 ALTIVEC_BUILTIN_VPKUWSS,
2877 ALTIVEC_BUILTIN_VPKSWSS,
2878 ALTIVEC_BUILTIN_VPKUHUS,
2879 ALTIVEC_BUILTIN_VPKSHUS,
2880 ALTIVEC_BUILTIN_VPKUWUS,
2881 ALTIVEC_BUILTIN_VPKSWUS,
2882 ALTIVEC_BUILTIN_VRLB,
2883 ALTIVEC_BUILTIN_VRLH,
2884 ALTIVEC_BUILTIN_VRLW,
2885 ALTIVEC_BUILTIN_VSLB,
2886 ALTIVEC_BUILTIN_VSLH,
2887 ALTIVEC_BUILTIN_VSLW,
2888 ALTIVEC_BUILTIN_VSL,
2889 ALTIVEC_BUILTIN_VSLO,
2890 ALTIVEC_BUILTIN_VSRB,
2891 ALTIVEC_BUILTIN_VRSH,
2892 ALTIVEC_BUILTIN_VRSW,
2893 ALTIVEC_BUILTIN_VSRAB,
2894 ALTIVEC_BUILTIN_VSRAH,
2895 ALTIVEC_BUILTIN_VSRAW,
2896 ALTIVEC_BUILTIN_VSR,
2897 ALTIVEC_BUILTIN_VSRO,
2898 ALTIVEC_BUILTIN_VSUBUBM,
2899 ALTIVEC_BUILTIN_VSUBUHM,
2900 ALTIVEC_BUILTIN_VSUBUWM,
2901 ALTIVEC_BUILTIN_VSUBFP,
2902 ALTIVEC_BUILTIN_VSUBCUW,
2903 ALTIVEC_BUILTIN_VSUBUBS,
2904 ALTIVEC_BUILTIN_VSUBSBS,
2905 ALTIVEC_BUILTIN_VSUBUHS,
2906 ALTIVEC_BUILTIN_VSUBSHS,
2907 ALTIVEC_BUILTIN_VSUBUWS,
2908 ALTIVEC_BUILTIN_VSUBSWS,
2909 ALTIVEC_BUILTIN_VSUM4UBS,
2910 ALTIVEC_BUILTIN_VSUM4SBS,
2911 ALTIVEC_BUILTIN_VSUM4SHS,
2912 ALTIVEC_BUILTIN_VSUM2SWS,
2913 ALTIVEC_BUILTIN_VSUMSWS,
2914 ALTIVEC_BUILTIN_VXOR
OSDN Git Service
