1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 Free Software Foundation, Inc.
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
27 <http://www.gnu.org/licenses/>. */
29 /* Note that some other tm.h files include this one and then override
30 many of the definitions. */
33 #include "config/rs6000/rs6000-opts.h"
36 /* Definitions for the object file format. These are set at
39 #define OBJECT_XCOFF 1
42 #define OBJECT_MACHO 4
44 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
45 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
46 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
54 #define TARGET_AIX_OS 0
57 /* Control whether function entry points use a "dot" symbol when
61 /* Default string to use for cpu if not specified. */
62 #ifndef TARGET_CPU_DEFAULT
63 #define TARGET_CPU_DEFAULT ((char *)0)
66 /* If configured for PPC405, support PPC405CR Erratum77. */
67 #ifdef CONFIG_PPC405CR
68 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
70 #define PPC405_ERRATUM77 0
73 #ifndef TARGET_PAIRED_FLOAT
74 #define TARGET_PAIRED_FLOAT 0
77 #ifdef HAVE_AS_POPCNTB
78 #define ASM_CPU_POWER5_SPEC "-mpower5"
80 #define ASM_CPU_POWER5_SPEC "-mpower4"
84 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
86 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
89 #ifdef HAVE_AS_POPCNTD
90 #define ASM_CPU_POWER7_SPEC "-mpower7"
92 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
96 #define ASM_CPU_476_SPEC "-m476"
98 #define ASM_CPU_476_SPEC "-mpower4"
101 /* Common ASM definitions used by ASM_SPEC among the various targets for
102 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
103 provide the default assembler options if the user uses -mcpu=native, so if
104 you make changes here, make them also there. */
105 #define ASM_CPU_SPEC \
107 %{mpower: %{!mpower2: -mpwr}} \
109 %{mpowerpc64*: -mppc64} \
110 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
111 %{mno-power: %{!mpowerpc*: -mcom}} \
112 %{!mno-power: %{!mpower*: %(asm_default)}}} \
113 %{mcpu=native: %(asm_cpu_native)} \
114 %{mcpu=common: -mcom} \
115 %{mcpu=cell: -mcell} \
116 %{mcpu=power: -mpwr} \
117 %{mcpu=power2: -mpwrx} \
118 %{mcpu=power3: -mppc64} \
119 %{mcpu=power4: -mpower4} \
120 %{mcpu=power5: %(asm_cpu_power5)} \
121 %{mcpu=power5+: %(asm_cpu_power5)} \
122 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
123 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
124 %{mcpu=power7: %(asm_cpu_power7)} \
126 %{mcpu=powerpc: -mppc} \
127 %{mcpu=rios: -mpwr} \
128 %{mcpu=rios1: -mpwr} \
129 %{mcpu=rios2: -mpwrx} \
131 %{mcpu=rsc1: -mpwr} \
132 %{mcpu=rs64a: -mppc64} \
136 %{mcpu=405fp: -m405} \
138 %{mcpu=440fp: -m440} \
140 %{mcpu=464fp: -m440} \
141 %{mcpu=476: %(asm_cpu_476)} \
142 %{mcpu=476fp: %(asm_cpu_476)} \
147 %{mcpu=603e: -mppc} \
148 %{mcpu=ec603e: -mppc} \
150 %{mcpu=604e: -mppc} \
151 %{mcpu=620: -mppc64} \
152 %{mcpu=630: -mppc64} \
156 %{mcpu=7400: -mppc -maltivec} \
157 %{mcpu=7450: -mppc -maltivec} \
158 %{mcpu=G4: -mppc -maltivec} \
163 %{mcpu=970: -mpower4 -maltivec} \
164 %{mcpu=G5: -mpower4 -maltivec} \
165 %{mcpu=8540: -me500} \
166 %{mcpu=8548: -me500} \
167 %{mcpu=e300c2: -me300} \
168 %{mcpu=e300c3: -me300} \
169 %{mcpu=e500mc: -me500mc} \
170 %{mcpu=e500mc64: -me500mc64} \
171 %{maltivec: -maltivec} \
172 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
175 #define CPP_DEFAULT_SPEC ""
177 #define ASM_DEFAULT_SPEC ""
179 /* This macro defines names of additional specifications to put in the specs
180 that can be used in various specifications like CC1_SPEC. Its definition
181 is an initializer with a subgrouping for each command option.
183 Each subgrouping contains a string constant, that defines the
184 specification name, and a string constant that used by the GCC driver
187 Do not define this macro if it does not need to do anything. */
189 #define SUBTARGET_EXTRA_SPECS
191 #define EXTRA_SPECS \
192 { "cpp_default", CPP_DEFAULT_SPEC }, \
193 { "asm_cpu", ASM_CPU_SPEC }, \
194 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
195 { "asm_default", ASM_DEFAULT_SPEC }, \
196 { "cc1_cpu", CC1_CPU_SPEC }, \
197 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
198 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
199 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
200 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
201 SUBTARGET_EXTRA_SPECS
203 /* -mcpu=native handling only makes sense with compiler running on
204 an PowerPC chip. If changing this condition, also change
205 the condition in driver-rs6000.c. */
206 #if 0 /* defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) */
207 /* In driver-rs6000.c. */
208 extern const char *host_detect_local_cpu (int argc, const char **argv);
209 #define EXTRA_SPEC_FUNCTIONS \
210 { "local_cpu_detect", host_detect_local_cpu },
211 #define HAVE_LOCAL_CPU_DETECT
212 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
215 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
219 #ifdef HAVE_LOCAL_CPU_DETECT
220 #define CC1_CPU_SPEC \
221 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
222 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
224 #define CC1_CPU_SPEC ""
228 /* Architecture type. */
230 /* Define TARGET_MFCRF if the target assembler does not support the
231 optional field operand for mfcr. */
233 #ifndef HAVE_AS_MFCRF
235 #define TARGET_MFCRF 0
238 /* Define TARGET_POPCNTB if the target assembler does not support the
239 popcount byte instruction. */
241 #ifndef HAVE_AS_POPCNTB
242 #undef TARGET_POPCNTB
243 #define TARGET_POPCNTB 0
246 /* Define TARGET_FPRND if the target assembler does not support the
247 fp rounding instructions. */
249 #ifndef HAVE_AS_FPRND
251 #define TARGET_FPRND 0
254 /* Define TARGET_CMPB if the target assembler does not support the
259 #define TARGET_CMPB 0
262 /* Define TARGET_MFPGPR if the target assembler does not support the
263 mffpr and mftgpr instructions. */
265 #ifndef HAVE_AS_MFPGPR
267 #define TARGET_MFPGPR 0
270 /* Define TARGET_DFP if the target assembler does not support decimal
271 floating point instructions. */
277 /* Define TARGET_POPCNTD if the target assembler does not support the
278 popcount word and double word instructions. */
280 #ifndef HAVE_AS_POPCNTD
281 #undef TARGET_POPCNTD
282 #define TARGET_POPCNTD 0
285 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
286 not, generate the lwsync code as an integer constant. */
287 #ifdef HAVE_AS_LWSYNC
288 #define TARGET_LWSYNC_INSTRUCTION 1
290 #define TARGET_LWSYNC_INSTRUCTION 0
293 /* Define TARGET_TLS_MARKERS if the target assembler does not support
294 arg markers for __tls_get_addr calls. */
295 #ifndef HAVE_AS_TLS_MARKERS
296 #undef TARGET_TLS_MARKERS
297 #define TARGET_TLS_MARKERS 0
299 #define TARGET_TLS_MARKERS tls_markers
302 #ifndef TARGET_SECURE_PLT
303 #define TARGET_SECURE_PLT 0
306 #ifndef TARGET_CMODEL
307 #define TARGET_CMODEL CMODEL_SMALL
310 #define TARGET_32BIT (! TARGET_64BIT)
313 #define HAVE_AS_TLS 0
316 #ifndef TARGET_LINK_STACK
317 #define TARGET_LINK_STACK 0
320 #ifndef SET_TARGET_LINK_STACK
321 #define SET_TARGET_LINK_STACK(X) do { } while (0)
324 /* Return 1 for a symbol ref for a thread-local storage symbol. */
325 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
326 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
329 /* For libgcc2 we make sure this is a compile time constant */
330 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
331 #undef TARGET_POWERPC64
332 #define TARGET_POWERPC64 1
334 #undef TARGET_POWERPC64
335 #define TARGET_POWERPC64 0
338 /* The option machinery will define this. */
341 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
343 /* FPU operations supported.
344 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
345 also test TARGET_HARD_FLOAT. */
346 #define TARGET_SINGLE_FLOAT 1
347 #define TARGET_DOUBLE_FLOAT 1
348 #define TARGET_SINGLE_FPU 0
349 #define TARGET_SIMPLE_FPU 0
350 #define TARGET_XILINX_FPU 0
352 /* Recast the processor type to the cpu attribute. */
353 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
355 /* Define generic processor types based upon current deployment. */
356 #define PROCESSOR_COMMON PROCESSOR_PPC601
357 #define PROCESSOR_POWER PROCESSOR_RIOS1
358 #define PROCESSOR_POWERPC PROCESSOR_PPC604
359 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
361 /* Define the default processor. This is overridden by other tm.h files. */
362 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
363 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
365 /* Specify the dialect of assembler to use. New mnemonics is dialect one
366 and the old mnemonics are dialect zero. */
367 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
370 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
371 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
372 #define MASK_DEBUG_REG 0x04 /* debug register handling */
373 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
374 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
375 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
376 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
377 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
382 | MASK_DEBUG_TARGET \
383 | MASK_DEBUG_BUILTIN)
385 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
386 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
387 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
388 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
389 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
390 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
391 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
393 extern enum rs6000_vector rs6000_vector_unit[];
395 #define VECTOR_UNIT_NONE_P(MODE) \
396 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
398 #define VECTOR_UNIT_VSX_P(MODE) \
399 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
401 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
402 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
404 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
405 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
406 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
408 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
409 same unit as the vector unit we are using, but we may want to migrate to
410 using VSX style loads even for types handled by altivec. */
411 extern enum rs6000_vector rs6000_vector_mem[];
413 #define VECTOR_MEM_NONE_P(MODE) \
414 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
416 #define VECTOR_MEM_VSX_P(MODE) \
417 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
419 #define VECTOR_MEM_ALTIVEC_P(MODE) \
420 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
422 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
423 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
424 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
426 /* Return the alignment of a given vector type, which is set based on the
427 vector unit use. VSX for instance can load 32 or 64 bit aligned words
428 without problems, while Altivec requires 128-bit aligned vectors. */
429 extern int rs6000_vector_align[];
431 #define VECTOR_ALIGN(MODE) \
432 ((rs6000_vector_align[(MODE)] != 0) \
433 ? rs6000_vector_align[(MODE)] \
434 : (int)GET_MODE_BITSIZE ((MODE)))
436 /* Alignment options for fields in structures for sub-targets following
438 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
439 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
441 Override the macro definitions when compiling libobjc to avoid undefined
442 reference to rs6000_alignment_flags due to library's use of GCC alignment
443 macros which use the macros below. */
445 #ifndef IN_TARGET_LIBS
446 #define MASK_ALIGN_POWER 0x00000000
447 #define MASK_ALIGN_NATURAL 0x00000001
448 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
450 #define TARGET_ALIGN_NATURAL 0
453 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
454 #define TARGET_IEEEQUAD rs6000_ieeequad
455 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
456 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
458 #define TARGET_SPE_ABI 0
460 #define TARGET_E500 0
461 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
462 #define TARGET_FPRS 1
463 #define TARGET_E500_SINGLE 0
464 #define TARGET_E500_DOUBLE 0
465 #define CHECK_E500_OPTIONS do { } while (0)
467 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
468 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
470 #define TARGET_FCFID (TARGET_POWERPC64 \
471 || TARGET_PPC_GPOPT /* 970/power4 */ \
472 || TARGET_POPCNTB /* ISA 2.02 */ \
473 || TARGET_CMPB /* ISA 2.05 */ \
474 || TARGET_POPCNTD /* ISA 2.06 */ \
475 || TARGET_XILINX_FPU)
477 #define TARGET_FCTIDZ TARGET_FCFID
478 #define TARGET_STFIWX TARGET_PPC_GFXOPT
479 #define TARGET_LFIWAX TARGET_CMPB
480 #define TARGET_LFIWZX TARGET_POPCNTD
481 #define TARGET_FCFIDS TARGET_POPCNTD
482 #define TARGET_FCFIDU TARGET_POPCNTD
483 #define TARGET_FCFIDUS TARGET_POPCNTD
484 #define TARGET_FCTIDUZ TARGET_POPCNTD
485 #define TARGET_FCTIWUZ TARGET_POPCNTD
487 /* For power systems, we want to enable Altivec and VSX builtins even if the
488 user did not use -maltivec or -mvsx to allow the builtins to be used inside
489 of #pragma GCC target or the target attribute to change the code level for a
490 given system. The SPE and Paired builtins are only enabled if you configure
491 the compiler for those builtins, and those machines don't support altivec or
494 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
495 && ((TARGET_POWERPC64 \
496 || TARGET_PPC_GPOPT /* 970/power4 */ \
497 || TARGET_POPCNTB /* ISA 2.02 */ \
498 || TARGET_CMPB /* ISA 2.05 */ \
499 || TARGET_POPCNTD /* ISA 2.06 */ \
505 /* E500 processors only support plain "sync", not lwsync. */
506 #define TARGET_NO_LWSYNC TARGET_E500
508 /* Which machine supports the various reciprocal estimate instructions. */
509 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
510 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
512 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
513 && TARGET_DOUBLE_FLOAT \
514 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
516 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
517 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
519 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
520 && TARGET_DOUBLE_FLOAT \
521 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
523 /* Whether the various reciprocal divide/square root estimate instructions
524 exist, and whether we should automatically generate code for the instruction
526 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
527 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
528 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
529 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
531 extern unsigned char rs6000_recip_bits[];
533 #define RS6000_RECIP_HAVE_RE_P(MODE) \
534 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
536 #define RS6000_RECIP_AUTO_RE_P(MODE) \
537 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
539 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
540 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
542 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
543 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
545 #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
546 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
548 /* The default CPU for TARGET_OPTION_OVERRIDE. */
549 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
552 #define REGISTER_TARGET_PRAGMAS() do { \
553 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
554 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
555 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
556 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
559 /* Target #defines. */
560 #define TARGET_CPU_CPP_BUILTINS() \
561 rs6000_cpu_cpp_builtins (pfile)
563 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
564 we're compiling for. Some configurations may need to override it. */
565 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
568 if (BYTES_BIG_ENDIAN) \
570 builtin_define ("__BIG_ENDIAN__"); \
571 builtin_define ("_BIG_ENDIAN"); \
572 builtin_assert ("machine=bigendian"); \
576 builtin_define ("__LITTLE_ENDIAN__"); \
577 builtin_define ("_LITTLE_ENDIAN"); \
578 builtin_assert ("machine=littleendian"); \
583 /* Target machine storage layout. */
585 /* Define this macro if it is advisable to hold scalars in registers
586 in a wider mode than that declared by the program. In such cases,
587 the value is constrained to be within the bounds of the declared
588 type, but kept valid in the wider mode. The signedness of the
589 extension may differ from that of the type. */
591 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
592 if (GET_MODE_CLASS (MODE) == MODE_INT \
593 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
594 (MODE) = TARGET_32BIT ? SImode : DImode;
596 /* Define this if most significant bit is lowest numbered
597 in instructions that operate on numbered bit-fields. */
598 /* That is true on RS/6000. */
599 #define BITS_BIG_ENDIAN 1
601 /* Define this if most significant byte of a word is the lowest numbered. */
602 /* That is true on RS/6000. */
603 #define BYTES_BIG_ENDIAN 1
605 /* Define this if most significant word of a multiword number is lowest
608 For RS/6000 we can decide arbitrarily since there are no machine
609 instructions for them. Might as well be consistent with bits and bytes. */
610 #define WORDS_BIG_ENDIAN 1
612 #define MAX_BITS_PER_WORD 64
614 /* Width of a word, in units (bytes). */
615 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
617 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
619 #define MIN_UNITS_PER_WORD 4
621 #define UNITS_PER_FP_WORD 8
622 #define UNITS_PER_ALTIVEC_WORD 16
623 #define UNITS_PER_VSX_WORD 16
624 #define UNITS_PER_SPE_WORD 8
625 #define UNITS_PER_PAIRED_WORD 8
627 /* Type used for ptrdiff_t, as a string used in a declaration. */
628 #define PTRDIFF_TYPE "int"
630 /* Type used for size_t, as a string used in a declaration. */
631 #define SIZE_TYPE "long unsigned int"
633 /* Type used for wchar_t, as a string used in a declaration. */
634 #define WCHAR_TYPE "short unsigned int"
636 /* Width of wchar_t in bits. */
637 #define WCHAR_TYPE_SIZE 16
639 /* A C expression for the size in bits of the type `short' on the
640 target machine. If you don't define this, the default is half a
641 word. (If this would be less than one storage unit, it is
642 rounded up to one unit.) */
643 #define SHORT_TYPE_SIZE 16
645 /* A C expression for the size in bits of the type `int' on the
646 target machine. If you don't define this, the default is one
648 #define INT_TYPE_SIZE 32
650 /* A C expression for the size in bits of the type `long' on the
651 target machine. If you don't define this, the default is one
653 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
655 /* A C expression for the size in bits of the type `long long' on the
656 target machine. If you don't define this, the default is two
658 #define LONG_LONG_TYPE_SIZE 64
660 /* A C expression for the size in bits of the type `float' on the
661 target machine. If you don't define this, the default is one
663 #define FLOAT_TYPE_SIZE 32
665 /* A C expression for the size in bits of the type `double' on the
666 target machine. If you don't define this, the default is two
668 #define DOUBLE_TYPE_SIZE 64
670 /* A C expression for the size in bits of the type `long double' on
671 the target machine. If you don't define this, the default is two
673 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
675 /* Define this to set long double type size to use in libgcc2.c, which can
676 not depend on target_flags. */
677 #ifdef __LONG_DOUBLE_128__
678 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
680 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
683 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
684 #define WIDEST_HARDWARE_FP_SIZE 64
686 /* Width in bits of a pointer.
687 See also the macro `Pmode' defined below. */
688 extern unsigned rs6000_pointer_size;
689 #define POINTER_SIZE rs6000_pointer_size
691 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
692 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
694 /* Boundary (in *bits*) on which stack pointer should be aligned. */
695 #define STACK_BOUNDARY \
696 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
699 /* Allocation boundary (in *bits*) for the code of a function. */
700 #define FUNCTION_BOUNDARY 32
702 /* No data type wants to be aligned rounder than this. */
703 #define BIGGEST_ALIGNMENT 128
705 /* A C expression to compute the alignment for a variables in the
706 local store. TYPE is the data type, and ALIGN is the alignment
707 that the object would ordinarily have. */
708 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
709 DATA_ALIGNMENT (TYPE, ALIGN)
711 /* Alignment of field after `int : 0' in a structure. */
712 #define EMPTY_FIELD_BOUNDARY 32
714 /* Every structure's size must be a multiple of this. */
715 #define STRUCTURE_SIZE_BOUNDARY 8
717 /* Return 1 if a structure or array containing FIELD should be
718 accessed using `BLKMODE'.
720 For the SPE, simd types are V2SI, and gcc can be tempted to put the
721 entire thing in a DI and use subregs to access the internals.
722 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
723 back-end. Because a single GPR can hold a V2SI, but not a DI, the
724 best thing to do is set structs to BLKmode and avoid Severe Tire
727 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
728 fit into 1, whereas DI still needs two. */
729 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
730 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
731 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
733 /* A bit-field declared as `int' forces `int' alignment for the struct. */
734 #define PCC_BITFIELD_TYPE_MATTERS 1
736 /* Make strings word-aligned so strcpy from constants will be faster.
737 Make vector constants quadword aligned. */
738 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
739 (TREE_CODE (EXP) == STRING_CST \
740 && (STRICT_ALIGNMENT || !optimize_size) \
741 && (ALIGN) < BITS_PER_WORD \
745 /* Make arrays of chars word-aligned for the same reasons.
746 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
748 #define DATA_ALIGNMENT(TYPE, ALIGN) \
749 (TREE_CODE (TYPE) == VECTOR_TYPE \
750 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
751 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
753 : ((TARGET_E500_DOUBLE \
754 && TREE_CODE (TYPE) == REAL_TYPE \
755 && TYPE_MODE (TYPE) == DFmode) \
757 : (TREE_CODE (TYPE) == ARRAY_TYPE \
758 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
759 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
761 /* Nonzero if move instructions will actually fail to work
762 when given unaligned data. */
763 #define STRICT_ALIGNMENT 0
765 /* Define this macro to be the value 1 if unaligned accesses have a cost
766 many times greater than aligned accesses, for example if they are
767 emulated in a trap handler. */
768 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
769 memory instructions trap on unaligned accesses; VSX memory instructions are
770 aligned to 4 or 8 bytes. */
771 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
773 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
774 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
775 || (MODE) == DImode) \
777 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
780 /* Standard register usage. */
782 /* Number of actual hardware registers.
783 The hardware registers are assigned numbers for the compiler
784 from 0 to just below FIRST_PSEUDO_REGISTER.
785 All registers that the compiler knows about must be given numbers,
786 even those that are not normally considered general registers.
788 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
789 an MQ register, a count register, a link register, and 8 condition
790 register fields, which we view here as separate registers. AltiVec
791 adds 32 vector registers and a VRsave register.
793 In addition, the difference between the frame and argument pointers is
794 a function of the number of registers saved, so we need to have a
795 register for AP that will later be eliminated in favor of SP or FP.
796 This is a normal register, but it is fixed.
798 We also create a pseudo register for float/int conversions, that will
799 really represent the memory location used. It is represented here as
800 a register, in order to work around problems in allocating stack storage
803 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
804 pointer, which is eventually eliminated in favor of SP or FP. */
806 #define FIRST_PSEUDO_REGISTER 114
808 /* This must be included for pre gcc 3.0 glibc compatibility. */
809 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
811 /* Add 32 dwarf columns for synthetic SPE registers. */
812 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
814 /* The SPE has an additional 32 synthetic registers, with DWARF debug
815 info numbering for these registers starting at 1200. While eh_frame
816 register numbering need not be the same as the debug info numbering,
817 we choose to number these regs for eh_frame at 1200 too. This allows
818 future versions of the rs6000 backend to add hard registers and
819 continue to use the gcc hard register numbering for eh_frame. If the
820 extra SPE registers in eh_frame were numbered starting from the
821 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
822 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
823 avoid invalidating older SPE eh_frame info.
825 We must map them here to avoid huge unwinder tables mostly consisting
827 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
828 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
830 /* Use standard DWARF numbering for DWARF debugging information. */
831 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
833 /* Use gcc hard register numbering for eh_frame. */
834 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
836 /* Map register numbers held in the call frame info that gcc has
837 collected using DWARF_FRAME_REGNUM to those that should be output in
838 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
839 for .eh_frame, but use the numbers mandated by the various ABIs for
840 .debug_frame. rs6000_emit_prologue has translated any combination of
841 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
842 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
843 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
844 ((FOR_EH) ? (REGNO) \
845 : (REGNO) == CR2_REGNO ? 64 \
846 : DBX_REGISTER_NUMBER (REGNO))
848 /* 1 for registers that have pervasive standard uses
849 and are not available for the register allocator.
851 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
852 as a local register; for all other OS's r2 is the TOC pointer.
854 cr5 is not supposed to be used.
856 On System V implementations, r13 is fixed and not available for use. */
858 #define FIXED_REGISTERS \
859 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
864 /* AltiVec registers. */ \
865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 /* 1 for registers not available across function calls.
872 These must include the FIXED_REGISTERS and also any
873 registers that can be used without being saved.
874 The latter must include the registers where values are returned
875 and the register where structure-value addresses are passed.
876 Aside from that, you can include as many other registers as you like. */
878 #define CALL_USED_REGISTERS \
879 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
880 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
881 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
883 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
884 /* AltiVec registers. */ \
885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
886 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
891 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
892 the entire set of `FIXED_REGISTERS' be included.
893 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
894 This macro is optional. If not specified, it defaults to the value
895 of `CALL_USED_REGISTERS'. */
897 #define CALL_REALLY_USED_REGISTERS \
898 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
900 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
902 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
903 /* AltiVec registers. */ \
904 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
905 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
910 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
912 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
913 #define FIRST_SAVED_FP_REGNO (14+32)
914 #define FIRST_SAVED_GP_REGNO 13
916 /* List the order in which to allocate registers. Each register must be
917 listed once, even those in FIXED_REGISTERS.
919 We allocate in the following order:
920 fp0 (not saved or used for anything)
921 fp13 - fp2 (not saved; incoming fp arg registers)
922 fp1 (not saved; return value)
923 fp31 - fp14 (saved; order given to save least number)
924 cr7, cr6 (not saved or special)
925 cr1 (not saved, but used for FP operations)
926 cr0 (not saved, but used for arithmetic operations)
927 cr4, cr3, cr2 (saved)
928 r9 (not saved; best for TImode)
929 r10, r8-r4 (not saved; highest first for less conflict with params)
930 r3 (not saved; return value register)
931 r11 (not saved; later alloc to help shrink-wrap)
932 r0 (not saved; cannot be base reg)
933 r31 - r13 (saved; order given to save least number)
934 r12 (not saved; if used for DImode or DFmode would use r13)
935 mq (not saved; best to use it if we can)
936 ctr (not saved; when we have the choice ctr is better)
938 cr5, r1, r2, ap, ca (fixed)
939 v0 - v1 (not saved or used for anything)
940 v13 - v3 (not saved; incoming vector arg registers)
941 v2 (not saved; incoming vector arg reg; return value)
942 v19 - v14 (not saved or used for anything)
943 v31 - v20 (saved; order given to save least number)
945 spe_acc, spefscr (fixed)
950 #define MAYBE_R2_AVAILABLE
951 #define MAYBE_R2_FIXED 2,
953 #define MAYBE_R2_AVAILABLE 2,
954 #define MAYBE_R2_FIXED
958 #define EARLY_R12 12,
965 #define REG_ALLOC_ORDER \
967 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
969 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
970 50, 49, 48, 47, 46, \
971 75, 74, 69, 68, 72, 71, 70, \
973 9, 10, 8, 7, 6, 5, 4, \
974 3, EARLY_R12 11, 0, \
975 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
976 18, 17, 16, 15, 14, 13, LATE_R12 \
978 73, 1, MAYBE_R2_FIXED 67, 76, \
979 /* AltiVec registers. */ \
981 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
983 96, 95, 94, 93, 92, 91, \
984 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
989 /* True if register is floating-point. */
990 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
992 /* True if register is a condition register. */
993 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
995 /* True if register is a condition register, but not cr0. */
996 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
998 /* True if register is an integer register. */
999 #define INT_REGNO_P(N) \
1000 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1002 /* SPE SIMD registers are just the GPRs. */
1003 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1005 /* PAIRED SIMD registers are just the FPRs. */
1006 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1008 /* True if register is the CA register. */
1009 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1011 /* True if register is an AltiVec register. */
1012 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1014 /* True if register is a VSX register. */
1015 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1017 /* Alternate name for any vector register supporting floating point, no matter
1018 which instruction set(s) are available. */
1019 #define VFLOAT_REGNO_P(N) \
1020 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1022 /* Alternate name for any vector register supporting integer, no matter which
1023 instruction set(s) are available. */
1024 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1026 /* Alternate name for any vector register supporting logical operations, no
1027 matter which instruction set(s) are available. */
1028 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1030 /* Return number of consecutive hard regs needed starting at reg REGNO
1031 to hold something of mode MODE. */
1033 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1035 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1036 enough space to account for vectors in FP regs. However, TFmode/TDmode
1037 should not use VSX instructions to do a caller save. */
1038 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1040 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1041 && FP_REGNO_P (REGNO) \
1043 : ((MODE) == TFmode && FP_REGNO_P (REGNO)) \
1045 : ((MODE) == TDmode && FP_REGNO_P (REGNO)) \
1047 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1049 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1050 (((TARGET_32BIT && TARGET_POWERPC64 \
1051 && (GET_MODE_SIZE (MODE) > 4) \
1052 && INT_REGNO_P (REGNO)) ? 1 : 0) \
1053 || (TARGET_VSX && FP_REGNO_P (REGNO) \
1054 && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \
1055 && ((MODE) != TFmode)))
1057 #define VSX_VECTOR_MODE(MODE) \
1058 ((MODE) == V4SFmode \
1059 || (MODE) == V2DFmode) \
1061 #define ALTIVEC_VECTOR_MODE(MODE) \
1062 ((MODE) == V16QImode \
1063 || (MODE) == V8HImode \
1064 || (MODE) == V4SFmode \
1065 || (MODE) == V4SImode)
1067 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1068 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1069 || (MODE) == V2DImode)
1071 #define SPE_VECTOR_MODE(MODE) \
1072 ((MODE) == V4HImode \
1073 || (MODE) == V2SFmode \
1074 || (MODE) == V1DImode \
1075 || (MODE) == V2SImode)
1077 #define PAIRED_VECTOR_MODE(MODE) \
1078 ((MODE) == V2SFmode)
1080 /* Value is TRUE if hard register REGNO can hold a value of
1081 machine-mode MODE. */
1082 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1083 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1085 /* Value is 1 if it is a good idea to tie two pseudo registers
1086 when one has mode MODE1 and one has mode MODE2.
1087 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1088 for any hard reg, then this must be 0 for correct output. */
1089 #define MODES_TIEABLE_P(MODE1, MODE2) \
1090 (SCALAR_FLOAT_MODE_P (MODE1) \
1091 ? SCALAR_FLOAT_MODE_P (MODE2) \
1092 : SCALAR_FLOAT_MODE_P (MODE2) \
1093 ? SCALAR_FLOAT_MODE_P (MODE1) \
1094 : GET_MODE_CLASS (MODE1) == MODE_CC \
1095 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1096 : GET_MODE_CLASS (MODE2) == MODE_CC \
1097 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1098 : SPE_VECTOR_MODE (MODE1) \
1099 ? SPE_VECTOR_MODE (MODE2) \
1100 : SPE_VECTOR_MODE (MODE2) \
1101 ? SPE_VECTOR_MODE (MODE1) \
1102 : ALTIVEC_VECTOR_MODE (MODE1) \
1103 ? ALTIVEC_VECTOR_MODE (MODE2) \
1104 : ALTIVEC_VECTOR_MODE (MODE2) \
1105 ? ALTIVEC_VECTOR_MODE (MODE1) \
1106 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1107 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1108 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1109 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1112 /* Post-reload, we can't use any new AltiVec registers, as we already
1113 emitted the vrsave mask. */
1115 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1116 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1118 /* Specify the cost of a branch insn; roughly the number of extra insns that
1119 should be added to avoid a branch.
1121 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1122 unscheduled conditional branch. */
1124 #define BRANCH_COST(speed_p, predictable_p) 3
1126 /* Override BRANCH_COST heuristic which empirically produces worse
1127 performance for removing short circuiting from the logical ops. */
1129 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1131 /* A fixed register used at epilogue generation to address SPE registers
1132 with negative offsets. The 64-bit load/store instructions on the SPE
1133 only take positive offsets (and small ones at that), so we need to
1134 reserve a register for consing up negative offsets. */
1136 #define FIXED_SCRATCH 0
1138 /* Specify the registers used for certain standard purposes.
1139 The values of these macros are register numbers. */
1141 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1142 /* #define PC_REGNUM */
1144 /* Register to use for pushing function arguments. */
1145 #define STACK_POINTER_REGNUM 1
1147 /* Base register for access to local variables of the function. */
1148 #define HARD_FRAME_POINTER_REGNUM 31
1150 /* Base register for access to local variables of the function. */
1151 #define FRAME_POINTER_REGNUM 113
1153 /* Base register for access to arguments of the function. */
1154 #define ARG_POINTER_REGNUM 67
1156 /* Place to put static chain when calling a function that requires it. */
1157 #define STATIC_CHAIN_REGNUM 11
1160 /* Define the classes of registers for register constraints in the
1161 machine description. Also define ranges of constants.
1163 One of the classes must always be named ALL_REGS and include all hard regs.
1164 If there is more than one class, another class must be named NO_REGS
1165 and contain no registers.
1167 The name GENERAL_REGS must be the name of a class (or an alias for
1168 another name such as ALL_REGS). This is the class of registers
1169 that is allowed by "g" or "r" in a register constraint.
1170 Also, registers outside this class are allocated only when
1171 instructions express preferences for them.
1173 The classes must be numbered in nondecreasing order; that is,
1174 a larger-numbered class must never be contained completely
1175 in a smaller-numbered class.
1177 For any two classes, it is very desirable that there be another
1178 class that represents their union. */
1180 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1181 condition registers, plus three special registers, MQ, CTR, and the link
1182 register. AltiVec adds a vector register class. VSX registers overlap the
1183 FPR registers and the Altivec registers.
1185 However, r0 is special in that it cannot be used as a base register.
1186 So make a class for registers valid as base registers.
1188 Also, cr0 is the only condition code register that can be used in
1189 arithmetic insns, so make a separate class for it. */
1218 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1220 /* Give names of register classes as strings for dump file. */
1222 #define REG_CLASS_NAMES \
1234 "NON_SPECIAL_REGS", \
1238 "LINK_OR_CTR_REGS", \
1240 "SPEC_OR_GEN_REGS", \
1248 /* Define which registers fit in which classes.
1249 This is an initializer for a vector of HARD_REG_SET
1250 of length N_REG_CLASSES. */
1252 #define REG_CLASS_CONTENTS \
1254 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1255 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1256 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1257 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1258 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1259 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
1260 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1261 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1262 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1263 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1264 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1265 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1266 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1267 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1268 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1269 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1270 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1271 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1272 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1273 { 0xffffffff, 0x00000000, 0x00000fff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1274 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
1275 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1278 /* The same information, inverted:
1279 Return the class number of the smallest class containing
1280 reg number REGNO. This could be a conditional expression
1281 or could index an array. */
1283 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1286 #define REGNO_REG_CLASS(REGNO) \
1287 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1288 rs6000_regno_regclass[(REGNO)])
1291 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1294 /* Register classes for various constraints that are based on the target
1296 enum r6000_reg_class_enum {
1297 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1298 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1299 RS6000_CONSTRAINT_v, /* Altivec registers */
1300 RS6000_CONSTRAINT_wa, /* Any VSX register */
1301 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1302 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1303 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1304 RS6000_CONSTRAINT_MAX
1307 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1309 /* The class value for index registers, and the one for base regs. */
1310 #define INDEX_REG_CLASS GENERAL_REGS
1311 #define BASE_REG_CLASS BASE_REGS
1313 /* Return whether a given register class can hold VSX objects. */
1314 #define VSX_REG_CLASS_P(CLASS) \
1315 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1317 /* Given an rtx X being reloaded into a reg required to be
1318 in class CLASS, return the class of reg to actually use.
1319 In general this is just CLASS; but on some machines
1320 in some cases it is preferable to use a more restrictive class.
1322 On the RS/6000, we have to return NO_REGS when we want to reload a
1323 floating-point CONST_DOUBLE to force it to be copied to memory.
1325 We also don't want to reload integer values into floating-point
1326 registers if we can at all help it. In fact, this can
1327 cause reload to die, if it tries to generate a reload of CTR
1328 into a FP register and discovers it doesn't have the memory location
1331 ??? Would it be a good idea to have reload do the converse, that is
1332 try to reload floating modes into FP registers if possible?
1335 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1336 rs6000_preferred_reload_class_ptr (X, CLASS)
1338 /* Return the register class of a scratch register needed to copy IN into
1339 or out of a register in CLASS in MODE. If it can be done directly,
1340 NO_REGS is returned. */
1342 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1343 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1345 /* If we are copying between FP or AltiVec registers and anything
1346 else, we need a memory location. The exception is when we are
1347 targeting ppc64 and the move to/from fpr to gpr instructions
1350 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1351 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1353 /* For cpus that cannot load/store SDmode values from the 64-bit
1354 FP registers without using a full 64-bit load/store, we need
1355 to allocate a full 64-bit stack slot for them. */
1357 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1358 rs6000_secondary_memory_needed_rtx (MODE)
1360 /* Return the maximum number of consecutive registers
1361 needed to represent mode MODE in a register of class CLASS.
1363 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1364 a single reg is enough for two words, unless we have VSX, where the FP
1365 registers can hold 128 bits. */
1366 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1368 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1370 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1371 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1373 /* Stack layout; function entry, exit and calling. */
1375 /* Define this if pushing a word on the stack
1376 makes the stack pointer a smaller address. */
1377 #define STACK_GROWS_DOWNWARD
1379 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1380 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1382 /* Define this to nonzero if the nominal address of the stack frame
1383 is at the high-address end of the local variables;
1384 that is, each additional local variable allocated
1385 goes at a more negative offset in the frame.
1387 On the RS/6000, we grow upwards, from the area after the outgoing
1389 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1391 /* Size of the outgoing register save area */
1392 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1393 || DEFAULT_ABI == ABI_DARWIN) \
1394 ? (TARGET_64BIT ? 64 : 32) \
1397 /* Size of the fixed area on the stack */
1398 #define RS6000_SAVE_AREA \
1399 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1400 << (TARGET_64BIT ? 1 : 0))
1402 /* MEM representing address to save the TOC register */
1403 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1404 plus_constant (stack_pointer_rtx, \
1405 (TARGET_32BIT ? 20 : 40)))
1407 /* Align an address */
1408 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1410 /* Offset within stack frame to start allocating local variables at.
1411 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1412 first local allocated. Otherwise, it is the offset to the BEGINNING
1413 of the first local allocated.
1415 On the RS/6000, the frame pointer is the same as the stack pointer,
1416 except for dynamic allocations. So we start after the fixed area and
1417 outgoing parameter area. */
1419 #define STARTING_FRAME_OFFSET \
1420 (FRAME_GROWS_DOWNWARD \
1422 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1423 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1424 + RS6000_SAVE_AREA))
1426 /* Offset from the stack pointer register to an item dynamically
1427 allocated on the stack, e.g., by `alloca'.
1429 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1430 length of the outgoing arguments. The default is correct for most
1431 machines. See `function.c' for details. */
1432 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1433 (RS6000_ALIGN (crtl->outgoing_args_size, \
1434 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1435 + (STACK_POINTER_OFFSET))
1437 /* If we generate an insn to push BYTES bytes,
1438 this says how many the stack pointer really advances by.
1439 On RS/6000, don't define this because there are no push insns. */
1440 /* #define PUSH_ROUNDING(BYTES) */
1442 /* Offset of first parameter from the argument pointer register value.
1443 On the RS/6000, we define the argument pointer to the start of the fixed
1445 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1447 /* Offset from the argument pointer register value to the top of
1448 stack. This is different from FIRST_PARM_OFFSET because of the
1449 register save area. */
1450 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1452 /* Define this if stack space is still allocated for a parameter passed
1453 in a register. The value is the number of bytes allocated to this
1455 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1457 /* Define this if the above stack space is to be considered part of the
1458 space allocated by the caller. */
1459 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1461 /* This is the difference between the logical top of stack and the actual sp.
1463 For the RS/6000, sp points past the fixed area. */
1464 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1466 /* Define this if the maximum size of all the outgoing args is to be
1467 accumulated and pushed during the prologue. The amount can be
1468 found in the variable crtl->outgoing_args_size. */
1469 #define ACCUMULATE_OUTGOING_ARGS 1
1471 /* Define how to find the value returned by a library function
1472 assuming the value has mode MODE. */
1474 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1476 /* DRAFT_V4_STRUCT_RET defaults off. */
1477 #define DRAFT_V4_STRUCT_RET 0
1479 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1480 #define DEFAULT_PCC_STRUCT_RETURN 0
1482 /* Mode of stack savearea.
1483 FUNCTION is VOIDmode because calling convention maintains SP.
1484 BLOCK needs Pmode for SP.
1485 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1486 #define STACK_SAVEAREA_MODE(LEVEL) \
1487 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1488 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1490 /* Minimum and maximum general purpose registers used to hold arguments. */
1491 #define GP_ARG_MIN_REG 3
1492 #define GP_ARG_MAX_REG 10
1493 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1495 /* Minimum and maximum floating point registers used to hold arguments. */
1496 #define FP_ARG_MIN_REG 33
1497 #define FP_ARG_AIX_MAX_REG 45
1498 #define FP_ARG_V4_MAX_REG 40
1499 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1500 || DEFAULT_ABI == ABI_DARWIN) \
1501 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1502 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1504 /* Minimum and maximum AltiVec registers used to hold arguments. */
1505 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1506 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1507 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1509 /* Return registers */
1510 #define GP_ARG_RETURN GP_ARG_MIN_REG
1511 #define FP_ARG_RETURN FP_ARG_MIN_REG
1512 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1514 /* Flags for the call/call_value rtl operations set up by function_arg */
1515 #define CALL_NORMAL 0x00000000 /* no special processing */
1516 /* Bits in 0x00000001 are unused. */
1517 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1518 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1519 #define CALL_LONG 0x00000008 /* always call indirect */
1520 #define CALL_LIBCALL 0x00000010 /* libcall */
1522 /* We don't have prologue and epilogue functions to save/restore
1523 everything for most ABIs. */
1524 #define WORLD_SAVE_P(INFO) 0
1526 /* 1 if N is a possible register number for a function value
1527 as seen by the caller.
1529 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1530 #define FUNCTION_VALUE_REGNO_P(N) \
1531 ((N) == GP_ARG_RETURN \
1532 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1533 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1535 /* 1 if N is a possible register number for function argument passing.
1536 On RS/6000, these are r3-r10 and fp1-fp13.
1537 On AltiVec, v2 - v13 are used for passing vectors. */
1538 #define FUNCTION_ARG_REGNO_P(N) \
1539 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1540 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1541 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1542 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1543 && TARGET_HARD_FLOAT && TARGET_FPRS))
1545 /* Define a data type for recording info about an argument list
1546 during the scan of that argument list. This data type should
1547 hold all necessary information about the function itself
1548 and about the args processed so far, enough to enable macros
1549 such as FUNCTION_ARG to determine where the next arg should go.
1551 On the RS/6000, this is a structure. The first element is the number of
1552 total argument words, the second is used to store the next
1553 floating-point register number, and the third says how many more args we
1554 have prototype types for.
1556 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1557 the next available GP register, `fregno' is the next available FP
1558 register, and `words' is the number of words used on the stack.
1560 The varargs/stdarg support requires that this structure's size
1561 be a multiple of sizeof(int). */
1563 typedef struct rs6000_args
1565 int words; /* # words used for passing GP registers */
1566 int fregno; /* next available FP register */
1567 int vregno; /* next available AltiVec register */
1568 int nargs_prototype; /* # args left in the current prototype */
1569 int prototype; /* Whether a prototype was defined */
1570 int stdarg; /* Whether function is a stdarg function. */
1571 int call_cookie; /* Do special things for this call */
1572 int sysv_gregno; /* next available GP register */
1573 int intoffset; /* running offset in struct (darwin64) */
1574 int use_stack; /* any part of struct on stack (darwin64) */
1575 int floats_in_gpr; /* count of SFmode floats taking up
1576 GPR space (darwin64) */
1577 int named; /* false for varargs params */
1578 int escapes; /* if function visible outside tu */
1581 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1582 for a call to a function whose data type is FNTYPE.
1583 For a library call, FNTYPE is 0. */
1585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1586 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1587 N_NAMED_ARGS, FNDECL, VOIDmode)
1589 /* Similar, but when scanning the definition of a procedure. We always
1590 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1592 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1593 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1594 1000, current_function_decl, VOIDmode)
1596 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1598 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1599 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1602 /* If defined, a C expression which determines whether, and in which
1603 direction, to pad out an argument with extra space. The value
1604 should be of type `enum direction': either `upward' to pad above
1605 the argument, `downward' to pad below, or `none' to inhibit
1608 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1610 #define PAD_VARARGS_DOWN \
1611 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1613 /* Output assembler code to FILE to increment profiler label # LABELNO
1614 for profiling a function entry. */
1616 #define FUNCTION_PROFILER(FILE, LABELNO) \
1617 output_function_profiler ((FILE), (LABELNO));
1619 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1620 the stack pointer does not matter. No definition is equivalent to
1623 On the RS/6000, this is nonzero because we can restore the stack from
1624 its backpointer, which we maintain. */
1625 #define EXIT_IGNORE_STACK 1
1627 /* Define this macro as a C expression that is nonzero for registers
1628 that are used by the epilogue or the return' pattern. The stack
1629 and frame pointer registers are already be assumed to be used as
1632 #define EPILOGUE_USES(REGNO) \
1633 ((reload_completed && (REGNO) == LR_REGNO) \
1634 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1635 || (crtl->calls_eh_return \
1640 /* Length in units of the trampoline for entering a nested function. */
1642 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1644 /* Definitions for __builtin_return_address and __builtin_frame_address.
1645 __builtin_return_address (0) should give link register (65), enable
1647 /* This should be uncommented, so that the link register is used, but
1648 currently this would result in unmatched insns and spilling fixed
1649 registers so we'll leave it for another day. When these problems are
1650 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1652 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1654 /* Number of bytes into the frame return addresses can be found. See
1655 rs6000_stack_info in rs6000.c for more information on how the different
1656 abi's store the return address. */
1657 #define RETURN_ADDRESS_OFFSET \
1658 ((DEFAULT_ABI == ABI_AIX \
1659 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1660 (DEFAULT_ABI == ABI_V4) ? 4 : \
1661 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1663 /* The current return address is in link register (65). The return address
1664 of anything farther back is accessed normally at an offset of 8 from the
1666 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1667 (rs6000_return_addr (COUNT, FRAME))
1670 /* Definitions for register eliminations.
1672 We have two registers that can be eliminated on the RS/6000. First, the
1673 frame pointer register can often be eliminated in favor of the stack
1674 pointer register. Secondly, the argument pointer register can always be
1675 eliminated; it is replaced with either the stack or frame pointer.
1677 In addition, we use the elimination mechanism to see if r30 is needed
1678 Initially we assume that it isn't. If it is, we spill it. This is done
1679 by making it an eliminable register. We replace it with itself so that
1680 if it isn't needed, then existing uses won't be modified. */
1682 /* This is an array of structures. Each structure initializes one pair
1683 of eliminable registers. The "from" register number is given first,
1684 followed by "to". Eliminations of the same "from" register are listed
1685 in order of preference. */
1686 #define ELIMINABLE_REGS \
1687 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1688 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1689 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1690 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1691 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1692 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1694 /* Define the offset between two registers, one to be eliminated, and the other
1695 its replacement, at the start of a routine. */
1696 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1697 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1699 /* Addressing modes, and classification of registers for them. */
1701 #define HAVE_PRE_DECREMENT 1
1702 #define HAVE_PRE_INCREMENT 1
1703 #define HAVE_PRE_MODIFY_DISP 1
1704 #define HAVE_PRE_MODIFY_REG 1
1706 /* Macros to check register numbers against specific register classes. */
1708 /* These assume that REGNO is a hard or pseudo reg number.
1709 They give nonzero only if REGNO is a hard reg of the suitable class
1710 or a pseudo reg currently allocated to a suitable hard reg.
1711 Since they use reg_renumber, they are safe only once reg_renumber
1712 has been allocated, which happens in local-alloc.c. */
1714 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1715 ((REGNO) < FIRST_PSEUDO_REGISTER \
1716 ? (REGNO) <= 31 || (REGNO) == 67 \
1717 || (REGNO) == FRAME_POINTER_REGNUM \
1718 : (reg_renumber[REGNO] >= 0 \
1719 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1720 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1722 #define REGNO_OK_FOR_BASE_P(REGNO) \
1723 ((REGNO) < FIRST_PSEUDO_REGISTER \
1724 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1725 || (REGNO) == FRAME_POINTER_REGNUM \
1726 : (reg_renumber[REGNO] > 0 \
1727 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1728 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1730 /* Nonzero if X is a hard reg that can be used as an index
1731 or if it is a pseudo reg in the non-strict case. */
1732 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1733 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1734 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1736 /* Nonzero if X is a hard reg that can be used as a base reg
1737 or if it is a pseudo reg in the non-strict case. */
1738 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1739 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1740 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1743 /* Maximum number of registers that can appear in a valid memory address. */
1745 #define MAX_REGS_PER_ADDRESS 2
1747 /* Recognize any constant value that is a valid address. */
1749 #define CONSTANT_ADDRESS_P(X) \
1750 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1751 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1752 || GET_CODE (X) == HIGH)
1754 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1755 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1756 && EASY_VECTOR_15((n) >> 1) \
1759 #define EASY_VECTOR_MSB(n,mode) \
1760 (((unsigned HOST_WIDE_INT)n) == \
1761 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1764 /* Try a machine-dependent way of reloading an illegitimate address
1765 operand. If we find one, push the reload and jump to WIN. This
1766 macro is used in only one place: `find_reloads_address' in reload.c.
1768 Implemented on rs6000 by rs6000_legitimize_reload_address.
1769 Note that (X) is evaluated twice; this is safe in current usage. */
1771 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1774 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1775 (int)(TYPE), (IND_LEVELS), &win); \
1780 #define FIND_BASE_TERM rs6000_find_base_term
1782 /* The register number of the register used to address a table of
1783 static data addresses in memory. In some cases this register is
1784 defined by a processor's "application binary interface" (ABI).
1785 When this macro is defined, RTL is generated for this register
1786 once, as with the stack pointer and frame pointer registers. If
1787 this macro is not defined, it is up to the machine-dependent files
1788 to allocate such a register (if necessary). */
1790 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1791 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1793 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1795 /* Define this macro if the register defined by
1796 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1797 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1799 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1801 /* A C expression that is nonzero if X is a legitimate immediate
1802 operand on the target machine when generating position independent
1803 code. You can assume that X satisfies `CONSTANT_P', so you need
1804 not check this. You can also assume FLAG_PIC is true, so you need
1805 not check it either. You need not define this macro if all
1806 constants (including `SYMBOL_REF') can be immediate operands when
1807 generating position independent code. */
1809 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1811 /* Define this if some processing needs to be done immediately before
1812 emitting code for an insn. */
1814 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1815 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
1817 /* Specify the machine mode that this machine uses
1818 for the index in the tablejump instruction. */
1819 #define CASE_VECTOR_MODE SImode
1821 /* Define as C expression which evaluates to nonzero if the tablejump
1822 instruction expects the table to contain offsets from the address of the
1824 Do not define this if the table should contain absolute addresses. */
1825 #define CASE_VECTOR_PC_RELATIVE 1
1827 /* Define this as 1 if `char' should by default be signed; else as 0. */
1828 #define DEFAULT_SIGNED_CHAR 0
1830 /* This flag, if defined, says the same insns that convert to a signed fixnum
1831 also convert validly to an unsigned one. */
1833 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1835 /* An integer expression for the size in bits of the largest integer machine
1836 mode that should actually be used. */
1838 /* Allow pairs of registers to be used, which is the intent of the default. */
1839 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1841 /* Max number of bytes we can move from memory to memory
1842 in one reasonably fast instruction. */
1843 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1844 #define MAX_MOVE_MAX 8
1846 /* Nonzero if access to memory by bytes is no faster than for words.
1847 Also nonzero if doing byte operations (specifically shifts) in registers
1849 #define SLOW_BYTE_ACCESS 1
1851 /* Define if operations between registers always perform the operation
1852 on the full register even if a narrower mode is specified. */
1853 #define WORD_REGISTER_OPERATIONS
1855 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1856 will either zero-extend or sign-extend. The value of this macro should
1857 be the code that says which one of the two operations is implicitly
1858 done, UNKNOWN if none. */
1859 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1861 /* Define if loading short immediate values into registers sign extends. */
1862 #define SHORT_IMMEDIATES_SIGN_EXTEND
1864 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1865 is done just by pretending it is already truncated. */
1866 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1868 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1869 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1870 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1872 /* The CTZ patterns return -1 for input of zero. */
1873 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1875 /* Specify the machine mode that pointers have.
1876 After generation of rtl, the compiler makes no further distinction
1877 between pointers and any other objects of this machine mode. */
1878 extern unsigned rs6000_pmode;
1879 #define Pmode ((enum machine_mode)rs6000_pmode)
1881 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1882 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1884 /* Mode of a function address in a call instruction (for indexing purposes).
1885 Doesn't matter on RS/6000. */
1886 #define FUNCTION_MODE SImode
1888 /* Define this if addresses of constant functions
1889 shouldn't be put through pseudo regs where they can be cse'd.
1890 Desirable on machines where ordinary constants are expensive
1891 but a CALL with constant address is cheap. */
1892 #define NO_FUNCTION_CSE
1894 /* Define this to be nonzero if shift instructions ignore all but the low-order
1897 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1898 have been dropped from the PowerPC architecture. */
1900 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1902 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1903 should be adjusted to reflect any required changes. This macro is used when
1904 there is some systematic length adjustment required that would be difficult
1905 to express in the length attribute. */
1907 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1909 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1910 COMPARE, return the mode to be used for the comparison. For
1911 floating-point, CCFPmode should be used. CCUNSmode should be used
1912 for unsigned comparisons. CCEQmode should be used when we are
1913 doing an inequality comparison on the result of a
1914 comparison. CCmode should be used in all other cases. */
1916 #define SELECT_CC_MODE(OP,X,Y) \
1917 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1918 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1919 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1920 ? CCEQmode : CCmode))
1922 /* Can the condition code MODE be safely reversed? This is safe in
1923 all cases on this port, because at present it doesn't use the
1924 trapping FP comparisons (fcmpo). */
1925 #define REVERSIBLE_CC_MODE(MODE) 1
1927 /* Given a condition code and a mode, return the inverse condition. */
1928 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1931 /* Control the assembler format that we output. */
1933 /* A C string constant describing how to begin a comment in the target
1934 assembler language. The compiler assumes that the comment will end at
1935 the end of the line. */
1936 #define ASM_COMMENT_START " #"
1938 /* Flag to say the TOC is initialized */
1939 extern int toc_initialized;
1941 /* Macro to output a special constant pool entry. Go to WIN if we output
1942 it. Otherwise, it is written the usual way.
1944 On the RS/6000, toc entries are handled this way. */
1946 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1947 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1949 output_toc (FILE, X, LABELNO, MODE); \
1954 #ifdef HAVE_GAS_WEAK
1955 #define RS6000_WEAK 1
1957 #define RS6000_WEAK 0
1961 /* Used in lieu of ASM_WEAKEN_LABEL. */
1962 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1965 fputs ("\t.weak\t", (FILE)); \
1966 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1967 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1968 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1971 fputs ("[DS]", (FILE)); \
1972 fputs ("\n\t.weak\t.", (FILE)); \
1973 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1975 fputc ('\n', (FILE)); \
1978 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1979 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1980 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1982 fputs ("\t.set\t.", (FILE)); \
1983 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1984 fputs (",.", (FILE)); \
1985 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
1986 fputc ('\n', (FILE)); \
1993 #if HAVE_GAS_WEAKREF
1994 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1997 fputs ("\t.weakref\t", (FILE)); \
1998 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1999 fputs (", ", (FILE)); \
2000 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2001 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2002 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2004 fputs ("\n\t.weakref\t.", (FILE)); \
2005 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2006 fputs (", .", (FILE)); \
2007 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2009 fputc ('\n', (FILE)); \
2013 /* This implements the `alias' attribute. */
2014 #undef ASM_OUTPUT_DEF_FROM_DECLS
2015 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2018 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2019 const char *name = IDENTIFIER_POINTER (TARGET); \
2020 if (TREE_CODE (DECL) == FUNCTION_DECL \
2021 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2023 if (TREE_PUBLIC (DECL)) \
2025 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2027 fputs ("\t.globl\t.", FILE); \
2028 RS6000_OUTPUT_BASENAME (FILE, alias); \
2029 putc ('\n', FILE); \
2032 else if (TARGET_XCOFF) \
2034 fputs ("\t.lglobl\t.", FILE); \
2035 RS6000_OUTPUT_BASENAME (FILE, alias); \
2036 putc ('\n', FILE); \
2038 fputs ("\t.set\t.", FILE); \
2039 RS6000_OUTPUT_BASENAME (FILE, alias); \
2040 fputs (",.", FILE); \
2041 RS6000_OUTPUT_BASENAME (FILE, name); \
2042 fputc ('\n', FILE); \
2044 ASM_OUTPUT_DEF (FILE, alias, name); \
2048 #define TARGET_ASM_FILE_START rs6000_file_start
2050 /* Output to assembler file text saying following lines
2051 may contain character constants, extra white space, comments, etc. */
2053 #define ASM_APP_ON ""
2055 /* Output to assembler file text saying following lines
2056 no longer contain unusual constructs. */
2058 #define ASM_APP_OFF ""
2060 /* How to refer to registers in assembler output.
2061 This sequence is indexed by compiler's hard-register-number (see above). */
2063 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2065 #define REGISTER_NAMES \
2067 &rs6000_reg_names[ 0][0], /* r0 */ \
2068 &rs6000_reg_names[ 1][0], /* r1 */ \
2069 &rs6000_reg_names[ 2][0], /* r2 */ \
2070 &rs6000_reg_names[ 3][0], /* r3 */ \
2071 &rs6000_reg_names[ 4][0], /* r4 */ \
2072 &rs6000_reg_names[ 5][0], /* r5 */ \
2073 &rs6000_reg_names[ 6][0], /* r6 */ \
2074 &rs6000_reg_names[ 7][0], /* r7 */ \
2075 &rs6000_reg_names[ 8][0], /* r8 */ \
2076 &rs6000_reg_names[ 9][0], /* r9 */ \
2077 &rs6000_reg_names[10][0], /* r10 */ \
2078 &rs6000_reg_names[11][0], /* r11 */ \
2079 &rs6000_reg_names[12][0], /* r12 */ \
2080 &rs6000_reg_names[13][0], /* r13 */ \
2081 &rs6000_reg_names[14][0], /* r14 */ \
2082 &rs6000_reg_names[15][0], /* r15 */ \
2083 &rs6000_reg_names[16][0], /* r16 */ \
2084 &rs6000_reg_names[17][0], /* r17 */ \
2085 &rs6000_reg_names[18][0], /* r18 */ \
2086 &rs6000_reg_names[19][0], /* r19 */ \
2087 &rs6000_reg_names[20][0], /* r20 */ \
2088 &rs6000_reg_names[21][0], /* r21 */ \
2089 &rs6000_reg_names[22][0], /* r22 */ \
2090 &rs6000_reg_names[23][0], /* r23 */ \
2091 &rs6000_reg_names[24][0], /* r24 */ \
2092 &rs6000_reg_names[25][0], /* r25 */ \
2093 &rs6000_reg_names[26][0], /* r26 */ \
2094 &rs6000_reg_names[27][0], /* r27 */ \
2095 &rs6000_reg_names[28][0], /* r28 */ \
2096 &rs6000_reg_names[29][0], /* r29 */ \
2097 &rs6000_reg_names[30][0], /* r30 */ \
2098 &rs6000_reg_names[31][0], /* r31 */ \
2100 &rs6000_reg_names[32][0], /* fr0 */ \
2101 &rs6000_reg_names[33][0], /* fr1 */ \
2102 &rs6000_reg_names[34][0], /* fr2 */ \
2103 &rs6000_reg_names[35][0], /* fr3 */ \
2104 &rs6000_reg_names[36][0], /* fr4 */ \
2105 &rs6000_reg_names[37][0], /* fr5 */ \
2106 &rs6000_reg_names[38][0], /* fr6 */ \
2107 &rs6000_reg_names[39][0], /* fr7 */ \
2108 &rs6000_reg_names[40][0], /* fr8 */ \
2109 &rs6000_reg_names[41][0], /* fr9 */ \
2110 &rs6000_reg_names[42][0], /* fr10 */ \
2111 &rs6000_reg_names[43][0], /* fr11 */ \
2112 &rs6000_reg_names[44][0], /* fr12 */ \
2113 &rs6000_reg_names[45][0], /* fr13 */ \
2114 &rs6000_reg_names[46][0], /* fr14 */ \
2115 &rs6000_reg_names[47][0], /* fr15 */ \
2116 &rs6000_reg_names[48][0], /* fr16 */ \
2117 &rs6000_reg_names[49][0], /* fr17 */ \
2118 &rs6000_reg_names[50][0], /* fr18 */ \
2119 &rs6000_reg_names[51][0], /* fr19 */ \
2120 &rs6000_reg_names[52][0], /* fr20 */ \
2121 &rs6000_reg_names[53][0], /* fr21 */ \
2122 &rs6000_reg_names[54][0], /* fr22 */ \
2123 &rs6000_reg_names[55][0], /* fr23 */ \
2124 &rs6000_reg_names[56][0], /* fr24 */ \
2125 &rs6000_reg_names[57][0], /* fr25 */ \
2126 &rs6000_reg_names[58][0], /* fr26 */ \
2127 &rs6000_reg_names[59][0], /* fr27 */ \
2128 &rs6000_reg_names[60][0], /* fr28 */ \
2129 &rs6000_reg_names[61][0], /* fr29 */ \
2130 &rs6000_reg_names[62][0], /* fr30 */ \
2131 &rs6000_reg_names[63][0], /* fr31 */ \
2133 &rs6000_reg_names[64][0], /* mq */ \
2134 &rs6000_reg_names[65][0], /* lr */ \
2135 &rs6000_reg_names[66][0], /* ctr */ \
2136 &rs6000_reg_names[67][0], /* ap */ \
2138 &rs6000_reg_names[68][0], /* cr0 */ \
2139 &rs6000_reg_names[69][0], /* cr1 */ \
2140 &rs6000_reg_names[70][0], /* cr2 */ \
2141 &rs6000_reg_names[71][0], /* cr3 */ \
2142 &rs6000_reg_names[72][0], /* cr4 */ \
2143 &rs6000_reg_names[73][0], /* cr5 */ \
2144 &rs6000_reg_names[74][0], /* cr6 */ \
2145 &rs6000_reg_names[75][0], /* cr7 */ \
2147 &rs6000_reg_names[76][0], /* ca */ \
2149 &rs6000_reg_names[77][0], /* v0 */ \
2150 &rs6000_reg_names[78][0], /* v1 */ \
2151 &rs6000_reg_names[79][0], /* v2 */ \
2152 &rs6000_reg_names[80][0], /* v3 */ \
2153 &rs6000_reg_names[81][0], /* v4 */ \
2154 &rs6000_reg_names[82][0], /* v5 */ \
2155 &rs6000_reg_names[83][0], /* v6 */ \
2156 &rs6000_reg_names[84][0], /* v7 */ \
2157 &rs6000_reg_names[85][0], /* v8 */ \
2158 &rs6000_reg_names[86][0], /* v9 */ \
2159 &rs6000_reg_names[87][0], /* v10 */ \
2160 &rs6000_reg_names[88][0], /* v11 */ \
2161 &rs6000_reg_names[89][0], /* v12 */ \
2162 &rs6000_reg_names[90][0], /* v13 */ \
2163 &rs6000_reg_names[91][0], /* v14 */ \
2164 &rs6000_reg_names[92][0], /* v15 */ \
2165 &rs6000_reg_names[93][0], /* v16 */ \
2166 &rs6000_reg_names[94][0], /* v17 */ \
2167 &rs6000_reg_names[95][0], /* v18 */ \
2168 &rs6000_reg_names[96][0], /* v19 */ \
2169 &rs6000_reg_names[97][0], /* v20 */ \
2170 &rs6000_reg_names[98][0], /* v21 */ \
2171 &rs6000_reg_names[99][0], /* v22 */ \
2172 &rs6000_reg_names[100][0], /* v23 */ \
2173 &rs6000_reg_names[101][0], /* v24 */ \
2174 &rs6000_reg_names[102][0], /* v25 */ \
2175 &rs6000_reg_names[103][0], /* v26 */ \
2176 &rs6000_reg_names[104][0], /* v27 */ \
2177 &rs6000_reg_names[105][0], /* v28 */ \
2178 &rs6000_reg_names[106][0], /* v29 */ \
2179 &rs6000_reg_names[107][0], /* v30 */ \
2180 &rs6000_reg_names[108][0], /* v31 */ \
2181 &rs6000_reg_names[109][0], /* vrsave */ \
2182 &rs6000_reg_names[110][0], /* vscr */ \
2183 &rs6000_reg_names[111][0], /* spe_acc */ \
2184 &rs6000_reg_names[112][0], /* spefscr */ \
2185 &rs6000_reg_names[113][0], /* sfp */ \
2188 /* Table of additional register names to use in user input. */
2190 #define ADDITIONAL_REGISTER_NAMES \
2191 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2192 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2193 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2194 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2195 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2196 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2197 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2198 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2199 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2200 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2201 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2202 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2203 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2204 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2205 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2206 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2207 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2208 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2209 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2210 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2211 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2212 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2213 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2214 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2215 {"vrsave", 109}, {"vscr", 110}, \
2216 {"spe_acc", 111}, {"spefscr", 112}, \
2217 /* no additional names for: mq, lr, ctr, ap */ \
2218 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2219 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2220 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2221 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2223 /* VSX registers overlaid on top of FR, Altivec registers */ \
2224 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2225 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2226 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2227 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2228 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2229 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2230 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2231 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2232 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2233 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2234 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2235 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2236 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2237 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2238 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2239 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
2241 /* Text to write out after a CALL that may be replaced by glue code by
2242 the loader. This depends on the AIX version. */
2243 #define RS6000_CALL_GLUE "cror 31,31,31"
2245 /* This is how to output an element of a case-vector that is relative. */
2247 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2248 do { char buf[100]; \
2249 fputs ("\t.long ", FILE); \
2250 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2251 assemble_name (FILE, buf); \
2253 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2254 assemble_name (FILE, buf); \
2255 putc ('\n', FILE); \
2258 /* This is how to output an assembler line
2259 that says to advance the location counter
2260 to a multiple of 2**LOG bytes. */
2262 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2264 fprintf (FILE, "\t.align %d\n", (LOG))
2266 /* How to align the given loop. */
2267 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2269 /* Pick up the return address upon entry to a procedure. Used for
2270 dwarf2 unwind information. This also enables the table driven
2273 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2274 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2276 /* Describe how we implement __builtin_eh_return. */
2277 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2278 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2280 /* Print operand X (an rtx) in assembler syntax to file FILE.
2281 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2282 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2284 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2286 /* Define which CODE values are valid. */
2288 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2289 ((CODE) == '.' || (CODE) == '&')
2291 /* Print a memory address as an operand to reference that memory location. */
2293 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2295 /* uncomment for disabling the corresponding default options */
2296 /* #define MACHINE_no_sched_interblock */
2297 /* #define MACHINE_no_sched_speculative */
2298 /* #define MACHINE_no_sched_speculative_load */
2300 /* General flags. */
2301 extern int frame_pointer_needed;
2303 /* Classification of the builtin functions as to which switches enable the
2304 builtin, and what attributes it should have. We used to use the target
2305 flags macros, but we've run out of bits, so we now map the options into new
2306 settings used here. */
2308 /* Builtin attributes. */
2309 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2310 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2311 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2312 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2313 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2314 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2315 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */
2316 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2317 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2319 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2320 #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
2321 #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */
2322 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2323 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2325 /* Miscellaneous information. */
2326 #define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */
2328 /* Convenience macros to document the instruction type. */
2329 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2330 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2332 /* Builtin targets. For now, we reuse the masks for those options that are in
2333 target flags, and pick two random bits for SPE and paired which aren't in
2335 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2336 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2337 #define RS6000_BTM_SPE MASK_STRING /* E500 */
2338 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
2339 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2340 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2341 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2342 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2343 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2344 #define RS6000_BTM_POWERPC MASK_POWERPC /* Target is powerpc. */
2345 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2347 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2351 | RS6000_BTM_FRSQRTE \
2352 | RS6000_BTM_FRSQRTES \
2353 | RS6000_BTM_POPCNTD \
2354 | RS6000_BTM_POWERPC \
2357 /* Define builtin enum index. */
2359 #undef RS6000_BUILTIN_1
2360 #undef RS6000_BUILTIN_2
2361 #undef RS6000_BUILTIN_3
2362 #undef RS6000_BUILTIN_A
2363 #undef RS6000_BUILTIN_D
2364 #undef RS6000_BUILTIN_E
2365 #undef RS6000_BUILTIN_P
2366 #undef RS6000_BUILTIN_Q
2367 #undef RS6000_BUILTIN_S
2368 #undef RS6000_BUILTIN_X
2370 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2371 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2372 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2373 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2374 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2375 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2376 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2377 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2378 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2379 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2381 enum rs6000_builtins
2383 #include "rs6000-builtin.def"
2385 RS6000_BUILTIN_COUNT
2388 #undef RS6000_BUILTIN_1
2389 #undef RS6000_BUILTIN_2
2390 #undef RS6000_BUILTIN_3
2391 #undef RS6000_BUILTIN_A
2392 #undef RS6000_BUILTIN_D
2393 #undef RS6000_BUILTIN_E
2394 #undef RS6000_BUILTIN_P
2395 #undef RS6000_BUILTIN_Q
2396 #undef RS6000_BUILTIN_S
2397 #undef RS6000_BUILTIN_X
2399 enum rs6000_builtin_type_index
2401 RS6000_BTI_NOT_OPAQUE,
2402 RS6000_BTI_opaque_V2SI,
2403 RS6000_BTI_opaque_V2SF,
2404 RS6000_BTI_opaque_p_V2SI,
2405 RS6000_BTI_opaque_V4SI,
2415 RS6000_BTI_unsigned_V16QI,
2416 RS6000_BTI_unsigned_V8HI,
2417 RS6000_BTI_unsigned_V4SI,
2418 RS6000_BTI_unsigned_V2DI,
2419 RS6000_BTI_bool_char, /* __bool char */
2420 RS6000_BTI_bool_short, /* __bool short */
2421 RS6000_BTI_bool_int, /* __bool int */
2422 RS6000_BTI_bool_long, /* __bool long */
2423 RS6000_BTI_pixel, /* __pixel */
2424 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2425 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2426 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2427 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2428 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2429 RS6000_BTI_long, /* long_integer_type_node */
2430 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2431 RS6000_BTI_long_long, /* long_long_integer_type_node */
2432 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2433 RS6000_BTI_INTQI, /* intQI_type_node */
2434 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2435 RS6000_BTI_INTHI, /* intHI_type_node */
2436 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2437 RS6000_BTI_INTSI, /* intSI_type_node */
2438 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2439 RS6000_BTI_INTDI, /* intDI_type_node */
2440 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2441 RS6000_BTI_float, /* float_type_node */
2442 RS6000_BTI_double, /* double_type_node */
2443 RS6000_BTI_void, /* void_type_node */
2448 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2449 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2450 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2451 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2452 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2453 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2454 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2455 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2456 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2457 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2458 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2459 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2460 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2461 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2462 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2463 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2464 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2465 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2466 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2467 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2468 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2469 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2470 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2471 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2472 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2473 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2474 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2476 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2477 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2478 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2479 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2480 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2481 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2482 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2483 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2484 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2485 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2486 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2487 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2488 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2489 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2490 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2492 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2493 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];