1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "integrate.h"
48 #include "target-def.h"
49 #include "langhooks.h"
52 #ifndef TARGET_NO_PROTOTYPE
53 #define TARGET_NO_PROTOTYPE 0
56 #define min(A,B) ((A) < (B) ? (A) : (B))
57 #define max(A,B) ((A) > (B) ? (A) : (B))
61 enum processor_type rs6000_cpu;
62 struct rs6000_cpu_select rs6000_select[3] =
64 /* switch name, tune arch */
65 { (const char *)0, "--with-cpu=", 1, 1 },
66 { (const char *)0, "-mcpu=", 1, 1 },
67 { (const char *)0, "-mtune=", 1, 0 },
70 /* Size of long double */
71 const char *rs6000_long_double_size_string;
72 int rs6000_long_double_type_size;
74 /* Whether -mabi=altivec has appeared */
75 int rs6000_altivec_abi;
77 /* Whether VRSAVE instructions should be generated. */
78 int rs6000_altivec_vrsave;
80 /* String from -mvrsave= option. */
81 const char *rs6000_altivec_vrsave_string;
83 /* Set to non-zero once AIX common-mode calls have been defined. */
84 static int common_mode_defined;
86 /* Save information from a "cmpxx" operation until the branch or scc is
88 rtx rs6000_compare_op0, rs6000_compare_op1;
89 int rs6000_compare_fp_p;
91 /* Label number of label created for -mrelocatable, to call to so we can
92 get the address of the GOT section */
93 int rs6000_pic_labelno;
96 /* Which abi to adhere to */
97 const char *rs6000_abi_name = RS6000_ABI_NAME;
99 /* Semantics of the small data area */
100 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
102 /* Which small data model to use */
103 const char *rs6000_sdata_name = (char *)0;
105 /* Counter for labels which are to be placed in .fixup. */
106 int fixuplabelno = 0;
109 /* ABI enumeration available for subtarget to use. */
110 enum rs6000_abi rs6000_current_abi;
112 /* ABI string from -mabi= option. */
113 const char *rs6000_abi_string;
116 const char *rs6000_debug_name;
117 int rs6000_debug_stack; /* debug stack applications */
118 int rs6000_debug_arg; /* debug argument handling */
120 /* Flag to say the TOC is initialized */
122 char toc_label_name[10];
124 /* Alias set for saves and restores from the rs6000 stack. */
125 static int rs6000_sr_alias_set;
127 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
128 The only place that looks at this is rs6000_set_default_type_attributes;
129 everywhere else should rely on the presence or absence of a longcall
130 attribute on the function declaration. */
131 int rs6000_default_long_calls;
132 const char *rs6000_longcall_switch;
134 static void rs6000_add_gc_roots PARAMS ((void));
135 static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT));
136 static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx));
137 static void validate_condition_mode
138 PARAMS ((enum rtx_code, enum machine_mode));
139 static rtx rs6000_generate_compare PARAMS ((enum rtx_code));
140 static void rs6000_maybe_dead PARAMS ((rtx));
141 static void rs6000_emit_stack_tie PARAMS ((void));
142 static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx));
143 static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int));
144 static unsigned rs6000_hash_constant PARAMS ((rtx));
145 static unsigned toc_hash_function PARAMS ((const void *));
146 static int toc_hash_eq PARAMS ((const void *, const void *));
147 static int toc_hash_mark_entry PARAMS ((void **, void *));
148 static void toc_hash_mark_table PARAMS ((void *));
149 static int constant_pool_expr_1 PARAMS ((rtx, int *, int *));
150 static void rs6000_free_machine_status PARAMS ((struct function *));
151 static void rs6000_init_machine_status PARAMS ((struct function *));
152 static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int));
153 static int rs6000_ra_ever_killed PARAMS ((void));
154 static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *));
155 const struct attribute_spec rs6000_attribute_table[];
156 static void rs6000_set_default_type_attributes PARAMS ((tree));
157 static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
158 static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
159 static rtx rs6000_emit_set_long_const PARAMS ((rtx,
160 HOST_WIDE_INT, HOST_WIDE_INT));
162 static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *,
164 static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int));
165 static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int));
166 static void rs6000_elf_select_section PARAMS ((tree, int,
167 unsigned HOST_WIDE_INT));
168 static void rs6000_elf_unique_section PARAMS ((tree, int));
169 static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx,
170 unsigned HOST_WIDE_INT));
171 static void rs6000_elf_encode_section_info PARAMS ((tree, int));
172 static const char *rs6000_elf_strip_name_encoding PARAMS ((const char *));
174 #ifdef OBJECT_FORMAT_COFF
175 static void xcoff_asm_named_section PARAMS ((const char *, unsigned int));
176 static void rs6000_xcoff_select_section PARAMS ((tree, int,
177 unsigned HOST_WIDE_INT));
178 static void rs6000_xcoff_unique_section PARAMS ((tree, int));
179 static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx,
180 unsigned HOST_WIDE_INT));
181 static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *));
183 static void rs6000_xcoff_encode_section_info PARAMS ((tree, int))
185 static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
186 static int rs6000_adjust_priority PARAMS ((rtx, int));
187 static int rs6000_issue_rate PARAMS ((void));
189 static void rs6000_init_builtins PARAMS ((void));
190 static void altivec_init_builtins PARAMS ((void));
191 static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
192 static rtx altivec_expand_builtin PARAMS ((tree, rtx));
193 static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
194 static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx));
195 static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx));
196 static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx));
197 static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx));
198 static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
199 static void rs6000_parse_abi_options PARAMS ((void));
200 static void rs6000_parse_vrsave_option PARAMS ((void));
201 static int first_altivec_reg_to_save PARAMS ((void));
202 static unsigned int compute_vrsave_mask PARAMS ((void));
203 static void is_altivec_return_reg PARAMS ((rtx, void *));
204 int vrsave_operation PARAMS ((rtx, enum machine_mode));
205 static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int));
206 static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT));
207 static int easy_vector_constant PARAMS ((rtx));
209 /* Default register names. */
210 char rs6000_reg_names[][8] =
212 "0", "1", "2", "3", "4", "5", "6", "7",
213 "8", "9", "10", "11", "12", "13", "14", "15",
214 "16", "17", "18", "19", "20", "21", "22", "23",
215 "24", "25", "26", "27", "28", "29", "30", "31",
216 "0", "1", "2", "3", "4", "5", "6", "7",
217 "8", "9", "10", "11", "12", "13", "14", "15",
218 "16", "17", "18", "19", "20", "21", "22", "23",
219 "24", "25", "26", "27", "28", "29", "30", "31",
220 "mq", "lr", "ctr","ap",
221 "0", "1", "2", "3", "4", "5", "6", "7",
223 /* AltiVec registers. */
224 "0", "1", "2", "3", "4", "5", "6", "7",
225 "8", "9", "10", "11", "12", "13", "14", "15",
226 "16", "17", "18", "19", "20", "21", "22", "23",
227 "24", "25", "26", "27", "28", "29", "30", "31",
231 #ifdef TARGET_REGNAMES
232 static const char alt_reg_names[][8] =
234 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
235 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
236 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
237 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
238 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
239 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
240 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
241 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
242 "mq", "lr", "ctr", "ap",
243 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
245 /* AltiVec registers. */
246 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
247 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
248 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
249 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
254 #ifndef MASK_STRICT_ALIGN
255 #define MASK_STRICT_ALIGN 0
258 /* Initialize the GCC target structure. */
259 #undef TARGET_ATTRIBUTE_TABLE
260 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
261 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
262 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
264 #undef TARGET_ASM_ALIGNED_DI_OP
265 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
267 /* Default unaligned ops are only provided for ELF. Find the ops needed
268 for non-ELF systems. */
269 #ifndef OBJECT_FORMAT_ELF
270 #ifdef OBJECT_FORMAT_COFF
271 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
273 #undef TARGET_ASM_UNALIGNED_HI_OP
274 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
275 #undef TARGET_ASM_UNALIGNED_SI_OP
276 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
277 #undef TARGET_ASM_UNALIGNED_DI_OP
278 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
281 #undef TARGET_ASM_UNALIGNED_HI_OP
282 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
283 #undef TARGET_ASM_UNALIGNED_SI_OP
284 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
288 /* This hook deals with fixups for relocatable code and DI-mode objects
290 #undef TARGET_ASM_INTEGER
291 #define TARGET_ASM_INTEGER rs6000_assemble_integer
293 #undef TARGET_ASM_FUNCTION_PROLOGUE
294 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
295 #undef TARGET_ASM_FUNCTION_EPILOGUE
296 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
299 #undef TARGET_SECTION_TYPE_FLAGS
300 #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags
303 #undef TARGET_SCHED_ISSUE_RATE
304 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
305 #undef TARGET_SCHED_ADJUST_COST
306 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
307 #undef TARGET_SCHED_ADJUST_PRIORITY
308 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
310 #undef TARGET_INIT_BUILTINS
311 #define TARGET_INIT_BUILTINS rs6000_init_builtins
313 #undef TARGET_EXPAND_BUILTIN
314 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
316 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
317 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
319 struct gcc_target targetm = TARGET_INITIALIZER;
321 /* Override command line options. Mostly we process the processor
322 type and sometimes adjust other TARGET_ options. */
325 rs6000_override_options (default_cpu)
326 const char *default_cpu;
329 struct rs6000_cpu_select *ptr;
331 /* Simplify the entries below by making a mask for any POWER
332 variant and any PowerPC variant. */
334 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
335 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
336 | MASK_PPC_GFXOPT | MASK_POWERPC64)
337 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
341 const char *const name; /* Canonical processor name. */
342 const enum processor_type processor; /* Processor type enum value. */
343 const int target_enable; /* Target flags to enable. */
344 const int target_disable; /* Target flags to disable. */
345 } const processor_target_table[]
346 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
347 POWER_MASKS | POWERPC_MASKS},
348 {"power", PROCESSOR_POWER,
349 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
350 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
351 {"power2", PROCESSOR_POWER,
352 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
353 POWERPC_MASKS | MASK_NEW_MNEMONICS},
354 {"power3", PROCESSOR_PPC630,
355 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
356 POWER_MASKS | MASK_PPC_GPOPT},
357 {"powerpc", PROCESSOR_POWERPC,
358 MASK_POWERPC | MASK_NEW_MNEMONICS,
359 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
360 {"powerpc64", PROCESSOR_POWERPC64,
361 MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
362 POWER_MASKS | POWERPC_OPT_MASKS},
363 {"rios", PROCESSOR_RIOS1,
364 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
365 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
366 {"rios1", PROCESSOR_RIOS1,
367 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
368 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
369 {"rsc", PROCESSOR_PPC601,
370 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
371 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
372 {"rsc1", PROCESSOR_PPC601,
373 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
374 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
375 {"rios2", PROCESSOR_RIOS2,
376 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
377 POWERPC_MASKS | MASK_NEW_MNEMONICS},
378 {"rs64a", PROCESSOR_RS64A,
379 MASK_POWERPC | MASK_NEW_MNEMONICS,
380 POWER_MASKS | POWERPC_OPT_MASKS},
381 {"401", PROCESSOR_PPC403,
382 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
383 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
384 {"403", PROCESSOR_PPC403,
385 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
386 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
387 {"405", PROCESSOR_PPC405,
388 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
389 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
390 {"505", PROCESSOR_MPCCORE,
391 MASK_POWERPC | MASK_NEW_MNEMONICS,
392 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
393 {"601", PROCESSOR_PPC601,
394 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
395 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
396 {"602", PROCESSOR_PPC603,
397 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
398 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
399 {"603", PROCESSOR_PPC603,
400 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
401 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
402 {"603e", PROCESSOR_PPC603,
403 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
404 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
405 {"ec603e", PROCESSOR_PPC603,
406 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
407 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
408 {"604", PROCESSOR_PPC604,
409 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
410 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
411 {"604e", PROCESSOR_PPC604e,
412 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
413 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
414 {"620", PROCESSOR_PPC620,
415 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
416 POWER_MASKS | MASK_PPC_GPOPT},
417 {"630", PROCESSOR_PPC630,
418 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
419 POWER_MASKS | MASK_PPC_GPOPT},
420 {"740", PROCESSOR_PPC750,
421 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
422 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
423 {"750", PROCESSOR_PPC750,
424 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
425 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
426 {"7400", PROCESSOR_PPC7400,
427 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
428 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
429 {"7450", PROCESSOR_PPC7450,
430 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
431 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
432 {"801", PROCESSOR_MPCCORE,
433 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
434 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
435 {"821", PROCESSOR_MPCCORE,
436 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
437 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
438 {"823", PROCESSOR_MPCCORE,
439 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
440 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
441 {"860", PROCESSOR_MPCCORE,
442 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
443 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
445 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
447 /* Save current -mmultiple/-mno-multiple status. */
448 int multiple = TARGET_MULTIPLE;
449 /* Save current -mstring/-mno-string status. */
450 int string = TARGET_STRING;
452 /* Identify the processor type. */
453 rs6000_select[0].string = default_cpu;
454 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
456 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
458 ptr = &rs6000_select[i];
459 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
461 for (j = 0; j < ptt_size; j++)
462 if (! strcmp (ptr->string, processor_target_table[j].name))
465 rs6000_cpu = processor_target_table[j].processor;
469 target_flags |= processor_target_table[j].target_enable;
470 target_flags &= ~processor_target_table[j].target_disable;
476 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
480 /* If we are optimizing big endian systems for space, use the store
481 multiple instructions. */
482 if (BYTES_BIG_ENDIAN && optimize_size)
483 target_flags |= MASK_MULTIPLE;
485 /* If -mmultiple or -mno-multiple was explicitly used, don't
486 override with the processor default */
487 if (TARGET_MULTIPLE_SET)
488 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
490 /* If -mstring or -mno-string was explicitly used, don't override
491 with the processor default. */
492 if (TARGET_STRING_SET)
493 target_flags = (target_flags & ~MASK_STRING) | string;
495 /* Don't allow -mmultiple or -mstring on little endian systems
496 unless the cpu is a 750, because the hardware doesn't support the
497 instructions used in little endian mode, and causes an alignment
498 trap. The 750 does not cause an alignment trap (except when the
499 target is unaligned). */
501 if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
505 target_flags &= ~MASK_MULTIPLE;
506 if (TARGET_MULTIPLE_SET)
507 warning ("-mmultiple is not supported on little endian systems");
512 target_flags &= ~MASK_STRING;
513 if (TARGET_STRING_SET)
514 warning ("-mstring is not supported on little endian systems");
518 if (flag_pic != 0 && DEFAULT_ABI == ABI_AIX)
523 warning ("-f%s ignored (all code is position independent)",
524 (flag_pic > 1) ? "PIC" : "pic");
527 #ifdef XCOFF_DEBUGGING_INFO
528 if (flag_function_sections && (write_symbols != NO_DEBUG)
529 && DEFAULT_ABI == ABI_AIX)
531 warning ("-ffunction-sections disabled on AIX when debugging");
532 flag_function_sections = 0;
535 if (flag_data_sections && (DEFAULT_ABI == ABI_AIX))
537 warning ("-fdata-sections not supported on AIX");
538 flag_data_sections = 0;
542 /* Set debug flags */
543 if (rs6000_debug_name)
545 if (! strcmp (rs6000_debug_name, "all"))
546 rs6000_debug_stack = rs6000_debug_arg = 1;
547 else if (! strcmp (rs6000_debug_name, "stack"))
548 rs6000_debug_stack = 1;
549 else if (! strcmp (rs6000_debug_name, "arg"))
550 rs6000_debug_arg = 1;
552 error ("unknown -mdebug-%s switch", rs6000_debug_name);
555 /* Set size of long double */
556 rs6000_long_double_type_size = 64;
557 if (rs6000_long_double_size_string)
560 int size = strtol (rs6000_long_double_size_string, &tail, 10);
561 if (*tail != '\0' || (size != 64 && size != 128))
562 error ("Unknown switch -mlong-double-%s",
563 rs6000_long_double_size_string);
565 rs6000_long_double_type_size = size;
568 /* Handle -mabi= options. */
569 rs6000_parse_abi_options ();
571 /* Handle -mvrsave= option. */
572 rs6000_parse_vrsave_option ();
574 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
575 using TARGET_OPTIONS to handle a toggle switch, but we're out of
576 bits in target_flags so TARGET_SWITCHES cannot be used.
577 Assumption here is that rs6000_longcall_switch points into the
578 text of the complete option, rather than being a copy, so we can
579 scan back for the presence or absence of the no- modifier. */
580 if (rs6000_longcall_switch)
582 const char *base = rs6000_longcall_switch;
583 while (base[-1] != 'm') base--;
585 if (*rs6000_longcall_switch != '\0')
586 error ("invalid option `%s'", base);
587 rs6000_default_long_calls = (base[0] != 'n');
590 #ifdef TARGET_REGNAMES
591 /* If the user desires alternate register names, copy in the
592 alternate names now. */
594 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
597 #ifdef SUBTARGET_OVERRIDE_OPTIONS
598 SUBTARGET_OVERRIDE_OPTIONS;
600 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
601 SUBSUBTARGET_OVERRIDE_OPTIONS;
604 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
605 If -maix-struct-return or -msvr4-struct-return was explicitly
606 used, don't override with the ABI default. */
607 if (!(target_flags & MASK_AIX_STRUCT_RET_SET))
609 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
610 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
612 target_flags |= MASK_AIX_STRUCT_RET;
615 /* Register global variables with the garbage collector. */
616 rs6000_add_gc_roots ();
618 /* Allocate an alias set for register saves & restores from stack. */
619 rs6000_sr_alias_set = new_alias_set ();
622 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
624 /* We can only guarantee the availability of DI pseudo-ops when
625 assembling for 64-bit targets. */
628 targetm.asm_out.aligned_op.di = NULL;
629 targetm.asm_out.unaligned_op.di = NULL;
632 /* Arrange to save and restore machine status around nested functions. */
633 init_machine_status = rs6000_init_machine_status;
634 free_machine_status = rs6000_free_machine_status;
637 /* Handle -mvrsave= options. */
639 rs6000_parse_vrsave_option ()
641 /* Generate VRSAVE instructions by default. */
642 if (rs6000_altivec_vrsave_string == 0
643 || ! strcmp (rs6000_altivec_vrsave_string, "yes"))
644 rs6000_altivec_vrsave = 1;
645 else if (! strcmp (rs6000_altivec_vrsave_string, "no"))
646 rs6000_altivec_vrsave = 0;
648 error ("unknown -mvrsave= option specified: '%s'",
649 rs6000_altivec_vrsave_string);
652 /* Handle -mabi= options. */
654 rs6000_parse_abi_options ()
656 if (rs6000_abi_string == 0)
658 else if (! strcmp (rs6000_abi_string, "altivec"))
659 rs6000_altivec_abi = 1;
660 else if (! strcmp (rs6000_abi_string, "no-altivec"))
661 rs6000_altivec_abi = 0;
663 error ("unknown ABI specified: '%s'", rs6000_abi_string);
667 optimization_options (level, size)
668 int level ATTRIBUTE_UNUSED;
669 int size ATTRIBUTE_UNUSED;
673 /* Do anything needed at the start of the asm file. */
676 rs6000_file_start (file, default_cpu)
678 const char *default_cpu;
682 const char *start = buffer;
683 struct rs6000_cpu_select *ptr;
685 if (flag_verbose_asm)
687 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
688 rs6000_select[0].string = default_cpu;
690 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
692 ptr = &rs6000_select[i];
693 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
695 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
701 switch (rs6000_sdata)
703 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
704 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
705 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
706 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
709 if (rs6000_sdata && g_switch_value)
711 fprintf (file, "%s -G %d", start, g_switch_value);
721 /* Return non-zero if this function is known to have a null epilogue. */
726 if (reload_completed)
728 rs6000_stack_t *info = rs6000_stack_info ();
730 if (info->first_gp_reg_save == 32
731 && info->first_fp_reg_save == 64
732 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
735 && info->vrsave_mask == 0
743 /* Returns 1 always. */
746 any_operand (op, mode)
747 rtx op ATTRIBUTE_UNUSED;
748 enum machine_mode mode ATTRIBUTE_UNUSED;
753 /* Returns 1 if op is the count register. */
755 count_register_operand (op, mode)
757 enum machine_mode mode ATTRIBUTE_UNUSED;
759 if (GET_CODE (op) != REG)
762 if (REGNO (op) == COUNT_REGISTER_REGNUM)
765 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
771 /* Returns 1 if op is an altivec register. */
773 altivec_register_operand (op, mode)
775 enum machine_mode mode ATTRIBUTE_UNUSED;
778 return (register_operand (op, mode)
779 && (GET_CODE (op) != REG
780 || REGNO (op) > FIRST_PSEUDO_REGISTER
781 || ALTIVEC_REGNO_P (REGNO (op))));
785 xer_operand (op, mode)
787 enum machine_mode mode ATTRIBUTE_UNUSED;
789 if (GET_CODE (op) != REG)
792 if (XER_REGNO_P (REGNO (op)))
798 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
799 by such constants completes more quickly. */
802 s8bit_cint_operand (op, mode)
804 enum machine_mode mode ATTRIBUTE_UNUSED;
806 return ( GET_CODE (op) == CONST_INT
807 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
810 /* Return 1 if OP is a constant that can fit in a D field. */
813 short_cint_operand (op, mode)
815 enum machine_mode mode ATTRIBUTE_UNUSED;
817 return (GET_CODE (op) == CONST_INT
818 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
821 /* Similar for an unsigned D field. */
824 u_short_cint_operand (op, mode)
826 enum machine_mode mode ATTRIBUTE_UNUSED;
828 return (GET_CODE (op) == CONST_INT
829 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
832 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
835 non_short_cint_operand (op, mode)
837 enum machine_mode mode ATTRIBUTE_UNUSED;
839 return (GET_CODE (op) == CONST_INT
840 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
843 /* Returns 1 if OP is a CONST_INT that is a positive value
844 and an exact power of 2. */
847 exact_log2_cint_operand (op, mode)
849 enum machine_mode mode ATTRIBUTE_UNUSED;
851 return (GET_CODE (op) == CONST_INT
853 && exact_log2 (INTVAL (op)) >= 0);
856 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
860 gpc_reg_operand (op, mode)
862 enum machine_mode mode;
864 return (register_operand (op, mode)
865 && (GET_CODE (op) != REG
866 || (REGNO (op) >= ARG_POINTER_REGNUM
867 && !XER_REGNO_P (REGNO (op)))
868 || REGNO (op) < MQ_REGNO));
871 /* Returns 1 if OP is either a pseudo-register or a register denoting a
875 cc_reg_operand (op, mode)
877 enum machine_mode mode;
879 return (register_operand (op, mode)
880 && (GET_CODE (op) != REG
881 || REGNO (op) >= FIRST_PSEUDO_REGISTER
882 || CR_REGNO_P (REGNO (op))));
885 /* Returns 1 if OP is either a pseudo-register or a register denoting a
886 CR field that isn't CR0. */
889 cc_reg_not_cr0_operand (op, mode)
891 enum machine_mode mode;
893 return (register_operand (op, mode)
894 && (GET_CODE (op) != REG
895 || REGNO (op) >= FIRST_PSEUDO_REGISTER
896 || CR_REGNO_NOT_CR0_P (REGNO (op))));
899 /* Returns 1 if OP is either a constant integer valid for a D-field or
900 a non-special register. If a register, it must be in the proper
901 mode unless MODE is VOIDmode. */
904 reg_or_short_operand (op, mode)
906 enum machine_mode mode;
908 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
911 /* Similar, except check if the negation of the constant would be
912 valid for a D-field. */
915 reg_or_neg_short_operand (op, mode)
917 enum machine_mode mode;
919 if (GET_CODE (op) == CONST_INT)
920 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
922 return gpc_reg_operand (op, mode);
925 /* Returns 1 if OP is either a constant integer valid for a DS-field or
926 a non-special register. If a register, it must be in the proper
927 mode unless MODE is VOIDmode. */
930 reg_or_aligned_short_operand (op, mode)
932 enum machine_mode mode;
934 if (gpc_reg_operand (op, mode))
936 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
943 /* Return 1 if the operand is either a register or an integer whose
944 high-order 16 bits are zero. */
947 reg_or_u_short_operand (op, mode)
949 enum machine_mode mode;
951 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
954 /* Return 1 is the operand is either a non-special register or ANY
958 reg_or_cint_operand (op, mode)
960 enum machine_mode mode;
962 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
965 /* Return 1 is the operand is either a non-special register or ANY
966 32-bit signed constant integer. */
969 reg_or_arith_cint_operand (op, mode)
971 enum machine_mode mode;
973 return (gpc_reg_operand (op, mode)
974 || (GET_CODE (op) == CONST_INT
975 #if HOST_BITS_PER_WIDE_INT != 32
976 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
977 < (unsigned HOST_WIDE_INT) 0x100000000ll)
982 /* Return 1 is the operand is either a non-special register or a 32-bit
983 signed constant integer valid for 64-bit addition. */
986 reg_or_add_cint64_operand (op, mode)
988 enum machine_mode mode;
990 return (gpc_reg_operand (op, mode)
991 || (GET_CODE (op) == CONST_INT
992 #if HOST_BITS_PER_WIDE_INT == 32
993 && INTVAL (op) < 0x7fff8000
995 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1001 /* Return 1 is the operand is either a non-special register or a 32-bit
1002 signed constant integer valid for 64-bit subtraction. */
1005 reg_or_sub_cint64_operand (op, mode)
1007 enum machine_mode mode;
1009 return (gpc_reg_operand (op, mode)
1010 || (GET_CODE (op) == CONST_INT
1011 #if HOST_BITS_PER_WIDE_INT == 32
1012 && (- INTVAL (op)) < 0x7fff8000
1014 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1020 /* Return 1 is the operand is either a non-special register or ANY
1021 32-bit unsigned constant integer. */
1024 reg_or_logical_cint_operand (op, mode)
1026 enum machine_mode mode;
1028 if (GET_CODE (op) == CONST_INT)
1030 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1032 if (GET_MODE_BITSIZE (mode) <= 32)
1035 if (INTVAL (op) < 0)
1039 return ((INTVAL (op) & GET_MODE_MASK (mode)
1040 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1042 else if (GET_CODE (op) == CONST_DOUBLE)
1044 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1048 return CONST_DOUBLE_HIGH (op) == 0;
1051 return gpc_reg_operand (op, mode);
1054 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1057 got_operand (op, mode)
1059 enum machine_mode mode ATTRIBUTE_UNUSED;
1061 return (GET_CODE (op) == SYMBOL_REF
1062 || GET_CODE (op) == CONST
1063 || GET_CODE (op) == LABEL_REF);
1066 /* Return 1 if the operand is a simple references that can be loaded via
1067 the GOT (labels involving addition aren't allowed). */
1070 got_no_const_operand (op, mode)
1072 enum machine_mode mode ATTRIBUTE_UNUSED;
1074 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1077 /* Return the number of instructions it takes to form a constant in an
1078 integer register. */
1081 num_insns_constant_wide (value)
1082 HOST_WIDE_INT value;
1084 /* signed constant loadable with {cal|addi} */
1085 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1088 /* constant loadable with {cau|addis} */
1089 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1092 #if HOST_BITS_PER_WIDE_INT == 64
1093 else if (TARGET_POWERPC64)
1095 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1096 HOST_WIDE_INT high = value >> 31;
1098 if (high == 0 || high == -1)
1104 return num_insns_constant_wide (high) + 1;
1106 return (num_insns_constant_wide (high)
1107 + num_insns_constant_wide (low) + 1);
1116 num_insns_constant (op, mode)
1118 enum machine_mode mode;
1120 if (GET_CODE (op) == CONST_INT)
1122 #if HOST_BITS_PER_WIDE_INT == 64
1123 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1124 && mask64_operand (op, mode))
1128 return num_insns_constant_wide (INTVAL (op));
1131 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1136 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1137 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1138 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1141 else if (GET_CODE (op) == CONST_DOUBLE)
1147 int endian = (WORDS_BIG_ENDIAN == 0);
1149 if (mode == VOIDmode || mode == DImode)
1151 high = CONST_DOUBLE_HIGH (op);
1152 low = CONST_DOUBLE_LOW (op);
1156 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1157 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1159 low = l[1 - endian];
1163 return (num_insns_constant_wide (low)
1164 + num_insns_constant_wide (high));
1168 if (high == 0 && low >= 0)
1169 return num_insns_constant_wide (low);
1171 else if (high == -1 && low < 0)
1172 return num_insns_constant_wide (low);
1174 else if (mask64_operand (op, mode))
1178 return num_insns_constant_wide (high) + 1;
1181 return (num_insns_constant_wide (high)
1182 + num_insns_constant_wide (low) + 1);
1190 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1191 register with one instruction per word. We only do this if we can
1192 safely read CONST_DOUBLE_{LOW,HIGH}. */
1195 easy_fp_constant (op, mode)
1197 enum machine_mode mode;
1199 if (GET_CODE (op) != CONST_DOUBLE
1200 || GET_MODE (op) != mode
1201 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1204 /* Consider all constants with -msoft-float to be easy. */
1205 if (TARGET_SOFT_FLOAT && mode != DImode)
1208 /* If we are using V.4 style PIC, consider all constants to be hard. */
1209 if (flag_pic && DEFAULT_ABI == ABI_V4)
1212 #ifdef TARGET_RELOCATABLE
1213 /* Similarly if we are using -mrelocatable, consider all constants
1215 if (TARGET_RELOCATABLE)
1224 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1225 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1227 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1228 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1231 else if (mode == SFmode)
1236 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1237 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1239 return num_insns_constant_wide (l) == 1;
1242 else if (mode == DImode)
1243 return ((TARGET_POWERPC64
1244 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1245 || (num_insns_constant (op, DImode) <= 2));
1247 else if (mode == SImode)
1253 /* Return 1 if the operand is a CONST_INT and can be put into a
1254 register with one instruction. */
1257 easy_vector_constant (op)
1263 if (GET_CODE (op) != CONST_VECTOR)
1266 units = CONST_VECTOR_NUNITS (op);
1268 /* We can generate 0 easily. Look for that. */
1269 for (i = 0; i < units; ++i)
1271 elt = CONST_VECTOR_ELT (op, i);
1273 /* We could probably simplify this by just checking for equality
1274 with CONST0_RTX for the current mode, but let's be safe
1277 switch (GET_CODE (elt))
1280 if (INTVAL (elt) != 0)
1284 if (CONST_DOUBLE_LOW (elt) != 0 || CONST_DOUBLE_HIGH (elt) != 0)
1292 /* We could probably generate a few other constants trivially, but
1293 gcc doesn't generate them yet. FIXME later. */
1297 /* Return 1 if the operand is the constant 0. This works for scalars
1298 as well as vectors. */
1300 zero_constant (op, mode)
1302 enum machine_mode mode;
1304 return op == CONST0_RTX (mode);
1307 /* Return 1 if the operand is 0.0. */
1309 zero_fp_constant (op, mode)
1311 enum machine_mode mode;
1313 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1316 /* Return 1 if the operand is in volatile memory. Note that during
1317 the RTL generation phase, memory_operand does not return TRUE for
1318 volatile memory references. So this function allows us to
1319 recognize volatile references where its safe. */
1322 volatile_mem_operand (op, mode)
1324 enum machine_mode mode;
1326 if (GET_CODE (op) != MEM)
1329 if (!MEM_VOLATILE_P (op))
1332 if (mode != GET_MODE (op))
1335 if (reload_completed)
1336 return memory_operand (op, mode);
1338 if (reload_in_progress)
1339 return strict_memory_address_p (mode, XEXP (op, 0));
1341 return memory_address_p (mode, XEXP (op, 0));
1344 /* Return 1 if the operand is an offsettable memory operand. */
1347 offsettable_mem_operand (op, mode)
1349 enum machine_mode mode;
1351 return ((GET_CODE (op) == MEM)
1352 && offsettable_address_p (reload_completed || reload_in_progress,
1353 mode, XEXP (op, 0)));
1356 /* Return 1 if the operand is either an easy FP constant (see above) or
1360 mem_or_easy_const_operand (op, mode)
1362 enum machine_mode mode;
1364 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1367 /* Return 1 if the operand is either a non-special register or an item
1368 that can be used as the operand of a `mode' add insn. */
1371 add_operand (op, mode)
1373 enum machine_mode mode;
1375 if (GET_CODE (op) == CONST_INT)
1376 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1377 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1379 return gpc_reg_operand (op, mode);
1382 /* Return 1 if OP is a constant but not a valid add_operand. */
1385 non_add_cint_operand (op, mode)
1387 enum machine_mode mode ATTRIBUTE_UNUSED;
1389 return (GET_CODE (op) == CONST_INT
1390 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1391 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1394 /* Return 1 if the operand is a non-special register or a constant that
1395 can be used as the operand of an OR or XOR insn on the RS/6000. */
1398 logical_operand (op, mode)
1400 enum machine_mode mode;
1402 HOST_WIDE_INT opl, oph;
1404 if (gpc_reg_operand (op, mode))
1407 if (GET_CODE (op) == CONST_INT)
1409 opl = INTVAL (op) & GET_MODE_MASK (mode);
1411 #if HOST_BITS_PER_WIDE_INT <= 32
1412 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1416 else if (GET_CODE (op) == CONST_DOUBLE)
1418 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1421 opl = CONST_DOUBLE_LOW (op);
1422 oph = CONST_DOUBLE_HIGH (op);
1429 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1430 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1433 /* Return 1 if C is a constant that is not a logical operand (as
1434 above), but could be split into one. */
1437 non_logical_cint_operand (op, mode)
1439 enum machine_mode mode;
1441 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1442 && ! logical_operand (op, mode)
1443 && reg_or_logical_cint_operand (op, mode));
1446 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1447 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1448 Reject all ones and all zeros, since these should have been optimized
1449 away and confuse the making of MB and ME. */
1452 mask_operand (op, mode)
1454 enum machine_mode mode ATTRIBUTE_UNUSED;
1456 HOST_WIDE_INT c, lsb;
1458 if (GET_CODE (op) != CONST_INT)
1463 /* Fail in 64-bit mode if the mask wraps around because the upper
1464 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
1465 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1468 /* We don't change the number of transitions by inverting,
1469 so make sure we start with the LS bit zero. */
1473 /* Reject all zeros or all ones. */
1477 /* Find the first transition. */
1480 /* Invert to look for a second transition. */
1483 /* Erase first transition. */
1486 /* Find the second transition (if any). */
1489 /* Match if all the bits above are 1's (or c is zero). */
1493 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1494 It is if there are no more than one 1->0 or 0->1 transitions.
1495 Reject all ones and all zeros, since these should have been optimized
1496 away and confuse the making of MB and ME. */
1499 mask64_operand (op, mode)
1501 enum machine_mode mode;
1503 if (GET_CODE (op) == CONST_INT)
1505 HOST_WIDE_INT c, lsb;
1507 /* We don't change the number of transitions by inverting,
1508 so make sure we start with the LS bit zero. */
1513 /* Reject all zeros or all ones. */
1517 /* Find the transition, and check that all bits above are 1's. */
1521 else if (GET_CODE (op) == CONST_DOUBLE
1522 && (mode == VOIDmode || mode == DImode))
1524 HOST_WIDE_INT low, high, lsb;
1526 if (HOST_BITS_PER_WIDE_INT < 64)
1527 high = CONST_DOUBLE_HIGH (op);
1529 low = CONST_DOUBLE_LOW (op);
1532 if (HOST_BITS_PER_WIDE_INT < 64)
1539 if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)
1543 return high == -lsb;
1547 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
1553 /* Return 1 if the operand is either a non-special register or a constant
1554 that can be used as the operand of a PowerPC64 logical AND insn. */
1557 and64_operand (op, mode)
1559 enum machine_mode mode;
1561 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1562 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
1564 return (logical_operand (op, mode) || mask64_operand (op, mode));
1567 /* Return 1 if the operand is either a non-special register or a
1568 constant that can be used as the operand of an RS/6000 logical AND insn. */
1571 and_operand (op, mode)
1573 enum machine_mode mode;
1575 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1576 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
1578 return (logical_operand (op, mode) || mask_operand (op, mode));
1581 /* Return 1 if the operand is a general register or memory operand. */
1584 reg_or_mem_operand (op, mode)
1586 enum machine_mode mode;
1588 return (gpc_reg_operand (op, mode)
1589 || memory_operand (op, mode)
1590 || volatile_mem_operand (op, mode));
1593 /* Return 1 if the operand is a general register or memory operand without
1594 pre_inc or pre_dec which produces invalid form of PowerPC lwa
1598 lwa_operand (op, mode)
1600 enum machine_mode mode;
1604 if (reload_completed && GET_CODE (inner) == SUBREG)
1605 inner = SUBREG_REG (inner);
1607 return gpc_reg_operand (inner, mode)
1608 || (memory_operand (inner, mode)
1609 && GET_CODE (XEXP (inner, 0)) != PRE_INC
1610 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
1611 && (GET_CODE (XEXP (inner, 0)) != PLUS
1612 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
1613 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
1616 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
1619 symbol_ref_operand (op, mode)
1621 enum machine_mode mode;
1623 if (mode != VOIDmode && GET_MODE (op) != mode)
1626 return (GET_CODE (op) == SYMBOL_REF);
1629 /* Return 1 if the operand, used inside a MEM, is a valid first argument
1630 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
1633 call_operand (op, mode)
1635 enum machine_mode mode;
1637 if (mode != VOIDmode && GET_MODE (op) != mode)
1640 return (GET_CODE (op) == SYMBOL_REF
1641 || (GET_CODE (op) == REG
1642 && (REGNO (op) == LINK_REGISTER_REGNUM
1643 || REGNO (op) == COUNT_REGISTER_REGNUM
1644 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1647 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
1648 this file and the function is not weakly defined. */
1651 current_file_function_operand (op, mode)
1653 enum machine_mode mode ATTRIBUTE_UNUSED;
1655 return (GET_CODE (op) == SYMBOL_REF
1656 && (SYMBOL_REF_FLAG (op)
1657 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1658 && ! DECL_WEAK (current_function_decl))));
1661 /* Return 1 if this operand is a valid input for a move insn. */
1664 input_operand (op, mode)
1666 enum machine_mode mode;
1668 /* Memory is always valid. */
1669 if (memory_operand (op, mode))
1672 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1673 if (GET_CODE (op) == CONSTANT_P_RTX)
1676 /* For floating-point, easy constants are valid. */
1677 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1679 && easy_fp_constant (op, mode))
1682 /* Allow any integer constant. */
1683 if (GET_MODE_CLASS (mode) == MODE_INT
1684 && (GET_CODE (op) == CONST_INT
1685 || GET_CODE (op) == CONST_DOUBLE))
1688 /* For floating-point or multi-word mode, the only remaining valid type
1690 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1691 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1692 return register_operand (op, mode);
1694 /* The only cases left are integral modes one word or smaller (we
1695 do not get called for MODE_CC values). These can be in any
1697 if (register_operand (op, mode))
1700 /* A SYMBOL_REF referring to the TOC is valid. */
1701 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
1704 /* A constant pool expression (relative to the TOC) is valid */
1705 if (TOC_RELATIVE_EXPR_P (op))
1708 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1710 if (DEFAULT_ABI == ABI_V4
1711 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1712 && small_data_operand (op, Pmode))
1718 /* Return 1 for an operand in small memory on V.4/eabi. */
1721 small_data_operand (op, mode)
1722 rtx op ATTRIBUTE_UNUSED;
1723 enum machine_mode mode ATTRIBUTE_UNUSED;
1728 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
1731 if (DEFAULT_ABI != ABI_V4)
1734 if (GET_CODE (op) == SYMBOL_REF)
1737 else if (GET_CODE (op) != CONST
1738 || GET_CODE (XEXP (op, 0)) != PLUS
1739 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
1740 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
1745 rtx sum = XEXP (op, 0);
1746 HOST_WIDE_INT summand;
1748 /* We have to be careful here, because it is the referenced address
1749 that must be 32k from _SDA_BASE_, not just the symbol. */
1750 summand = INTVAL (XEXP (sum, 1));
1751 if (summand < 0 || summand > g_switch_value)
1754 sym_ref = XEXP (sum, 0);
1757 if (*XSTR (sym_ref, 0) != '@')
1768 constant_pool_expr_1 (op, have_sym, have_toc)
1773 switch (GET_CODE(op))
1776 if (CONSTANT_POOL_ADDRESS_P (op))
1778 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
1786 else if (! strcmp (XSTR (op, 0), toc_label_name))
1795 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
1796 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
1798 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
1807 constant_pool_expr_p (op)
1812 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
1816 toc_relative_expr_p (op)
1821 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
1824 /* Try machine-dependent ways of modifying an illegitimate address
1825 to be legitimate. If we find one, return the new, valid address.
1826 This is used from only one place: `memory_address' in explow.c.
1828 OLDX is the address as it was before break_out_memory_refs was
1829 called. In some cases it is useful to look at this to decide what
1832 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
1834 It is always safe for this function to do nothing. It exists to
1835 recognize opportunities to optimize the output.
1837 On RS/6000, first check for the sum of a register with a constant
1838 integer that is out of range. If so, generate code to add the
1839 constant with the low-order 16 bits masked to the register and force
1840 this result into another register (this can be done with `cau').
1841 Then generate an address of REG+(CONST&0xffff), allowing for the
1842 possibility of bit 16 being a one.
1844 Then check for the sum of a register and something not constant, try to
1845 load the other things into a register and return the sum. */
1847 rs6000_legitimize_address (x, oldx, mode)
1849 rtx oldx ATTRIBUTE_UNUSED;
1850 enum machine_mode mode;
1852 if (GET_CODE (x) == PLUS
1853 && GET_CODE (XEXP (x, 0)) == REG
1854 && GET_CODE (XEXP (x, 1)) == CONST_INT
1855 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
1857 HOST_WIDE_INT high_int, low_int;
1859 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
1860 high_int = INTVAL (XEXP (x, 1)) - low_int;
1861 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
1862 GEN_INT (high_int)), 0);
1863 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
1865 else if (GET_CODE (x) == PLUS
1866 && GET_CODE (XEXP (x, 0)) == REG
1867 && GET_CODE (XEXP (x, 1)) != CONST_INT
1868 && GET_MODE_NUNITS (mode) == 1
1869 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
1870 && (TARGET_POWERPC64 || mode != DImode)
1873 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
1874 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
1876 else if (ALTIVEC_VECTOR_MODE (mode))
1880 /* Make sure both operands are registers. */
1881 if (GET_CODE (x) == PLUS)
1882 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
1883 force_reg (Pmode, XEXP (x, 1)));
1885 reg = force_reg (Pmode, x);
1888 else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic
1889 && GET_CODE (x) != CONST_INT
1890 && GET_CODE (x) != CONST_DOUBLE
1892 && GET_MODE_NUNITS (mode) == 1
1893 && (GET_MODE_BITSIZE (mode) <= 32
1894 || (TARGET_HARD_FLOAT && mode == DFmode)))
1896 rtx reg = gen_reg_rtx (Pmode);
1897 emit_insn (gen_elf_high (reg, (x)));
1898 return gen_rtx_LO_SUM (Pmode, reg, (x));
1900 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
1902 && GET_CODE (x) != CONST_INT
1903 && GET_CODE (x) != CONST_DOUBLE
1905 && (TARGET_HARD_FLOAT || mode != DFmode)
1909 rtx reg = gen_reg_rtx (Pmode);
1910 emit_insn (gen_macho_high (reg, (x)));
1911 return gen_rtx_LO_SUM (Pmode, reg, (x));
1914 && CONSTANT_POOL_EXPR_P (x)
1915 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
1917 return create_TOC_reference (x);
1923 /* The convention appears to be to define this wherever it is used.
1924 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
1925 is now used here. */
1926 #ifndef REG_MODE_OK_FOR_BASE_P
1927 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
1930 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
1931 replace the input X, or the original X if no replacement is called for.
1932 The output parameter *WIN is 1 if the calling macro should goto WIN,
1935 For RS/6000, we wish to handle large displacements off a base
1936 register by splitting the addend across an addiu/addis and the mem insn.
1937 This cuts number of extra insns needed from 3 to 1.
1939 On Darwin, we use this to generate code for floating point constants.
1940 A movsf_low is generated so we wind up with 2 instructions rather than 3.
1941 The Darwin code is inside #if TARGET_MACHO because only then is
1942 machopic_function_base_name() defined. */
1944 rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
1946 enum machine_mode mode;
1949 int ind_levels ATTRIBUTE_UNUSED;
1952 /* We must recognize output that we have already generated ourselves. */
1953 if (GET_CODE (x) == PLUS
1954 && GET_CODE (XEXP (x, 0)) == PLUS
1955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1956 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1957 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1959 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1960 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1961 opnum, (enum reload_type)type);
1967 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
1968 && GET_CODE (x) == LO_SUM
1969 && GET_CODE (XEXP (x, 0)) == PLUS
1970 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
1971 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
1972 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
1973 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
1974 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
1975 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
1976 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
1978 /* Result of previous invocation of this function on Darwin
1979 floating point constant. */
1980 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1981 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
1982 opnum, (enum reload_type)type);
1987 if (GET_CODE (x) == PLUS
1988 && GET_CODE (XEXP (x, 0)) == REG
1989 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
1990 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
1991 && GET_CODE (XEXP (x, 1)) == CONST_INT
1992 && !ALTIVEC_VECTOR_MODE (mode))
1994 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
1995 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1997 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1999 /* Check for 32-bit overflow. */
2000 if (high + low != val)
2006 /* Reload the high part into a base reg; leave the low part
2007 in the mem directly. */
2009 x = gen_rtx_PLUS (GET_MODE (x),
2010 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2014 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2015 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2016 opnum, (enum reload_type)type);
2021 if (GET_CODE (x) == SYMBOL_REF
2022 && DEFAULT_ABI == ABI_DARWIN
2023 && !ALTIVEC_VECTOR_MODE (mode)
2026 /* Darwin load of floating point constant. */
2027 rtx offset = gen_rtx (CONST, Pmode,
2028 gen_rtx (MINUS, Pmode, x,
2029 gen_rtx (SYMBOL_REF, Pmode,
2030 machopic_function_base_name ())));
2031 x = gen_rtx (LO_SUM, GET_MODE (x),
2032 gen_rtx (PLUS, Pmode, pic_offset_table_rtx,
2033 gen_rtx (HIGH, Pmode, offset)), offset);
2034 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2035 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2036 opnum, (enum reload_type)type);
2042 && CONSTANT_POOL_EXPR_P (x)
2043 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
2045 (x) = create_TOC_reference (x);
2053 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2054 that is a valid memory address for an instruction.
2055 The MODE argument is the machine mode for the MEM expression
2056 that wants to use this address.
2058 On the RS/6000, there are four valid address: a SYMBOL_REF that
2059 refers to a constant pool entry of an address (or the sum of it
2060 plus a constant), a short (16-bit signed) constant plus a register,
2061 the sum of two registers, or a register indirect, possibly with an
2062 auto-increment. For DFmode and DImode with an constant plus register,
2063 we must ensure that both words are addressable or PowerPC64 with offset
2066 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2067 32-bit DImode, TImode), indexed addressing cannot be used because
2068 adjacent memory cells are accessed by adding word-sized offsets
2069 during assembly output. */
2071 rs6000_legitimate_address (mode, x, reg_ok_strict)
2072 enum machine_mode mode;
2076 if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict))
2078 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
2079 && !ALTIVEC_VECTOR_MODE (mode)
2081 && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict))
2083 if (LEGITIMATE_SMALL_DATA_P (mode, x))
2085 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
2087 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
2089 && GET_CODE (x) == PLUS
2090 && GET_CODE (XEXP (x, 0)) == REG
2091 && XEXP (x, 0) == virtual_stack_vars_rtx
2092 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2094 if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict))
2097 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
2098 && (TARGET_POWERPC64 || mode != DImode)
2099 && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict))
2101 if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict))
2106 /* Try to output insns to set TARGET equal to the constant C if it can
2107 be done in less than N insns. Do all computations in MODE.
2108 Returns the place where the output has been placed if it can be
2109 done and the insns have been emitted. If it would take more than N
2110 insns, zero is returned and no insns and emitted. */
2113 rs6000_emit_set_const (dest, mode, source, n)
2115 enum machine_mode mode;
2116 int n ATTRIBUTE_UNUSED;
2118 HOST_WIDE_INT c0, c1;
2120 if (mode == QImode || mode == HImode || mode == SImode)
2123 dest = gen_reg_rtx (mode);
2124 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
2128 if (GET_CODE (source) == CONST_INT)
2130 c0 = INTVAL (source);
2133 else if (GET_CODE (source) == CONST_DOUBLE)
2135 #if HOST_BITS_PER_WIDE_INT >= 64
2136 c0 = CONST_DOUBLE_LOW (source);
2139 c0 = CONST_DOUBLE_LOW (source);
2140 c1 = CONST_DOUBLE_HIGH (source);
2146 return rs6000_emit_set_long_const (dest, c0, c1);
2149 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
2150 fall back to a straight forward decomposition. We do this to avoid
2151 exponential run times encountered when looking for longer sequences
2152 with rs6000_emit_set_const. */
2154 rs6000_emit_set_long_const (dest, c1, c2)
2156 HOST_WIDE_INT c1, c2;
2158 if (!TARGET_POWERPC64)
2160 rtx operand1, operand2;
2162 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
2164 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
2166 emit_move_insn (operand1, GEN_INT (c1));
2167 emit_move_insn (operand2, GEN_INT (c2));
2171 HOST_WIDE_INT ud1, ud2, ud3, ud4;
2174 ud2 = (c1 & 0xffff0000) >> 16;
2175 #if HOST_BITS_PER_WIDE_INT >= 64
2179 ud4 = (c2 & 0xffff0000) >> 16;
2181 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
2182 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2185 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
2187 emit_move_insn (dest, GEN_INT (ud1));
2190 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
2191 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
2194 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
2197 emit_move_insn (dest, GEN_INT (ud2 << 16));
2199 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
2201 else if ((ud4 == 0xffff && (ud3 & 0x8000))
2202 || (ud4 == 0 && ! (ud3 & 0x8000)))
2205 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
2208 emit_move_insn (dest, GEN_INT (ud3 << 16));
2211 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
2212 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
2214 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
2219 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
2222 emit_move_insn (dest, GEN_INT (ud4 << 16));
2225 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2227 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
2229 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
2230 GEN_INT (ud2 << 16)));
2232 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
2238 /* Emit a move from SOURCE to DEST in mode MODE. */
2240 rs6000_emit_move (dest, source, mode)
2243 enum machine_mode mode;
2247 operands[1] = source;
2249 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
2250 if (GET_CODE (operands[1]) == CONST_DOUBLE
2251 && ! FLOAT_MODE_P (mode)
2252 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2254 /* FIXME. This should never happen. */
2255 /* Since it seems that it does, do the safe thing and convert
2257 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
2259 if (GET_CODE (operands[1]) == CONST_DOUBLE
2260 && ! FLOAT_MODE_P (mode)
2261 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
2262 && CONST_DOUBLE_LOW (operands[1]) >= 0)
2263 || (CONST_DOUBLE_HIGH (operands[1]) == -1
2264 && CONST_DOUBLE_LOW (operands[1]) < 0)))
2267 /* Check if GCC is setting up a block move that will end up using FP
2268 registers as temporaries. We must make sure this is acceptable. */
2269 if (GET_CODE (operands[0]) == MEM
2270 && GET_CODE (operands[1]) == MEM
2272 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
2273 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
2274 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
2275 ? 32 : MEM_ALIGN (operands[0])))
2276 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
2278 : MEM_ALIGN (operands[1]))))
2279 && ! MEM_VOLATILE_P (operands [0])
2280 && ! MEM_VOLATILE_P (operands [1]))
2282 emit_move_insn (adjust_address (operands[0], SImode, 0),
2283 adjust_address (operands[1], SImode, 0));
2284 emit_move_insn (adjust_address (operands[0], SImode, 4),
2285 adjust_address (operands[1], SImode, 4));
2289 if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
2290 operands[1] = force_reg (mode, operands[1]);
2292 if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT
2293 && GET_CODE (operands[0]) == MEM)
2297 if (reload_in_progress || reload_completed)
2298 regnum = true_regnum (operands[1]);
2299 else if (GET_CODE (operands[1]) == REG)
2300 regnum = REGNO (operands[1]);
2304 /* If operands[1] is a register, on POWER it may have
2305 double-precision data in it, so truncate it to single
2307 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
2310 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
2311 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
2312 operands[1] = newreg;
2316 /* Handle the case where reload calls us with an invalid address;
2317 and the case of CONSTANT_P_RTX. */
2318 if (!ALTIVEC_VECTOR_MODE (mode)
2319 && (! general_operand (operands[1], mode)
2320 || ! nonimmediate_operand (operands[0], mode)
2321 || GET_CODE (operands[1]) == CONSTANT_P_RTX))
2323 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2327 /* FIXME: In the long term, this switch statement should go away
2328 and be replaced by a sequence of tests based on things like
2334 if (CONSTANT_P (operands[1])
2335 && GET_CODE (operands[1]) != CONST_INT)
2336 operands[1] = force_const_mem (mode, operands[1]);
2342 if (CONSTANT_P (operands[1])
2343 && ! easy_fp_constant (operands[1], mode))
2344 operands[1] = force_const_mem (mode, operands[1]);
2351 if (CONSTANT_P (operands[1])
2352 && !easy_vector_constant (operands[1]))
2353 operands[1] = force_const_mem (mode, operands[1]);
2358 /* Use default pattern for address of ELF small data */
2361 && DEFAULT_ABI == ABI_V4
2362 && (GET_CODE (operands[1]) == SYMBOL_REF
2363 || GET_CODE (operands[1]) == CONST)
2364 && small_data_operand (operands[1], mode))
2366 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2370 if (DEFAULT_ABI == ABI_V4
2371 && mode == Pmode && mode == SImode
2372 && flag_pic == 1 && got_operand (operands[1], mode))
2374 emit_insn (gen_movsi_got (operands[0], operands[1]));
2378 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
2379 && TARGET_NO_TOC && ! flag_pic
2381 && CONSTANT_P (operands[1])
2382 && GET_CODE (operands[1]) != HIGH
2383 && GET_CODE (operands[1]) != CONST_INT)
2385 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
2387 /* If this is a function address on -mcall-aixdesc,
2388 convert it to the address of the descriptor. */
2389 if (DEFAULT_ABI == ABI_AIX
2390 && GET_CODE (operands[1]) == SYMBOL_REF
2391 && XSTR (operands[1], 0)[0] == '.')
2393 const char *name = XSTR (operands[1], 0);
2395 while (*name == '.')
2397 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
2398 CONSTANT_POOL_ADDRESS_P (new_ref)
2399 = CONSTANT_POOL_ADDRESS_P (operands[1]);
2400 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
2401 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
2402 operands[1] = new_ref;
2405 if (DEFAULT_ABI == ABI_DARWIN)
2407 emit_insn (gen_macho_high (target, operands[1]));
2408 emit_insn (gen_macho_low (operands[0], target, operands[1]));
2412 emit_insn (gen_elf_high (target, operands[1]));
2413 emit_insn (gen_elf_low (operands[0], target, operands[1]));
2417 /* If this is a SYMBOL_REF that refers to a constant pool entry,
2418 and we have put it in the TOC, we just need to make a TOC-relative
2421 && GET_CODE (operands[1]) == SYMBOL_REF
2422 && CONSTANT_POOL_EXPR_P (operands[1])
2423 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
2424 get_pool_mode (operands[1])))
2426 operands[1] = create_TOC_reference (operands[1]);
2428 else if (mode == Pmode
2429 && CONSTANT_P (operands[1])
2430 && ((GET_CODE (operands[1]) != CONST_INT
2431 && ! easy_fp_constant (operands[1], mode))
2432 || (GET_CODE (operands[1]) == CONST_INT
2433 && num_insns_constant (operands[1], mode) > 2)
2434 || (GET_CODE (operands[0]) == REG
2435 && FP_REGNO_P (REGNO (operands[0]))))
2436 && GET_CODE (operands[1]) != HIGH
2437 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])
2438 && ! TOC_RELATIVE_EXPR_P (operands[1]))
2440 /* Emit a USE operation so that the constant isn't deleted if
2441 expensive optimizations are turned on because nobody
2442 references it. This should only be done for operands that
2443 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
2444 This should not be done for operands that contain LABEL_REFs.
2445 For now, we just handle the obvious case. */
2446 if (GET_CODE (operands[1]) != LABEL_REF)
2447 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
2450 /* Darwin uses a special PIC legitimizer. */
2451 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
2454 rs6000_machopic_legitimize_pic_address (operands[1], mode,
2456 if (operands[0] != operands[1])
2457 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2462 /* If we are to limit the number of things we put in the TOC and
2463 this is a symbol plus a constant we can add in one insn,
2464 just put the symbol in the TOC and add the constant. Don't do
2465 this if reload is in progress. */
2466 if (GET_CODE (operands[1]) == CONST
2467 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
2468 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2469 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
2470 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
2471 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
2472 && ! side_effects_p (operands[0]))
2475 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
2476 rtx other = XEXP (XEXP (operands[1], 0), 1);
2478 sym = force_reg (mode, sym);
2480 emit_insn (gen_addsi3 (operands[0], sym, other));
2482 emit_insn (gen_adddi3 (operands[0], sym, other));
2486 operands[1] = force_const_mem (mode, operands[1]);
2489 && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0))
2490 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
2491 get_pool_constant (XEXP (operands[1], 0)),
2492 get_pool_mode (XEXP (operands[1], 0))))
2495 = gen_rtx_MEM (mode,
2496 create_TOC_reference (XEXP (operands[1], 0)));
2497 set_mem_alias_set (operands[1], get_TOC_alias_set ());
2498 RTX_UNCHANGING_P (operands[1]) = 1;
2504 if (GET_CODE (operands[0]) == MEM
2505 && GET_CODE (XEXP (operands[0], 0)) != REG
2506 && ! reload_in_progress)
2508 = replace_equiv_address (operands[0],
2509 copy_addr_to_reg (XEXP (operands[0], 0)));
2511 if (GET_CODE (operands[1]) == MEM
2512 && GET_CODE (XEXP (operands[1], 0)) != REG
2513 && ! reload_in_progress)
2515 = replace_equiv_address (operands[1],
2516 copy_addr_to_reg (XEXP (operands[1], 0)));
2523 /* Above, we may have called force_const_mem which may have returned
2524 an invalid address. If we can, fix this up; otherwise, reload will
2525 have to deal with it. */
2526 if (GET_CODE (operands[1]) == MEM
2527 && ! memory_address_p (mode, XEXP (operands[1], 0))
2528 && ! reload_in_progress)
2529 operands[1] = adjust_address (operands[1], mode, 0);
2531 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2535 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2536 for a call to a function whose data type is FNTYPE.
2537 For a library call, FNTYPE is 0.
2539 For incoming args we set the number of arguments in the prototype large
2540 so we never return a PARALLEL. */
2543 init_cumulative_args (cum, fntype, libname, incoming)
2544 CUMULATIVE_ARGS *cum;
2546 rtx libname ATTRIBUTE_UNUSED;
2549 static CUMULATIVE_ARGS zero_cumulative;
2551 *cum = zero_cumulative;
2553 cum->fregno = FP_ARG_MIN_REG;
2554 cum->vregno = ALTIVEC_ARG_MIN_REG;
2555 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
2556 cum->call_cookie = CALL_NORMAL;
2557 cum->sysv_gregno = GP_ARG_MIN_REG;
2560 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
2562 else if (cum->prototype)
2563 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
2564 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
2565 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
2568 cum->nargs_prototype = 0;
2570 cum->orig_nargs = cum->nargs_prototype;
2572 /* Check for a longcall attribute. */
2574 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
2575 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
2576 cum->call_cookie = CALL_LONG;
2578 if (TARGET_DEBUG_ARG)
2580 fprintf (stderr, "\ninit_cumulative_args:");
2583 tree ret_type = TREE_TYPE (fntype);
2584 fprintf (stderr, " ret code = %s,",
2585 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2588 if (cum->call_cookie & CALL_LONG)
2589 fprintf (stderr, " longcall,");
2591 fprintf (stderr, " proto = %d, nargs = %d\n",
2592 cum->prototype, cum->nargs_prototype);
2596 /* If defined, a C expression which determines whether, and in which
2597 direction, to pad out an argument with extra space. The value
2598 should be of type `enum direction': either `upward' to pad above
2599 the argument, `downward' to pad below, or `none' to inhibit
2602 For the AIX ABI structs are always stored left shifted in their
2606 function_arg_padding (mode, type)
2607 enum machine_mode mode;
2610 if (type != 0 && AGGREGATE_TYPE_P (type))
2613 /* This is the default definition. */
2614 return (! BYTES_BIG_ENDIAN
2617 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2618 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
2619 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
2620 ? downward : upward));
2623 /* If defined, a C expression that gives the alignment boundary, in bits,
2624 of an argument with the specified mode and type. If it is not defined,
2625 PARM_BOUNDARY is used for all arguments.
2627 V.4 wants long longs to be double word aligned. */
2630 function_arg_boundary (mode, type)
2631 enum machine_mode mode;
2632 tree type ATTRIBUTE_UNUSED;
2634 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
2636 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
2639 return PARM_BOUNDARY;
2642 /* Update the data in CUM to advance over an argument
2643 of mode MODE and data type TYPE.
2644 (TYPE is null for libcalls where that information may not be available.) */
2647 function_arg_advance (cum, mode, type, named)
2648 CUMULATIVE_ARGS *cum;
2649 enum machine_mode mode;
2653 cum->nargs_prototype--;
2655 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
2657 if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0)
2660 cum->words += RS6000_ARG_SIZE (mode, type);
2662 else if (DEFAULT_ABI == ABI_V4)
2664 if (TARGET_HARD_FLOAT
2665 && (mode == SFmode || mode == DFmode))
2667 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2672 cum->words += cum->words & 1;
2673 cum->words += RS6000_ARG_SIZE (mode, type);
2679 int gregno = cum->sysv_gregno;
2681 /* Aggregates and IEEE quad get passed by reference. */
2682 if ((type && AGGREGATE_TYPE_P (type))
2686 n_words = RS6000_ARG_SIZE (mode, type);
2688 /* Long long is put in odd registers. */
2689 if (n_words == 2 && (gregno & 1) == 0)
2692 /* Long long is not split between registers and stack. */
2693 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
2695 /* Long long is aligned on the stack. */
2697 cum->words += cum->words & 1;
2698 cum->words += n_words;
2701 /* Note: continuing to accumulate gregno past when we've started
2702 spilling to the stack indicates the fact that we've started
2703 spilling to the stack to expand_builtin_saveregs. */
2704 cum->sysv_gregno = gregno + n_words;
2707 if (TARGET_DEBUG_ARG)
2709 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2710 cum->words, cum->fregno);
2711 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
2712 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
2713 fprintf (stderr, "mode = %4s, named = %d\n",
2714 GET_MODE_NAME (mode), named);
2719 int align = (TARGET_32BIT && (cum->words & 1) != 0
2720 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2722 cum->words += align + RS6000_ARG_SIZE (mode, type);
2724 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
2727 if (TARGET_DEBUG_ARG)
2729 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2730 cum->words, cum->fregno);
2731 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
2732 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
2733 fprintf (stderr, "named = %d, align = %d\n", named, align);
2738 /* Determine where to put an argument to a function.
2739 Value is zero to push the argument on the stack,
2740 or a hard register in which to store the argument.
2742 MODE is the argument's machine mode.
2743 TYPE is the data type of the argument (as a tree).
2744 This is null for libcalls where that information may
2746 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2747 the preceding args and about the function being called.
2748 NAMED is nonzero if this argument is a named parameter
2749 (otherwise it is an extra parameter matching an ellipsis).
2751 On RS/6000 the first eight words of non-FP are normally in registers
2752 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
2753 Under V.4, the first 8 FP args are in registers.
2755 If this is floating-point and no prototype is specified, we use
2756 both an FP and integer register (or possibly FP reg and stack). Library
2757 functions (when TYPE is zero) always have the proper types for args,
2758 so we can pass the FP value just in one register. emit_library_function
2759 doesn't support PARALLEL anyway. */
2762 function_arg (cum, mode, type, named)
2763 CUMULATIVE_ARGS *cum;
2764 enum machine_mode mode;
2768 enum rs6000_abi abi = DEFAULT_ABI;
2770 /* Return a marker to indicate whether CR1 needs to set or clear the
2771 bit that V.4 uses to say fp args were passed in registers.
2772 Assume that we don't need the marker for software floating point,
2773 or compiler generated library calls. */
2774 if (mode == VOIDmode)
2777 && TARGET_HARD_FLOAT
2778 && cum->nargs_prototype < 0
2779 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
2781 return GEN_INT (cum->call_cookie
2782 | ((cum->fregno == FP_ARG_MIN_REG)
2783 ? CALL_V4_SET_FP_ARGS
2784 : CALL_V4_CLEAR_FP_ARGS));
2787 return GEN_INT (cum->call_cookie);
2790 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
2792 if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG)
2793 return gen_rtx_REG (mode, cum->vregno);
2797 else if (abi == ABI_V4)
2799 if (TARGET_HARD_FLOAT
2800 && (mode == SFmode || mode == DFmode))
2802 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2803 return gen_rtx_REG (mode, cum->fregno);
2810 int gregno = cum->sysv_gregno;
2812 /* Aggregates and IEEE quad get passed by reference. */
2813 if ((type && AGGREGATE_TYPE_P (type))
2817 n_words = RS6000_ARG_SIZE (mode, type);
2819 /* Long long is put in odd registers. */
2820 if (n_words == 2 && (gregno & 1) == 0)
2823 /* Long long is not split between registers and stack. */
2824 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
2825 return gen_rtx_REG (mode, gregno);
2832 int align = (TARGET_32BIT && (cum->words & 1) != 0
2833 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2834 int align_words = cum->words + align;
2836 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2839 if (USE_FP_FOR_ARG_P (*cum, mode, type))
2842 || ((cum->nargs_prototype > 0)
2843 /* IBM AIX extended its linkage convention definition always
2844 to require FP args after register save area hole on the
2846 && (DEFAULT_ABI != ABI_AIX
2848 || (align_words < GP_ARG_NUM_REG))))
2849 return gen_rtx_REG (mode, cum->fregno);
2851 return gen_rtx_PARALLEL (mode,
2853 gen_rtx_EXPR_LIST (VOIDmode,
2854 ((align_words >= GP_ARG_NUM_REG)
2857 + RS6000_ARG_SIZE (mode, type)
2859 /* If this is partially on the stack, then
2860 we only include the portion actually
2861 in registers here. */
2862 ? gen_rtx_REG (SImode,
2863 GP_ARG_MIN_REG + align_words)
2864 : gen_rtx_REG (mode,
2865 GP_ARG_MIN_REG + align_words))),
2867 gen_rtx_EXPR_LIST (VOIDmode,
2868 gen_rtx_REG (mode, cum->fregno),
2871 else if (align_words < GP_ARG_NUM_REG)
2872 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
2878 /* For an arg passed partly in registers and partly in memory,
2879 this is the number of registers used.
2880 For args passed entirely in registers or entirely in memory, zero. */
2883 function_arg_partial_nregs (cum, mode, type, named)
2884 CUMULATIVE_ARGS *cum;
2885 enum machine_mode mode;
2887 int named ATTRIBUTE_UNUSED;
2889 if (DEFAULT_ABI == ABI_V4)
2892 if (USE_FP_FOR_ARG_P (*cum, mode, type)
2893 || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type))
2895 if (cum->nargs_prototype >= 0)
2899 if (cum->words < GP_ARG_NUM_REG
2900 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
2902 int ret = GP_ARG_NUM_REG - cum->words;
2903 if (ret && TARGET_DEBUG_ARG)
2904 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2912 /* A C expression that indicates when an argument must be passed by
2913 reference. If nonzero for an argument, a copy of that argument is
2914 made in memory and a pointer to the argument is passed instead of
2915 the argument itself. The pointer is passed in whatever way is
2916 appropriate for passing a pointer to that type.
2918 Under V.4, structures and unions are passed by reference. */
2921 function_arg_pass_by_reference (cum, mode, type, named)
2922 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2923 enum machine_mode mode ATTRIBUTE_UNUSED;
2925 int named ATTRIBUTE_UNUSED;
2927 if (DEFAULT_ABI == ABI_V4
2928 && ((type && AGGREGATE_TYPE_P (type))
2931 if (TARGET_DEBUG_ARG)
2932 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
2940 /* Perform any needed actions needed for a function that is receiving a
2941 variable number of arguments.
2945 MODE and TYPE are the mode and type of the current parameter.
2947 PRETEND_SIZE is a variable that should be set to the amount of stack
2948 that must be pushed by the prolog to pretend that our caller pushed
2951 Normally, this macro will push all remaining incoming registers on the
2952 stack and set PRETEND_SIZE to the length of the registers pushed. */
2955 setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2956 CUMULATIVE_ARGS *cum;
2957 enum machine_mode mode;
2963 CUMULATIVE_ARGS next_cum;
2964 int reg_size = TARGET_32BIT ? 4 : 8;
2965 rtx save_area = NULL_RTX, mem;
2966 int first_reg_offset, set;
2970 fntype = TREE_TYPE (current_function_decl);
2971 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
2972 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2973 != void_type_node));
2975 /* For varargs, we do not want to skip the dummy va_dcl argument.
2976 For stdargs, we do want to skip the last named argument. */
2979 function_arg_advance (&next_cum, mode, type, 1);
2981 if (DEFAULT_ABI == ABI_V4)
2983 /* Indicate to allocate space on the stack for varargs save area. */
2984 cfun->machine->sysv_varargs_p = 1;
2986 save_area = plus_constant (virtual_stack_vars_rtx,
2987 - RS6000_VARARGS_SIZE);
2989 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
2993 first_reg_offset = next_cum.words;
2994 save_area = virtual_incoming_args_rtx;
2995 cfun->machine->sysv_varargs_p = 0;
2997 if (MUST_PASS_IN_STACK (mode, type))
2998 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
3001 set = get_varargs_alias_set ();
3002 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
3004 mem = gen_rtx_MEM (BLKmode,
3005 plus_constant (save_area,
3006 first_reg_offset * reg_size)),
3007 set_mem_alias_set (mem, set);
3008 set_mem_align (mem, BITS_PER_WORD);
3011 (GP_ARG_MIN_REG + first_reg_offset, mem,
3012 GP_ARG_NUM_REG - first_reg_offset,
3013 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
3015 /* ??? Does ABI_V4 need this at all? */
3016 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
3019 /* Save FP registers if needed. */
3020 if (DEFAULT_ABI == ABI_V4
3021 && TARGET_HARD_FLOAT && ! no_rtl
3022 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
3024 int fregno = next_cum.fregno;
3025 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
3026 rtx lab = gen_label_rtx ();
3027 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
3029 emit_jump_insn (gen_rtx_SET (VOIDmode,
3031 gen_rtx_IF_THEN_ELSE (VOIDmode,
3032 gen_rtx_NE (VOIDmode, cr1,
3034 gen_rtx_LABEL_REF (VOIDmode, lab),
3037 while (fregno <= FP_ARG_V4_MAX_REG)
3039 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
3040 set_mem_alias_set (mem, set);
3041 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
3050 /* Create the va_list data type. */
3053 rs6000_build_va_list ()
3055 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3057 /* For AIX, prefer 'char *' because that's what the system
3058 header files like. */
3059 if (DEFAULT_ABI != ABI_V4)
3060 return build_pointer_type (char_type_node);
3062 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3063 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3065 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
3066 unsigned_char_type_node);
3067 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
3068 unsigned_char_type_node);
3069 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3071 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3074 DECL_FIELD_CONTEXT (f_gpr) = record;
3075 DECL_FIELD_CONTEXT (f_fpr) = record;
3076 DECL_FIELD_CONTEXT (f_ovf) = record;
3077 DECL_FIELD_CONTEXT (f_sav) = record;
3079 TREE_CHAIN (record) = type_decl;
3080 TYPE_NAME (record) = type_decl;
3081 TYPE_FIELDS (record) = f_gpr;
3082 TREE_CHAIN (f_gpr) = f_fpr;
3083 TREE_CHAIN (f_fpr) = f_ovf;
3084 TREE_CHAIN (f_ovf) = f_sav;
3086 layout_type (record);
3088 /* The correct type is an array type of one element. */
3089 return build_array_type (record, build_index_type (size_zero_node));
3092 /* Implement va_start. */
3095 rs6000_va_start (stdarg_p, valist, nextarg)
3100 HOST_WIDE_INT words, n_gpr, n_fpr;
3101 tree f_gpr, f_fpr, f_ovf, f_sav;
3102 tree gpr, fpr, ovf, sav, t;
3104 /* Only SVR4 needs something special. */
3105 if (DEFAULT_ABI != ABI_V4)
3107 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
3111 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3112 f_fpr = TREE_CHAIN (f_gpr);
3113 f_ovf = TREE_CHAIN (f_fpr);
3114 f_sav = TREE_CHAIN (f_ovf);
3116 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
3117 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
3118 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
3119 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
3120 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
3122 /* Count number of gp and fp argument registers used. */
3123 words = current_function_args_info.words;
3124 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
3125 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
3127 if (TARGET_DEBUG_ARG)
3129 fputs ("va_start: words = ", stderr);
3130 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words);
3131 fputs (", n_gpr = ", stderr);
3132 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr);
3133 fputs (", n_fpr = ", stderr);
3134 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr);
3135 putc ('\n', stderr);
3138 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
3139 TREE_SIDE_EFFECTS (t) = 1;
3140 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3142 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
3143 TREE_SIDE_EFFECTS (t) = 1;
3144 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3146 /* Find the overflow area. */
3147 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
3149 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
3150 build_int_2 (words * UNITS_PER_WORD, 0));
3151 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3152 TREE_SIDE_EFFECTS (t) = 1;
3153 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3155 /* Find the register save area. */
3156 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
3157 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
3158 build_int_2 (-RS6000_VARARGS_SIZE, -1));
3159 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
3160 TREE_SIDE_EFFECTS (t) = 1;
3161 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3164 /* Implement va_arg. */
3167 rs6000_va_arg (valist, type)
3170 tree f_gpr, f_fpr, f_ovf, f_sav;
3171 tree gpr, fpr, ovf, sav, reg, t, u;
3172 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
3173 rtx lab_false, lab_over, addr_rtx, r;
3175 if (DEFAULT_ABI != ABI_V4)
3176 return std_expand_builtin_va_arg (valist, type);
3178 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3179 f_fpr = TREE_CHAIN (f_gpr);
3180 f_ovf = TREE_CHAIN (f_fpr);
3181 f_sav = TREE_CHAIN (f_ovf);
3183 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
3184 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
3185 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
3186 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
3187 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
3189 size = int_size_in_bytes (type);
3190 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3192 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
3194 /* Aggregates and long doubles are passed by reference. */
3200 size = UNITS_PER_WORD;
3203 else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT)
3205 /* FP args go in FP registers, if present. */
3214 /* Otherwise into GP registers. */
3222 /* Pull the value out of the saved registers ... */
3224 lab_false = gen_label_rtx ();
3225 lab_over = gen_label_rtx ();
3226 addr_rtx = gen_reg_rtx (Pmode);
3228 /* AltiVec vectors never go in registers. */
3229 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
3231 TREE_THIS_VOLATILE (reg) = 1;
3232 emit_cmp_and_jump_insns
3233 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
3234 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
3237 /* Long long is aligned in the registers. */
3240 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
3241 build_int_2 (n_reg - 1, 0));
3242 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
3243 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
3244 TREE_SIDE_EFFECTS (u) = 1;
3245 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
3249 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
3253 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
3254 build_int_2 (n_reg, 0));
3255 TREE_SIDE_EFFECTS (u) = 1;
3257 u = build1 (CONVERT_EXPR, integer_type_node, u);
3258 TREE_SIDE_EFFECTS (u) = 1;
3260 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
3261 TREE_SIDE_EFFECTS (u) = 1;
3263 t = build (PLUS_EXPR, ptr_type_node, t, u);
3264 TREE_SIDE_EFFECTS (t) = 1;
3266 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
3268 emit_move_insn (addr_rtx, r);
3270 emit_jump_insn (gen_jump (lab_over));
3274 emit_label (lab_false);
3276 /* ... otherwise out of the overflow area. */
3278 /* Make sure we don't find reg 7 for the next int arg.
3280 All AltiVec vectors go in the overflow area. So in the AltiVec
3281 case we need to get the vectors from the overflow area, but
3282 remember where the GPRs and FPRs are. */
3283 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
3284 || !TARGET_ALTIVEC))
3286 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
3287 TREE_SIDE_EFFECTS (t) = 1;
3288 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3291 /* Care for on-stack alignment if needed. */
3298 /* AltiVec vectors are 16 byte aligned. */
3299 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
3304 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
3305 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
3309 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
3311 emit_move_insn (addr_rtx, r);
3313 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
3314 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3315 TREE_SIDE_EFFECTS (t) = 1;
3316 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3318 emit_label (lab_over);
3322 r = gen_rtx_MEM (Pmode, addr_rtx);
3323 set_mem_alias_set (r, get_varargs_alias_set ());
3324 emit_move_insn (addr_rtx, r);
3332 #define def_builtin(MASK, NAME, TYPE, CODE) \
3334 if ((MASK) & target_flags) \
3335 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \
3338 struct builtin_description
3340 const unsigned int mask;
3341 const enum insn_code icode;
3342 const char *const name;
3343 const enum rs6000_builtins code;
3346 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
3348 static const struct builtin_description bdesc_3arg[] =
3350 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
3351 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
3352 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
3353 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
3354 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
3355 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
3356 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
3357 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
3358 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
3359 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
3360 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
3361 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
3362 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
3363 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
3364 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
3365 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
3366 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
3367 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
3368 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
3369 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
3370 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
3371 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
3372 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
3375 /* DST operations: void foo (void *, const int, const char). */
3377 static const struct builtin_description bdesc_dst[] =
3379 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
3380 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
3381 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
3382 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
3385 /* Simple binary operations: VECc = foo (VECa, VECb). */
3387 static const struct builtin_description bdesc_2arg[] =
3389 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
3390 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
3391 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
3392 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
3393 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
3394 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
3395 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
3396 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
3397 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
3398 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
3399 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
3400 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
3401 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
3402 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
3403 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
3404 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
3405 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
3406 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
3407 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
3408 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
3409 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
3410 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
3411 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
3412 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
3413 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
3414 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
3415 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
3416 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
3417 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
3418 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
3419 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
3420 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
3421 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
3422 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
3423 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
3424 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
3425 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
3426 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
3427 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
3428 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
3429 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
3430 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
3431 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
3432 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
3433 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
3434 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
3435 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
3436 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
3437 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
3438 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
3439 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
3440 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
3441 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
3442 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
3443 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
3444 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
3445 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
3446 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
3447 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
3448 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
3449 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
3450 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
3451 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
3452 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
3453 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
3454 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
3455 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
3456 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
3457 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
3458 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
3459 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
3460 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
3461 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
3462 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
3463 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
3464 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
3465 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
3466 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
3467 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
3468 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
3469 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
3470 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
3471 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
3472 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
3473 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
3474 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
3475 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
3476 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
3477 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
3478 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
3479 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
3480 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
3481 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
3482 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
3483 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
3484 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
3485 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
3486 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
3487 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
3488 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
3489 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
3490 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
3491 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
3492 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
3493 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
3494 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
3495 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
3496 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
3497 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
3498 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
3499 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
3500 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
3501 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
3504 /* AltiVec predicates. */
3506 struct builtin_description_predicates
3508 const unsigned int mask;
3509 const enum insn_code icode;
3511 const char *const name;
3512 const enum rs6000_builtins code;
3515 static const struct builtin_description_predicates bdesc_altivec_preds[] =
3517 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
3518 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
3519 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
3520 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
3521 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
3522 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
3523 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
3524 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
3525 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
3526 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
3527 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
3528 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
3529 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
3532 /* ABS* opreations. */
3534 static const struct builtin_description bdesc_abs[] =
3536 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
3537 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
3538 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
3539 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
3540 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
3541 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
3542 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
3545 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
3548 static const struct builtin_description bdesc_1arg[] =
3550 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
3551 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
3552 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
3553 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
3554 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
3555 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
3556 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
3557 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
3558 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
3559 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
3560 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
3561 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
3562 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
3563 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
3564 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
3565 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
3566 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
3570 altivec_expand_unop_builtin (icode, arglist, target)
3571 enum insn_code icode;
3576 tree arg0 = TREE_VALUE (arglist);
3577 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3578 enum machine_mode tmode = insn_data[icode].operand[0].mode;
3579 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
3581 /* If we got invalid arguments bail out before generating bad rtl. */
3582 if (arg0 == error_mark_node)
3587 /* Only allow 5-bit *signed* literals. */
3588 case CODE_FOR_altivec_vspltisb:
3589 case CODE_FOR_altivec_vspltish:
3590 case CODE_FOR_altivec_vspltisw:
3591 if (GET_CODE (op0) != CONST_INT
3592 || INTVAL (op0) > 0x1f
3593 || INTVAL (op0) < -0x1f)
3595 error ("argument 1 must be a 5-bit signed literal");
3604 || GET_MODE (target) != tmode
3605 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3606 target = gen_reg_rtx (tmode);
3608 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3609 op0 = copy_to_mode_reg (mode0, op0);
3611 pat = GEN_FCN (icode) (target, op0);
3620 altivec_expand_abs_builtin (icode, arglist, target)
3621 enum insn_code icode;
3625 rtx pat, scratch1, scratch2;
3626 tree arg0 = TREE_VALUE (arglist);
3627 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3628 enum machine_mode tmode = insn_data[icode].operand[0].mode;
3629 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
3631 /* If we have invalid arguments, bail out before generating bad rtl. */
3632 if (arg0 == error_mark_node)
3636 || GET_MODE (target) != tmode
3637 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3638 target = gen_reg_rtx (tmode);
3640 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3641 op0 = copy_to_mode_reg (mode0, op0);
3643 scratch1 = gen_reg_rtx (mode0);
3644 scratch2 = gen_reg_rtx (mode0);
3646 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
3655 altivec_expand_binop_builtin (icode, arglist, target)
3656 enum insn_code icode;
3661 tree arg0 = TREE_VALUE (arglist);
3662 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3663 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3664 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3665 enum machine_mode tmode = insn_data[icode].operand[0].mode;
3666 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
3667 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
3669 /* If we got invalid arguments bail out before generating bad rtl. */
3670 if (arg0 == error_mark_node || arg1 == error_mark_node)
3675 /* Only allow 5-bit unsigned literals. */
3676 case CODE_FOR_altivec_vcfux:
3677 case CODE_FOR_altivec_vcfsx:
3678 case CODE_FOR_altivec_vctsxs:
3679 case CODE_FOR_altivec_vctuxs:
3680 case CODE_FOR_altivec_vspltb:
3681 case CODE_FOR_altivec_vsplth:
3682 case CODE_FOR_altivec_vspltw:
3683 if (TREE_CODE (arg1) != INTEGER_CST
3684 || TREE_INT_CST_LOW (arg1) & ~0x1f)
3686 error ("argument 2 must be a 5-bit unsigned literal");
3695 || GET_MODE (target) != tmode
3696 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3697 target = gen_reg_rtx (tmode);
3699 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3700 op0 = copy_to_mode_reg (mode0, op0);
3701 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
3702 op1 = copy_to_mode_reg (mode1, op1);
3704 pat = GEN_FCN (icode) (target, op0, op1);
3713 altivec_expand_predicate_builtin (icode, opcode, arglist, target)
3714 enum insn_code icode;
3720 tree cr6_form = TREE_VALUE (arglist);
3721 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
3722 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3723 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3724 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3725 enum machine_mode tmode = SImode;
3726 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
3727 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
3730 if (TREE_CODE (cr6_form) != INTEGER_CST)
3732 error ("argument 1 of __builtin_altivec_predicate must be a constant");
3736 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
3741 /* If we have invalid arguments, bail out before generating bad rtl. */
3742 if (arg0 == error_mark_node || arg1 == error_mark_node)
3746 || GET_MODE (target) != tmode
3747 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3748 target = gen_reg_rtx (tmode);
3750 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3751 op0 = copy_to_mode_reg (mode0, op0);
3752 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
3753 op1 = copy_to_mode_reg (mode1, op1);
3755 scratch = gen_reg_rtx (mode0);
3757 pat = GEN_FCN (icode) (scratch, op0, op1,
3758 gen_rtx (SYMBOL_REF, Pmode, opcode));
3763 /* The vec_any* and vec_all* predicates use the same opcodes for two
3764 different operations, but the bits in CR6 will be different
3765 depending on what information we want. So we have to play tricks
3766 with CR6 to get the right bits out.
3768 If you think this is disgusting, look at the specs for the
3769 AltiVec predicates. */
3771 switch (cr6_form_int)
3774 emit_insn (gen_cr6_test_for_zero (target));
3777 emit_insn (gen_cr6_test_for_zero_reverse (target));
3780 emit_insn (gen_cr6_test_for_lt (target));
3783 emit_insn (gen_cr6_test_for_lt_reverse (target));
3786 error ("argument 1 of __builtin_altivec_predicate is out of range");
3794 altivec_expand_stv_builtin (icode, arglist)
3795 enum insn_code icode;
3798 tree arg0 = TREE_VALUE (arglist);
3799 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3800 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3801 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3802 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3803 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3805 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
3806 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
3807 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
3809 /* Invalid arguments. Bail before doing anything stoopid! */
3810 if (arg0 == error_mark_node
3811 || arg1 == error_mark_node
3812 || arg2 == error_mark_node)
3815 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
3816 op0 = copy_to_mode_reg (mode2, op0);
3817 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
3818 op1 = copy_to_mode_reg (mode0, op1);
3819 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
3820 op2 = copy_to_mode_reg (mode1, op2);
3822 pat = GEN_FCN (icode) (op1, op2, op0);
3829 altivec_expand_ternop_builtin (icode, arglist, target)
3830 enum insn_code icode;
3835 tree arg0 = TREE_VALUE (arglist);
3836 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3837 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3838 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3839 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3840 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3841 enum machine_mode tmode = insn_data[icode].operand[0].mode;
3842 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
3843 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
3844 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
3846 /* If we got invalid arguments bail out before generating bad rtl. */
3847 if (arg0 == error_mark_node
3848 || arg1 == error_mark_node
3849 || arg2 == error_mark_node)
3854 /* Only allow 4-bit unsigned literals. */
3855 case CODE_FOR_altivec_vsldoi_4sf:
3856 case CODE_FOR_altivec_vsldoi_4si:
3857 case CODE_FOR_altivec_vsldoi_8hi:
3858 case CODE_FOR_altivec_vsldoi_16qi:
3859 if (TREE_CODE (arg2) != INTEGER_CST
3860 || TREE_INT_CST_LOW (arg2) & ~0xf)
3862 error ("argument 3 must be a 4-bit unsigned literal");
3871 || GET_MODE (target) != tmode
3872 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3873 target = gen_reg_rtx (tmode);
3875 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3876 op0 = copy_to_mode_reg (mode0, op0);
3877 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
3878 op1 = copy_to_mode_reg (mode1, op1);
3879 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
3880 op2 = copy_to_mode_reg (mode2, op2);
3882 pat = GEN_FCN (icode) (target, op0, op1, op2);
3890 altivec_expand_builtin (exp, target)
3894 struct builtin_description *d;
3895 struct builtin_description_predicates *dp;
3897 enum insn_code icode;
3898 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
3899 tree arglist = TREE_OPERAND (exp, 1);
3900 tree arg0, arg1, arg2;
3901 rtx op0, op1, op2, pat;
3902 enum machine_mode tmode, mode0, mode1, mode2;
3903 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3907 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
3908 icode = CODE_FOR_altivec_lvx_16qi;
3909 arg0 = TREE_VALUE (arglist);
3910 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3911 tmode = insn_data[icode].operand[0].mode;
3912 mode0 = insn_data[icode].operand[1].mode;
3915 || GET_MODE (target) != tmode
3916 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3917 target = gen_reg_rtx (tmode);
3919 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3920 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
3922 pat = GEN_FCN (icode) (target, op0);
3928 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
3929 icode = CODE_FOR_altivec_lvx_8hi;
3930 arg0 = TREE_VALUE (arglist);
3931 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3932 tmode = insn_data[icode].operand[0].mode;
3933 mode0 = insn_data[icode].operand[1].mode;
3936 || GET_MODE (target) != tmode
3937 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3938 target = gen_reg_rtx (tmode);
3940 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3941 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
3943 pat = GEN_FCN (icode) (target, op0);
3949 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
3950 icode = CODE_FOR_altivec_lvx_4si;
3951 arg0 = TREE_VALUE (arglist);
3952 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3953 tmode = insn_data[icode].operand[0].mode;
3954 mode0 = insn_data[icode].operand[1].mode;
3957 || GET_MODE (target) != tmode
3958 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3959 target = gen_reg_rtx (tmode);
3961 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3962 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
3964 pat = GEN_FCN (icode) (target, op0);
3970 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
3971 icode = CODE_FOR_altivec_lvx_4sf;
3972 arg0 = TREE_VALUE (arglist);
3973 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3974 tmode = insn_data[icode].operand[0].mode;
3975 mode0 = insn_data[icode].operand[1].mode;
3978 || GET_MODE (target) != tmode
3979 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
3980 target = gen_reg_rtx (tmode);
3982 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
3983 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
3985 pat = GEN_FCN (icode) (target, op0);
3991 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
3992 icode = CODE_FOR_altivec_stvx_16qi;
3993 arg0 = TREE_VALUE (arglist);
3994 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3995 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3996 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3997 mode0 = insn_data[icode].operand[0].mode;
3998 mode1 = insn_data[icode].operand[1].mode;
4000 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4001 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
4002 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
4003 op1 = copy_to_mode_reg (mode1, op1);
4005 pat = GEN_FCN (icode) (op0, op1);
4010 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
4011 icode = CODE_FOR_altivec_stvx_8hi;
4012 arg0 = TREE_VALUE (arglist);
4013 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4014 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4015 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4016 mode0 = insn_data[icode].operand[0].mode;
4017 mode1 = insn_data[icode].operand[1].mode;
4019 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4020 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
4021 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
4022 op1 = copy_to_mode_reg (mode1, op1);
4024 pat = GEN_FCN (icode) (op0, op1);
4029 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
4030 icode = CODE_FOR_altivec_stvx_4si;
4031 arg0 = TREE_VALUE (arglist);
4032 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4033 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4034 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4035 mode0 = insn_data[icode].operand[0].mode;
4036 mode1 = insn_data[icode].operand[1].mode;
4038 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4039 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
4040 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
4041 op1 = copy_to_mode_reg (mode1, op1);
4043 pat = GEN_FCN (icode) (op0, op1);
4048 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
4049 icode = CODE_FOR_altivec_stvx_4sf;
4050 arg0 = TREE_VALUE (arglist);
4051 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4052 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4053 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4054 mode0 = insn_data[icode].operand[0].mode;
4055 mode1 = insn_data[icode].operand[1].mode;
4057 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4058 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
4059 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
4060 op1 = copy_to_mode_reg (mode1, op1);
4062 pat = GEN_FCN (icode) (op0, op1);
4067 case ALTIVEC_BUILTIN_STVX:
4068 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
4069 case ALTIVEC_BUILTIN_STVEBX:
4070 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
4071 case ALTIVEC_BUILTIN_STVEHX:
4072 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
4073 case ALTIVEC_BUILTIN_STVEWX:
4074 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
4075 case ALTIVEC_BUILTIN_STVXL:
4076 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
4078 case ALTIVEC_BUILTIN_MFVSCR:
4079 icode = CODE_FOR_altivec_mfvscr;
4080 tmode = insn_data[icode].operand[0].mode;
4083 || GET_MODE (target) != tmode
4084 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4085 target = gen_reg_rtx (tmode);
4087 pat = GEN_FCN (icode) (target);
4093 case ALTIVEC_BUILTIN_MTVSCR:
4094 icode = CODE_FOR_altivec_mtvscr;
4095 arg0 = TREE_VALUE (arglist);
4096 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4097 mode0 = insn_data[icode].operand[0].mode;
4099 /* If we got invalid arguments bail out before generating bad rtl. */
4100 if (arg0 == error_mark_node)
4103 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4104 op0 = copy_to_mode_reg (mode0, op0);
4106 pat = GEN_FCN (icode) (op0);
4111 case ALTIVEC_BUILTIN_DSSALL:
4112 emit_insn (gen_altivec_dssall ());
4115 case ALTIVEC_BUILTIN_DSS:
4116 icode = CODE_FOR_altivec_dss;
4117 arg0 = TREE_VALUE (arglist);
4118 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4119 mode0 = insn_data[icode].operand[0].mode;
4121 /* If we got invalid arguments bail out before generating bad rtl. */
4122 if (arg0 == error_mark_node)
4125 if (TREE_CODE (arg0) != INTEGER_CST
4126 || TREE_INT_CST_LOW (arg0) & ~0x3)
4128 error ("argument to dss must be a 2-bit unsigned literal");
4132 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4133 op0 = copy_to_mode_reg (mode0, op0);
4135 emit_insn (gen_altivec_dss (op0));
4139 /* Handle DST variants. */
4140 d = (struct builtin_description *) bdesc_dst;
4141 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
4142 if (d->code == fcode)
4144 arg0 = TREE_VALUE (arglist);
4145 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4146 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4147 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4148 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4149 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
4150 mode0 = insn_data[d->icode].operand[0].mode;
4151 mode1 = insn_data[d->icode].operand[1].mode;
4152 mode2 = insn_data[d->icode].operand[2].mode;
4154 /* Invalid arguments, bail out before generating bad rtl. */
4155 if (arg0 == error_mark_node
4156 || arg1 == error_mark_node
4157 || arg2 == error_mark_node)
4160 if (TREE_CODE (arg2) != INTEGER_CST
4161 || TREE_INT_CST_LOW (arg2) & ~0x3)
4163 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
4167 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
4168 op0 = copy_to_mode_reg (mode0, op0);
4169 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
4170 op1 = copy_to_mode_reg (mode1, op1);
4172 pat = GEN_FCN (d->icode) (op0, op1, op2);
4179 /* Expand abs* operations. */
4180 d = (struct builtin_description *) bdesc_abs;
4181 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
4182 if (d->code == fcode)
4183 return altivec_expand_abs_builtin (d->icode, arglist, target);
4185 /* Handle simple unary operations. */
4186 d = (struct builtin_description *) bdesc_1arg;
4187 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
4188 if (d->code == fcode)
4189 return altivec_expand_unop_builtin (d->icode, arglist, target);
4191 /* Handle simple binary operations. */
4192 d = (struct builtin_description *) bdesc_2arg;
4193 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
4194 if (d->code == fcode)
4195 return altivec_expand_binop_builtin (d->icode, arglist, target);
4197 /* Expand the AltiVec predicates. */
4198 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
4199 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
4200 if (dp->code == fcode)
4201 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
4203 /* LV* are funky. We initialized them differently. */
4206 case ALTIVEC_BUILTIN_LVSL:
4207 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsl,
4209 case ALTIVEC_BUILTIN_LVSR:
4210 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsr,
4212 case ALTIVEC_BUILTIN_LVEBX:
4213 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvebx,
4215 case ALTIVEC_BUILTIN_LVEHX:
4216 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvehx,
4218 case ALTIVEC_BUILTIN_LVEWX:
4219 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvewx,
4221 case ALTIVEC_BUILTIN_LVXL:
4222 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvxl,
4224 case ALTIVEC_BUILTIN_LVX:
4225 return altivec_expand_binop_builtin (CODE_FOR_altivec_lvx,
4232 /* Handle simple ternary operations. */
4233 d = (struct builtin_description *) bdesc_3arg;
4234 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
4235 if (d->code == fcode)
4236 return altivec_expand_ternop_builtin (d->icode, arglist, target);
4242 /* Expand an expression EXP that calls a built-in function,
4243 with result going to TARGET if that's convenient
4244 (and in mode MODE if that's convenient).
4245 SUBTARGET may be used as the target for computing one of EXP's operands.
4246 IGNORE is nonzero if the value is to be ignored. */
4249 rs6000_expand_builtin (exp, target, subtarget, mode, ignore)
4252 rtx subtarget ATTRIBUTE_UNUSED;
4253 enum machine_mode mode ATTRIBUTE_UNUSED;
4254 int ignore ATTRIBUTE_UNUSED;
4257 return altivec_expand_builtin (exp, target);
4263 rs6000_init_builtins ()
4266 altivec_init_builtins ();
4270 altivec_init_builtins (void)
4272 struct builtin_description *d;
4273 struct builtin_description_predicates *dp;
4276 tree endlink = void_list_node;
4278 tree pint_type_node = build_pointer_type (integer_type_node);
4279 tree pvoid_type_node = build_pointer_type (void_type_node);
4280 tree pshort_type_node = build_pointer_type (short_integer_type_node);
4281 tree pchar_type_node = build_pointer_type (char_type_node);
4282 tree pfloat_type_node = build_pointer_type (float_type_node);
4284 tree v4sf_ftype_v4sf_v4sf_v16qi
4285 = build_function_type (V4SF_type_node,
4286 tree_cons (NULL_TREE, V4SF_type_node,
4287 tree_cons (NULL_TREE, V4SF_type_node,
4288 tree_cons (NULL_TREE,
4291 tree v4si_ftype_v4si_v4si_v16qi
4292 = build_function_type (V4SI_type_node,
4293 tree_cons (NULL_TREE, V4SI_type_node,
4294 tree_cons (NULL_TREE, V4SI_type_node,
4295 tree_cons (NULL_TREE,
4298 tree v8hi_ftype_v8hi_v8hi_v16qi
4299 = build_function_type (V8HI_type_node,
4300 tree_cons (NULL_TREE, V8HI_type_node,
4301 tree_cons (NULL_TREE, V8HI_type_node,
4302 tree_cons (NULL_TREE,
4305 tree v16qi_ftype_v16qi_v16qi_v16qi
4306 = build_function_type (V16QI_type_node,
4307 tree_cons (NULL_TREE, V16QI_type_node,
4308 tree_cons (NULL_TREE, V16QI_type_node,
4309 tree_cons (NULL_TREE,
4313 /* V4SI foo (char). */
4314 tree v4si_ftype_char
4315 = build_function_type (V4SI_type_node,
4316 tree_cons (NULL_TREE, char_type_node, endlink));
4318 /* V8HI foo (char). */
4319 tree v8hi_ftype_char
4320 = build_function_type (V8HI_type_node,
4321 tree_cons (NULL_TREE, char_type_node, endlink));
4323 /* V16QI foo (char). */
4324 tree v16qi_ftype_char
4325 = build_function_type (V16QI_type_node,
4326 tree_cons (NULL_TREE, char_type_node, endlink));
4327 /* V4SF foo (V4SF). */
4328 tree v4sf_ftype_v4sf
4329 = build_function_type (V4SF_type_node,
4330 tree_cons (NULL_TREE, V4SF_type_node, endlink));
4332 /* V4SI foo (int *). */
4333 tree v4si_ftype_pint
4334 = build_function_type (V4SI_type_node,
4335 tree_cons (NULL_TREE, pint_type_node, endlink));
4336 /* V8HI foo (short *). */
4337 tree v8hi_ftype_pshort
4338 = build_function_type (V8HI_type_node,
4339 tree_cons (NULL_TREE, pshort_type_node, endlink));
4340 /* V16QI foo (char *). */
4341 tree v16qi_ftype_pchar
4342 = build_function_type (V16QI_type_node,
4343 tree_cons (NULL_TREE, pchar_type_node, endlink));
4344 /* V4SF foo (float *). */
4345 tree v4sf_ftype_pfloat
4346 = build_function_type (V4SF_type_node,
4347 tree_cons (NULL_TREE, pfloat_type_node, endlink));
4349 /* V8HI foo (V16QI). */
4350 tree v8hi_ftype_v16qi
4351 = build_function_type (V8HI_type_node,
4352 tree_cons (NULL_TREE, V16QI_type_node, endlink));
4354 /* void foo (void *, int, char/literal). */
4355 tree void_ftype_pvoid_int_char
4356 = build_function_type (void_type_node,
4357 tree_cons (NULL_TREE, pvoid_type_node,
4358 tree_cons (NULL_TREE, integer_type_node,
4359 tree_cons (NULL_TREE,
4363 /* void foo (int *, V4SI). */
4364 tree void_ftype_pint_v4si
4365 = build_function_type (void_type_node,
4366 tree_cons (NULL_TREE, pint_type_node,
4367 tree_cons (NULL_TREE, V4SI_type_node,
4369 /* void foo (short *, V8HI). */
4370 tree void_ftype_pshort_v8hi
4371 = build_function_type (void_type_node,
4372 tree_cons (NULL_TREE, pshort_type_node,
4373 tree_cons (NULL_TREE, V8HI_type_node,
4375 /* void foo (char *, V16QI). */
4376 tree void_ftype_pchar_v16qi
4377 = build_function_type (void_type_node,
4378 tree_cons (NULL_TREE, pchar_type_node,
4379 tree_cons (NULL_TREE, V16QI_type_node,
4381 /* void foo (float *, V4SF). */
4382 tree void_ftype_pfloat_v4sf
4383 = build_function_type (void_type_node,
4384 tree_cons (NULL_TREE, pfloat_type_node,
4385 tree_cons (NULL_TREE, V4SF_type_node,
4388 /* void foo (V4SI). */
4389 tree void_ftype_v4si
4390 = build_function_type (void_type_node,
4391 tree_cons (NULL_TREE, V4SI_type_node,
4394 /* void foo (vint, int, void *). */
4395 tree void_ftype_v4si_int_pvoid
4396 = build_function_type (void_type_node,
4397 tree_cons (NULL_TREE, V4SI_type_node,
4398 tree_cons (NULL_TREE, integer_type_node,
4399 tree_cons (NULL_TREE,
4403 /* void foo (vchar, int, void *). */
4404 tree void_ftype_v16qi_int_pvoid
4405 = build_function_type (void_type_node,
4406 tree_cons (NULL_TREE, V16QI_type_node,
4407 tree_cons (NULL_TREE, integer_type_node,
4408 tree_cons (NULL_TREE,
4412 /* void foo (vshort, int, void *). */
4413 tree void_ftype_v8hi_int_pvoid
4414 = build_function_type (void_type_node,
4415 tree_cons (NULL_TREE, V8HI_type_node,
4416 tree_cons (NULL_TREE, integer_type_node,
4417 tree_cons (NULL_TREE,
4421 /* void foo (char). */
4423 = build_function_type (void_type_node,
4424 tree_cons (NULL_TREE, char_type_node,
4427 /* void foo (void). */
4428 tree void_ftype_void
4429 = build_function_type (void_type_node, void_list_node);
4431 /* vshort foo (void). */
4432 tree v8hi_ftype_void
4433 = build_function_type (V8HI_type_node, void_list_node);
4435 tree v4si_ftype_v4si_v4si
4436 = build_function_type (V4SI_type_node,
4437 tree_cons (NULL_TREE, V4SI_type_node,
4438 tree_cons (NULL_TREE, V4SI_type_node,
4441 /* These are for the unsigned 5 bit literals. */
4443 tree v4sf_ftype_v4si_char
4444 = build_function_type (V4SF_type_node,
4445 tree_cons (NULL_TREE, V4SI_type_node,
4446 tree_cons (NULL_TREE, char_type_node,
4448 tree v4si_ftype_v4sf_char
4449 = build_function_type (V4SI_type_node,
4450 tree_cons (NULL_TREE, V4SF_type_node,
4451 tree_cons (NULL_TREE, char_type_node,
4453 tree v4si_ftype_v4si_char
4454 = build_function_type (V4SI_type_node,
4455 tree_cons (NULL_TREE, V4SI_type_node,
4456 tree_cons (NULL_TREE, char_type_node,
4458 tree v8hi_ftype_v8hi_char
4459 = build_function_type (V8HI_type_node,
4460 tree_cons (NULL_TREE, V8HI_type_node,
4461 tree_cons (NULL_TREE, char_type_node,
4463 tree v16qi_ftype_v16qi_char
4464 = build_function_type (V16QI_type_node,
4465 tree_cons (NULL_TREE, V16QI_type_node,
4466 tree_cons (NULL_TREE, char_type_node,
4469 /* These are for the unsigned 4 bit literals. */
4471 tree v16qi_ftype_v16qi_v16qi_char
4472 = build_function_type (V16QI_type_node,
4473 tree_cons (NULL_TREE, V16QI_type_node,
4474 tree_cons (NULL_TREE, V16QI_type_node,
4475 tree_cons (NULL_TREE,
4479 tree v8hi_ftype_v8hi_v8hi_char
4480 = build_function_type (V8HI_type_node,
4481 tree_cons (NULL_TREE, V8HI_type_node,
4482 tree_cons (NULL_TREE, V8HI_type_node,
4483 tree_cons (NULL_TREE,
4487 tree v4si_ftype_v4si_v4si_char
4488 = build_function_type (V4SI_type_node,
4489 tree_cons (NULL_TREE, V4SI_type_node,
4490 tree_cons (NULL_TREE, V4SI_type_node,
4491 tree_cons (NULL_TREE,
4495 tree v4sf_ftype_v4sf_v4sf_char
4496 = build_function_type (V4SF_type_node,
4497 tree_cons (NULL_TREE, V4SF_type_node,
4498 tree_cons (NULL_TREE, V4SF_type_node,
4499 tree_cons (NULL_TREE,
4503 /* End of 4 bit literals. */
4505 tree v4sf_ftype_v4sf_v4sf
4506 = build_function_type (V4SF_type_node,
4507 tree_cons (NULL_TREE, V4SF_type_node,
4508 tree_cons (NULL_TREE, V4SF_type_node,
4510 tree v4sf_ftype_v4sf_v4sf_v4si
4511 = build_function_type (V4SF_type_node,
4512 tree_cons (NULL_TREE, V4SF_type_node,
4513 tree_cons (NULL_TREE, V4SF_type_node,
4514 tree_cons (NULL_TREE,
4517 tree v4sf_ftype_v4sf_v4sf_v4sf
4518 = build_function_type (V4SF_type_node,
4519 tree_cons (NULL_TREE, V4SF_type_node,
4520 tree_cons (NULL_TREE, V4SF_type_node,
4521 tree_cons (NULL_TREE,
4524 tree v4si_ftype_v4si_v4si_v4si
4525 = build_function_type (V4SI_type_node,
4526 tree_cons (NULL_TREE, V4SI_type_node,
4527 tree_cons (NULL_TREE, V4SI_type_node,
4528 tree_cons (NULL_TREE,
4532 tree v8hi_ftype_v8hi_v8hi
4533 = build_function_type (V8HI_type_node,
4534 tree_cons (NULL_TREE, V8HI_type_node,
4535 tree_cons (NULL_TREE, V8HI_type_node,
4537 tree v8hi_ftype_v8hi_v8hi_v8hi
4538 = build_function_type (V8HI_type_node,
4539 tree_cons (NULL_TREE, V8HI_type_node,
4540 tree_cons (NULL_TREE, V8HI_type_node,
4541 tree_cons (NULL_TREE,
4544 tree v4si_ftype_v8hi_v8hi_v4si
4545 = build_function_type (V4SI_type_node,
4546 tree_cons (NULL_TREE, V8HI_type_node,
4547 tree_cons (NULL_TREE, V8HI_type_node,
4548 tree_cons (NULL_TREE,
4551 tree v4si_ftype_v16qi_v16qi_v4si
4552 = build_function_type (V4SI_type_node,
4553 tree_cons (NULL_TREE, V16QI_type_node,
4554 tree_cons (NULL_TREE, V16QI_type_node,
4555 tree_cons (NULL_TREE,
4559 tree v16qi_ftype_v16qi_v16qi
4560 = build_function_type (V16QI_type_node,
4561 tree_cons (NULL_TREE, V16QI_type_node,
4562 tree_cons (NULL_TREE, V16QI_type_node,
4565 tree v4si_ftype_v4sf_v4sf
4566 = build_function_type (V4SI_type_node,
4567 tree_cons (NULL_TREE, V4SF_type_node,
4568 tree_cons (NULL_TREE, V4SF_type_node,
4571 tree v4si_ftype_v4si
4572 = build_function_type (V4SI_type_node,
4573 tree_cons (NULL_TREE, V4SI_type_node, endlink));
4575 tree v8hi_ftype_v8hi
4576 = build_function_type (V8HI_type_node,
4577 tree_cons (NULL_TREE, V8HI_type_node, endlink));
4579 tree v16qi_ftype_v16qi
4580 = build_function_type (V16QI_type_node,
4581 tree_cons (NULL_TREE, V16QI_type_node, endlink));
4583 tree v8hi_ftype_v16qi_v16qi
4584 = build_function_type (V8HI_type_node,
4585 tree_cons (NULL_TREE, V16QI_type_node,
4586 tree_cons (NULL_TREE, V16QI_type_node,
4589 tree v4si_ftype_v8hi_v8hi
4590 = build_function_type (V4SI_type_node,
4591 tree_cons (NULL_TREE, V8HI_type_node,
4592 tree_cons (NULL_TREE, V8HI_type_node,
4595 tree v8hi_ftype_v4si_v4si
4596 = build_function_type (V8HI_type_node,
4597 tree_cons (NULL_TREE, V4SI_type_node,
4598 tree_cons (NULL_TREE, V4SI_type_node,
4601 tree v16qi_ftype_v8hi_v8hi
4602 = build_function_type (V16QI_type_node,
4603 tree_cons (NULL_TREE, V8HI_type_node,
4604 tree_cons (NULL_TREE, V8HI_type_node,
4607 tree v4si_ftype_v16qi_v4si
4608 = build_function_type (V4SI_type_node,
4609 tree_cons (NULL_TREE, V16QI_type_node,
4610 tree_cons (NULL_TREE, V4SI_type_node,
4613 tree v4si_ftype_v16qi_v16qi
4614 = build_function_type (V4SI_type_node,
4615 tree_cons (NULL_TREE, V16QI_type_node,
4616 tree_cons (NULL_TREE, V16QI_type_node,
4619 tree v4si_ftype_v8hi_v4si
4620 = build_function_type (V4SI_type_node,
4621 tree_cons (NULL_TREE, V8HI_type_node,
4622 tree_cons (NULL_TREE, V4SI_type_node,
4625 tree v4si_ftype_v8hi
4626 = build_function_type (V4SI_type_node,
4627 tree_cons (NULL_TREE, V8HI_type_node, endlink));
4629 tree int_ftype_v4si_v4si
4630 = build_function_type (integer_type_node,
4631 tree_cons (NULL_TREE, V4SI_type_node,
4632 tree_cons (NULL_TREE, V4SI_type_node,
4635 tree int_ftype_v4sf_v4sf
4636 = build_function_type (integer_type_node,
4637 tree_cons (NULL_TREE, V4SF_type_node,
4638 tree_cons (NULL_TREE, V4SF_type_node,
4641 tree int_ftype_v16qi_v16qi
4642 = build_function_type (integer_type_node,
4643 tree_cons (NULL_TREE, V16QI_type_node,
4644 tree_cons (NULL_TREE, V16QI_type_node,
4647 tree int_ftype_int_v4si_v4si
4648 = build_function_type
4650 tree_cons (NULL_TREE, integer_type_node,
4651 tree_cons (NULL_TREE, V4SI_type_node,
4652 tree_cons (NULL_TREE, V4SI_type_node,
4655 tree int_ftype_int_v4sf_v4sf
4656 = build_function_type
4658 tree_cons (NULL_TREE, integer_type_node,
4659 tree_cons (NULL_TREE, V4SF_type_node,
4660 tree_cons (NULL_TREE, V4SF_type_node,
4663 tree int_ftype_int_v8hi_v8hi
4664 = build_function_type
4666 tree_cons (NULL_TREE, integer_type_node,
4667 tree_cons (NULL_TREE, V8HI_type_node,
4668 tree_cons (NULL_TREE, V8HI_type_node,
4671 tree int_ftype_int_v16qi_v16qi
4672 = build_function_type
4674 tree_cons (NULL_TREE, integer_type_node,
4675 tree_cons (NULL_TREE, V16QI_type_node,
4676 tree_cons (NULL_TREE, V16QI_type_node,
4679 tree v16qi_ftype_int_pvoid
4680 = build_function_type (V16QI_type_node,
4681 tree_cons (NULL_TREE, integer_type_node,
4682 tree_cons (NULL_TREE, pvoid_type_node,
4685 tree v4si_ftype_int_pvoid
4686 = build_function_type (V4SI_type_node,
4687 tree_cons (NULL_TREE, integer_type_node,
4688 tree_cons (NULL_TREE, pvoid_type_node,
4691 tree v8hi_ftype_int_pvoid
4692 = build_function_type (V8HI_type_node,
4693 tree_cons (NULL_TREE, integer_type_node,
4694 tree_cons (NULL_TREE, pvoid_type_node,
4697 tree int_ftype_v8hi_v8hi
4698 = build_function_type (integer_type_node,
4699 tree_cons (NULL_TREE, V8HI_type_node,
4700 tree_cons (NULL_TREE, V8HI_type_node,
4703 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
4704 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
4705 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si);
4706 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si);
4707 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
4708 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
4709 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
4710 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
4711 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
4712 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
4713 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
4714 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
4715 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSL);
4716 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSR);
4717 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEBX);
4718 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEHX);
4719 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEWX);
4720 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVXL);
4721 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVX);
4722 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX);
4723 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX);
4724 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX);
4725 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX);
4726 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL);
4728 /* Add the simple ternary operators. */
4729 d = (struct builtin_description *) bdesc_3arg;
4730 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
4733 enum machine_mode mode0, mode1, mode2, mode3;
4739 mode0 = insn_data[d->icode].operand[0].mode;
4740 mode1 = insn_data[d->icode].operand[1].mode;
4741 mode2 = insn_data[d->icode].operand[2].mode;
4742 mode3 = insn_data[d->icode].operand[3].mode;
4744 /* When all four are of the same mode. */
4745 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
4750 type = v4si_ftype_v4si_v4si_v4si;
4753 type = v4sf_ftype_v4sf_v4sf_v4sf;
4756 type = v8hi_ftype_v8hi_v8hi_v8hi;
4759 type = v16qi_ftype_v16qi_v16qi_v16qi;
4765 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
4770 type = v4si_ftype_v4si_v4si_v16qi;
4773 type = v4sf_ftype_v4sf_v4sf_v16qi;
4776 type = v8hi_ftype_v8hi_v8hi_v16qi;
4779 type = v16qi_ftype_v16qi_v16qi_v16qi;
4785 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
4786 && mode3 == V4SImode)
4787 type = v4si_ftype_v16qi_v16qi_v4si;
4788 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
4789 && mode3 == V4SImode)
4790 type = v4si_ftype_v8hi_v8hi_v4si;
4791 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
4792 && mode3 == V4SImode)
4793 type = v4sf_ftype_v4sf_v4sf_v4si;
4795 /* vchar, vchar, vchar, 4 bit literal. */
4796 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
4798 type = v16qi_ftype_v16qi_v16qi_char;
4800 /* vshort, vshort, vshort, 4 bit literal. */
4801 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
4803 type = v8hi_ftype_v8hi_v8hi_char;
4805 /* vint, vint, vint, 4 bit literal. */
4806 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
4808 type = v4si_ftype_v4si_v4si_char;
4810 /* vfloat, vfloat, vfloat, 4 bit literal. */
4811 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
4813 type = v4sf_ftype_v4sf_v4sf_char;
4818 def_builtin (d->mask, d->name, type, d->code);
4821 /* Add the DST variants. */
4822 d = (struct builtin_description *) bdesc_dst;
4823 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
4824 def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code);
4826 /* Initialize the predicates. */
4827 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
4828 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
4830 enum machine_mode mode1;
4833 mode1 = insn_data[dp->icode].operand[1].mode;
4838 type = int_ftype_int_v4si_v4si;
4841 type = int_ftype_int_v8hi_v8hi;
4844 type = int_ftype_int_v16qi_v16qi;
4847 type = int_ftype_int_v4sf_v4sf;
4853 def_builtin (dp->mask, dp->name, type, dp->code);
4856 /* Add the simple binary operators. */
4857 d = (struct builtin_description *) bdesc_2arg;
4858 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
4860 enum machine_mode mode0, mode1, mode2;
4866 mode0 = insn_data[d->icode].operand[0].mode;
4867 mode1 = insn_data[d->icode].operand[1].mode;
4868 mode2 = insn_data[d->icode].operand[2].mode;
4870 /* When all three operands are of the same mode. */
4871 if (mode0 == mode1 && mode1 == mode2)
4876 type = v4sf_ftype_v4sf_v4sf;
4879 type = v4si_ftype_v4si_v4si;
4882 type = v16qi_ftype_v16qi_v16qi;
4885 type = v8hi_ftype_v8hi_v8hi;
4892 /* A few other combos we really don't want to do manually. */
4894 /* vint, vfloat, vfloat. */
4895 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
4896 type = v4si_ftype_v4sf_v4sf;
4898 /* vshort, vchar, vchar. */
4899 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
4900 type = v8hi_ftype_v16qi_v16qi;
4902 /* vint, vshort, vshort. */
4903 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
4904 type = v4si_ftype_v8hi_v8hi;
4906 /* vshort, vint, vint. */
4907 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
4908 type = v8hi_ftype_v4si_v4si;
4910 /* vchar, vshort, vshort. */
4911 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
4912 type = v16qi_ftype_v8hi_v8hi;
4914 /* vint, vchar, vint. */
4915 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
4916 type = v4si_ftype_v16qi_v4si;
4918 /* vint, vchar, vchar. */
4919 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
4920 type = v4si_ftype_v16qi_v16qi;
4922 /* vint, vshort, vint. */
4923 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
4924 type = v4si_ftype_v8hi_v4si;
4926 /* vint, vint, 5 bit literal. */
4927 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
4928 type = v4si_ftype_v4si_char;
4930 /* vshort, vshort, 5 bit literal. */
4931 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
4932 type = v8hi_ftype_v8hi_char;
4934 /* vchar, vchar, 5 bit literal. */
4935 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
4936 type = v16qi_ftype_v16qi_char;
4938 /* vfloat, vint, 5 bit literal. */
4939 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
4940 type = v4sf_ftype_v4si_char;
4942 /* vint, vfloat, 5 bit literal. */
4943 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
4944 type = v4si_ftype_v4sf_char;
4947 else if (mode0 == SImode)
4952 type = int_ftype_v4si_v4si;
4955 type = int_ftype_v4sf_v4sf;
4958 type = int_ftype_v16qi_v16qi;
4961 type = int_ftype_v8hi_v8hi;
4971 def_builtin (d->mask, d->name, type, d->code);
4974 /* Initialize the abs* operators. */
4975 d = (struct builtin_description *) bdesc_abs;
4976 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
4978 enum machine_mode mode0;
4981 mode0 = insn_data[d->icode].operand[0].mode;
4986 type = v4si_ftype_v4si;
4989 type = v8hi_ftype_v8hi;
4992 type = v16qi_ftype_v16qi;
4995 type = v4sf_ftype_v4sf;
5001 def_builtin (d->mask, d->name, type, d->code);
5004 /* Add the simple unary operators. */
5005 d = (struct builtin_description *) bdesc_1arg;
5006 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
5008 enum machine_mode mode0, mode1;
5014 mode0 = insn_data[d->icode].operand[0].mode;
5015 mode1 = insn_data[d->icode].operand[1].mode;
5017 if (mode0 == V4SImode && mode1 == QImode)
5018 type = v4si_ftype_char;
5019 else if (mode0 == V8HImode && mode1 == QImode)
5020 type = v8hi_ftype_char;
5021 else if (mode0 == V16QImode && mode1 == QImode)
5022 type = v16qi_ftype_char;
5023 else if (mode0 == V4SFmode && mode1 == V4SFmode)
5024 type = v4sf_ftype_v4sf;
5025 else if (mode0 == V8HImode && mode1 == V16QImode)
5026 type = v8hi_ftype_v16qi;
5027 else if (mode0 == V4SImode && mode1 == V8HImode)
5028 type = v4si_ftype_v8hi;
5032 def_builtin (d->mask, d->name, type, d->code);
5037 /* Generate a memory reference for expand_block_move, copying volatile,
5038 and other bits from an original memory reference. */
5041 expand_block_move_mem (mode, addr, orig_mem)
5042 enum machine_mode mode;
5046 rtx mem = gen_rtx_MEM (mode, addr);
5048 MEM_COPY_ATTRIBUTES (mem, orig_mem);
5052 /* Expand a block move operation, and return 1 if successful. Return 0
5053 if we should let the compiler generate normal code.
5055 operands[0] is the destination
5056 operands[1] is the source
5057 operands[2] is the length
5058 operands[3] is the alignment */
5060 #define MAX_MOVE_REG 4
5063 expand_block_move (operands)
5066 rtx orig_dest = operands[0];
5067 rtx orig_src = operands[1];
5068 rtx bytes_rtx = operands[2];
5069 rtx align_rtx = operands[3];
5070 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5081 rtx stores[MAX_MOVE_REG];
5084 /* If this is not a fixed size move, just call memcpy */
5088 /* If this is not a fixed size alignment, abort */
5089 if (GET_CODE (align_rtx) != CONST_INT)
5091 align = INTVAL (align_rtx);
5093 /* Anything to move? */
5094 bytes = INTVAL (bytes_rtx);
5098 /* store_one_arg depends on expand_block_move to handle at least the size of
5099 reg_parm_stack_space. */
5100 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
5103 /* Move the address into scratch registers. */
5104 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
5105 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
5107 if (TARGET_STRING) /* string instructions are available */
5109 for ( ; bytes > 0; bytes -= move_bytes)
5111 if (bytes > 24 /* move up to 32 bytes at a time */
5119 && ! fixed_regs[12])
5121 move_bytes = (bytes > 32) ? 32 : bytes;
5122 emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode,
5125 expand_block_move_mem (BLKmode,
5128 GEN_INT ((move_bytes == 32)
5132 else if (bytes > 16 /* move up to 24 bytes at a time */
5138 && ! fixed_regs[10])
5140 move_bytes = (bytes > 24) ? 24 : bytes;
5141 emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode,
5144 expand_block_move_mem (BLKmode,
5147 GEN_INT (move_bytes),
5150 else if (bytes > 8 /* move up to 16 bytes at a time */
5156 move_bytes = (bytes > 16) ? 16 : bytes;
5157 emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode,
5160 expand_block_move_mem (BLKmode,
5163 GEN_INT (move_bytes),
5166 else if (bytes >= 8 && TARGET_POWERPC64
5167 /* 64-bit loads and stores require word-aligned
5169 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
5172 tmp_reg = gen_reg_rtx (DImode);
5173 emit_move_insn (tmp_reg,
5174 expand_block_move_mem (DImode,
5175 src_reg, orig_src));
5176 emit_move_insn (expand_block_move_mem (DImode,
5177 dest_reg, orig_dest),
5180 else if (bytes > 4 && !TARGET_POWERPC64)
5181 { /* move up to 8 bytes at a time */
5182 move_bytes = (bytes > 8) ? 8 : bytes;
5183 emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
5186 expand_block_move_mem (BLKmode,
5189 GEN_INT (move_bytes),
5192 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
5193 { /* move 4 bytes */
5195 tmp_reg = gen_reg_rtx (SImode);
5196 emit_move_insn (tmp_reg,
5197 expand_block_move_mem (SImode,
5198 src_reg, orig_src));
5199 emit_move_insn (expand_block_move_mem (SImode,
5200 dest_reg, orig_dest),
5203 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
5204 { /* move 2 bytes */
5206 tmp_reg = gen_reg_rtx (HImode);
5207 emit_move_insn (tmp_reg,
5208 expand_block_move_mem (HImode,
5209 src_reg, orig_src));
5210 emit_move_insn (expand_block_move_mem (HImode,
5211 dest_reg, orig_dest),
5214 else if (bytes == 1) /* move 1 byte */
5217 tmp_reg = gen_reg_rtx (QImode);
5218 emit_move_insn (tmp_reg,
5219 expand_block_move_mem (QImode,
5220 src_reg, orig_src));
5221 emit_move_insn (expand_block_move_mem (QImode,
5222 dest_reg, orig_dest),
5226 { /* move up to 4 bytes at a time */
5227 move_bytes = (bytes > 4) ? 4 : bytes;
5228 emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode,
5231 expand_block_move_mem (BLKmode,
5234 GEN_INT (move_bytes),
5238 if (bytes > move_bytes)
5240 if (! TARGET_POWERPC64)
5242 emit_insn (gen_addsi3 (src_reg, src_reg,
5243 GEN_INT (move_bytes)));
5244 emit_insn (gen_addsi3 (dest_reg, dest_reg,
5245 GEN_INT (move_bytes)));
5249 emit_insn (gen_adddi3 (src_reg, src_reg,
5250 GEN_INT (move_bytes)));
5251 emit_insn (gen_adddi3 (dest_reg, dest_reg,
5252 GEN_INT (move_bytes)));
5258 else /* string instructions not available */
5260 num_reg = offset = 0;
5261 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
5263 /* Calculate the correct offset for src/dest */
5267 dest_addr = dest_reg;
5271 src_addr = plus_constant (src_reg, offset);
5272 dest_addr = plus_constant (dest_reg, offset);
5275 /* Generate the appropriate load and store, saving the stores
5277 if (bytes >= 8 && TARGET_POWERPC64
5278 /* 64-bit loads and stores require word-aligned
5280 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
5283 tmp_reg = gen_reg_rtx (DImode);
5284 emit_insn (gen_movdi (tmp_reg,
5285 expand_block_move_mem (DImode,
5288 stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode,
5293 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
5296 tmp_reg = gen_reg_rtx (SImode);
5297 emit_insn (gen_movsi (tmp_reg,
5298 expand_block_move_mem (SImode,
5301 stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode,
5306 else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT))
5309 tmp_reg = gen_reg_rtx (HImode);
5310 emit_insn (gen_movhi (tmp_reg,
5311 expand_block_move_mem (HImode,
5314 stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode,
5322 tmp_reg = gen_reg_rtx (QImode);
5323 emit_insn (gen_movqi (tmp_reg,
5324 expand_block_move_mem (QImode,
5327 stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode,
5333 if (num_reg >= MAX_MOVE_REG)
5335 for (i = 0; i < num_reg; i++)
5336 emit_insn (stores[i]);
5341 for (i = 0; i < num_reg; i++)
5342 emit_insn (stores[i]);
5349 /* Return 1 if OP is a load multiple operation. It is known to be a
5350 PARALLEL and the first section will be tested. */
5353 load_multiple_operation (op, mode)
5355 enum machine_mode mode ATTRIBUTE_UNUSED;
5357 int count = XVECLEN (op, 0);
5358 unsigned int dest_regno;
5362 /* Perform a quick check so we don't blow up below. */
5364 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5365 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
5366 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
5369 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
5370 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
5372 for (i = 1; i < count; i++)
5374 rtx elt = XVECEXP (op, 0, i);
5376 if (GET_CODE (elt) != SET
5377 || GET_CODE (SET_DEST (elt)) != REG
5378 || GET_MODE (SET_DEST (elt)) != SImode
5379 || REGNO (SET_DEST (elt)) != dest_regno + i
5380 || GET_CODE (SET_SRC (elt)) != MEM
5381 || GET_MODE (SET_SRC (elt)) != SImode
5382 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5383 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5384 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5385 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
5392 /* Similar, but tests for store multiple. Here, the second vector element
5393 is a CLOBBER. It will be tested later. */
5396 store_multiple_operation (op, mode)
5398 enum machine_mode mode ATTRIBUTE_UNUSED;
5400 int count = XVECLEN (op, 0) - 1;
5401 unsigned int src_regno;
5405 /* Perform a quick check so we don't blow up below. */
5407 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5408 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
5409 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
5412 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
5413 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
5415 for (i = 1; i < count; i++)
5417 rtx elt = XVECEXP (op, 0, i + 1);
5419 if (GET_CODE (elt) != SET
5420 || GET_CODE (SET_SRC (elt)) != REG
5421 || GET_MODE (SET_SRC (elt)) != SImode
5422 || REGNO (SET_SRC (elt)) != src_regno + i
5423 || GET_CODE (SET_DEST (elt)) != MEM
5424 || GET_MODE (SET_DEST (elt)) != SImode
5425 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5426 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5427 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5428 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
5435 /* Return 1 for a parallel vrsave operation. */
5438 vrsave_operation (op, mode)
5440 enum machine_mode mode ATTRIBUTE_UNUSED;
5442 int count = XVECLEN (op, 0);
5443 unsigned int dest_regno, src_regno;
5447 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5448 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
5449 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
5452 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
5453 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
5455 if (dest_regno != VRSAVE_REGNO
5456 && src_regno != VRSAVE_REGNO)
5459 for (i = 1; i < count; i++)
5461 rtx elt = XVECEXP (op, 0, i);
5463 if (GET_CODE (elt) != CLOBBER
5464 && GET_CODE (elt) != SET)
5471 /* Return 1 for an PARALLEL suitable for mtcrf. */
5474 mtcrf_operation (op, mode)
5476 enum machine_mode mode ATTRIBUTE_UNUSED;
5478 int count = XVECLEN (op, 0);
5482 /* Perform a quick check so we don't blow up below. */
5484 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5485 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
5486 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
5488 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
5490 if (GET_CODE (src_reg) != REG
5491 || GET_MODE (src_reg) != SImode
5492 || ! INT_REGNO_P (REGNO (src_reg)))
5495 for (i = 0; i < count; i++)
5497 rtx exp = XVECEXP (op, 0, i);
5501 if (GET_CODE (exp) != SET
5502 || GET_CODE (SET_DEST (exp)) != REG
5503 || GET_MODE (SET_DEST (exp)) != CCmode
5504 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
5506 unspec = SET_SRC (exp);
5507 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
5509 if (GET_CODE (unspec) != UNSPEC
5510 || XINT (unspec, 1) != 20
5511 || XVECLEN (unspec, 0) != 2
5512 || XVECEXP (unspec, 0, 0) != src_reg
5513 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
5514 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
5520 /* Return 1 for an PARALLEL suitable for lmw. */
5523 lmw_operation (op, mode)
5525 enum machine_mode mode ATTRIBUTE_UNUSED;
5527 int count = XVECLEN (op, 0);
5528 unsigned int dest_regno;
5530 unsigned int base_regno;
5531 HOST_WIDE_INT offset;
5534 /* Perform a quick check so we don't blow up below. */
5536 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5537 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
5538 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
5541 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
5542 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
5545 || count != 32 - (int) dest_regno)
5548 if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0))
5551 base_regno = REGNO (src_addr);
5552 if (base_regno == 0)
5555 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0))
5557 offset = INTVAL (XEXP (src_addr, 1));
5558 base_regno = REGNO (XEXP (src_addr, 0));
5563 for (i = 0; i < count; i++)
5565 rtx elt = XVECEXP (op, 0, i);
5568 HOST_WIDE_INT newoffset;
5570 if (GET_CODE (elt) != SET
5571 || GET_CODE (SET_DEST (elt)) != REG
5572 || GET_MODE (SET_DEST (elt)) != SImode
5573 || REGNO (SET_DEST (elt)) != dest_regno + i
5574 || GET_CODE (SET_SRC (elt)) != MEM
5575 || GET_MODE (SET_SRC (elt)) != SImode)
5577 newaddr = XEXP (SET_SRC (elt), 0);
5578 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
5583 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
5585 addr_reg = XEXP (newaddr, 0);
5586 newoffset = INTVAL (XEXP (newaddr, 1));
5590 if (REGNO (addr_reg) != base_regno
5591 || newoffset != offset + 4 * i)
5598 /* Return 1 for an PARALLEL suitable for stmw. */
5601 stmw_operation (op, mode)
5603 enum machine_mode mode ATTRIBUTE_UNUSED;
5605 int count = XVECLEN (op, 0);
5606 unsigned int src_regno;
5608 unsigned int base_regno;
5609 HOST_WIDE_INT offset;
5612 /* Perform a quick check so we don't blow up below. */
5614 || GET_CODE (XVECEXP (op, 0, 0)) != SET
5615 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
5616 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
5619 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
5620 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
5623 || count != 32 - (int) src_regno)
5626 if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0))
5629 base_regno = REGNO (dest_addr);
5630 if (base_regno == 0)
5633 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0))
5635 offset = INTVAL (XEXP (dest_addr, 1));
5636 base_regno = REGNO (XEXP (dest_addr, 0));
5641 for (i = 0; i < count; i++)
5643 rtx elt = XVECEXP (op, 0, i);
5646 HOST_WIDE_INT newoffset;
5648 if (GET_CODE (elt) != SET
5649 || GET_CODE (SET_SRC (elt)) != REG
5650 || GET_MODE (SET_SRC (elt)) != SImode
5651 || REGNO (SET_SRC (elt)) != src_regno + i
5652 || GET_CODE (SET_DEST (elt)) != MEM
5653 || GET_MODE (SET_DEST (elt)) != SImode)
5655 newaddr = XEXP (SET_DEST (elt), 0);
5656 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
5661 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
5663 addr_reg = XEXP (newaddr, 0);
5664 newoffset = INTVAL (XEXP (newaddr, 1));
5668 if (REGNO (addr_reg) != base_regno
5669 || newoffset != offset + 4 * i)
5676 /* A validation routine: say whether CODE, a condition code, and MODE
5677 match. The other alternatives either don't make sense or should
5678 never be generated. */
5681 validate_condition_mode (code, mode)
5683 enum machine_mode mode;
5685 if (GET_RTX_CLASS (code) != '<'
5686 || GET_MODE_CLASS (mode) != MODE_CC)
5689 /* These don't make sense. */
5690 if ((code == GT || code == LT || code == GE || code == LE)
5691 && mode == CCUNSmode)
5694 if ((code == GTU || code == LTU || code == GEU || code == LEU)
5695 && mode != CCUNSmode)
5698 if (mode != CCFPmode
5699 && (code == ORDERED || code == UNORDERED
5700 || code == UNEQ || code == LTGT
5701 || code == UNGT || code == UNLT
5702 || code == UNGE || code == UNLE))
5705 /* These should never be generated except for
5706 flag_unsafe_math_optimizations. */
5707 if (mode == CCFPmode
5708 && ! flag_unsafe_math_optimizations
5709 && (code == LE || code == GE
5710 || code == UNEQ || code == LTGT
5711 || code == UNGT || code == UNLT))
5714 /* These are invalid; the information is not there. */
5715 if (mode == CCEQmode
5716 && code != EQ && code != NE)
5720 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
5721 We only check the opcode against the mode of the CC value here. */
5724 branch_comparison_operator (op, mode)
5726 enum machine_mode mode ATTRIBUTE_UNUSED;
5728 enum rtx_code code = GET_CODE (op);
5729 enum machine_mode cc_mode;
5731 if (GET_RTX_CLASS (code) != '<')
5734 cc_mode = GET_MODE (XEXP (op, 0));
5735 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
5738 validate_condition_mode (code, cc_mode);
5743 /* Return 1 if OP is a comparison operation that is valid for a branch
5744 insn and which is true if the corresponding bit in the CC register
5748 branch_positive_comparison_operator (op, mode)
5750 enum machine_mode mode;
5754 if (! branch_comparison_operator (op, mode))
5757 code = GET_CODE (op);
5758 return (code == EQ || code == LT || code == GT
5759 || code == LTU || code == GTU
5760 || code == UNORDERED);
5763 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
5764 We check the opcode against the mode of the CC value and disallow EQ or
5765 NE comparisons for integers. */
5768 scc_comparison_operator (op, mode)
5770 enum machine_mode mode;
5772 enum rtx_code code = GET_CODE (op);
5773 enum machine_mode cc_mode;
5775 if (GET_MODE (op) != mode && mode != VOIDmode)
5778 if (GET_RTX_CLASS (code) != '<')
5781 cc_mode = GET_MODE (XEXP (op, 0));
5782 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
5785 validate_condition_mode (code, cc_mode);
5787 if (code == NE && cc_mode != CCFPmode)
5794 trap_comparison_operator (op, mode)
5796 enum machine_mode mode;
5798 if (mode != VOIDmode && mode != GET_MODE (op))
5800 return GET_RTX_CLASS (GET_CODE (op)) == '<';
5804 boolean_operator (op, mode)
5806 enum machine_mode mode ATTRIBUTE_UNUSED;
5808 enum rtx_code code = GET_CODE (op);
5809 return (code == AND || code == IOR || code == XOR);
5813 boolean_or_operator (op, mode)
5815 enum machine_mode mode ATTRIBUTE_UNUSED;
5817 enum rtx_code code = GET_CODE (op);
5818 return (code == IOR || code == XOR);
5822 min_max_operator (op, mode)
5824 enum machine_mode mode ATTRIBUTE_UNUSED;
5826 enum rtx_code code = GET_CODE (op);
5827 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
5830 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
5831 mask required to convert the result of a rotate insn into a shift
5832 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
5835 includes_lshift_p (shiftop, andop)
5839 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
5841 shift_mask <<= INTVAL (shiftop);
5843 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
5846 /* Similar, but for right shift. */
5849 includes_rshift_p (shiftop, andop)
5853 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
5855 shift_mask >>= INTVAL (shiftop);
5857 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
5860 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
5861 to perform a left shift. It must have exactly SHIFTOP least
5862 signifigant 0's, then one or more 1's, then zero or more 0's. */
5865 includes_rldic_lshift_p (shiftop, andop)
5869 if (GET_CODE (andop) == CONST_INT)
5871 HOST_WIDE_INT c, lsb, shift_mask;
5874 if (c == 0 || c == ~0)
5878 shift_mask <<= INTVAL (shiftop);
5880 /* Find the least signifigant one bit. */
5883 /* It must coincide with the LSB of the shift mask. */
5884 if (-lsb != shift_mask)
5887 /* Invert to look for the next transition (if any). */
5890 /* Remove the low group of ones (originally low group of zeros). */
5893 /* Again find the lsb, and check we have all 1's above. */
5897 else if (GET_CODE (andop) == CONST_DOUBLE
5898 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
5900 HOST_WIDE_INT low, high, lsb;
5901 HOST_WIDE_INT shift_mask_low, shift_mask_high;
5903 low = CONST_DOUBLE_LOW (andop);
5904 if (HOST_BITS_PER_WIDE_INT < 64)
5905 high = CONST_DOUBLE_HIGH (andop);
5907 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
5908 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
5911 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
5913 shift_mask_high = ~0;
5914 if (INTVAL (shiftop) > 32)
5915 shift_mask_high <<= INTVAL (shiftop) - 32;
5919 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
5926 return high == -lsb;
5929 shift_mask_low = ~0;
5930 shift_mask_low <<= INTVAL (shiftop);
5934 if (-lsb != shift_mask_low)
5937 if (HOST_BITS_PER_WIDE_INT < 64)
5942 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
5945 return high == -lsb;
5949 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
5955 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
5956 to perform a left shift. It must have SHIFTOP or more least
5957 signifigant 0's, with the remainder of the word 1's. */
5960 includes_rldicr_lshift_p (shiftop, andop)
5964 if (GET_CODE (andop) == CONST_INT)
5966 HOST_WIDE_INT c, lsb, shift_mask;
5969 shift_mask <<= INTVAL (shiftop);
5972 /* Find the least signifigant one bit. */
5975 /* It must be covered by the shift mask.
5976 This test also rejects c == 0. */
5977 if ((lsb & shift_mask) == 0)
5980 /* Check we have all 1's above the transition, and reject all 1's. */
5981 return c == -lsb && lsb != 1;
5983 else if (GET_CODE (andop) == CONST_DOUBLE
5984 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
5986 HOST_WIDE_INT low, lsb, shift_mask_low;
5988 low = CONST_DOUBLE_LOW (andop);
5990 if (HOST_BITS_PER_WIDE_INT < 64)
5992 HOST_WIDE_INT high, shift_mask_high;
5994 high = CONST_DOUBLE_HIGH (andop);
5998 shift_mask_high = ~0;
5999 if (INTVAL (shiftop) > 32)
6000 shift_mask_high <<= INTVAL (shiftop) - 32;
6004 if ((lsb & shift_mask_high) == 0)
6007 return high == -lsb;
6013 shift_mask_low = ~0;
6014 shift_mask_low <<= INTVAL (shiftop);
6018 if ((lsb & shift_mask_low) == 0)
6021 return low == -lsb && lsb != 1;
6027 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
6028 for lfq and stfq insns.
6030 Note reg1 and reg2 *must* be hard registers. To be sure we will
6031 abort if we are passed pseudo registers. */
6034 registers_ok_for_quad_peep (reg1, reg2)
6037 /* We might have been passed a SUBREG. */
6038 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6041 return (REGNO (reg1) == REGNO (reg2) - 1);
6044 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
6045 addr1 and addr2 must be in consecutive memory locations
6046 (addr2 == addr1 + 8). */
6049 addrs_ok_for_quad_peep (addr1, addr2)
6056 /* Extract an offset (if used) from the first addr. */
6057 if (GET_CODE (addr1) == PLUS)
6059 /* If not a REG, return zero. */
6060 if (GET_CODE (XEXP (addr1, 0)) != REG)
6064 reg1 = REGNO (XEXP (addr1, 0));
6065 /* The offset must be constant! */
6066 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6068 offset1 = INTVAL (XEXP (addr1, 1));
6071 else if (GET_CODE (addr1) != REG)
6075 reg1 = REGNO (addr1);
6076 /* This was a simple (mem (reg)) expression. Offset is 0. */
6080 /* Make sure the second address is a (mem (plus (reg) (const_int))). */
6081 if (GET_CODE (addr2) != PLUS)
6084 if (GET_CODE (XEXP (addr2, 0)) != REG
6085 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6088 if (reg1 != REGNO (XEXP (addr2, 0)))
6091 /* The offset for the second addr must be 8 more than the first addr. */
6092 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
6095 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
6100 /* Return the register class of a scratch register needed to copy IN into
6101 or out of a register in CLASS in MODE. If it can be done directly,
6102 NO_REGS is returned. */
6105 secondary_reload_class (class, mode, in)
6106 enum reg_class class;
6107 enum machine_mode mode ATTRIBUTE_UNUSED;
6112 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic))
6114 /* We cannot copy a symbolic operand directly into anything
6115 other than BASE_REGS for TARGET_ELF. So indicate that a
6116 register from BASE_REGS is needed as an intermediate
6119 On Darwin, pic addresses require a load from memory, which
6120 needs a base register. */
6121 if (class != BASE_REGS
6122 && (GET_CODE (in) == SYMBOL_REF
6123 || GET_CODE (in) == HIGH
6124 || GET_CODE (in) == LABEL_REF
6125 || GET_CODE (in) == CONST))
6129 if (GET_CODE (in) == REG)
6132 if (regno >= FIRST_PSEUDO_REGISTER)
6134 regno = true_regnum (in);
6135 if (regno >= FIRST_PSEUDO_REGISTER)
6139 else if (GET_CODE (in) == SUBREG)
6141 regno = true_regnum (in);
6142 if (regno >= FIRST_PSEUDO_REGISTER)
6148 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
6150 if (class == GENERAL_REGS || class == BASE_REGS
6151 || (regno >= 0 && INT_REGNO_P (regno)))
6154 /* Constants, memory, and FP registers can go into FP registers. */
6155 if ((regno == -1 || FP_REGNO_P (regno))
6156 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
6159 /* Memory, and AltiVec registers can go into AltiVec registers. */
6160 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
6161 && class == ALTIVEC_REGS)
6164 /* We can copy among the CR registers. */
6165 if ((class == CR_REGS || class == CR0_REGS)
6166 && regno >= 0 && CR_REGNO_P (regno))
6169 /* Otherwise, we need GENERAL_REGS. */
6170 return GENERAL_REGS;
6173 /* Given a comparison operation, return the bit number in CCR to test. We
6174 know this is a valid comparison.
6176 SCC_P is 1 if this is for an scc. That means that %D will have been
6177 used instead of %C, so the bits will be in different places.
6179 Return -1 if OP isn't a valid comparison for some reason. */
6186 enum rtx_code code = GET_CODE (op);
6187 enum machine_mode cc_mode;
6192 if (GET_RTX_CLASS (code) != '<')
6197 if (GET_CODE (reg) != REG
6198 || ! CR_REGNO_P (REGNO (reg)))
6201 cc_mode = GET_MODE (reg);
6202 cc_regnum = REGNO (reg);
6203 base_bit = 4 * (cc_regnum - CR0_REGNO);
6205 validate_condition_mode (code, cc_mode);
6210 return scc_p ? base_bit + 3 : base_bit + 2;
6212 return base_bit + 2;
6213 case GT: case GTU: case UNLE:
6214 return base_bit + 1;
6215 case LT: case LTU: case UNGE:
6217 case ORDERED: case UNORDERED:
6218 return base_bit + 3;
6221 /* If scc, we will have done a cror to put the bit in the
6222 unordered position. So test that bit. For integer, this is ! LT
6223 unless this is an scc insn. */
6224 return scc_p ? base_bit + 3 : base_bit;
6227 return scc_p ? base_bit + 3 : base_bit + 1;
6234 /* Return the GOT register. */
6237 rs6000_got_register (value)
6238 rtx value ATTRIBUTE_UNUSED;
6240 /* The second flow pass currently (June 1999) can't update
6241 regs_ever_live without disturbing other parts of the compiler, so
6242 update it here to make the prolog/epilogue code happy. */
6243 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
6244 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6246 current_function_uses_pic_offset_table = 1;
6248 return pic_offset_table_rtx;
6251 /* Functions to init, mark and free struct machine_function.
6252 These will be called, via pointer variables,
6253 from push_function_context and pop_function_context. */
6256 rs6000_init_machine_status (p)
6259 p->machine = (machine_function *) xcalloc (1, sizeof (machine_function));
6263 rs6000_free_machine_status (p)
6266 if (p->machine == NULL)
6274 /* Print an operand. Recognize special options, documented below. */
6277 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
6278 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
6280 #define SMALL_DATA_RELOC "sda21"
6281 #define SMALL_DATA_REG 0
6285 print_operand (file, x, code)
6293 /* These macros test for integers and extract the low-order bits. */
6295 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
6296 && GET_MODE (X) == VOIDmode)
6298 #define INT_LOWPART(X) \
6299 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
6304 /* Write out an instruction after the call which may be replaced
6305 with glue code by the loader. This depends on the AIX version. */
6306 asm_fprintf (file, RS6000_CALL_GLUE);
6309 /* %a is output_address. */
6312 /* If X is a constant integer whose low-order 5 bits are zero,
6313 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
6314 in the AIX assembler where "sri" with a zero shift count
6315 writes a trash instruction. */
6316 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
6323 /* If constant, low-order 16 bits of constant, unsigned.
6324 Otherwise, write normally. */
6326 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
6328 print_operand (file, x, 0);
6332 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
6333 for 64-bit mask direction. */
6334 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
6337 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
6341 /* There used to be a comment for 'C' reading "This is an
6342 optional cror needed for certain floating-point
6343 comparisons. Otherwise write nothing." */
6345 /* Similar, except that this is for an scc, so we must be able to
6346 encode the test in a single bit that is one. We do the above
6347 for any LE, GE, GEU, or LEU and invert the bit for NE. */
6348 if (GET_CODE (x) == LE || GET_CODE (x) == GE
6349 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
6351 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
6353 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
6355 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
6358 else if (GET_CODE (x) == NE)
6360 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
6362 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
6363 base_bit + 2, base_bit + 2);
6368 /* X is a CR register. Print the number of the EQ bit of the CR */
6369 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
6370 output_operand_lossage ("invalid %%E value");
6372 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
6376 /* X is a CR register. Print the shift count needed to move it
6377 to the high-order four bits. */
6378 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
6379 output_operand_lossage ("invalid %%f value");
6381 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
6385 /* Similar, but print the count for the rotate in the opposite
6387 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
6388 output_operand_lossage ("invalid %%F value");
6390 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
6394 /* X is a constant integer. If it is negative, print "m",
6395 otherwise print "z". This is to make a aze or ame insn. */
6396 if (GET_CODE (x) != CONST_INT)
6397 output_operand_lossage ("invalid %%G value");
6398 else if (INTVAL (x) >= 0)
6405 /* If constant, output low-order five bits. Otherwise, write
6408 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
6410 print_operand (file, x, 0);
6414 /* If constant, output low-order six bits. Otherwise, write
6417 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
6419 print_operand (file, x, 0);
6423 /* Print `i' if this is a constant, else nothing. */
6429 /* Write the bit number in CCR for jump. */
6432 output_operand_lossage ("invalid %%j code");
6434 fprintf (file, "%d", i);
6438 /* Similar, but add one for shift count in rlinm for scc and pass
6439 scc flag to `ccr_bit'. */
6442 output_operand_lossage ("invalid %%J code");
6444 /* If we want bit 31, write a shift count of zero, not 32. */
6445 fprintf (file, "%d", i == 31 ? 0 : i + 1);
6449 /* X must be a constant. Write the 1's complement of the
6452 output_operand_lossage ("invalid %%k value");
6454 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
6458 /* X must be a symbolic constant on ELF. Write an
6459 expression suitable for an 'addi' that adds in the low 16
6461 if (GET_CODE (x) != CONST)
6463 print_operand_address (file, x);
6468 if (GET_CODE (XEXP (x, 0)) != PLUS
6469 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
6470 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
6471 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
6472 output_operand_lossage ("invalid %%K value");
6473 print_operand_address (file, XEXP (XEXP (x, 0), 0));
6475 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
6479 /* %l is output_asm_label. */
6482 /* Write second word of DImode or DFmode reference. Works on register
6483 or non-indexed memory only. */
6484 if (GET_CODE (x) == REG)
6485 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
6486 else if (GET_CODE (x) == MEM)
6488 /* Handle possible auto-increment. Since it is pre-increment and
6489 we have already done it, we can just use an offset of word. */
6490 if (GET_CODE (XEXP (x, 0)) == PRE_INC
6491 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
6492 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
6495 output_address (XEXP (adjust_address_nv (x, SImode,
6499 if (small_data_operand (x, GET_MODE (x)))
6500 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
6501 reg_names[SMALL_DATA_REG]);
6506 /* MB value for a mask operand. */
6507 if (! mask_operand (x, SImode))
6508 output_operand_lossage ("invalid %%m value");
6510 val = INT_LOWPART (x);
6512 /* If the high bit is set and the low bit is not, the value is zero.
6513 If the high bit is zero, the value is the first 1 bit we find from
6515 if ((val & 0x80000000) && ((val & 1) == 0))
6520 else if ((val & 0x80000000) == 0)
6522 for (i = 1; i < 32; i++)
6523 if ((val <<= 1) & 0x80000000)
6525 fprintf (file, "%d", i);
6529 /* Otherwise, look for the first 0 bit from the right. The result is its
6530 number plus 1. We know the low-order bit is one. */
6531 for (i = 0; i < 32; i++)
6532 if (((val >>= 1) & 1) == 0)
6535 /* If we ended in ...01, i would be 0. The correct value is 31, so
6537 fprintf (file, "%d", 31 - i);
6541 /* ME value for a mask operand. */
6542 if (! mask_operand (x, SImode))
6543 output_operand_lossage ("invalid %%M value");
6545 val = INT_LOWPART (x);
6547 /* If the low bit is set and the high bit is not, the value is 31.
6548 If the low bit is zero, the value is the first 1 bit we find from
6550 if ((val & 1) && ((val & 0x80000000) == 0))
6555 else if ((val & 1) == 0)
6557 for (i = 0; i < 32; i++)
6558 if ((val >>= 1) & 1)
6561 /* If we had ....10, i would be 0. The result should be
6562 30, so we need 30 - i. */
6563 fprintf (file, "%d", 30 - i);
6567 /* Otherwise, look for the first 0 bit from the left. The result is its
6568 number minus 1. We know the high-order bit is one. */
6569 for (i = 0; i < 32; i++)
6570 if (((val <<= 1) & 0x80000000) == 0)
6573 fprintf (file, "%d", i);
6576 /* %n outputs the negative of its operand. */
6579 /* Write the number of elements in the vector times 4. */
6580 if (GET_CODE (x) != PARALLEL)
6581 output_operand_lossage ("invalid %%N value");
6583 fprintf (file, "%d", XVECLEN (x, 0) * 4);
6587 /* Similar, but subtract 1 first. */
6588 if (GET_CODE (x) != PARALLEL)
6589 output_operand_lossage ("invalid %%O value");
6591 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
6595 /* X is a CONST_INT that is a power of two. Output the logarithm. */
6597 || INT_LOWPART (x) < 0
6598 || (i = exact_log2 (INT_LOWPART (x))) < 0)
6599 output_operand_lossage ("invalid %%p value");
6601 fprintf (file, "%d", i);
6605 /* The operand must be an indirect memory reference. The result
6606 is the register number. */
6607 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
6608 || REGNO (XEXP (x, 0)) >= 32)
6609 output_operand_lossage ("invalid %%P value");
6611 fprintf (file, "%d", REGNO (XEXP (x, 0)));
6615 /* This outputs the logical code corresponding to a boolean
6616 expression. The expression may have one or both operands
6617 negated (if one, only the first one). For condition register
6618 logical operations, it will also treat the negated
6619 CR codes as NOTs, but not handle NOTs of them. */
6621 const char *const *t = 0;
6623 enum rtx_code code = GET_CODE (x);
6624 static const char * const tbl[3][3] = {
6625 { "and", "andc", "nor" },
6626 { "or", "orc", "nand" },
6627 { "xor", "eqv", "xor" } };
6631 else if (code == IOR)
6633 else if (code == XOR)
6636 output_operand_lossage ("invalid %%q value");
6638 if (GET_CODE (XEXP (x, 0)) != NOT)
6642 if (GET_CODE (XEXP (x, 1)) == NOT)
6653 /* X is a CR register. Print the mask for `mtcrf'. */
6654 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
6655 output_operand_lossage ("invalid %%R value");
6657 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
6661 /* Low 5 bits of 32 - value */
6663 output_operand_lossage ("invalid %%s value");
6665 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
6669 /* PowerPC64 mask position. All 0's and all 1's are excluded.
6670 CONST_INT 32-bit mask is considered sign-extended so any
6671 transition must occur within the CONST_INT, not on the boundary. */
6672 if (! mask64_operand (x, DImode))
6673 output_operand_lossage ("invalid %%S value");
6675 val = INT_LOWPART (x);
6677 if (val & 1) /* Clear Left */
6679 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
6680 if (!((val >>= 1) & 1))
6683 #if HOST_BITS_PER_WIDE_INT == 32
6684 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
6686 val = CONST_DOUBLE_HIGH (x);
6691 for (i = 32; i < 64; i++)
6692 if (!((val >>= 1) & 1))
6696 /* i = index of last set bit from right
6697 mask begins at 63 - i from left */
6699 output_operand_lossage ("%%S computed all 1's mask");
6701 fprintf (file, "%d", 63 - i);
6704 else /* Clear Right */
6706 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
6707 if ((val >>= 1) & 1)
6710 #if HOST_BITS_PER_WIDE_INT == 32
6711 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
6713 val = CONST_DOUBLE_HIGH (x);
6715 if (val == (HOST_WIDE_INT) -1)
6718 for (i = 32; i < 64; i++)
6719 if ((val >>= 1) & 1)
6723 /* i = index of last clear bit from right
6724 mask ends at 62 - i from left */
6726 output_operand_lossage ("%%S computed all 0's mask");
6728 fprintf (file, "%d", 62 - i);
6733 /* Print the symbolic name of a branch target register. */
6734 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
6735 && REGNO (x) != COUNT_REGISTER_REGNUM))
6736 output_operand_lossage ("invalid %%T value");
6737 else if (REGNO (x) == LINK_REGISTER_REGNUM)
6738 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
6740 fputs ("ctr", file);
6744 /* High-order 16 bits of constant for use in unsigned operand. */
6746 output_operand_lossage ("invalid %%u value");
6748 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
6749 (INT_LOWPART (x) >> 16) & 0xffff);
6753 /* High-order 16 bits of constant for use in signed operand. */
6755 output_operand_lossage ("invalid %%v value");
6757 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
6758 (INT_LOWPART (x) >> 16) & 0xffff);
6762 /* Print `u' if this has an auto-increment or auto-decrement. */
6763 if (GET_CODE (x) == MEM
6764 && (GET_CODE (XEXP (x, 0)) == PRE_INC
6765 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
6770 /* Print the trap code for this operand. */
6771 switch (GET_CODE (x))
6774 fputs ("eq", file); /* 4 */
6777 fputs ("ne", file); /* 24 */
6780 fputs ("lt", file); /* 16 */
6783 fputs ("le", file); /* 20 */
6786 fputs ("gt", file); /* 8 */
6789 fputs ("ge", file); /* 12 */
6792 fputs ("llt", file); /* 2 */
6795 fputs ("lle", file); /* 6 */
6798 fputs ("lgt", file); /* 1 */
6801 fputs ("lge", file); /* 5 */
6809 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
6812 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6813 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
6815 print_operand (file, x, 0);
6819 /* MB value for a PowerPC64 rldic operand. */
6820 val = (GET_CODE (x) == CONST_INT
6821 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
6826 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
6827 if ((val <<= 1) < 0)
6830 #if HOST_BITS_PER_WIDE_INT == 32
6831 if (GET_CODE (x) == CONST_INT && i >= 0)
6832 i += 32; /* zero-extend high-part was all 0's */
6833 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
6835 val = CONST_DOUBLE_LOW (x);
6842 for ( ; i < 64; i++)
6843 if ((val <<= 1) < 0)
6848 fprintf (file, "%d", i + 1);
6852 if (GET_CODE (x) == MEM
6853 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0))
6858 /* Like 'L', for third word of TImode */
6859 if (GET_CODE (x) == REG)
6860 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
6861 else if (GET_CODE (x) == MEM)
6863 if (GET_CODE (XEXP (x, 0)) == PRE_INC
6864 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
6865 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
6867 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
6868 if (small_data_operand (x, GET_MODE (x)))
6869 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
6870 reg_names[SMALL_DATA_REG]);
6875 /* X is a SYMBOL_REF. Write out the name preceded by a
6876 period and without any trailing data in brackets. Used for function
6877 names. If we are configured for System V (or the embedded ABI) on
6878 the PowerPC, do not emit the period, since those systems do not use
6879 TOCs and the like. */
6880 if (GET_CODE (x) != SYMBOL_REF)
6883 if (XSTR (x, 0)[0] != '.')
6885 switch (DEFAULT_ABI)
6895 case ABI_AIX_NODESC:
6901 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
6903 assemble_name (file, XSTR (x, 0));
6908 /* Like 'L', for last word of TImode. */
6909 if (GET_CODE (x) == REG)
6910 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
6911 else if (GET_CODE (x) == MEM)
6913 if (GET_CODE (XEXP (x, 0)) == PRE_INC
6914 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
6915 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
6917 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
6918 if (small_data_operand (x, GET_MODE (x)))
6919 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
6920 reg_names[SMALL_DATA_REG]);
6924 /* Print AltiVec memory operand. */
6929 if (GET_CODE (x) != MEM)
6934 if (GET_CODE (tmp) == REG)
6935 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
6936 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
6938 if (REGNO (XEXP (tmp, 0)) == 0)
6939 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
6940 reg_names[ REGNO (XEXP (tmp, 0)) ]);
6942 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
6943 reg_names[ REGNO (XEXP (tmp, 1)) ]);
6951 if (GET_CODE (x) == REG)
6952 fprintf (file, "%s", reg_names[REGNO (x)]);
6953 else if (GET_CODE (x) == MEM)
6955 /* We need to handle PRE_INC and PRE_DEC here, since we need to
6956 know the width from the mode. */
6957 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
6958 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
6959 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
6960 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
6961 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
6962 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
6964 output_address (XEXP (x, 0));
6967 output_addr_const (file, x);
6971 output_operand_lossage ("invalid %%xn code");
6975 /* Print the address of an operand. */
6978 print_operand_address (file, x)
6982 if (GET_CODE (x) == REG)
6983 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
6984 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
6985 || GET_CODE (x) == LABEL_REF)
6987 output_addr_const (file, x);
6988 if (small_data_operand (x, GET_MODE (x)))
6989 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
6990 reg_names[SMALL_DATA_REG]);
6991 else if (TARGET_TOC)
6994 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
6996 if (REGNO (XEXP (x, 0)) == 0)
6997 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
6998 reg_names[ REGNO (XEXP (x, 0)) ]);
7000 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
7001 reg_names[ REGNO (XEXP (x, 1)) ]);
7003 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
7005 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
7006 fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
7009 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
7010 && CONSTANT_P (XEXP (x, 1)))
7012 output_addr_const (file, XEXP (x, 1));
7013 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
7017 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
7018 && CONSTANT_P (XEXP (x, 1)))
7020 fprintf (file, "lo16(");
7021 output_addr_const (file, XEXP (x, 1));
7022 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
7025 else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
7027 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
7029 rtx contains_minus = XEXP (x, 1);
7033 /* Find the (minus (sym) (toc)) buried in X, and temporarily
7034 turn it into (sym) for output_addr_const. */
7035 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
7036 contains_minus = XEXP (contains_minus, 0);
7038 minus = XEXP (contains_minus, 0);
7039 symref = XEXP (minus, 0);
7040 XEXP (contains_minus, 0) = symref;
7045 name = XSTR (symref, 0);
7046 newname = alloca (strlen (name) + sizeof ("@toc"));
7047 strcpy (newname, name);
7048 strcat (newname, "@toc");
7049 XSTR (symref, 0) = newname;
7051 output_addr_const (file, XEXP (x, 1));
7053 XSTR (symref, 0) = name;
7054 XEXP (contains_minus, 0) = minus;
7057 output_addr_const (file, XEXP (x, 1));
7059 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
7065 /* Target hook for assembling integer objects. The powerpc version has
7066 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
7067 is defined. It also needs to handle DI-mode objects on 64-bit
7071 rs6000_assemble_integer (x, size, aligned_p)
7076 #ifdef RELOCATABLE_NEEDS_FIXUP
7077 /* Special handling for SI values. */
7078 if (size == 4 && aligned_p)
7080 extern int in_toc_section PARAMS ((void));
7081 static int recurse = 0;
7083 /* For -mrelocatable, we mark all addresses that need to be fixed up
7084 in the .fixup section. */
7085 if (TARGET_RELOCATABLE
7086 && !in_toc_section ()
7087 && !in_text_section ()
7089 && GET_CODE (x) != CONST_INT
7090 && GET_CODE (x) != CONST_DOUBLE
7096 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
7098 ASM_OUTPUT_LABEL (asm_out_file, buf);
7099 fprintf (asm_out_file, "\t.long\t(");
7100 output_addr_const (asm_out_file, x);
7101 fprintf (asm_out_file, ")@fixup\n");
7102 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
7103 ASM_OUTPUT_ALIGN (asm_out_file, 2);
7104 fprintf (asm_out_file, "\t.long\t");
7105 assemble_name (asm_out_file, buf);
7106 fprintf (asm_out_file, "\n\t.previous\n");
7110 /* Remove initial .'s to turn a -mcall-aixdesc function
7111 address into the address of the descriptor, not the function
7113 else if (GET_CODE (x) == SYMBOL_REF
7114 && XSTR (x, 0)[0] == '.'
7115 && DEFAULT_ABI == ABI_AIX)
7117 const char *name = XSTR (x, 0);
7118 while (*name == '.')
7121 fprintf (asm_out_file, "\t.long\t%s\n", name);
7125 #endif /* RELOCATABLE_NEEDS_FIXUP */
7126 return default_assemble_integer (x, size, aligned_p);
7130 rs6000_reverse_condition (mode, code)
7131 enum machine_mode mode;
7134 /* Reversal of FP compares takes care -- an ordered compare
7135 becomes an unordered compare and vice versa. */
7136 if (mode == CCFPmode)
7137 return reverse_condition_maybe_unordered (code);
7139 return reverse_condition (code);
7142 /* Generate a compare for CODE. Return a brand-new rtx that
7143 represents the result of the compare. */
7146 rs6000_generate_compare (code)
7149 enum machine_mode comp_mode;
7152 if (rs6000_compare_fp_p)
7153 comp_mode = CCFPmode;
7154 else if (code == GTU || code == LTU
7155 || code == GEU || code == LEU)
7156 comp_mode = CCUNSmode;
7160 /* First, the compare. */
7161 compare_result = gen_reg_rtx (comp_mode);
7162 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
7163 gen_rtx_COMPARE (comp_mode,
7165 rs6000_compare_op1)));
7167 /* Some kinds of FP comparisons need an OR operation;
7168 except for flag_unsafe_math_optimizations we don't bother. */
7169 if (rs6000_compare_fp_p
7170 && ! flag_unsafe_math_optimizations
7171 && (code == LE || code == GE
7172 || code == UNEQ || code == LTGT
7173 || code == UNGT || code == UNLT))
7175 enum rtx_code or1, or2;
7176 rtx or1_rtx, or2_rtx, compare2_rtx;
7177 rtx or_result = gen_reg_rtx (CCEQmode);
7181 case LE: or1 = LT; or2 = EQ; break;
7182 case GE: or1 = GT; or2 = EQ; break;
7183 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
7184 case LTGT: or1 = LT; or2 = GT; break;
7185 case UNGT: or1 = UNORDERED; or2 = GT; break;
7186 case UNLT: or1 = UNORDERED; or2 = LT; break;
7189 validate_condition_mode (or1, comp_mode);
7190 validate_condition_mode (or2, comp_mode);
7191 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
7192 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
7193 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
7194 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
7196 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
7198 compare_result = or_result;
7202 validate_condition_mode (code, GET_MODE (compare_result));
7204 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
7208 /* Emit the RTL for an sCOND pattern. */
7211 rs6000_emit_sCOND (code, result)
7216 enum machine_mode op_mode;
7218 condition_rtx = rs6000_generate_compare (code);
7220 op_mode = GET_MODE (rs6000_compare_op0);
7221 if (op_mode == VOIDmode)
7222 op_mode = GET_MODE (rs6000_compare_op1);
7224 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
7226 PUT_MODE (condition_rtx, DImode);
7227 convert_move (result, condition_rtx, 0);
7231 PUT_MODE (condition_rtx, SImode);
7232 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
7236 /* Emit a branch of kind CODE to location LOC. */
7239 rs6000_emit_cbranch (code, loc)
7243 rtx condition_rtx, loc_ref;
7245 condition_rtx = rs6000_generate_compare (code);
7246 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
7247 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
7248 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
7252 /* Return the string to output a conditional branch to LABEL, which is
7253 the operand number of the label, or -1 if the branch is really a
7256 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
7257 condition code register and its mode specifies what kind of
7260 REVERSED is non-zero if we should reverse the sense of the comparison.
7262 INSN is the insn. */
7265 output_cbranch (op, label, reversed, insn)
7271 static char string[64];
7272 enum rtx_code code = GET_CODE (op);
7273 rtx cc_reg = XEXP (op, 0);
7274 enum machine_mode mode = GET_MODE (cc_reg);
7275 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
7276 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
7277 int really_reversed = reversed ^ need_longbranch;
7283 validate_condition_mode (code, mode);
7285 /* Work out which way this really branches. We could use
7286 reverse_condition_maybe_unordered here always but this
7287 makes the resulting assembler clearer. */
7288 if (really_reversed)
7289 code = rs6000_reverse_condition (mode, code);
7293 /* Not all of these are actually distinct opcodes, but
7294 we distinguish them for clarity of the resulting assembler. */
7296 ccode = "ne"; break;
7298 ccode = "eq"; break;
7300 ccode = "ge"; break;
7301 case GT: case GTU: case UNGT:
7302 ccode = "gt"; break;
7304 ccode = "le"; break;
7305 case LT: case LTU: case UNLT:
7306 ccode = "lt"; break;
7307 case UNORDERED: ccode = "un"; break;
7308 case ORDERED: ccode = "nu"; break;
7309 case UNGE: ccode = "nl"; break;
7310 case UNLE: ccode = "ng"; break;
7315 /* Maybe we have a guess as to how likely the branch is.
7316 The old mnemonics don't have a way to specify this information. */
7317 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
7318 if (note != NULL_RTX)
7320 /* PROB is the difference from 50%. */
7321 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
7323 /* For branches that are very close to 50%, assume not-taken. */
7324 if (abs (prob) > REG_BR_PROB_BASE / 20
7325 && ((prob > 0) ^ need_longbranch))
7334 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
7336 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
7338 /* We need to escape any '%' characters in the reg_names string.
7339 Assume they'd only be the first character... */
7340 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
7342 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
7346 /* If the branch distance was too far, we may have to use an
7347 unconditional branch to go the distance. */
7348 if (need_longbranch)
7349 s += sprintf (s, ",$+8\n\tb %s", label);
7351 s += sprintf (s, ",%s", label);
7357 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
7358 operands of the last comparison is nonzero/true, FALSE_COND if it
7359 is zero/false. Return 0 if the hardware has no such operation. */
7362 rs6000_emit_cmove (dest, op, true_cond, false_cond)
7368 enum rtx_code code = GET_CODE (op);
7369 rtx op0 = rs6000_compare_op0;
7370 rtx op1 = rs6000_compare_op1;
7372 enum machine_mode compare_mode = GET_MODE (op0);
7373 enum machine_mode result_mode = GET_MODE (dest);
7376 /* These modes should always match. */
7377 if (GET_MODE (op1) != compare_mode)
7379 if (GET_MODE (true_cond) != result_mode)
7381 if (GET_MODE (false_cond) != result_mode)
7384 /* First, work out if the hardware can do this at all, or
7385 if it's too slow... */
7386 /* If the comparison is an integer one, since we only have fsel
7387 it'll be cheaper to use a branch. */
7388 if (! rs6000_compare_fp_p)
7391 /* Eliminate half of the comparisons by switching operands, this
7392 makes the remaining code simpler. */
7393 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
7394 || code == LTGT || code == LT)
7396 code = reverse_condition_maybe_unordered (code);
7398 true_cond = false_cond;
7402 /* UNEQ and LTGT take four instructions for a comparison with zero,
7403 it'll probably be faster to use a branch here too. */
7407 if (GET_CODE (op1) == CONST_DOUBLE)
7408 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
7410 /* We're going to try to implement comparions by performing
7411 a subtract, then comparing against zero. Unfortunately,
7412 Inf - Inf is NaN which is not zero, and so if we don't
7413 know that the the operand is finite and the comparison
7414 would treat EQ different to UNORDERED, we can't do it. */
7415 if (! flag_unsafe_math_optimizations
7416 && code != GT && code != UNGE
7417 && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1))
7418 /* Constructs of the form (a OP b ? a : b) are safe. */
7419 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
7420 || (! rtx_equal_p (op0, true_cond)
7421 && ! rtx_equal_p (op1, true_cond))))
7423 /* At this point we know we can use fsel. */
7425 /* Reduce the comparison to a comparison against zero. */
7426 temp = gen_reg_rtx (compare_mode);
7427 emit_insn (gen_rtx_SET (VOIDmode, temp,
7428 gen_rtx_MINUS (compare_mode, op0, op1)));
7430 op1 = CONST0_RTX (compare_mode);
7432 /* If we don't care about NaNs we can reduce some of the comparisons
7433 down to faster ones. */
7434 if (flag_unsafe_math_optimizations)
7440 true_cond = false_cond;
7453 /* Now, reduce everything down to a GE. */
7460 temp = gen_reg_rtx (compare_mode);
7461 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
7466 temp = gen_reg_rtx (compare_mode);
7467 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
7472 temp = gen_reg_rtx (compare_mode);
7473 emit_insn (gen_rtx_SET (VOIDmode, temp,
7474 gen_rtx_NEG (compare_mode,
7475 gen_rtx_ABS (compare_mode, op0))));
7480 temp = gen_reg_rtx (result_mode);
7481 emit_insn (gen_rtx_SET (VOIDmode, temp,
7482 gen_rtx_IF_THEN_ELSE (result_mode,
7483 gen_rtx_GE (VOIDmode,
7485 true_cond, false_cond)));
7487 true_cond = false_cond;
7489 temp = gen_reg_rtx (compare_mode);
7490 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
7495 temp = gen_reg_rtx (result_mode);
7496 emit_insn (gen_rtx_SET (VOIDmode, temp,
7497 gen_rtx_IF_THEN_ELSE (result_mode,
7498 gen_rtx_GE (VOIDmode,
7500 true_cond, false_cond)));
7502 false_cond = true_cond;
7504 temp = gen_reg_rtx (compare_mode);
7505 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
7513 emit_insn (gen_rtx_SET (VOIDmode, dest,
7514 gen_rtx_IF_THEN_ELSE (result_mode,
7515 gen_rtx_GE (VOIDmode,
7517 true_cond, false_cond)));
7522 rs6000_emit_minmax (dest, code, op0, op1)
7528 enum machine_mode mode = GET_MODE (op0);
7530 if (code == SMAX || code == UMAX)
7531 target = emit_conditional_move (dest, GE, op0, op1, mode,
7534 target = emit_conditional_move (dest, GE, op0, op1, mode,
7536 if (target == NULL_RTX)
7539 emit_move_insn (dest, target);
7542 /* This page contains routines that are used to determine what the
7543 function prologue and epilogue code will do and write them out. */
7545 /* Return the first fixed-point register that is required to be
7546 saved. 32 if none. */
7549 first_reg_to_save ()
7553 /* Find lowest numbered live register. */
7554 for (first_reg = 13; first_reg <= 31; first_reg++)
7555 if (regs_ever_live[first_reg]
7556 && (! call_used_regs[first_reg]
7557 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
7558 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
7559 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
7562 if (current_function_profile)
7564 /* AIX must save/restore every register that contains a parameter
7565 before/after the .__mcount call plus an additional register
7566 for the static chain, if needed; use registers from 30 down to 22
7568 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7570 int last_parm_reg, profile_first_reg;
7572 /* Figure out last used parameter register. The proper thing
7573 to do is to walk incoming args of the function. A function
7574 might have live parameter registers even if it has no
7576 for (last_parm_reg = 10;
7577 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
7581 /* Calculate first reg for saving parameter registers
7583 Skip reg 31 which may contain the frame pointer. */
7584 profile_first_reg = (33 - last_parm_reg
7585 - (current_function_needs_context ? 1 : 0));
7587 /* Need to skip another reg to account for R31 being PICBASE
7588 (when flag_pic is set) or R30 being used as the frame
7589 pointer (when flag_pic is not set). */
7590 --profile_first_reg;
7592 /* Do not save frame pointer if no parameters needs to be saved. */
7593 if (profile_first_reg == 31)
7594 profile_first_reg = 32;
7596 if (first_reg > profile_first_reg)
7597 first_reg = profile_first_reg;
7600 /* SVR4 may need one register to preserve the static chain. */
7601 else if (current_function_needs_context)
7603 /* Skip reg 31 which may contain the frame pointer. */
7610 if (flag_pic && current_function_uses_pic_offset_table &&
7611 (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM))
7612 return RS6000_PIC_OFFSET_TABLE_REGNUM;
7618 /* Similar, for FP regs. */
7621 first_fp_reg_to_save ()
7625 /* Find lowest numbered live register. */
7626 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
7627 if (regs_ever_live[first_reg])
7633 /* Similar, for AltiVec regs. */
7636 first_altivec_reg_to_save ()
7640 /* Stack frame remains as is unless we are in AltiVec ABI. */
7641 if (! TARGET_ALTIVEC_ABI)
7642 return LAST_ALTIVEC_REGNO + 1;
7644 /* Find lowest numbered live register. */
7645 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
7646 if (regs_ever_live[i])
7652 /* Return a 32-bit mask of the AltiVec registers we need to set in
7653 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
7654 the 32-bit word is 0. */
7657 compute_vrsave_mask ()
7659 unsigned int i, mask = 0;
7661 /* First, find out if we use _any_ altivec registers. */
7662 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
7663 if (regs_ever_live[i])
7664 mask |= ALTIVEC_REG_BIT (i);
7669 /* Next, add all registers that are call-clobbered. We do this
7670 because post-reload register optimizers such as regrename_optimize
7671 may choose to use them. They never change the register class
7672 chosen by reload, so cannot create new uses of altivec registers
7673 if there were none before, so the early exit above is safe. */
7674 /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow
7675 altivec registers not saved in the mask, which might well make the
7676 adjustments below more effective in eliding the save/restore of
7677 VRSAVE in small functions. */
7678 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
7679 if (call_used_regs[i])
7680 mask |= ALTIVEC_REG_BIT (i);
7682 /* Next, remove the argument registers from the set. These must
7683 be in the VRSAVE mask set by the caller, so we don't need to add
7684 them in again. More importantly, the mask we compute here is
7685 used to generate CLOBBERs in the set_vrsave insn, and we do not
7686 wish the argument registers to die. */
7687 for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i)
7688 mask &= ~ALTIVEC_REG_BIT (i);
7690 /* Similarly, remove the return value from the set. */
7693 diddle_return_value (is_altivec_return_reg, &yes);
7695 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
7702 is_altivec_return_reg (reg, xyes)
7706 bool *yes = (bool *) xyes;
7707 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
7712 /* Calculate the stack information for the current function. This is
7713 complicated by having two separate calling sequences, the AIX calling
7714 sequence and the V.4 calling sequence.
7716 AIX (and Darwin/Mac OS X) stack frames look like:
7718 SP----> +---------------------------------------+
7719 | back chain to caller | 0 0
7720 +---------------------------------------+
7721 | saved CR | 4 8 (8-11)
7722 +---------------------------------------+
7724 +---------------------------------------+
7725 | reserved for compilers | 12 24
7726 +---------------------------------------+
7727 | reserved for binders | 16 32
7728 +---------------------------------------+
7729 | saved TOC pointer | 20 40
7730 +---------------------------------------+
7731 | Parameter save area (P) | 24 48
7732 +---------------------------------------+
7733 | Alloca space (A) | 24+P etc.
7734 +---------------------------------------+
7735 | Local variable space (L) | 24+P+A
7736 +---------------------------------------+
7737 | Float/int conversion temporary (X) | 24+P+A+L
7738 +---------------------------------------+
7739 | Save area for AltiVec registers (W) | 24+P+A+L+X
7740 +---------------------------------------+
7741 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
7742 +---------------------------------------+
7743 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
7744 +---------------------------------------+
7745 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
7746 +---------------------------------------+
7747 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
7748 +---------------------------------------+
7749 old SP->| back chain to caller's caller |
7750 +---------------------------------------+
7752 The required alignment for AIX configurations is two words (i.e., 8
7756 V.4 stack frames look like:
7758 SP----> +---------------------------------------+
7759 | back chain to caller | 0
7760 +---------------------------------------+
7761 | caller's saved LR | 4
7762 +---------------------------------------+
7763 | Parameter save area (P) | 8
7764 +---------------------------------------+
7765 | Alloca space (A) | 8+P
7766 +---------------------------------------+
7767 | Varargs save area (V) | 8+P+A
7768 +---------------------------------------+
7769 | Local variable space (L) | 8+P+A+V
7770 +---------------------------------------+
7771 | Float/int conversion temporary (X) | 8+P+A+V+L
7772 +---------------------------------------+
7773 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
7774 +---------------------------------------+
7775 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
7776 +---------------------------------------+
7777 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
7778 +---------------------------------------+
7779 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
7780 +---------------------------------------+
7781 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
7782 +---------------------------------------+
7783 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
7784 +---------------------------------------+
7785 old SP->| back chain to caller's caller |
7786 +---------------------------------------+
7788 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
7789 given. (But note below and in sysv4.h that we require only 8 and
7790 may round up the size of our stack frame anyways. The historical
7791 reason is early versions of powerpc-linux which didn't properly
7792 align the stack at program startup. A happy side-effect is that
7793 -mno-eabi libraries can be used with -meabi programs.)
7795 The EABI configuration defaults to the V.4 layout, unless
7796 -mcall-aix is used, in which case the AIX layout is used. However,
7797 the stack alignment requirements may differ. If -mno-eabi is not
7798 given, the required stack alignment is 8 bytes; if -mno-eabi is
7799 given, the required alignment is 16 bytes. (But see V.4 comment
7802 #ifndef ABI_STACK_BOUNDARY
7803 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
7807 rs6000_stack_info ()
7809 static rs6000_stack_t info, zero_info;
7810 rs6000_stack_t *info_ptr = &info;
7811 int reg_size = TARGET_POWERPC64 ? 8 : 4;
7812 enum rs6000_abi abi;
7816 /* Zero all fields portably. */
7819 /* Select which calling sequence. */
7820 info_ptr->abi = abi = DEFAULT_ABI;
7822 /* Calculate which registers need to be saved & save area size. */
7823 info_ptr->first_gp_reg_save = first_reg_to_save ();
7824 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
7825 even if it currently looks like we won't. */
7826 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
7827 || (flag_pic == 1 && abi == ABI_V4)
7828 || (flag_pic && abi == ABI_DARWIN))
7829 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
7830 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
7832 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
7834 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
7835 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
7837 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
7838 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
7839 - info_ptr->first_altivec_reg_save);
7841 /* Does this function call anything? */
7842 info_ptr->calls_p = (! current_function_is_leaf
7843 || cfun->machine->ra_needs_full_frame);
7845 /* Determine if we need to save the link register. */
7846 if (rs6000_ra_ever_killed ()
7847 || (DEFAULT_ABI == ABI_AIX && current_function_profile)
7848 #ifdef TARGET_RELOCATABLE
7849 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
7851 || (info_ptr->first_fp_reg_save != 64
7852 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
7853 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
7854 || (abi == ABI_V4 && current_function_calls_alloca)
7855 || (DEFAULT_ABI == ABI_DARWIN
7857 && current_function_uses_pic_offset_table)
7858 || info_ptr->calls_p)
7860 info_ptr->lr_save_p = 1;
7861 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
7864 /* Determine if we need to save the condition code registers. */
7865 if (regs_ever_live[CR2_REGNO]
7866 || regs_ever_live[CR3_REGNO]
7867 || regs_ever_live[CR4_REGNO])
7869 info_ptr->cr_save_p = 1;
7871 info_ptr->cr_size = reg_size;
7874 /* If the current function calls __builtin_eh_return, then we need
7875 to allocate stack space for registers that will hold data for
7876 the exception handler. */
7877 if (current_function_calls_eh_return)
7880 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
7882 ehrd_size = i * UNITS_PER_WORD;
7887 /* Determine various sizes. */
7888 info_ptr->reg_size = reg_size;
7889 info_ptr->fixed_size = RS6000_SAVE_AREA;
7890 info_ptr->varargs_size = RS6000_VARARGS_AREA;
7891 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
7892 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
7895 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE)
7897 info_ptr->vrsave_mask = compute_vrsave_mask ();
7898 info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0;
7902 info_ptr->vrsave_mask = 0;
7903 info_ptr->vrsave_size = 0;
7906 /* Calculate the offsets. */
7914 case ABI_AIX_NODESC:
7916 info_ptr->fp_save_offset = - info_ptr->fp_size;
7917 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
7919 if (TARGET_ALTIVEC_ABI)
7921 info_ptr->vrsave_save_offset
7922 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
7924 /* Align stack so vector save area is on a quadword boundary. */
7925 if (info_ptr->altivec_size != 0)
7926 info_ptr->altivec_padding_size
7927 = 16 - (-info_ptr->vrsave_save_offset % 16);
7929 info_ptr->altivec_padding_size = 0;
7931 info_ptr->altivec_save_offset
7932 = info_ptr->vrsave_save_offset
7933 - info_ptr->altivec_padding_size
7934 - info_ptr->altivec_size;
7936 /* Adjust for AltiVec case. */
7937 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
7940 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
7941 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
7942 info_ptr->lr_save_offset = 2*reg_size;
7946 info_ptr->fp_save_offset = - info_ptr->fp_size;
7947 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
7948 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
7950 if (TARGET_ALTIVEC_ABI)
7952 info_ptr->vrsave_save_offset
7953 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
7955 /* Align stack so vector save area is on a quadword boundary. */
7956 if (info_ptr->altivec_size != 0)
7957 info_ptr->altivec_padding_size
7958 = 16 - (-info_ptr->vrsave_save_offset % 16);
7960 info_ptr->altivec_padding_size = 0;
7962 info_ptr->altivec_save_offset
7963 = info_ptr->vrsave_save_offset
7964 - info_ptr->altivec_padding_size
7965 - info_ptr->altivec_size;
7967 /* Adjust for AltiVec case. */
7968 info_ptr->toc_save_offset
7969 = info_ptr->altivec_save_offset - info_ptr->toc_size;
7972 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
7973 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
7974 info_ptr->lr_save_offset = reg_size;
7978 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
7980 + info_ptr->altivec_size
7981 + info_ptr->altivec_padding_size
7982 + info_ptr->vrsave_size
7986 + info_ptr->vrsave_size
7987 + info_ptr->toc_size,
7988 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
7991 total_raw_size = (info_ptr->vars_size
7992 + info_ptr->parm_size
7993 + info_ptr->save_size
7994 + info_ptr->varargs_size
7995 + info_ptr->fixed_size);
7997 info_ptr->total_size =
7998 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
8000 /* Determine if we need to allocate any stack frame:
8002 For AIX we need to push the stack if a frame pointer is needed
8003 (because the stack might be dynamically adjusted), if we are
8004 debugging, if we make calls, or if the sum of fp_save, gp_save,
8005 and local variables are more than the space needed to save all
8006 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
8007 + 18*8 = 288 (GPR13 reserved).
8009 For V.4 we don't have the stack cushion that AIX uses, but assume
8010 that the debugger can handle stackless frames. */
8012 if (info_ptr->calls_p)
8013 info_ptr->push_p = 1;
8015 else if (abi == ABI_V4)
8016 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
8019 info_ptr->push_p = (frame_pointer_needed
8020 || (abi != ABI_DARWIN && write_symbols != NO_DEBUG)
8021 || ((total_raw_size - info_ptr->fixed_size)
8022 > (TARGET_32BIT ? 220 : 288)));
8024 /* Zero offsets if we're not saving those registers. */
8025 if (info_ptr->fp_size == 0)
8026 info_ptr->fp_save_offset = 0;
8028 if (info_ptr->gp_size == 0)
8029 info_ptr->gp_save_offset = 0;
8031 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
8032 info_ptr->altivec_save_offset = 0;
8034 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
8035 info_ptr->vrsave_save_offset = 0;
8037 if (! info_ptr->lr_save_p)
8038 info_ptr->lr_save_offset = 0;
8040 if (! info_ptr->cr_save_p)
8041 info_ptr->cr_save_offset = 0;
8043 if (! info_ptr->toc_save_p)
8044 info_ptr->toc_save_offset = 0;
8050 debug_stack_info (info)
8051 rs6000_stack_t *info;
8053 const char *abi_string;
8056 info = rs6000_stack_info ();
8058 fprintf (stderr, "\nStack information for function %s:\n",
8059 ((current_function_decl && DECL_NAME (current_function_decl))
8060 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
8065 default: abi_string = "Unknown"; break;
8066 case ABI_NONE: abi_string = "NONE"; break;
8068 case ABI_AIX_NODESC: abi_string = "AIX"; break;
8069 case ABI_DARWIN: abi_string = "Darwin"; break;
8070 case ABI_V4: abi_string = "V.4"; break;
8073 fprintf (stderr, "\tABI = %5s\n", abi_string);
8075 if (TARGET_ALTIVEC_ABI)
8076 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
8078 if (info->first_gp_reg_save != 32)
8079 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
8081 if (info->first_fp_reg_save != 64)
8082 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
8084 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
8085 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
8086 info->first_altivec_reg_save);
8088 if (info->lr_save_p)
8089 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
8091 if (info->cr_save_p)
8092 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
8094 if (info->toc_save_p)
8095 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
8097 if (info->vrsave_mask)
8098 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
8101 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
8104 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
8106 if (info->gp_save_offset)
8107 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
8109 if (info->fp_save_offset)
8110 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
8112 if (info->altivec_save_offset)
8113 fprintf (stderr, "\taltivec_save_offset = %5d\n",
8114 info->altivec_save_offset);
8116 if (info->vrsave_save_offset)
8117 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
8118 info->vrsave_save_offset);
8120 if (info->lr_save_offset)
8121 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
8123 if (info->cr_save_offset)
8124 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
8126 if (info->toc_save_offset)
8127 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
8129 if (info->varargs_save_offset)
8130 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
8132 if (info->total_size)
8133 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
8135 if (info->varargs_size)
8136 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
8138 if (info->vars_size)
8139 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
8141 if (info->parm_size)
8142 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
8144 if (info->fixed_size)
8145 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
8148 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
8151 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
8153 if (info->altivec_size)
8154 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
8156 if (info->vrsave_size)
8157 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
8159 if (info->altivec_padding_size)
8160 fprintf (stderr, "\taltivec_padding_size= %5d\n",
8161 info->altivec_padding_size);
8164 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
8167 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
8170 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
8172 if (info->save_size)
8173 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
8175 if (info->reg_size != 4)
8176 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
8178 fprintf (stderr, "\n");
8182 rs6000_return_addr (count, frame)
8186 /* Currently we don't optimize very well between prolog and body
8187 code and for PIC code the code can be actually quite bad, so
8188 don't try to be too clever here. */
8189 if (count != 0 || flag_pic != 0)
8191 cfun->machine->ra_needs_full_frame = 1;
8198 plus_constant (copy_to_reg
8199 (gen_rtx_MEM (Pmode,
8200 memory_address (Pmode, frame))),
8201 RETURN_ADDRESS_OFFSET)));
8204 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
8208 rs6000_ra_ever_killed ()
8212 #ifdef ASM_OUTPUT_MI_THUNK
8213 if (current_function_is_thunk)
8216 if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM)
8217 || cfun->machine->ra_needs_full_frame)
8218 return regs_ever_live[LINK_REGISTER_REGNUM];
8220 push_topmost_sequence ();
8222 pop_topmost_sequence ();
8224 return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
8228 /* Add a REG_MAYBE_DEAD note to the insn. */
8230 rs6000_maybe_dead (insn)
8233 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
8238 /* Emit instructions needed to load the TOC register.
8239 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
8240 a constant pool; or for SVR4 -fpic. */
8243 rs6000_emit_load_toc_table (fromprolog)
8247 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8249 if (TARGET_ELF && DEFAULT_ABI != ABI_AIX)
8251 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
8253 rtx temp = (fromprolog
8254 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
8255 : gen_reg_rtx (Pmode));
8256 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp)));
8257 rs6000_maybe_dead (emit_move_insn (dest, temp));
8259 else if (flag_pic == 2)
8262 rtx tempLR = (fromprolog
8263 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
8264 : gen_reg_rtx (Pmode));
8265 rtx temp0 = (fromprolog
8266 ? gen_rtx_REG (Pmode, 0)
8267 : gen_reg_rtx (Pmode));
8270 /* possibly create the toc section */
8271 if (! toc_initialized)
8274 function_section (current_function_decl);
8281 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
8282 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8284 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
8285 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8287 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
8289 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
8290 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
8297 static int reload_toc_labelno = 0;
8299 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
8301 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
8302 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8304 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR,
8307 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
8308 rs6000_maybe_dead (emit_move_insn (temp0,
8309 gen_rtx_MEM (Pmode, dest)));
8311 rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest)));
8313 else if (flag_pic == 0 && TARGET_MINIMAL_TOC)
8315 /* This is for AIX code running in non-PIC ELF. */
8318 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
8319 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8321 rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym)));
8322 rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym)));
8330 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest)));
8332 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest)));
8337 get_TOC_alias_set ()
8339 static int set = -1;
8341 set = new_alias_set ();
8345 /* This retuns nonzero if the current function uses the TOC. This is
8346 determined by the presence of (unspec ... 7), which is generated by
8347 the various load_toc_* patterns. */
8354 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8357 rtx pat = PATTERN (insn);
8360 if (GET_CODE (pat) == PARALLEL)
8361 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8362 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC
8363 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7)
8370 create_TOC_reference (symbol)
8373 return gen_rtx_PLUS (Pmode,
8374 gen_rtx_REG (Pmode, TOC_REGISTER),
8375 gen_rtx_CONST (Pmode,
8376 gen_rtx_MINUS (Pmode, symbol,
8377 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
8381 /* __throw will restore its own return address to be the same as the
8382 return address of the function that the throw is being made to.
8383 This is unfortunate, because we want to check the original
8384 return address to see if we need to restore the TOC.
8385 So we have to squirrel it away here.
8386 This is used only in compiling __throw and __rethrow.
8388 Most of this code should be removed by CSE. */
8389 static rtx insn_after_throw;
8391 /* This does the saving... */
8393 rs6000_aix_emit_builtin_unwind_init ()
8396 rtx stack_top = gen_reg_rtx (Pmode);
8397 rtx opcode_addr = gen_reg_rtx (Pmode);
8399 insn_after_throw = gen_reg_rtx (SImode);
8401 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8402 emit_move_insn (stack_top, mem);
8404 mem = gen_rtx_MEM (Pmode,
8405 gen_rtx_PLUS (Pmode, stack_top,
8406 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
8407 emit_move_insn (opcode_addr, mem);
8408 emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr));
8411 /* Emit insns to _restore_ the TOC register, at runtime (specifically
8412 in _eh.o). Only used on AIX.
8414 The idea is that on AIX, function calls look like this:
8415 bl somefunction-trampoline
8419 somefunction-trampoline:
8421 ... load function address in the count register ...
8423 or like this, if the linker determines that this is not a cross-module call
8424 and so the TOC need not be restored:
8427 or like this, if the compiler could determine that this is not a
8430 now, the tricky bit here is that register 2 is saved and restored
8431 by the _linker_, so we can't readily generate debugging information
8432 for it. So we need to go back up the call chain looking at the
8433 insns at return addresses to see which calls saved the TOC register
8434 and so see where it gets restored from.
8436 Oh, and all this gets done in RTL inside the eh_epilogue pattern,
8437 just before the actual epilogue.
8439 On the bright side, this incurs no space or time overhead unless an
8440 exception is thrown, except for the extra code in libgcc.a.
8442 The parameter STACKSIZE is a register containing (at runtime)
8443 the amount to be popped off the stack in addition to the stack frame
8444 of this routine (which will be __throw or __rethrow, and so is
8445 guaranteed to have a stack frame). */
8448 rs6000_emit_eh_toc_restore (stacksize)
8452 rtx bottom_of_stack = gen_reg_rtx (Pmode);
8453 rtx tocompare = gen_reg_rtx (SImode);
8454 rtx opcode = gen_reg_rtx (SImode);
8455 rtx opcode_addr = gen_reg_rtx (Pmode);
8457 rtx loop_start = gen_label_rtx ();
8458 rtx no_toc_restore_needed = gen_label_rtx ();
8459 rtx loop_exit = gen_label_rtx ();
8461 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8462 set_mem_alias_set (mem, rs6000_sr_alias_set);
8463 emit_move_insn (bottom_of_stack, mem);
8465 top_of_stack = expand_binop (Pmode, add_optab,
8466 bottom_of_stack, stacksize,
8467 NULL_RTX, 1, OPTAB_WIDEN);
8469 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
8470 : 0xE8410028, SImode));
8472 if (insn_after_throw == NULL_RTX)
8474 emit_move_insn (opcode, insn_after_throw);
8476 emit_note (NULL, NOTE_INSN_LOOP_BEG);
8477 emit_label (loop_start);
8479 do_compare_rtx_and_jump (opcode, tocompare, NE, 1,
8480 SImode, NULL_RTX, NULL_RTX,
8481 no_toc_restore_needed);
8483 mem = gen_rtx_MEM (Pmode,
8484 gen_rtx_PLUS (Pmode, bottom_of_stack,
8485 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
8486 emit_move_insn (gen_rtx_REG (Pmode, 2), mem);
8488 emit_label (no_toc_restore_needed);
8489 do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1,
8490 Pmode, NULL_RTX, NULL_RTX,
8493 mem = gen_rtx_MEM (Pmode, bottom_of_stack);
8494 set_mem_alias_set (mem, rs6000_sr_alias_set);
8495 emit_move_insn (bottom_of_stack, mem);
8497 mem = gen_rtx_MEM (Pmode,
8498 gen_rtx_PLUS (Pmode, bottom_of_stack,
8499 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
8500 emit_move_insn (opcode_addr, mem);
8501 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
8503 emit_note (NULL, NOTE_INSN_LOOP_CONT);
8504 emit_jump (loop_start);
8505 emit_note (NULL, NOTE_INSN_LOOP_END);
8506 emit_label (loop_exit);
8508 #endif /* TARGET_AIX */
8510 /* This ties together stack memory (MEM with an alias set of
8511 rs6000_sr_alias_set) and the change to the stack pointer. */
8514 rs6000_emit_stack_tie ()
8516 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8518 set_mem_alias_set (mem, rs6000_sr_alias_set);
8519 emit_insn (gen_stack_tie (mem));
8522 /* Emit the correct code for allocating stack space, as insns.
8523 If COPY_R12, make sure a copy of the old frame is left in r12.
8524 The generated code may use hard register 0 as a temporary. */
8527 rs6000_emit_allocate_stack (size, copy_r12)
8532 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8533 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
8534 rtx todec = GEN_INT (-size);
8536 if (current_function_limit_stack)
8538 if (REG_P (stack_limit_rtx)
8539 && REGNO (stack_limit_rtx) > 1
8540 && REGNO (stack_limit_rtx) <= 31)
8542 emit_insn (Pmode == SImode
8543 ? gen_addsi3 (tmp_reg,
8546 : gen_adddi3 (tmp_reg,
8550 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
8553 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
8555 && DEFAULT_ABI == ABI_V4)
8557 rtx toload = gen_rtx_CONST (VOIDmode,
8558 gen_rtx_PLUS (Pmode,
8562 emit_insn (gen_elf_high (tmp_reg, toload));
8563 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
8564 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
8568 warning ("stack limit expression is not supported");
8571 if (copy_r12 || ! TARGET_UPDATE)
8572 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
8578 /* Need a note here so that try_split doesn't get confused. */
8579 if (get_last_insn() == NULL_RTX)
8580 emit_note (0, NOTE_INSN_DELETED);
8581 insn = emit_move_insn (tmp_reg, todec);
8582 try_split (PATTERN (insn), insn, 0);
8586 if (Pmode == SImode)
8587 insn = emit_insn (gen_movsi_update (stack_reg, stack_reg,
8590 insn = emit_insn (gen_movdi_update (stack_reg, stack_reg,
8595 if (Pmode == SImode)
8596 insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec));
8598 insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec));
8599 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
8600 gen_rtx_REG (Pmode, 12));
8603 RTX_FRAME_RELATED_P (insn) = 1;
8605 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8606 gen_rtx_SET (VOIDmode, stack_reg,
8607 gen_rtx_PLUS (Pmode, stack_reg,
8612 /* Add a RTX_FRAME_RELATED note so that dwarf2out_frame_debug_expr
8615 (mem (plus (blah) (regXX)))
8619 (mem (plus (blah) (const VALUE_OF_REGXX))). */
8622 altivec_frame_fixup (insn, reg, val)
8628 real = copy_rtx (PATTERN (insn));
8630 real = replace_rtx (real, reg, GEN_INT (val));
8632 RTX_FRAME_RELATED_P (insn) = 1;
8633 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8638 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
8639 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
8640 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
8641 deduce these equivalences by itself so it wasn't necessary to hold
8642 its hand so much. */
8645 rs6000_frame_related (insn, reg, val, reg2, rreg)
8654 real = copy_rtx (PATTERN (insn));
8656 real = replace_rtx (real, reg,
8657 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
8658 STACK_POINTER_REGNUM),
8661 /* We expect that 'real' is either a SET or a PARALLEL containing
8662 SETs (and possibly other stuff). In a PARALLEL, all the SETs
8663 are important so they all have to be marked RTX_FRAME_RELATED_P. */
8665 if (GET_CODE (real) == SET)
8669 temp = simplify_rtx (SET_SRC (set));
8671 SET_SRC (set) = temp;
8672 temp = simplify_rtx (SET_DEST (set));
8674 SET_DEST (set) = temp;
8675 if (GET_CODE (SET_DEST (set)) == MEM)
8677 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
8679 XEXP (SET_DEST (set), 0) = temp;
8682 else if (GET_CODE (real) == PARALLEL)
8685 for (i = 0; i < XVECLEN (real, 0); i++)
8686 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
8688 rtx set = XVECEXP (real, 0, i);
8690 temp = simplify_rtx (SET_SRC (set));
8692 SET_SRC (set) = temp;
8693 temp = simplify_rtx (SET_DEST (set));
8695 SET_DEST (set) = temp;
8696 if (GET_CODE (SET_DEST (set)) == MEM)
8698 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
8700 XEXP (SET_DEST (set), 0) = temp;
8702 RTX_FRAME_RELATED_P (set) = 1;
8708 if (reg2 != NULL_RTX)
8709 real = replace_rtx (real, reg2, rreg);
8711 RTX_FRAME_RELATED_P (insn) = 1;
8712 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8717 /* Returns an insn that has a vrsave set operation with the
8718 appropriate CLOBBERs. */
8721 generate_set_vrsave (reg, info, epiloguep)
8723 rs6000_stack_t *info;
8727 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
8728 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
8731 = gen_rtx_SET (VOIDmode,
8733 gen_rtx_UNSPEC_VOLATILE (SImode,
8734 gen_rtvec (2, reg, vrsave),
8739 /* We need to clobber the registers in the mask so the scheduler
8740 does not move sets to VRSAVE before sets of AltiVec registers.
8742 However, if the function receives nonlocal gotos, reload will set
8743 all call saved registers live. We will end up with:
8745 (set (reg 999) (mem))
8746 (parallel [ (set (reg vrsave) (unspec blah))
8747 (clobber (reg 999))])
8749 The clobber will cause the store into reg 999 to be dead, and
8750 flow will attempt to delete an epilogue insn. In this case, we
8751 need an unspec use/set of the register. */
8753 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
8754 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
8756 if (!epiloguep || call_used_regs [i])
8757 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
8758 gen_rtx_REG (V4SImode, i));
8761 rtx reg = gen_rtx_REG (V4SImode, i);
8764 = gen_rtx_SET (VOIDmode,
8766 gen_rtx_UNSPEC (V4SImode,
8767 gen_rtvec (1, reg), 27));
8771 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
8773 for (i = 0; i < nclobs; ++i)
8774 XVECEXP (insn, 0, i) = clobs[i];
8779 /* Emit function prologue as insns. */
8782 rs6000_emit_prologue ()
8784 rs6000_stack_t *info = rs6000_stack_info ();
8785 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
8786 int reg_size = TARGET_POWERPC64 ? 8 : 4;
8787 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8788 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
8789 rtx frame_reg_rtx = sp_reg_rtx;
8790 rtx cr_save_rtx = NULL;
8792 int saving_FPRs_inline;
8793 int using_store_multiple;
8794 HOST_WIDE_INT sp_offset = 0;
8796 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
8797 && info->first_gp_reg_save < 31);
8798 saving_FPRs_inline = (info->first_fp_reg_save == 64
8799 || FP_SAVE_INLINE (info->first_fp_reg_save));
8801 /* For V.4, update stack before we do any saving and set back pointer. */
8802 if (info->push_p && DEFAULT_ABI == ABI_V4)
8804 if (info->total_size < 32767)
8805 sp_offset = info->total_size;
8807 frame_reg_rtx = frame_ptr_rtx;
8808 rs6000_emit_allocate_stack (info->total_size,
8809 (frame_reg_rtx != sp_reg_rtx
8812 || info->first_fp_reg_save < 64
8813 || info->first_gp_reg_save < 32
8815 if (frame_reg_rtx != sp_reg_rtx)
8816 rs6000_emit_stack_tie ();
8819 /* Save AltiVec registers if needed. */
8820 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
8824 /* There should be a non inline version of this, for when we
8825 are saving lots of vector registers. */
8826 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
8827 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
8829 rtx areg, savereg, mem;
8832 offset = info->altivec_save_offset + sp_offset
8833 + 16 * (i - info->first_altivec_reg_save);
8835 savereg = gen_rtx_REG (V4SImode, i);
8837 areg = gen_rtx_REG (Pmode, 0);
8838 emit_move_insn (areg, GEN_INT (offset));
8840 /* AltiVec addressing mode is [reg+reg]. */
8841 mem = gen_rtx_MEM (V4SImode,
8842 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
8844 set_mem_alias_set (mem, rs6000_sr_alias_set);
8846 insn = emit_move_insn (mem, savereg);
8848 altivec_frame_fixup (insn, areg, offset);
8852 /* VRSAVE is a bit vector representing which AltiVec registers
8853 are used. The OS uses this to determine which vector
8854 registers to save on a context switch. We need to save
8855 VRSAVE on the stack frame, add whatever AltiVec registers we
8856 used in this function, and do the corresponding magic in the
8859 if (TARGET_ALTIVEC && info->vrsave_mask != 0)
8861 rtx reg, mem, vrsave;
8864 /* Get VRSAVE onto a GPR. */
8865 reg = gen_rtx_REG (SImode, 12);
8866 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
8868 emit_insn (gen_get_vrsave_internal (reg));
8870 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
8873 offset = info->vrsave_save_offset + sp_offset;
8875 = gen_rtx_MEM (SImode,
8876 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
8877 set_mem_alias_set (mem, rs6000_sr_alias_set);
8878 insn = emit_move_insn (mem, reg);
8880 /* Include the registers in the mask. */
8881 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
8883 insn = emit_insn (generate_set_vrsave (reg, info, 0));
8886 /* If we use the link register, get it into r0. */
8887 if (info->lr_save_p)
8888 emit_move_insn (gen_rtx_REG (Pmode, 0),
8889 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
8891 /* If we need to save CR, put it into r12. */
8892 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
8894 cr_save_rtx = gen_rtx_REG (SImode, 12);
8895 emit_insn (gen_movesi_from_cr (cr_save_rtx));
8898 /* Do any required saving of fpr's. If only one or two to save, do
8899 it ourselves. Otherwise, call function. */
8900 if (saving_FPRs_inline)
8903 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
8904 if ((regs_ever_live[info->first_fp_reg_save+i]
8905 && ! call_used_regs[info->first_fp_reg_save+i]))
8908 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
8909 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
8910 GEN_INT (info->fp_save_offset
8913 mem = gen_rtx_MEM (DFmode, addr);
8914 set_mem_alias_set (mem, rs6000_sr_alias_set);
8916 insn = emit_move_insn (mem, reg);
8917 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
8918 NULL_RTX, NULL_RTX);
8921 else if (info->first_fp_reg_save != 64)
8925 const char *alloc_rname;
8927 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
8929 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
8931 LINK_REGISTER_REGNUM));
8932 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
8933 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
8934 alloc_rname = ggc_strdup (rname);
8935 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
8936 gen_rtx_SYMBOL_REF (Pmode,
8938 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
8941 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
8942 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
8943 GEN_INT (info->fp_save_offset
8944 + sp_offset + 8*i));
8945 mem = gen_rtx_MEM (DFmode, addr);
8946 set_mem_alias_set (mem, rs6000_sr_alias_set);
8948 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
8950 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
8951 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
8952 NULL_RTX, NULL_RTX);
8955 /* Save GPRs. This is done as a PARALLEL if we are using
8956 the store-multiple instructions. */
8957 if (using_store_multiple)
8961 p = rtvec_alloc (32 - info->first_gp_reg_save);
8962 dwarfp = rtvec_alloc (32 - info->first_gp_reg_save);
8963 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
8966 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
8967 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
8968 GEN_INT (info->gp_save_offset
8971 mem = gen_rtx_MEM (reg_mode, addr);
8972 set_mem_alias_set (mem, rs6000_sr_alias_set);
8974 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
8976 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
8977 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
8978 NULL_RTX, NULL_RTX);
8983 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
8984 if ((regs_ever_live[info->first_gp_reg_save+i]
8985 && ! call_used_regs[info->first_gp_reg_save+i])
8986 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
8987 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
8988 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
8991 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
8992 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
8993 GEN_INT (info->gp_save_offset
8996 mem = gen_rtx_MEM (reg_mode, addr);
8997 set_mem_alias_set (mem, rs6000_sr_alias_set);
8999 insn = emit_move_insn (mem, reg);
9000 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9001 NULL_RTX, NULL_RTX);
9005 /* ??? There's no need to emit actual instructions here, but it's the
9006 easiest way to get the frame unwind information emitted. */
9007 if (current_function_calls_eh_return)
9009 unsigned int i, regno;
9015 regno = EH_RETURN_DATA_REGNO (i);
9016 if (regno == INVALID_REGNUM)
9019 reg = gen_rtx_REG (reg_mode, regno);
9020 addr = plus_constant (frame_reg_rtx,
9021 info->ehrd_offset + sp_offset
9022 + reg_size * (int) i);
9023 mem = gen_rtx_MEM (reg_mode, addr);
9024 set_mem_alias_set (mem, rs6000_sr_alias_set);
9026 insn = emit_move_insn (mem, reg);
9027 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9028 NULL_RTX, NULL_RTX);
9032 /* Save lr if we used it. */
9033 if (info->lr_save_p)
9035 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9036 GEN_INT (info->lr_save_offset + sp_offset));
9037 rtx reg = gen_rtx_REG (Pmode, 0);
9038 rtx mem = gen_rtx_MEM (Pmode, addr);
9039 /* This should not be of rs6000_sr_alias_set, because of
9040 __builtin_return_address. */
9042 insn = emit_move_insn (mem, reg);
9043 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9044 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
9047 /* Save CR if we use any that must be preserved. */
9048 if (info->cr_save_p)
9050 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9051 GEN_INT (info->cr_save_offset + sp_offset));
9052 rtx mem = gen_rtx_MEM (SImode, addr);
9054 set_mem_alias_set (mem, rs6000_sr_alias_set);
9056 /* If r12 was used to hold the original sp, copy cr into r0 now
9058 if (REGNO (frame_reg_rtx) == 12)
9060 cr_save_rtx = gen_rtx_REG (SImode, 0);
9061 emit_insn (gen_movesi_from_cr (cr_save_rtx));
9063 insn = emit_move_insn (mem, cr_save_rtx);
9065 /* Now, there's no way that dwarf2out_frame_debug_expr is going
9066 to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's
9067 OK. All we have to do is specify that _one_ condition code
9068 register is saved in this stack slot. The thrower's epilogue
9069 will then restore all the call-saved registers.
9070 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
9071 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9072 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
9075 /* Update stack and set back pointer unless this is V.4,
9076 for which it was done previously. */
9077 if (info->push_p && DEFAULT_ABI != ABI_V4)
9078 rs6000_emit_allocate_stack (info->total_size, FALSE);
9080 /* Set frame pointer, if needed. */
9081 if (frame_pointer_needed)
9083 insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM),
9085 RTX_FRAME_RELATED_P (insn) = 1;
9088 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9089 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
9090 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
9091 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
9093 /* If emit_load_toc_table will use the link register, we need to save
9094 it. We use R11 for this purpose because emit_load_toc_table
9095 can use register 0. This allows us to use a plain 'blr' to return
9096 from the procedure more often. */
9097 int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0
9098 && ! info->lr_save_p
9099 && EXIT_BLOCK_PTR->pred != NULL);
9100 if (save_LR_around_toc_setup)
9101 emit_move_insn (gen_rtx_REG (Pmode, 11),
9102 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
9104 rs6000_emit_load_toc_table (TRUE);
9106 if (save_LR_around_toc_setup)
9107 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
9108 gen_rtx_REG (Pmode, 11));
9111 if (DEFAULT_ABI == ABI_DARWIN
9112 && flag_pic && current_function_uses_pic_offset_table)
9114 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
9116 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest)));
9119 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
9120 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
9124 /* Write function prologue. */
9127 rs6000_output_function_prologue (file, size)
9129 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
9131 rs6000_stack_t *info = rs6000_stack_info ();
9133 if (TARGET_DEBUG_STACK)
9134 debug_stack_info (info);
9136 /* Write .extern for any function we will call to save and restore
9138 if (info->first_fp_reg_save < 64
9139 && !FP_SAVE_INLINE (info->first_fp_reg_save))
9140 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
9141 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
9142 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
9145 /* Write .extern for AIX common mode routines, if needed. */
9146 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
9148 fputs ("\t.extern __mulh\n", file);
9149 fputs ("\t.extern __mull\n", file);
9150 fputs ("\t.extern __divss\n", file);
9151 fputs ("\t.extern __divus\n", file);
9152 fputs ("\t.extern __quoss\n", file);
9153 fputs ("\t.extern __quous\n", file);
9154 common_mode_defined = 1;
9157 if (! HAVE_prologue)
9161 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
9162 the "toplevel" insn chain. */
9163 emit_note (0, NOTE_INSN_DELETED);
9164 rs6000_emit_prologue ();
9165 emit_note (0, NOTE_INSN_DELETED);
9167 /* Expand INSN_ADDRESSES so final() doesn't crash. */
9171 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9173 INSN_ADDRESSES_NEW (insn, addr);
9178 if (TARGET_DEBUG_STACK)
9179 debug_rtx_list (get_insns (), 100);
9180 final (get_insns (), file, FALSE, FALSE);
9184 rs6000_pic_labelno++;
9187 /* Emit function epilogue as insns.
9189 At present, dwarf2out_frame_debug_expr doesn't understand
9190 register restores, so we don't bother setting RTX_FRAME_RELATED_P
9191 anywhere in the epilogue. Most of the insns below would in any case
9192 need special notes to explain where r11 is in relation to the stack. */
9195 rs6000_emit_epilogue (sibcall)
9198 rs6000_stack_t *info;
9199 int restoring_FPRs_inline;
9200 int using_load_multiple;
9201 int using_mfcr_multiple;
9202 int use_backchain_to_restore_sp;
9204 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
9205 rtx frame_reg_rtx = sp_reg_rtx;
9206 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
9207 int reg_size = TARGET_POWERPC64 ? 8 : 4;
9210 info = rs6000_stack_info ();
9211 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
9212 && info->first_gp_reg_save < 31);
9213 restoring_FPRs_inline = (sibcall
9214 || current_function_calls_eh_return
9215 || info->first_fp_reg_save == 64
9216 || FP_SAVE_INLINE (info->first_fp_reg_save));
9217 use_backchain_to_restore_sp = (frame_pointer_needed
9218 || current_function_calls_alloca
9219 || info->total_size > 32767);
9220 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
9221 || rs6000_cpu == PROCESSOR_PPC603
9222 || rs6000_cpu == PROCESSOR_PPC750
9225 /* If we have a frame pointer, a call to alloca, or a large stack
9226 frame, restore the old stack pointer using the backchain. Otherwise,
9227 we know what size to update it with. */
9228 if (use_backchain_to_restore_sp)
9230 /* Under V.4, don't reset the stack pointer until after we're done
9231 loading the saved registers. */
9232 if (DEFAULT_ABI == ABI_V4)
9233 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
9235 emit_move_insn (frame_reg_rtx,
9236 gen_rtx_MEM (Pmode, sp_reg_rtx));
9239 else if (info->push_p)
9241 if (DEFAULT_ABI == ABI_V4)
9242 sp_offset = info->total_size;
9245 emit_insn (TARGET_32BIT
9246 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
9247 GEN_INT (info->total_size))
9248 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
9249 GEN_INT (info->total_size)));
9253 /* Restore AltiVec registers if needed. */
9254 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9258 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
9259 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9261 rtx addr, areg, mem;
9263 areg = gen_rtx_REG (Pmode, 0);
9265 (areg, GEN_INT (info->altivec_save_offset
9267 + 16 * (i - info->first_altivec_reg_save)));
9269 /* AltiVec addressing mode is [reg+reg]. */
9270 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
9271 mem = gen_rtx_MEM (V4SImode, addr);
9272 set_mem_alias_set (mem, rs6000_sr_alias_set);
9274 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
9278 /* Restore VRSAVE if needed. */
9279 if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0)
9283 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9284 GEN_INT (info->vrsave_save_offset + sp_offset));
9285 mem = gen_rtx_MEM (SImode, addr);
9286 set_mem_alias_set (mem, rs6000_sr_alias_set);
9287 reg = gen_rtx_REG (SImode, 12);
9288 emit_move_insn (reg, mem);
9290 emit_insn (generate_set_vrsave (reg, info, 1));
9293 /* Get the old lr if we saved it. */
9294 if (info->lr_save_p)
9296 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9297 GEN_INT (info->lr_save_offset + sp_offset));
9298 rtx mem = gen_rtx_MEM (Pmode, addr);
9300 set_mem_alias_set (mem, rs6000_sr_alias_set);
9302 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
9305 /* Get the old cr if we saved it. */
9306 if (info->cr_save_p)
9308 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9309 GEN_INT (info->cr_save_offset + sp_offset));
9310 rtx mem = gen_rtx_MEM (SImode, addr);
9312 set_mem_alias_set (mem, rs6000_sr_alias_set);
9314 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
9317 /* Set LR here to try to overlap restores below. */
9318 if (info->lr_save_p)
9319 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
9320 gen_rtx_REG (Pmode, 0));
9322 /* Load exception handler data registers, if needed. */
9323 if (current_function_calls_eh_return)
9325 unsigned int i, regno;
9331 regno = EH_RETURN_DATA_REGNO (i);
9332 if (regno == INVALID_REGNUM)
9335 addr = plus_constant (frame_reg_rtx,
9336 info->ehrd_offset + sp_offset
9337 + reg_size * (int) i);
9338 mem = gen_rtx_MEM (reg_mode, addr);
9339 set_mem_alias_set (mem, rs6000_sr_alias_set);
9341 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
9345 /* Restore GPRs. This is done as a PARALLEL if we are using
9346 the load-multiple instructions. */
9347 if (using_load_multiple)
9350 p = rtvec_alloc (32 - info->first_gp_reg_save);
9351 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
9353 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9354 GEN_INT (info->gp_save_offset
9357 rtx mem = gen_rtx_MEM (reg_mode, addr);
9359 set_mem_alias_set (mem, rs6000_sr_alias_set);
9362 gen_rtx_SET (VOIDmode,
9363 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
9366 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
9369 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
9370 if ((regs_ever_live[info->first_gp_reg_save+i]
9371 && ! call_used_regs[info->first_gp_reg_save+i])
9372 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
9373 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9374 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9376 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9377 GEN_INT (info->gp_save_offset
9380 rtx mem = gen_rtx_MEM (reg_mode, addr);
9382 set_mem_alias_set (mem, rs6000_sr_alias_set);
9384 emit_move_insn (gen_rtx_REG (reg_mode,
9385 info->first_gp_reg_save + i),
9389 /* Restore fpr's if we need to do it without calling a function. */
9390 if (restoring_FPRs_inline)
9391 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
9392 if ((regs_ever_live[info->first_fp_reg_save+i]
9393 && ! call_used_regs[info->first_fp_reg_save+i]))
9396 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
9397 GEN_INT (info->fp_save_offset
9400 mem = gen_rtx_MEM (DFmode, addr);
9401 set_mem_alias_set (mem, rs6000_sr_alias_set);
9403 emit_move_insn (gen_rtx_REG (DFmode,
9404 info->first_fp_reg_save + i),
9408 /* If we saved cr, restore it here. Just those that were used. */
9409 if (info->cr_save_p)
9411 rtx r12_rtx = gen_rtx_REG (SImode, 12);
9414 if (using_mfcr_multiple)
9416 for (i = 0; i < 8; i++)
9417 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
9423 if (using_mfcr_multiple && count > 1)
9428 p = rtvec_alloc (count);
9431 for (i = 0; i < 8; i++)
9432 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
9434 rtvec r = rtvec_alloc (2);
9435 RTVEC_ELT (r, 0) = r12_rtx;
9436 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
9437 RTVEC_ELT (p, ndx) =
9438 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
9439 gen_rtx_UNSPEC (CCmode, r, 20));
9442 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
9447 for (i = 0; i < 8; i++)
9448 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
9450 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9456 /* If this is V.4, unwind the stack pointer after all of the loads
9457 have been done. We need to emit a block here so that sched
9458 doesn't decide to move the sp change before the register restores
9459 (which may not have any obvious dependency on the stack). This
9460 doesn't hurt performance, because there is no scheduling that can
9461 be done after this point. */
9462 if (DEFAULT_ABI == ABI_V4)
9464 if (frame_reg_rtx != sp_reg_rtx)
9465 rs6000_emit_stack_tie ();
9467 if (use_backchain_to_restore_sp)
9469 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
9471 else if (sp_offset != 0)
9473 emit_insn (Pmode == SImode
9474 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
9475 GEN_INT (sp_offset))
9476 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
9477 GEN_INT (sp_offset)));
9481 if (current_function_calls_eh_return)
9483 rtx sa = EH_RETURN_STACKADJ_RTX;
9484 emit_insn (Pmode == SImode
9485 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
9486 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
9492 if (! restoring_FPRs_inline)
9493 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
9495 p = rtvec_alloc (2);
9497 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
9498 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
9500 LINK_REGISTER_REGNUM));
9502 /* If we have to restore more than two FP registers, branch to the
9503 restore function. It will return to our caller. */
9504 if (! restoring_FPRs_inline)
9508 const char *alloc_rname;
9510 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9511 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
9512 alloc_rname = ggc_strdup (rname);
9513 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
9514 gen_rtx_SYMBOL_REF (Pmode,
9517 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
9520 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
9521 GEN_INT (info->fp_save_offset + 8*i));
9522 mem = gen_rtx_MEM (DFmode, addr);
9523 set_mem_alias_set (mem, rs6000_sr_alias_set);
9525 RTVEC_ELT (p, i+3) =
9526 gen_rtx_SET (VOIDmode,
9527 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
9532 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9536 /* Write function epilogue. */
9539 rs6000_output_function_epilogue (file, size)
9541 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
9543 rs6000_stack_t *info = rs6000_stack_info ();
9544 int optional_tbtab = (optimize_size || TARGET_ELF) ? 0 : 1;
9546 if (! HAVE_epilogue)
9548 rtx insn = get_last_insn ();
9549 /* If the last insn was a BARRIER, we don't have to write anything except
9551 if (GET_CODE (insn) == NOTE)
9552 insn = prev_nonnote_insn (insn);
9553 if (insn == 0 || GET_CODE (insn) != BARRIER)
9555 /* This is slightly ugly, but at least we don't have two
9556 copies of the epilogue-emitting code. */
9559 /* A NOTE_INSN_DELETED is supposed to be at the start
9560 and end of the "toplevel" insn chain. */
9561 emit_note (0, NOTE_INSN_DELETED);
9562 rs6000_emit_epilogue (FALSE);
9563 emit_note (0, NOTE_INSN_DELETED);
9565 /* Expand INSN_ADDRESSES so final() doesn't crash. */
9569 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9571 INSN_ADDRESSES_NEW (insn, addr);
9576 if (TARGET_DEBUG_STACK)
9577 debug_rtx_list (get_insns (), 100);
9578 final (get_insns (), file, FALSE, FALSE);
9583 /* Output a traceback table here. See /usr/include/sys/debug.h for info
9586 We don't output a traceback table if -finhibit-size-directive was
9587 used. The documentation for -finhibit-size-directive reads
9588 ``don't output a @code{.size} assembler directive, or anything
9589 else that would cause trouble if the function is split in the
9590 middle, and the two halves are placed at locations far apart in
9591 memory.'' The traceback table has this property, since it
9592 includes the offset from the start of the function to the
9593 traceback table itself.
9595 System V.4 Powerpc's (and the embedded ABI derived from it) use a
9596 different traceback table. */
9597 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
9599 const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9600 const char *language_string = lang_hooks.name;
9601 int fixed_parms = 0, float_parms = 0, parm_info = 0;
9604 while (*fname == '.') /* V.4 encodes . in the name */
9607 /* Need label immediately before tbtab, so we can compute its offset
9608 from the function start. */
9611 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
9612 ASM_OUTPUT_LABEL (file, fname);
9614 /* The .tbtab pseudo-op can only be used for the first eight
9615 expressions, since it can't handle the possibly variable
9616 length fields that follow. However, if you omit the optional
9617 fields, the assembler outputs zeros for all optional fields
9618 anyways, giving each variable length field is minimum length
9619 (as defined in sys/debug.h). Thus we can not use the .tbtab
9620 pseudo-op at all. */
9622 /* An all-zero word flags the start of the tbtab, for debuggers
9623 that have to find it by searching forward from the entry
9624 point or from the current pc. */
9625 fputs ("\t.long 0\n", file);
9627 /* Tbtab format type. Use format type 0. */
9628 fputs ("\t.byte 0,", file);
9630 /* Language type. Unfortunately, there doesn't seem to be any
9631 official way to get this info, so we use language_string. C
9632 is 0. C++ is 9. No number defined for Obj-C, so use the
9633 value for C for now. There is no official value for Java,
9634 although IBM appears to be using 13. There is no official value
9635 for Chill, so we've chosen 44 pseudo-randomly. */
9636 if (! strcmp (language_string, "GNU C")
9637 || ! strcmp (language_string, "GNU Objective-C"))
9639 else if (! strcmp (language_string, "GNU F77"))
9641 else if (! strcmp (language_string, "GNU Ada"))
9643 else if (! strcmp (language_string, "GNU Pascal"))
9645 else if (! strcmp (language_string, "GNU C++"))
9647 else if (! strcmp (language_string, "GNU Java"))
9649 else if (! strcmp (language_string, "GNU CHILL"))
9653 fprintf (file, "%d,", i);
9655 /* 8 single bit fields: global linkage (not set for C extern linkage,
9656 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
9657 from start of procedure stored in tbtab, internal function, function
9658 has controlled storage, function has no toc, function uses fp,
9659 function logs/aborts fp operations. */
9660 /* Assume that fp operations are used if any fp reg must be saved. */
9661 fprintf (file, "%d,",
9662 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
9664 /* 6 bitfields: function is interrupt handler, name present in
9665 proc table, function calls alloca, on condition directives
9666 (controls stack walks, 3 bits), saves condition reg, saves
9668 /* The `function calls alloca' bit seems to be set whenever reg 31 is
9669 set up as a frame pointer, even when there is no alloca call. */
9670 fprintf (file, "%d,",
9671 ((optional_tbtab << 6)
9672 | ((optional_tbtab & frame_pointer_needed) << 5)
9673 | (info->cr_save_p << 1)
9674 | (info->lr_save_p)));
9676 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
9678 fprintf (file, "%d,",
9679 (info->push_p << 7) | (64 - info->first_fp_reg_save));
9681 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
9682 fprintf (file, "%d,", (32 - first_reg_to_save ()));
9686 /* Compute the parameter info from the function decl argument
9689 int next_parm_info_bit = 31;
9691 for (decl = DECL_ARGUMENTS (current_function_decl);
9692 decl; decl = TREE_CHAIN (decl))
9694 rtx parameter = DECL_INCOMING_RTL (decl);
9695 enum machine_mode mode = GET_MODE (parameter);
9697 if (GET_CODE (parameter) == REG)
9699 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
9707 else if (mode == DFmode)
9712 /* If only one bit will fit, don't or in this entry. */
9713 if (next_parm_info_bit > 0)
9714 parm_info |= (bits << (next_parm_info_bit - 1));
9715 next_parm_info_bit -= 2;
9719 fixed_parms += ((GET_MODE_SIZE (mode)
9720 + (UNITS_PER_WORD - 1))
9722 next_parm_info_bit -= 1;
9728 /* Number of fixed point parameters. */
9729 /* This is actually the number of words of fixed point parameters; thus
9730 an 8 byte struct counts as 2; and thus the maximum value is 8. */
9731 fprintf (file, "%d,", fixed_parms);
9733 /* 2 bitfields: number of floating point parameters (7 bits), parameters
9735 /* This is actually the number of fp registers that hold parameters;
9736 and thus the maximum value is 13. */
9737 /* Set parameters on stack bit if parameters are not in their original
9738 registers, regardless of whether they are on the stack? Xlc
9739 seems to set the bit when not optimizing. */
9740 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
9742 if (! optional_tbtab)
9745 /* Optional fields follow. Some are variable length. */
9747 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
9749 /* There is an entry for each parameter in a register, in the order that
9750 they occur in the parameter list. Any intervening arguments on the
9751 stack are ignored. If the list overflows a long (max possible length
9752 34 bits) then completely leave off all elements that don't fit. */
9753 /* Only emit this long if there was at least one parameter. */
9754 if (fixed_parms || float_parms)
9755 fprintf (file, "\t.long %d\n", parm_info);
9757 /* Offset from start of code to tb table. */
9758 fputs ("\t.long ", file);
9759 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
9761 RS6000_OUTPUT_BASENAME (file, fname);
9763 assemble_name (file, fname);
9767 RS6000_OUTPUT_BASENAME (file, fname);
9769 assemble_name (file, fname);
9773 /* Interrupt handler mask. */
9774 /* Omit this long, since we never set the interrupt handler bit
9777 /* Number of CTL (controlled storage) anchors. */
9778 /* Omit this long, since the has_ctl bit is never set above. */
9780 /* Displacement into stack of each CTL anchor. */
9781 /* Omit this list of longs, because there are no CTL anchors. */
9783 /* Length of function name. */
9784 fprintf (file, "\t.short %d\n", (int) strlen (fname));
9786 /* Function name. */
9787 assemble_string (fname, strlen (fname));
9789 /* Register for alloca automatic storage; this is always reg 31.
9790 Only emit this if the alloca bit was set above. */
9791 if (frame_pointer_needed)
9792 fputs ("\t.byte 31\n", file);
9794 fputs ("\t.align 2\n", file);
9799 /* A C compound statement that outputs the assembler code for a thunk
9800 function, used to implement C++ virtual function calls with
9801 multiple inheritance. The thunk acts as a wrapper around a virtual
9802 function, adjusting the implicit object parameter before handing
9803 control off to the real function.
9805 First, emit code to add the integer DELTA to the location that
9806 contains the incoming first argument. Assume that this argument
9807 contains a pointer, and is the one used to pass the `this' pointer
9808 in C++. This is the incoming argument *before* the function
9809 prologue, e.g. `%o0' on a sparc. The addition must preserve the
9810 values of all other incoming arguments.
9812 After the addition, emit code to jump to FUNCTION, which is a
9813 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
9814 not touch the return address. Hence returning from FUNCTION will
9815 return to whoever called the current `thunk'.
9817 The effect must be as if FUNCTION had been called directly with the
9818 adjusted first argument. This macro is responsible for emitting
9819 all of the code for a thunk function; output_function_prologue()
9820 and output_function_epilogue() are not invoked.
9822 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
9823 been extracted from it.) It might possibly be useful on some
9824 targets, but probably not.
9826 If you do not define this macro, the target-independent code in the
9827 C++ frontend will generate a less efficient heavyweight thunk that
9828 calls FUNCTION instead of jumping to it. The generic approach does
9829 not support varargs. */
9832 output_mi_thunk (file, thunk_fndecl, delta, function)
9834 tree thunk_fndecl ATTRIBUTE_UNUSED;
9838 const char *this_reg =
9839 reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ];
9842 const char *r0 = reg_names[0];
9843 const char *toc = reg_names[2];
9844 const char *schain = reg_names[11];
9845 const char *r12 = reg_names[12];
9847 static int labelno = 0;
9849 /* Small constants that can be done by one add instruction. */
9850 if (delta >= -32768 && delta <= 32767)
9852 if (! TARGET_NEW_MNEMONICS)
9853 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg);
9855 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta);
9858 /* Large constants that can be done by one addis instruction. */
9859 else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1)
9860 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
9863 /* 32-bit constants that can be done by an add and addis instruction. */
9864 else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1)
9866 /* Break into two pieces, propagating the sign bit from the low
9867 word to the upper word. */
9868 int delta_high = delta >> 16;
9869 int delta_low = delta & 0xffff;
9870 if ((delta_low & 0x8000) != 0)
9873 delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */
9876 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
9879 if (! TARGET_NEW_MNEMONICS)
9880 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg);
9882 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low);
9885 /* 64-bit constants, fixme */
9889 /* Get the prefix in front of the names. */
9890 switch (DEFAULT_ABI)
9900 case ABI_AIX_NODESC:
9905 /* If the function is compiled in this module, jump to it directly.
9906 Otherwise, load up its address and jump to it. */
9908 fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
9910 if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode)
9911 && (! lookup_attribute ("longcall",
9912 TYPE_ATTRIBUTES (TREE_TYPE (function)))
9913 || lookup_attribute ("shortcall",
9914 TYPE_ATTRIBUTES (TREE_TYPE (function)))))
9917 fprintf (file, "\tb %s", prefix);
9918 assemble_name (file, fname);
9919 if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file);
9925 switch (DEFAULT_ABI)
9931 /* Set up a TOC entry for the function. */
9932 ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno);
9934 ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno);
9937 if (TARGET_MINIMAL_TOC)
9938 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
9941 fputs ("\t.tc ", file);
9942 assemble_name (file, fname);
9943 fputs ("[TC],", file);
9945 assemble_name (file, fname);
9948 if (TARGET_MINIMAL_TOC)
9949 asm_fprintf (file, (TARGET_32BIT)
9950 ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12,
9951 TARGET_ELF ? ".LCTOC0@toc" : ".LCTOC..1", toc);
9952 asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12);
9953 assemble_name (file, buf);
9954 if (TARGET_ELF && TARGET_MINIMAL_TOC)
9955 fputs ("-(.LCTOC1)", file);
9956 asm_fprintf (file, "(%s)\n", TARGET_MINIMAL_TOC ? r12 : toc);
9958 (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n",
9962 (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n",
9965 asm_fprintf (file, "\tmtctr %s\n", r0);
9967 (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n",
9970 asm_fprintf (file, "\tbctr\n");
9973 case ABI_AIX_NODESC:
9975 fprintf (file, "\tb %s", prefix);
9976 assemble_name (file, fname);
9977 if (flag_pic) fputs ("@plt", file);
9983 fprintf (file, "\tb %s", prefix);
9984 if (flag_pic && !machopic_name_defined_p (fname))
9985 assemble_name (file, machopic_stub_name (fname));
9987 assemble_name (file, fname);
9996 /* A quick summary of the various types of 'constant-pool tables'
9999 Target Flags Name One table per
10000 AIX (none) AIX TOC object file
10001 AIX -mfull-toc AIX TOC object file
10002 AIX -mminimal-toc AIX minimal TOC translation unit
10003 SVR4/EABI (none) SVR4 SDATA object file
10004 SVR4/EABI -fpic SVR4 pic object file
10005 SVR4/EABI -fPIC SVR4 PIC translation unit
10006 SVR4/EABI -mrelocatable EABI TOC function
10007 SVR4/EABI -maix AIX TOC object file
10008 SVR4/EABI -maix -mminimal-toc
10009 AIX minimal TOC translation unit
10011 Name Reg. Set by entries contains:
10012 made by addrs? fp? sum?
10014 AIX TOC 2 crt0 as Y option option
10015 AIX minimal TOC 30 prolog gcc Y Y option
10016 SVR4 SDATA 13 crt0 gcc N Y N
10017 SVR4 pic 30 prolog ld Y not yet N
10018 SVR4 PIC 30 prolog gcc Y option option
10019 EABI TOC 30 prolog gcc Y option option
10023 /* Hash table stuff for keeping track of TOC entries. */
10025 struct toc_hash_struct
10027 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
10028 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
10030 enum machine_mode key_mode;
10034 static htab_t toc_hash_table;
10036 /* Hash functions for the hash table. */
10039 rs6000_hash_constant (k)
10042 unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k);
10043 const char *format = GET_RTX_FORMAT (GET_CODE (k));
10044 int flen = strlen (format);
10047 if (GET_CODE (k) == LABEL_REF)
10048 return result * 1231 + X0INT (XEXP (k, 0), 3);
10050 if (GET_CODE (k) == CODE_LABEL)
10055 for (; fidx < flen; fidx++)
10056 switch (format[fidx])
10061 const char *str = XSTR (k, fidx);
10062 len = strlen (str);
10063 result = result * 613 + len;
10064 for (i = 0; i < len; i++)
10065 result = result * 613 + (unsigned) str[i];
10070 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
10074 result = result * 613 + (unsigned) XINT (k, fidx);
10077 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
10078 result = result * 613 + (unsigned) XWINT (k, fidx);
10082 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
10083 result = result * 613 + (unsigned) (XWINT (k, fidx)
10094 toc_hash_function (hash_entry)
10095 const void * hash_entry;
10097 const struct toc_hash_struct *thc =
10098 (const struct toc_hash_struct *) hash_entry;
10099 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
10102 /* Compare H1 and H2 for equivalence. */
10105 toc_hash_eq (h1, h2)
10109 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
10110 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
10112 if (((const struct toc_hash_struct *) h1)->key_mode
10113 != ((const struct toc_hash_struct *) h2)->key_mode)
10116 return rtx_equal_p (r1, r2);
10119 /* Mark the hash table-entry HASH_ENTRY. */
10122 toc_hash_mark_entry (hash_slot, unused)
10124 void * unused ATTRIBUTE_UNUSED;
10126 const struct toc_hash_struct * hash_entry =
10127 *(const struct toc_hash_struct **) hash_slot;
10128 rtx r = hash_entry->key;
10129 ggc_set_mark (hash_entry);
10130 /* For CODE_LABELS, we don't want to drag in the whole insn chain... */
10131 if (GET_CODE (r) == LABEL_REF)
10134 ggc_set_mark (XEXP (r, 0));
10141 /* Mark all the elements of the TOC hash-table *HT. */
10144 toc_hash_mark_table (vht)
10149 htab_traverse (*ht, toc_hash_mark_entry, (void *)0);
10152 /* These are the names given by the C++ front-end to vtables, and
10153 vtable-like objects. Ideally, this logic should not be here;
10154 instead, there should be some programmatic way of inquiring as
10155 to whether or not an object is a vtable. */
10157 #define VTABLE_NAME_P(NAME) \
10158 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
10159 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
10160 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
10161 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
10164 rs6000_output_symbol_ref (file, x)
10168 /* Currently C++ toc references to vtables can be emitted before it
10169 is decided whether the vtable is public or private. If this is
10170 the case, then the linker will eventually complain that there is
10171 a reference to an unknown section. Thus, for vtables only,
10172 we emit the TOC reference to reference the symbol and not the
10174 const char *name = XSTR (x, 0);
10176 if (VTABLE_NAME_P (name))
10178 RS6000_OUTPUT_BASENAME (file, name);
10181 assemble_name (file, name);
10184 /* Output a TOC entry. We derive the entry name from what is being
10188 output_toc (file, x, labelno, mode)
10192 enum machine_mode mode;
10195 const char *name = buf;
10196 const char *real_name;
10203 /* When the linker won't eliminate them, don't output duplicate
10204 TOC entries (this happens on AIX if there is any kind of TOC,
10205 and on SVR4 under -fPIC or -mrelocatable). */
10208 struct toc_hash_struct *h;
10211 h = ggc_alloc (sizeof (*h));
10213 h->key_mode = mode;
10214 h->labelno = labelno;
10216 found = htab_find_slot (toc_hash_table, h, 1);
10217 if (*found == NULL)
10219 else /* This is indeed a duplicate.
10220 Set this label equal to that label. */
10222 fputs ("\t.set ", file);
10223 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
10224 fprintf (file, "%d,", labelno);
10225 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
10226 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
10232 /* If we're going to put a double constant in the TOC, make sure it's
10233 aligned properly when strict alignment is on. */
10234 if (GET_CODE (x) == CONST_DOUBLE
10235 && STRICT_ALIGNMENT
10236 && GET_MODE_BITSIZE (mode) >= 64
10237 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
10238 ASM_OUTPUT_ALIGN (file, 3);
10241 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
10243 /* Handle FP constants specially. Note that if we have a minimal
10244 TOC, things we put here aren't actually in the TOC, so we can allow
10246 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
10248 REAL_VALUE_TYPE rv;
10251 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
10252 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
10256 if (TARGET_MINIMAL_TOC)
10257 fputs (DOUBLE_INT_ASM_OP, file);
10259 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
10260 fprintf (file, "0x%lx%08lx\n", k[0], k[1]);
10265 if (TARGET_MINIMAL_TOC)
10266 fputs ("\t.long ", file);
10268 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
10269 fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]);
10273 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
10275 REAL_VALUE_TYPE rv;
10278 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
10279 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
10283 if (TARGET_MINIMAL_TOC)
10284 fputs (DOUBLE_INT_ASM_OP, file);
10286 fprintf (file, "\t.tc FS_%lx[TC],", l);
10287 fprintf (file, "0x%lx00000000\n", l);
10292 if (TARGET_MINIMAL_TOC)
10293 fputs ("\t.long ", file);
10295 fprintf (file, "\t.tc FS_%lx[TC],", l);
10296 fprintf (file, "0x%lx\n", l);
10300 else if (GET_MODE (x) == VOIDmode
10301 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
10303 unsigned HOST_WIDE_INT low;
10304 HOST_WIDE_INT high;
10306 if (GET_CODE (x) == CONST_DOUBLE)
10308 low = CONST_DOUBLE_LOW (x);
10309 high = CONST_DOUBLE_HIGH (x);
10312 #if HOST_BITS_PER_WIDE_INT == 32
10315 high = (low & 0x80000000) ? ~0 : 0;
10319 low = INTVAL (x) & 0xffffffff;
10320 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
10324 /* TOC entries are always Pmode-sized, but since this
10325 is a bigendian machine then if we're putting smaller
10326 integer constants in the TOC we have to pad them.
10327 (This is still a win over putting the constants in
10328 a separate constant pool, because then we'd have
10329 to have both a TOC entry _and_ the actual constant.)
10331 For a 32-bit target, CONST_INT values are loaded and shifted
10332 entirely within `low' and can be stored in one TOC entry. */
10334 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
10335 abort ();/* It would be easy to make this work, but it doesn't now. */
10337 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
10338 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
10339 POINTER_SIZE, &low, &high, 0);
10343 if (TARGET_MINIMAL_TOC)
10344 fputs (DOUBLE_INT_ASM_OP, file);
10346 fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long) high, (long) low);
10347 fprintf (file, "0x%lx%08lx\n", (long) high, (long) low);
10352 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
10354 if (TARGET_MINIMAL_TOC)
10355 fputs ("\t.long ", file);
10357 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
10358 (long) high, (long) low);
10359 fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low);
10363 if (TARGET_MINIMAL_TOC)
10364 fputs ("\t.long ", file);
10366 fprintf (file, "\t.tc IS_%lx[TC],", (long) low);
10367 fprintf (file, "0x%lx\n", (long) low);
10373 if (GET_CODE (x) == CONST)
10375 if (GET_CODE (XEXP (x, 0)) != PLUS)
10378 base = XEXP (XEXP (x, 0), 0);
10379 offset = INTVAL (XEXP (XEXP (x, 0), 1));
10382 if (GET_CODE (base) == SYMBOL_REF)
10383 name = XSTR (base, 0);
10384 else if (GET_CODE (base) == LABEL_REF)
10385 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
10386 else if (GET_CODE (base) == CODE_LABEL)
10387 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
10391 real_name = (*targetm.strip_name_encoding) (name);
10392 if (TARGET_MINIMAL_TOC)
10393 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
10396 fprintf (file, "\t.tc %s", real_name);
10399 fprintf (file, ".N%d", - offset);
10401 fprintf (file, ".P%d", offset);
10403 fputs ("[TC],", file);
10406 /* Currently C++ toc references to vtables can be emitted before it
10407 is decided whether the vtable is public or private. If this is
10408 the case, then the linker will eventually complain that there is
10409 a TOC reference to an unknown section. Thus, for vtables only,
10410 we emit the TOC reference to reference the symbol and not the
10412 if (VTABLE_NAME_P (name))
10414 RS6000_OUTPUT_BASENAME (file, name);
10416 fprintf (file, "%d", offset);
10417 else if (offset > 0)
10418 fprintf (file, "+%d", offset);
10421 output_addr_const (file, x);
10425 /* Output an assembler pseudo-op to write an ASCII string of N characters
10426 starting at P to FILE.
10428 On the RS/6000, we have to do this using the .byte operation and
10429 write out special characters outside the quoted string.
10430 Also, the assembler is broken; very long strings are truncated,
10431 so we must artificially break them up early. */
10434 output_ascii (file, p, n)
10440 int i, count_string;
10441 const char *for_string = "\t.byte \"";
10442 const char *for_decimal = "\t.byte ";
10443 const char *to_close = NULL;
10446 for (i = 0; i < n; i++)
10449 if (c >= ' ' && c < 0177)
10452 fputs (for_string, file);
10455 /* Write two quotes to get one. */
10463 for_decimal = "\"\n\t.byte ";
10467 if (count_string >= 512)
10469 fputs (to_close, file);
10471 for_string = "\t.byte \"";
10472 for_decimal = "\t.byte ";
10480 fputs (for_decimal, file);
10481 fprintf (file, "%d", c);
10483 for_string = "\n\t.byte \"";
10484 for_decimal = ", ";
10490 /* Now close the string if we have written one. Then end the line. */
10492 fputs (to_close, file);
10495 /* Generate a unique section name for FILENAME for a section type
10496 represented by SECTION_DESC. Output goes into BUF.
10498 SECTION_DESC can be any string, as long as it is different for each
10499 possible section type.
10501 We name the section in the same manner as xlc. The name begins with an
10502 underscore followed by the filename (after stripping any leading directory
10503 names) with the last period replaced by the string SECTION_DESC. If
10504 FILENAME does not contain a period, SECTION_DESC is appended to the end of
10508 rs6000_gen_section_name (buf, filename, section_desc)
10510 const char *filename;
10511 const char *section_desc;
10513 const char *q, *after_last_slash, *last_period = 0;
10517 after_last_slash = filename;
10518 for (q = filename; *q; q++)
10521 after_last_slash = q + 1;
10522 else if (*q == '.')
10526 len = strlen (after_last_slash) + strlen (section_desc) + 2;
10527 *buf = (char *) permalloc (len);
10532 for (q = after_last_slash; *q; q++)
10534 if (q == last_period)
10536 strcpy (p, section_desc);
10537 p += strlen (section_desc);
10540 else if (ISALNUM (*q))
10544 if (last_period == 0)
10545 strcpy (p, section_desc);
10550 /* Emit profile function. */
10553 output_profile_hook (labelno)
10556 if (DEFAULT_ABI == ABI_AIX)
10559 const char *label_name;
10562 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10563 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
10564 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
10566 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
10569 else if (DEFAULT_ABI == ABI_DARWIN)
10571 const char *mcount_name = RS6000_MCOUNT;
10572 int caller_addr_regno = LINK_REGISTER_REGNUM;
10574 /* Be conservative and always set this, at least for now. */
10575 current_function_uses_pic_offset_table = 1;
10578 /* For PIC code, set up a stub and collect the caller's address
10579 from r0, which is where the prologue puts it. */
10582 mcount_name = machopic_stub_name (mcount_name);
10583 if (current_function_uses_pic_offset_table)
10584 caller_addr_regno = 0;
10587 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
10589 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
10593 /* Write function profiler code. */
10596 output_function_profiler (file, labelno)
10602 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10603 switch (DEFAULT_ABI)
10609 case ABI_AIX_NODESC:
10610 fprintf (file, "\tmflr %s\n", reg_names[0]);
10613 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
10614 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
10615 reg_names[0], reg_names[1]);
10616 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
10617 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
10618 assemble_name (file, buf);
10619 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
10621 else if (flag_pic > 1)
10623 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
10624 reg_names[0], reg_names[1]);
10625 /* Now, we need to get the address of the label. */
10626 fputs ("\tbl 1f\n\t.long ", file);
10627 assemble_name (file, buf);
10628 fputs ("-.\n1:", file);
10629 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
10630 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
10631 reg_names[0], reg_names[11]);
10632 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
10633 reg_names[0], reg_names[0], reg_names[11]);
10637 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
10638 assemble_name (file, buf);
10639 fputs ("@ha\n", file);
10640 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
10641 reg_names[0], reg_names[1]);
10642 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
10643 assemble_name (file, buf);
10644 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
10647 if (current_function_needs_context)
10648 asm_fprintf (file, "\tmr %s,%s\n",
10649 reg_names[30], reg_names[STATIC_CHAIN_REGNUM]);
10650 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
10651 if (current_function_needs_context)
10652 asm_fprintf (file, "\tmr %s,%s\n",
10653 reg_names[STATIC_CHAIN_REGNUM], reg_names[30]);
10658 /* Don't do anything, done in output_profile_hook (). */
10664 /* Adjust the cost of a scheduling dependency. Return the new cost of
10665 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
10668 rs6000_adjust_cost (insn, link, dep_insn, cost)
10671 rtx dep_insn ATTRIBUTE_UNUSED;
10674 if (! recog_memoized (insn))
10677 if (REG_NOTE_KIND (link) != 0)
10680 if (REG_NOTE_KIND (link) == 0)
10682 /* Data dependency; DEP_INSN writes a register that INSN reads
10683 some cycles later. */
10684 switch (get_attr_type (insn))
10687 /* Tell the first scheduling pass about the latency between
10688 a mtctr and bctr (and mtlr and br/blr). The first
10689 scheduling pass will not know about this latency since
10690 the mtctr instruction, which has the latency associated
10691 to it, will be generated by reload. */
10692 return TARGET_POWER ? 5 : 4;
10694 /* Leave some extra cycles between a compare and its
10695 dependent branch, to inhibit expensive mispredicts. */
10696 if ((rs6000_cpu_attr == CPU_PPC750
10697 || rs6000_cpu_attr == CPU_PPC7400
10698 || rs6000_cpu_attr == CPU_PPC7450)
10699 && recog_memoized (dep_insn)
10700 && (INSN_CODE (dep_insn) >= 0)
10701 && (get_attr_type (dep_insn) == TYPE_COMPARE
10702 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
10703 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
10704 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL))
10709 /* Fall out to return default cost. */
10715 /* A C statement (sans semicolon) to update the integer scheduling
10716 priority INSN_PRIORITY (INSN). Reduce the priority to execute the
10717 INSN earlier, increase the priority to execute INSN later. Do not
10718 define this macro if you do not need to adjust the scheduling
10719 priorities of insns. */
10722 rs6000_adjust_priority (insn, priority)
10723 rtx insn ATTRIBUTE_UNUSED;
10726 /* On machines (like the 750) which have asymmetric integer units,
10727 where one integer unit can do multiply and divides and the other
10728 can't, reduce the priority of multiply/divide so it is scheduled
10729 before other integer operations. */
10732 if (! INSN_P (insn))
10735 if (GET_CODE (PATTERN (insn)) == USE)
10738 switch (rs6000_cpu_attr) {
10740 switch (get_attr_type (insn))
10747 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
10748 priority, priority);
10749 if (priority >= 0 && priority < 0x01000000)
10759 /* Return how many instructions the machine can issue per cycle. */
10762 rs6000_issue_rate ()
10764 switch (rs6000_cpu_attr) {
10765 case CPU_RIOS1: /* ? */
10767 case CPU_PPC601: /* ? */
10786 /* Length in units of the trampoline for entering a nested function. */
10789 rs6000_trampoline_size ()
10793 switch (DEFAULT_ABI)
10799 ret = (TARGET_32BIT) ? 12 : 24;
10804 case ABI_AIX_NODESC:
10805 ret = (TARGET_32BIT) ? 40 : 48;
10812 /* Emit RTL insns to initialize the variable parts of a trampoline.
10813 FNADDR is an RTX for the address of the function's pure code.
10814 CXT is an RTX for the static chain value for the function. */
10817 rs6000_initialize_trampoline (addr, fnaddr, cxt)
10822 enum machine_mode pmode = Pmode;
10823 int regsize = (TARGET_32BIT) ? 4 : 8;
10824 rtx ctx_reg = force_reg (pmode, cxt);
10826 switch (DEFAULT_ABI)
10831 /* Macros to shorten the code expansions below. */
10832 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
10833 #define MEM_PLUS(addr,offset) \
10834 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
10836 /* Under AIX, just build the 3 word function descriptor */
10839 rtx fn_reg = gen_reg_rtx (pmode);
10840 rtx toc_reg = gen_reg_rtx (pmode);
10841 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
10842 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
10843 emit_move_insn (MEM_DEREF (addr), fn_reg);
10844 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
10845 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
10849 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
10852 case ABI_AIX_NODESC:
10853 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
10854 FALSE, VOIDmode, 4,
10856 GEN_INT (rs6000_trampoline_size ()), SImode,
10866 /* Table of valid machine attributes. */
10868 const struct attribute_spec rs6000_attribute_table[] =
10870 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
10871 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
10872 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
10873 { NULL, 0, 0, false, false, false, NULL }
10876 /* Handle a "longcall" or "shortcall" attribute; arguments as in
10877 struct attribute_spec.handler. */
10880 rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs)
10883 tree args ATTRIBUTE_UNUSED;
10884 int flags ATTRIBUTE_UNUSED;
10885 bool *no_add_attrs;
10887 if (TREE_CODE (*node) != FUNCTION_TYPE
10888 && TREE_CODE (*node) != FIELD_DECL
10889 && TREE_CODE (*node) != TYPE_DECL)
10891 warning ("`%s' attribute only applies to functions",
10892 IDENTIFIER_POINTER (name));
10893 *no_add_attrs = true;
10899 /* Set longcall attributes on all functions declared when
10900 rs6000_default_long_calls is true. */
10902 rs6000_set_default_type_attributes (type)
10905 if (rs6000_default_long_calls
10906 && (TREE_CODE (type) == FUNCTION_TYPE
10907 || TREE_CODE (type) == METHOD_TYPE))
10908 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
10910 TYPE_ATTRIBUTES (type));
10913 /* Return a reference suitable for calling a function with the
10914 longcall attribute. */
10917 rs6000_longcall_ref (call_ref)
10920 const char *call_name;
10923 if (GET_CODE (call_ref) != SYMBOL_REF)
10926 /* System V adds '.' to the internal name, so skip them. */
10927 call_name = XSTR (call_ref, 0);
10928 if (*call_name == '.')
10930 while (*call_name == '.')
10933 node = get_identifier (call_name);
10934 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
10937 return force_reg (Pmode, call_ref);
10941 #ifdef USING_ELFOS_H
10943 /* A C statement or statements to switch to the appropriate section
10944 for output of RTX in mode MODE. You can assume that RTX is some
10945 kind of constant in RTL. The argument MODE is redundant except in
10946 the case of a `const_int' rtx. Select the section by calling
10947 `text_section' or one of the alternatives for other sections.
10949 Do not define this macro if you put all constants in the read-only
10953 rs6000_elf_select_rtx_section (mode, x, align)
10954 enum machine_mode mode;
10956 unsigned HOST_WIDE_INT align;
10958 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
10961 default_elf_select_rtx_section (mode, x, align);
10964 /* A C statement or statements to switch to the appropriate
10965 section for output of DECL. DECL is either a `VAR_DECL' node
10966 or a constant of some sort. RELOC indicates whether forming
10967 the initial value of DECL requires link-time relocations. */
10970 rs6000_elf_select_section (decl, reloc, align)
10973 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
10975 int size = int_size_in_bytes (TREE_TYPE (decl));
10978 static void (* const sec_funcs[4]) PARAMS ((void)) = {
10979 &readonly_data_section,
10985 needs_sdata = (size > 0
10986 && size <= g_switch_value
10987 && rs6000_sdata != SDATA_NONE
10988 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
10990 if (TREE_CODE (decl) == STRING_CST)
10991 readonly = ! flag_writable_strings;
10992 else if (TREE_CODE (decl) == VAR_DECL)
10993 readonly = (! (flag_pic && reloc)
10994 && TREE_READONLY (decl)
10995 && ! TREE_SIDE_EFFECTS (decl)
10996 && DECL_INITIAL (decl)
10997 && DECL_INITIAL (decl) != error_mark_node
10998 && TREE_CONSTANT (DECL_INITIAL (decl)));
10999 else if (TREE_CODE (decl) == CONSTRUCTOR)
11000 readonly = (! (flag_pic && reloc)
11001 && ! TREE_SIDE_EFFECTS (decl)
11002 && TREE_CONSTANT (decl));
11005 if (needs_sdata && rs6000_sdata != SDATA_EABI)
11008 (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])();
11011 /* A C statement to build up a unique section name, expressed as a
11012 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
11013 RELOC indicates whether the initial value of EXP requires
11014 link-time relocations. If you do not define this macro, GCC will use
11015 the symbol name prefixed by `.' as the section name. Note - this
11016 macro can now be called for uninitialized data items as well as
11017 initialised data and functions. */
11020 rs6000_elf_unique_section (decl, reloc)
11028 const char *prefix;
11030 static const char *const prefixes[7][2] =
11032 { ".rodata.", ".gnu.linkonce.r." },
11033 { ".sdata2.", ".gnu.linkonce.s2." },
11034 { ".data.", ".gnu.linkonce.d." },
11035 { ".sdata.", ".gnu.linkonce.s." },
11036 { ".bss.", ".gnu.linkonce.b." },
11037 { ".sbss.", ".gnu.linkonce.sb." },
11038 { ".text.", ".gnu.linkonce.t." }
11041 if (TREE_CODE (decl) == FUNCTION_DECL)
11050 if (TREE_CODE (decl) == STRING_CST)
11051 readonly = ! flag_writable_strings;
11052 else if (TREE_CODE (decl) == VAR_DECL)
11053 readonly = (! (flag_pic && reloc)
11054 && TREE_READONLY (decl)
11055 && ! TREE_SIDE_EFFECTS (decl)
11056 && TREE_CONSTANT (DECL_INITIAL (decl)));
11058 size = int_size_in_bytes (TREE_TYPE (decl));
11059 needs_sdata = (size > 0
11060 && size <= g_switch_value
11061 && rs6000_sdata != SDATA_NONE
11062 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
11064 if (DECL_INITIAL (decl) == 0
11065 || DECL_INITIAL (decl) == error_mark_node)
11067 else if (! readonly)
11074 /* .sdata2 is only for EABI. */
11075 if (sec == 0 && rs6000_sdata != SDATA_EABI)
11081 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
11082 name = (*targetm.strip_name_encoding) (name);
11083 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
11084 len = strlen (name) + strlen (prefix);
11085 string = alloca (len + 1);
11087 sprintf (string, "%s%s", prefix, name);
11089 DECL_SECTION_NAME (decl) = build_string (len, string);
11093 /* If we are referencing a function that is static or is known to be
11094 in this file, make the SYMBOL_REF special. We can use this to indicate
11095 that we can branch to this function without emitting a no-op after the
11096 call. For real AIX calling sequences, we also replace the
11097 function name with the real name (1 or 2 leading .'s), rather than
11098 the function descriptor name. This saves a lot of overriding code
11099 to read the prefixes. */
11102 rs6000_elf_encode_section_info (decl, first)
11109 if (TREE_CODE (decl) == FUNCTION_DECL)
11111 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
11112 if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
11113 && ! DECL_WEAK (decl))
11114 SYMBOL_REF_FLAG (sym_ref) = 1;
11116 if (DEFAULT_ABI == ABI_AIX)
11118 size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2;
11119 size_t len2 = strlen (XSTR (sym_ref, 0));
11120 char *str = alloca (len1 + len2 + 1);
11123 memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1);
11125 XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2);
11128 else if (rs6000_sdata != SDATA_NONE
11129 && DEFAULT_ABI == ABI_V4
11130 && TREE_CODE (decl) == VAR_DECL)
11132 int size = int_size_in_bytes (TREE_TYPE (decl));
11133 tree section_name = DECL_SECTION_NAME (decl);
11134 const char *name = (char *)0;
11139 if (TREE_CODE (section_name) == STRING_CST)
11141 name = TREE_STRING_POINTER (section_name);
11142 len = TREE_STRING_LENGTH (section_name);
11148 if ((size > 0 && size <= g_switch_value)
11150 && ((len == sizeof (".sdata") - 1
11151 && strcmp (name, ".sdata") == 0)
11152 || (len == sizeof (".sdata2") - 1
11153 && strcmp (name, ".sdata2") == 0)
11154 || (len == sizeof (".sbss") - 1
11155 && strcmp (name, ".sbss") == 0)
11156 || (len == sizeof (".sbss2") - 1
11157 && strcmp (name, ".sbss2") == 0)
11158 || (len == sizeof (".PPC.EMB.sdata0") - 1
11159 && strcmp (name, ".PPC.EMB.sdata0") == 0)
11160 || (len == sizeof (".PPC.EMB.sbss0") - 1
11161 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
11163 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
11164 size_t len = strlen (XSTR (sym_ref, 0));
11165 char *str = alloca (len + 2);
11168 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
11169 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
11174 static const char *
11175 rs6000_elf_strip_name_encoding (str)
11178 while (*str == '*' || *str == '@')
11183 #endif /* USING_ELFOS_H */
11186 /* Return a REG that occurs in ADDR with coefficient 1.
11187 ADDR can be effectively incremented by incrementing REG.
11189 r0 is special and we must not select it as an address
11190 register by this routine since our caller will try to
11191 increment the returned register via an "la" instruction. */
11194 find_addr_reg (addr)
11197 while (GET_CODE (addr) == PLUS)
11199 if (GET_CODE (XEXP (addr, 0)) == REG
11200 && REGNO (XEXP (addr, 0)) != 0)
11201 addr = XEXP (addr, 0);
11202 else if (GET_CODE (XEXP (addr, 1)) == REG
11203 && REGNO (XEXP (addr, 1)) != 0)
11204 addr = XEXP (addr, 1);
11205 else if (CONSTANT_P (XEXP (addr, 0)))
11206 addr = XEXP (addr, 1);
11207 else if (CONSTANT_P (XEXP (addr, 1)))
11208 addr = XEXP (addr, 0);
11212 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
11218 rs6000_fatal_bad_address (op)
11221 fatal_insn ("bad address", op);
11224 /* Called to register all of our global variables with the garbage
11228 rs6000_add_gc_roots ()
11230 ggc_add_rtx_root (&rs6000_compare_op0, 1);
11231 ggc_add_rtx_root (&rs6000_compare_op1, 1);
11233 toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL);
11234 ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table),
11235 toc_hash_mark_table);
11238 machopic_add_gc_roots ();
11245 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
11246 reference and a constant. */
11249 symbolic_operand (op)
11252 switch (GET_CODE (op))
11259 return (GET_CODE (op) == SYMBOL_REF ||
11260 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
11261 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
11262 && GET_CODE (XEXP (op, 1)) == CONST_INT);
11269 #ifdef RS6000_LONG_BRANCH
11271 static tree stub_list = 0;
11273 /* ADD_COMPILER_STUB adds the compiler generated stub for handling
11274 procedure calls to the linked list. */
11277 add_compiler_stub (label_name, function_name, line_number)
11279 tree function_name;
11282 tree stub = build_tree_list (function_name, label_name);
11283 TREE_TYPE (stub) = build_int_2 (line_number, 0);
11284 TREE_CHAIN (stub) = stub_list;
11288 #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB)
11289 #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB)
11290 #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB))
11292 /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for
11293 handling procedure calls from the linked list and initializes the
11297 output_compiler_stub ()
11300 char label_buf[256];
11302 tree tmp_stub, stub;
11305 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
11307 fprintf (asm_out_file,
11308 "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub)));
11310 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
11311 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
11312 fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub));
11313 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
11315 if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*')
11317 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1);
11320 label_buf[0] = '_';
11321 strcpy (label_buf+1,
11322 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub)));
11325 strcpy (tmp_buf, "lis r12,hi16(");
11326 strcat (tmp_buf, label_buf);
11327 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
11328 strcat (tmp_buf, label_buf);
11329 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
11330 output_asm_insn (tmp_buf, 0);
11332 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
11333 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
11334 fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub));
11335 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
11341 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
11342 already there or not. */
11345 no_previous_def (function_name)
11346 tree function_name;
11349 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
11350 if (function_name == STUB_FUNCTION_NAME (stub))
11355 /* GET_PREV_LABEL gets the label name from the previous definition of
11359 get_prev_label (function_name)
11360 tree function_name;
11363 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
11364 if (function_name == STUB_FUNCTION_NAME (stub))
11365 return STUB_LABEL_NAME (stub);
11369 /* INSN is either a function call or a millicode call. It may have an
11370 unconditional jump in its delay slot.
11372 CALL_DEST is the routine we are calling. */
11375 output_call (insn, call_dest, operand_number)
11378 int operand_number;
11380 static char buf[256];
11381 if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic)
11384 tree funname = get_identifier (XSTR (call_dest, 0));
11386 if (no_previous_def (funname))
11389 rtx label_rtx = gen_label_rtx ();
11390 char *label_buf, temp_buf[256];
11391 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
11392 CODE_LABEL_NUMBER (label_rtx));
11393 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
11394 labelname = get_identifier (label_buf);
11395 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
11397 line_number = NOTE_LINE_NUMBER (insn);
11398 add_compiler_stub (labelname, funname, line_number);
11401 labelname = get_prev_label (funname);
11403 sprintf (buf, "jbsr %%z%d,%.246s",
11404 operand_number, IDENTIFIER_POINTER (labelname));
11409 sprintf (buf, "bl %%z%d", operand_number);
11414 #endif /* RS6000_LONG_BRANCH */
11416 #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \
11418 const char *const symbol_ = (SYMBOL); \
11419 char *buffer_ = (BUF); \
11420 if (symbol_[0] == '"') \
11422 sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \
11424 else if (name_needs_quotes(symbol_)) \
11426 sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \
11430 sprintf(buffer_, "L%d$%s", (N), symbol_); \
11435 /* Generate PIC and indirect symbol stubs. */
11438 machopic_output_stub (file, symb, stub)
11440 const char *symb, *stub;
11442 unsigned int length;
11443 char *symbol_name, *lazy_ptr_name;
11444 char *local_label_0;
11445 static int label = 0;
11447 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
11448 symb = (*targetm.strip_name_encoding) (symb);
11452 length = strlen (symb);
11453 symbol_name = alloca (length + 32);
11454 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
11456 lazy_ptr_name = alloca (length + 32);
11457 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
11459 local_label_0 = alloca (length + 32);
11460 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0);
11463 machopic_picsymbol_stub_section ();
11465 machopic_symbol_stub_section ();
11467 fprintf (file, "%s:\n", stub);
11468 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
11472 fprintf (file, "\tmflr r0\n");
11473 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
11474 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
11475 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
11476 lazy_ptr_name, local_label_0);
11477 fprintf (file, "\tmtlr r0\n");
11478 fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n",
11479 lazy_ptr_name, local_label_0);
11480 fprintf (file, "\tmtctr r12\n");
11481 fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n",
11482 lazy_ptr_name, local_label_0);
11483 fprintf (file, "\tbctr\n");
11486 fprintf (file, "non-pure not supported\n");
11488 machopic_lazy_symbol_ptr_section ();
11489 fprintf (file, "%s:\n", lazy_ptr_name);
11490 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
11491 fprintf (file, "\t.long dyld_stub_binding_helper\n");
11494 /* Legitimize PIC addresses. If the address is already
11495 position-independent, we return ORIG. Newly generated
11496 position-independent addresses go into a reg. This is REG if non
11497 zero, otherwise we allocate register(s) as necessary. */
11499 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
11502 rs6000_machopic_legitimize_pic_address (orig, mode, reg)
11504 enum machine_mode mode;
11509 if (reg == NULL && ! reload_in_progress && ! reload_completed)
11510 reg = gen_reg_rtx (Pmode);
11512 if (GET_CODE (orig) == CONST)
11514 if (GET_CODE (XEXP (orig, 0)) == PLUS
11515 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
11518 if (GET_CODE (XEXP (orig, 0)) == PLUS)
11521 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
11524 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
11530 if (GET_CODE (offset) == CONST_INT)
11532 if (SMALL_INT (offset))
11533 return plus_constant (base, INTVAL (offset));
11534 else if (! reload_in_progress && ! reload_completed)
11535 offset = force_reg (Pmode, offset);
11538 rtx mem = force_const_mem (Pmode, orig);
11539 return machopic_legitimize_pic_address (mem, Pmode, reg);
11542 return gen_rtx (PLUS, Pmode, base, offset);
11545 /* Fall back on generic machopic code. */
11546 return machopic_legitimize_pic_address (orig, mode, reg);
11549 /* This is just a placeholder to make linking work without having to
11550 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
11551 ever needed for Darwin (not too likely!) this would have to get a
11552 real definition. */
11559 #endif /* TARGET_MACHO */
11562 static unsigned int
11563 rs6000_elf_section_type_flags (decl, name, reloc)
11568 unsigned int flags = default_section_type_flags (decl, name, reloc);
11570 if (TARGET_RELOCATABLE)
11571 flags |= SECTION_WRITE;
11576 /* Record an element in the table of global constructors. SYMBOL is
11577 a SYMBOL_REF of the function to be called; PRIORITY is a number
11578 between 0 and MAX_INIT_PRIORITY.
11580 This differs from default_named_section_asm_out_constructor in
11581 that we have special handling for -mrelocatable. */
11584 rs6000_elf_asm_out_constructor (symbol, priority)
11588 const char *section = ".ctors";
11591 if (priority != DEFAULT_INIT_PRIORITY)
11593 sprintf (buf, ".ctors.%.5u",
11594 /* Invert the numbering so the linker puts us in the proper
11595 order; constructors are run from right to left, and the
11596 linker sorts in increasing order. */
11597 MAX_INIT_PRIORITY - priority);
11601 named_section_flags (section, SECTION_WRITE);
11602 assemble_align (POINTER_SIZE);
11604 if (TARGET_RELOCATABLE)
11606 fputs ("\t.long (", asm_out_file);
11607 output_addr_const (asm_out_file, symbol);
11608 fputs (")@fixup\n", asm_out_file);
11611 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
11615 rs6000_elf_asm_out_destructor (symbol, priority)
11619 const char *section = ".dtors";
11622 if (priority != DEFAULT_INIT_PRIORITY)
11624 sprintf (buf, ".dtors.%.5u",
11625 /* Invert the numbering so the linker puts us in the proper
11626 order; constructors are run from right to left, and the
11627 linker sorts in increasing order. */
11628 MAX_INIT_PRIORITY - priority);
11632 named_section_flags (section, SECTION_WRITE);
11633 assemble_align (POINTER_SIZE);
11635 if (TARGET_RELOCATABLE)
11637 fputs ("\t.long (", asm_out_file);
11638 output_addr_const (asm_out_file, symbol);
11639 fputs (")@fixup\n", asm_out_file);
11642 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
11646 #ifdef OBJECT_FORMAT_COFF
11648 xcoff_asm_named_section (name, flags)
11650 unsigned int flags ATTRIBUTE_UNUSED;
11652 fprintf (asm_out_file, "\t.csect %s\n", name);
11656 rs6000_xcoff_select_section (exp, reloc, align)
11659 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
11661 if ((TREE_CODE (exp) == STRING_CST
11662 && ! flag_writable_strings)
11663 || (TREE_CODE_CLASS (TREE_CODE (exp)) == 'd'
11664 && TREE_READONLY (exp) && ! TREE_THIS_VOLATILE (exp)
11665 && DECL_INITIAL (exp)
11666 && (DECL_INITIAL (exp) == error_mark_node
11667 || TREE_CONSTANT (DECL_INITIAL (exp)))
11670 if (TREE_PUBLIC (exp))
11671 read_only_data_section ();
11673 read_only_private_data_section ();
11677 if (TREE_PUBLIC (exp))
11680 private_data_section ();
11685 rs6000_xcoff_unique_section (decl, reloc)
11687 int reloc ATTRIBUTE_UNUSED;
11693 if (TREE_CODE (decl) == FUNCTION_DECL)
11695 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
11696 len = strlen (name) + 5;
11697 string = alloca (len + 1);
11698 sprintf (string, ".%s[PR]", name);
11699 DECL_SECTION_NAME (decl) = build_string (len, string);
11703 /* Select section for constant in constant pool.
11705 On RS/6000, all constants are in the private read-only data area.
11706 However, if this is being placed in the TOC it must be output as a
11710 rs6000_xcoff_select_rtx_section (mode, x, align)
11711 enum machine_mode mode;
11713 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
11715 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
11718 read_only_private_data_section ();
11721 /* Remove any trailing [DS] or the like from the symbol name. */
11723 static const char *
11724 rs6000_xcoff_strip_name_encoding (name)
11730 len = strlen (name);
11731 if (name[len - 1] == ']')
11732 return ggc_alloc_string (name, len - 4);
11737 #endif /* OBJECT_FORMAT_COFF */
11739 /* Note that this is also used for ELF64. */
11742 rs6000_xcoff_encode_section_info (decl, first)
11744 int first ATTRIBUTE_UNUSED;
11746 if (TREE_CODE (decl) == FUNCTION_DECL
11747 && (TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
11748 && ! DECL_WEAK (decl))
11749 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;