1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct GTY(()) machine_function
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu;
138 struct rs6000_cpu_select rs6000_select[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 /* Always emit branch hint bits. */
147 static GTY(()) bool rs6000_always_hint;
149 /* Schedule instructions for group formation. */
150 static GTY(()) bool rs6000_sched_groups;
152 /* Align branch targets. */
153 static GTY(()) bool rs6000_align_branch_targets;
155 /* Support for -msched-costly-dep option. */
156 const char *rs6000_sched_costly_dep_str;
157 enum rs6000_dependence_cost rs6000_sched_costly_dep;
159 /* Support for -minsert-sched-nops option. */
160 const char *rs6000_sched_insert_nops_str;
161 enum rs6000_nop_insertion rs6000_sched_insert_nops;
163 /* Support targetm.vectorize.builtin_mask_for_load. */
164 static GTY(()) tree altivec_builtin_mask_for_load;
166 /* Size of long double. */
167 int rs6000_long_double_type_size;
169 /* IEEE quad extended precision long double. */
172 /* Nonzero to use AltiVec ABI. */
173 int rs6000_altivec_abi;
175 /* Nonzero if we want SPE SIMD instructions. */
178 /* Nonzero if we want SPE ABI extensions. */
181 /* Nonzero to use isel instructions. */
184 /* Nonzero if floating point operations are done in the GPRs. */
185 int rs6000_float_gprs = 0;
187 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
188 int rs6000_darwin64_abi;
190 /* Set to nonzero once AIX common-mode calls have been defined. */
191 static GTY(()) int common_mode_defined;
193 /* Save information from a "cmpxx" operation until the branch or scc is
195 rtx rs6000_compare_op0, rs6000_compare_op1;
196 int rs6000_compare_fp_p;
198 /* Label number of label created for -mrelocatable, to call to so we can
199 get the address of the GOT section */
200 int rs6000_pic_labelno;
203 /* Which abi to adhere to */
204 const char *rs6000_abi_name;
206 /* Semantics of the small data area */
207 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
209 /* Which small data model to use */
210 const char *rs6000_sdata_name = (char *)0;
212 /* Counter for labels which are to be placed in .fixup. */
213 int fixuplabelno = 0;
216 /* Bit size of immediate TLS offsets and string from which it is decoded. */
217 int rs6000_tls_size = 32;
218 const char *rs6000_tls_size_string;
220 /* ABI enumeration available for subtarget to use. */
221 enum rs6000_abi rs6000_current_abi;
223 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
227 const char *rs6000_debug_name;
228 int rs6000_debug_stack; /* debug stack applications */
229 int rs6000_debug_arg; /* debug argument handling */
231 /* Value is TRUE if register/mode pair is acceptable. */
232 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
234 /* Built in types. */
236 tree rs6000_builtin_types[RS6000_BTI_MAX];
237 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
239 const char *rs6000_traceback_name;
241 traceback_default = 0,
247 /* Flag to say the TOC is initialized */
249 char toc_label_name[10];
251 /* Cached value of rs6000_variable_issue. This is cached in
252 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
253 static short cached_can_issue_more;
255 static GTY(()) section *read_only_data_section;
256 static GTY(()) section *private_data_section;
257 static GTY(()) section *read_only_private_data_section;
258 static GTY(()) section *sdata2_section;
259 static GTY(()) section *toc_section;
261 /* Control alignment for fields within structures. */
262 /* String from -malign-XXXXX. */
263 int rs6000_alignment_flags;
265 /* True for any options that were explicitly set. */
267 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
268 bool alignment; /* True if -malign- was used. */
269 bool spe_abi; /* True if -mabi=spe/no-spe was used. */
270 bool altivec_abi; /* True if -mabi=altivec/no-altivec used. */
271 bool spe; /* True if -mspe= was used. */
272 bool float_gprs; /* True if -mfloat-gprs= was used. */
273 bool isel; /* True if -misel was used. */
274 bool long_double; /* True if -mlong-double- was used. */
275 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
276 bool vrsave; /* True if -mvrsave was used. */
277 } rs6000_explicit_options;
279 struct builtin_description
281 /* mask is not const because we're going to alter it below. This
282 nonsense will go away when we rewrite the -march infrastructure
283 to give us more target flag bits. */
285 const enum insn_code icode;
286 const char *const name;
287 const enum rs6000_builtins code;
290 /* Target cpu costs. */
292 struct processor_costs {
293 const int mulsi; /* cost of SImode multiplication. */
294 const int mulsi_const; /* cost of SImode multiplication by constant. */
295 const int mulsi_const9; /* cost of SImode mult by short constant. */
296 const int muldi; /* cost of DImode multiplication. */
297 const int divsi; /* cost of SImode division. */
298 const int divdi; /* cost of DImode division. */
299 const int fp; /* cost of simple SFmode and DFmode insns. */
300 const int dmul; /* cost of DFmode multiplication (and fmadd). */
301 const int sdiv; /* cost of SFmode division (fdivs). */
302 const int ddiv; /* cost of DFmode division (fdiv). */
303 const int cache_line_size; /* cache line size in bytes. */
304 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
305 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
306 const int simultaneous_prefetches; /* number of parallel prefetch
310 const struct processor_costs *rs6000_cost;
312 /* Processor costs (relative to an add) */
314 /* Instruction size costs on 32bit processors. */
316 struct processor_costs size32_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
333 /* Instruction size costs on 64bit processors. */
335 struct processor_costs size64_cost = {
336 COSTS_N_INSNS (1), /* mulsi */
337 COSTS_N_INSNS (1), /* mulsi_const */
338 COSTS_N_INSNS (1), /* mulsi_const9 */
339 COSTS_N_INSNS (1), /* muldi */
340 COSTS_N_INSNS (1), /* divsi */
341 COSTS_N_INSNS (1), /* divdi */
342 COSTS_N_INSNS (1), /* fp */
343 COSTS_N_INSNS (1), /* dmul */
344 COSTS_N_INSNS (1), /* sdiv */
345 COSTS_N_INSNS (1), /* ddiv */
352 /* Instruction costs on RIOS1 processors. */
354 struct processor_costs rios1_cost = {
355 COSTS_N_INSNS (5), /* mulsi */
356 COSTS_N_INSNS (4), /* mulsi_const */
357 COSTS_N_INSNS (3), /* mulsi_const9 */
358 COSTS_N_INSNS (5), /* muldi */
359 COSTS_N_INSNS (19), /* divsi */
360 COSTS_N_INSNS (19), /* divdi */
361 COSTS_N_INSNS (2), /* fp */
362 COSTS_N_INSNS (2), /* dmul */
363 COSTS_N_INSNS (19), /* sdiv */
364 COSTS_N_INSNS (19), /* ddiv */
365 128, /* cache line size */
371 /* Instruction costs on RIOS2 processors. */
373 struct processor_costs rios2_cost = {
374 COSTS_N_INSNS (2), /* mulsi */
375 COSTS_N_INSNS (2), /* mulsi_const */
376 COSTS_N_INSNS (2), /* mulsi_const9 */
377 COSTS_N_INSNS (2), /* muldi */
378 COSTS_N_INSNS (13), /* divsi */
379 COSTS_N_INSNS (13), /* divdi */
380 COSTS_N_INSNS (2), /* fp */
381 COSTS_N_INSNS (2), /* dmul */
382 COSTS_N_INSNS (17), /* sdiv */
383 COSTS_N_INSNS (17), /* ddiv */
384 256, /* cache line size */
390 /* Instruction costs on RS64A processors. */
392 struct processor_costs rs64a_cost = {
393 COSTS_N_INSNS (20), /* mulsi */
394 COSTS_N_INSNS (12), /* mulsi_const */
395 COSTS_N_INSNS (8), /* mulsi_const9 */
396 COSTS_N_INSNS (34), /* muldi */
397 COSTS_N_INSNS (65), /* divsi */
398 COSTS_N_INSNS (67), /* divdi */
399 COSTS_N_INSNS (4), /* fp */
400 COSTS_N_INSNS (4), /* dmul */
401 COSTS_N_INSNS (31), /* sdiv */
402 COSTS_N_INSNS (31), /* ddiv */
403 128, /* cache line size */
409 /* Instruction costs on MPCCORE processors. */
411 struct processor_costs mpccore_cost = {
412 COSTS_N_INSNS (2), /* mulsi */
413 COSTS_N_INSNS (2), /* mulsi_const */
414 COSTS_N_INSNS (2), /* mulsi_const9 */
415 COSTS_N_INSNS (2), /* muldi */
416 COSTS_N_INSNS (6), /* divsi */
417 COSTS_N_INSNS (6), /* divdi */
418 COSTS_N_INSNS (4), /* fp */
419 COSTS_N_INSNS (5), /* dmul */
420 COSTS_N_INSNS (10), /* sdiv */
421 COSTS_N_INSNS (17), /* ddiv */
422 32, /* cache line size */
428 /* Instruction costs on PPC403 processors. */
430 struct processor_costs ppc403_cost = {
431 COSTS_N_INSNS (4), /* mulsi */
432 COSTS_N_INSNS (4), /* mulsi_const */
433 COSTS_N_INSNS (4), /* mulsi_const9 */
434 COSTS_N_INSNS (4), /* muldi */
435 COSTS_N_INSNS (33), /* divsi */
436 COSTS_N_INSNS (33), /* divdi */
437 COSTS_N_INSNS (11), /* fp */
438 COSTS_N_INSNS (11), /* dmul */
439 COSTS_N_INSNS (11), /* sdiv */
440 COSTS_N_INSNS (11), /* ddiv */
441 32, /* cache line size */
447 /* Instruction costs on PPC405 processors. */
449 struct processor_costs ppc405_cost = {
450 COSTS_N_INSNS (5), /* mulsi */
451 COSTS_N_INSNS (4), /* mulsi_const */
452 COSTS_N_INSNS (3), /* mulsi_const9 */
453 COSTS_N_INSNS (5), /* muldi */
454 COSTS_N_INSNS (35), /* divsi */
455 COSTS_N_INSNS (35), /* divdi */
456 COSTS_N_INSNS (11), /* fp */
457 COSTS_N_INSNS (11), /* dmul */
458 COSTS_N_INSNS (11), /* sdiv */
459 COSTS_N_INSNS (11), /* ddiv */
460 32, /* cache line size */
466 /* Instruction costs on PPC440 processors. */
468 struct processor_costs ppc440_cost = {
469 COSTS_N_INSNS (3), /* mulsi */
470 COSTS_N_INSNS (2), /* mulsi_const */
471 COSTS_N_INSNS (2), /* mulsi_const9 */
472 COSTS_N_INSNS (3), /* muldi */
473 COSTS_N_INSNS (34), /* divsi */
474 COSTS_N_INSNS (34), /* divdi */
475 COSTS_N_INSNS (5), /* fp */
476 COSTS_N_INSNS (5), /* dmul */
477 COSTS_N_INSNS (19), /* sdiv */
478 COSTS_N_INSNS (33), /* ddiv */
479 32, /* cache line size */
485 /* Instruction costs on PPC601 processors. */
487 struct processor_costs ppc601_cost = {
488 COSTS_N_INSNS (5), /* mulsi */
489 COSTS_N_INSNS (5), /* mulsi_const */
490 COSTS_N_INSNS (5), /* mulsi_const9 */
491 COSTS_N_INSNS (5), /* muldi */
492 COSTS_N_INSNS (36), /* divsi */
493 COSTS_N_INSNS (36), /* divdi */
494 COSTS_N_INSNS (4), /* fp */
495 COSTS_N_INSNS (5), /* dmul */
496 COSTS_N_INSNS (17), /* sdiv */
497 COSTS_N_INSNS (31), /* ddiv */
498 32, /* cache line size */
504 /* Instruction costs on PPC603 processors. */
506 struct processor_costs ppc603_cost = {
507 COSTS_N_INSNS (5), /* mulsi */
508 COSTS_N_INSNS (3), /* mulsi_const */
509 COSTS_N_INSNS (2), /* mulsi_const9 */
510 COSTS_N_INSNS (5), /* muldi */
511 COSTS_N_INSNS (37), /* divsi */
512 COSTS_N_INSNS (37), /* divdi */
513 COSTS_N_INSNS (3), /* fp */
514 COSTS_N_INSNS (4), /* dmul */
515 COSTS_N_INSNS (18), /* sdiv */
516 COSTS_N_INSNS (33), /* ddiv */
517 32, /* cache line size */
523 /* Instruction costs on PPC604 processors. */
525 struct processor_costs ppc604_cost = {
526 COSTS_N_INSNS (4), /* mulsi */
527 COSTS_N_INSNS (4), /* mulsi_const */
528 COSTS_N_INSNS (4), /* mulsi_const9 */
529 COSTS_N_INSNS (4), /* muldi */
530 COSTS_N_INSNS (20), /* divsi */
531 COSTS_N_INSNS (20), /* divdi */
532 COSTS_N_INSNS (3), /* fp */
533 COSTS_N_INSNS (3), /* dmul */
534 COSTS_N_INSNS (18), /* sdiv */
535 COSTS_N_INSNS (32), /* ddiv */
536 32, /* cache line size */
542 /* Instruction costs on PPC604e processors. */
544 struct processor_costs ppc604e_cost = {
545 COSTS_N_INSNS (2), /* mulsi */
546 COSTS_N_INSNS (2), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (2), /* muldi */
549 COSTS_N_INSNS (20), /* divsi */
550 COSTS_N_INSNS (20), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (18), /* sdiv */
554 COSTS_N_INSNS (32), /* ddiv */
555 32, /* cache line size */
561 /* Instruction costs on PPC620 processors. */
563 struct processor_costs ppc620_cost = {
564 COSTS_N_INSNS (5), /* mulsi */
565 COSTS_N_INSNS (4), /* mulsi_const */
566 COSTS_N_INSNS (3), /* mulsi_const9 */
567 COSTS_N_INSNS (7), /* muldi */
568 COSTS_N_INSNS (21), /* divsi */
569 COSTS_N_INSNS (37), /* divdi */
570 COSTS_N_INSNS (3), /* fp */
571 COSTS_N_INSNS (3), /* dmul */
572 COSTS_N_INSNS (18), /* sdiv */
573 COSTS_N_INSNS (32), /* ddiv */
574 128, /* cache line size */
580 /* Instruction costs on PPC630 processors. */
582 struct processor_costs ppc630_cost = {
583 COSTS_N_INSNS (5), /* mulsi */
584 COSTS_N_INSNS (4), /* mulsi_const */
585 COSTS_N_INSNS (3), /* mulsi_const9 */
586 COSTS_N_INSNS (7), /* muldi */
587 COSTS_N_INSNS (21), /* divsi */
588 COSTS_N_INSNS (37), /* divdi */
589 COSTS_N_INSNS (3), /* fp */
590 COSTS_N_INSNS (3), /* dmul */
591 COSTS_N_INSNS (17), /* sdiv */
592 COSTS_N_INSNS (21), /* ddiv */
593 128, /* cache line size */
599 /* Instruction costs on Cell processor. */
600 /* COSTS_N_INSNS (1) ~ one add. */
602 struct processor_costs ppccell_cost = {
603 COSTS_N_INSNS (9/2)+2, /* mulsi */
604 COSTS_N_INSNS (6/2), /* mulsi_const */
605 COSTS_N_INSNS (6/2), /* mulsi_const9 */
606 COSTS_N_INSNS (15/2)+2, /* muldi */
607 COSTS_N_INSNS (38/2), /* divsi */
608 COSTS_N_INSNS (70/2), /* divdi */
609 COSTS_N_INSNS (10/2), /* fp */
610 COSTS_N_INSNS (10/2), /* dmul */
611 COSTS_N_INSNS (74/2), /* sdiv */
612 COSTS_N_INSNS (74/2), /* ddiv */
613 128, /* cache line size */
619 /* Instruction costs on PPC750 and PPC7400 processors. */
621 struct processor_costs ppc750_cost = {
622 COSTS_N_INSNS (5), /* mulsi */
623 COSTS_N_INSNS (3), /* mulsi_const */
624 COSTS_N_INSNS (2), /* mulsi_const9 */
625 COSTS_N_INSNS (5), /* muldi */
626 COSTS_N_INSNS (17), /* divsi */
627 COSTS_N_INSNS (17), /* divdi */
628 COSTS_N_INSNS (3), /* fp */
629 COSTS_N_INSNS (3), /* dmul */
630 COSTS_N_INSNS (17), /* sdiv */
631 COSTS_N_INSNS (31), /* ddiv */
632 32, /* cache line size */
638 /* Instruction costs on PPC7450 processors. */
640 struct processor_costs ppc7450_cost = {
641 COSTS_N_INSNS (4), /* mulsi */
642 COSTS_N_INSNS (3), /* mulsi_const */
643 COSTS_N_INSNS (3), /* mulsi_const9 */
644 COSTS_N_INSNS (4), /* muldi */
645 COSTS_N_INSNS (23), /* divsi */
646 COSTS_N_INSNS (23), /* divdi */
647 COSTS_N_INSNS (5), /* fp */
648 COSTS_N_INSNS (5), /* dmul */
649 COSTS_N_INSNS (21), /* sdiv */
650 COSTS_N_INSNS (35), /* ddiv */
651 32, /* cache line size */
657 /* Instruction costs on PPC8540 processors. */
659 struct processor_costs ppc8540_cost = {
660 COSTS_N_INSNS (4), /* mulsi */
661 COSTS_N_INSNS (4), /* mulsi_const */
662 COSTS_N_INSNS (4), /* mulsi_const9 */
663 COSTS_N_INSNS (4), /* muldi */
664 COSTS_N_INSNS (19), /* divsi */
665 COSTS_N_INSNS (19), /* divdi */
666 COSTS_N_INSNS (4), /* fp */
667 COSTS_N_INSNS (4), /* dmul */
668 COSTS_N_INSNS (29), /* sdiv */
669 COSTS_N_INSNS (29), /* ddiv */
670 32, /* cache line size */
673 1, /* prefetch streams /*/
676 /* Instruction costs on E300C2 and E300C3 cores. */
678 struct processor_costs ppce300c2c3_cost = {
679 COSTS_N_INSNS (4), /* mulsi */
680 COSTS_N_INSNS (4), /* mulsi_const */
681 COSTS_N_INSNS (4), /* mulsi_const9 */
682 COSTS_N_INSNS (4), /* muldi */
683 COSTS_N_INSNS (19), /* divsi */
684 COSTS_N_INSNS (19), /* divdi */
685 COSTS_N_INSNS (3), /* fp */
686 COSTS_N_INSNS (4), /* dmul */
687 COSTS_N_INSNS (18), /* sdiv */
688 COSTS_N_INSNS (33), /* ddiv */
692 1, /* prefetch streams /*/
695 /* Instruction costs on PPCE500MC processors. */
697 struct processor_costs ppce500mc_cost = {
698 COSTS_N_INSNS (4), /* mulsi */
699 COSTS_N_INSNS (4), /* mulsi_const */
700 COSTS_N_INSNS (4), /* mulsi_const9 */
701 COSTS_N_INSNS (4), /* muldi */
702 COSTS_N_INSNS (14), /* divsi */
703 COSTS_N_INSNS (14), /* divdi */
704 COSTS_N_INSNS (8), /* fp */
705 COSTS_N_INSNS (10), /* dmul */
706 COSTS_N_INSNS (36), /* sdiv */
707 COSTS_N_INSNS (66), /* ddiv */
708 64, /* cache line size */
711 1, /* prefetch streams /*/
714 /* Instruction costs on POWER4 and POWER5 processors. */
716 struct processor_costs power4_cost = {
717 COSTS_N_INSNS (3), /* mulsi */
718 COSTS_N_INSNS (2), /* mulsi_const */
719 COSTS_N_INSNS (2), /* mulsi_const9 */
720 COSTS_N_INSNS (4), /* muldi */
721 COSTS_N_INSNS (18), /* divsi */
722 COSTS_N_INSNS (34), /* divdi */
723 COSTS_N_INSNS (3), /* fp */
724 COSTS_N_INSNS (3), /* dmul */
725 COSTS_N_INSNS (17), /* sdiv */
726 COSTS_N_INSNS (17), /* ddiv */
727 128, /* cache line size */
730 8, /* prefetch streams /*/
733 /* Instruction costs on POWER6 processors. */
735 struct processor_costs power6_cost = {
736 COSTS_N_INSNS (8), /* mulsi */
737 COSTS_N_INSNS (8), /* mulsi_const */
738 COSTS_N_INSNS (8), /* mulsi_const9 */
739 COSTS_N_INSNS (8), /* muldi */
740 COSTS_N_INSNS (22), /* divsi */
741 COSTS_N_INSNS (28), /* divdi */
742 COSTS_N_INSNS (3), /* fp */
743 COSTS_N_INSNS (3), /* dmul */
744 COSTS_N_INSNS (13), /* sdiv */
745 COSTS_N_INSNS (16), /* ddiv */
746 128, /* cache line size */
749 16, /* prefetch streams */
753 static bool rs6000_function_ok_for_sibcall (tree, tree);
754 static const char *rs6000_invalid_within_doloop (const_rtx);
755 static rtx rs6000_generate_compare (enum rtx_code);
756 static void rs6000_emit_stack_tie (void);
757 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
758 static bool spe_func_has_64bit_regs_p (void);
759 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
761 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
762 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int, int);
763 static unsigned rs6000_hash_constant (rtx);
764 static unsigned toc_hash_function (const void *);
765 static int toc_hash_eq (const void *, const void *);
766 static bool constant_pool_expr_p (rtx);
767 static bool legitimate_small_data_p (enum machine_mode, rtx);
768 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
769 static struct machine_function * rs6000_init_machine_status (void);
770 static bool rs6000_assemble_integer (rtx, unsigned int, int);
771 static bool no_global_regs_above (int, bool);
772 #ifdef HAVE_GAS_HIDDEN
773 static void rs6000_assemble_visibility (tree, int);
775 static int rs6000_ra_ever_killed (void);
776 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
777 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
778 static bool rs6000_ms_bitfield_layout_p (const_tree);
779 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
780 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
781 static const char *rs6000_mangle_type (const_tree);
782 extern const struct attribute_spec rs6000_attribute_table[];
783 static void rs6000_set_default_type_attributes (tree);
784 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
785 static void rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
786 static rtx rs6000_make_savres_rtx (rs6000_stack_t *, rtx, int,
787 enum machine_mode, bool, bool, bool);
788 static bool rs6000_reg_live_or_pic_offset_p (int);
789 static int rs6000_savres_strategy (rs6000_stack_t *, bool, int, int);
790 static void rs6000_restore_saved_cr (rtx, int);
791 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
792 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
793 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
795 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
796 static bool rs6000_return_in_memory (const_tree, const_tree);
797 static void rs6000_file_start (void);
799 static int rs6000_elf_reloc_rw_mask (void);
800 static void rs6000_elf_asm_out_constructor (rtx, int);
801 static void rs6000_elf_asm_out_destructor (rtx, int);
802 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
803 static void rs6000_elf_asm_init_sections (void);
804 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
805 unsigned HOST_WIDE_INT);
806 static void rs6000_elf_encode_section_info (tree, rtx, int)
809 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
810 static void rs6000_alloc_sdmode_stack_slot (void);
811 static void rs6000_instantiate_decls (void);
813 static void rs6000_xcoff_asm_output_anchor (rtx);
814 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
815 static void rs6000_xcoff_asm_init_sections (void);
816 static int rs6000_xcoff_reloc_rw_mask (void);
817 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
818 static section *rs6000_xcoff_select_section (tree, int,
819 unsigned HOST_WIDE_INT);
820 static void rs6000_xcoff_unique_section (tree, int);
821 static section *rs6000_xcoff_select_rtx_section
822 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
823 static const char * rs6000_xcoff_strip_name_encoding (const char *);
824 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
825 static void rs6000_xcoff_file_start (void);
826 static void rs6000_xcoff_file_end (void);
828 static int rs6000_variable_issue (FILE *, int, rtx, int);
829 static bool rs6000_rtx_costs (rtx, int, int, int *, bool);
830 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
831 static void rs6000_sched_init (FILE *, int, int);
832 static bool is_microcoded_insn (rtx);
833 static bool is_nonpipeline_insn (rtx);
834 static bool is_cracked_insn (rtx);
835 static bool is_branch_slot_insn (rtx);
836 static bool is_load_insn (rtx);
837 static rtx get_store_dest (rtx pat);
838 static bool is_store_insn (rtx);
839 static bool set_to_load_agen (rtx,rtx);
840 static bool adjacent_mem_locations (rtx,rtx);
841 static int rs6000_adjust_priority (rtx, int);
842 static int rs6000_issue_rate (void);
843 static bool rs6000_is_costly_dependence (dep_t, int, int);
844 static rtx get_next_active_insn (rtx, rtx);
845 static bool insn_terminates_group_p (rtx , enum group_termination);
846 static bool insn_must_be_first_in_group (rtx);
847 static bool insn_must_be_last_in_group (rtx);
848 static bool is_costly_group (rtx *, rtx);
849 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
850 static int redefine_groups (FILE *, int, rtx, rtx);
851 static int pad_groups (FILE *, int, rtx, rtx);
852 static void rs6000_sched_finish (FILE *, int);
853 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
854 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
855 static int rs6000_use_sched_lookahead (void);
856 static int rs6000_use_sched_lookahead_guard (rtx);
857 static void * rs6000_alloc_sched_context (void);
858 static void rs6000_init_sched_context (void *, bool);
859 static void rs6000_set_sched_context (void *);
860 static void rs6000_free_sched_context (void *);
861 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
862 static tree rs6000_builtin_mask_for_load (void);
863 static tree rs6000_builtin_mul_widen_even (tree);
864 static tree rs6000_builtin_mul_widen_odd (tree);
865 static tree rs6000_builtin_conversion (enum tree_code, tree);
866 static tree rs6000_builtin_vec_perm (tree, tree *);
868 static void def_builtin (int, const char *, tree, int);
869 static bool rs6000_vector_alignment_reachable (const_tree, bool);
870 static void rs6000_init_builtins (void);
871 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
872 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
873 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
874 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
875 static void altivec_init_builtins (void);
876 static void rs6000_common_init_builtins (void);
877 static void rs6000_init_libfuncs (void);
879 static void paired_init_builtins (void);
880 static rtx paired_expand_builtin (tree, rtx, bool *);
881 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
882 static rtx paired_expand_stv_builtin (enum insn_code, tree);
883 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
885 static void enable_mask_for_builtins (struct builtin_description *, int,
886 enum rs6000_builtins,
887 enum rs6000_builtins);
888 static void spe_init_builtins (void);
889 static rtx spe_expand_builtin (tree, rtx, bool *);
890 static rtx spe_expand_stv_builtin (enum insn_code, tree);
891 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
892 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
893 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
894 static rs6000_stack_t *rs6000_stack_info (void);
895 static void debug_stack_info (rs6000_stack_t *);
897 static rtx altivec_expand_builtin (tree, rtx, bool *);
898 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
899 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
900 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
901 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
902 static rtx altivec_expand_predicate_builtin (enum insn_code,
903 const char *, tree, rtx);
904 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
905 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
906 static rtx altivec_expand_vec_set_builtin (tree);
907 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
908 static int get_element_number (tree, tree);
909 static bool rs6000_handle_option (size_t, const char *, int);
910 static void rs6000_parse_tls_size_option (void);
911 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
912 static int first_altivec_reg_to_save (void);
913 static unsigned int compute_vrsave_mask (void);
914 static void compute_save_world_info (rs6000_stack_t *info_ptr);
915 static void is_altivec_return_reg (rtx, void *);
916 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
917 int easy_vector_constant (rtx, enum machine_mode);
918 static rtx rs6000_dwarf_register_span (rtx);
919 static void rs6000_init_dwarf_reg_sizes_extra (tree);
920 static rtx rs6000_legitimize_address (rtx, rtx, enum machine_mode);
921 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
922 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
923 static rtx rs6000_tls_get_addr (void);
924 static rtx rs6000_got_sym (void);
925 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
926 static const char *rs6000_get_some_local_dynamic_name (void);
927 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
928 static rtx rs6000_complex_function_value (enum machine_mode);
929 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
930 enum machine_mode, tree);
931 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
933 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
934 tree, HOST_WIDE_INT);
935 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
938 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
939 const_tree, HOST_WIDE_INT,
941 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
942 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
943 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
944 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
945 enum machine_mode, tree,
947 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
949 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
951 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
953 static void macho_branch_islands (void);
954 static int no_previous_def (tree function_name);
955 static tree get_prev_label (tree function_name);
956 static void rs6000_darwin_file_start (void);
959 static tree rs6000_build_builtin_va_list (void);
960 static void rs6000_va_start (tree, rtx);
961 static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
962 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
963 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
964 static bool rs6000_vector_mode_supported_p (enum machine_mode);
965 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
967 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
969 static int get_vsel_insn (enum machine_mode);
970 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
971 static tree rs6000_stack_protect_fail (void);
973 const int INSN_NOT_AVAILABLE = -1;
974 static enum machine_mode rs6000_eh_return_filter_mode (void);
976 /* Hash table stuff for keeping track of TOC entries. */
978 struct GTY(()) toc_hash_struct
980 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
981 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
983 enum machine_mode key_mode;
987 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
989 /* Default register names. */
990 char rs6000_reg_names[][8] =
992 "0", "1", "2", "3", "4", "5", "6", "7",
993 "8", "9", "10", "11", "12", "13", "14", "15",
994 "16", "17", "18", "19", "20", "21", "22", "23",
995 "24", "25", "26", "27", "28", "29", "30", "31",
996 "0", "1", "2", "3", "4", "5", "6", "7",
997 "8", "9", "10", "11", "12", "13", "14", "15",
998 "16", "17", "18", "19", "20", "21", "22", "23",
999 "24", "25", "26", "27", "28", "29", "30", "31",
1000 "mq", "lr", "ctr","ap",
1001 "0", "1", "2", "3", "4", "5", "6", "7",
1003 /* AltiVec registers. */
1004 "0", "1", "2", "3", "4", "5", "6", "7",
1005 "8", "9", "10", "11", "12", "13", "14", "15",
1006 "16", "17", "18", "19", "20", "21", "22", "23",
1007 "24", "25", "26", "27", "28", "29", "30", "31",
1009 /* SPE registers. */
1010 "spe_acc", "spefscr",
1011 /* Soft frame pointer. */
1015 #ifdef TARGET_REGNAMES
1016 static const char alt_reg_names[][8] =
1018 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1019 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1020 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1021 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1022 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1023 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1024 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1025 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1026 "mq", "lr", "ctr", "ap",
1027 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1029 /* AltiVec registers. */
1030 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1031 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1032 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1033 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1035 /* SPE registers. */
1036 "spe_acc", "spefscr",
1037 /* Soft frame pointer. */
1042 #ifndef MASK_STRICT_ALIGN
1043 #define MASK_STRICT_ALIGN 0
1045 #ifndef TARGET_PROFILE_KERNEL
1046 #define TARGET_PROFILE_KERNEL 0
1049 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1050 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1052 /* Initialize the GCC target structure. */
1053 #undef TARGET_ATTRIBUTE_TABLE
1054 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1055 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1056 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1058 #undef TARGET_ASM_ALIGNED_DI_OP
1059 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1061 /* Default unaligned ops are only provided for ELF. Find the ops needed
1062 for non-ELF systems. */
1063 #ifndef OBJECT_FORMAT_ELF
1065 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1067 #undef TARGET_ASM_UNALIGNED_HI_OP
1068 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1069 #undef TARGET_ASM_UNALIGNED_SI_OP
1070 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1071 #undef TARGET_ASM_UNALIGNED_DI_OP
1072 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1075 #undef TARGET_ASM_UNALIGNED_HI_OP
1076 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1077 #undef TARGET_ASM_UNALIGNED_SI_OP
1078 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1079 #undef TARGET_ASM_UNALIGNED_DI_OP
1080 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1081 #undef TARGET_ASM_ALIGNED_DI_OP
1082 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1086 /* This hook deals with fixups for relocatable code and DI-mode objects
1088 #undef TARGET_ASM_INTEGER
1089 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1091 #ifdef HAVE_GAS_HIDDEN
1092 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1093 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1096 #undef TARGET_HAVE_TLS
1097 #define TARGET_HAVE_TLS HAVE_AS_TLS
1099 #undef TARGET_CANNOT_FORCE_CONST_MEM
1100 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1102 #undef TARGET_ASM_FUNCTION_PROLOGUE
1103 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1104 #undef TARGET_ASM_FUNCTION_EPILOGUE
1105 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1107 #undef TARGET_LEGITIMIZE_ADDRESS
1108 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1110 #undef TARGET_SCHED_VARIABLE_ISSUE
1111 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1113 #undef TARGET_SCHED_ISSUE_RATE
1114 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1115 #undef TARGET_SCHED_ADJUST_COST
1116 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1117 #undef TARGET_SCHED_ADJUST_PRIORITY
1118 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1119 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1120 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1121 #undef TARGET_SCHED_INIT
1122 #define TARGET_SCHED_INIT rs6000_sched_init
1123 #undef TARGET_SCHED_FINISH
1124 #define TARGET_SCHED_FINISH rs6000_sched_finish
1125 #undef TARGET_SCHED_REORDER
1126 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1127 #undef TARGET_SCHED_REORDER2
1128 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1130 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1131 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1133 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1134 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1136 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1137 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1138 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1139 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1140 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1141 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1142 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1143 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1145 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1146 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1147 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1148 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1149 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1150 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1151 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1152 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1153 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
1154 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM rs6000_builtin_vec_perm
1156 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1157 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1159 #undef TARGET_INIT_BUILTINS
1160 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1162 #undef TARGET_EXPAND_BUILTIN
1163 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1165 #undef TARGET_MANGLE_TYPE
1166 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1168 #undef TARGET_INIT_LIBFUNCS
1169 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1172 #undef TARGET_BINDS_LOCAL_P
1173 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1176 #undef TARGET_MS_BITFIELD_LAYOUT_P
1177 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1179 #undef TARGET_ASM_OUTPUT_MI_THUNK
1180 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1182 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1183 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1185 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1186 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1188 #undef TARGET_INVALID_WITHIN_DOLOOP
1189 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1191 #undef TARGET_RTX_COSTS
1192 #define TARGET_RTX_COSTS rs6000_rtx_costs
1193 #undef TARGET_ADDRESS_COST
1194 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1196 #undef TARGET_DWARF_REGISTER_SPAN
1197 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1199 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1200 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1202 /* On rs6000, function arguments are promoted, as are function return
1204 #undef TARGET_PROMOTE_FUNCTION_ARGS
1205 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1206 #undef TARGET_PROMOTE_FUNCTION_RETURN
1207 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1209 #undef TARGET_RETURN_IN_MEMORY
1210 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1212 #undef TARGET_SETUP_INCOMING_VARARGS
1213 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1215 /* Always strict argument naming on rs6000. */
1216 #undef TARGET_STRICT_ARGUMENT_NAMING
1217 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1218 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1219 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1220 #undef TARGET_SPLIT_COMPLEX_ARG
1221 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1222 #undef TARGET_MUST_PASS_IN_STACK
1223 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1224 #undef TARGET_PASS_BY_REFERENCE
1225 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1226 #undef TARGET_ARG_PARTIAL_BYTES
1227 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1229 #undef TARGET_BUILD_BUILTIN_VA_LIST
1230 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1232 #undef TARGET_EXPAND_BUILTIN_VA_START
1233 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1235 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1236 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1238 #undef TARGET_EH_RETURN_FILTER_MODE
1239 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1241 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1242 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1244 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1245 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1247 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1248 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1250 #undef TARGET_HANDLE_OPTION
1251 #define TARGET_HANDLE_OPTION rs6000_handle_option
1253 #undef TARGET_DEFAULT_TARGET_FLAGS
1254 #define TARGET_DEFAULT_TARGET_FLAGS \
1257 #undef TARGET_STACK_PROTECT_FAIL
1258 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1260 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1261 The PowerPC architecture requires only weak consistency among
1262 processors--that is, memory accesses between processors need not be
1263 sequentially consistent and memory accesses among processors can occur
1264 in any order. The ability to order memory accesses weakly provides
1265 opportunities for more efficient use of the system bus. Unless a
1266 dependency exists, the 604e allows read operations to precede store
1268 #undef TARGET_RELAXED_ORDERING
1269 #define TARGET_RELAXED_ORDERING true
1272 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1273 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1276 /* Use a 32-bit anchor range. This leads to sequences like:
1278 addis tmp,anchor,high
1281 where tmp itself acts as an anchor, and can be shared between
1282 accesses to the same 64k page. */
1283 #undef TARGET_MIN_ANCHOR_OFFSET
1284 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1285 #undef TARGET_MAX_ANCHOR_OFFSET
1286 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1287 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1288 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1290 #undef TARGET_BUILTIN_RECIPROCAL
1291 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1293 #undef TARGET_EXPAND_TO_RTL_HOOK
1294 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1296 #undef TARGET_INSTANTIATE_DECLS
1297 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1299 struct gcc_target targetm = TARGET_INITIALIZER;
1302 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1305 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1307 /* The GPRs can hold any mode, but values bigger than one register
1308 cannot go past R31. */
1309 if (INT_REGNO_P (regno))
1310 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1312 /* The float registers can only hold floating modes and DImode.
1313 This excludes the 32-bit decimal float mode for now. */
1314 if (FP_REGNO_P (regno))
1316 ((SCALAR_FLOAT_MODE_P (mode)
1317 && (mode != TDmode || (regno % 2) == 0)
1318 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1319 || (GET_MODE_CLASS (mode) == MODE_INT
1320 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1321 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1322 && PAIRED_VECTOR_MODE (mode)));
1324 /* The CR register can only hold CC modes. */
1325 if (CR_REGNO_P (regno))
1326 return GET_MODE_CLASS (mode) == MODE_CC;
1328 if (XER_REGNO_P (regno))
1329 return mode == PSImode;
1331 /* AltiVec only in AldyVec registers. */
1332 if (ALTIVEC_REGNO_P (regno))
1333 return ALTIVEC_VECTOR_MODE (mode);
1335 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1336 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1339 /* We cannot put TImode anywhere except general register and it must be
1340 able to fit within the register set. */
1342 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1345 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1347 rs6000_init_hard_regno_mode_ok (void)
1351 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1352 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1353 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode) m))
1354 rs6000_hard_regno_mode_ok_p[m][r] = true;
1358 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1361 darwin_rs6000_override_options (void)
1363 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1365 rs6000_altivec_abi = 1;
1366 TARGET_ALTIVEC_VRSAVE = 1;
1367 if (DEFAULT_ABI == ABI_DARWIN)
1369 if (MACHO_DYNAMIC_NO_PIC_P)
1372 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1375 else if (flag_pic == 1)
1380 if (TARGET_64BIT && ! TARGET_POWERPC64)
1382 target_flags |= MASK_POWERPC64;
1383 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1387 rs6000_default_long_calls = 1;
1388 target_flags |= MASK_SOFT_FLOAT;
1391 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1393 if (!flag_mkernel && !flag_apple_kext
1395 && ! (target_flags_explicit & MASK_ALTIVEC))
1396 target_flags |= MASK_ALTIVEC;
1398 /* Unless the user (not the configurer) has explicitly overridden
1399 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1400 G4 unless targetting the kernel. */
1403 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1404 && ! (target_flags_explicit & MASK_ALTIVEC)
1405 && ! rs6000_select[1].string)
1407 target_flags |= MASK_ALTIVEC;
1412 /* If not otherwise specified by a target, make 'long double' equivalent to
1415 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1416 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1419 /* Override command line options. Mostly we process the processor
1420 type and sometimes adjust other TARGET_ options. */
1423 rs6000_override_options (const char *default_cpu)
1426 struct rs6000_cpu_select *ptr;
1429 /* Simplifications for entries below. */
1432 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1433 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1436 /* This table occasionally claims that a processor does not support
1437 a particular feature even though it does, but the feature is slower
1438 than the alternative. Thus, it shouldn't be relied on as a
1439 complete description of the processor's support.
1441 Please keep this list in order, and don't forget to update the
1442 documentation in invoke.texi when adding a new processor or
1446 const char *const name; /* Canonical processor name. */
1447 const enum processor_type processor; /* Processor type enum value. */
1448 const int target_enable; /* Target flags to enable. */
1449 } const processor_target_table[]
1450 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1451 {"403", PROCESSOR_PPC403,
1452 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1453 {"405", PROCESSOR_PPC405,
1454 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1455 {"405fp", PROCESSOR_PPC405,
1456 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1457 {"440", PROCESSOR_PPC440,
1458 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1459 {"440fp", PROCESSOR_PPC440,
1460 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1461 {"464", PROCESSOR_PPC440,
1462 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1463 {"464fp", PROCESSOR_PPC440,
1464 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1465 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1466 {"601", PROCESSOR_PPC601,
1467 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1468 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1469 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1470 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1471 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1472 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1473 {"620", PROCESSOR_PPC620,
1474 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1475 {"630", PROCESSOR_PPC630,
1476 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1477 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1478 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1479 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1480 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1481 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1482 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1483 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1484 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1485 /* 8548 has a dummy entry for now. */
1486 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1487 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1488 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
1489 {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1490 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1491 {"970", PROCESSOR_POWER4,
1492 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1493 {"cell", PROCESSOR_CELL,
1494 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1495 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1496 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1497 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1498 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1499 {"G5", PROCESSOR_POWER4,
1500 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1501 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1502 {"power2", PROCESSOR_POWER,
1503 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1504 {"power3", PROCESSOR_PPC630,
1505 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1506 {"power4", PROCESSOR_POWER4,
1507 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1509 {"power5", PROCESSOR_POWER5,
1510 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1511 | MASK_MFCRF | MASK_POPCNTB},
1512 {"power5+", PROCESSOR_POWER5,
1513 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1514 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1515 {"power6", PROCESSOR_POWER6,
1516 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1517 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP},
1518 {"power6x", PROCESSOR_POWER6,
1519 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT
1520 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP
1522 {"power7", PROCESSOR_POWER5,
1523 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
1524 | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP},
1525 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1526 {"powerpc64", PROCESSOR_POWERPC64,
1527 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1528 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1529 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1530 {"rios2", PROCESSOR_RIOS2,
1531 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1532 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1533 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1534 {"rs64", PROCESSOR_RS64A,
1535 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1538 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1540 /* Some OSs don't support saving the high part of 64-bit registers on
1541 context switch. Other OSs don't support saving Altivec registers.
1542 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1543 settings; if the user wants either, the user must explicitly specify
1544 them and we won't interfere with the user's specification. */
1547 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1548 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1549 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1550 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1551 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1554 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1555 #ifdef OS_MISSING_POWERPC64
1556 if (OS_MISSING_POWERPC64)
1557 set_masks &= ~MASK_POWERPC64;
1559 #ifdef OS_MISSING_ALTIVEC
1560 if (OS_MISSING_ALTIVEC)
1561 set_masks &= ~MASK_ALTIVEC;
1564 /* Don't override by the processor default if given explicitly. */
1565 set_masks &= ~target_flags_explicit;
1567 /* Identify the processor type. */
1568 rs6000_select[0].string = default_cpu;
1569 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1571 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1573 ptr = &rs6000_select[i];
1574 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1576 for (j = 0; j < ptt_size; j++)
1577 if (! strcmp (ptr->string, processor_target_table[j].name))
1579 if (ptr->set_tune_p)
1580 rs6000_cpu = processor_target_table[j].processor;
1582 if (ptr->set_arch_p)
1584 target_flags &= ~set_masks;
1585 target_flags |= (processor_target_table[j].target_enable
1592 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1596 if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1597 && !rs6000_explicit_options.isel)
1600 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
1601 || rs6000_cpu == PROCESSOR_PPCE500MC)
1604 error ("AltiVec not supported in this target");
1606 error ("Spe not supported in this target");
1609 /* Disable Cell microcode if we are optimizing for the Cell
1610 and not optimizing for size. */
1611 if (rs6000_gen_cell_microcode == -1)
1612 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
1615 /* If we are optimizing big endian systems for space, use the load/store
1616 multiple and string instructions unless we are not generating
1618 if (BYTES_BIG_ENDIAN && optimize_size && !rs6000_gen_cell_microcode)
1619 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1621 /* Don't allow -mmultiple or -mstring on little endian systems
1622 unless the cpu is a 750, because the hardware doesn't support the
1623 instructions used in little endian mode, and causes an alignment
1624 trap. The 750 does not cause an alignment trap (except when the
1625 target is unaligned). */
1627 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1629 if (TARGET_MULTIPLE)
1631 target_flags &= ~MASK_MULTIPLE;
1632 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1633 warning (0, "-mmultiple is not supported on little endian systems");
1638 target_flags &= ~MASK_STRING;
1639 if ((target_flags_explicit & MASK_STRING) != 0)
1640 warning (0, "-mstring is not supported on little endian systems");
1644 /* Set debug flags */
1645 if (rs6000_debug_name)
1647 if (! strcmp (rs6000_debug_name, "all"))
1648 rs6000_debug_stack = rs6000_debug_arg = 1;
1649 else if (! strcmp (rs6000_debug_name, "stack"))
1650 rs6000_debug_stack = 1;
1651 else if (! strcmp (rs6000_debug_name, "arg"))
1652 rs6000_debug_arg = 1;
1654 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1657 if (rs6000_traceback_name)
1659 if (! strncmp (rs6000_traceback_name, "full", 4))
1660 rs6000_traceback = traceback_full;
1661 else if (! strncmp (rs6000_traceback_name, "part", 4))
1662 rs6000_traceback = traceback_part;
1663 else if (! strncmp (rs6000_traceback_name, "no", 2))
1664 rs6000_traceback = traceback_none;
1666 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1667 rs6000_traceback_name);
1670 if (!rs6000_explicit_options.long_double)
1671 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1673 #ifndef POWERPC_LINUX
1674 if (!rs6000_explicit_options.ieee)
1675 rs6000_ieeequad = 1;
1678 /* Enable Altivec ABI for AIX -maltivec. */
1679 if (TARGET_XCOFF && TARGET_ALTIVEC)
1680 rs6000_altivec_abi = 1;
1682 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1683 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1684 be explicitly overridden in either case. */
1687 if (!rs6000_explicit_options.altivec_abi
1688 && (TARGET_64BIT || TARGET_ALTIVEC))
1689 rs6000_altivec_abi = 1;
1691 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1692 if (!rs6000_explicit_options.vrsave)
1693 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
1696 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1697 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1699 rs6000_darwin64_abi = 1;
1701 darwin_one_byte_bool = 1;
1703 /* Default to natural alignment, for better performance. */
1704 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1707 /* Place FP constants in the constant pool instead of TOC
1708 if section anchors enabled. */
1709 if (flag_section_anchors)
1710 TARGET_NO_FP_IN_TOC = 1;
1712 /* Handle -mtls-size option. */
1713 rs6000_parse_tls_size_option ();
1715 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1716 SUBTARGET_OVERRIDE_OPTIONS;
1718 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1719 SUBSUBTARGET_OVERRIDE_OPTIONS;
1721 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1722 SUB3TARGET_OVERRIDE_OPTIONS;
1725 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
1727 /* The e500 and e500mc do not have string instructions, and we set
1728 MASK_STRING above when optimizing for size. */
1729 if ((target_flags & MASK_STRING) != 0)
1730 target_flags = target_flags & ~MASK_STRING;
1732 else if (rs6000_select[1].string != NULL)
1734 /* For the powerpc-eabispe configuration, we set all these by
1735 default, so let's unset them if we manually set another
1736 CPU that is not the E500. */
1737 if (!rs6000_explicit_options.spe_abi)
1739 if (!rs6000_explicit_options.spe)
1741 if (!rs6000_explicit_options.float_gprs)
1742 rs6000_float_gprs = 0;
1743 if (!rs6000_explicit_options.isel)
1747 /* Detect invalid option combinations with E500. */
1750 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1751 && rs6000_cpu != PROCESSOR_POWER5
1752 && rs6000_cpu != PROCESSOR_POWER6
1753 && rs6000_cpu != PROCESSOR_CELL);
1754 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1755 || rs6000_cpu == PROCESSOR_POWER5);
1756 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1757 || rs6000_cpu == PROCESSOR_POWER5
1758 || rs6000_cpu == PROCESSOR_POWER6);
1760 rs6000_sched_restricted_insns_priority
1761 = (rs6000_sched_groups ? 1 : 0);
1763 /* Handle -msched-costly-dep option. */
1764 rs6000_sched_costly_dep
1765 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1767 if (rs6000_sched_costly_dep_str)
1769 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1770 rs6000_sched_costly_dep = no_dep_costly;
1771 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1772 rs6000_sched_costly_dep = all_deps_costly;
1773 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1774 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1775 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1776 rs6000_sched_costly_dep = store_to_load_dep_costly;
1778 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
1779 atoi (rs6000_sched_costly_dep_str));
1782 /* Handle -minsert-sched-nops option. */
1783 rs6000_sched_insert_nops
1784 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1786 if (rs6000_sched_insert_nops_str)
1788 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1789 rs6000_sched_insert_nops = sched_finish_none;
1790 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1791 rs6000_sched_insert_nops = sched_finish_pad_groups;
1792 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1793 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1795 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
1796 atoi (rs6000_sched_insert_nops_str));
1799 #ifdef TARGET_REGNAMES
1800 /* If the user desires alternate register names, copy in the
1801 alternate names now. */
1802 if (TARGET_REGNAMES)
1803 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1806 /* Set aix_struct_return last, after the ABI is determined.
1807 If -maix-struct-return or -msvr4-struct-return was explicitly
1808 used, don't override with the ABI default. */
1809 if (!rs6000_explicit_options.aix_struct_ret)
1810 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1812 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1813 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1816 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1818 /* We can only guarantee the availability of DI pseudo-ops when
1819 assembling for 64-bit targets. */
1822 targetm.asm_out.aligned_op.di = NULL;
1823 targetm.asm_out.unaligned_op.di = NULL;
1826 /* Set branch target alignment, if not optimizing for size. */
1829 /* Cell wants to be aligned 8byte for dual issue. */
1830 if (rs6000_cpu == PROCESSOR_CELL)
1832 if (align_functions <= 0)
1833 align_functions = 8;
1834 if (align_jumps <= 0)
1836 if (align_loops <= 0)
1839 if (rs6000_align_branch_targets)
1841 if (align_functions <= 0)
1842 align_functions = 16;
1843 if (align_jumps <= 0)
1845 if (align_loops <= 0)
1848 if (align_jumps_max_skip <= 0)
1849 align_jumps_max_skip = 15;
1850 if (align_loops_max_skip <= 0)
1851 align_loops_max_skip = 15;
1854 /* Arrange to save and restore machine status around nested functions. */
1855 init_machine_status = rs6000_init_machine_status;
1857 /* We should always be splitting complex arguments, but we can't break
1858 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1859 if (DEFAULT_ABI != ABI_AIX)
1860 targetm.calls.split_complex_arg = NULL;
1862 /* Initialize rs6000_cost with the appropriate target costs. */
1864 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1868 case PROCESSOR_RIOS1:
1869 rs6000_cost = &rios1_cost;
1872 case PROCESSOR_RIOS2:
1873 rs6000_cost = &rios2_cost;
1876 case PROCESSOR_RS64A:
1877 rs6000_cost = &rs64a_cost;
1880 case PROCESSOR_MPCCORE:
1881 rs6000_cost = &mpccore_cost;
1884 case PROCESSOR_PPC403:
1885 rs6000_cost = &ppc403_cost;
1888 case PROCESSOR_PPC405:
1889 rs6000_cost = &ppc405_cost;
1892 case PROCESSOR_PPC440:
1893 rs6000_cost = &ppc440_cost;
1896 case PROCESSOR_PPC601:
1897 rs6000_cost = &ppc601_cost;
1900 case PROCESSOR_PPC603:
1901 rs6000_cost = &ppc603_cost;
1904 case PROCESSOR_PPC604:
1905 rs6000_cost = &ppc604_cost;
1908 case PROCESSOR_PPC604e:
1909 rs6000_cost = &ppc604e_cost;
1912 case PROCESSOR_PPC620:
1913 rs6000_cost = &ppc620_cost;
1916 case PROCESSOR_PPC630:
1917 rs6000_cost = &ppc630_cost;
1920 case PROCESSOR_CELL:
1921 rs6000_cost = &ppccell_cost;
1924 case PROCESSOR_PPC750:
1925 case PROCESSOR_PPC7400:
1926 rs6000_cost = &ppc750_cost;
1929 case PROCESSOR_PPC7450:
1930 rs6000_cost = &ppc7450_cost;
1933 case PROCESSOR_PPC8540:
1934 rs6000_cost = &ppc8540_cost;
1937 case PROCESSOR_PPCE300C2:
1938 case PROCESSOR_PPCE300C3:
1939 rs6000_cost = &ppce300c2c3_cost;
1942 case PROCESSOR_PPCE500MC:
1943 rs6000_cost = &ppce500mc_cost;
1946 case PROCESSOR_POWER4:
1947 case PROCESSOR_POWER5:
1948 rs6000_cost = &power4_cost;
1951 case PROCESSOR_POWER6:
1952 rs6000_cost = &power6_cost;
1959 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1960 set_param_value ("simultaneous-prefetches",
1961 rs6000_cost->simultaneous_prefetches);
1962 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1963 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1964 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1965 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1966 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1967 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1969 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1970 can be optimized to ap = __builtin_next_arg (0). */
1971 if (DEFAULT_ABI != ABI_V4)
1972 targetm.expand_builtin_va_start = NULL;
1974 /* Set up single/double float flags.
1975 If TARGET_HARD_FLOAT is set, but neither single or double is set,
1976 then set both flags. */
1977 if (TARGET_HARD_FLOAT && TARGET_FPRS
1978 && rs6000_single_float == 0 && rs6000_double_float == 0)
1979 rs6000_single_float = rs6000_double_float = 1;
1981 /* Reset single and double FP flags if target is E500. */
1984 rs6000_single_float = rs6000_double_float = 0;
1985 if (TARGET_E500_SINGLE)
1986 rs6000_single_float = 1;
1987 if (TARGET_E500_DOUBLE)
1988 rs6000_single_float = rs6000_double_float = 1;
1991 /* If not explicitly specified via option, decide whether to generate indexed
1992 load/store instructions. */
1993 if (TARGET_AVOID_XFORM == -1)
1994 /* Avoid indexed addressing when targeting Power6 in order to avoid
1995 the DERAT mispredict penalty. */
1996 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB);
1998 rs6000_init_hard_regno_mode_ok ();
2001 /* Implement targetm.vectorize.builtin_mask_for_load. */
2003 rs6000_builtin_mask_for_load (void)
2006 return altivec_builtin_mask_for_load;
2011 /* Implement targetm.vectorize.builtin_conversion.
2012 Returns a decl of a function that implements conversion of an integer vector
2013 into a floating-point vector, or vice-versa. TYPE is the type of the integer
2014 side of the conversion.
2015 Return NULL_TREE if it is not available. */
2017 rs6000_builtin_conversion (enum tree_code code, tree type)
2019 if (!TARGET_ALTIVEC)
2024 case FIX_TRUNC_EXPR:
2025 switch (TYPE_MODE (type))
2028 return TYPE_UNSIGNED (type)
2029 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VCTUXS]
2030 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VCTSXS];
2036 switch (TYPE_MODE (type))
2039 return TYPE_UNSIGNED (type)
2040 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX]
2041 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
2051 /* Implement targetm.vectorize.builtin_mul_widen_even. */
2053 rs6000_builtin_mul_widen_even (tree type)
2055 if (!TARGET_ALTIVEC)
2058 switch (TYPE_MODE (type))
2061 return TYPE_UNSIGNED (type)
2062 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH]
2063 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
2066 return TYPE_UNSIGNED (type)
2067 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB]
2068 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
2074 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2076 rs6000_builtin_mul_widen_odd (tree type)
2078 if (!TARGET_ALTIVEC)
2081 switch (TYPE_MODE (type))
2084 return TYPE_UNSIGNED (type)
2085 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH]
2086 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
2089 return TYPE_UNSIGNED (type)
2090 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB]
2091 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
2098 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2099 after applying N number of iterations. This routine does not determine
2100 how may iterations are required to reach desired alignment. */
2103 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
2110 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
2113 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
2123 /* Assuming that all other types are naturally aligned. CHECKME! */
2128 /* Implement targetm.vectorize.builtin_vec_perm. */
2130 rs6000_builtin_vec_perm (tree type, tree *mask_element_type)
2134 *mask_element_type = unsigned_char_type_node;
2136 switch (TYPE_MODE (type))
2139 d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_16QI];
2143 d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_8HI];
2147 d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_4SI];
2151 d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_4SF];
2162 /* Handle generic options of the form -mfoo=yes/no.
2163 NAME is the option name.
2164 VALUE is the option value.
2165 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2166 whether the option value is 'yes' or 'no' respectively. */
2168 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
2172 else if (!strcmp (value, "yes"))
2174 else if (!strcmp (value, "no"))
2177 error ("unknown -m%s= option specified: '%s'", name, value);
2180 /* Validate and record the size specified with the -mtls-size option. */
2183 rs6000_parse_tls_size_option (void)
2185 if (rs6000_tls_size_string == 0)
2187 else if (strcmp (rs6000_tls_size_string, "16") == 0)
2188 rs6000_tls_size = 16;
2189 else if (strcmp (rs6000_tls_size_string, "32") == 0)
2190 rs6000_tls_size = 32;
2191 else if (strcmp (rs6000_tls_size_string, "64") == 0)
2192 rs6000_tls_size = 64;
2194 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
2198 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
2200 if (DEFAULT_ABI == ABI_DARWIN)
2201 /* The Darwin libraries never set errno, so we might as well
2202 avoid calling them when that's the only reason we would. */
2203 flag_errno_math = 0;
2205 /* Double growth factor to counter reduced min jump length. */
2206 set_param_value ("max-grow-copy-bb-insns", 16);
2208 /* Enable section anchors by default.
2209 Skip section anchors for Objective C and Objective C++
2210 until front-ends fixed. */
2211 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2212 flag_section_anchors = 2;
2215 static enum fpu_type_t
2216 rs6000_parse_fpu_option (const char *option)
2218 if (!strcmp("none", option)) return FPU_NONE;
2219 if (!strcmp("sp_lite", option)) return FPU_SF_LITE;
2220 if (!strcmp("dp_lite", option)) return FPU_DF_LITE;
2221 if (!strcmp("sp_full", option)) return FPU_SF_FULL;
2222 if (!strcmp("dp_full", option)) return FPU_DF_FULL;
2223 error("unknown value %s for -mfpu", option);
2227 /* Implement TARGET_HANDLE_OPTION. */
2230 rs6000_handle_option (size_t code, const char *arg, int value)
2232 enum fpu_type_t fpu_type = FPU_NONE;
2237 target_flags &= ~(MASK_POWER | MASK_POWER2
2238 | MASK_MULTIPLE | MASK_STRING);
2239 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2240 | MASK_MULTIPLE | MASK_STRING);
2242 case OPT_mno_powerpc:
2243 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2244 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2245 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2246 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2249 target_flags &= ~MASK_MINIMAL_TOC;
2250 TARGET_NO_FP_IN_TOC = 0;
2251 TARGET_NO_SUM_IN_TOC = 0;
2252 target_flags_explicit |= MASK_MINIMAL_TOC;
2253 #ifdef TARGET_USES_SYSV4_OPT
2254 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2255 just the same as -mminimal-toc. */
2256 target_flags |= MASK_MINIMAL_TOC;
2257 target_flags_explicit |= MASK_MINIMAL_TOC;
2261 #ifdef TARGET_USES_SYSV4_OPT
2263 /* Make -mtoc behave like -mminimal-toc. */
2264 target_flags |= MASK_MINIMAL_TOC;
2265 target_flags_explicit |= MASK_MINIMAL_TOC;
2269 #ifdef TARGET_USES_AIX64_OPT
2274 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2275 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2276 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2279 #ifdef TARGET_USES_AIX64_OPT
2284 target_flags &= ~MASK_POWERPC64;
2285 target_flags_explicit |= MASK_POWERPC64;
2288 case OPT_minsert_sched_nops_:
2289 rs6000_sched_insert_nops_str = arg;
2292 case OPT_mminimal_toc:
2295 TARGET_NO_FP_IN_TOC = 0;
2296 TARGET_NO_SUM_IN_TOC = 0;
2303 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2304 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2311 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2312 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2316 case OPT_mpowerpc_gpopt:
2317 case OPT_mpowerpc_gfxopt:
2320 target_flags |= MASK_POWERPC;
2321 target_flags_explicit |= MASK_POWERPC;
2325 case OPT_maix_struct_return:
2326 case OPT_msvr4_struct_return:
2327 rs6000_explicit_options.aix_struct_ret = true;
2331 rs6000_explicit_options.vrsave = true;
2332 TARGET_ALTIVEC_VRSAVE = value;
2336 rs6000_explicit_options.vrsave = true;
2337 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2341 rs6000_explicit_options.isel = true;
2342 rs6000_isel = value;
2346 rs6000_explicit_options.isel = true;
2347 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2351 rs6000_explicit_options.spe = true;
2356 rs6000_explicit_options.spe = true;
2357 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2361 rs6000_debug_name = arg;
2364 #ifdef TARGET_USES_SYSV4_OPT
2366 rs6000_abi_name = arg;
2370 rs6000_sdata_name = arg;
2373 case OPT_mtls_size_:
2374 rs6000_tls_size_string = arg;
2377 case OPT_mrelocatable:
2380 target_flags |= MASK_MINIMAL_TOC;
2381 target_flags_explicit |= MASK_MINIMAL_TOC;
2382 TARGET_NO_FP_IN_TOC = 1;
2386 case OPT_mrelocatable_lib:
2389 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2390 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2391 TARGET_NO_FP_IN_TOC = 1;
2395 target_flags &= ~MASK_RELOCATABLE;
2396 target_flags_explicit |= MASK_RELOCATABLE;
2402 if (!strcmp (arg, "altivec"))
2404 rs6000_explicit_options.altivec_abi = true;
2405 rs6000_altivec_abi = 1;
2407 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2410 else if (! strcmp (arg, "no-altivec"))
2412 rs6000_explicit_options.altivec_abi = true;
2413 rs6000_altivec_abi = 0;
2415 else if (! strcmp (arg, "spe"))
2417 rs6000_explicit_options.spe_abi = true;
2419 rs6000_altivec_abi = 0;
2420 if (!TARGET_SPE_ABI)
2421 error ("not configured for ABI: '%s'", arg);
2423 else if (! strcmp (arg, "no-spe"))
2425 rs6000_explicit_options.spe_abi = true;
2429 /* These are here for testing during development only, do not
2430 document in the manual please. */
2431 else if (! strcmp (arg, "d64"))
2433 rs6000_darwin64_abi = 1;
2434 warning (0, "Using darwin64 ABI");
2436 else if (! strcmp (arg, "d32"))
2438 rs6000_darwin64_abi = 0;
2439 warning (0, "Using old darwin ABI");
2442 else if (! strcmp (arg, "ibmlongdouble"))
2444 rs6000_explicit_options.ieee = true;
2445 rs6000_ieeequad = 0;
2446 warning (0, "Using IBM extended precision long double");
2448 else if (! strcmp (arg, "ieeelongdouble"))
2450 rs6000_explicit_options.ieee = true;
2451 rs6000_ieeequad = 1;
2452 warning (0, "Using IEEE extended precision long double");
2457 error ("unknown ABI specified: '%s'", arg);
2463 rs6000_select[1].string = arg;
2467 rs6000_select[2].string = arg;
2470 case OPT_mtraceback_:
2471 rs6000_traceback_name = arg;
2474 case OPT_mfloat_gprs_:
2475 rs6000_explicit_options.float_gprs = true;
2476 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2477 rs6000_float_gprs = 1;
2478 else if (! strcmp (arg, "double"))
2479 rs6000_float_gprs = 2;
2480 else if (! strcmp (arg, "no"))
2481 rs6000_float_gprs = 0;
2484 error ("invalid option for -mfloat-gprs: '%s'", arg);
2489 case OPT_mlong_double_:
2490 rs6000_explicit_options.long_double = true;
2491 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2492 if (value != 64 && value != 128)
2494 error ("Unknown switch -mlong-double-%s", arg);
2495 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2499 rs6000_long_double_type_size = value;
2502 case OPT_msched_costly_dep_:
2503 rs6000_sched_costly_dep_str = arg;
2507 rs6000_explicit_options.alignment = true;
2508 if (! strcmp (arg, "power"))
2510 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2511 some C library functions, so warn about it. The flag may be
2512 useful for performance studies from time to time though, so
2513 don't disable it entirely. */
2514 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2515 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2516 " it is incompatible with the installed C and C++ libraries");
2517 rs6000_alignment_flags = MASK_ALIGN_POWER;
2519 else if (! strcmp (arg, "natural"))
2520 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2523 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2528 case OPT_msingle_float:
2529 if (!TARGET_SINGLE_FPU)
2530 warning (0, "-msingle-float option equivalent to -mhard-float");
2531 /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
2532 rs6000_double_float = 0;
2533 target_flags &= ~MASK_SOFT_FLOAT;
2534 target_flags_explicit |= MASK_SOFT_FLOAT;
2537 case OPT_mdouble_float:
2538 /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
2539 rs6000_single_float = 1;
2540 target_flags &= ~MASK_SOFT_FLOAT;
2541 target_flags_explicit |= MASK_SOFT_FLOAT;
2544 case OPT_msimple_fpu:
2545 if (!TARGET_SINGLE_FPU)
2546 warning (0, "-msimple-fpu option ignored");
2549 case OPT_mhard_float:
2550 /* -mhard_float implies -msingle-float and -mdouble-float. */
2551 rs6000_single_float = rs6000_double_float = 1;
2554 case OPT_msoft_float:
2555 /* -msoft_float implies -mnosingle-float and -mnodouble-float. */
2556 rs6000_single_float = rs6000_double_float = 0;
2560 fpu_type = rs6000_parse_fpu_option(arg);
2561 if (fpu_type != FPU_NONE)
2562 /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */
2564 target_flags &= ~MASK_SOFT_FLOAT;
2565 target_flags_explicit |= MASK_SOFT_FLOAT;
2566 rs6000_xilinx_fpu = 1;
2567 if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL)
2568 rs6000_single_float = 1;
2569 if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL)
2570 rs6000_single_float = rs6000_double_float = 1;
2571 if (fpu_type == FPU_SF_LITE || fpu_type == FPU_DF_LITE)
2572 rs6000_simple_fpu = 1;
2576 /* -mfpu=none is equivalent to -msoft-float */
2577 target_flags |= MASK_SOFT_FLOAT;
2578 target_flags_explicit |= MASK_SOFT_FLOAT;
2579 rs6000_single_float = rs6000_double_float = 0;
2586 /* Do anything needed at the start of the asm file. */
2589 rs6000_file_start (void)
2593 const char *start = buffer;
2594 struct rs6000_cpu_select *ptr;
2595 const char *default_cpu = TARGET_CPU_DEFAULT;
2596 FILE *file = asm_out_file;
2598 default_file_start ();
2600 #ifdef TARGET_BI_ARCH
2601 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2605 if (flag_verbose_asm)
2607 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2608 rs6000_select[0].string = default_cpu;
2610 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2612 ptr = &rs6000_select[i];
2613 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2615 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2620 if (PPC405_ERRATUM77)
2622 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2626 #ifdef USING_ELFOS_H
2627 switch (rs6000_sdata)
2629 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2630 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2631 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2632 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2635 if (rs6000_sdata && g_switch_value)
2637 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2647 #ifdef HAVE_AS_GNU_ATTRIBUTE
2648 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2650 fprintf (file, "\t.gnu_attribute 4, %d\n",
2651 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
2652 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
2654 fprintf (file, "\t.gnu_attribute 8, %d\n",
2655 (TARGET_ALTIVEC_ABI ? 2
2656 : TARGET_SPE_ABI ? 3
2658 fprintf (file, "\t.gnu_attribute 12, %d\n",
2659 aix_struct_return ? 2 : 1);
2664 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2666 switch_to_section (toc_section);
2667 switch_to_section (text_section);
2672 /* Return nonzero if this function is known to have a null epilogue. */
2675 direct_return (void)
2677 if (reload_completed)
2679 rs6000_stack_t *info = rs6000_stack_info ();
2681 if (info->first_gp_reg_save == 32
2682 && info->first_fp_reg_save == 64
2683 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2684 && ! info->lr_save_p
2685 && ! info->cr_save_p
2686 && info->vrsave_mask == 0
2694 /* Return the number of instructions it takes to form a constant in an
2695 integer register. */
2698 num_insns_constant_wide (HOST_WIDE_INT value)
2700 /* signed constant loadable with {cal|addi} */
2701 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2704 /* constant loadable with {cau|addis} */
2705 else if ((value & 0xffff) == 0
2706 && (value >> 31 == -1 || value >> 31 == 0))
2709 #if HOST_BITS_PER_WIDE_INT == 64
2710 else if (TARGET_POWERPC64)
2712 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2713 HOST_WIDE_INT high = value >> 31;
2715 if (high == 0 || high == -1)
2721 return num_insns_constant_wide (high) + 1;
2723 return (num_insns_constant_wide (high)
2724 + num_insns_constant_wide (low) + 1);
2733 num_insns_constant (rtx op, enum machine_mode mode)
2735 HOST_WIDE_INT low, high;
2737 switch (GET_CODE (op))
2740 #if HOST_BITS_PER_WIDE_INT == 64
2741 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2742 && mask64_operand (op, mode))
2746 return num_insns_constant_wide (INTVAL (op));
2749 if (mode == SFmode || mode == SDmode)
2754 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2755 if (DECIMAL_FLOAT_MODE_P (mode))
2756 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
2758 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2759 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2762 if (mode == VOIDmode || mode == DImode)
2764 high = CONST_DOUBLE_HIGH (op);
2765 low = CONST_DOUBLE_LOW (op);
2772 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2773 if (DECIMAL_FLOAT_MODE_P (mode))
2774 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2776 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2777 high = l[WORDS_BIG_ENDIAN == 0];
2778 low = l[WORDS_BIG_ENDIAN != 0];
2782 return (num_insns_constant_wide (low)
2783 + num_insns_constant_wide (high));
2786 if ((high == 0 && low >= 0)
2787 || (high == -1 && low < 0))
2788 return num_insns_constant_wide (low);
2790 else if (mask64_operand (op, mode))
2794 return num_insns_constant_wide (high) + 1;
2797 return (num_insns_constant_wide (high)
2798 + num_insns_constant_wide (low) + 1);
2806 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2807 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2808 corresponding element of the vector, but for V4SFmode and V2SFmode,
2809 the corresponding "float" is interpreted as an SImode integer. */
2812 const_vector_elt_as_int (rtx op, unsigned int elt)
2814 rtx tmp = CONST_VECTOR_ELT (op, elt);
2815 if (GET_MODE (op) == V4SFmode
2816 || GET_MODE (op) == V2SFmode)
2817 tmp = gen_lowpart (SImode, tmp);
2818 return INTVAL (tmp);
2821 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2822 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2823 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2824 all items are set to the same value and contain COPIES replicas of the
2825 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2826 operand and the others are set to the value of the operand's msb. */
2829 vspltis_constant (rtx op, unsigned step, unsigned copies)
2831 enum machine_mode mode = GET_MODE (op);
2832 enum machine_mode inner = GET_MODE_INNER (mode);
2835 unsigned nunits = GET_MODE_NUNITS (mode);
2836 unsigned bitsize = GET_MODE_BITSIZE (inner);
2837 unsigned mask = GET_MODE_MASK (inner);
2839 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2840 HOST_WIDE_INT splat_val = val;
2841 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2843 /* Construct the value to be splatted, if possible. If not, return 0. */
2844 for (i = 2; i <= copies; i *= 2)
2846 HOST_WIDE_INT small_val;
2848 small_val = splat_val >> bitsize;
2850 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2852 splat_val = small_val;
2855 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2856 if (EASY_VECTOR_15 (splat_val))
2859 /* Also check if we can splat, and then add the result to itself. Do so if
2860 the value is positive, of if the splat instruction is using OP's mode;
2861 for splat_val < 0, the splat and the add should use the same mode. */
2862 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2863 && (splat_val >= 0 || (step == 1 && copies == 1)))
2869 /* Check if VAL is present in every STEP-th element, and the
2870 other elements are filled with its most significant bit. */
2871 for (i = 0; i < nunits - 1; ++i)
2873 HOST_WIDE_INT desired_val;
2874 if (((i + 1) & (step - 1)) == 0)
2877 desired_val = msb_val;
2879 if (desired_val != const_vector_elt_as_int (op, i))
2887 /* Return true if OP is of the given MODE and can be synthesized
2888 with a vspltisb, vspltish or vspltisw. */
2891 easy_altivec_constant (rtx op, enum machine_mode mode)
2893 unsigned step, copies;
2895 if (mode == VOIDmode)
2896 mode = GET_MODE (op);
2897 else if (mode != GET_MODE (op))
2900 /* Start with a vspltisw. */
2901 step = GET_MODE_NUNITS (mode) / 4;
2904 if (vspltis_constant (op, step, copies))
2907 /* Then try with a vspltish. */
2913 if (vspltis_constant (op, step, copies))
2916 /* And finally a vspltisb. */
2922 if (vspltis_constant (op, step, copies))
2928 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2929 result is OP. Abort if it is not possible. */
2932 gen_easy_altivec_constant (rtx op)
2934 enum machine_mode mode = GET_MODE (op);
2935 int nunits = GET_MODE_NUNITS (mode);
2936 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2937 unsigned step = nunits / 4;
2938 unsigned copies = 1;
2940 /* Start with a vspltisw. */
2941 if (vspltis_constant (op, step, copies))
2942 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2944 /* Then try with a vspltish. */
2950 if (vspltis_constant (op, step, copies))
2951 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2953 /* And finally a vspltisb. */
2959 if (vspltis_constant (op, step, copies))
2960 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2966 output_vec_const_move (rtx *operands)
2969 enum machine_mode mode;
2974 mode = GET_MODE (dest);
2979 if (zero_constant (vec, mode))
2980 return "vxor %0,%0,%0";
2982 splat_vec = gen_easy_altivec_constant (vec);
2983 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2984 operands[1] = XEXP (splat_vec, 0);
2985 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2988 switch (GET_MODE (splat_vec))
2991 return "vspltisw %0,%1";
2994 return "vspltish %0,%1";
2997 return "vspltisb %0,%1";
3004 gcc_assert (TARGET_SPE);
3006 /* Vector constant 0 is handled as a splitter of V2SI, and in the
3007 pattern of V1DI, V4HI, and V2SF.
3009 FIXME: We should probably return # and add post reload
3010 splitters for these, but this way is so easy ;-). */
3011 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
3012 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
3013 operands[1] = CONST_VECTOR_ELT (vec, 0);
3014 operands[2] = CONST_VECTOR_ELT (vec, 1);
3016 return "li %0,%1\n\tevmergelo %0,%0,%0";
3018 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
3021 /* Initialize TARGET of vector PAIRED to VALS. */
3024 paired_expand_vector_init (rtx target, rtx vals)
3026 enum machine_mode mode = GET_MODE (target);
3027 int n_elts = GET_MODE_NUNITS (mode);
3029 rtx x, new_rtx, tmp, constant_op, op1, op2;
3032 for (i = 0; i < n_elts; ++i)
3034 x = XVECEXP (vals, 0, i);
3035 if (!CONSTANT_P (x))
3040 /* Load from constant pool. */
3041 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
3047 /* The vector is initialized only with non-constants. */
3048 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
3049 XVECEXP (vals, 0, 1));
3051 emit_move_insn (target, new_rtx);
3055 /* One field is non-constant and the other one is a constant. Load the
3056 constant from the constant pool and use ps_merge instruction to
3057 construct the whole vector. */
3058 op1 = XVECEXP (vals, 0, 0);
3059 op2 = XVECEXP (vals, 0, 1);
3061 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
3063 tmp = gen_reg_rtx (GET_MODE (constant_op));
3064 emit_move_insn (tmp, constant_op);
3066 if (CONSTANT_P (op1))
3067 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
3069 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
3071 emit_move_insn (target, new_rtx);
3075 paired_expand_vector_move (rtx operands[])
3077 rtx op0 = operands[0], op1 = operands[1];
3079 emit_move_insn (op0, op1);
3082 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
3083 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
3084 operands for the relation operation COND. This is a recursive
3088 paired_emit_vector_compare (enum rtx_code rcode,
3089 rtx dest, rtx op0, rtx op1,
3090 rtx cc_op0, rtx cc_op1)
3092 rtx tmp = gen_reg_rtx (V2SFmode);
3093 rtx tmp1, max, min, equal_zero;
3095 gcc_assert (TARGET_PAIRED_FLOAT);
3096 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
3102 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
3106 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
3107 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
3111 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
3114 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
3117 tmp1 = gen_reg_rtx (V2SFmode);
3118 max = gen_reg_rtx (V2SFmode);
3119 min = gen_reg_rtx (V2SFmode);
3120 equal_zero = gen_reg_rtx (V2SFmode);
3122 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
3123 emit_insn (gen_selv2sf4
3124 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
3125 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
3126 emit_insn (gen_selv2sf4
3127 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
3128 emit_insn (gen_subv2sf3 (tmp1, min, max));
3129 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
3132 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
3135 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
3138 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
3141 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
3144 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
3153 /* Emit vector conditional expression.
3154 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
3155 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
3158 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
3159 rtx cond, rtx cc_op0, rtx cc_op1)
3161 enum rtx_code rcode = GET_CODE (cond);
3163 if (!TARGET_PAIRED_FLOAT)
3166 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
3171 /* Initialize vector TARGET to VALS. */
3174 rs6000_expand_vector_init (rtx target, rtx vals)
3176 enum machine_mode mode = GET_MODE (target);
3177 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3178 int n_elts = GET_MODE_NUNITS (mode);
3179 int n_var = 0, one_var = -1;
3180 bool all_same = true, all_const_zero = true;
3184 for (i = 0; i < n_elts; ++i)
3186 x = XVECEXP (vals, 0, i);
3187 if (!CONSTANT_P (x))
3188 ++n_var, one_var = i;
3189 else if (x != CONST0_RTX (inner_mode))
3190 all_const_zero = false;
3192 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
3198 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
3199 if (mode != V4SFmode && all_const_zero)
3201 /* Zero register. */
3202 emit_insn (gen_rtx_SET (VOIDmode, target,
3203 gen_rtx_XOR (mode, target, target)));
3206 else if (mode != V4SFmode && easy_vector_constant (const_vec, mode))
3208 /* Splat immediate. */
3209 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
3213 ; /* Splat vector element. */
3216 /* Load from constant pool. */
3217 emit_move_insn (target, const_vec);
3222 /* Store value to stack temp. Load vector element. Splat. */
3225 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3226 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
3227 XVECEXP (vals, 0, 0));
3228 x = gen_rtx_UNSPEC (VOIDmode,
3229 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3230 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3232 gen_rtx_SET (VOIDmode,
3235 x = gen_rtx_VEC_SELECT (inner_mode, target,
3236 gen_rtx_PARALLEL (VOIDmode,
3237 gen_rtvec (1, const0_rtx)));
3238 emit_insn (gen_rtx_SET (VOIDmode, target,
3239 gen_rtx_VEC_DUPLICATE (mode, x)));
3243 /* One field is non-constant. Load constant then overwrite
3247 rtx copy = copy_rtx (vals);
3249 /* Load constant part of vector, substitute neighboring value for
3251 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
3252 rs6000_expand_vector_init (target, copy);
3254 /* Insert variable. */
3255 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
3259 /* Construct the vector in memory one field at a time
3260 and load the whole vector. */
3261 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3262 for (i = 0; i < n_elts; i++)
3263 emit_move_insn (adjust_address_nv (mem, inner_mode,
3264 i * GET_MODE_SIZE (inner_mode)),
3265 XVECEXP (vals, 0, i));
3266 emit_move_insn (target, mem);
3269 /* Set field ELT of TARGET to VAL. */
3272 rs6000_expand_vector_set (rtx target, rtx val, int elt)
3274 enum machine_mode mode = GET_MODE (target);
3275 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3276 rtx reg = gen_reg_rtx (mode);
3278 int width = GET_MODE_SIZE (inner_mode);
3281 /* Load single variable value. */
3282 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
3283 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
3284 x = gen_rtx_UNSPEC (VOIDmode,
3285 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
3286 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3288 gen_rtx_SET (VOIDmode,
3292 /* Linear sequence. */
3293 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
3294 for (i = 0; i < 16; ++i)
3295 XVECEXP (mask, 0, i) = GEN_INT (i);
3297 /* Set permute mask to insert element into target. */
3298 for (i = 0; i < width; ++i)
3299 XVECEXP (mask, 0, elt*width + i)
3300 = GEN_INT (i + 0x10);
3301 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
3302 x = gen_rtx_UNSPEC (mode,
3303 gen_rtvec (3, target, reg,
3304 force_reg (V16QImode, x)),
3306 emit_insn (gen_rtx_SET (VOIDmode, target, x));
3309 /* Extract field ELT from VEC into TARGET. */
3312 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
3314 enum machine_mode mode = GET_MODE (vec);
3315 enum machine_mode inner_mode = GET_MODE_INNER (mode);
3318 /* Allocate mode-sized buffer. */
3319 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
3321 /* Add offset to field within buffer matching vector element. */
3322 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
3324 /* Store single field into mode-sized buffer. */
3325 x = gen_rtx_UNSPEC (VOIDmode,
3326 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
3327 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3329 gen_rtx_SET (VOIDmode,
3332 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
3335 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3336 implement ANDing by the mask IN. */
3338 build_mask64_2_operands (rtx in, rtx *out)
3340 #if HOST_BITS_PER_WIDE_INT >= 64
3341 unsigned HOST_WIDE_INT c, lsb, m1, m2;
3344 gcc_assert (GET_CODE (in) == CONST_INT);
3349 /* Assume c initially something like 0x00fff000000fffff. The idea
3350 is to rotate the word so that the middle ^^^^^^ group of zeros
3351 is at the MS end and can be cleared with an rldicl mask. We then
3352 rotate back and clear off the MS ^^ group of zeros with a
3354 c = ~c; /* c == 0xff000ffffff00000 */
3355 lsb = c & -c; /* lsb == 0x0000000000100000 */
3356 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
3357 c = ~c; /* c == 0x00fff000000fffff */
3358 c &= -lsb; /* c == 0x00fff00000000000 */
3359 lsb = c & -c; /* lsb == 0x0000100000000000 */
3360 c = ~c; /* c == 0xff000fffffffffff */
3361 c &= -lsb; /* c == 0xff00000000000000 */
3363 while ((lsb >>= 1) != 0)
3364 shift++; /* shift == 44 on exit from loop */
3365 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
3366 m1 = ~m1; /* m1 == 0x000000ffffffffff */
3367 m2 = ~c; /* m2 == 0x00ffffffffffffff */
3371 /* Assume c initially something like 0xff000f0000000000. The idea
3372 is to rotate the word so that the ^^^ middle group of zeros
3373 is at the LS end and can be cleared with an rldicr mask. We then
3374 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3376 lsb = c & -c; /* lsb == 0x0000010000000000 */
3377 m2 = -lsb; /* m2 == 0xffffff0000000000 */
3378 c = ~c; /* c == 0x00fff0ffffffffff */
3379 c &= -lsb; /* c == 0x00fff00000000000 */
3380 lsb = c & -c; /* lsb == 0x0000100000000000 */
3381 c = ~c; /* c == 0xff000fffffffffff */
3382 c &= -lsb; /* c == 0xff00000000000000 */
3384 while ((lsb >>= 1) != 0)
3385 shift++; /* shift == 44 on exit from loop */
3386 m1 = ~c; /* m1 == 0x00ffffffffffffff */
3387 m1 >>= shift; /* m1 == 0x0000000000000fff */
3388 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
3391 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3392 masks will be all 1's. We are guaranteed more than one transition. */
3393 out[0] = GEN_INT (64 - shift);
3394 out[1] = GEN_INT (m1);
3395 out[2] = GEN_INT (shift);
3396 out[3] = GEN_INT (m2);
3404 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3407 invalid_e500_subreg (rtx op, enum machine_mode mode)
3409 if (TARGET_E500_DOUBLE)
3411 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3412 subreg:TI and reg:TF. Decimal float modes are like integer
3413 modes (only low part of each register used) for this
3415 if (GET_CODE (op) == SUBREG
3416 && (mode == SImode || mode == DImode || mode == TImode
3417 || mode == DDmode || mode == TDmode)
3418 && REG_P (SUBREG_REG (op))
3419 && (GET_MODE (SUBREG_REG (op)) == DFmode
3420 || GET_MODE (SUBREG_REG (op)) == TFmode))
3423 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3425 if (GET_CODE (op) == SUBREG
3426 && (mode == DFmode || mode == TFmode)
3427 && REG_P (SUBREG_REG (op))
3428 && (GET_MODE (SUBREG_REG (op)) == DImode
3429 || GET_MODE (SUBREG_REG (op)) == TImode
3430 || GET_MODE (SUBREG_REG (op)) == DDmode
3431 || GET_MODE (SUBREG_REG (op)) == TDmode))
3436 && GET_CODE (op) == SUBREG
3438 && REG_P (SUBREG_REG (op))
3439 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
3445 /* AIX increases natural record alignment to doubleword if the first
3446 field is an FP double while the FP fields remain word aligned. */
3449 rs6000_special_round_type_align (tree type, unsigned int computed,
3450 unsigned int specified)
3452 unsigned int align = MAX (computed, specified);
3453 tree field = TYPE_FIELDS (type);
3455 /* Skip all non field decls */
3456 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3457 field = TREE_CHAIN (field);
3459 if (field != NULL && field != type)
3461 type = TREE_TYPE (field);
3462 while (TREE_CODE (type) == ARRAY_TYPE)
3463 type = TREE_TYPE (type);
3465 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3466 align = MAX (align, 64);
3472 /* Darwin increases record alignment to the natural alignment of
3476 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3477 unsigned int specified)
3479 unsigned int align = MAX (computed, specified);
3481 if (TYPE_PACKED (type))
3484 /* Find the first field, looking down into aggregates. */
3486 tree field = TYPE_FIELDS (type);
3487 /* Skip all non field decls */
3488 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3489 field = TREE_CHAIN (field);
3492 type = TREE_TYPE (field);
3493 while (TREE_CODE (type) == ARRAY_TYPE)
3494 type = TREE_TYPE (type);
3495 } while (AGGREGATE_TYPE_P (type));
3497 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3498 align = MAX (align, TYPE_ALIGN (type));
3503 /* Return 1 for an operand in small memory on V.4/eabi. */
3506 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3507 enum machine_mode mode ATTRIBUTE_UNUSED)
3512 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3515 if (DEFAULT_ABI != ABI_V4)
3518 /* Vector and float memory instructions have a limited offset on the
3519 SPE, so using a vector or float variable directly as an operand is
3522 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
3525 if (GET_CODE (op) == SYMBOL_REF)
3528 else if (GET_CODE (op) != CONST
3529 || GET_CODE (XEXP (op, 0)) != PLUS
3530 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3531 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3536 rtx sum = XEXP (op, 0);
3537 HOST_WIDE_INT summand;
3539 /* We have to be careful here, because it is the referenced address
3540 that must be 32k from _SDA_BASE_, not just the symbol. */
3541 summand = INTVAL (XEXP (sum, 1));
3542 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3545 sym_ref = XEXP (sum, 0);
3548 return SYMBOL_REF_SMALL_P (sym_ref);
3554 /* Return true if either operand is a general purpose register. */
3557 gpr_or_gpr_p (rtx op0, rtx op1)
3559 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3560 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3564 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3567 constant_pool_expr_p (rtx op)
3571 split_const (op, &base, &offset);
3572 return (GET_CODE (base) == SYMBOL_REF
3573 && CONSTANT_POOL_ADDRESS_P (base)
3574 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
3578 toc_relative_expr_p (rtx op)
3582 if (GET_CODE (op) != CONST)
3585 split_const (op, &base, &offset);
3586 return (GET_CODE (base) == UNSPEC
3587 && XINT (base, 1) == UNSPEC_TOCREL);
3591 legitimate_constant_pool_address_p (rtx x)
3594 && GET_CODE (x) == PLUS
3595 && GET_CODE (XEXP (x, 0)) == REG
3596 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3597 && toc_relative_expr_p (XEXP (x, 1)));
3601 legitimate_small_data_p (enum machine_mode mode, rtx x)
3603 return (DEFAULT_ABI == ABI_V4
3604 && !flag_pic && !TARGET_TOC
3605 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3606 && small_data_operand (x, mode));
3609 /* SPE offset addressing is limited to 5-bits worth of double words. */
3610 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3613 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3615 unsigned HOST_WIDE_INT offset, extra;
3617 if (GET_CODE (x) != PLUS)
3619 if (GET_CODE (XEXP (x, 0)) != REG)
3621 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3623 if (legitimate_constant_pool_address_p (x))
3625 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3628 offset = INTVAL (XEXP (x, 1));
3636 /* AltiVec vector modes. Only reg+reg addressing is valid and
3637 constant offset zero should not occur due to canonicalization. */
3644 /* Paired vector modes. Only reg+reg addressing is valid and
3645 constant offset zero should not occur due to canonicalization. */
3646 if (TARGET_PAIRED_FLOAT)
3648 /* SPE vector modes. */
3649 return SPE_CONST_OFFSET_OK (offset);
3652 if (TARGET_E500_DOUBLE)
3653 return SPE_CONST_OFFSET_OK (offset);
3657 /* On e500v2, we may have:
3659 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3661 Which gets addressed with evldd instructions. */
3662 if (TARGET_E500_DOUBLE)
3663 return SPE_CONST_OFFSET_OK (offset);
3665 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3667 else if (offset & 3)
3672 if (TARGET_E500_DOUBLE)
3673 return (SPE_CONST_OFFSET_OK (offset)
3674 && SPE_CONST_OFFSET_OK (offset + 8));
3678 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3680 else if (offset & 3)
3691 return (offset < 0x10000) && (offset + extra < 0x10000);
3695 legitimate_indexed_address_p (rtx x, int strict)
3699 if (GET_CODE (x) != PLUS)
3705 /* Recognize the rtl generated by reload which we know will later be
3706 replaced with proper base and index regs. */
3708 && reload_in_progress
3709 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3713 return (REG_P (op0) && REG_P (op1)
3714 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3715 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3716 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3717 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3721 avoiding_indexed_address_p (enum machine_mode mode)
3723 /* Avoid indexed addressing for modes that have non-indexed
3724 load/store instruction forms. */
3725 return TARGET_AVOID_XFORM && !ALTIVEC_VECTOR_MODE (mode);
3729 legitimate_indirect_address_p (rtx x, int strict)
3731 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3735 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3737 if (!TARGET_MACHO || !flag_pic
3738 || mode != SImode || GET_CODE (x) != MEM)
3742 if (GET_CODE (x) != LO_SUM)
3744 if (GET_CODE (XEXP (x, 0)) != REG)
3746 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3750 return CONSTANT_P (x);
3754 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3756 if (GET_CODE (x) != LO_SUM)
3758 if (GET_CODE (XEXP (x, 0)) != REG)
3760 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3762 /* Restrict addressing for DI because of our SUBREG hackery. */
3763 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3764 || mode == DDmode || mode == TDmode
3769 if (TARGET_ELF || TARGET_MACHO)
3771 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3775 if (GET_MODE_NUNITS (mode) != 1)
3777 if (GET_MODE_BITSIZE (mode) > 64
3778 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3779 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
3780 && (mode == DFmode || mode == DDmode))))
3783 return CONSTANT_P (x);
3790 /* Try machine-dependent ways of modifying an illegitimate address
3791 to be legitimate. If we find one, return the new, valid address.
3792 This is used from only one place: `memory_address' in explow.c.
3794 OLDX is the address as it was before break_out_memory_refs was
3795 called. In some cases it is useful to look at this to decide what
3798 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3800 It is always safe for this function to do nothing. It exists to
3801 recognize opportunities to optimize the output.
3803 On RS/6000, first check for the sum of a register with a constant
3804 integer that is out of range. If so, generate code to add the
3805 constant with the low-order 16 bits masked to the register and force
3806 this result into another register (this can be done with `cau').
3807 Then generate an address of REG+(CONST&0xffff), allowing for the
3808 possibility of bit 16 being a one.
3810 Then check for the sum of a register and something not constant, try to
3811 load the other things into a register and return the sum. */
3814 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3815 enum machine_mode mode)
3817 if (GET_CODE (x) == SYMBOL_REF)
3819 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3821 return rs6000_legitimize_tls_address (x, model);
3824 if (GET_CODE (x) == PLUS
3825 && GET_CODE (XEXP (x, 0)) == REG
3826 && GET_CODE (XEXP (x, 1)) == CONST_INT
3827 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
3828 && !((TARGET_POWERPC64
3829 && (mode == DImode || mode == TImode)
3830 && (INTVAL (XEXP (x, 1)) & 3) != 0)
3831 || SPE_VECTOR_MODE (mode)
3832 || ALTIVEC_VECTOR_MODE (mode)
3833 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3834 || mode == DImode || mode == DDmode
3835 || mode == TDmode))))
3837 HOST_WIDE_INT high_int, low_int;
3839 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3840 high_int = INTVAL (XEXP (x, 1)) - low_int;
3841 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3842 GEN_INT (high_int)), 0);
3843 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3845 else if (GET_CODE (x) == PLUS
3846 && GET_CODE (XEXP (x, 0)) == REG
3847 && GET_CODE (XEXP (x, 1)) != CONST_INT
3848 && GET_MODE_NUNITS (mode) == 1
3849 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
3851 || ((mode != DImode && mode != DFmode && mode != DDmode)
3852 || (TARGET_E500_DOUBLE && mode != DDmode)))
3853 && (TARGET_POWERPC64 || mode != DImode)
3854 && !avoiding_indexed_address_p (mode)
3859 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3860 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3862 else if (ALTIVEC_VECTOR_MODE (mode))
3866 /* Make sure both operands are registers. */
3867 if (GET_CODE (x) == PLUS)
3868 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3869 force_reg (Pmode, XEXP (x, 1)));
3871 reg = force_reg (Pmode, x);
3874 else if (SPE_VECTOR_MODE (mode)
3875 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3876 || mode == DDmode || mode == TDmode
3877 || mode == DImode)))
3881 /* We accept [reg + reg] and [reg + OFFSET]. */
3883 if (GET_CODE (x) == PLUS)
3885 rtx op1 = XEXP (x, 0);
3886 rtx op2 = XEXP (x, 1);
3889 op1 = force_reg (Pmode, op1);
3891 if (GET_CODE (op2) != REG
3892 && (GET_CODE (op2) != CONST_INT
3893 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
3894 || (GET_MODE_SIZE (mode) > 8
3895 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
3896 op2 = force_reg (Pmode, op2);
3898 /* We can't always do [reg + reg] for these, because [reg +
3899 reg + offset] is not a legitimate addressing mode. */
3900 y = gen_rtx_PLUS (Pmode, op1, op2);
3902 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
3903 return force_reg (Pmode, y);
3908 return force_reg (Pmode, x);
3914 && GET_CODE (x) != CONST_INT
3915 && GET_CODE (x) != CONST_DOUBLE
3917 && GET_MODE_NUNITS (mode) == 1
3918 && (GET_MODE_BITSIZE (mode) <= 32
3919 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
3920 && (mode == DFmode || mode == DDmode))))
3922 rtx reg = gen_reg_rtx (Pmode);
3923 emit_insn (gen_elf_high (reg, x));
3924 return gen_rtx_LO_SUM (Pmode, reg, x);
3926 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3929 && ! MACHO_DYNAMIC_NO_PIC_P
3931 && GET_CODE (x) != CONST_INT
3932 && GET_CODE (x) != CONST_DOUBLE
3934 && GET_MODE_NUNITS (mode) == 1
3935 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
3936 || (mode != DFmode && mode != DDmode))
3940 rtx reg = gen_reg_rtx (Pmode);
3941 emit_insn (gen_macho_high (reg, x));
3942 return gen_rtx_LO_SUM (Pmode, reg, x);
3945 && GET_CODE (x) == SYMBOL_REF
3946 && constant_pool_expr_p (x)
3947 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3949 return create_TOC_reference (x);
3955 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3956 We need to emit DTP-relative relocations. */
3959 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3964 fputs ("\t.long\t", file);
3967 fputs (DOUBLE_INT_ASM_OP, file);
3972 output_addr_const (file, x);
3973 fputs ("@dtprel+0x8000", file);
3976 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3978 static GTY(()) rtx rs6000_tls_symbol;
3980 rs6000_tls_get_addr (void)
3982 if (!rs6000_tls_symbol)
3983 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3985 return rs6000_tls_symbol;
3988 /* Construct the SYMBOL_REF for TLS GOT references. */
3990 static GTY(()) rtx rs6000_got_symbol;
3992 rs6000_got_sym (void)
3994 if (!rs6000_got_symbol)
3996 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3997 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3998 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
4001 return rs6000_got_symbol;
4004 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4005 this (thread-local) address. */
4008 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
4012 dest = gen_reg_rtx (Pmode);
4013 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
4019 tlsreg = gen_rtx_REG (Pmode, 13);
4020 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
4024 tlsreg = gen_rtx_REG (Pmode, 2);
4025 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
4029 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
4033 tmp = gen_reg_rtx (Pmode);
4036 tlsreg = gen_rtx_REG (Pmode, 13);
4037 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
4041 tlsreg = gen_rtx_REG (Pmode, 2);
4042 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
4046 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
4048 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
4053 rtx r3, got, tga, tmp1, tmp2, eqv;
4055 /* We currently use relocations like @got@tlsgd for tls, which
4056 means the linker will handle allocation of tls entries, placing
4057 them in the .got section. So use a pointer to the .got section,
4058 not one to secondary TOC sections used by 64-bit -mminimal-toc,
4059 or to secondary GOT sections used by 32-bit -fPIC. */
4061 got = gen_rtx_REG (Pmode, 2);
4065 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
4068 rtx gsym = rs6000_got_sym ();
4069 got = gen_reg_rtx (Pmode);
4071 rs6000_emit_move (got, gsym, Pmode);
4077 tmp1 = gen_reg_rtx (Pmode);
4078 tmp2 = gen_reg_rtx (Pmode);
4079 tmp3 = gen_reg_rtx (Pmode);
4080 mem = gen_const_mem (Pmode, tmp1);
4082 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
4083 emit_move_insn (tmp1,
4084 gen_rtx_REG (Pmode, LR_REGNO));
4085 emit_move_insn (tmp2, mem);
4086 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
4087 last = emit_move_insn (got, tmp3);
4088 set_unique_reg_note (last, REG_EQUAL, gsym);
4093 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
4095 r3 = gen_rtx_REG (Pmode, 3);
4096 tga = rs6000_tls_get_addr ();
4098 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4099 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
4100 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
4101 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
4102 else if (DEFAULT_ABI == ABI_V4)
4103 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
4108 insn = emit_call_insn (insn);
4109 RTL_CONST_CALL_P (insn) = 1;
4110 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
4111 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
4112 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4113 insn = get_insns ();
4115 emit_libcall_block (insn, dest, r3, addr);
4117 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
4119 r3 = gen_rtx_REG (Pmode, 3);
4120 tga = rs6000_tls_get_addr ();
4122 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4123 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
4124 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
4125 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
4126 else if (DEFAULT_ABI == ABI_V4)
4127 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
4132 insn = emit_call_insn (insn);
4133 RTL_CONST_CALL_P (insn) = 1;
4134 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
4135 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
4136 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4137 insn = get_insns ();
4139 tmp1 = gen_reg_rtx (Pmode);
4140 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
4142 emit_libcall_block (insn, tmp1, r3, eqv);
4143 if (rs6000_tls_size == 16)
4146 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
4148 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
4150 else if (rs6000_tls_size == 32)
4152 tmp2 = gen_reg_rtx (Pmode);
4154 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
4156 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
4159 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
4161 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
4165 tmp2 = gen_reg_rtx (Pmode);
4167 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
4169 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
4171 insn = gen_rtx_SET (Pmode, dest,
4172 gen_rtx_PLUS (Pmode, tmp2, tmp1));
4178 /* IE, or 64-bit offset LE. */
4179 tmp2 = gen_reg_rtx (Pmode);
4181 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
4183 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
4186 insn = gen_tls_tls_64 (dest, tmp2, addr);
4188 insn = gen_tls_tls_32 (dest, tmp2, addr);
4196 /* Return 1 if X contains a thread-local symbol. */
4199 rs6000_tls_referenced_p (rtx x)
4201 if (! TARGET_HAVE_TLS)
4204 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
4207 /* Return 1 if *X is a thread-local symbol. This is the same as
4208 rs6000_tls_symbol_ref except for the type of the unused argument. */
4211 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4213 return RS6000_SYMBOL_REF_TLS_P (*x);
4216 /* The convention appears to be to define this wherever it is used.
4217 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4218 is now used here. */
4219 #ifndef REG_MODE_OK_FOR_BASE_P
4220 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4223 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4224 replace the input X, or the original X if no replacement is called for.
4225 The output parameter *WIN is 1 if the calling macro should goto WIN,
4228 For RS/6000, we wish to handle large displacements off a base
4229 register by splitting the addend across an addiu/addis and the mem insn.
4230 This cuts number of extra insns needed from 3 to 1.
4232 On Darwin, we use this to generate code for floating point constants.
4233 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4234 The Darwin code is inside #if TARGET_MACHO because only then are the
4235 machopic_* functions defined. */
4237 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
4238 int opnum, int type,
4239 int ind_levels ATTRIBUTE_UNUSED, int *win)
4241 /* We must recognize output that we have already generated ourselves. */
4242 if (GET_CODE (x) == PLUS
4243 && GET_CODE (XEXP (x, 0)) == PLUS
4244 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4245 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4246 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4248 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4249 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4250 opnum, (enum reload_type)type);
4256 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
4257 && GET_CODE (x) == LO_SUM
4258 && GET_CODE (XEXP (x, 0)) == PLUS
4259 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
4260 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
4261 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
4262 && machopic_operand_p (XEXP (x, 1)))
4264 /* Result of previous invocation of this function on Darwin
4265 floating point constant. */
4266 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4267 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4268 opnum, (enum reload_type)type);
4274 /* Force ld/std non-word aligned offset into base register by wrapping
4276 if (GET_CODE (x) == PLUS
4277 && GET_CODE (XEXP (x, 0)) == REG
4278 && REGNO (XEXP (x, 0)) < 32
4279 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4280 && GET_CODE (XEXP (x, 1)) == CONST_INT
4281 && (INTVAL (XEXP (x, 1)) & 3) != 0
4282 && !ALTIVEC_VECTOR_MODE (mode)
4283 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
4284 && TARGET_POWERPC64)
4286 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
4287 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4288 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4289 opnum, (enum reload_type) type);
4294 if (GET_CODE (x) == PLUS
4295 && GET_CODE (XEXP (x, 0)) == REG
4296 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
4297 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
4298 && GET_CODE (XEXP (x, 1)) == CONST_INT
4299 && !SPE_VECTOR_MODE (mode)
4300 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
4301 || mode == DDmode || mode == TDmode
4303 && !ALTIVEC_VECTOR_MODE (mode))
4305 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
4306 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
4308 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4310 /* Check for 32-bit overflow. */
4311 if (high + low != val)
4317 /* Reload the high part into a base reg; leave the low part
4318 in the mem directly. */
4320 x = gen_rtx_PLUS (GET_MODE (x),
4321 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
4325 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4326 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
4327 opnum, (enum reload_type)type);
4332 if (GET_CODE (x) == SYMBOL_REF
4333 && !ALTIVEC_VECTOR_MODE (mode)
4334 && !SPE_VECTOR_MODE (mode)
4336 && DEFAULT_ABI == ABI_DARWIN
4337 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
4339 && DEFAULT_ABI == ABI_V4
4342 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4343 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4347 && (mode != DImode || TARGET_POWERPC64)
4348 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
4349 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
4354 rtx offset = machopic_gen_offset (x);
4355 x = gen_rtx_LO_SUM (GET_MODE (x),
4356 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
4357 gen_rtx_HIGH (Pmode, offset)), offset);
4361 x = gen_rtx_LO_SUM (GET_MODE (x),
4362 gen_rtx_HIGH (Pmode, x), x);
4364 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
4365 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4366 opnum, (enum reload_type)type);
4371 /* Reload an offset address wrapped by an AND that represents the
4372 masking of the lower bits. Strip the outer AND and let reload
4373 convert the offset address into an indirect address. */
4375 && ALTIVEC_VECTOR_MODE (mode)
4376 && GET_CODE (x) == AND
4377 && GET_CODE (XEXP (x, 0)) == PLUS
4378 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4379 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4380 && GET_CODE (XEXP (x, 1)) == CONST_INT
4381 && INTVAL (XEXP (x, 1)) == -16)
4389 && GET_CODE (x) == SYMBOL_REF
4390 && constant_pool_expr_p (x)
4391 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
4393 x = create_TOC_reference (x);
4401 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4402 that is a valid memory address for an instruction.
4403 The MODE argument is the machine mode for the MEM expression
4404 that wants to use this address.
4406 On the RS/6000, there are four valid address: a SYMBOL_REF that
4407 refers to a constant pool entry of an address (or the sum of it
4408 plus a constant), a short (16-bit signed) constant plus a register,
4409 the sum of two registers, or a register indirect, possibly with an
4410 auto-increment. For DFmode, DDmode and DImode with a constant plus
4411 register, we must ensure that both words are addressable or PowerPC64
4412 with offset word aligned.
4414 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4415 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4416 because adjacent memory cells are accessed by adding word-sized offsets
4417 during assembly output. */
4419 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
4421 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4423 && ALTIVEC_VECTOR_MODE (mode)
4424 && GET_CODE (x) == AND
4425 && GET_CODE (XEXP (x, 1)) == CONST_INT
4426 && INTVAL (XEXP (x, 1)) == -16)
4429 if (RS6000_SYMBOL_REF_TLS_P (x))
4431 if (legitimate_indirect_address_p (x, reg_ok_strict))
4433 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
4434 && !ALTIVEC_VECTOR_MODE (mode)
4435 && !SPE_VECTOR_MODE (mode)
4438 /* Restrict addressing for DI because of our SUBREG hackery. */
4439 && !(TARGET_E500_DOUBLE
4440 && (mode == DFmode || mode == DDmode || mode == DImode))
4442 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4444 if (legitimate_small_data_p (mode, x))
4446 if (legitimate_constant_pool_address_p (x))
4448 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4450 && GET_CODE (x) == PLUS
4451 && GET_CODE (XEXP (x, 0)) == REG
4452 && (XEXP (x, 0) == virtual_stack_vars_rtx
4453 || XEXP (x, 0) == arg_pointer_rtx)
4454 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4456 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4461 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4463 || (mode != DFmode && mode != DDmode)
4464 || (TARGET_E500_DOUBLE && mode != DDmode))
4465 && (TARGET_POWERPC64 || mode != DImode)
4466 && !avoiding_indexed_address_p (mode)
4467 && legitimate_indexed_address_p (x, reg_ok_strict))
4469 if (GET_CODE (x) == PRE_MODIFY
4473 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
4475 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
4476 && (TARGET_POWERPC64 || mode != DImode)
4477 && !ALTIVEC_VECTOR_MODE (mode)
4478 && !SPE_VECTOR_MODE (mode)
4479 /* Restrict addressing for DI because of our SUBREG hackery. */
4480 && !(TARGET_E500_DOUBLE
4481 && (mode == DFmode || mode == DDmode || mode == DImode))
4483 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
4484 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
4485 || (!avoiding_indexed_address_p (mode)
4486 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
4487 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4489 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4494 /* Go to LABEL if ADDR (a legitimate address expression)
4495 has an effect that depends on the machine mode it is used for.
4497 On the RS/6000 this is true of all integral offsets (since AltiVec
4498 modes don't allow them) or is a pre-increment or decrement.
4500 ??? Except that due to conceptual problems in offsettable_address_p
4501 we can't really report the problems of integral offsets. So leave
4502 this assuming that the adjustable offset must be valid for the
4503 sub-words of a TFmode operand, which is what we had before. */
4506 rs6000_mode_dependent_address (rtx addr)
4508 switch (GET_CODE (addr))
4511 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4513 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4514 return val + 12 + 0x8000 >= 0x10000;
4521 /* Auto-increment cases are now treated generically in recog.c. */
4523 return TARGET_UPDATE;
4532 /* Implement FIND_BASE_TERM. */
4535 rs6000_find_base_term (rtx op)
4539 split_const (op, &base, &offset);
4540 if (GET_CODE (base) == UNSPEC)
4541 switch (XINT (base, 1))
4544 case UNSPEC_MACHOPIC_OFFSET:
4545 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
4546 for aliasing purposes. */
4547 return XVECEXP (base, 0, 0);
4553 /* More elaborate version of recog's offsettable_memref_p predicate
4554 that works around the ??? note of rs6000_mode_dependent_address.
4555 In particular it accepts
4557 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4559 in 32-bit mode, that the recog predicate rejects. */
4562 rs6000_offsettable_memref_p (rtx op)
4567 /* First mimic offsettable_memref_p. */
4568 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4571 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4572 the latter predicate knows nothing about the mode of the memory
4573 reference and, therefore, assumes that it is the largest supported
4574 mode (TFmode). As a consequence, legitimate offsettable memory
4575 references are rejected. rs6000_legitimate_offset_address_p contains
4576 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4577 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4580 /* Return number of consecutive hard regs needed starting at reg REGNO
4581 to hold something of mode MODE.
4582 This is ordinarily the length in words of a value of mode MODE
4583 but can be less for certain modes in special long registers.
4585 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4586 scalar instructions. The upper 32 bits are only available to the
4589 POWER and PowerPC GPRs hold 32 bits worth;
4590 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4593 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4595 if (FP_REGNO_P (regno))
4596 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4598 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4599 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4601 if (ALTIVEC_REGNO_P (regno))
4603 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4605 /* The value returned for SCmode in the E500 double case is 2 for
4606 ABI compatibility; storing an SCmode value in a single register
4607 would require function_arg and rs6000_spe_function_arg to handle
4608 SCmode so as to pass the value correctly in a pair of
4610 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
4611 && !DECIMAL_FLOAT_MODE_P (mode))
4612 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4614 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4617 /* Change register usage conditional on target flags. */
4619 rs6000_conditional_register_usage (void)
4623 /* Set MQ register fixed (already call_used) if not POWER
4624 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4629 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4631 fixed_regs[13] = call_used_regs[13]
4632 = call_really_used_regs[13] = 1;
4634 /* Conditionally disable FPRs. */
4635 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4636 for (i = 32; i < 64; i++)
4637 fixed_regs[i] = call_used_regs[i]
4638 = call_really_used_regs[i] = 1;
4640 /* The TOC register is not killed across calls in a way that is
4641 visible to the compiler. */
4642 if (DEFAULT_ABI == ABI_AIX)
4643 call_really_used_regs[2] = 0;
4645 if (DEFAULT_ABI == ABI_V4
4646 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4648 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4650 if (DEFAULT_ABI == ABI_V4
4651 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4653 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4654 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4655 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4657 if (DEFAULT_ABI == ABI_DARWIN
4658 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4659 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4660 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4661 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4663 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4664 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4665 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4669 global_regs[SPEFSCR_REGNO] = 1;
4670 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4671 registers in prologues and epilogues. We no longer use r14
4672 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4673 pool for link-compatibility with older versions of GCC. Once
4674 "old" code has died out, we can return r14 to the allocation
4677 = call_used_regs[14]
4678 = call_really_used_regs[14] = 1;
4681 if (!TARGET_ALTIVEC)
4683 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4684 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4685 call_really_used_regs[VRSAVE_REGNO] = 1;
4689 global_regs[VSCR_REGNO] = 1;
4691 if (TARGET_ALTIVEC_ABI)
4693 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4694 call_used_regs[i] = call_really_used_regs[i] = 1;
4696 /* AIX reserves VR20:31 in non-extended ABI mode. */
4698 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
4699 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4703 /* Try to output insns to set TARGET equal to the constant C if it can
4704 be done in less than N insns. Do all computations in MODE.
4705 Returns the place where the output has been placed if it can be
4706 done and the insns have been emitted. If it would take more than N
4707 insns, zero is returned and no insns and emitted. */
4710 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4711 rtx source, int n ATTRIBUTE_UNUSED)
4713 rtx result, insn, set;
4714 HOST_WIDE_INT c0, c1;
4721 dest = gen_reg_rtx (mode);
4722 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4726 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4728 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4729 GEN_INT (INTVAL (source)
4730 & (~ (HOST_WIDE_INT) 0xffff))));
4731 emit_insn (gen_rtx_SET (VOIDmode, dest,
4732 gen_rtx_IOR (SImode, copy_rtx (result),
4733 GEN_INT (INTVAL (source) & 0xffff))));
4738 switch (GET_CODE (source))
4741 c0 = INTVAL (source);
4746 #if HOST_BITS_PER_WIDE_INT >= 64
4747 c0 = CONST_DOUBLE_LOW (source);
4750 c0 = CONST_DOUBLE_LOW (source);
4751 c1 = CONST_DOUBLE_HIGH (source);
4759 result = rs6000_emit_set_long_const (dest, c0, c1);
4766 insn = get_last_insn ();
4767 set = single_set (insn);
4768 if (! CONSTANT_P (SET_SRC (set)))
4769 set_unique_reg_note (insn, REG_EQUAL, source);
4774 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4775 fall back to a straight forward decomposition. We do this to avoid
4776 exponential run times encountered when looking for longer sequences
4777 with rs6000_emit_set_const. */
4779 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4781 if (!TARGET_POWERPC64)
4783 rtx operand1, operand2;
4785 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4787 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4789 emit_move_insn (operand1, GEN_INT (c1));
4790 emit_move_insn (operand2, GEN_INT (c2));
4794 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4797 ud2 = (c1 & 0xffff0000) >> 16;
4798 #if HOST_BITS_PER_WIDE_INT >= 64
4802 ud4 = (c2 & 0xffff0000) >> 16;
4804 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4805 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4808 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4810 emit_move_insn (dest, GEN_INT (ud1));
4813 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4814 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4817 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4820 emit_move_insn (dest, GEN_INT (ud2 << 16));
4822 emit_move_insn (copy_rtx (dest),
4823 gen_rtx_IOR (DImode, copy_rtx (dest),
4826 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4827 || (ud4 == 0 && ! (ud3 & 0x8000)))
4830 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4833 emit_move_insn (dest, GEN_INT (ud3 << 16));
4836 emit_move_insn (copy_rtx (dest),
4837 gen_rtx_IOR (DImode, copy_rtx (dest),
4839 emit_move_insn (copy_rtx (dest),
4840 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4843 emit_move_insn (copy_rtx (dest),
4844 gen_rtx_IOR (DImode, copy_rtx (dest),
4850 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4853 emit_move_insn (dest, GEN_INT (ud4 << 16));
4856 emit_move_insn (copy_rtx (dest),
4857 gen_rtx_IOR (DImode, copy_rtx (dest),
4860 emit_move_insn (copy_rtx (dest),
4861 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4864 emit_move_insn (copy_rtx (dest),
4865 gen_rtx_IOR (DImode, copy_rtx (dest),
4866 GEN_INT (ud2 << 16)));
4868 emit_move_insn (copy_rtx (dest),
4869 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4875 /* Helper for the following. Get rid of [r+r] memory refs
4876 in cases where it won't work (TImode, TFmode, TDmode). */
4879 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4881 if (GET_CODE (operands[0]) == MEM
4882 && GET_CODE (XEXP (operands[0], 0)) != REG
4883 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4884 && ! reload_in_progress)
4886 = replace_equiv_address (operands[0],
4887 copy_addr_to_reg (XEXP (operands[0], 0)));
4889 if (GET_CODE (operands[1]) == MEM
4890 && GET_CODE (XEXP (operands[1], 0)) != REG
4891 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4892 && ! reload_in_progress)
4894 = replace_equiv_address (operands[1],
4895 copy_addr_to_reg (XEXP (operands[1], 0)));
4898 /* Emit a move from SOURCE to DEST in mode MODE. */
4900 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4904 operands[1] = source;
4906 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4907 if (GET_CODE (operands[1]) == CONST_DOUBLE
4908 && ! FLOAT_MODE_P (mode)
4909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4911 /* FIXME. This should never happen. */
4912 /* Since it seems that it does, do the safe thing and convert
4914 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4916 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4917 || FLOAT_MODE_P (mode)
4918 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4919 || CONST_DOUBLE_LOW (operands[1]) < 0)
4920 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4921 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4923 /* Check if GCC is setting up a block move that will end up using FP
4924 registers as temporaries. We must make sure this is acceptable. */
4925 if (GET_CODE (operands[0]) == MEM
4926 && GET_CODE (operands[1]) == MEM
4928 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4929 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4930 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4931 ? 32 : MEM_ALIGN (operands[0])))
4932 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4934 : MEM_ALIGN (operands[1]))))
4935 && ! MEM_VOLATILE_P (operands [0])
4936 && ! MEM_VOLATILE_P (operands [1]))
4938 emit_move_insn (adjust_address (operands[0], SImode, 0),
4939 adjust_address (operands[1], SImode, 0));
4940 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4941 adjust_address (copy_rtx (operands[1]), SImode, 4));
4945 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4946 && !gpc_reg_operand (operands[1], mode))
4947 operands[1] = force_reg (mode, operands[1]);
4949 if (mode == SFmode && ! TARGET_POWERPC
4950 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4951 && GET_CODE (operands[0]) == MEM)
4955 if (reload_in_progress || reload_completed)
4956 regnum = true_regnum (operands[1]);
4957 else if (GET_CODE (operands[1]) == REG)
4958 regnum = REGNO (operands[1]);
4962 /* If operands[1] is a register, on POWER it may have
4963 double-precision data in it, so truncate it to single
4965 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4968 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4969 : gen_reg_rtx (mode));
4970 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4971 operands[1] = newreg;
4975 /* Recognize the case where operand[1] is a reference to thread-local
4976 data and load its address to a register. */
4977 if (rs6000_tls_referenced_p (operands[1]))
4979 enum tls_model model;
4980 rtx tmp = operands[1];
4983 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4985 addend = XEXP (XEXP (tmp, 0), 1);
4986 tmp = XEXP (XEXP (tmp, 0), 0);
4989 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4990 model = SYMBOL_REF_TLS_MODEL (tmp);
4991 gcc_assert (model != 0);
4993 tmp = rs6000_legitimize_tls_address (tmp, model);
4996 tmp = gen_rtx_PLUS (mode, tmp, addend);
4997 tmp = force_operand (tmp, operands[0]);
5002 /* Handle the case where reload calls us with an invalid address. */
5003 if (reload_in_progress && mode == Pmode
5004 && (! general_operand (operands[1], mode)
5005 || ! nonimmediate_operand (operands[0], mode)))
5008 /* 128-bit constant floating-point values on Darwin should really be
5009 loaded as two parts. */
5010 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
5011 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
5013 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
5014 know how to get a DFmode SUBREG of a TFmode. */
5015 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
5016 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
5017 simplify_gen_subreg (imode, operands[1], mode, 0),
5019 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
5020 GET_MODE_SIZE (imode)),
5021 simplify_gen_subreg (imode, operands[1], mode,
5022 GET_MODE_SIZE (imode)),
5027 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
5028 cfun->machine->sdmode_stack_slot =
5029 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
5031 if (reload_in_progress
5033 && MEM_P (operands[0])
5034 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
5035 && REG_P (operands[1]))
5037 if (FP_REGNO_P (REGNO (operands[1])))
5039 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
5040 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
5041 emit_insn (gen_movsd_store (mem, operands[1]));
5043 else if (INT_REGNO_P (REGNO (operands[1])))
5045 rtx mem = adjust_address_nv (operands[0], mode, 4);
5046 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
5047 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
5053 if (reload_in_progress
5055 && REG_P (operands[0])
5056 && MEM_P (operands[1])
5057 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
5059 if (FP_REGNO_P (REGNO (operands[0])))
5061 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
5062 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
5063 emit_insn (gen_movsd_load (operands[0], mem));
5065 else if (INT_REGNO_P (REGNO (operands[0])))
5067 rtx mem = adjust_address_nv (operands[1], mode, 4);
5068 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
5069 emit_insn (gen_movsd_hardfloat (operands[0], mem));
5076 /* FIXME: In the long term, this switch statement should go away
5077 and be replaced by a sequence of tests based on things like
5083 if (CONSTANT_P (operands[1])
5084 && GET_CODE (operands[1]) != CONST_INT)
5085 operands[1] = force_const_mem (mode, operands[1]);
5090 rs6000_eliminate_indexed_memrefs (operands);
5097 if (CONSTANT_P (operands[1])
5098 && ! easy_fp_constant (operands[1], mode))
5099 operands[1] = force_const_mem (mode, operands[1]);
5110 if (CONSTANT_P (operands[1])
5111 && !easy_vector_constant (operands[1], mode))
5112 operands[1] = force_const_mem (mode, operands[1]);
5117 /* Use default pattern for address of ELF small data */
5120 && DEFAULT_ABI == ABI_V4
5121 && (GET_CODE (operands[1]) == SYMBOL_REF
5122 || GET_CODE (operands[1]) == CONST)
5123 && small_data_operand (operands[1], mode))
5125 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5129 if (DEFAULT_ABI == ABI_V4
5130 && mode == Pmode && mode == SImode
5131 && flag_pic == 1 && got_operand (operands[1], mode))
5133 emit_insn (gen_movsi_got (operands[0], operands[1]));
5137 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
5141 && CONSTANT_P (operands[1])
5142 && GET_CODE (operands[1]) != HIGH
5143 && GET_CODE (operands[1]) != CONST_INT)
5145 rtx target = (!can_create_pseudo_p ()
5147 : gen_reg_rtx (mode));
5149 /* If this is a function address on -mcall-aixdesc,
5150 convert it to the address of the descriptor. */
5151 if (DEFAULT_ABI == ABI_AIX
5152 && GET_CODE (operands[1]) == SYMBOL_REF
5153 && XSTR (operands[1], 0)[0] == '.')
5155 const char *name = XSTR (operands[1], 0);
5157 while (*name == '.')
5159 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
5160 CONSTANT_POOL_ADDRESS_P (new_ref)
5161 = CONSTANT_POOL_ADDRESS_P (operands[1]);
5162 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
5163 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
5164 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
5165 operands[1] = new_ref;
5168 if (DEFAULT_ABI == ABI_DARWIN)
5171 if (MACHO_DYNAMIC_NO_PIC_P)
5173 /* Take care of any required data indirection. */
5174 operands[1] = rs6000_machopic_legitimize_pic_address (
5175 operands[1], mode, operands[0]);
5176 if (operands[0] != operands[1])
5177 emit_insn (gen_rtx_SET (VOIDmode,
5178 operands[0], operands[1]));
5182 emit_insn (gen_macho_high (target, operands[1]));
5183 emit_insn (gen_macho_low (operands[0], target, operands[1]));
5187 emit_insn (gen_elf_high (target, operands[1]));
5188 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5192 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5193 and we have put it in the TOC, we just need to make a TOC-relative
5196 && GET_CODE (operands[1]) == SYMBOL_REF
5197 && constant_pool_expr_p (operands[1])
5198 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
5199 get_pool_mode (operands[1])))
5201 operands[1] = create_TOC_reference (operands[1]);
5203 else if (mode == Pmode
5204 && CONSTANT_P (operands[1])
5205 && ((GET_CODE (operands[1]) != CONST_INT
5206 && ! easy_fp_constant (operands[1], mode))
5207 || (GET_CODE (operands[1]) == CONST_INT
5208 && num_insns_constant (operands[1], mode) > 2)
5209 || (GET_CODE (operands[0]) == REG
5210 && FP_REGNO_P (REGNO (operands[0]))))
5211 && GET_CODE (operands[1]) != HIGH
5212 && ! legitimate_constant_pool_address_p (operands[1])
5213 && ! toc_relative_expr_p (operands[1]))
5215 /* Emit a USE operation so that the constant isn't deleted if
5216 expensive optimizations are turned on because nobody
5217 references it. This should only be done for operands that
5218 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5219 This should not be done for operands that contain LABEL_REFs.
5220 For now, we just handle the obvious case. */
5221 if (GET_CODE (operands[1]) != LABEL_REF)
5222 emit_use (operands[1]);
5225 /* Darwin uses a special PIC legitimizer. */
5226 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
5229 rs6000_machopic_legitimize_pic_address (operands[1], mode,
5231 if (operands[0] != operands[1])
5232 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5237 /* If we are to limit the number of things we put in the TOC and
5238 this is a symbol plus a constant we can add in one insn,
5239 just put the symbol in the TOC and add the constant. Don't do
5240 this if reload is in progress. */
5241 if (GET_CODE (operands[1]) == CONST
5242 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5243 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5244 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
5245 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5246 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5247 && ! side_effects_p (operands[0]))
5250 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
5251 rtx other = XEXP (XEXP (operands[1], 0), 1);
5253 sym = force_reg (mode, sym);
5255 emit_insn (gen_addsi3 (operands[0], sym, other));
5257 emit_insn (gen_adddi3 (operands[0], sym, other));
5261 operands[1] = force_const_mem (mode, operands[1]);
5264 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
5265 && constant_pool_expr_p (XEXP (operands[1], 0))
5266 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5267 get_pool_constant (XEXP (operands[1], 0)),
5268 get_pool_mode (XEXP (operands[1], 0))))
5271 = gen_const_mem (mode,
5272 create_TOC_reference (XEXP (operands[1], 0)));
5273 set_mem_alias_set (operands[1], get_TOC_alias_set ());
5279 rs6000_eliminate_indexed_memrefs (operands);
5283 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5285 gen_rtx_SET (VOIDmode,
5286 operands[0], operands[1]),
5287 gen_rtx_CLOBBER (VOIDmode,
5288 gen_rtx_SCRATCH (SImode)))));
5297 /* Above, we may have called force_const_mem which may have returned
5298 an invalid address. If we can, fix this up; otherwise, reload will
5299 have to deal with it. */
5300 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
5301 operands[1] = validize_mem (operands[1]);
5304 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5307 /* Nonzero if we can use a floating-point register to pass this arg. */
5308 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5309 (SCALAR_FLOAT_MODE_P (MODE) \
5310 && (CUM)->fregno <= FP_ARG_MAX_REG \
5311 && TARGET_HARD_FLOAT && TARGET_FPRS)
5313 /* Nonzero if we can use an AltiVec register to pass this arg. */
5314 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5315 (ALTIVEC_VECTOR_MODE (MODE) \
5316 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5317 && TARGET_ALTIVEC_ABI \
5320 /* Return a nonzero value to say to return the function value in
5321 memory, just as large structures are always returned. TYPE will be
5322 the data type of the value, and FNTYPE will be the type of the
5323 function doing the returning, or @code{NULL} for libcalls.
5325 The AIX ABI for the RS/6000 specifies that all structures are
5326 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5327 specifies that structures <= 8 bytes are returned in r3/r4, but a
5328 draft put them in memory, and GCC used to implement the draft
5329 instead of the final standard. Therefore, aix_struct_return
5330 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5331 compatibility can change DRAFT_V4_STRUCT_RET to override the
5332 default, and -m switches get the final word. See
5333 rs6000_override_options for more details.
5335 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5336 long double support is enabled. These values are returned in memory.
5338 int_size_in_bytes returns -1 for variable size objects, which go in
5339 memory always. The cast to unsigned makes -1 > 8. */
5342 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5344 /* In the darwin64 abi, try to use registers for larger structs
5346 if (rs6000_darwin64_abi
5347 && TREE_CODE (type) == RECORD_TYPE
5348 && int_size_in_bytes (type) > 0)
5350 CUMULATIVE_ARGS valcum;
5354 valcum.fregno = FP_ARG_MIN_REG;
5355 valcum.vregno = ALTIVEC_ARG_MIN_REG;
5356 /* Do a trial code generation as if this were going to be passed
5357 as an argument; if any part goes in memory, we return NULL. */
5358 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
5361 /* Otherwise fall through to more conventional ABI rules. */
5364 if (AGGREGATE_TYPE_P (type)
5365 && (aix_struct_return
5366 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
5369 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5370 modes only exist for GCC vector types if -maltivec. */
5371 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
5372 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5375 /* Return synthetic vectors in memory. */
5376 if (TREE_CODE (type) == VECTOR_TYPE
5377 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5379 static bool warned_for_return_big_vectors = false;
5380 if (!warned_for_return_big_vectors)
5382 warning (0, "GCC vector returned by reference: "
5383 "non-standard ABI extension with no compatibility guarantee");
5384 warned_for_return_big_vectors = true;
5389 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
5395 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5396 for a call to a function whose data type is FNTYPE.
5397 For a library call, FNTYPE is 0.
5399 For incoming args we set the number of arguments in the prototype large
5400 so we never return a PARALLEL. */
5403 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
5404 rtx libname ATTRIBUTE_UNUSED, int incoming,
5405 int libcall, int n_named_args)
5407 static CUMULATIVE_ARGS zero_cumulative;
5409 *cum = zero_cumulative;
5411 cum->fregno = FP_ARG_MIN_REG;
5412 cum->vregno = ALTIVEC_ARG_MIN_REG;
5413 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
5414 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
5415 ? CALL_LIBCALL : CALL_NORMAL);
5416 cum->sysv_gregno = GP_ARG_MIN_REG;
5417 cum->stdarg = fntype
5418 && (TYPE_ARG_TYPES (fntype) != 0
5419 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5420 != void_type_node));
5422 cum->nargs_prototype = 0;
5423 if (incoming || cum->prototype)
5424 cum->nargs_prototype = n_named_args;
5426 /* Check for a longcall attribute. */
5427 if ((!fntype && rs6000_default_long_calls)
5429 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
5430 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
5431 cum->call_cookie |= CALL_LONG;
5433 if (TARGET_DEBUG_ARG)
5435 fprintf (stderr, "\ninit_cumulative_args:");
5438 tree ret_type = TREE_TYPE (fntype);
5439 fprintf (stderr, " ret code = %s,",
5440 tree_code_name[ (int)TREE_CODE (ret_type) ]);
5443 if (cum->call_cookie & CALL_LONG)
5444 fprintf (stderr, " longcall,");
5446 fprintf (stderr, " proto = %d, nargs = %d\n",
5447 cum->prototype, cum->nargs_prototype);
5452 && TARGET_ALTIVEC_ABI
5453 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
5455 error ("cannot return value in vector register because"
5456 " altivec instructions are disabled, use -maltivec"
5461 /* Return true if TYPE must be passed on the stack and not in registers. */
5464 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
5466 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
5467 return must_pass_in_stack_var_size (mode, type);
5469 return must_pass_in_stack_var_size_or_pad (mode, type);
5472 /* If defined, a C expression which determines whether, and in which
5473 direction, to pad out an argument with extra space. The value
5474 should be of type `enum direction': either `upward' to pad above
5475 the argument, `downward' to pad below, or `none' to inhibit
5478 For the AIX ABI structs are always stored left shifted in their
5482 function_arg_padding (enum machine_mode mode, const_tree type)
5484 #ifndef AGGREGATE_PADDING_FIXED
5485 #define AGGREGATE_PADDING_FIXED 0
5487 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5488 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5491 if (!AGGREGATE_PADDING_FIXED)
5493 /* GCC used to pass structures of the same size as integer types as
5494 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5495 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5496 passed padded downward, except that -mstrict-align further
5497 muddied the water in that multi-component structures of 2 and 4
5498 bytes in size were passed padded upward.
5500 The following arranges for best compatibility with previous
5501 versions of gcc, but removes the -mstrict-align dependency. */
5502 if (BYTES_BIG_ENDIAN)
5504 HOST_WIDE_INT size = 0;
5506 if (mode == BLKmode)
5508 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5509 size = int_size_in_bytes (type);
5512 size = GET_MODE_SIZE (mode);
5514 if (size == 1 || size == 2 || size == 4)
5520 if (AGGREGATES_PAD_UPWARD_ALWAYS)
5522 if (type != 0 && AGGREGATE_TYPE_P (type))
5526 /* Fall back to the default. */
5527 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5530 /* If defined, a C expression that gives the alignment boundary, in bits,
5531 of an argument with the specified mode and type. If it is not defined,
5532 PARM_BOUNDARY is used for all arguments.
5534 V.4 wants long longs and doubles to be double word aligned. Just
5535 testing the mode size is a boneheaded way to do this as it means
5536 that other types such as complex int are also double word aligned.
5537 However, we're stuck with this because changing the ABI might break
5538 existing library interfaces.
5540 Doubleword align SPE vectors.
5541 Quadword align Altivec vectors.
5542 Quadword align large synthetic vector types. */
5545 function_arg_boundary (enum machine_mode mode, tree type)
5547 if (DEFAULT_ABI == ABI_V4
5548 && (GET_MODE_SIZE (mode) == 8
5549 || (TARGET_HARD_FLOAT
5551 && (mode == TFmode || mode == TDmode))))
5553 else if (SPE_VECTOR_MODE (mode)
5554 || (type && TREE_CODE (type) == VECTOR_TYPE
5555 && int_size_in_bytes (type) >= 8
5556 && int_size_in_bytes (type) < 16))
5558 else if (ALTIVEC_VECTOR_MODE (mode)
5559 || (type && TREE_CODE (type) == VECTOR_TYPE
5560 && int_size_in_bytes (type) >= 16))
5562 else if (rs6000_darwin64_abi && mode == BLKmode
5563 && type && TYPE_ALIGN (type) > 64)
5566 return PARM_BOUNDARY;
5569 /* For a function parm of MODE and TYPE, return the starting word in
5570 the parameter area. NWORDS of the parameter area are already used. */
5573 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5576 unsigned int parm_offset;
5578 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5579 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5580 return nwords + (-(parm_offset + nwords) & align);
5583 /* Compute the size (in words) of a function argument. */
5585 static unsigned long
5586 rs6000_arg_size (enum machine_mode mode, tree type)
5590 if (mode != BLKmode)
5591 size = GET_MODE_SIZE (mode);
5593 size = int_size_in_bytes (type);
5596 return (size + 3) >> 2;
5598 return (size + 7) >> 3;
5601 /* Use this to flush pending int fields. */
5604 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5605 HOST_WIDE_INT bitpos)
5607 unsigned int startbit, endbit;
5608 int intregs, intoffset;
5609 enum machine_mode mode;
5611 if (cum->intoffset == -1)
5614 intoffset = cum->intoffset;
5615 cum->intoffset = -1;
5617 if (intoffset % BITS_PER_WORD != 0)
5619 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5621 if (mode == BLKmode)
5623 /* We couldn't find an appropriate mode, which happens,
5624 e.g., in packed structs when there are 3 bytes to load.
5625 Back intoffset back to the beginning of the word in this
5627 intoffset = intoffset & -BITS_PER_WORD;
5631 startbit = intoffset & -BITS_PER_WORD;
5632 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5633 intregs = (endbit - startbit) / BITS_PER_WORD;
5634 cum->words += intregs;
5637 /* The darwin64 ABI calls for us to recurse down through structs,
5638 looking for elements passed in registers. Unfortunately, we have
5639 to track int register count here also because of misalignments
5640 in powerpc alignment mode. */
5643 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5645 HOST_WIDE_INT startbitpos)
5649 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5650 if (TREE_CODE (f) == FIELD_DECL)
5652 HOST_WIDE_INT bitpos = startbitpos;
5653 tree ftype = TREE_TYPE (f);
5654 enum machine_mode mode;
5655 if (ftype == error_mark_node)
5657 mode = TYPE_MODE (ftype);
5659 if (DECL_SIZE (f) != 0
5660 && host_integerp (bit_position (f), 1))
5661 bitpos += int_bit_position (f);
5663 /* ??? FIXME: else assume zero offset. */
5665 if (TREE_CODE (ftype) == RECORD_TYPE)
5666 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5667 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5669 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5670 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5671 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5673 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5675 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5679 else if (cum->intoffset == -1)
5680 cum->intoffset = bitpos;
5684 /* Update the data in CUM to advance over an argument
5685 of mode MODE and data type TYPE.
5686 (TYPE is null for libcalls where that information may not be available.)
5688 Note that for args passed by reference, function_arg will be called
5689 with MODE and TYPE set to that of the pointer to the arg, not the arg
5693 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5694 tree type, int named, int depth)
5698 /* Only tick off an argument if we're not recursing. */
5700 cum->nargs_prototype--;
5702 if (TARGET_ALTIVEC_ABI
5703 && (ALTIVEC_VECTOR_MODE (mode)
5704 || (type && TREE_CODE (type) == VECTOR_TYPE
5705 && int_size_in_bytes (type) == 16)))
5709 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5712 if (!TARGET_ALTIVEC)
5713 error ("cannot pass argument in vector register because"
5714 " altivec instructions are disabled, use -maltivec"
5717 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5718 even if it is going to be passed in a vector register.
5719 Darwin does the same for variable-argument functions. */
5720 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5721 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5731 /* Vector parameters must be 16-byte aligned. This places
5732 them at 2 mod 4 in terms of words in 32-bit mode, since
5733 the parameter save area starts at offset 24 from the
5734 stack. In 64-bit mode, they just have to start on an
5735 even word, since the parameter save area is 16-byte
5736 aligned. Space for GPRs is reserved even if the argument
5737 will be passed in memory. */
5739 align = (2 - cum->words) & 3;
5741 align = cum->words & 1;
5742 cum->words += align + rs6000_arg_size (mode, type);
5744 if (TARGET_DEBUG_ARG)
5746 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5748 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5749 cum->nargs_prototype, cum->prototype,
5750 GET_MODE_NAME (mode));
5754 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5756 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5759 else if (rs6000_darwin64_abi
5761 && TREE_CODE (type) == RECORD_TYPE
5762 && (size = int_size_in_bytes (type)) > 0)
5764 /* Variable sized types have size == -1 and are
5765 treated as if consisting entirely of ints.
5766 Pad to 16 byte boundary if needed. */
5767 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5768 && (cum->words % 2) != 0)
5770 /* For varargs, we can just go up by the size of the struct. */
5772 cum->words += (size + 7) / 8;
5775 /* It is tempting to say int register count just goes up by
5776 sizeof(type)/8, but this is wrong in a case such as
5777 { int; double; int; } [powerpc alignment]. We have to
5778 grovel through the fields for these too. */
5780 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5781 rs6000_darwin64_record_arg_advance_flush (cum,
5782 size * BITS_PER_UNIT);
5785 else if (DEFAULT_ABI == ABI_V4)
5787 if (TARGET_HARD_FLOAT && TARGET_FPRS
5788 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
5789 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
5790 || (mode == TFmode && !TARGET_IEEEQUAD)
5791 || mode == SDmode || mode == DDmode || mode == TDmode))
5793 /* _Decimal128 must use an even/odd register pair. This assumes
5794 that the register number is odd when fregno is odd. */
5795 if (mode == TDmode && (cum->fregno % 2) == 1)
5798 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5799 <= FP_ARG_V4_MAX_REG)
5800 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5803 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5804 if (mode == DFmode || mode == TFmode
5805 || mode == DDmode || mode == TDmode)
5806 cum->words += cum->words & 1;
5807 cum->words += rs6000_arg_size (mode, type);
5812 int n_words = rs6000_arg_size (mode, type);
5813 int gregno = cum->sysv_gregno;
5815 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5816 (r7,r8) or (r9,r10). As does any other 2 word item such
5817 as complex int due to a historical mistake. */
5819 gregno += (1 - gregno) & 1;
5821 /* Multi-reg args are not split between registers and stack. */
5822 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5824 /* Long long and SPE vectors are aligned on the stack.
5825 So are other 2 word items such as complex int due to
5826 a historical mistake. */
5828 cum->words += cum->words & 1;
5829 cum->words += n_words;
5832 /* Note: continuing to accumulate gregno past when we've started
5833 spilling to the stack indicates the fact that we've started
5834 spilling to the stack to expand_builtin_saveregs. */
5835 cum->sysv_gregno = gregno + n_words;
5838 if (TARGET_DEBUG_ARG)
5840 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5841 cum->words, cum->fregno);
5842 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5843 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5844 fprintf (stderr, "mode = %4s, named = %d\n",
5845 GET_MODE_NAME (mode), named);
5850 int n_words = rs6000_arg_size (mode, type);
5851 int start_words = cum->words;
5852 int align_words = rs6000_parm_start (mode, type, start_words);
5854 cum->words = align_words + n_words;
5856 if (SCALAR_FLOAT_MODE_P (mode)
5857 && TARGET_HARD_FLOAT && TARGET_FPRS)
5859 /* _Decimal128 must be passed in an even/odd float register pair.
5860 This assumes that the register number is odd when fregno is
5862 if (mode == TDmode && (cum->fregno % 2) == 1)
5864 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5867 if (TARGET_DEBUG_ARG)
5869 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5870 cum->words, cum->fregno);
5871 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5872 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5873 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5874 named, align_words - start_words, depth);
5880 spe_build_register_parallel (enum machine_mode mode, int gregno)
5887 r1 = gen_rtx_REG (DImode, gregno);
5888 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5889 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5893 r1 = gen_rtx_REG (DImode, gregno);
5894 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5895 r3 = gen_rtx_REG (DImode, gregno + 2);
5896 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5897 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5900 r1 = gen_rtx_REG (DImode, gregno);
5901 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5902 r3 = gen_rtx_REG (DImode, gregno + 2);
5903 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5904 r5 = gen_rtx_REG (DImode, gregno + 4);
5905 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5906 r7 = gen_rtx_REG (DImode, gregno + 6);
5907 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5908 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5915 /* Determine where to put a SIMD argument on the SPE. */
5917 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5920 int gregno = cum->sysv_gregno;
5922 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5923 are passed and returned in a pair of GPRs for ABI compatibility. */
5924 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5925 || mode == DCmode || mode == TCmode))
5927 int n_words = rs6000_arg_size (mode, type);
5929 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5931 gregno += (1 - gregno) & 1;
5933 /* Multi-reg args are not split between registers and stack. */
5934 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5937 return spe_build_register_parallel (mode, gregno);
5941 int n_words = rs6000_arg_size (mode, type);
5943 /* SPE vectors are put in odd registers. */
5944 if (n_words == 2 && (gregno & 1) == 0)
5947 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5950 enum machine_mode m = SImode;
5952 r1 = gen_rtx_REG (m, gregno);
5953 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5954 r2 = gen_rtx_REG (m, gregno + 1);
5955 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5956 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5963 if (gregno <= GP_ARG_MAX_REG)
5964 return gen_rtx_REG (mode, gregno);
5970 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5971 structure between cum->intoffset and bitpos to integer registers. */
5974 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5975 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5977 enum machine_mode mode;
5979 unsigned int startbit, endbit;
5980 int this_regno, intregs, intoffset;
5983 if (cum->intoffset == -1)
5986 intoffset = cum->intoffset;
5987 cum->intoffset = -1;
5989 /* If this is the trailing part of a word, try to only load that
5990 much into the register. Otherwise load the whole register. Note
5991 that in the latter case we may pick up unwanted bits. It's not a
5992 problem at the moment but may wish to revisit. */
5994 if (intoffset % BITS_PER_WORD != 0)
5996 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5998 if (mode == BLKmode)
6000 /* We couldn't find an appropriate mode, which happens,
6001 e.g., in packed structs when there are 3 bytes to load.
6002 Back intoffset back to the beginning of the word in this
6004 intoffset = intoffset & -BITS_PER_WORD;
6011 startbit = intoffset & -BITS_PER_WORD;
6012 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6013 intregs = (endbit - startbit) / BITS_PER_WORD;
6014 this_regno = cum->words + intoffset / BITS_PER_WORD;
6016 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
6019 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
6023 intoffset /= BITS_PER_UNIT;
6026 regno = GP_ARG_MIN_REG + this_regno;
6027 reg = gen_rtx_REG (mode, regno);
6029 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6032 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
6036 while (intregs > 0);
6039 /* Recursive workhorse for the following. */
6042 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
6043 HOST_WIDE_INT startbitpos, rtx rvec[],
6048 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
6049 if (TREE_CODE (f) == FIELD_DECL)
6051 HOST_WIDE_INT bitpos = startbitpos;
6052 tree ftype = TREE_TYPE (f);
6053 enum machine_mode mode;
6054 if (ftype == error_mark_node)
6056 mode = TYPE_MODE (ftype);
6058 if (DECL_SIZE (f) != 0
6059 && host_integerp (bit_position (f), 1))
6060 bitpos += int_bit_position (f);
6062 /* ??? FIXME: else assume zero offset. */
6064 if (TREE_CODE (ftype) == RECORD_TYPE)
6065 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
6066 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
6071 case SCmode: mode = SFmode; break;
6072 case DCmode: mode = DFmode; break;
6073 case TCmode: mode = TFmode; break;
6077 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6079 = gen_rtx_EXPR_LIST (VOIDmode,
6080 gen_rtx_REG (mode, cum->fregno++),
6081 GEN_INT (bitpos / BITS_PER_UNIT));
6082 if (mode == TFmode || mode == TDmode)
6085 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
6087 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
6089 = gen_rtx_EXPR_LIST (VOIDmode,
6090 gen_rtx_REG (mode, cum->vregno++),
6091 GEN_INT (bitpos / BITS_PER_UNIT));
6093 else if (cum->intoffset == -1)
6094 cum->intoffset = bitpos;
6098 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
6099 the register(s) to be used for each field and subfield of a struct
6100 being passed by value, along with the offset of where the
6101 register's value may be found in the block. FP fields go in FP
6102 register, vector fields go in vector registers, and everything
6103 else goes in int registers, packed as in memory.
6105 This code is also used for function return values. RETVAL indicates
6106 whether this is the case.
6108 Much of this is taken from the SPARC V9 port, which has a similar
6109 calling convention. */
6112 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
6113 int named, bool retval)
6115 rtx rvec[FIRST_PSEUDO_REGISTER];
6116 int k = 1, kbase = 1;
6117 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6118 /* This is a copy; modifications are not visible to our caller. */
6119 CUMULATIVE_ARGS copy_cum = *orig_cum;
6120 CUMULATIVE_ARGS *cum = ©_cum;
6122 /* Pad to 16 byte boundary if needed. */
6123 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
6124 && (cum->words % 2) != 0)
6131 /* Put entries into rvec[] for individual FP and vector fields, and
6132 for the chunks of memory that go in int regs. Note we start at
6133 element 1; 0 is reserved for an indication of using memory, and
6134 may or may not be filled in below. */
6135 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
6136 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
6138 /* If any part of the struct went on the stack put all of it there.
6139 This hack is because the generic code for
6140 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
6141 parts of the struct are not at the beginning. */
6145 return NULL_RTX; /* doesn't go in registers at all */
6147 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6149 if (k > 1 || cum->use_stack)
6150 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
6155 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
6158 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
6162 rtx rvec[GP_ARG_NUM_REG + 1];
6164 if (align_words >= GP_ARG_NUM_REG)
6167 n_units = rs6000_arg_size (mode, type);
6169 /* Optimize the simple case where the arg fits in one gpr, except in
6170 the case of BLKmode due to assign_parms assuming that registers are
6171 BITS_PER_WORD wide. */
6173 || (n_units == 1 && mode != BLKmode))
6174 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6177 if (align_words + n_units > GP_ARG_NUM_REG)
6178 /* Not all of the arg fits in gprs. Say that it goes in memory too,
6179 using a magic NULL_RTX component.
6180 This is not strictly correct. Only some of the arg belongs in
6181 memory, not all of it. However, the normal scheme using
6182 function_arg_partial_nregs can result in unusual subregs, eg.
6183 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6184 store the whole arg to memory is often more efficient than code
6185 to store pieces, and we know that space is available in the right
6186 place for the whole arg. */
6187 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6192 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
6193 rtx off = GEN_INT (i++ * 4);
6194 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6196 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
6198 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6201 /* Determine where to put an argument to a function.
6202 Value is zero to push the argument on the stack,
6203 or a hard register in which to store the argument.
6205 MODE is the argument's machine mode.
6206 TYPE is the data type of the argument (as a tree).
6207 This is null for libcalls where that information may
6209 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6210 the preceding args and about the function being called. It is
6211 not modified in this routine.
6212 NAMED is nonzero if this argument is a named parameter
6213 (otherwise it is an extra parameter matching an ellipsis).
6215 On RS/6000 the first eight words of non-FP are normally in registers
6216 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6217 Under V.4, the first 8 FP args are in registers.
6219 If this is floating-point and no prototype is specified, we use
6220 both an FP and integer register (or possibly FP reg and stack). Library
6221 functions (when CALL_LIBCALL is set) always have the proper types for args,
6222 so we can pass the FP value just in one register. emit_library_function
6223 doesn't support PARALLEL anyway.
6225 Note that for args passed by reference, function_arg will be called
6226 with MODE and TYPE set to that of the pointer to the arg, not the arg
6230 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6231 tree type, int named)
6233 enum rs6000_abi abi = DEFAULT_ABI;
6235 /* Return a marker to indicate whether CR1 needs to set or clear the
6236 bit that V.4 uses to say fp args were passed in registers.
6237 Assume that we don't need the marker for software floating point,
6238 or compiler generated library calls. */
6239 if (mode == VOIDmode)
6242 && (cum->call_cookie & CALL_LIBCALL) == 0
6244 || (cum->nargs_prototype < 0
6245 && (cum->prototype || TARGET_NO_PROTOTYPE))))
6247 /* For the SPE, we need to crxor CR6 always. */
6249 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
6250 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
6251 return GEN_INT (cum->call_cookie
6252 | ((cum->fregno == FP_ARG_MIN_REG)
6253 ? CALL_V4_SET_FP_ARGS
6254 : CALL_V4_CLEAR_FP_ARGS));
6257 return GEN_INT (cum->call_cookie);
6260 if (rs6000_darwin64_abi && mode == BLKmode
6261 && TREE_CODE (type) == RECORD_TYPE)
6263 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
6264 if (rslt != NULL_RTX)
6266 /* Else fall through to usual handling. */
6269 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
6270 if (TARGET_64BIT && ! cum->prototype)
6272 /* Vector parameters get passed in vector register
6273 and also in GPRs or memory, in absence of prototype. */
6276 align_words = (cum->words + 1) & ~1;
6278 if (align_words >= GP_ARG_NUM_REG)
6284 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6286 return gen_rtx_PARALLEL (mode,
6288 gen_rtx_EXPR_LIST (VOIDmode,
6290 gen_rtx_EXPR_LIST (VOIDmode,
6291 gen_rtx_REG (mode, cum->vregno),
6295 return gen_rtx_REG (mode, cum->vregno);
6296 else if (TARGET_ALTIVEC_ABI
6297 && (ALTIVEC_VECTOR_MODE (mode)
6298 || (type && TREE_CODE (type) == VECTOR_TYPE
6299 && int_size_in_bytes (type) == 16)))
6301 if (named || abi == ABI_V4)
6305 /* Vector parameters to varargs functions under AIX or Darwin
6306 get passed in memory and possibly also in GPRs. */
6307 int align, align_words, n_words;
6308 enum machine_mode part_mode;
6310 /* Vector parameters must be 16-byte aligned. This places them at
6311 2 mod 4 in terms of words in 32-bit mode, since the parameter
6312 save area starts at offset 24 from the stack. In 64-bit mode,
6313 they just have to start on an even word, since the parameter
6314 save area is 16-byte aligned. */
6316 align = (2 - cum->words) & 3;
6318 align = cum->words & 1;
6319 align_words = cum->words + align;
6321 /* Out of registers? Memory, then. */
6322 if (align_words >= GP_ARG_NUM_REG)
6325 if (TARGET_32BIT && TARGET_POWERPC64)
6326 return rs6000_mixed_function_arg (mode, type, align_words);
6328 /* The vector value goes in GPRs. Only the part of the
6329 value in GPRs is reported here. */
6331 n_words = rs6000_arg_size (mode, type);
6332 if (align_words + n_words > GP_ARG_NUM_REG)
6333 /* Fortunately, there are only two possibilities, the value
6334 is either wholly in GPRs or half in GPRs and half not. */
6337 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
6340 else if (TARGET_SPE_ABI && TARGET_SPE
6341 && (SPE_VECTOR_MODE (mode)
6342 || (TARGET_E500_DOUBLE && (mode == DFmode
6345 || mode == TCmode))))
6346 return rs6000_spe_function_arg (cum, mode, type);
6348 else if (abi == ABI_V4)
6350 if (TARGET_HARD_FLOAT && TARGET_FPRS
6351 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
6352 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
6353 || (mode == TFmode && !TARGET_IEEEQUAD)
6354 || mode == SDmode || mode == DDmode || mode == TDmode))
6356 /* _Decimal128 must use an even/odd register pair. This assumes
6357 that the register number is odd when fregno is odd. */
6358 if (mode == TDmode && (cum->fregno % 2) == 1)
6361 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
6362 <= FP_ARG_V4_MAX_REG)
6363 return gen_rtx_REG (mode, cum->fregno);
6369 int n_words = rs6000_arg_size (mode, type);
6370 int gregno = cum->sysv_gregno;
6372 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6373 (r7,r8) or (r9,r10). As does any other 2 word item such
6374 as complex int due to a historical mistake. */
6376 gregno += (1 - gregno) & 1;
6378 /* Multi-reg args are not split between registers and stack. */
6379 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
6382 if (TARGET_32BIT && TARGET_POWERPC64)
6383 return rs6000_mixed_function_arg (mode, type,
6384 gregno - GP_ARG_MIN_REG);
6385 return gen_rtx_REG (mode, gregno);
6390 int align_words = rs6000_parm_start (mode, type, cum->words);
6392 /* _Decimal128 must be passed in an even/odd float register pair.
6393 This assumes that the register number is odd when fregno is odd. */
6394 if (mode == TDmode && (cum->fregno % 2) == 1)
6397 if (USE_FP_FOR_ARG_P (cum, mode, type))
6399 rtx rvec[GP_ARG_NUM_REG + 1];
6403 enum machine_mode fmode = mode;
6404 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
6406 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
6408 /* Currently, we only ever need one reg here because complex
6409 doubles are split. */
6410 gcc_assert (cum->fregno == FP_ARG_MAX_REG
6411 && (fmode == TFmode || fmode == TDmode));
6413 /* Long double or _Decimal128 split over regs and memory. */
6414 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
6417 /* Do we also need to pass this arg in the parameter save
6420 && (cum->nargs_prototype <= 0
6421 || (DEFAULT_ABI == ABI_AIX
6423 && align_words >= GP_ARG_NUM_REG)));
6425 if (!needs_psave && mode == fmode)
6426 return gen_rtx_REG (fmode, cum->fregno);
6431 /* Describe the part that goes in gprs or the stack.
6432 This piece must come first, before the fprs. */
6433 if (align_words < GP_ARG_NUM_REG)
6435 unsigned long n_words = rs6000_arg_size (mode, type);
6437 if (align_words + n_words > GP_ARG_NUM_REG
6438 || (TARGET_32BIT && TARGET_POWERPC64))
6440 /* If this is partially on the stack, then we only
6441 include the portion actually in registers here. */
6442 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
6445 if (align_words + n_words > GP_ARG_NUM_REG)
6446 /* Not all of the arg fits in gprs. Say that it
6447 goes in memory too, using a magic NULL_RTX
6448 component. Also see comment in
6449 rs6000_mixed_function_arg for why the normal
6450 function_arg_partial_nregs scheme doesn't work
6452 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
6456 r = gen_rtx_REG (rmode,
6457 GP_ARG_MIN_REG + align_words);
6458 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
6459 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
6461 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
6465 /* The whole arg fits in gprs. */
6466 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6467 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6471 /* It's entirely in memory. */
6472 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6475 /* Describe where this piece goes in the fprs. */
6476 r = gen_rtx_REG (fmode, cum->fregno);
6477 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
6479 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
6481 else if (align_words < GP_ARG_NUM_REG)
6483 if (TARGET_32BIT && TARGET_POWERPC64)
6484 return rs6000_mixed_function_arg (mode, type, align_words);
6486 if (mode == BLKmode)
6489 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
6496 /* For an arg passed partly in registers and partly in memory, this is
6497 the number of bytes passed in registers. For args passed entirely in
6498 registers or entirely in memory, zero. When an arg is described by a
6499 PARALLEL, perhaps using more than one register type, this function
6500 returns the number of bytes used by the first element of the PARALLEL. */
6503 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6504 tree type, bool named)
6509 if (DEFAULT_ABI == ABI_V4)
6512 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
6513 && cum->nargs_prototype >= 0)
6516 /* In this complicated case we just disable the partial_nregs code. */
6517 if (rs6000_darwin64_abi && mode == BLKmode
6518 && TREE_CODE (type) == RECORD_TYPE
6519 && int_size_in_bytes (type) > 0)
6522 align_words = rs6000_parm_start (mode, type, cum->words);
6524 if (USE_FP_FOR_ARG_P (cum, mode, type))
6526 /* If we are passing this arg in the fixed parameter save area
6527 (gprs or memory) as well as fprs, then this function should
6528 return the number of partial bytes passed in the parameter
6529 save area rather than partial bytes passed in fprs. */
6531 && (cum->nargs_prototype <= 0
6532 || (DEFAULT_ABI == ABI_AIX
6534 && align_words >= GP_ARG_NUM_REG)))
6536 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
6537 > FP_ARG_MAX_REG + 1)
6538 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
6539 else if (cum->nargs_prototype >= 0)
6543 if (align_words < GP_ARG_NUM_REG
6544 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
6545 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
6547 if (ret != 0 && TARGET_DEBUG_ARG)
6548 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
6553 /* A C expression that indicates when an argument must be passed by
6554 reference. If nonzero for an argument, a copy of that argument is
6555 made in memory and a pointer to the argument is passed instead of
6556 the argument itself. The pointer is passed in whatever way is
6557 appropriate for passing a pointer to that type.
6559 Under V.4, aggregates and long double are passed by reference.
6561 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6562 reference unless the AltiVec vector extension ABI is in force.
6564 As an extension to all ABIs, variable sized types are passed by
6568 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6569 enum machine_mode mode, const_tree type,
6570 bool named ATTRIBUTE_UNUSED)
6572 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6574 if (TARGET_DEBUG_ARG)
6575 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6582 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6584 if (TARGET_DEBUG_ARG)
6585 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6589 if (int_size_in_bytes (type) < 0)
6591 if (TARGET_DEBUG_ARG)
6592 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6596 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6597 modes only exist for GCC vector types if -maltivec. */
6598 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6600 if (TARGET_DEBUG_ARG)
6601 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6605 /* Pass synthetic vectors in memory. */
6606 if (TREE_CODE (type) == VECTOR_TYPE
6607 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6609 static bool warned_for_pass_big_vectors = false;
6610 if (TARGET_DEBUG_ARG)
6611 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6612 if (!warned_for_pass_big_vectors)
6614 warning (0, "GCC vector passed by reference: "
6615 "non-standard ABI extension with no compatibility guarantee");
6616 warned_for_pass_big_vectors = true;
6625 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6628 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6633 for (i = 0; i < nregs; i++)
6635 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6636 if (reload_completed)
6638 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6641 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6642 i * GET_MODE_SIZE (reg_mode));
6645 tem = replace_equiv_address (tem, XEXP (tem, 0));
6649 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6653 /* Perform any needed actions needed for a function that is receiving a
6654 variable number of arguments.
6658 MODE and TYPE are the mode and type of the current parameter.
6660 PRETEND_SIZE is a variable that should be set to the amount of stack
6661 that must be pushed by the prolog to pretend that our caller pushed
6664 Normally, this macro will push all remaining incoming registers on the
6665 stack and set PRETEND_SIZE to the length of the registers pushed. */
6668 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6669 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6672 CUMULATIVE_ARGS next_cum;
6673 int reg_size = TARGET_32BIT ? 4 : 8;
6674 rtx save_area = NULL_RTX, mem;
6675 int first_reg_offset;
6678 /* Skip the last named argument. */
6680 function_arg_advance (&next_cum, mode, type, 1, 0);
6682 if (DEFAULT_ABI == ABI_V4)
6684 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6688 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6689 HOST_WIDE_INT offset = 0;
6691 /* Try to optimize the size of the varargs save area.
6692 The ABI requires that ap.reg_save_area is doubleword
6693 aligned, but we don't need to allocate space for all
6694 the bytes, only those to which we actually will save
6696 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6697 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6698 if (TARGET_HARD_FLOAT && TARGET_FPRS
6699 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6700 && cfun->va_list_fpr_size)
6703 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6704 * UNITS_PER_FP_WORD;
6705 if (cfun->va_list_fpr_size
6706 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6707 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6709 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6710 * UNITS_PER_FP_WORD;
6714 offset = -((first_reg_offset * reg_size) & ~7);
6715 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6717 gpr_reg_num = cfun->va_list_gpr_size;
6718 if (reg_size == 4 && (first_reg_offset & 1))
6721 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6724 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6726 - (int) (GP_ARG_NUM_REG * reg_size);
6728 if (gpr_size + fpr_size)
6731 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6732 gcc_assert (GET_CODE (reg_save_area) == MEM);
6733 reg_save_area = XEXP (reg_save_area, 0);
6734 if (GET_CODE (reg_save_area) == PLUS)
6736 gcc_assert (XEXP (reg_save_area, 0)
6737 == virtual_stack_vars_rtx);
6738 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6739 offset += INTVAL (XEXP (reg_save_area, 1));
6742 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6745 cfun->machine->varargs_save_offset = offset;
6746 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6751 first_reg_offset = next_cum.words;
6752 save_area = virtual_incoming_args_rtx;
6754 if (targetm.calls.must_pass_in_stack (mode, type))
6755 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6758 set = get_varargs_alias_set ();
6759 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6760 && cfun->va_list_gpr_size)
6762 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6764 if (va_list_gpr_counter_field)
6766 /* V4 va_list_gpr_size counts number of registers needed. */
6767 if (nregs > cfun->va_list_gpr_size)
6768 nregs = cfun->va_list_gpr_size;
6772 /* char * va_list instead counts number of bytes needed. */
6773 if (nregs > cfun->va_list_gpr_size / reg_size)
6774 nregs = cfun->va_list_gpr_size / reg_size;
6777 mem = gen_rtx_MEM (BLKmode,
6778 plus_constant (save_area,
6779 first_reg_offset * reg_size));
6780 MEM_NOTRAP_P (mem) = 1;
6781 set_mem_alias_set (mem, set);
6782 set_mem_align (mem, BITS_PER_WORD);
6784 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6788 /* Save FP registers if needed. */
6789 if (DEFAULT_ABI == ABI_V4
6790 && TARGET_HARD_FLOAT && TARGET_FPRS
6792 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6793 && cfun->va_list_fpr_size)
6795 int fregno = next_cum.fregno, nregs;
6796 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6797 rtx lab = gen_label_rtx ();
6798 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6799 * UNITS_PER_FP_WORD);
6802 (gen_rtx_SET (VOIDmode,
6804 gen_rtx_IF_THEN_ELSE (VOIDmode,
6805 gen_rtx_NE (VOIDmode, cr1,
6807 gen_rtx_LABEL_REF (VOIDmode, lab),
6811 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6812 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6814 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
6816 plus_constant (save_area, off));
6817 MEM_NOTRAP_P (mem) = 1;
6818 set_mem_alias_set (mem, set);
6819 set_mem_align (mem, GET_MODE_ALIGNMENT (
6820 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
6821 ? DFmode : SFmode));
6822 emit_move_insn (mem, gen_rtx_REG (
6823 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
6824 ? DFmode : SFmode, fregno));
6831 /* Create the va_list data type. */
6834 rs6000_build_builtin_va_list (void)
6836 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6838 /* For AIX, prefer 'char *' because that's what the system
6839 header files like. */
6840 if (DEFAULT_ABI != ABI_V4)
6841 return build_pointer_type (char_type_node);
6843 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6844 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6846 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6847 unsigned_char_type_node);
6848 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6849 unsigned_char_type_node);
6850 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6852 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6853 short_unsigned_type_node);
6854 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6856 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6859 va_list_gpr_counter_field = f_gpr;
6860 va_list_fpr_counter_field = f_fpr;
6862 DECL_FIELD_CONTEXT (f_gpr) = record;
6863 DECL_FIELD_CONTEXT (f_fpr) = record;
6864 DECL_FIELD_CONTEXT (f_res) = record;
6865 DECL_FIELD_CONTEXT (f_ovf) = record;
6866 DECL_FIELD_CONTEXT (f_sav) = record;
6868 TREE_CHAIN (record) = type_decl;
6869 TYPE_NAME (record) = type_decl;
6870 TYPE_FIELDS (record) = f_gpr;
6871 TREE_CHAIN (f_gpr) = f_fpr;
6872 TREE_CHAIN (f_fpr) = f_res;
6873 TREE_CHAIN (f_res) = f_ovf;
6874 TREE_CHAIN (f_ovf) = f_sav;
6876 layout_type (record);
6878 /* The correct type is an array type of one element. */
6879 return build_array_type (record, build_index_type (size_zero_node));
6882 /* Implement va_start. */
6885 rs6000_va_start (tree valist, rtx nextarg)
6887 HOST_WIDE_INT words, n_gpr, n_fpr;
6888 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6889 tree gpr, fpr, ovf, sav, t;
6891 /* Only SVR4 needs something special. */
6892 if (DEFAULT_ABI != ABI_V4)
6894 std_expand_builtin_va_start (valist, nextarg);
6898 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6899 f_fpr = TREE_CHAIN (f_gpr);
6900 f_res = TREE_CHAIN (f_fpr);
6901 f_ovf = TREE_CHAIN (f_res);
6902 f_sav = TREE_CHAIN (f_ovf);
6904 valist = build_va_arg_indirect_ref (valist);
6905 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6906 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
6908 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
6910 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
6913 /* Count number of gp and fp argument registers used. */
6914 words = crtl->args.info.words;
6915 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
6917 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
6920 if (TARGET_DEBUG_ARG)
6921 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6922 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6923 words, n_gpr, n_fpr);
6925 if (cfun->va_list_gpr_size)
6927 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
6928 build_int_cst (NULL_TREE, n_gpr));
6929 TREE_SIDE_EFFECTS (t) = 1;
6930 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6933 if (cfun->va_list_fpr_size)
6935 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
6936 build_int_cst (NULL_TREE, n_fpr));
6937 TREE_SIDE_EFFECTS (t) = 1;
6938 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6941 /* Find the overflow area. */
6942 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6944 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6945 size_int (words * UNITS_PER_WORD));
6946 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6947 TREE_SIDE_EFFECTS (t) = 1;
6948 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6950 /* If there were no va_arg invocations, don't set up the register
6952 if (!cfun->va_list_gpr_size
6953 && !cfun->va_list_fpr_size
6954 && n_gpr < GP_ARG_NUM_REG
6955 && n_fpr < FP_ARG_V4_MAX_REG)
6958 /* Find the register save area. */
6959 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6960 if (cfun->machine->varargs_save_offset)
6961 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6962 size_int (cfun->machine->varargs_save_offset));
6963 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
6964 TREE_SIDE_EFFECTS (t) = 1;
6965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6968 /* Implement va_arg. */
6971 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6974 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6975 tree gpr, fpr, ovf, sav, reg, t, u;
6976 int size, rsize, n_reg, sav_ofs, sav_scale;
6977 tree lab_false, lab_over, addr;
6979 tree ptrtype = build_pointer_type (type);
6983 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6985 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6986 return build_va_arg_indirect_ref (t);
6989 if (DEFAULT_ABI != ABI_V4)
6991 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6993 tree elem_type = TREE_TYPE (type);
6994 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6995 int elem_size = GET_MODE_SIZE (elem_mode);
6997 if (elem_size < UNITS_PER_WORD)
6999 tree real_part, imag_part;
7000 gimple_seq post = NULL;
7002 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
7004 /* Copy the value into a temporary, lest the formal temporary
7005 be reused out from under us. */
7006 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
7007 gimple_seq_add_seq (pre_p, post);
7009 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
7012 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
7016 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
7019 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7020 f_fpr = TREE_CHAIN (f_gpr);
7021 f_res = TREE_CHAIN (f_fpr);
7022 f_ovf = TREE_CHAIN (f_res);
7023 f_sav = TREE_CHAIN (f_ovf);
7025 valist = build_va_arg_indirect_ref (valist);
7026 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7027 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
7029 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
7031 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
7034 size = int_size_in_bytes (type);
7035 rsize = (size + 3) / 4;
7038 if (TARGET_HARD_FLOAT && TARGET_FPRS
7039 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
7040 || (TARGET_DOUBLE_FLOAT
7041 && (TYPE_MODE (type) == DFmode
7042 || TYPE_MODE (type) == TFmode
7043 || TYPE_MODE (type) == SDmode
7044 || TYPE_MODE (type) == DDmode
7045 || TYPE_MODE (type) == TDmode))))
7047 /* FP args go in FP registers, if present. */
7049 n_reg = (size + 7) / 8;
7050 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
7051 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
7052 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
7057 /* Otherwise into GP registers. */
7066 /* Pull the value out of the saved registers.... */
7069 addr = create_tmp_var (ptr_type_node, "addr");
7070 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7072 /* AltiVec vectors never go in registers when -mabi=altivec. */
7073 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7077 lab_false = create_artificial_label ();
7078 lab_over = create_artificial_label ();
7080 /* Long long and SPE vectors are aligned in the registers.
7081 As are any other 2 gpr item such as complex int due to a
7082 historical mistake. */
7084 if (n_reg == 2 && reg == gpr)
7087 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
7088 build_int_cst (TREE_TYPE (reg), n_reg - 1));
7089 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
7090 unshare_expr (reg), u);
7092 /* _Decimal128 is passed in even/odd fpr pairs; the stored
7093 reg number is 0 for f1, so we want to make it odd. */
7094 else if (reg == fpr && TYPE_MODE (type) == TDmode)
7096 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
7097 build_int_cst (TREE_TYPE (reg), 1));
7098 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
7101 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
7102 t = build2 (GE_EXPR, boolean_type_node, u, t);
7103 u = build1 (GOTO_EXPR, void_type_node, lab_false);
7104 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7105 gimplify_and_add (t, pre_p);
7109 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
7111 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
7112 build_int_cst (TREE_TYPE (reg), n_reg));
7113 u = fold_convert (sizetype, u);
7114 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
7115 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
7117 /* _Decimal32 varargs are located in the second word of the 64-bit
7118 FP register for 32-bit binaries. */
7119 if (!TARGET_POWERPC64
7120 && TARGET_HARD_FLOAT && TARGET_FPRS
7121 && TYPE_MODE (type) == SDmode)
7122 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
7124 gimplify_assign (addr, t, pre_p);
7126 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7128 stmt = gimple_build_label (lab_false);
7129 gimple_seq_add_stmt (pre_p, stmt);
7131 if ((n_reg == 2 && !regalign) || n_reg > 2)
7133 /* Ensure that we don't find any more args in regs.
7134 Alignment has taken care of for special cases. */
7135 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
7139 /* ... otherwise out of the overflow area. */
7141 /* Care for on-stack alignment if needed. */
7145 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
7146 t = fold_convert (sizetype, t);
7147 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7149 t = fold_convert (TREE_TYPE (ovf), t);
7151 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7153 gimplify_assign (unshare_expr (addr), t, pre_p);
7155 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
7156 gimplify_assign (unshare_expr (ovf), t, pre_p);
7160 stmt = gimple_build_label (lab_over);
7161 gimple_seq_add_stmt (pre_p, stmt);
7164 if (STRICT_ALIGNMENT
7165 && (TYPE_ALIGN (type)
7166 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
7168 /* The value (of type complex double, for example) may not be
7169 aligned in memory in the saved registers, so copy via a
7170 temporary. (This is the same code as used for SPARC.) */
7171 tree tmp = create_tmp_var (type, "va_arg_tmp");
7172 tree dest_addr = build_fold_addr_expr (tmp);
7174 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
7175 3, dest_addr, addr, size_int (rsize * 4));
7177 gimplify_and_add (copy, pre_p);
7181 addr = fold_convert (ptrtype, addr);
7182 return build_va_arg_indirect_ref (addr);
7188 def_builtin (int mask, const char *name, tree type, int code)
7190 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
7192 if (rs6000_builtin_decls[code])
7195 rs6000_builtin_decls[code] =
7196 add_builtin_function (name, type, code, BUILT_IN_MD,
7201 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7203 static const struct builtin_description bdesc_3arg[] =
7205 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
7206 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
7207 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
7208 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
7209 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
7210 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
7211 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
7212 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
7213 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
7214 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
7215 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
7216 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
7217 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
7218 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
7219 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
7220 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
7221 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
7222 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
7223 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
7224 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
7225 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
7226 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
7227 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
7229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
7230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
7231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
7232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
7233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
7234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
7235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
7236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
7237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
7238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
7239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
7240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
7241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
7242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
7243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
7245 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
7246 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
7247 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
7248 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
7249 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
7250 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
7251 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
7252 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
7253 { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
7256 /* DST operations: void foo (void *, const int, const char). */
7258 static const struct builtin_description bdesc_dst[] =
7260 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
7261 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
7262 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
7263 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
7265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
7266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
7267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
7268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
7271 /* Simple binary operations: VECc = foo (VECa, VECb). */
7273 static struct builtin_description bdesc_2arg[] =
7275 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
7276 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
7277 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
7278 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
7279 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
7280 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
7281 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
7282 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
7283 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
7284 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
7285 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
7286 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
7287 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
7288 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
7289 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
7290 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
7291 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
7292 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
7293 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
7294 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
7295 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
7296 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
7297 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
7298 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
7299 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
7300 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
7301 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
7302 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
7303 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
7304 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
7305 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
7306 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
7307 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
7308 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
7309 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
7310 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
7311 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
7312 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
7313 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
7314 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
7315 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
7316 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
7317 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
7318 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
7319 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
7320 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
7321 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
7322 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
7323 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
7324 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
7325 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
7326 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
7327 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
7328 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
7329 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
7330 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
7331 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
7332 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
7333 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
7334 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
7335 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
7336 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
7337 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
7338 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
7339 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
7340 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
7341 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
7342 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
7343 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
7344 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
7345 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
7346 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
7347 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
7348 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
7349 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
7350 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
7351 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
7352 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
7353 { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
7354 { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
7355 { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
7356 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
7357 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
7358 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
7359 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
7360 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
7361 { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
7362 { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
7363 { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
7364 { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
7365 { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
7366 { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
7367 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
7368 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
7369 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
7370 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
7371 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
7372 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
7373 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
7374 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
7375 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
7376 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
7377 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
7378 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
7379 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
7380 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
7381 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
7382 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
7383 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
7384 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
7385 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
7387 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
7388 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
7389 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
7390 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
7391 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
7392 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
7393 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
7394 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
7395 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
7396 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
7397 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
7398 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
7399 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
7400 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
7401 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
7402 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
7403 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
7404 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
7405 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
7406 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
7407 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
7408 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
7409 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
7410 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
7411 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
7412 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
7413 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
7414 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
7415 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
7416 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
7417 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
7418 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
7419 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
7420 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
7421 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
7422 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
7423 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
7424 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
7425 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
7426 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
7427 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
7428 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
7429 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
7430 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
7431 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
7432 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
7433 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
7434 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
7435 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
7436 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
7437 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
7438 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
7439 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
7440 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
7441 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
7442 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
7443 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
7444 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
7445 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
7446 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
7447 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
7448 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
7449 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
7450 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
7451 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
7452 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
7453 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
7454 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
7455 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
7456 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
7457 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
7458 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
7459 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
7460 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
7461 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
7462 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
7463 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
7464 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
7465 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
7466 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
7467 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
7468 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
7469 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
7470 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
7471 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
7472 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
7473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
7474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
7475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
7476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
7477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
7478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
7479 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
7480 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
7481 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
7482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
7483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
7484 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
7485 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
7486 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
7487 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
7488 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
7489 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
7490 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
7491 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
7492 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
7493 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
7494 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
7495 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
7496 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
7497 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
7498 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
7499 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
7500 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
7501 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
7502 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
7503 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
7504 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
7505 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
7506 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
7507 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
7508 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
7509 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
7510 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
7511 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
7512 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
7513 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
7515 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
7516 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
7517 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
7518 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
7519 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
7520 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
7521 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
7522 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
7523 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
7524 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
7526 /* Place holder, leave as first spe builtin. */
7527 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
7528 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
7529 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
7530 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
7531 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
7532 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
7533 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
7534 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
7535 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
7536 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
7537 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
7538 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
7539 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
7540 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
7541 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
7542 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
7543 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
7544 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
7545 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
7546 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
7547 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
7548 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
7549 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
7550 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
7551 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
7552 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
7553 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
7554 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
7555 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
7556 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
7557 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
7558 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
7559 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
7560 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
7561 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
7562 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
7563 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
7564 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
7565 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
7566 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
7567 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
7568 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
7569 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
7570 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
7571 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
7572 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
7573 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
7574 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
7575 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
7576 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
7577 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
7578 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
7579 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
7580 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
7581 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
7582 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
7583 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
7584 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
7585 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7586 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7587 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7588 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7589 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7590 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7591 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7592 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7593 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7594 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7595 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7596 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7597 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7598 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7599 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7600 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7601 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7602 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7603 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7604 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7605 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7606 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7607 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7608 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7609 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7610 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7611 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7612 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7613 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7614 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7615 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7616 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7617 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7618 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7619 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7620 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7621 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7622 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7623 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7624 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7625 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7626 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7627 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7628 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7629 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7630 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7631 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7632 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7633 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7634 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7635 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7637 /* SPE binary operations expecting a 5-bit unsigned literal. */
7638 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7640 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7641 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7642 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7643 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7644 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7645 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7646 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7647 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7648 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7649 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7650 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7651 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7652 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7653 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7654 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7655 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7656 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7657 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7658 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7659 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7660 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7661 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7662 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7663 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7664 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7665 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7667 /* Place-holder. Leave as last binary SPE builtin. */
7668 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7671 /* AltiVec predicates. */
7673 struct builtin_description_predicates
7675 const unsigned int mask;
7676 const enum insn_code icode;
7678 const char *const name;
7679 const enum rs6000_builtins code;
7682 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7684 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7685 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7686 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7687 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7688 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7689 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7690 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7691 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7692 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7693 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7694 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7695 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7696 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7698 { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7699 { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7700 { MASK_ALTIVEC, CODE_FOR_nothing, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7703 /* SPE predicates. */
7704 static struct builtin_description bdesc_spe_predicates[] =
7706 /* Place-holder. Leave as first. */
7707 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7708 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7709 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7710 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7711 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7712 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7713 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7714 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7715 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7716 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7717 /* Place-holder. Leave as last. */
7718 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7721 /* SPE evsel predicates. */
7722 static struct builtin_description bdesc_spe_evsel[] =
7724 /* Place-holder. Leave as first. */
7725 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7726 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7727 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7728 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7729 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7730 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7731 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7732 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7733 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7734 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7735 /* Place-holder. Leave as last. */
7736 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7739 /* PAIRED predicates. */
7740 static const struct builtin_description bdesc_paired_preds[] =
7742 /* Place-holder. Leave as first. */
7743 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7744 /* Place-holder. Leave as last. */
7745 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7748 /* ABS* operations. */
7750 static const struct builtin_description bdesc_abs[] =
7752 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7753 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7754 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7755 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7756 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7757 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7758 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7761 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7764 static struct builtin_description bdesc_1arg[] =
7766 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7767 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7768 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7769 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7770 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7771 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7772 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7773 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7774 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7775 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7776 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7777 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7778 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7779 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7780 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7781 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7782 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7804 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7805 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7806 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7807 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7808 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7809 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7810 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7811 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7812 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7813 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7814 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7815 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7816 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7817 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7818 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7819 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7820 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7821 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7822 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7823 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7824 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7825 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7826 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7827 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7828 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7829 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7830 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7831 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7832 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7833 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7835 /* Place-holder. Leave as last unary SPE builtin. */
7836 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7838 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7839 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7840 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7841 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7842 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7846 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7849 tree arg0 = CALL_EXPR_ARG (exp, 0);
7850 rtx op0 = expand_normal (arg0);
7851 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7852 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7854 if (icode == CODE_FOR_nothing)
7855 /* Builtin not supported on this processor. */
7858 /* If we got invalid arguments bail out before generating bad rtl. */
7859 if (arg0 == error_mark_node)
7862 if (icode == CODE_FOR_altivec_vspltisb
7863 || icode == CODE_FOR_altivec_vspltish
7864 || icode == CODE_FOR_altivec_vspltisw
7865 || icode == CODE_FOR_spe_evsplatfi
7866 || icode == CODE_FOR_spe_evsplati)
7868 /* Only allow 5-bit *signed* literals. */
7869 if (GET_CODE (op0) != CONST_INT
7870 || INTVAL (op0) > 15
7871 || INTVAL (op0) < -16)
7873 error ("argument 1 must be a 5-bit signed literal");
7879 || GET_MODE (target) != tmode
7880 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7881 target = gen_reg_rtx (tmode);
7883 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7884 op0 = copy_to_mode_reg (mode0, op0);
7886 pat = GEN_FCN (icode) (target, op0);
7895 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7897 rtx pat, scratch1, scratch2;
7898 tree arg0 = CALL_EXPR_ARG (exp, 0);
7899 rtx op0 = expand_normal (arg0);
7900 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7901 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7903 /* If we have invalid arguments, bail out before generating bad rtl. */
7904 if (arg0 == error_mark_node)
7908 || GET_MODE (target) != tmode
7909 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7910 target = gen_reg_rtx (tmode);
7912 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7913 op0 = copy_to_mode_reg (mode0, op0);
7915 scratch1 = gen_reg_rtx (mode0);
7916 scratch2 = gen_reg_rtx (mode0);
7918 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7927 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7930 tree arg0 = CALL_EXPR_ARG (exp, 0);
7931 tree arg1 = CALL_EXPR_ARG (exp, 1);
7932 rtx op0 = expand_normal (arg0);
7933 rtx op1 = expand_normal (arg1);
7934 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7935 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7936 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7938 if (icode == CODE_FOR_nothing)
7939 /* Builtin not supported on this processor. */
7942 /* If we got invalid arguments bail out before generating bad rtl. */
7943 if (arg0 == error_mark_node || arg1 == error_mark_node)
7946 if (icode == CODE_FOR_altivec_vcfux
7947 || icode == CODE_FOR_altivec_vcfsx
7948 || icode == CODE_FOR_altivec_vctsxs
7949 || icode == CODE_FOR_altivec_vctuxs
7950 || icode == CODE_FOR_altivec_vspltb
7951 || icode == CODE_FOR_altivec_vsplth
7952 || icode == CODE_FOR_altivec_vspltw
7953 || icode == CODE_FOR_spe_evaddiw
7954 || icode == CODE_FOR_spe_evldd
7955 || icode == CODE_FOR_spe_evldh
7956 || icode == CODE_FOR_spe_evldw
7957 || icode == CODE_FOR_spe_evlhhesplat
7958 || icode == CODE_FOR_spe_evlhhossplat
7959 || icode == CODE_FOR_spe_evlhhousplat
7960 || icode == CODE_FOR_spe_evlwhe
7961 || icode == CODE_FOR_spe_evlwhos
7962 || icode == CODE_FOR_spe_evlwhou
7963 || icode == CODE_FOR_spe_evlwhsplat
7964 || icode == CODE_FOR_spe_evlwwsplat
7965 || icode == CODE_FOR_spe_evrlwi
7966 || icode == CODE_FOR_spe_evslwi
7967 || icode == CODE_FOR_spe_evsrwis
7968 || icode == CODE_FOR_spe_evsubifw
7969 || icode == CODE_FOR_spe_evsrwiu)
7971 /* Only allow 5-bit unsigned literals. */
7973 if (TREE_CODE (arg1) != INTEGER_CST
7974 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7976 error ("argument 2 must be a 5-bit unsigned literal");
7982 || GET_MODE (target) != tmode
7983 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7984 target = gen_reg_rtx (tmode);
7986 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7987 op0 = copy_to_mode_reg (mode0, op0);
7988 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7989 op1 = copy_to_mode_reg (mode1, op1);
7991 pat = GEN_FCN (icode) (target, op0, op1);
8000 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
8001 tree exp, rtx target)
8004 tree cr6_form = CALL_EXPR_ARG (exp, 0);
8005 tree arg0 = CALL_EXPR_ARG (exp, 1);
8006 tree arg1 = CALL_EXPR_ARG (exp, 2);
8007 rtx op0 = expand_normal (arg0);
8008 rtx op1 = expand_normal (arg1);
8009 enum machine_mode tmode = SImode;
8010 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8011 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8014 if (TREE_CODE (cr6_form) != INTEGER_CST)
8016 error ("argument 1 of __builtin_altivec_predicate must be a constant");
8020 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
8022 gcc_assert (mode0 == mode1);
8024 /* If we have invalid arguments, bail out before generating bad rtl. */
8025 if (arg0 == error_mark_node || arg1 == error_mark_node)
8029 || GET_MODE (target) != tmode
8030 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8031 target = gen_reg_rtx (tmode);
8033 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8034 op0 = copy_to_mode_reg (mode0, op0);
8035 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8036 op1 = copy_to_mode_reg (mode1, op1);
8038 scratch = gen_reg_rtx (mode0);
8040 pat = GEN_FCN (icode) (scratch, op0, op1,
8041 gen_rtx_SYMBOL_REF (Pmode, opcode));
8046 /* The vec_any* and vec_all* predicates use the same opcodes for two
8047 different operations, but the bits in CR6 will be different
8048 depending on what information we want. So we have to play tricks
8049 with CR6 to get the right bits out.
8051 If you think this is disgusting, look at the specs for the
8052 AltiVec predicates. */
8054 switch (cr6_form_int)
8057 emit_insn (gen_cr6_test_for_zero (target));
8060 emit_insn (gen_cr6_test_for_zero_reverse (target));
8063 emit_insn (gen_cr6_test_for_lt (target));
8066 emit_insn (gen_cr6_test_for_lt_reverse (target));
8069 error ("argument 1 of __builtin_altivec_predicate is out of range");
8077 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
8080 tree arg0 = CALL_EXPR_ARG (exp, 0);
8081 tree arg1 = CALL_EXPR_ARG (exp, 1);
8082 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8083 enum machine_mode mode0 = Pmode;
8084 enum machine_mode mode1 = Pmode;
8085 rtx op0 = expand_normal (arg0);
8086 rtx op1 = expand_normal (arg1);
8088 if (icode == CODE_FOR_nothing)
8089 /* Builtin not supported on this processor. */
8092 /* If we got invalid arguments bail out before generating bad rtl. */
8093 if (arg0 == error_mark_node || arg1 == error_mark_node)
8097 || GET_MODE (target) != tmode
8098 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8099 target = gen_reg_rtx (tmode);
8101 op1 = copy_to_mode_reg (mode1, op1);
8103 if (op0 == const0_rtx)
8105 addr = gen_rtx_MEM (tmode, op1);
8109 op0 = copy_to_mode_reg (mode0, op0);
8110 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
8113 pat = GEN_FCN (icode) (target, addr);
8123 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
8126 tree arg0 = CALL_EXPR_ARG (exp, 0);
8127 tree arg1 = CALL_EXPR_ARG (exp, 1);
8128 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8129 enum machine_mode mode0 = Pmode;
8130 enum machine_mode mode1 = Pmode;
8131 rtx op0 = expand_normal (arg0);
8132 rtx op1 = expand_normal (arg1);
8134 if (icode == CODE_FOR_nothing)
8135 /* Builtin not supported on this processor. */
8138 /* If we got invalid arguments bail out before generating bad rtl. */
8139 if (arg0 == error_mark_node || arg1 == error_mark_node)
8143 || GET_MODE (target) != tmode
8144 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8145 target = gen_reg_rtx (tmode);
8147 op1 = copy_to_mode_reg (mode1, op1);
8149 if (op0 == const0_rtx)
8151 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
8155 op0 = copy_to_mode_reg (mode0, op0);
8156 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
8159 pat = GEN_FCN (icode) (target, addr);
8169 spe_expand_stv_builtin (enum insn_code icode, tree exp)
8171 tree arg0 = CALL_EXPR_ARG (exp, 0);
8172 tree arg1 = CALL_EXPR_ARG (exp, 1);
8173 tree arg2 = CALL_EXPR_ARG (exp, 2);
8174 rtx op0 = expand_normal (arg0);
8175 rtx op1 = expand_normal (arg1);
8176 rtx op2 = expand_normal (arg2);
8178 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8179 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
8180 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
8182 /* Invalid arguments. Bail before doing anything stoopid! */
8183 if (arg0 == error_mark_node
8184 || arg1 == error_mark_node
8185 || arg2 == error_mark_node)
8188 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
8189 op0 = copy_to_mode_reg (mode2, op0);
8190 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
8191 op1 = copy_to_mode_reg (mode0, op1);
8192 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8193 op2 = copy_to_mode_reg (mode1, op2);
8195 pat = GEN_FCN (icode) (op1, op2, op0);
8202 paired_expand_stv_builtin (enum insn_code icode, tree exp)
8204 tree arg0 = CALL_EXPR_ARG (exp, 0);
8205 tree arg1 = CALL_EXPR_ARG (exp, 1);
8206 tree arg2 = CALL_EXPR_ARG (exp, 2);
8207 rtx op0 = expand_normal (arg0);
8208 rtx op1 = expand_normal (arg1);
8209 rtx op2 = expand_normal (arg2);
8211 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8212 enum machine_mode mode1 = Pmode;
8213 enum machine_mode mode2 = Pmode;
8215 /* Invalid arguments. Bail before doing anything stoopid! */
8216 if (arg0 == error_mark_node
8217 || arg1 == error_mark_node
8218 || arg2 == error_mark_node)
8221 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8222 op0 = copy_to_mode_reg (tmode, op0);
8224 op2 = copy_to_mode_reg (mode2, op2);
8226 if (op1 == const0_rtx)
8228 addr = gen_rtx_MEM (tmode, op2);
8232 op1 = copy_to_mode_reg (mode1, op1);
8233 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8236 pat = GEN_FCN (icode) (addr, op0);
8243 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
8245 tree arg0 = CALL_EXPR_ARG (exp, 0);
8246 tree arg1 = CALL_EXPR_ARG (exp, 1);
8247 tree arg2 = CALL_EXPR_ARG (exp, 2);
8248 rtx op0 = expand_normal (arg0);
8249 rtx op1 = expand_normal (arg1);
8250 rtx op2 = expand_normal (arg2);
8252 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8253 enum machine_mode mode1 = Pmode;
8254 enum machine_mode mode2 = Pmode;
8256 /* Invalid arguments. Bail before doing anything stoopid! */
8257 if (arg0 == error_mark_node
8258 || arg1 == error_mark_node
8259 || arg2 == error_mark_node)
8262 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
8263 op0 = copy_to_mode_reg (tmode, op0);
8265 op2 = copy_to_mode_reg (mode2, op2);
8267 if (op1 == const0_rtx)
8269 addr = gen_rtx_MEM (tmode, op2);
8273 op1 = copy_to_mode_reg (mode1, op1);
8274 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
8277 pat = GEN_FCN (icode) (addr, op0);
8284 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
8287 tree arg0 = CALL_EXPR_ARG (exp, 0);
8288 tree arg1 = CALL_EXPR_ARG (exp, 1);
8289 tree arg2 = CALL_EXPR_ARG (exp, 2);
8290 rtx op0 = expand_normal (arg0);
8291 rtx op1 = expand_normal (arg1);
8292 rtx op2 = expand_normal (arg2);
8293 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8294 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8295 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8296 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
8298 if (icode == CODE_FOR_nothing)
8299 /* Builtin not supported on this processor. */
8302 /* If we got invalid arguments bail out before generating bad rtl. */
8303 if (arg0 == error_mark_node
8304 || arg1 == error_mark_node
8305 || arg2 == error_mark_node)
8308 if (icode == CODE_FOR_altivec_vsldoi_v4sf
8309 || icode == CODE_FOR_altivec_vsldoi_v4si
8310 || icode == CODE_FOR_altivec_vsldoi_v8hi
8311 || icode == CODE_FOR_altivec_vsldoi_v16qi)
8313 /* Only allow 4-bit unsigned literals. */
8315 if (TREE_CODE (arg2) != INTEGER_CST
8316 || TREE_INT_CST_LOW (arg2) & ~0xf)
8318 error ("argument 3 must be a 4-bit unsigned literal");
8324 || GET_MODE (target) != tmode
8325 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8326 target = gen_reg_rtx (tmode);
8328 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8329 op0 = copy_to_mode_reg (mode0, op0);
8330 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8331 op1 = copy_to_mode_reg (mode1, op1);
8332 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
8333 op2 = copy_to_mode_reg (mode2, op2);
8335 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
8336 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
8338 pat = GEN_FCN (icode) (target, op0, op1, op2);
8346 /* Expand the lvx builtins. */
8348 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
8350 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8351 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8353 enum machine_mode tmode, mode0;
8355 enum insn_code icode;
8359 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
8360 icode = CODE_FOR_altivec_lvx_v16qi;
8362 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
8363 icode = CODE_FOR_altivec_lvx_v8hi;
8365 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
8366 icode = CODE_FOR_altivec_lvx_v4si;
8368 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
8369 icode = CODE_FOR_altivec_lvx_v4sf;
8378 arg0 = CALL_EXPR_ARG (exp, 0);
8379 op0 = expand_normal (arg0);
8380 tmode = insn_data[icode].operand[0].mode;
8381 mode0 = insn_data[icode].operand[1].mode;
8384 || GET_MODE (target) != tmode
8385 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8386 target = gen_reg_rtx (tmode);
8388 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8389 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8391 pat = GEN_FCN (icode) (target, op0);
8398 /* Expand the stvx builtins. */
8400 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8403 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8404 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8406 enum machine_mode mode0, mode1;
8408 enum insn_code icode;
8412 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
8413 icode = CODE_FOR_altivec_stvx_v16qi;
8415 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
8416 icode = CODE_FOR_altivec_stvx_v8hi;
8418 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
8419 icode = CODE_FOR_altivec_stvx_v4si;
8421 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
8422 icode = CODE_FOR_altivec_stvx_v4sf;
8429 arg0 = CALL_EXPR_ARG (exp, 0);
8430 arg1 = CALL_EXPR_ARG (exp, 1);
8431 op0 = expand_normal (arg0);
8432 op1 = expand_normal (arg1);
8433 mode0 = insn_data[icode].operand[0].mode;
8434 mode1 = insn_data[icode].operand[1].mode;
8436 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8437 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
8438 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8439 op1 = copy_to_mode_reg (mode1, op1);
8441 pat = GEN_FCN (icode) (op0, op1);
8449 /* Expand the dst builtins. */
8451 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
8454 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8455 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8456 tree arg0, arg1, arg2;
8457 enum machine_mode mode0, mode1, mode2;
8458 rtx pat, op0, op1, op2;
8459 const struct builtin_description *d;
8464 /* Handle DST variants. */
8466 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8467 if (d->code == fcode)
8469 arg0 = CALL_EXPR_ARG (exp, 0);
8470 arg1 = CALL_EXPR_ARG (exp, 1);
8471 arg2 = CALL_EXPR_ARG (exp, 2);
8472 op0 = expand_normal (arg0);
8473 op1 = expand_normal (arg1);
8474 op2 = expand_normal (arg2);
8475 mode0 = insn_data[d->icode].operand[0].mode;
8476 mode1 = insn_data[d->icode].operand[1].mode;
8477 mode2 = insn_data[d->icode].operand[2].mode;
8479 /* Invalid arguments, bail out before generating bad rtl. */
8480 if (arg0 == error_mark_node
8481 || arg1 == error_mark_node
8482 || arg2 == error_mark_node)
8487 if (TREE_CODE (arg2) != INTEGER_CST
8488 || TREE_INT_CST_LOW (arg2) & ~0x3)
8490 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
8494 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
8495 op0 = copy_to_mode_reg (Pmode, op0);
8496 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
8497 op1 = copy_to_mode_reg (mode1, op1);
8499 pat = GEN_FCN (d->icode) (op0, op1, op2);
8509 /* Expand vec_init builtin. */
8511 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
8513 enum machine_mode tmode = TYPE_MODE (type);
8514 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
8515 int i, n_elt = GET_MODE_NUNITS (tmode);
8516 rtvec v = rtvec_alloc (n_elt);
8518 gcc_assert (VECTOR_MODE_P (tmode));
8519 gcc_assert (n_elt == call_expr_nargs (exp));
8521 for (i = 0; i < n_elt; ++i)
8523 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
8524 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
8527 if (!target || !register_operand (target, tmode))
8528 target = gen_reg_rtx (tmode);
8530 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
8534 /* Return the integer constant in ARG. Constrain it to be in the range
8535 of the subparts of VEC_TYPE; issue an error if not. */
8538 get_element_number (tree vec_type, tree arg)
8540 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
8542 if (!host_integerp (arg, 1)
8543 || (elt = tree_low_cst (arg, 1), elt > max))
8545 error ("selector must be an integer constant in the range 0..%wi", max);
8552 /* Expand vec_set builtin. */
8554 altivec_expand_vec_set_builtin (tree exp)
8556 enum machine_mode tmode, mode1;
8557 tree arg0, arg1, arg2;
8561 arg0 = CALL_EXPR_ARG (exp, 0);
8562 arg1 = CALL_EXPR_ARG (exp, 1);
8563 arg2 = CALL_EXPR_ARG (exp, 2);
8565 tmode = TYPE_MODE (TREE_TYPE (arg0));
8566 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8567 gcc_assert (VECTOR_MODE_P (tmode));
8569 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
8570 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
8571 elt = get_element_number (TREE_TYPE (arg0), arg2);
8573 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
8574 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
8576 op0 = force_reg (tmode, op0);
8577 op1 = force_reg (mode1, op1);
8579 rs6000_expand_vector_set (op0, op1, elt);
8584 /* Expand vec_ext builtin. */
8586 altivec_expand_vec_ext_builtin (tree exp, rtx target)
8588 enum machine_mode tmode, mode0;
8593 arg0 = CALL_EXPR_ARG (exp, 0);
8594 arg1 = CALL_EXPR_ARG (exp, 1);
8596 op0 = expand_normal (arg0);
8597 elt = get_element_number (TREE_TYPE (arg0), arg1);
8599 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8600 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8601 gcc_assert (VECTOR_MODE_P (mode0));
8603 op0 = force_reg (mode0, op0);
8605 if (optimize || !target || !register_operand (target, tmode))
8606 target = gen_reg_rtx (tmode);
8608 rs6000_expand_vector_extract (target, op0, elt);
8613 /* Expand the builtin in EXP and store the result in TARGET. Store
8614 true in *EXPANDEDP if we found a builtin to expand. */
8616 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8618 const struct builtin_description *d;
8619 const struct builtin_description_predicates *dp;
8621 enum insn_code icode;
8622 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8625 enum machine_mode tmode, mode0;
8626 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8628 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8629 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8632 error ("unresolved overload for Altivec builtin %qF", fndecl);
8636 target = altivec_expand_ld_builtin (exp, target, expandedp);
8640 target = altivec_expand_st_builtin (exp, target, expandedp);
8644 target = altivec_expand_dst_builtin (exp, target, expandedp);
8652 case ALTIVEC_BUILTIN_STVX:
8653 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8654 case ALTIVEC_BUILTIN_STVEBX:
8655 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8656 case ALTIVEC_BUILTIN_STVEHX:
8657 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8658 case ALTIVEC_BUILTIN_STVEWX:
8659 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8660 case ALTIVEC_BUILTIN_STVXL:
8661 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8663 case ALTIVEC_BUILTIN_STVLX:
8664 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
8665 case ALTIVEC_BUILTIN_STVLXL:
8666 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
8667 case ALTIVEC_BUILTIN_STVRX:
8668 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
8669 case ALTIVEC_BUILTIN_STVRXL:
8670 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
8672 case ALTIVEC_BUILTIN_MFVSCR:
8673 icode = CODE_FOR_altivec_mfvscr;
8674 tmode = insn_data[icode].operand[0].mode;
8677 || GET_MODE (target) != tmode
8678 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8679 target = gen_reg_rtx (tmode);
8681 pat = GEN_FCN (icode) (target);
8687 case ALTIVEC_BUILTIN_MTVSCR:
8688 icode = CODE_FOR_altivec_mtvscr;
8689 arg0 = CALL_EXPR_ARG (exp, 0);
8690 op0 = expand_normal (arg0);
8691 mode0 = insn_data[icode].operand[0].mode;
8693 /* If we got invalid arguments bail out before generating bad rtl. */
8694 if (arg0 == error_mark_node)
8697 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8698 op0 = copy_to_mode_reg (mode0, op0);
8700 pat = GEN_FCN (icode) (op0);
8705 case ALTIVEC_BUILTIN_DSSALL:
8706 emit_insn (gen_altivec_dssall ());
8709 case ALTIVEC_BUILTIN_DSS:
8710 icode = CODE_FOR_altivec_dss;
8711 arg0 = CALL_EXPR_ARG (exp, 0);
8713 op0 = expand_normal (arg0);
8714 mode0 = insn_data[icode].operand[0].mode;
8716 /* If we got invalid arguments bail out before generating bad rtl. */
8717 if (arg0 == error_mark_node)
8720 if (TREE_CODE (arg0) != INTEGER_CST
8721 || TREE_INT_CST_LOW (arg0) & ~0x3)
8723 error ("argument to dss must be a 2-bit unsigned literal");
8727 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8728 op0 = copy_to_mode_reg (mode0, op0);
8730 emit_insn (gen_altivec_dss (op0));
8733 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8734 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8735 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8736 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8737 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8739 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8740 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8741 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8742 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8743 return altivec_expand_vec_set_builtin (exp);
8745 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8746 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8747 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8748 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8749 return altivec_expand_vec_ext_builtin (exp, target);
8756 /* Expand abs* operations. */
8758 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8759 if (d->code == fcode)
8760 return altivec_expand_abs_builtin (d->icode, exp, target);
8762 /* Expand the AltiVec predicates. */
8763 dp = bdesc_altivec_preds;
8764 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8765 if (dp->code == fcode)
8766 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8769 /* LV* are funky. We initialized them differently. */
8772 case ALTIVEC_BUILTIN_LVSL:
8773 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8774 exp, target, false);
8775 case ALTIVEC_BUILTIN_LVSR:
8776 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8777 exp, target, false);
8778 case ALTIVEC_BUILTIN_LVEBX:
8779 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8780 exp, target, false);
8781 case ALTIVEC_BUILTIN_LVEHX:
8782 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8783 exp, target, false);
8784 case ALTIVEC_BUILTIN_LVEWX:
8785 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8786 exp, target, false);
8787 case ALTIVEC_BUILTIN_LVXL:
8788 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8789 exp, target, false);
8790 case ALTIVEC_BUILTIN_LVX:
8791 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8792 exp, target, false);
8793 case ALTIVEC_BUILTIN_LVLX:
8794 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
8796 case ALTIVEC_BUILTIN_LVLXL:
8797 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
8799 case ALTIVEC_BUILTIN_LVRX:
8800 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
8802 case ALTIVEC_BUILTIN_LVRXL:
8803 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
8814 /* Expand the builtin in EXP and store the result in TARGET. Store
8815 true in *EXPANDEDP if we found a builtin to expand. */
8817 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8819 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8820 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8821 const struct builtin_description *d;
8828 case PAIRED_BUILTIN_STX:
8829 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8830 case PAIRED_BUILTIN_LX:
8831 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8837 /* Expand the paired predicates. */
8838 d = bdesc_paired_preds;
8839 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8840 if (d->code == fcode)
8841 return paired_expand_predicate_builtin (d->icode, exp, target);
8847 /* Binops that need to be initialized manually, but can be expanded
8848 automagically by rs6000_expand_binop_builtin. */
8849 static struct builtin_description bdesc_2arg_spe[] =
8851 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8852 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8853 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8854 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8855 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8856 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8857 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8858 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8859 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8860 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8861 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8862 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8863 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8864 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8865 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8866 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8867 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8868 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8869 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8870 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8871 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8872 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8875 /* Expand the builtin in EXP and store the result in TARGET. Store
8876 true in *EXPANDEDP if we found a builtin to expand.
8878 This expands the SPE builtins that are not simple unary and binary
8881 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8883 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8885 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8886 enum insn_code icode;
8887 enum machine_mode tmode, mode0;
8889 struct builtin_description *d;
8894 /* Syntax check for a 5-bit unsigned immediate. */
8897 case SPE_BUILTIN_EVSTDD:
8898 case SPE_BUILTIN_EVSTDH:
8899 case SPE_BUILTIN_EVSTDW:
8900 case SPE_BUILTIN_EVSTWHE:
8901 case SPE_BUILTIN_EVSTWHO:
8902 case SPE_BUILTIN_EVSTWWE:
8903 case SPE_BUILTIN_EVSTWWO:
8904 arg1 = CALL_EXPR_ARG (exp, 2);
8905 if (TREE_CODE (arg1) != INTEGER_CST
8906 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8908 error ("argument 2 must be a 5-bit unsigned literal");
8916 /* The evsplat*i instructions are not quite generic. */
8919 case SPE_BUILTIN_EVSPLATFI:
8920 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8922 case SPE_BUILTIN_EVSPLATI:
8923 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8929 d = (struct builtin_description *) bdesc_2arg_spe;
8930 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8931 if (d->code == fcode)
8932 return rs6000_expand_binop_builtin (d->icode, exp, target);
8934 d = (struct builtin_description *) bdesc_spe_predicates;
8935 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8936 if (d->code == fcode)
8937 return spe_expand_predicate_builtin (d->icode, exp, target);
8939 d = (struct builtin_description *) bdesc_spe_evsel;
8940 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8941 if (d->code == fcode)
8942 return spe_expand_evsel_builtin (d->icode, exp, target);
8946 case SPE_BUILTIN_EVSTDDX:
8947 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8948 case SPE_BUILTIN_EVSTDHX:
8949 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8950 case SPE_BUILTIN_EVSTDWX:
8951 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8952 case SPE_BUILTIN_EVSTWHEX:
8953 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8954 case SPE_BUILTIN_EVSTWHOX:
8955 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8956 case SPE_BUILTIN_EVSTWWEX:
8957 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8958 case SPE_BUILTIN_EVSTWWOX:
8959 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8960 case SPE_BUILTIN_EVSTDD:
8961 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8962 case SPE_BUILTIN_EVSTDH:
8963 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8964 case SPE_BUILTIN_EVSTDW:
8965 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8966 case SPE_BUILTIN_EVSTWHE:
8967 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8968 case SPE_BUILTIN_EVSTWHO:
8969 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8970 case SPE_BUILTIN_EVSTWWE:
8971 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8972 case SPE_BUILTIN_EVSTWWO:
8973 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8974 case SPE_BUILTIN_MFSPEFSCR:
8975 icode = CODE_FOR_spe_mfspefscr;
8976 tmode = insn_data[icode].operand[0].mode;
8979 || GET_MODE (target) != tmode
8980 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8981 target = gen_reg_rtx (tmode);
8983 pat = GEN_FCN (icode) (target);
8988 case SPE_BUILTIN_MTSPEFSCR:
8989 icode = CODE_FOR_spe_mtspefscr;
8990 arg0 = CALL_EXPR_ARG (exp, 0);
8991 op0 = expand_normal (arg0);
8992 mode0 = insn_data[icode].operand[0].mode;
8994 if (arg0 == error_mark_node)
8997 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8998 op0 = copy_to_mode_reg (mode0, op0);
9000 pat = GEN_FCN (icode) (op0);
9013 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9015 rtx pat, scratch, tmp;
9016 tree form = CALL_EXPR_ARG (exp, 0);
9017 tree arg0 = CALL_EXPR_ARG (exp, 1);
9018 tree arg1 = CALL_EXPR_ARG (exp, 2);
9019 rtx op0 = expand_normal (arg0);
9020 rtx op1 = expand_normal (arg1);
9021 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9022 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9026 if (TREE_CODE (form) != INTEGER_CST)
9028 error ("argument 1 of __builtin_paired_predicate must be a constant");
9032 form_int = TREE_INT_CST_LOW (form);
9034 gcc_assert (mode0 == mode1);
9036 if (arg0 == error_mark_node || arg1 == error_mark_node)
9040 || GET_MODE (target) != SImode
9041 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
9042 target = gen_reg_rtx (SImode);
9043 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
9044 op0 = copy_to_mode_reg (mode0, op0);
9045 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
9046 op1 = copy_to_mode_reg (mode1, op1);
9048 scratch = gen_reg_rtx (CCFPmode);
9050 pat = GEN_FCN (icode) (scratch, op0, op1);
9072 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
9075 error ("argument 1 of __builtin_paired_predicate is out of range");
9079 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
9080 emit_move_insn (target, tmp);
9085 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9087 rtx pat, scratch, tmp;
9088 tree form = CALL_EXPR_ARG (exp, 0);
9089 tree arg0 = CALL_EXPR_ARG (exp, 1);
9090 tree arg1 = CALL_EXPR_ARG (exp, 2);
9091 rtx op0 = expand_normal (arg0);
9092 rtx op1 = expand_normal (arg1);
9093 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9094 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9098 if (TREE_CODE (form) != INTEGER_CST)
9100 error ("argument 1 of __builtin_spe_predicate must be a constant");
9104 form_int = TREE_INT_CST_LOW (form);
9106 gcc_assert (mode0 == mode1);
9108 if (arg0 == error_mark_node || arg1 == error_mark_node)
9112 || GET_MODE (target) != SImode
9113 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
9114 target = gen_reg_rtx (SImode);
9116 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9117 op0 = copy_to_mode_reg (mode0, op0);
9118 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9119 op1 = copy_to_mode_reg (mode1, op1);
9121 scratch = gen_reg_rtx (CCmode);
9123 pat = GEN_FCN (icode) (scratch, op0, op1);
9128 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
9129 _lower_. We use one compare, but look in different bits of the
9130 CR for each variant.
9132 There are 2 elements in each SPE simd type (upper/lower). The CR
9133 bits are set as follows:
9135 BIT0 | BIT 1 | BIT 2 | BIT 3
9136 U | L | (U | L) | (U & L)
9138 So, for an "all" relationship, BIT 3 would be set.
9139 For an "any" relationship, BIT 2 would be set. Etc.
9141 Following traditional nomenclature, these bits map to:
9143 BIT0 | BIT 1 | BIT 2 | BIT 3
9146 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
9151 /* All variant. OV bit. */
9153 /* We need to get to the OV bit, which is the ORDERED bit. We
9154 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
9155 that's ugly and will make validate_condition_mode die.
9156 So let's just use another pattern. */
9157 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
9159 /* Any variant. EQ bit. */
9163 /* Upper variant. LT bit. */
9167 /* Lower variant. GT bit. */
9172 error ("argument 1 of __builtin_spe_predicate is out of range");
9176 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
9177 emit_move_insn (target, tmp);
9182 /* The evsel builtins look like this:
9184 e = __builtin_spe_evsel_OP (a, b, c, d);
9188 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
9189 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
9193 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
9196 tree arg0 = CALL_EXPR_ARG (exp, 0);
9197 tree arg1 = CALL_EXPR_ARG (exp, 1);
9198 tree arg2 = CALL_EXPR_ARG (exp, 2);
9199 tree arg3 = CALL_EXPR_ARG (exp, 3);
9200 rtx op0 = expand_normal (arg0);
9201 rtx op1 = expand_normal (arg1);
9202 rtx op2 = expand_normal (arg2);
9203 rtx op3 = expand_normal (arg3);
9204 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9205 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9207 gcc_assert (mode0 == mode1);
9209 if (arg0 == error_mark_node || arg1 == error_mark_node
9210 || arg2 == error_mark_node || arg3 == error_mark_node)
9214 || GET_MODE (target) != mode0
9215 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
9216 target = gen_reg_rtx (mode0);
9218 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9219 op0 = copy_to_mode_reg (mode0, op0);
9220 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
9221 op1 = copy_to_mode_reg (mode0, op1);
9222 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
9223 op2 = copy_to_mode_reg (mode0, op2);
9224 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
9225 op3 = copy_to_mode_reg (mode0, op3);
9227 /* Generate the compare. */
9228 scratch = gen_reg_rtx (CCmode);
9229 pat = GEN_FCN (icode) (scratch, op0, op1);
9234 if (mode0 == V2SImode)
9235 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
9237 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
9242 /* Expand an expression EXP that calls a built-in function,
9243 with result going to TARGET if that's convenient
9244 (and in mode MODE if that's convenient).
9245 SUBTARGET may be used as the target for computing one of EXP's operands.
9246 IGNORE is nonzero if the value is to be ignored. */
9249 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9250 enum machine_mode mode ATTRIBUTE_UNUSED,
9251 int ignore ATTRIBUTE_UNUSED)
9253 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9254 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9255 const struct builtin_description *d;
9260 if (fcode == RS6000_BUILTIN_RECIP)
9261 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
9263 if (fcode == RS6000_BUILTIN_RECIPF)
9264 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
9266 if (fcode == RS6000_BUILTIN_RSQRTF)
9267 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
9269 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
9270 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9272 int icode = (int) CODE_FOR_altivec_lvsr;
9273 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9274 enum machine_mode mode = insn_data[icode].operand[1].mode;
9278 gcc_assert (TARGET_ALTIVEC);
9280 arg = CALL_EXPR_ARG (exp, 0);
9281 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
9282 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
9283 addr = memory_address (mode, op);
9284 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
9288 /* For the load case need to negate the address. */
9289 op = gen_reg_rtx (GET_MODE (addr));
9290 emit_insn (gen_rtx_SET (VOIDmode, op,
9291 gen_rtx_NEG (GET_MODE (addr), addr)));
9293 op = gen_rtx_MEM (mode, op);
9296 || GET_MODE (target) != tmode
9297 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9298 target = gen_reg_rtx (tmode);
9300 /*pat = gen_altivec_lvsr (target, op);*/
9301 pat = GEN_FCN (icode) (target, op);
9309 /* FIXME: There's got to be a nicer way to handle this case than
9310 constructing a new CALL_EXPR. */
9311 if (fcode == ALTIVEC_BUILTIN_VCFUX
9312 || fcode == ALTIVEC_BUILTIN_VCFSX
9313 || fcode == ALTIVEC_BUILTIN_VCTUXS
9314 || fcode == ALTIVEC_BUILTIN_VCTSXS)
9316 if (call_expr_nargs (exp) == 1)
9317 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
9318 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
9323 ret = altivec_expand_builtin (exp, target, &success);
9330 ret = spe_expand_builtin (exp, target, &success);
9335 if (TARGET_PAIRED_FLOAT)
9337 ret = paired_expand_builtin (exp, target, &success);
9343 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
9345 /* Handle simple unary operations. */
9346 d = (struct builtin_description *) bdesc_1arg;
9347 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9348 if (d->code == fcode)
9349 return rs6000_expand_unop_builtin (d->icode, exp, target);
9351 /* Handle simple binary operations. */
9352 d = (struct builtin_description *) bdesc_2arg;
9353 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9354 if (d->code == fcode)
9355 return rs6000_expand_binop_builtin (d->icode, exp, target);
9357 /* Handle simple ternary operations. */
9359 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9360 if (d->code == fcode)
9361 return rs6000_expand_ternop_builtin (d->icode, exp, target);
9367 rs6000_init_builtins (void)
9371 V2SI_type_node = build_vector_type (intSI_type_node, 2);
9372 V2SF_type_node = build_vector_type (float_type_node, 2);
9373 V4HI_type_node = build_vector_type (intHI_type_node, 4);
9374 V4SI_type_node = build_vector_type (intSI_type_node, 4);
9375 V4SF_type_node = build_vector_type (float_type_node, 4);
9376 V8HI_type_node = build_vector_type (intHI_type_node, 8);
9377 V16QI_type_node = build_vector_type (intQI_type_node, 16);
9379 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
9380 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
9381 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
9383 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
9384 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
9385 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
9386 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
9388 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9389 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9390 'vector unsigned short'. */
9392 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
9393 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9394 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
9395 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
9397 long_integer_type_internal_node = long_integer_type_node;
9398 long_unsigned_type_internal_node = long_unsigned_type_node;
9399 intQI_type_internal_node = intQI_type_node;
9400 uintQI_type_internal_node = unsigned_intQI_type_node;
9401 intHI_type_internal_node = intHI_type_node;
9402 uintHI_type_internal_node = unsigned_intHI_type_node;
9403 intSI_type_internal_node = intSI_type_node;
9404 uintSI_type_internal_node = unsigned_intSI_type_node;
9405 float_type_internal_node = float_type_node;
9406 void_type_internal_node = void_type_node;
9408 tdecl = build_decl (TYPE_DECL, get_identifier ("__bool char"),
9409 bool_char_type_node);
9410 TYPE_NAME (bool_char_type_node) = tdecl;
9411 (*lang_hooks.decls.pushdecl) (tdecl);
9412 tdecl = build_decl (TYPE_DECL, get_identifier ("__bool short"),
9413 bool_short_type_node);
9414 TYPE_NAME (bool_short_type_node) = tdecl;
9415 (*lang_hooks.decls.pushdecl) (tdecl);
9416 tdecl = build_decl (TYPE_DECL, get_identifier ("__bool int"),
9417 bool_int_type_node);
9418 TYPE_NAME (bool_int_type_node) = tdecl;
9419 (*lang_hooks.decls.pushdecl) (tdecl);
9420 tdecl = build_decl (TYPE_DECL, get_identifier ("__pixel"),
9422 TYPE_NAME (pixel_type_node) = tdecl;
9423 (*lang_hooks.decls.pushdecl) (tdecl);
9425 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
9426 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
9427 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
9428 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
9430 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned char"),
9431 unsigned_V16QI_type_node);
9432 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
9433 (*lang_hooks.decls.pushdecl) (tdecl);
9434 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed char"),
9436 TYPE_NAME (V16QI_type_node) = tdecl;
9437 (*lang_hooks.decls.pushdecl) (tdecl);
9438 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool char"),
9439 bool_V16QI_type_node);
9440 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
9441 (*lang_hooks.decls.pushdecl) (tdecl);
9443 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned short"),
9444 unsigned_V8HI_type_node);
9445 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
9446 (*lang_hooks.decls.pushdecl) (tdecl);
9447 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed short"),
9449 TYPE_NAME (V8HI_type_node) = tdecl;
9450 (*lang_hooks.decls.pushdecl) (tdecl);
9451 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool short"),
9452 bool_V8HI_type_node);
9453 TYPE_NAME (bool_V8HI_type_node) = tdecl;
9454 (*lang_hooks.decls.pushdecl) (tdecl);
9456 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned int"),
9457 unsigned_V4SI_type_node);
9458 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
9459 (*lang_hooks.decls.pushdecl) (tdecl);
9460 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed int"),
9462 TYPE_NAME (V4SI_type_node) = tdecl;
9463 (*lang_hooks.decls.pushdecl) (tdecl);
9464 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool int"),
9465 bool_V4SI_type_node);
9466 TYPE_NAME (bool_V4SI_type_node) = tdecl;
9467 (*lang_hooks.decls.pushdecl) (tdecl);
9469 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector float"),
9471 TYPE_NAME (V4SF_type_node) = tdecl;
9472 (*lang_hooks.decls.pushdecl) (tdecl);
9473 tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __pixel"),
9474 pixel_V8HI_type_node);
9475 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
9476 (*lang_hooks.decls.pushdecl) (tdecl);
9478 if (TARGET_PAIRED_FLOAT)
9479 paired_init_builtins ();
9481 spe_init_builtins ();
9483 altivec_init_builtins ();
9484 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
9485 rs6000_common_init_builtins ();
9486 if (TARGET_PPC_GFXOPT)
9488 tree ftype = build_function_type_list (float_type_node,
9492 def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
9493 RS6000_BUILTIN_RECIPF);
9495 ftype = build_function_type_list (float_type_node,
9498 def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
9499 RS6000_BUILTIN_RSQRTF);
9503 tree ftype = build_function_type_list (double_type_node,
9507 def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
9508 RS6000_BUILTIN_RECIP);
9513 /* AIX libm provides clog as __clog. */
9514 if (built_in_decls [BUILT_IN_CLOG])
9515 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
9518 #ifdef SUBTARGET_INIT_BUILTINS
9519 SUBTARGET_INIT_BUILTINS;
9523 /* Search through a set of builtins and enable the mask bits.
9524 DESC is an array of builtins.
9525 SIZE is the total number of builtins.
9526 START is the builtin enum at which to start.
9527 END is the builtin enum at which to end. */
9529 enable_mask_for_builtins (struct builtin_description *desc, int size,
9530 enum rs6000_builtins start,
9531 enum rs6000_builtins end)
9535 for (i = 0; i < size; ++i)
9536 if (desc[i].code == start)
9542 for (; i < size; ++i)
9544 /* Flip all the bits on. */
9545 desc[i].mask = target_flags;
9546 if (desc[i].code == end)
9552 spe_init_builtins (void)
9554 tree endlink = void_list_node;
9555 tree puint_type_node = build_pointer_type (unsigned_type_node);
9556 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
9557 struct builtin_description *d;
9560 tree v2si_ftype_4_v2si
9561 = build_function_type
9562 (opaque_V2SI_type_node,
9563 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9564 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9565 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9566 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9569 tree v2sf_ftype_4_v2sf
9570 = build_function_type
9571 (opaque_V2SF_type_node,
9572 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9573 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9574 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9575 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9578 tree int_ftype_int_v2si_v2si
9579 = build_function_type
9581 tree_cons (NULL_TREE, integer_type_node,
9582 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9583 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9586 tree int_ftype_int_v2sf_v2sf
9587 = build_function_type
9589 tree_cons (NULL_TREE, integer_type_node,
9590 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9591 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9594 tree void_ftype_v2si_puint_int
9595 = build_function_type (void_type_node,
9596 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9597 tree_cons (NULL_TREE, puint_type_node,
9598 tree_cons (NULL_TREE,
9602 tree void_ftype_v2si_puint_char
9603 = build_function_type (void_type_node,
9604 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9605 tree_cons (NULL_TREE, puint_type_node,
9606 tree_cons (NULL_TREE,
9610 tree void_ftype_v2si_pv2si_int
9611 = build_function_type (void_type_node,
9612 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9613 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9614 tree_cons (NULL_TREE,
9618 tree void_ftype_v2si_pv2si_char
9619 = build_function_type (void_type_node,
9620 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9621 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9622 tree_cons (NULL_TREE,
9627 = build_function_type (void_type_node,
9628 tree_cons (NULL_TREE, integer_type_node, endlink));
9631 = build_function_type (integer_type_node, endlink);
9633 tree v2si_ftype_pv2si_int
9634 = build_function_type (opaque_V2SI_type_node,
9635 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9636 tree_cons (NULL_TREE, integer_type_node,
9639 tree v2si_ftype_puint_int
9640 = build_function_type (opaque_V2SI_type_node,
9641 tree_cons (NULL_TREE, puint_type_node,
9642 tree_cons (NULL_TREE, integer_type_node,
9645 tree v2si_ftype_pushort_int
9646 = build_function_type (opaque_V2SI_type_node,
9647 tree_cons (NULL_TREE, pushort_type_node,
9648 tree_cons (NULL_TREE, integer_type_node,
9651 tree v2si_ftype_signed_char
9652 = build_function_type (opaque_V2SI_type_node,
9653 tree_cons (NULL_TREE, signed_char_type_node,
9656 /* The initialization of the simple binary and unary builtins is
9657 done in rs6000_common_init_builtins, but we have to enable the
9658 mask bits here manually because we have run out of `target_flags'
9659 bits. We really need to redesign this mask business. */
9661 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9662 ARRAY_SIZE (bdesc_2arg),
9665 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9666 ARRAY_SIZE (bdesc_1arg),
9668 SPE_BUILTIN_EVSUBFUSIAAW);
9669 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9670 ARRAY_SIZE (bdesc_spe_predicates),
9671 SPE_BUILTIN_EVCMPEQ,
9672 SPE_BUILTIN_EVFSTSTLT);
9673 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9674 ARRAY_SIZE (bdesc_spe_evsel),
9675 SPE_BUILTIN_EVSEL_CMPGTS,
9676 SPE_BUILTIN_EVSEL_FSTSTEQ);
9678 (*lang_hooks.decls.pushdecl)
9679 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9680 opaque_V2SI_type_node));
9682 /* Initialize irregular SPE builtins. */
9684 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9685 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9686 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9687 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9688 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9689 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9690 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9691 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9692 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9693 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9694 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9695 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9696 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9697 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9698 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9699 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9700 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9701 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9704 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9705 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9706 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9707 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9708 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9709 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9710 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9711 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9712 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9713 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9714 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9715 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9716 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9717 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9718 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9719 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9720 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9721 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9722 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9723 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9724 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9725 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9728 d = (struct builtin_description *) bdesc_spe_predicates;
9729 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9733 switch (insn_data[d->icode].operand[1].mode)
9736 type = int_ftype_int_v2si_v2si;
9739 type = int_ftype_int_v2sf_v2sf;
9745 def_builtin (d->mask, d->name, type, d->code);
9748 /* Evsel predicates. */
9749 d = (struct builtin_description *) bdesc_spe_evsel;
9750 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9754 switch (insn_data[d->icode].operand[1].mode)
9757 type = v2si_ftype_4_v2si;
9760 type = v2sf_ftype_4_v2sf;
9766 def_builtin (d->mask, d->name, type, d->code);
9771 paired_init_builtins (void)
9773 const struct builtin_description *d;
9775 tree endlink = void_list_node;
9777 tree int_ftype_int_v2sf_v2sf
9778 = build_function_type
9780 tree_cons (NULL_TREE, integer_type_node,
9781 tree_cons (NULL_TREE, V2SF_type_node,
9782 tree_cons (NULL_TREE, V2SF_type_node,
9784 tree pcfloat_type_node =
9785 build_pointer_type (build_qualified_type
9786 (float_type_node, TYPE_QUAL_CONST));
9788 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9789 long_integer_type_node,
9792 tree void_ftype_v2sf_long_pcfloat =
9793 build_function_type_list (void_type_node,
9795 long_integer_type_node,
9800 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9804 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9805 PAIRED_BUILTIN_STX);
9808 d = bdesc_paired_preds;
9809 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9813 switch (insn_data[d->icode].operand[1].mode)
9816 type = int_ftype_int_v2sf_v2sf;
9822 def_builtin (d->mask, d->name, type, d->code);
9827 altivec_init_builtins (void)
9829 const struct builtin_description *d;
9830 const struct builtin_description_predicates *dp;
9834 tree pfloat_type_node = build_pointer_type (float_type_node);
9835 tree pint_type_node = build_pointer_type (integer_type_node);
9836 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9837 tree pchar_type_node = build_pointer_type (char_type_node);
9839 tree pvoid_type_node = build_pointer_type (void_type_node);
9841 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9842 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9843 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9844 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9846 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9848 tree int_ftype_opaque
9849 = build_function_type_list (integer_type_node,
9850 opaque_V4SI_type_node, NULL_TREE);
9851 tree opaque_ftype_opaque
9852 = build_function_type (integer_type_node,
9854 tree opaque_ftype_opaque_int
9855 = build_function_type_list (opaque_V4SI_type_node,
9856 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9857 tree opaque_ftype_opaque_opaque_int
9858 = build_function_type_list (opaque_V4SI_type_node,
9859 opaque_V4SI_type_node, opaque_V4SI_type_node,
9860 integer_type_node, NULL_TREE);
9861 tree int_ftype_int_opaque_opaque
9862 = build_function_type_list (integer_type_node,
9863 integer_type_node, opaque_V4SI_type_node,
9864 opaque_V4SI_type_node, NULL_TREE);
9865 tree int_ftype_int_v4si_v4si
9866 = build_function_type_list (integer_type_node,
9867 integer_type_node, V4SI_type_node,
9868 V4SI_type_node, NULL_TREE);
9869 tree v4sf_ftype_pcfloat
9870 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9871 tree void_ftype_pfloat_v4sf
9872 = build_function_type_list (void_type_node,
9873 pfloat_type_node, V4SF_type_node, NULL_TREE);
9874 tree v4si_ftype_pcint
9875 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9876 tree void_ftype_pint_v4si
9877 = build_function_type_list (void_type_node,
9878 pint_type_node, V4SI_type_node, NULL_TREE);
9879 tree v8hi_ftype_pcshort
9880 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9881 tree void_ftype_pshort_v8hi
9882 = build_function_type_list (void_type_node,
9883 pshort_type_node, V8HI_type_node, NULL_TREE);
9884 tree v16qi_ftype_pcchar
9885 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9886 tree void_ftype_pchar_v16qi
9887 = build_function_type_list (void_type_node,
9888 pchar_type_node, V16QI_type_node, NULL_TREE);
9889 tree void_ftype_v4si
9890 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9891 tree v8hi_ftype_void
9892 = build_function_type (V8HI_type_node, void_list_node);
9893 tree void_ftype_void
9894 = build_function_type (void_type_node, void_list_node);
9896 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9898 tree opaque_ftype_long_pcvoid
9899 = build_function_type_list (opaque_V4SI_type_node,
9900 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9901 tree v16qi_ftype_long_pcvoid
9902 = build_function_type_list (V16QI_type_node,
9903 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9904 tree v8hi_ftype_long_pcvoid
9905 = build_function_type_list (V8HI_type_node,
9906 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9907 tree v4si_ftype_long_pcvoid
9908 = build_function_type_list (V4SI_type_node,
9909 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9911 tree void_ftype_opaque_long_pvoid
9912 = build_function_type_list (void_type_node,
9913 opaque_V4SI_type_node, long_integer_type_node,
9914 pvoid_type_node, NULL_TREE);
9915 tree void_ftype_v4si_long_pvoid
9916 = build_function_type_list (void_type_node,
9917 V4SI_type_node, long_integer_type_node,
9918 pvoid_type_node, NULL_TREE);
9919 tree void_ftype_v16qi_long_pvoid
9920 = build_function_type_list (void_type_node,
9921 V16QI_type_node, long_integer_type_node,
9922 pvoid_type_node, NULL_TREE);
9923 tree void_ftype_v8hi_long_pvoid
9924 = build_function_type_list (void_type_node,
9925 V8HI_type_node, long_integer_type_node,
9926 pvoid_type_node, NULL_TREE);
9927 tree int_ftype_int_v8hi_v8hi
9928 = build_function_type_list (integer_type_node,
9929 integer_type_node, V8HI_type_node,
9930 V8HI_type_node, NULL_TREE);
9931 tree int_ftype_int_v16qi_v16qi
9932 = build_function_type_list (integer_type_node,
9933 integer_type_node, V16QI_type_node,
9934 V16QI_type_node, NULL_TREE);
9935 tree int_ftype_int_v4sf_v4sf
9936 = build_function_type_list (integer_type_node,
9937 integer_type_node, V4SF_type_node,
9938 V4SF_type_node, NULL_TREE);
9939 tree v4si_ftype_v4si
9940 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9941 tree v8hi_ftype_v8hi
9942 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9943 tree v16qi_ftype_v16qi
9944 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9945 tree v4sf_ftype_v4sf
9946 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9947 tree void_ftype_pcvoid_int_int
9948 = build_function_type_list (void_type_node,
9949 pcvoid_type_node, integer_type_node,
9950 integer_type_node, NULL_TREE);
9952 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9953 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9954 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9955 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9956 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9957 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9958 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9959 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9960 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9961 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9962 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9963 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9964 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9965 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9966 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9967 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9968 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9969 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9970 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9971 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9972 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9973 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9974 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9975 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9976 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9977 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9978 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9979 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9980 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9981 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9982 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9983 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9984 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9985 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9986 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9987 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9988 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9989 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9990 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9991 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9992 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9993 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9994 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9995 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9996 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9997 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9999 if (rs6000_cpu == PROCESSOR_CELL)
10001 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
10002 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
10003 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
10004 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
10006 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
10007 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
10008 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
10009 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
10011 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
10012 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
10013 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
10014 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
10016 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
10017 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
10018 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
10019 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
10021 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
10022 def_builtin (MASK_ALTIVEC, "__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
10023 def_builtin (MASK_ALTIVEC, "__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
10025 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
10026 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
10027 def_builtin (MASK_ALTIVEC, "__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
10028 def_builtin (MASK_ALTIVEC, "__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
10029 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
10030 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
10031 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
10032 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
10033 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
10034 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
10035 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
10036 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
10038 /* Add the DST variants. */
10040 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10041 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
10043 /* Initialize the predicates. */
10044 dp = bdesc_altivec_preds;
10045 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
10047 enum machine_mode mode1;
10049 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10050 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10055 mode1 = insn_data[dp->icode].operand[1].mode;
10060 type = int_ftype_int_opaque_opaque;
10063 type = int_ftype_int_v4si_v4si;
10066 type = int_ftype_int_v8hi_v8hi;
10069 type = int_ftype_int_v16qi_v16qi;
10072 type = int_ftype_int_v4sf_v4sf;
10075 gcc_unreachable ();
10078 def_builtin (dp->mask, dp->name, type, dp->code);
10081 /* Initialize the abs* operators. */
10083 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10085 enum machine_mode mode0;
10088 mode0 = insn_data[d->icode].operand[0].mode;
10093 type = v4si_ftype_v4si;
10096 type = v8hi_ftype_v8hi;
10099 type = v16qi_ftype_v16qi;
10102 type = v4sf_ftype_v4sf;
10105 gcc_unreachable ();
10108 def_builtin (d->mask, d->name, type, d->code);
10111 if (TARGET_ALTIVEC)
10115 /* Initialize target builtin that implements
10116 targetm.vectorize.builtin_mask_for_load. */
10118 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
10119 v16qi_ftype_long_pcvoid,
10120 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
10121 BUILT_IN_MD, NULL, NULL_TREE);
10122 TREE_READONLY (decl) = 1;
10123 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
10124 altivec_builtin_mask_for_load = decl;
10127 /* Access to the vec_init patterns. */
10128 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
10129 integer_type_node, integer_type_node,
10130 integer_type_node, NULL_TREE);
10131 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
10132 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
10134 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
10135 short_integer_type_node,
10136 short_integer_type_node,
10137 short_integer_type_node,
10138 short_integer_type_node,
10139 short_integer_type_node,
10140 short_integer_type_node,
10141 short_integer_type_node, NULL_TREE);
10142 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
10143 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
10145 ftype = build_function_type_list (V16QI_type_node, char_type_node,
10146 char_type_node, char_type_node,
10147 char_type_node, char_type_node,
10148 char_type_node, char_type_node,
10149 char_type_node, char_type_node,
10150 char_type_node, char_type_node,
10151 char_type_node, char_type_node,
10152 char_type_node, char_type_node,
10153 char_type_node, NULL_TREE);
10154 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
10155 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
10157 ftype = build_function_type_list (V4SF_type_node, float_type_node,
10158 float_type_node, float_type_node,
10159 float_type_node, NULL_TREE);
10160 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
10161 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
10163 /* Access to the vec_set patterns. */
10164 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
10166 integer_type_node, NULL_TREE);
10167 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
10168 ALTIVEC_BUILTIN_VEC_SET_V4SI);
10170 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
10172 integer_type_node, NULL_TREE);
10173 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
10174 ALTIVEC_BUILTIN_VEC_SET_V8HI);
10176 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
10178 integer_type_node, NULL_TREE);
10179 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
10180 ALTIVEC_BUILTIN_VEC_SET_V16QI);
10182 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
10184 integer_type_node, NULL_TREE);
10185 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
10186 ALTIVEC_BUILTIN_VEC_SET_V4SF);
10188 /* Access to the vec_extract patterns. */
10189 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
10190 integer_type_node, NULL_TREE);
10191 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
10192 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
10194 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
10195 integer_type_node, NULL_TREE);
10196 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
10197 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
10199 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
10200 integer_type_node, NULL_TREE);
10201 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
10202 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
10204 ftype = build_function_type_list (float_type_node, V4SF_type_node,
10205 integer_type_node, NULL_TREE);
10206 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
10207 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
10211 rs6000_common_init_builtins (void)
10213 const struct builtin_description *d;
10216 tree v2sf_ftype_v2sf_v2sf_v2sf
10217 = build_function_type_list (V2SF_type_node,
10218 V2SF_type_node, V2SF_type_node,
10219 V2SF_type_node, NULL_TREE);
10221 tree v4sf_ftype_v4sf_v4sf_v16qi
10222 = build_function_type_list (V4SF_type_node,
10223 V4SF_type_node, V4SF_type_node,
10224 V16QI_type_node, NULL_TREE);
10225 tree v4si_ftype_v4si_v4si_v16qi
10226 = build_function_type_list (V4SI_type_node,
10227 V4SI_type_node, V4SI_type_node,
10228 V16QI_type_node, NULL_TREE);
10229 tree v8hi_ftype_v8hi_v8hi_v16qi
10230 = build_function_type_list (V8HI_type_node,
10231 V8HI_type_node, V8HI_type_node,
10232 V16QI_type_node, NULL_TREE);
10233 tree v16qi_ftype_v16qi_v16qi_v16qi
10234 = build_function_type_list (V16QI_type_node,
10235 V16QI_type_node, V16QI_type_node,
10236 V16QI_type_node, NULL_TREE);
10237 tree v4si_ftype_int
10238 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
10239 tree v8hi_ftype_int
10240 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
10241 tree v16qi_ftype_int
10242 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
10243 tree v8hi_ftype_v16qi
10244 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
10245 tree v4sf_ftype_v4sf
10246 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
10248 tree v2si_ftype_v2si_v2si
10249 = build_function_type_list (opaque_V2SI_type_node,
10250 opaque_V2SI_type_node,
10251 opaque_V2SI_type_node, NULL_TREE);
10253 tree v2sf_ftype_v2sf_v2sf_spe
10254 = build_function_type_list (opaque_V2SF_type_node,
10255 opaque_V2SF_type_node,
10256 opaque_V2SF_type_node, NULL_TREE);
10258 tree v2sf_ftype_v2sf_v2sf
10259 = build_function_type_list (V2SF_type_node,
10261 V2SF_type_node, NULL_TREE);
10264 tree v2si_ftype_int_int
10265 = build_function_type_list (opaque_V2SI_type_node,
10266 integer_type_node, integer_type_node,
10269 tree opaque_ftype_opaque
10270 = build_function_type_list (opaque_V4SI_type_node,
10271 opaque_V4SI_type_node, NULL_TREE);
10273 tree v2si_ftype_v2si
10274 = build_function_type_list (opaque_V2SI_type_node,
10275 opaque_V2SI_type_node, NULL_TREE);
10277 tree v2sf_ftype_v2sf_spe
10278 = build_function_type_list (opaque_V2SF_type_node,
10279 opaque_V2SF_type_node, NULL_TREE);
10281 tree v2sf_ftype_v2sf
10282 = build_function_type_list (V2SF_type_node,
10283 V2SF_type_node, NULL_TREE);
10285 tree v2sf_ftype_v2si
10286 = build_function_type_list (opaque_V2SF_type_node,
10287 opaque_V2SI_type_node, NULL_TREE);
10289 tree v2si_ftype_v2sf
10290 = build_function_type_list (opaque_V2SI_type_node,
10291 opaque_V2SF_type_node, NULL_TREE);
10293 tree v2si_ftype_v2si_char
10294 = build_function_type_list (opaque_V2SI_type_node,
10295 opaque_V2SI_type_node,
10296 char_type_node, NULL_TREE);
10298 tree v2si_ftype_int_char
10299 = build_function_type_list (opaque_V2SI_type_node,
10300 integer_type_node, char_type_node, NULL_TREE);
10302 tree v2si_ftype_char
10303 = build_function_type_list (opaque_V2SI_type_node,
10304 char_type_node, NULL_TREE);
10306 tree int_ftype_int_int
10307 = build_function_type_list (integer_type_node,
10308 integer_type_node, integer_type_node,
10311 tree opaque_ftype_opaque_opaque
10312 = build_function_type_list (opaque_V4SI_type_node,
10313 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
10314 tree v4si_ftype_v4si_v4si
10315 = build_function_type_list (V4SI_type_node,
10316 V4SI_type_node, V4SI_type_node, NULL_TREE);
10317 tree v4sf_ftype_v4si_int
10318 = build_function_type_list (V4SF_type_node,
10319 V4SI_type_node, integer_type_node, NULL_TREE);
10320 tree v4si_ftype_v4sf_int
10321 = build_function_type_list (V4SI_type_node,
10322 V4SF_type_node, integer_type_node, NULL_TREE);
10323 tree v4si_ftype_v4si_int
10324 = build_function_type_list (V4SI_type_node,
10325 V4SI_type_node, integer_type_node, NULL_TREE);
10326 tree v8hi_ftype_v8hi_int
10327 = build_function_type_list (V8HI_type_node,
10328 V8HI_type_node, integer_type_node, NULL_TREE);
10329 tree v16qi_ftype_v16qi_int
10330 = build_function_type_list (V16QI_type_node,
10331 V16QI_type_node, integer_type_node, NULL_TREE);
10332 tree v16qi_ftype_v16qi_v16qi_int
10333 = build_function_type_list (V16QI_type_node,
10334 V16QI_type_node, V16QI_type_node,
10335 integer_type_node, NULL_TREE);
10336 tree v8hi_ftype_v8hi_v8hi_int
10337 = build_function_type_list (V8HI_type_node,
10338 V8HI_type_node, V8HI_type_node,
10339 integer_type_node, NULL_TREE);
10340 tree v4si_ftype_v4si_v4si_int
10341 = build_function_type_list (V4SI_type_node,
10342 V4SI_type_node, V4SI_type_node,
10343 integer_type_node, NULL_TREE);
10344 tree v4sf_ftype_v4sf_v4sf_int
10345 = build_function_type_list (V4SF_type_node,
10346 V4SF_type_node, V4SF_type_node,
10347 integer_type_node, NULL_TREE);
10348 tree v4sf_ftype_v4sf_v4sf
10349 = build_function_type_list (V4SF_type_node,
10350 V4SF_type_node, V4SF_type_node, NULL_TREE);
10351 tree opaque_ftype_opaque_opaque_opaque
10352 = build_function_type_list (opaque_V4SI_type_node,
10353 opaque_V4SI_type_node, opaque_V4SI_type_node,
10354 opaque_V4SI_type_node, NULL_TREE);
10355 tree v4sf_ftype_v4sf_v4sf_v4si
10356 = build_function_type_list (V4SF_type_node,
10357 V4SF_type_node, V4SF_type_node,
10358 V4SI_type_node, NULL_TREE);
10359 tree v4sf_ftype_v4sf_v4sf_v4sf
10360 = build_function_type_list (V4SF_type_node,
10361 V4SF_type_node, V4SF_type_node,
10362 V4SF_type_node, NULL_TREE);
10363 tree v4si_ftype_v4si_v4si_v4si
10364 = build_function_type_list (V4SI_type_node,
10365 V4SI_type_node, V4SI_type_node,
10366 V4SI_type_node, NULL_TREE);
10367 tree v8hi_ftype_v8hi_v8hi
10368 = build_function_type_list (V8HI_type_node,
10369 V8HI_type_node, V8HI_type_node, NULL_TREE);
10370 tree v8hi_ftype_v8hi_v8hi_v8hi
10371 = build_function_type_list (V8HI_type_node,
10372 V8HI_type_node, V8HI_type_node,
10373 V8HI_type_node, NULL_TREE);
10374 tree v4si_ftype_v8hi_v8hi_v4si
10375 = build_function_type_list (V4SI_type_node,
10376 V8HI_type_node, V8HI_type_node,
10377 V4SI_type_node, NULL_TREE);
10378 tree v4si_ftype_v16qi_v16qi_v4si
10379 = build_function_type_list (V4SI_type_node,
10380 V16QI_type_node, V16QI_type_node,
10381 V4SI_type_node, NULL_TREE);
10382 tree v16qi_ftype_v16qi_v16qi
10383 = build_function_type_list (V16QI_type_node,
10384 V16QI_type_node, V16QI_type_node, NULL_TREE);
10385 tree v4si_ftype_v4sf_v4sf
10386 = build_function_type_list (V4SI_type_node,
10387 V4SF_type_node, V4SF_type_node, NULL_TREE);
10388 tree v8hi_ftype_v16qi_v16qi
10389 = build_function_type_list (V8HI_type_node,
10390 V16QI_type_node, V16QI_type_node, NULL_TREE);
10391 tree v4si_ftype_v8hi_v8hi
10392 = build_function_type_list (V4SI_type_node,
10393 V8HI_type_node, V8HI_type_node, NULL_TREE);
10394 tree v8hi_ftype_v4si_v4si
10395 = build_function_type_list (V8HI_type_node,
10396 V4SI_type_node, V4SI_type_node, NULL_TREE);
10397 tree v16qi_ftype_v8hi_v8hi
10398 = build_function_type_list (V16QI_type_node,
10399 V8HI_type_node, V8HI_type_node, NULL_TREE);
10400 tree v4si_ftype_v16qi_v4si
10401 = build_function_type_list (V4SI_type_node,
10402 V16QI_type_node, V4SI_type_node, NULL_TREE);
10403 tree v4si_ftype_v16qi_v16qi
10404 = build_function_type_list (V4SI_type_node,
10405 V16QI_type_node, V16QI_type_node, NULL_TREE);
10406 tree v4si_ftype_v8hi_v4si
10407 = build_function_type_list (V4SI_type_node,
10408 V8HI_type_node, V4SI_type_node, NULL_TREE);
10409 tree v4si_ftype_v8hi
10410 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
10411 tree int_ftype_v4si_v4si
10412 = build_function_type_list (integer_type_node,
10413 V4SI_type_node, V4SI_type_node, NULL_TREE);
10414 tree int_ftype_v4sf_v4sf
10415 = build_function_type_list (integer_type_node,
10416 V4SF_type_node, V4SF_type_node, NULL_TREE);
10417 tree int_ftype_v16qi_v16qi
10418 = build_function_type_list (integer_type_node,
10419 V16QI_type_node, V16QI_type_node, NULL_TREE);
10420 tree int_ftype_v8hi_v8hi
10421 = build_function_type_list (integer_type_node,
10422 V8HI_type_node, V8HI_type_node, NULL_TREE);
10424 /* Add the simple ternary operators. */
10426 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
10428 enum machine_mode mode0, mode1, mode2, mode3;
10430 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10431 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10442 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10445 mode0 = insn_data[d->icode].operand[0].mode;
10446 mode1 = insn_data[d->icode].operand[1].mode;
10447 mode2 = insn_data[d->icode].operand[2].mode;
10448 mode3 = insn_data[d->icode].operand[3].mode;
10451 /* When all four are of the same mode. */
10452 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
10457 type = opaque_ftype_opaque_opaque_opaque;
10460 type = v4si_ftype_v4si_v4si_v4si;
10463 type = v4sf_ftype_v4sf_v4sf_v4sf;
10466 type = v8hi_ftype_v8hi_v8hi_v8hi;
10469 type = v16qi_ftype_v16qi_v16qi_v16qi;
10472 type = v2sf_ftype_v2sf_v2sf_v2sf;
10475 gcc_unreachable ();
10478 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
10483 type = v4si_ftype_v4si_v4si_v16qi;
10486 type = v4sf_ftype_v4sf_v4sf_v16qi;
10489 type = v8hi_ftype_v8hi_v8hi_v16qi;
10492 type = v16qi_ftype_v16qi_v16qi_v16qi;
10495 gcc_unreachable ();
10498 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
10499 && mode3 == V4SImode)
10500 type = v4si_ftype_v16qi_v16qi_v4si;
10501 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
10502 && mode3 == V4SImode)
10503 type = v4si_ftype_v8hi_v8hi_v4si;
10504 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
10505 && mode3 == V4SImode)
10506 type = v4sf_ftype_v4sf_v4sf_v4si;
10508 /* vchar, vchar, vchar, 4-bit literal. */
10509 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
10510 && mode3 == QImode)
10511 type = v16qi_ftype_v16qi_v16qi_int;
10513 /* vshort, vshort, vshort, 4-bit literal. */
10514 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
10515 && mode3 == QImode)
10516 type = v8hi_ftype_v8hi_v8hi_int;
10518 /* vint, vint, vint, 4-bit literal. */
10519 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
10520 && mode3 == QImode)
10521 type = v4si_ftype_v4si_v4si_int;
10523 /* vfloat, vfloat, vfloat, 4-bit literal. */
10524 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
10525 && mode3 == QImode)
10526 type = v4sf_ftype_v4sf_v4sf_int;
10529 gcc_unreachable ();
10531 def_builtin (d->mask, d->name, type, d->code);
10534 /* Add the simple binary operators. */
10535 d = (struct builtin_description *) bdesc_2arg;
10536 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10538 enum machine_mode mode0, mode1, mode2;
10540 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10541 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10551 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10554 mode0 = insn_data[d->icode].operand[0].mode;
10555 mode1 = insn_data[d->icode].operand[1].mode;
10556 mode2 = insn_data[d->icode].operand[2].mode;
10559 /* When all three operands are of the same mode. */
10560 if (mode0 == mode1 && mode1 == mode2)
10565 type = opaque_ftype_opaque_opaque;
10568 type = v4sf_ftype_v4sf_v4sf;
10571 type = v4si_ftype_v4si_v4si;
10574 type = v16qi_ftype_v16qi_v16qi;
10577 type = v8hi_ftype_v8hi_v8hi;
10580 type = v2si_ftype_v2si_v2si;
10583 if (TARGET_PAIRED_FLOAT)
10584 type = v2sf_ftype_v2sf_v2sf;
10586 type = v2sf_ftype_v2sf_v2sf_spe;
10589 type = int_ftype_int_int;
10592 gcc_unreachable ();
10596 /* A few other combos we really don't want to do manually. */
10598 /* vint, vfloat, vfloat. */
10599 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
10600 type = v4si_ftype_v4sf_v4sf;
10602 /* vshort, vchar, vchar. */
10603 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
10604 type = v8hi_ftype_v16qi_v16qi;
10606 /* vint, vshort, vshort. */
10607 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
10608 type = v4si_ftype_v8hi_v8hi;
10610 /* vshort, vint, vint. */
10611 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
10612 type = v8hi_ftype_v4si_v4si;
10614 /* vchar, vshort, vshort. */
10615 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
10616 type = v16qi_ftype_v8hi_v8hi;
10618 /* vint, vchar, vint. */
10619 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
10620 type = v4si_ftype_v16qi_v4si;
10622 /* vint, vchar, vchar. */
10623 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
10624 type = v4si_ftype_v16qi_v16qi;
10626 /* vint, vshort, vint. */
10627 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
10628 type = v4si_ftype_v8hi_v4si;
10630 /* vint, vint, 5-bit literal. */
10631 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
10632 type = v4si_ftype_v4si_int;
10634 /* vshort, vshort, 5-bit literal. */
10635 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
10636 type = v8hi_ftype_v8hi_int;
10638 /* vchar, vchar, 5-bit literal. */
10639 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
10640 type = v16qi_ftype_v16qi_int;
10642 /* vfloat, vint, 5-bit literal. */
10643 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
10644 type = v4sf_ftype_v4si_int;
10646 /* vint, vfloat, 5-bit literal. */
10647 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
10648 type = v4si_ftype_v4sf_int;
10650 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
10651 type = v2si_ftype_int_int;
10653 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
10654 type = v2si_ftype_v2si_char;
10656 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
10657 type = v2si_ftype_int_char;
10662 gcc_assert (mode0 == SImode);
10666 type = int_ftype_v4si_v4si;
10669 type = int_ftype_v4sf_v4sf;
10672 type = int_ftype_v16qi_v16qi;
10675 type = int_ftype_v8hi_v8hi;
10678 gcc_unreachable ();
10682 def_builtin (d->mask, d->name, type, d->code);
10685 /* Add the simple unary operators. */
10686 d = (struct builtin_description *) bdesc_1arg;
10687 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10689 enum machine_mode mode0, mode1;
10691 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10692 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10701 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10704 mode0 = insn_data[d->icode].operand[0].mode;
10705 mode1 = insn_data[d->icode].operand[1].mode;
10708 if (mode0 == V4SImode && mode1 == QImode)
10709 type = v4si_ftype_int;
10710 else if (mode0 == V8HImode && mode1 == QImode)
10711 type = v8hi_ftype_int;
10712 else if (mode0 == V16QImode && mode1 == QImode)
10713 type = v16qi_ftype_int;
10714 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10715 type = opaque_ftype_opaque;
10716 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10717 type = v4sf_ftype_v4sf;
10718 else if (mode0 == V8HImode && mode1 == V16QImode)
10719 type = v8hi_ftype_v16qi;
10720 else if (mode0 == V4SImode && mode1 == V8HImode)
10721 type = v4si_ftype_v8hi;
10722 else if (mode0 == V2SImode && mode1 == V2SImode)
10723 type = v2si_ftype_v2si;
10724 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10726 if (TARGET_PAIRED_FLOAT)
10727 type = v2sf_ftype_v2sf;
10729 type = v2sf_ftype_v2sf_spe;
10731 else if (mode0 == V2SFmode && mode1 == V2SImode)
10732 type = v2sf_ftype_v2si;
10733 else if (mode0 == V2SImode && mode1 == V2SFmode)
10734 type = v2si_ftype_v2sf;
10735 else if (mode0 == V2SImode && mode1 == QImode)
10736 type = v2si_ftype_char;
10738 gcc_unreachable ();
10740 def_builtin (d->mask, d->name, type, d->code);
10745 rs6000_init_libfuncs (void)
10747 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10748 && !TARGET_POWER2 && !TARGET_POWERPC)
10750 /* AIX library routines for float->int conversion. */
10751 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10752 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10753 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10754 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10757 if (!TARGET_IEEEQUAD)
10758 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10759 if (!TARGET_XL_COMPAT)
10761 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10762 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10763 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10764 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10766 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10768 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10769 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10770 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10771 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10772 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10773 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10774 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10776 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10777 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10778 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10779 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10780 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10781 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10782 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10783 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10786 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10787 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10791 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10792 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10793 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10794 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10798 /* 32-bit SVR4 quad floating point routines. */
10800 set_optab_libfunc (add_optab, TFmode, "_q_add");
10801 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10802 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10803 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10804 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10805 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10806 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10808 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10809 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10810 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10811 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10812 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10813 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10815 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10816 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10817 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10818 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10819 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10820 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10821 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10822 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10827 /* Expand a block clear operation, and return 1 if successful. Return 0
10828 if we should let the compiler generate normal code.
10830 operands[0] is the destination
10831 operands[1] is the length
10832 operands[3] is the alignment */
10835 expand_block_clear (rtx operands[])
10837 rtx orig_dest = operands[0];
10838 rtx bytes_rtx = operands[1];
10839 rtx align_rtx = operands[3];
10840 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10841 HOST_WIDE_INT align;
10842 HOST_WIDE_INT bytes;
10847 /* If this is not a fixed size move, just call memcpy */
10851 /* This must be a fixed size alignment */
10852 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10853 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10855 /* Anything to clear? */
10856 bytes = INTVAL (bytes_rtx);
10860 /* Use the builtin memset after a point, to avoid huge code bloat.
10861 When optimize_size, avoid any significant code bloat; calling
10862 memset is about 4 instructions, so allow for one instruction to
10863 load zero and three to do clearing. */
10864 if (TARGET_ALTIVEC && align >= 128)
10866 else if (TARGET_POWERPC64 && align >= 32)
10868 else if (TARGET_SPE && align >= 64)
10873 if (optimize_size && bytes > 3 * clear_step)
10875 if (! optimize_size && bytes > 8 * clear_step)
10878 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10880 enum machine_mode mode = BLKmode;
10883 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10888 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10893 else if (bytes >= 8 && TARGET_POWERPC64
10894 /* 64-bit loads and stores require word-aligned
10896 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10901 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10902 { /* move 4 bytes */
10906 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10907 { /* move 2 bytes */
10911 else /* move 1 byte at a time */
10917 dest = adjust_address (orig_dest, mode, offset);
10919 emit_move_insn (dest, CONST0_RTX (mode));
10926 /* Expand a block move operation, and return 1 if successful. Return 0
10927 if we should let the compiler generate normal code.
10929 operands[0] is the destination
10930 operands[1] is the source
10931 operands[2] is the length
10932 operands[3] is the alignment */
10934 #define MAX_MOVE_REG 4
10937 expand_block_move (rtx operands[])
10939 rtx orig_dest = operands[0];
10940 rtx orig_src = operands[1];
10941 rtx bytes_rtx = operands[2];
10942 rtx align_rtx = operands[3];
10943 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10948 rtx stores[MAX_MOVE_REG];
10951 /* If this is not a fixed size move, just call memcpy */
10955 /* This must be a fixed size alignment */
10956 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10957 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10959 /* Anything to move? */
10960 bytes = INTVAL (bytes_rtx);
10964 /* store_one_arg depends on expand_block_move to handle at least the size of
10965 reg_parm_stack_space. */
10966 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10969 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10972 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10973 rtx (*mov) (rtx, rtx);
10975 enum machine_mode mode = BLKmode;
10978 /* Altivec first, since it will be faster than a string move
10979 when it applies, and usually not significantly larger. */
10980 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10984 gen_func.mov = gen_movv4si;
10986 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10990 gen_func.mov = gen_movv2si;
10992 else if (TARGET_STRING
10993 && bytes > 24 /* move up to 32 bytes at a time */
10999 && ! fixed_regs[10]
11000 && ! fixed_regs[11]
11001 && ! fixed_regs[12])
11003 move_bytes = (bytes > 32) ? 32 : bytes;
11004 gen_func.movmemsi = gen_movmemsi_8reg;
11006 else if (TARGET_STRING
11007 && bytes > 16 /* move up to 24 bytes at a time */
11013 && ! fixed_regs[10])
11015 move_bytes = (bytes > 24) ? 24 : bytes;
11016 gen_func.movmemsi = gen_movmemsi_6reg;
11018 else if (TARGET_STRING
11019 && bytes > 8 /* move up to 16 bytes at a time */
11023 && ! fixed_regs[8])
11025 move_bytes = (bytes > 16) ? 16 : bytes;
11026 gen_func.movmemsi = gen_movmemsi_4reg;
11028 else if (bytes >= 8 && TARGET_POWERPC64
11029 /* 64-bit loads and stores require word-aligned
11031 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
11035 gen_func.mov = gen_movdi;
11037 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
11038 { /* move up to 8 bytes at a time */
11039 move_bytes = (bytes > 8) ? 8 : bytes;
11040 gen_func.movmemsi = gen_movmemsi_2reg;
11042 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
11043 { /* move 4 bytes */
11046 gen_func.mov = gen_movsi;
11048 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
11049 { /* move 2 bytes */
11052 gen_func.mov = gen_movhi;
11054 else if (TARGET_STRING && bytes > 1)
11055 { /* move up to 4 bytes at a time */
11056 move_bytes = (bytes > 4) ? 4 : bytes;
11057 gen_func.movmemsi = gen_movmemsi_1reg;
11059 else /* move 1 byte at a time */
11063 gen_func.mov = gen_movqi;
11066 src = adjust_address (orig_src, mode, offset);
11067 dest = adjust_address (orig_dest, mode, offset);
11069 if (mode != BLKmode)
11071 rtx tmp_reg = gen_reg_rtx (mode);
11073 emit_insn ((*gen_func.mov) (tmp_reg, src));
11074 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
11077 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
11080 for (i = 0; i < num_reg; i++)
11081 emit_insn (stores[i]);
11085 if (mode == BLKmode)
11087 /* Move the address into scratch registers. The movmemsi
11088 patterns require zero offset. */
11089 if (!REG_P (XEXP (src, 0)))
11091 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
11092 src = replace_equiv_address (src, src_reg);
11094 set_mem_size (src, GEN_INT (move_bytes));
11096 if (!REG_P (XEXP (dest, 0)))
11098 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
11099 dest = replace_equiv_address (dest, dest_reg);
11101 set_mem_size (dest, GEN_INT (move_bytes));
11103 emit_insn ((*gen_func.movmemsi) (dest, src,
11104 GEN_INT (move_bytes & 31),
11113 /* Return a string to perform a load_multiple operation.
11114 operands[0] is the vector.
11115 operands[1] is the source address.
11116 operands[2] is the first destination register. */
11119 rs6000_output_load_multiple (rtx operands[3])
11121 /* We have to handle the case where the pseudo used to contain the address
11122 is assigned to one of the output registers. */
11124 int words = XVECLEN (operands[0], 0);
11127 if (XVECLEN (operands[0], 0) == 1)
11128 return "{l|lwz} %2,0(%1)";
11130 for (i = 0; i < words; i++)
11131 if (refers_to_regno_p (REGNO (operands[2]) + i,
11132 REGNO (operands[2]) + i + 1, operands[1], 0))
11136 xop[0] = GEN_INT (4 * (words-1));
11137 xop[1] = operands[1];
11138 xop[2] = operands[2];
11139 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
11144 xop[0] = GEN_INT (4 * (words-1));
11145 xop[1] = operands[1];
11146 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
11147 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
11152 for (j = 0; j < words; j++)
11155 xop[0] = GEN_INT (j * 4);
11156 xop[1] = operands[1];
11157 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
11158 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
11160 xop[0] = GEN_INT (i * 4);
11161 xop[1] = operands[1];
11162 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
11167 return "{lsi|lswi} %2,%1,%N0";
11171 /* A validation routine: say whether CODE, a condition code, and MODE
11172 match. The other alternatives either don't make sense or should
11173 never be generated. */
11176 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
11178 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
11179 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
11180 && GET_MODE_CLASS (mode) == MODE_CC);
11182 /* These don't make sense. */
11183 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
11184 || mode != CCUNSmode);
11186 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
11187 || mode == CCUNSmode);
11189 gcc_assert (mode == CCFPmode
11190 || (code != ORDERED && code != UNORDERED
11191 && code != UNEQ && code != LTGT
11192 && code != UNGT && code != UNLT
11193 && code != UNGE && code != UNLE));
11195 /* These should never be generated except for
11196 flag_finite_math_only. */
11197 gcc_assert (mode != CCFPmode
11198 || flag_finite_math_only
11199 || (code != LE && code != GE
11200 && code != UNEQ && code != LTGT
11201 && code != UNGT && code != UNLT));
11203 /* These are invalid; the information is not there. */
11204 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
11208 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
11209 mask required to convert the result of a rotate insn into a shift
11210 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
11213 includes_lshift_p (rtx shiftop, rtx andop)
11215 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
11217 shift_mask <<= INTVAL (shiftop);
11219 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
11222 /* Similar, but for right shift. */
11225 includes_rshift_p (rtx shiftop, rtx andop)
11227 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
11229 shift_mask >>= INTVAL (shiftop);
11231 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
11234 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
11235 to perform a left shift. It must have exactly SHIFTOP least
11236 significant 0's, then one or more 1's, then zero or more 0's. */
11239 includes_rldic_lshift_p (rtx shiftop, rtx andop)
11241 if (GET_CODE (andop) == CONST_INT)
11243 HOST_WIDE_INT c, lsb, shift_mask;
11245 c = INTVAL (andop);
11246 if (c == 0 || c == ~0)
11250 shift_mask <<= INTVAL (shiftop);
11252 /* Find the least significant one bit. */
11255 /* It must coincide with the LSB of the shift mask. */
11256 if (-lsb != shift_mask)
11259 /* Invert to look for the next transition (if any). */
11262 /* Remove the low group of ones (originally low group of zeros). */
11265 /* Again find the lsb, and check we have all 1's above. */
11269 else if (GET_CODE (andop) == CONST_DOUBLE
11270 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11272 HOST_WIDE_INT low, high, lsb;
11273 HOST_WIDE_INT shift_mask_low, shift_mask_high;
11275 low = CONST_DOUBLE_LOW (andop);
11276 if (HOST_BITS_PER_WIDE_INT < 64)
11277 high = CONST_DOUBLE_HIGH (andop);
11279 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
11280 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
11283 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11285 shift_mask_high = ~0;
11286 if (INTVAL (shiftop) > 32)
11287 shift_mask_high <<= INTVAL (shiftop) - 32;
11289 lsb = high & -high;
11291 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
11297 lsb = high & -high;
11298 return high == -lsb;
11301 shift_mask_low = ~0;
11302 shift_mask_low <<= INTVAL (shiftop);
11306 if (-lsb != shift_mask_low)
11309 if (HOST_BITS_PER_WIDE_INT < 64)
11314 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
11316 lsb = high & -high;
11317 return high == -lsb;
11321 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
11327 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11328 to perform a left shift. It must have SHIFTOP or more least
11329 significant 0's, with the remainder of the word 1's. */
11332 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
11334 if (GET_CODE (andop) == CONST_INT)
11336 HOST_WIDE_INT c, lsb, shift_mask;
11339 shift_mask <<= INTVAL (shiftop);
11340 c = INTVAL (andop);
11342 /* Find the least significant one bit. */
11345 /* It must be covered by the shift mask.
11346 This test also rejects c == 0. */
11347 if ((lsb & shift_mask) == 0)
11350 /* Check we have all 1's above the transition, and reject all 1's. */
11351 return c == -lsb && lsb != 1;
11353 else if (GET_CODE (andop) == CONST_DOUBLE
11354 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
11356 HOST_WIDE_INT low, lsb, shift_mask_low;
11358 low = CONST_DOUBLE_LOW (andop);
11360 if (HOST_BITS_PER_WIDE_INT < 64)
11362 HOST_WIDE_INT high, shift_mask_high;
11364 high = CONST_DOUBLE_HIGH (andop);
11368 shift_mask_high = ~0;
11369 if (INTVAL (shiftop) > 32)
11370 shift_mask_high <<= INTVAL (shiftop) - 32;
11372 lsb = high & -high;
11374 if ((lsb & shift_mask_high) == 0)
11377 return high == -lsb;
11383 shift_mask_low = ~0;
11384 shift_mask_low <<= INTVAL (shiftop);
11388 if ((lsb & shift_mask_low) == 0)
11391 return low == -lsb && lsb != 1;
11397 /* Return 1 if operands will generate a valid arguments to rlwimi
11398 instruction for insert with right shift in 64-bit mode. The mask may
11399 not start on the first bit or stop on the last bit because wrap-around
11400 effects of instruction do not correspond to semantics of RTL insn. */
11403 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
11405 if (INTVAL (startop) > 32
11406 && INTVAL (startop) < 64
11407 && INTVAL (sizeop) > 1
11408 && INTVAL (sizeop) + INTVAL (startop) < 64
11409 && INTVAL (shiftop) > 0
11410 && INTVAL (sizeop) + INTVAL (shiftop) < 32
11411 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
11417 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11418 for lfq and stfq insns iff the registers are hard registers. */
11421 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
11423 /* We might have been passed a SUBREG. */
11424 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
11427 /* We might have been passed non floating point registers. */
11428 if (!FP_REGNO_P (REGNO (reg1))
11429 || !FP_REGNO_P (REGNO (reg2)))
11432 return (REGNO (reg1) == REGNO (reg2) - 1);
11435 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11436 addr1 and addr2 must be in consecutive memory locations
11437 (addr2 == addr1 + 8). */
11440 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
11443 unsigned int reg1, reg2;
11444 int offset1, offset2;
11446 /* The mems cannot be volatile. */
11447 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
11450 addr1 = XEXP (mem1, 0);
11451 addr2 = XEXP (mem2, 0);
11453 /* Extract an offset (if used) from the first addr. */
11454 if (GET_CODE (addr1) == PLUS)
11456 /* If not a REG, return zero. */
11457 if (GET_CODE (XEXP (addr1, 0)) != REG)
11461 reg1 = REGNO (XEXP (addr1, 0));
11462 /* The offset must be constant! */
11463 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
11465 offset1 = INTVAL (XEXP (addr1, 1));
11468 else if (GET_CODE (addr1) != REG)
11472 reg1 = REGNO (addr1);
11473 /* This was a simple (mem (reg)) expression. Offset is 0. */
11477 /* And now for the second addr. */
11478 if (GET_CODE (addr2) == PLUS)
11480 /* If not a REG, return zero. */
11481 if (GET_CODE (XEXP (addr2, 0)) != REG)
11485 reg2 = REGNO (XEXP (addr2, 0));
11486 /* The offset must be constant. */
11487 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
11489 offset2 = INTVAL (XEXP (addr2, 1));
11492 else if (GET_CODE (addr2) != REG)
11496 reg2 = REGNO (addr2);
11497 /* This was a simple (mem (reg)) expression. Offset is 0. */
11501 /* Both of these must have the same base register. */
11505 /* The offset for the second addr must be 8 more than the first addr. */
11506 if (offset2 != offset1 + 8)
11509 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11516 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
11518 static bool eliminated = false;
11519 if (mode != SDmode)
11520 return assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
11523 rtx mem = cfun->machine->sdmode_stack_slot;
11524 gcc_assert (mem != NULL_RTX);
11528 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
11529 cfun->machine->sdmode_stack_slot = mem;
11537 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
11539 /* Don't walk into types. */
11540 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
11542 *walk_subtrees = 0;
11546 switch (TREE_CODE (*tp))
11555 case ALIGN_INDIRECT_REF:
11556 case MISALIGNED_INDIRECT_REF:
11557 case VIEW_CONVERT_EXPR:
11558 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
11569 /* Allocate a 64-bit stack slot to be used for copying SDmode
11570 values through if this function has any SDmode references. */
11573 rs6000_alloc_sdmode_stack_slot (void)
11577 gimple_stmt_iterator gsi;
11579 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
11582 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
11584 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
11587 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11588 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11594 /* Check for any SDmode parameters of the function. */
11595 for (t = DECL_ARGUMENTS (cfun->decl); t; t = TREE_CHAIN (t))
11597 if (TREE_TYPE (t) == error_mark_node)
11600 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
11601 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
11603 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
11604 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
11612 rs6000_instantiate_decls (void)
11614 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
11615 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
11618 /* Return the register class of a scratch register needed to copy IN into
11619 or out of a register in RCLASS in MODE. If it can be done directly,
11620 NO_REGS is returned. */
11623 rs6000_secondary_reload_class (enum reg_class rclass,
11624 enum machine_mode mode ATTRIBUTE_UNUSED,
11629 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
11631 && MACHOPIC_INDIRECT
11635 /* We cannot copy a symbolic operand directly into anything
11636 other than BASE_REGS for TARGET_ELF. So indicate that a
11637 register from BASE_REGS is needed as an intermediate
11640 On Darwin, pic addresses require a load from memory, which
11641 needs a base register. */
11642 if (rclass != BASE_REGS
11643 && (GET_CODE (in) == SYMBOL_REF
11644 || GET_CODE (in) == HIGH
11645 || GET_CODE (in) == LABEL_REF
11646 || GET_CODE (in) == CONST))
11650 if (GET_CODE (in) == REG)
11652 regno = REGNO (in);
11653 if (regno >= FIRST_PSEUDO_REGISTER)
11655 regno = true_regnum (in);
11656 if (regno >= FIRST_PSEUDO_REGISTER)
11660 else if (GET_CODE (in) == SUBREG)
11662 regno = true_regnum (in);
11663 if (regno >= FIRST_PSEUDO_REGISTER)
11669 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11671 if (rclass == GENERAL_REGS || rclass == BASE_REGS
11672 || (regno >= 0 && INT_REGNO_P (regno)))
11675 /* Constants, memory, and FP registers can go into FP registers. */
11676 if ((regno == -1 || FP_REGNO_P (regno))
11677 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
11678 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
11680 /* Memory, and AltiVec registers can go into AltiVec registers. */
11681 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
11682 && rclass == ALTIVEC_REGS)
11685 /* We can copy among the CR registers. */
11686 if ((rclass == CR_REGS || rclass == CR0_REGS)
11687 && regno >= 0 && CR_REGNO_P (regno))
11690 /* Otherwise, we need GENERAL_REGS. */
11691 return GENERAL_REGS;
11694 /* Given a comparison operation, return the bit number in CCR to test. We
11695 know this is a valid comparison.
11697 SCC_P is 1 if this is for an scc. That means that %D will have been
11698 used instead of %C, so the bits will be in different places.
11700 Return -1 if OP isn't a valid comparison for some reason. */
11703 ccr_bit (rtx op, int scc_p)
11705 enum rtx_code code = GET_CODE (op);
11706 enum machine_mode cc_mode;
11711 if (!COMPARISON_P (op))
11714 reg = XEXP (op, 0);
11716 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
11718 cc_mode = GET_MODE (reg);
11719 cc_regnum = REGNO (reg);
11720 base_bit = 4 * (cc_regnum - CR0_REGNO);
11722 validate_condition_mode (code, cc_mode);
11724 /* When generating a sCOND operation, only positive conditions are
11727 || code == EQ || code == GT || code == LT || code == UNORDERED
11728 || code == GTU || code == LTU);
11733 return scc_p ? base_bit + 3 : base_bit + 2;
11735 return base_bit + 2;
11736 case GT: case GTU: case UNLE:
11737 return base_bit + 1;
11738 case LT: case LTU: case UNGE:
11740 case ORDERED: case UNORDERED:
11741 return base_bit + 3;
11744 /* If scc, we will have done a cror to put the bit in the
11745 unordered position. So test that bit. For integer, this is ! LT
11746 unless this is an scc insn. */
11747 return scc_p ? base_bit + 3 : base_bit;
11750 return scc_p ? base_bit + 3 : base_bit + 1;
11753 gcc_unreachable ();
11757 /* Return the GOT register. */
11760 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
11762 /* The second flow pass currently (June 1999) can't update
11763 regs_ever_live without disturbing other parts of the compiler, so
11764 update it here to make the prolog/epilogue code happy. */
11765 if (!can_create_pseudo_p ()
11766 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
11767 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
11769 crtl->uses_pic_offset_table = 1;
11771 return pic_offset_table_rtx;
11774 /* Function to init struct machine_function.
11775 This will be called, via a pointer variable,
11776 from push_function_context. */
11778 static struct machine_function *
11779 rs6000_init_machine_status (void)
11781 return GGC_CNEW (machine_function);
11784 /* These macros test for integers and extract the low-order bits. */
11786 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11787 && GET_MODE (X) == VOIDmode)
11789 #define INT_LOWPART(X) \
11790 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11793 extract_MB (rtx op)
11796 unsigned long val = INT_LOWPART (op);
11798 /* If the high bit is zero, the value is the first 1 bit we find
11800 if ((val & 0x80000000) == 0)
11802 gcc_assert (val & 0xffffffff);
11805 while (((val <<= 1) & 0x80000000) == 0)
11810 /* If the high bit is set and the low bit is not, or the mask is all
11811 1's, the value is zero. */
11812 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11815 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11818 while (((val >>= 1) & 1) != 0)
11825 extract_ME (rtx op)
11828 unsigned long val = INT_LOWPART (op);
11830 /* If the low bit is zero, the value is the first 1 bit we find from
11832 if ((val & 1) == 0)
11834 gcc_assert (val & 0xffffffff);
11837 while (((val >>= 1) & 1) == 0)
11843 /* If the low bit is set and the high bit is not, or the mask is all
11844 1's, the value is 31. */
11845 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11848 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11851 while (((val <<= 1) & 0x80000000) != 0)
11857 /* Locate some local-dynamic symbol still in use by this function
11858 so that we can print its name in some tls_ld pattern. */
11860 static const char *
11861 rs6000_get_some_local_dynamic_name (void)
11865 if (cfun->machine->some_ld_name)
11866 return cfun->machine->some_ld_name;
11868 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11870 && for_each_rtx (&PATTERN (insn),
11871 rs6000_get_some_local_dynamic_name_1, 0))
11872 return cfun->machine->some_ld_name;
11874 gcc_unreachable ();
11877 /* Helper function for rs6000_get_some_local_dynamic_name. */
11880 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11884 if (GET_CODE (x) == SYMBOL_REF)
11886 const char *str = XSTR (x, 0);
11887 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11889 cfun->machine->some_ld_name = str;
11897 /* Write out a function code label. */
11900 rs6000_output_function_entry (FILE *file, const char *fname)
11902 if (fname[0] != '.')
11904 switch (DEFAULT_ABI)
11907 gcc_unreachable ();
11913 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11922 RS6000_OUTPUT_BASENAME (file, fname);
11924 assemble_name (file, fname);
11927 /* Print an operand. Recognize special options, documented below. */
11930 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11931 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11933 #define SMALL_DATA_RELOC "sda21"
11934 #define SMALL_DATA_REG 0
11938 print_operand (FILE *file, rtx x, int code)
11942 unsigned HOST_WIDE_INT uval;
11947 /* Write out an instruction after the call which may be replaced
11948 with glue code by the loader. This depends on the AIX version. */
11949 asm_fprintf (file, RS6000_CALL_GLUE);
11952 /* %a is output_address. */
11955 /* If X is a constant integer whose low-order 5 bits are zero,
11956 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11957 in the AIX assembler where "sri" with a zero shift count
11958 writes a trash instruction. */
11959 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11966 /* If constant, low-order 16 bits of constant, unsigned.
11967 Otherwise, write normally. */
11969 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11971 print_operand (file, x, 0);
11975 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11976 for 64-bit mask direction. */
11977 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11980 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11984 /* X is a CR register. Print the number of the GT bit of the CR. */
11985 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11986 output_operand_lossage ("invalid %%E value");
11988 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11992 /* Like 'J' but get to the GT bit only. */
11993 gcc_assert (GET_CODE (x) == REG);
11995 /* Bit 1 is GT bit. */
11996 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11998 /* Add one for shift count in rlinm for scc. */
11999 fprintf (file, "%d", i + 1);
12003 /* X is a CR register. Print the number of the EQ bit of the CR */
12004 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
12005 output_operand_lossage ("invalid %%E value");
12007 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
12011 /* X is a CR register. Print the shift count needed to move it
12012 to the high-order four bits. */
12013 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
12014 output_operand_lossage ("invalid %%f value");
12016 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
12020 /* Similar, but print the count for the rotate in the opposite
12022 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
12023 output_operand_lossage ("invalid %%F value");
12025 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
12029 /* X is a constant integer. If it is negative, print "m",
12030 otherwise print "z". This is to make an aze or ame insn. */
12031 if (GET_CODE (x) != CONST_INT)
12032 output_operand_lossage ("invalid %%G value");
12033 else if (INTVAL (x) >= 0)
12040 /* If constant, output low-order five bits. Otherwise, write
12043 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
12045 print_operand (file, x, 0);
12049 /* If constant, output low-order six bits. Otherwise, write
12052 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
12054 print_operand (file, x, 0);
12058 /* Print `i' if this is a constant, else nothing. */
12064 /* Write the bit number in CCR for jump. */
12065 i = ccr_bit (x, 0);
12067 output_operand_lossage ("invalid %%j code");
12069 fprintf (file, "%d", i);
12073 /* Similar, but add one for shift count in rlinm for scc and pass
12074 scc flag to `ccr_bit'. */
12075 i = ccr_bit (x, 1);
12077 output_operand_lossage ("invalid %%J code");
12079 /* If we want bit 31, write a shift count of zero, not 32. */
12080 fprintf (file, "%d", i == 31 ? 0 : i + 1);
12084 /* X must be a constant. Write the 1's complement of the
12087 output_operand_lossage ("invalid %%k value");
12089 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
12093 /* X must be a symbolic constant on ELF. Write an
12094 expression suitable for an 'addi' that adds in the low 16
12095 bits of the MEM. */
12096 if (GET_CODE (x) != CONST)
12098 print_operand_address (file, x);
12099 fputs ("@l", file);
12103 if (GET_CODE (XEXP (x, 0)) != PLUS
12104 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
12105 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
12106 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
12107 output_operand_lossage ("invalid %%K value");
12108 print_operand_address (file, XEXP (XEXP (x, 0), 0));
12109 fputs ("@l", file);
12110 /* For GNU as, there must be a non-alphanumeric character
12111 between 'l' and the number. The '-' is added by
12112 print_operand() already. */
12113 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
12115 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
12119 /* %l is output_asm_label. */
12122 /* Write second word of DImode or DFmode reference. Works on register
12123 or non-indexed memory only. */
12124 if (GET_CODE (x) == REG)
12125 fputs (reg_names[REGNO (x) + 1], file);
12126 else if (GET_CODE (x) == MEM)
12128 /* Handle possible auto-increment. Since it is pre-increment and
12129 we have already done it, we can just use an offset of word. */
12130 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12131 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12132 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
12134 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12135 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
12138 output_address (XEXP (adjust_address_nv (x, SImode,
12142 if (small_data_operand (x, GET_MODE (x)))
12143 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12144 reg_names[SMALL_DATA_REG]);
12149 /* MB value for a mask operand. */
12150 if (! mask_operand (x, SImode))
12151 output_operand_lossage ("invalid %%m value");
12153 fprintf (file, "%d", extract_MB (x));
12157 /* ME value for a mask operand. */
12158 if (! mask_operand (x, SImode))
12159 output_operand_lossage ("invalid %%M value");
12161 fprintf (file, "%d", extract_ME (x));
12164 /* %n outputs the negative of its operand. */
12167 /* Write the number of elements in the vector times 4. */
12168 if (GET_CODE (x) != PARALLEL)
12169 output_operand_lossage ("invalid %%N value");
12171 fprintf (file, "%d", XVECLEN (x, 0) * 4);
12175 /* Similar, but subtract 1 first. */
12176 if (GET_CODE (x) != PARALLEL)
12177 output_operand_lossage ("invalid %%O value");
12179 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
12183 /* X is a CONST_INT that is a power of two. Output the logarithm. */
12185 || INT_LOWPART (x) < 0
12186 || (i = exact_log2 (INT_LOWPART (x))) < 0)
12187 output_operand_lossage ("invalid %%p value");
12189 fprintf (file, "%d", i);
12193 /* The operand must be an indirect memory reference. The result
12194 is the register name. */
12195 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
12196 || REGNO (XEXP (x, 0)) >= 32)
12197 output_operand_lossage ("invalid %%P value");
12199 fputs (reg_names[REGNO (XEXP (x, 0))], file);
12203 /* This outputs the logical code corresponding to a boolean
12204 expression. The expression may have one or both operands
12205 negated (if one, only the first one). For condition register
12206 logical operations, it will also treat the negated
12207 CR codes as NOTs, but not handle NOTs of them. */
12209 const char *const *t = 0;
12211 enum rtx_code code = GET_CODE (x);
12212 static const char * const tbl[3][3] = {
12213 { "and", "andc", "nor" },
12214 { "or", "orc", "nand" },
12215 { "xor", "eqv", "xor" } };
12219 else if (code == IOR)
12221 else if (code == XOR)
12224 output_operand_lossage ("invalid %%q value");
12226 if (GET_CODE (XEXP (x, 0)) != NOT)
12230 if (GET_CODE (XEXP (x, 1)) == NOT)
12248 /* X is a CR register. Print the mask for `mtcrf'. */
12249 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
12250 output_operand_lossage ("invalid %%R value");
12252 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
12256 /* Low 5 bits of 32 - value */
12258 output_operand_lossage ("invalid %%s value");
12260 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
12264 /* PowerPC64 mask position. All 0's is excluded.
12265 CONST_INT 32-bit mask is considered sign-extended so any
12266 transition must occur within the CONST_INT, not on the boundary. */
12267 if (! mask64_operand (x, DImode))
12268 output_operand_lossage ("invalid %%S value");
12270 uval = INT_LOWPART (x);
12272 if (uval & 1) /* Clear Left */
12274 #if HOST_BITS_PER_WIDE_INT > 64
12275 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12279 else /* Clear Right */
12282 #if HOST_BITS_PER_WIDE_INT > 64
12283 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
12289 gcc_assert (i >= 0);
12290 fprintf (file, "%d", i);
12294 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12295 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
12297 /* Bit 3 is OV bit. */
12298 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
12300 /* If we want bit 31, write a shift count of zero, not 32. */
12301 fprintf (file, "%d", i == 31 ? 0 : i + 1);
12305 /* Print the symbolic name of a branch target register. */
12306 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
12307 && REGNO (x) != CTR_REGNO))
12308 output_operand_lossage ("invalid %%T value");
12309 else if (REGNO (x) == LR_REGNO)
12310 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
12312 fputs ("ctr", file);
12316 /* High-order 16 bits of constant for use in unsigned operand. */
12318 output_operand_lossage ("invalid %%u value");
12320 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12321 (INT_LOWPART (x) >> 16) & 0xffff);
12325 /* High-order 16 bits of constant for use in signed operand. */
12327 output_operand_lossage ("invalid %%v value");
12329 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
12330 (INT_LOWPART (x) >> 16) & 0xffff);
12334 /* Print `u' if this has an auto-increment or auto-decrement. */
12335 if (GET_CODE (x) == MEM
12336 && (GET_CODE (XEXP (x, 0)) == PRE_INC
12337 || GET_CODE (XEXP (x, 0)) == PRE_DEC
12338 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
12343 /* Print the trap code for this operand. */
12344 switch (GET_CODE (x))
12347 fputs ("eq", file); /* 4 */
12350 fputs ("ne", file); /* 24 */
12353 fputs ("lt", file); /* 16 */
12356 fputs ("le", file); /* 20 */
12359 fputs ("gt", file); /* 8 */
12362 fputs ("ge", file); /* 12 */
12365 fputs ("llt", file); /* 2 */
12368 fputs ("lle", file); /* 6 */
12371 fputs ("lgt", file); /* 1 */
12374 fputs ("lge", file); /* 5 */
12377 gcc_unreachable ();
12382 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12385 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
12386 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
12388 print_operand (file, x, 0);
12392 /* MB value for a PowerPC64 rldic operand. */
12393 val = (GET_CODE (x) == CONST_INT
12394 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
12399 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
12400 if ((val <<= 1) < 0)
12403 #if HOST_BITS_PER_WIDE_INT == 32
12404 if (GET_CODE (x) == CONST_INT && i >= 0)
12405 i += 32; /* zero-extend high-part was all 0's */
12406 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
12408 val = CONST_DOUBLE_LOW (x);
12414 for ( ; i < 64; i++)
12415 if ((val <<= 1) < 0)
12420 fprintf (file, "%d", i + 1);
12424 if (GET_CODE (x) == MEM
12425 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
12426 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
12427 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
12432 /* Like 'L', for third word of TImode */
12433 if (GET_CODE (x) == REG)
12434 fputs (reg_names[REGNO (x) + 2], file);
12435 else if (GET_CODE (x) == MEM)
12437 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12438 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12439 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12440 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12441 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
12443 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
12444 if (small_data_operand (x, GET_MODE (x)))
12445 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12446 reg_names[SMALL_DATA_REG]);
12451 /* X is a SYMBOL_REF. Write out the name preceded by a
12452 period and without any trailing data in brackets. Used for function
12453 names. If we are configured for System V (or the embedded ABI) on
12454 the PowerPC, do not emit the period, since those systems do not use
12455 TOCs and the like. */
12456 gcc_assert (GET_CODE (x) == SYMBOL_REF);
12458 /* Mark the decl as referenced so that cgraph will output the
12460 if (SYMBOL_REF_DECL (x))
12461 mark_decl_referenced (SYMBOL_REF_DECL (x));
12463 /* For macho, check to see if we need a stub. */
12466 const char *name = XSTR (x, 0);
12468 if (MACHOPIC_INDIRECT
12469 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
12470 name = machopic_indirection_name (x, /*stub_p=*/true);
12472 assemble_name (file, name);
12474 else if (!DOT_SYMBOLS)
12475 assemble_name (file, XSTR (x, 0));
12477 rs6000_output_function_entry (file, XSTR (x, 0));
12481 /* Like 'L', for last word of TImode. */
12482 if (GET_CODE (x) == REG)
12483 fputs (reg_names[REGNO (x) + 3], file);
12484 else if (GET_CODE (x) == MEM)
12486 if (GET_CODE (XEXP (x, 0)) == PRE_INC
12487 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
12488 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12489 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12490 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
12492 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
12493 if (small_data_operand (x, GET_MODE (x)))
12494 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12495 reg_names[SMALL_DATA_REG]);
12499 /* Print AltiVec or SPE memory operand. */
12504 gcc_assert (GET_CODE (x) == MEM);
12508 /* Ugly hack because %y is overloaded. */
12509 if ((TARGET_SPE || TARGET_E500_DOUBLE)
12510 && (GET_MODE_SIZE (GET_MODE (x)) == 8
12511 || GET_MODE (x) == TFmode
12512 || GET_MODE (x) == TImode))
12514 /* Handle [reg]. */
12515 if (GET_CODE (tmp) == REG)
12517 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
12520 /* Handle [reg+UIMM]. */
12521 else if (GET_CODE (tmp) == PLUS &&
12522 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
12526 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
12528 x = INTVAL (XEXP (tmp, 1));
12529 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
12533 /* Fall through. Must be [reg+reg]. */
12536 && GET_CODE (tmp) == AND
12537 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
12538 && INTVAL (XEXP (tmp, 1)) == -16)
12539 tmp = XEXP (tmp, 0);
12540 if (GET_CODE (tmp) == REG)
12541 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
12544 if (!GET_CODE (tmp) == PLUS
12545 || !REG_P (XEXP (tmp, 0))
12546 || !REG_P (XEXP (tmp, 1)))
12548 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
12552 if (REGNO (XEXP (tmp, 0)) == 0)
12553 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
12554 reg_names[ REGNO (XEXP (tmp, 0)) ]);
12556 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
12557 reg_names[ REGNO (XEXP (tmp, 1)) ]);
12563 if (GET_CODE (x) == REG)
12564 fprintf (file, "%s", reg_names[REGNO (x)]);
12565 else if (GET_CODE (x) == MEM)
12567 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12568 know the width from the mode. */
12569 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
12570 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
12571 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12572 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
12573 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
12574 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
12575 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
12576 output_address (XEXP (XEXP (x, 0), 1));
12578 output_address (XEXP (x, 0));
12581 output_addr_const (file, x);
12585 assemble_name (file, rs6000_get_some_local_dynamic_name ());
12589 output_operand_lossage ("invalid %%xn code");
12593 /* Print the address of an operand. */
12596 print_operand_address (FILE *file, rtx x)
12598 if (GET_CODE (x) == REG)
12599 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
12600 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
12601 || GET_CODE (x) == LABEL_REF)
12603 output_addr_const (file, x);
12604 if (small_data_operand (x, GET_MODE (x)))
12605 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
12606 reg_names[SMALL_DATA_REG]);
12608 gcc_assert (!TARGET_TOC);
12610 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
12612 gcc_assert (REG_P (XEXP (x, 0)));
12613 if (REGNO (XEXP (x, 0)) == 0)
12614 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
12615 reg_names[ REGNO (XEXP (x, 0)) ]);
12617 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
12618 reg_names[ REGNO (XEXP (x, 1)) ]);
12620 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
12621 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
12622 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
12624 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12625 && CONSTANT_P (XEXP (x, 1)))
12627 output_addr_const (file, XEXP (x, 1));
12628 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12632 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
12633 && CONSTANT_P (XEXP (x, 1)))
12635 fprintf (file, "lo16(");
12636 output_addr_const (file, XEXP (x, 1));
12637 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
12640 else if (legitimate_constant_pool_address_p (x))
12642 output_addr_const (file, XEXP (x, 1));
12643 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
12646 gcc_unreachable ();
12649 /* Implement OUTPUT_ADDR_CONST_EXTRA for address X. */
12652 rs6000_output_addr_const_extra (FILE *file, rtx x)
12654 if (GET_CODE (x) == UNSPEC)
12655 switch (XINT (x, 1))
12657 case UNSPEC_TOCREL:
12658 x = XVECEXP (x, 0, 0);
12659 gcc_assert (GET_CODE (x) == SYMBOL_REF);
12660 output_addr_const (file, x);
12661 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
12664 assemble_name (file, toc_label_name);
12666 else if (TARGET_ELF)
12667 fputs ("@toc", file);
12671 case UNSPEC_MACHOPIC_OFFSET:
12672 output_addr_const (file, XVECEXP (x, 0, 0));
12674 machopic_output_function_base_name (file);
12681 /* Target hook for assembling integer objects. The PowerPC version has
12682 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12683 is defined. It also needs to handle DI-mode objects on 64-bit
12687 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
12689 #ifdef RELOCATABLE_NEEDS_FIXUP
12690 /* Special handling for SI values. */
12691 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
12693 static int recurse = 0;
12695 /* For -mrelocatable, we mark all addresses that need to be fixed up
12696 in the .fixup section. */
12697 if (TARGET_RELOCATABLE
12698 && in_section != toc_section
12699 && in_section != text_section
12700 && !unlikely_text_section_p (in_section)
12702 && GET_CODE (x) != CONST_INT
12703 && GET_CODE (x) != CONST_DOUBLE
12709 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
12711 ASM_OUTPUT_LABEL (asm_out_file, buf);
12712 fprintf (asm_out_file, "\t.long\t(");
12713 output_addr_const (asm_out_file, x);
12714 fprintf (asm_out_file, ")@fixup\n");
12715 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
12716 ASM_OUTPUT_ALIGN (asm_out_file, 2);
12717 fprintf (asm_out_file, "\t.long\t");
12718 assemble_name (asm_out_file, buf);
12719 fprintf (asm_out_file, "\n\t.previous\n");
12723 /* Remove initial .'s to turn a -mcall-aixdesc function
12724 address into the address of the descriptor, not the function
12726 else if (GET_CODE (x) == SYMBOL_REF
12727 && XSTR (x, 0)[0] == '.'
12728 && DEFAULT_ABI == ABI_AIX)
12730 const char *name = XSTR (x, 0);
12731 while (*name == '.')
12734 fprintf (asm_out_file, "\t.long\t%s\n", name);
12738 #endif /* RELOCATABLE_NEEDS_FIXUP */
12739 return default_assemble_integer (x, size, aligned_p);
12742 #ifdef HAVE_GAS_HIDDEN
12743 /* Emit an assembler directive to set symbol visibility for DECL to
12744 VISIBILITY_TYPE. */
12747 rs6000_assemble_visibility (tree decl, int vis)
12749 /* Functions need to have their entry point symbol visibility set as
12750 well as their descriptor symbol visibility. */
12751 if (DEFAULT_ABI == ABI_AIX
12753 && TREE_CODE (decl) == FUNCTION_DECL)
12755 static const char * const visibility_types[] = {
12756 NULL, "internal", "hidden", "protected"
12759 const char *name, *type;
12761 name = ((* targetm.strip_name_encoding)
12762 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
12763 type = visibility_types[vis];
12765 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
12766 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
12769 default_assemble_visibility (decl, vis);
12774 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
12776 /* Reversal of FP compares takes care -- an ordered compare
12777 becomes an unordered compare and vice versa. */
12778 if (mode == CCFPmode
12779 && (!flag_finite_math_only
12780 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
12781 || code == UNEQ || code == LTGT))
12782 return reverse_condition_maybe_unordered (code);
12784 return reverse_condition (code);
12787 /* Generate a compare for CODE. Return a brand-new rtx that
12788 represents the result of the compare. */
12791 rs6000_generate_compare (enum rtx_code code)
12793 enum machine_mode comp_mode;
12794 rtx compare_result;
12796 if (rs6000_compare_fp_p)
12797 comp_mode = CCFPmode;
12798 else if (code == GTU || code == LTU
12799 || code == GEU || code == LEU)
12800 comp_mode = CCUNSmode;
12801 else if ((code == EQ || code == NE)
12802 && GET_CODE (rs6000_compare_op0) == SUBREG
12803 && GET_CODE (rs6000_compare_op1) == SUBREG
12804 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12805 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12806 /* These are unsigned values, perhaps there will be a later
12807 ordering compare that can be shared with this one.
12808 Unfortunately we cannot detect the signedness of the operands
12809 for non-subregs. */
12810 comp_mode = CCUNSmode;
12812 comp_mode = CCmode;
12814 /* First, the compare. */
12815 compare_result = gen_reg_rtx (comp_mode);
12817 /* E500 FP compare instructions on the GPRs. Yuck! */
12818 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12819 && rs6000_compare_fp_p)
12821 rtx cmp, or_result, compare_result2;
12822 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12824 if (op_mode == VOIDmode)
12825 op_mode = GET_MODE (rs6000_compare_op1);
12827 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12828 This explains the following mess. */
12832 case EQ: case UNEQ: case NE: case LTGT:
12836 cmp = (flag_finite_math_only && !flag_trapping_math)
12837 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12838 rs6000_compare_op1)
12839 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12840 rs6000_compare_op1);
12844 cmp = (flag_finite_math_only && !flag_trapping_math)
12845 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12846 rs6000_compare_op1)
12847 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12848 rs6000_compare_op1);
12852 cmp = (flag_finite_math_only && !flag_trapping_math)
12853 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12854 rs6000_compare_op1)
12855 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12856 rs6000_compare_op1);
12860 gcc_unreachable ();
12864 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12868 cmp = (flag_finite_math_only && !flag_trapping_math)
12869 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12870 rs6000_compare_op1)
12871 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12872 rs6000_compare_op1);
12876 cmp = (flag_finite_math_only && !flag_trapping_math)
12877 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12878 rs6000_compare_op1)
12879 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12880 rs6000_compare_op1);
12884 cmp = (flag_finite_math_only && !flag_trapping_math)
12885 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12886 rs6000_compare_op1)
12887 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12888 rs6000_compare_op1);
12892 gcc_unreachable ();
12896 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12900 cmp = (flag_finite_math_only && !flag_trapping_math)
12901 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12902 rs6000_compare_op1)
12903 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12904 rs6000_compare_op1);
12908 cmp = (flag_finite_math_only && !flag_trapping_math)
12909 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12910 rs6000_compare_op1)
12911 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12912 rs6000_compare_op1);
12916 cmp = (flag_finite_math_only && !flag_trapping_math)
12917 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12918 rs6000_compare_op1)
12919 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12920 rs6000_compare_op1);
12924 gcc_unreachable ();
12928 gcc_unreachable ();
12931 /* Synthesize LE and GE from LT/GT || EQ. */
12932 if (code == LE || code == GE || code == LEU || code == GEU)
12938 case LE: code = LT; break;
12939 case GE: code = GT; break;
12940 case LEU: code = LT; break;
12941 case GEU: code = GT; break;
12942 default: gcc_unreachable ();
12945 compare_result2 = gen_reg_rtx (CCFPmode);
12951 cmp = (flag_finite_math_only && !flag_trapping_math)
12952 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12953 rs6000_compare_op1)
12954 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12955 rs6000_compare_op1);
12959 cmp = (flag_finite_math_only && !flag_trapping_math)
12960 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12961 rs6000_compare_op1)
12962 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12963 rs6000_compare_op1);
12967 cmp = (flag_finite_math_only && !flag_trapping_math)
12968 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12969 rs6000_compare_op1)
12970 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12971 rs6000_compare_op1);
12975 gcc_unreachable ();
12979 /* OR them together. */
12980 or_result = gen_reg_rtx (CCFPmode);
12981 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12983 compare_result = or_result;
12988 if (code == NE || code == LTGT)
12998 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12999 CLOBBERs to match cmptf_internal2 pattern. */
13000 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
13001 && GET_MODE (rs6000_compare_op0) == TFmode
13002 && !TARGET_IEEEQUAD
13003 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
13004 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13006 gen_rtx_SET (VOIDmode,
13008 gen_rtx_COMPARE (comp_mode,
13009 rs6000_compare_op0,
13010 rs6000_compare_op1)),
13011 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13012 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13013 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13014 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13015 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13016 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13017 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
13018 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
13019 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
13020 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
13022 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
13023 comp_mode = CCEQmode;
13024 compare_result = gen_reg_rtx (CCEQmode);
13026 emit_insn (gen_stack_protect_testdi (compare_result,
13027 rs6000_compare_op0, op1));
13029 emit_insn (gen_stack_protect_testsi (compare_result,
13030 rs6000_compare_op0, op1));
13033 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
13034 gen_rtx_COMPARE (comp_mode,
13035 rs6000_compare_op0,
13036 rs6000_compare_op1)));
13039 /* Some kinds of FP comparisons need an OR operation;
13040 under flag_finite_math_only we don't bother. */
13041 if (rs6000_compare_fp_p
13042 && !flag_finite_math_only
13043 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
13044 && (code == LE || code == GE
13045 || code == UNEQ || code == LTGT
13046 || code == UNGT || code == UNLT))
13048 enum rtx_code or1, or2;
13049 rtx or1_rtx, or2_rtx, compare2_rtx;
13050 rtx or_result = gen_reg_rtx (CCEQmode);
13054 case LE: or1 = LT; or2 = EQ; break;
13055 case GE: or1 = GT; or2 = EQ; break;
13056 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
13057 case LTGT: or1 = LT; or2 = GT; break;
13058 case UNGT: or1 = UNORDERED; or2 = GT; break;
13059 case UNLT: or1 = UNORDERED; or2 = LT; break;
13060 default: gcc_unreachable ();
13062 validate_condition_mode (or1, comp_mode);
13063 validate_condition_mode (or2, comp_mode);
13064 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
13065 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
13066 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
13067 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
13069 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
13071 compare_result = or_result;
13075 validate_condition_mode (code, GET_MODE (compare_result));
13077 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
13081 /* Emit the RTL for an sCOND pattern. */
13084 rs6000_emit_sCOND (enum rtx_code code, rtx result)
13087 enum machine_mode op_mode;
13088 enum rtx_code cond_code;
13090 condition_rtx = rs6000_generate_compare (code);
13091 cond_code = GET_CODE (condition_rtx);
13093 if (rs6000_compare_fp_p
13094 && !TARGET_FPRS && TARGET_HARD_FLOAT)
13098 PUT_MODE (condition_rtx, SImode);
13099 t = XEXP (condition_rtx, 0);
13101 gcc_assert (cond_code == NE || cond_code == EQ);
13103 if (cond_code == NE)
13104 emit_insn (gen_e500_flip_gt_bit (t, t));
13106 emit_insn (gen_move_from_CR_gt_bit (result, t));
13110 if (cond_code == NE
13111 || cond_code == GE || cond_code == LE
13112 || cond_code == GEU || cond_code == LEU
13113 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
13115 rtx not_result = gen_reg_rtx (CCEQmode);
13116 rtx not_op, rev_cond_rtx;
13117 enum machine_mode cc_mode;
13119 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
13121 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
13122 SImode, XEXP (condition_rtx, 0), const0_rtx);
13123 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
13124 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
13125 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
13128 op_mode = GET_MODE (rs6000_compare_op0);
13129 if (op_mode == VOIDmode)
13130 op_mode = GET_MODE (rs6000_compare_op1);
13132 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
13134 PUT_MODE (condition_rtx, DImode);
13135 convert_move (result, condition_rtx, 0);
13139 PUT_MODE (condition_rtx, SImode);
13140 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
13144 /* Emit a branch of kind CODE to location LOC. */
13147 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
13149 rtx condition_rtx, loc_ref;
13151 condition_rtx = rs6000_generate_compare (code);
13152 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
13153 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
13154 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
13155 loc_ref, pc_rtx)));
13158 /* Return the string to output a conditional branch to LABEL, which is
13159 the operand number of the label, or -1 if the branch is really a
13160 conditional return.
13162 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
13163 condition code register and its mode specifies what kind of
13164 comparison we made.
13166 REVERSED is nonzero if we should reverse the sense of the comparison.
13168 INSN is the insn. */
13171 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
13173 static char string[64];
13174 enum rtx_code code = GET_CODE (op);
13175 rtx cc_reg = XEXP (op, 0);
13176 enum machine_mode mode = GET_MODE (cc_reg);
13177 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
13178 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
13179 int really_reversed = reversed ^ need_longbranch;
13185 validate_condition_mode (code, mode);
13187 /* Work out which way this really branches. We could use
13188 reverse_condition_maybe_unordered here always but this
13189 makes the resulting assembler clearer. */
13190 if (really_reversed)
13192 /* Reversal of FP compares takes care -- an ordered compare
13193 becomes an unordered compare and vice versa. */
13194 if (mode == CCFPmode)
13195 code = reverse_condition_maybe_unordered (code);
13197 code = reverse_condition (code);
13200 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
13202 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
13207 /* Opposite of GT. */
13216 gcc_unreachable ();
13222 /* Not all of these are actually distinct opcodes, but
13223 we distinguish them for clarity of the resulting assembler. */
13224 case NE: case LTGT:
13225 ccode = "ne"; break;
13226 case EQ: case UNEQ:
13227 ccode = "eq"; break;
13229 ccode = "ge"; break;
13230 case GT: case GTU: case UNGT:
13231 ccode = "gt"; break;
13233 ccode = "le"; break;
13234 case LT: case LTU: case UNLT:
13235 ccode = "lt"; break;
13236 case UNORDERED: ccode = "un"; break;
13237 case ORDERED: ccode = "nu"; break;
13238 case UNGE: ccode = "nl"; break;
13239 case UNLE: ccode = "ng"; break;
13241 gcc_unreachable ();
13244 /* Maybe we have a guess as to how likely the branch is.
13245 The old mnemonics don't have a way to specify this information. */
13247 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
13248 if (note != NULL_RTX)
13250 /* PROB is the difference from 50%. */
13251 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
13253 /* Only hint for highly probable/improbable branches on newer
13254 cpus as static prediction overrides processor dynamic
13255 prediction. For older cpus we may as well always hint, but
13256 assume not taken for branches that are very close to 50% as a
13257 mispredicted taken branch is more expensive than a
13258 mispredicted not-taken branch. */
13259 if (rs6000_always_hint
13260 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
13261 && br_prob_note_reliable_p (note)))
13263 if (abs (prob) > REG_BR_PROB_BASE / 20
13264 && ((prob > 0) ^ need_longbranch))
13272 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
13274 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
13276 /* We need to escape any '%' characters in the reg_names string.
13277 Assume they'd only be the first character.... */
13278 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
13280 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
13284 /* If the branch distance was too far, we may have to use an
13285 unconditional branch to go the distance. */
13286 if (need_longbranch)
13287 s += sprintf (s, ",$+8\n\tb %s", label);
13289 s += sprintf (s, ",%s", label);
13295 /* Return the string to flip the GT bit on a CR. */
13297 output_e500_flip_gt_bit (rtx dst, rtx src)
13299 static char string[64];
13302 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
13303 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
13306 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
13307 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
13309 sprintf (string, "crnot %d,%d", a, b);
13313 /* Return insn index for the vector compare instruction for given CODE,
13314 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13318 get_vec_cmp_insn (enum rtx_code code,
13319 enum machine_mode dest_mode,
13320 enum machine_mode op_mode)
13322 if (!TARGET_ALTIVEC)
13323 return INSN_NOT_AVAILABLE;
13328 if (dest_mode == V16QImode && op_mode == V16QImode)
13329 return UNSPEC_VCMPEQUB;
13330 if (dest_mode == V8HImode && op_mode == V8HImode)
13331 return UNSPEC_VCMPEQUH;
13332 if (dest_mode == V4SImode && op_mode == V4SImode)
13333 return UNSPEC_VCMPEQUW;
13334 if (dest_mode == V4SImode && op_mode == V4SFmode)
13335 return UNSPEC_VCMPEQFP;
13338 if (dest_mode == V4SImode && op_mode == V4SFmode)
13339 return UNSPEC_VCMPGEFP;
13341 if (dest_mode == V16QImode && op_mode == V16QImode)
13342 return UNSPEC_VCMPGTSB;
13343 if (dest_mode == V8HImode && op_mode == V8HImode)
13344 return UNSPEC_VCMPGTSH;
13345 if (dest_mode == V4SImode && op_mode == V4SImode)
13346 return UNSPEC_VCMPGTSW;
13347 if (dest_mode == V4SImode && op_mode == V4SFmode)
13348 return UNSPEC_VCMPGTFP;
13351 if (dest_mode == V16QImode && op_mode == V16QImode)
13352 return UNSPEC_VCMPGTUB;
13353 if (dest_mode == V8HImode && op_mode == V8HImode)
13354 return UNSPEC_VCMPGTUH;
13355 if (dest_mode == V4SImode && op_mode == V4SImode)
13356 return UNSPEC_VCMPGTUW;
13361 return INSN_NOT_AVAILABLE;
13364 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13365 DMODE is expected destination mode. This is a recursive function. */
13368 rs6000_emit_vector_compare (enum rtx_code rcode,
13370 enum machine_mode dmode)
13374 enum machine_mode dest_mode;
13375 enum machine_mode op_mode = GET_MODE (op1);
13377 gcc_assert (TARGET_ALTIVEC);
13378 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
13380 /* Floating point vector compare instructions uses destination V4SImode.
13381 Move destination to appropriate mode later. */
13382 if (dmode == V4SFmode)
13383 dest_mode = V4SImode;
13387 mask = gen_reg_rtx (dest_mode);
13388 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13390 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
13392 bool swap_operands = false;
13393 bool try_again = false;
13398 swap_operands = true;
13403 swap_operands = true;
13411 /* Invert condition and try again.
13412 e.g., A != B becomes ~(A==B). */
13414 enum rtx_code rev_code;
13415 enum insn_code nor_code;
13418 rev_code = reverse_condition_maybe_unordered (rcode);
13419 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
13422 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
13423 gcc_assert (nor_code != CODE_FOR_nothing);
13424 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
13426 if (dmode != dest_mode)
13428 rtx temp = gen_reg_rtx (dest_mode);
13429 convert_move (temp, mask, 0);
13439 /* Try GT/GTU/LT/LTU OR EQ */
13442 enum insn_code ior_code;
13443 enum rtx_code new_code;
13464 gcc_unreachable ();
13467 c_rtx = rs6000_emit_vector_compare (new_code,
13468 op0, op1, dest_mode);
13469 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
13472 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
13473 gcc_assert (ior_code != CODE_FOR_nothing);
13474 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
13475 if (dmode != dest_mode)
13477 rtx temp = gen_reg_rtx (dest_mode);
13478 convert_move (temp, mask, 0);
13485 gcc_unreachable ();
13490 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
13491 /* You only get two chances. */
13492 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
13504 emit_insn (gen_rtx_SET (VOIDmode, mask,
13505 gen_rtx_UNSPEC (dest_mode,
13506 gen_rtvec (2, op0, op1),
13508 if (dmode != dest_mode)
13510 rtx temp = gen_reg_rtx (dest_mode);
13511 convert_move (temp, mask, 0);
13517 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13518 valid insn doesn exist for given mode. */
13521 get_vsel_insn (enum machine_mode mode)
13526 return UNSPEC_VSEL4SI;
13529 return UNSPEC_VSEL4SF;
13532 return UNSPEC_VSEL8HI;
13535 return UNSPEC_VSEL16QI;
13538 return INSN_NOT_AVAILABLE;
13541 return INSN_NOT_AVAILABLE;
13544 /* Emit vector select insn where DEST is destination using
13545 operands OP1, OP2 and MASK. */
13548 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
13551 enum machine_mode dest_mode = GET_MODE (dest);
13552 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
13554 temp = gen_reg_rtx (dest_mode);
13556 /* For each vector element, select op1 when mask is 1 otherwise
13558 t = gen_rtx_SET (VOIDmode, temp,
13559 gen_rtx_UNSPEC (dest_mode,
13560 gen_rtvec (3, op2, op1, mask),
13563 emit_move_insn (dest, temp);
13567 /* Emit vector conditional expression.
13568 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13569 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13572 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
13573 rtx cond, rtx cc_op0, rtx cc_op1)
13575 enum machine_mode dest_mode = GET_MODE (dest);
13576 enum rtx_code rcode = GET_CODE (cond);
13579 if (!TARGET_ALTIVEC)
13582 /* Get the vector mask for the given relational operations. */
13583 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
13585 rs6000_emit_vector_select (dest, op1, op2, mask);
13590 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13591 operands of the last comparison is nonzero/true, FALSE_COND if it
13592 is zero/false. Return 0 if the hardware has no such operation. */
13595 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13597 enum rtx_code code = GET_CODE (op);
13598 rtx op0 = rs6000_compare_op0;
13599 rtx op1 = rs6000_compare_op1;
13600 REAL_VALUE_TYPE c1;
13601 enum machine_mode compare_mode = GET_MODE (op0);
13602 enum machine_mode result_mode = GET_MODE (dest);
13604 bool is_against_zero;
13606 /* These modes should always match. */
13607 if (GET_MODE (op1) != compare_mode
13608 /* In the isel case however, we can use a compare immediate, so
13609 op1 may be a small constant. */
13610 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
13612 if (GET_MODE (true_cond) != result_mode)
13614 if (GET_MODE (false_cond) != result_mode)
13617 /* First, work out if the hardware can do this at all, or
13618 if it's too slow.... */
13619 if (! rs6000_compare_fp_p)
13622 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
13625 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
13626 && SCALAR_FLOAT_MODE_P (compare_mode))
13629 is_against_zero = op1 == CONST0_RTX (compare_mode);
13631 /* A floating-point subtract might overflow, underflow, or produce
13632 an inexact result, thus changing the floating-point flags, so it
13633 can't be generated if we care about that. It's safe if one side
13634 of the construct is zero, since then no subtract will be
13636 if (SCALAR_FLOAT_MODE_P (compare_mode)
13637 && flag_trapping_math && ! is_against_zero)
13640 /* Eliminate half of the comparisons by switching operands, this
13641 makes the remaining code simpler. */
13642 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
13643 || code == LTGT || code == LT || code == UNLE)
13645 code = reverse_condition_maybe_unordered (code);
13647 true_cond = false_cond;
13651 /* UNEQ and LTGT take four instructions for a comparison with zero,
13652 it'll probably be faster to use a branch here too. */
13653 if (code == UNEQ && HONOR_NANS (compare_mode))
13656 if (GET_CODE (op1) == CONST_DOUBLE)
13657 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
13659 /* We're going to try to implement comparisons by performing
13660 a subtract, then comparing against zero. Unfortunately,
13661 Inf - Inf is NaN which is not zero, and so if we don't
13662 know that the operand is finite and the comparison
13663 would treat EQ different to UNORDERED, we can't do it. */
13664 if (HONOR_INFINITIES (compare_mode)
13665 && code != GT && code != UNGE
13666 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
13667 /* Constructs of the form (a OP b ? a : b) are safe. */
13668 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
13669 || (! rtx_equal_p (op0, true_cond)
13670 && ! rtx_equal_p (op1, true_cond))))
13673 /* At this point we know we can use fsel. */
13675 /* Reduce the comparison to a comparison against zero. */
13676 if (! is_against_zero)
13678 temp = gen_reg_rtx (compare_mode);
13679 emit_insn (gen_rtx_SET (VOIDmode, temp,
13680 gen_rtx_MINUS (compare_mode, op0, op1)));
13682 op1 = CONST0_RTX (compare_mode);
13685 /* If we don't care about NaNs we can reduce some of the comparisons
13686 down to faster ones. */
13687 if (! HONOR_NANS (compare_mode))
13693 true_cond = false_cond;
13706 /* Now, reduce everything down to a GE. */
13713 temp = gen_reg_rtx (compare_mode);
13714 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13719 temp = gen_reg_rtx (compare_mode);
13720 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
13725 temp = gen_reg_rtx (compare_mode);
13726 emit_insn (gen_rtx_SET (VOIDmode, temp,
13727 gen_rtx_NEG (compare_mode,
13728 gen_rtx_ABS (compare_mode, op0))));
13733 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13734 temp = gen_reg_rtx (result_mode);
13735 emit_insn (gen_rtx_SET (VOIDmode, temp,
13736 gen_rtx_IF_THEN_ELSE (result_mode,
13737 gen_rtx_GE (VOIDmode,
13739 true_cond, false_cond)));
13740 false_cond = true_cond;
13743 temp = gen_reg_rtx (compare_mode);
13744 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13749 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13750 temp = gen_reg_rtx (result_mode);
13751 emit_insn (gen_rtx_SET (VOIDmode, temp,
13752 gen_rtx_IF_THEN_ELSE (result_mode,
13753 gen_rtx_GE (VOIDmode,
13755 true_cond, false_cond)));
13756 true_cond = false_cond;
13759 temp = gen_reg_rtx (compare_mode);
13760 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13765 gcc_unreachable ();
13768 emit_insn (gen_rtx_SET (VOIDmode, dest,
13769 gen_rtx_IF_THEN_ELSE (result_mode,
13770 gen_rtx_GE (VOIDmode,
13772 true_cond, false_cond)));
13776 /* Same as above, but for ints (isel). */
13779 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13781 rtx condition_rtx, cr;
13783 /* All isel implementations thus far are 32-bits. */
13784 if (GET_MODE (rs6000_compare_op0) != SImode)
13787 /* We still have to do the compare, because isel doesn't do a
13788 compare, it just looks at the CRx bits set by a previous compare
13790 condition_rtx = rs6000_generate_compare (GET_CODE (op));
13791 cr = XEXP (condition_rtx, 0);
13793 if (GET_MODE (cr) == CCmode)
13794 emit_insn (gen_isel_signed (dest, condition_rtx,
13795 true_cond, false_cond, cr));
13797 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13798 true_cond, false_cond, cr));
13804 output_isel (rtx *operands)
13806 enum rtx_code code;
13808 code = GET_CODE (operands[1]);
13809 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13811 PUT_CODE (operands[1], reverse_condition (code));
13812 return "isel %0,%3,%2,%j1";
13815 return "isel %0,%2,%3,%j1";
13819 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13821 enum machine_mode mode = GET_MODE (op0);
13825 if (code == SMAX || code == SMIN)
13830 if (code == SMAX || code == UMAX)
13831 target = emit_conditional_move (dest, c, op0, op1, mode,
13832 op0, op1, mode, 0);
13834 target = emit_conditional_move (dest, c, op0, op1, mode,
13835 op1, op0, mode, 0);
13836 gcc_assert (target);
13837 if (target != dest)
13838 emit_move_insn (dest, target);
13841 /* Emit instructions to perform a load-reserved/store-conditional operation.
13842 The operation performed is an atomic
13843 (set M (CODE:MODE M OP))
13844 If not NULL, BEFORE is atomically set to M before the operation, and
13845 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13846 If SYNC_P then a memory barrier is emitted before the operation.
13847 Either OP or M may be wrapped in a NOT operation. */
13850 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13851 rtx m, rtx op, rtx before_param, rtx after_param,
13854 enum machine_mode used_mode;
13855 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13858 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13859 rtx shift = NULL_RTX;
13862 emit_insn (gen_lwsync ());
13866 /* If this is smaller than SImode, we'll have to use SImode with
13868 if (mode == QImode || mode == HImode)
13872 if (MEM_ALIGN (used_m) >= 32)
13875 if (BYTES_BIG_ENDIAN)
13876 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13878 shift = GEN_INT (ishift);
13879 used_m = change_address (used_m, SImode, 0);
13883 rtx addrSI, aligned_addr;
13884 int shift_mask = mode == QImode ? 0x18 : 0x10;
13886 addrSI = gen_lowpart_common (SImode,
13887 force_reg (Pmode, XEXP (used_m, 0)));
13888 addrSI = force_reg (SImode, addrSI);
13889 shift = gen_reg_rtx (SImode);
13891 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13892 GEN_INT (shift_mask)));
13893 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13895 aligned_addr = expand_binop (Pmode, and_optab,
13897 GEN_INT (-4), NULL_RTX,
13898 1, OPTAB_LIB_WIDEN);
13899 used_m = change_address (used_m, SImode, aligned_addr);
13900 set_mem_align (used_m, 32);
13902 /* It's safe to keep the old alias set of USED_M, because
13903 the operation is atomic and only affects the original
13907 if (GET_CODE (op) == NOT)
13909 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13910 oldop = gen_rtx_NOT (SImode, oldop);
13913 oldop = lowpart_subreg (SImode, op, mode);
13919 newop = expand_binop (SImode, and_optab,
13920 oldop, GEN_INT (imask), NULL_RTX,
13921 1, OPTAB_LIB_WIDEN);
13922 emit_insn (gen_ashlsi3 (newop, newop, shift));
13925 case NOT: /* NAND */
13926 newop = expand_binop (SImode, ior_optab,
13927 oldop, GEN_INT (~imask), NULL_RTX,
13928 1, OPTAB_LIB_WIDEN);
13929 emit_insn (gen_rotlsi3 (newop, newop, shift));
13933 newop = expand_binop (SImode, ior_optab,
13934 oldop, GEN_INT (~imask), NULL_RTX,
13935 1, OPTAB_LIB_WIDEN);
13936 emit_insn (gen_rotlsi3 (newop, newop, shift));
13944 newop = expand_binop (SImode, and_optab,
13945 oldop, GEN_INT (imask), NULL_RTX,
13946 1, OPTAB_LIB_WIDEN);
13947 emit_insn (gen_ashlsi3 (newop, newop, shift));
13949 mask = gen_reg_rtx (SImode);
13950 emit_move_insn (mask, GEN_INT (imask));
13951 emit_insn (gen_ashlsi3 (mask, mask, shift));
13954 newop = gen_rtx_PLUS (SImode, m, newop);
13956 newop = gen_rtx_MINUS (SImode, m, newop);
13957 newop = gen_rtx_AND (SImode, newop, mask);
13958 newop = gen_rtx_IOR (SImode, newop,
13959 gen_rtx_AND (SImode,
13960 gen_rtx_NOT (SImode, mask),
13966 gcc_unreachable ();
13970 used_mode = SImode;
13971 before = gen_reg_rtx (used_mode);
13972 after = gen_reg_rtx (used_mode);
13977 before = before_param;
13978 after = after_param;
13980 if (before == NULL_RTX)
13981 before = gen_reg_rtx (used_mode);
13982 if (after == NULL_RTX)
13983 after = gen_reg_rtx (used_mode);
13986 if ((code == PLUS || code == MINUS)
13987 && used_mode != mode)
13988 the_op = op; /* Computed above. */
13989 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13990 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13991 else if (code == NOT)
13992 the_op = gen_rtx_fmt_ee (IOR, used_mode,
13993 gen_rtx_NOT (used_mode, m),
13994 gen_rtx_NOT (used_mode, op));
13996 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13998 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13999 set_before = gen_rtx_SET (VOIDmode, before, used_m);
14000 set_atomic = gen_rtx_SET (VOIDmode, used_m,
14001 gen_rtx_UNSPEC (used_mode,
14002 gen_rtvec (1, the_op),
14004 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
14006 if ((code == PLUS || code == MINUS) && used_mode != mode)
14007 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
14008 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
14010 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
14011 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14013 /* Shift and mask the return values properly. */
14014 if (used_mode != mode && before_param)
14016 emit_insn (gen_lshrsi3 (before, before, shift));
14017 convert_move (before_param, before, 1);
14020 if (used_mode != mode && after_param)
14022 emit_insn (gen_lshrsi3 (after, after, shift));
14023 convert_move (after_param, after, 1);
14026 /* The previous sequence will end with a branch that's dependent on
14027 the conditional store, so placing an isync will ensure that no
14028 other instructions (especially, no load or store instructions)
14029 can start before the atomic operation completes. */
14031 emit_insn (gen_isync ());
14034 /* A subroutine of the atomic operation splitters. Jump to LABEL if
14035 COND is true. Mark the jump as unlikely to be taken. */
14038 emit_unlikely_jump (rtx cond, rtx label)
14040 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
14043 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
14044 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
14045 add_reg_note (x, REG_BR_PROB, very_unlikely);
14048 /* A subroutine of the atomic operation splitters. Emit a load-locked
14049 instruction in MODE. */
14052 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
14054 rtx (*fn) (rtx, rtx) = NULL;
14055 if (mode == SImode)
14056 fn = gen_load_locked_si;
14057 else if (mode == DImode)
14058 fn = gen_load_locked_di;
14059 emit_insn (fn (reg, mem));
14062 /* A subroutine of the atomic operation splitters. Emit a store-conditional
14063 instruction in MODE. */
14066 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
14068 rtx (*fn) (rtx, rtx, rtx) = NULL;
14069 if (mode == SImode)
14070 fn = gen_store_conditional_si;
14071 else if (mode == DImode)
14072 fn = gen_store_conditional_di;
14074 /* Emit sync before stwcx. to address PPC405 Erratum. */
14075 if (PPC405_ERRATUM77)
14076 emit_insn (gen_memory_barrier ());
14078 emit_insn (fn (res, mem, val));
14081 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
14082 to perform. MEM is the memory on which to operate. VAL is the second
14083 operand of the binary operator. BEFORE and AFTER are optional locations to
14084 return the value of MEM either before of after the operation. SCRATCH is
14085 a scratch register. */
14088 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
14089 rtx before, rtx after, rtx scratch)
14091 enum machine_mode mode = GET_MODE (mem);
14092 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
14094 emit_insn (gen_lwsync ());
14096 label = gen_label_rtx ();
14097 emit_label (label);
14098 label = gen_rtx_LABEL_REF (VOIDmode, label);
14100 if (before == NULL_RTX)
14102 emit_load_locked (mode, before, mem);
14105 x = gen_rtx_IOR (mode,
14106 gen_rtx_NOT (mode, before),
14107 gen_rtx_NOT (mode, val));
14108 else if (code == AND)
14109 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
14111 x = gen_rtx_fmt_ee (code, mode, before, val);
14113 if (after != NULL_RTX)
14114 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
14115 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14117 emit_store_conditional (mode, cond, mem, scratch);
14119 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14120 emit_unlikely_jump (x, label);
14122 emit_insn (gen_isync ());
14125 /* Expand an atomic compare and swap operation. MEM is the memory on which
14126 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
14127 value to be stored. SCRATCH is a scratch GPR. */
14130 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
14133 enum machine_mode mode = GET_MODE (mem);
14134 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
14136 emit_insn (gen_lwsync ());
14138 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14139 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14140 emit_label (XEXP (label1, 0));
14142 emit_load_locked (mode, retval, mem);
14144 x = gen_rtx_COMPARE (CCmode, retval, oldval);
14145 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
14147 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14148 emit_unlikely_jump (x, label2);
14150 emit_move_insn (scratch, newval);
14151 emit_store_conditional (mode, cond, mem, scratch);
14153 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14154 emit_unlikely_jump (x, label1);
14156 emit_insn (gen_isync ());
14157 emit_label (XEXP (label2, 0));
14160 /* Expand an atomic test and set operation. MEM is the memory on which
14161 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
14164 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
14166 enum machine_mode mode = GET_MODE (mem);
14167 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
14169 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14170 emit_label (XEXP (label, 0));
14172 emit_load_locked (mode, retval, mem);
14173 emit_move_insn (scratch, val);
14174 emit_store_conditional (mode, cond, mem, scratch);
14176 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14177 emit_unlikely_jump (x, label);
14179 emit_insn (gen_isync ());
14183 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
14185 enum machine_mode mode = GET_MODE (mem);
14186 rtx addrSI, align, wdst, shift, mask;
14187 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
14188 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
14190 /* Shift amount for subword relative to aligned word. */
14191 addrSI = force_reg (GET_MODE (XEXP (mem, 0)), XEXP (mem, 0));
14192 addrSI = force_reg (SImode, gen_lowpart_common (SImode, addrSI));
14193 shift = gen_reg_rtx (SImode);
14194 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
14195 GEN_INT (shift_mask)));
14196 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
14198 /* Shift and mask old value into position within word. */
14199 oldval = convert_modes (SImode, mode, oldval, 1);
14200 oldval = expand_binop (SImode, and_optab,
14201 oldval, GEN_INT (imask), NULL_RTX,
14202 1, OPTAB_LIB_WIDEN);
14203 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
14205 /* Shift and mask new value into position within word. */
14206 newval = convert_modes (SImode, mode, newval, 1);
14207 newval = expand_binop (SImode, and_optab,
14208 newval, GEN_INT (imask), NULL_RTX,
14209 1, OPTAB_LIB_WIDEN);
14210 emit_insn (gen_ashlsi3 (newval, newval, shift));
14212 /* Mask for insertion. */
14213 mask = gen_reg_rtx (SImode);
14214 emit_move_insn (mask, GEN_INT (imask));
14215 emit_insn (gen_ashlsi3 (mask, mask, shift));
14217 /* Address of aligned word containing subword. */
14218 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
14219 NULL_RTX, 1, OPTAB_LIB_WIDEN);
14220 mem = change_address (mem, SImode, align);
14221 set_mem_align (mem, 32);
14222 MEM_VOLATILE_P (mem) = 1;
14224 wdst = gen_reg_rtx (SImode);
14225 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
14226 oldval, newval, mem));
14228 /* Shift the result back. */
14229 emit_insn (gen_lshrsi3 (wdst, wdst, shift));
14231 emit_move_insn (dst, gen_lowpart (mode, wdst));
14235 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
14236 rtx oldval, rtx newval, rtx mem,
14239 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
14241 emit_insn (gen_lwsync ());
14242 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14243 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
14244 emit_label (XEXP (label1, 0));
14246 emit_load_locked (SImode, scratch, mem);
14248 /* Mask subword within loaded value for comparison with oldval.
14249 Use UNSPEC_AND to avoid clobber.*/
14250 emit_insn (gen_rtx_SET (SImode, dest,
14251 gen_rtx_UNSPEC (SImode,
14252 gen_rtvec (2, scratch, mask),
14255 x = gen_rtx_COMPARE (CCmode, dest, oldval);
14256 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
14258 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14259 emit_unlikely_jump (x, label2);
14261 /* Clear subword within loaded value for insertion of new value. */
14262 emit_insn (gen_rtx_SET (SImode, scratch,
14263 gen_rtx_AND (SImode,
14264 gen_rtx_NOT (SImode, mask), scratch)));
14265 emit_insn (gen_iorsi3 (scratch, scratch, newval));
14266 emit_store_conditional (SImode, cond, mem, scratch);
14268 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
14269 emit_unlikely_jump (x, label1);
14271 emit_insn (gen_isync ());
14272 emit_label (XEXP (label2, 0));
14276 /* Emit instructions to move SRC to DST. Called by splitters for
14277 multi-register moves. It will emit at most one instruction for
14278 each register that is accessed; that is, it won't emit li/lis pairs
14279 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14283 rs6000_split_multireg_move (rtx dst, rtx src)
14285 /* The register number of the first register being moved. */
14287 /* The mode that is to be moved. */
14288 enum machine_mode mode;
14289 /* The mode that the move is being done in, and its size. */
14290 enum machine_mode reg_mode;
14292 /* The number of registers that will be moved. */
14295 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
14296 mode = GET_MODE (dst);
14297 nregs = hard_regno_nregs[reg][mode];
14298 if (FP_REGNO_P (reg))
14299 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
14300 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
14301 else if (ALTIVEC_REGNO_P (reg))
14302 reg_mode = V16QImode;
14303 else if (TARGET_E500_DOUBLE && mode == TFmode)
14306 reg_mode = word_mode;
14307 reg_mode_size = GET_MODE_SIZE (reg_mode);
14309 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
14311 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
14313 /* Move register range backwards, if we might have destructive
14316 for (i = nregs - 1; i >= 0; i--)
14317 emit_insn (gen_rtx_SET (VOIDmode,
14318 simplify_gen_subreg (reg_mode, dst, mode,
14319 i * reg_mode_size),
14320 simplify_gen_subreg (reg_mode, src, mode,
14321 i * reg_mode_size)));
14327 bool used_update = false;
14329 if (MEM_P (src) && INT_REGNO_P (reg))
14333 if (GET_CODE (XEXP (src, 0)) == PRE_INC
14334 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
14337 breg = XEXP (XEXP (src, 0), 0);
14338 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
14339 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
14340 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
14341 emit_insn (TARGET_32BIT
14342 ? gen_addsi3 (breg, breg, delta_rtx)
14343 : gen_adddi3 (breg, breg, delta_rtx));
14344 src = replace_equiv_address (src, breg);
14346 else if (! rs6000_offsettable_memref_p (src))
14349 basereg = gen_rtx_REG (Pmode, reg);
14350 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
14351 src = replace_equiv_address (src, basereg);
14354 breg = XEXP (src, 0);
14355 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
14356 breg = XEXP (breg, 0);
14358 /* If the base register we are using to address memory is
14359 also a destination reg, then change that register last. */
14361 && REGNO (breg) >= REGNO (dst)
14362 && REGNO (breg) < REGNO (dst) + nregs)
14363 j = REGNO (breg) - REGNO (dst);
14366 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
14370 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
14371 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
14374 breg = XEXP (XEXP (dst, 0), 0);
14375 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
14376 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
14377 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
14379 /* We have to update the breg before doing the store.
14380 Use store with update, if available. */
14384 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
14385 emit_insn (TARGET_32BIT
14386 ? (TARGET_POWERPC64
14387 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
14388 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
14389 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
14390 used_update = true;
14393 emit_insn (TARGET_32BIT
14394 ? gen_addsi3 (breg, breg, delta_rtx)
14395 : gen_adddi3 (breg, breg, delta_rtx));
14396 dst = replace_equiv_address (dst, breg);
14399 gcc_assert (rs6000_offsettable_memref_p (dst));
14402 for (i = 0; i < nregs; i++)
14404 /* Calculate index to next subword. */
14409 /* If compiler already emitted move of first word by
14410 store with update, no need to do anything. */
14411 if (j == 0 && used_update)
14414 emit_insn (gen_rtx_SET (VOIDmode,
14415 simplify_gen_subreg (reg_mode, dst, mode,
14416 j * reg_mode_size),
14417 simplify_gen_subreg (reg_mode, src, mode,
14418 j * reg_mode_size)));
14424 /* This page contains routines that are used to determine what the
14425 function prologue and epilogue code will do and write them out. */
14427 /* Return the first fixed-point register that is required to be
14428 saved. 32 if none. */
14431 first_reg_to_save (void)
14435 /* Find lowest numbered live register. */
14436 for (first_reg = 13; first_reg <= 31; first_reg++)
14437 if (df_regs_ever_live_p (first_reg)
14438 && (! call_used_regs[first_reg]
14439 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14440 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14441 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
14442 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
14447 && crtl->uses_pic_offset_table
14448 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
14449 return RS6000_PIC_OFFSET_TABLE_REGNUM;
14455 /* Similar, for FP regs. */
14458 first_fp_reg_to_save (void)
14462 /* Find lowest numbered live register. */
14463 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
14464 if (df_regs_ever_live_p (first_reg))
14470 /* Similar, for AltiVec regs. */
14473 first_altivec_reg_to_save (void)
14477 /* Stack frame remains as is unless we are in AltiVec ABI. */
14478 if (! TARGET_ALTIVEC_ABI)
14479 return LAST_ALTIVEC_REGNO + 1;
14481 /* On Darwin, the unwind routines are compiled without
14482 TARGET_ALTIVEC, and use save_world to save/restore the
14483 altivec registers when necessary. */
14484 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14485 && ! TARGET_ALTIVEC)
14486 return FIRST_ALTIVEC_REGNO + 20;
14488 /* Find lowest numbered live register. */
14489 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
14490 if (df_regs_ever_live_p (i))
14496 /* Return a 32-bit mask of the AltiVec registers we need to set in
14497 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14498 the 32-bit word is 0. */
14500 static unsigned int
14501 compute_vrsave_mask (void)
14503 unsigned int i, mask = 0;
14505 /* On Darwin, the unwind routines are compiled without
14506 TARGET_ALTIVEC, and use save_world to save/restore the
14507 call-saved altivec registers when necessary. */
14508 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
14509 && ! TARGET_ALTIVEC)
14512 /* First, find out if we use _any_ altivec registers. */
14513 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14514 if (df_regs_ever_live_p (i))
14515 mask |= ALTIVEC_REG_BIT (i);
14520 /* Next, remove the argument registers from the set. These must
14521 be in the VRSAVE mask set by the caller, so we don't need to add
14522 them in again. More importantly, the mask we compute here is
14523 used to generate CLOBBERs in the set_vrsave insn, and we do not
14524 wish the argument registers to die. */
14525 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
14526 mask &= ~ALTIVEC_REG_BIT (i);
14528 /* Similarly, remove the return value from the set. */
14531 diddle_return_value (is_altivec_return_reg, &yes);
14533 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
14539 /* For a very restricted set of circumstances, we can cut down the
14540 size of prologues/epilogues by calling our own save/restore-the-world
14544 compute_save_world_info (rs6000_stack_t *info_ptr)
14546 info_ptr->world_save_p = 1;
14547 info_ptr->world_save_p
14548 = (WORLD_SAVE_P (info_ptr)
14549 && DEFAULT_ABI == ABI_DARWIN
14550 && ! (cfun->calls_setjmp && flag_exceptions)
14551 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
14552 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
14553 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
14554 && info_ptr->cr_save_p);
14556 /* This will not work in conjunction with sibcalls. Make sure there
14557 are none. (This check is expensive, but seldom executed.) */
14558 if (WORLD_SAVE_P (info_ptr))
14561 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
14562 if ( GET_CODE (insn) == CALL_INSN
14563 && SIBLING_CALL_P (insn))
14565 info_ptr->world_save_p = 0;
14570 if (WORLD_SAVE_P (info_ptr))
14572 /* Even if we're not touching VRsave, make sure there's room on the
14573 stack for it, if it looks like we're calling SAVE_WORLD, which
14574 will attempt to save it. */
14575 info_ptr->vrsave_size = 4;
14577 /* If we are going to save the world, we need to save the link register too. */
14578 info_ptr->lr_save_p = 1;
14580 /* "Save" the VRsave register too if we're saving the world. */
14581 if (info_ptr->vrsave_mask == 0)
14582 info_ptr->vrsave_mask = compute_vrsave_mask ();
14584 /* Because the Darwin register save/restore routines only handle
14585 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14587 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
14588 && (info_ptr->first_altivec_reg_save
14589 >= FIRST_SAVED_ALTIVEC_REGNO));
14596 is_altivec_return_reg (rtx reg, void *xyes)
14598 bool *yes = (bool *) xyes;
14599 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
14604 /* Calculate the stack information for the current function. This is
14605 complicated by having two separate calling sequences, the AIX calling
14606 sequence and the V.4 calling sequence.
14608 AIX (and Darwin/Mac OS X) stack frames look like:
14610 SP----> +---------------------------------------+
14611 | back chain to caller | 0 0
14612 +---------------------------------------+
14613 | saved CR | 4 8 (8-11)
14614 +---------------------------------------+
14616 +---------------------------------------+
14617 | reserved for compilers | 12 24
14618 +---------------------------------------+
14619 | reserved for binders | 16 32
14620 +---------------------------------------+
14621 | saved TOC pointer | 20 40
14622 +---------------------------------------+
14623 | Parameter save area (P) | 24 48
14624 +---------------------------------------+
14625 | Alloca space (A) | 24+P etc.
14626 +---------------------------------------+
14627 | Local variable space (L) | 24+P+A
14628 +---------------------------------------+
14629 | Float/int conversion temporary (X) | 24+P+A+L
14630 +---------------------------------------+
14631 | Save area for AltiVec registers (W) | 24+P+A+L+X
14632 +---------------------------------------+
14633 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14634 +---------------------------------------+
14635 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14636 +---------------------------------------+
14637 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14638 +---------------------------------------+
14639 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14640 +---------------------------------------+
14641 old SP->| back chain to caller's caller |
14642 +---------------------------------------+
14644 The required alignment for AIX configurations is two words (i.e., 8
14648 V.4 stack frames look like:
14650 SP----> +---------------------------------------+
14651 | back chain to caller | 0
14652 +---------------------------------------+
14653 | caller's saved LR | 4
14654 +---------------------------------------+
14655 | Parameter save area (P) | 8
14656 +---------------------------------------+
14657 | Alloca space (A) | 8+P
14658 +---------------------------------------+
14659 | Varargs save area (V) | 8+P+A
14660 +---------------------------------------+
14661 | Local variable space (L) | 8+P+A+V
14662 +---------------------------------------+
14663 | Float/int conversion temporary (X) | 8+P+A+V+L
14664 +---------------------------------------+
14665 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14666 +---------------------------------------+
14667 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14668 +---------------------------------------+
14669 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14670 +---------------------------------------+
14671 | SPE: area for 64-bit GP registers |
14672 +---------------------------------------+
14673 | SPE alignment padding |
14674 +---------------------------------------+
14675 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14676 +---------------------------------------+
14677 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14678 +---------------------------------------+
14679 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14680 +---------------------------------------+
14681 old SP->| back chain to caller's caller |
14682 +---------------------------------------+
14684 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14685 given. (But note below and in sysv4.h that we require only 8 and
14686 may round up the size of our stack frame anyways. The historical
14687 reason is early versions of powerpc-linux which didn't properly
14688 align the stack at program startup. A happy side-effect is that
14689 -mno-eabi libraries can be used with -meabi programs.)
14691 The EABI configuration defaults to the V.4 layout. However,
14692 the stack alignment requirements may differ. If -mno-eabi is not
14693 given, the required stack alignment is 8 bytes; if -mno-eabi is
14694 given, the required alignment is 16 bytes. (But see V.4 comment
14697 #ifndef ABI_STACK_BOUNDARY
14698 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14701 static rs6000_stack_t *
14702 rs6000_stack_info (void)
14704 static rs6000_stack_t info;
14705 rs6000_stack_t *info_ptr = &info;
14706 int reg_size = TARGET_32BIT ? 4 : 8;
14710 HOST_WIDE_INT non_fixed_size;
14712 memset (&info, 0, sizeof (info));
14716 /* Cache value so we don't rescan instruction chain over and over. */
14717 if (cfun->machine->insn_chain_scanned_p == 0)
14718 cfun->machine->insn_chain_scanned_p
14719 = spe_func_has_64bit_regs_p () + 1;
14720 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
14723 /* Select which calling sequence. */
14724 info_ptr->abi = DEFAULT_ABI;
14726 /* Calculate which registers need to be saved & save area size. */
14727 info_ptr->first_gp_reg_save = first_reg_to_save ();
14728 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14729 even if it currently looks like we won't. Reload may need it to
14730 get at a constant; if so, it will have already created a constant
14731 pool entry for it. */
14732 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
14733 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
14734 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
14735 && crtl->uses_const_pool
14736 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
14737 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
14739 first_gp = info_ptr->first_gp_reg_save;
14741 info_ptr->gp_size = reg_size * (32 - first_gp);
14743 /* For the SPE, we have an additional upper 32-bits on each GPR.
14744 Ideally we should save the entire 64-bits only when the upper
14745 half is used in SIMD instructions. Since we only record
14746 registers live (not the size they are used in), this proves
14747 difficult because we'd have to traverse the instruction chain at
14748 the right time, taking reload into account. This is a real pain,
14749 so we opt to save the GPRs in 64-bits always if but one register
14750 gets used in 64-bits. Otherwise, all the registers in the frame
14751 get saved in 32-bits.
14753 So... since when we save all GPRs (except the SP) in 64-bits, the
14754 traditional GP save area will be empty. */
14755 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14756 info_ptr->gp_size = 0;
14758 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
14759 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
14761 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
14762 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
14763 - info_ptr->first_altivec_reg_save);
14765 /* Does this function call anything? */
14766 info_ptr->calls_p = (! current_function_is_leaf
14767 || cfun->machine->ra_needs_full_frame);
14769 /* Determine if we need to save the link register. */
14770 if ((DEFAULT_ABI == ABI_AIX
14772 && !TARGET_PROFILE_KERNEL)
14773 #ifdef TARGET_RELOCATABLE
14774 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
14776 || (info_ptr->first_fp_reg_save != 64
14777 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
14778 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
14779 || info_ptr->calls_p
14780 || rs6000_ra_ever_killed ())
14782 info_ptr->lr_save_p = 1;
14783 df_set_regs_ever_live (LR_REGNO, true);
14786 /* Determine if we need to save the condition code registers. */
14787 if (df_regs_ever_live_p (CR2_REGNO)
14788 || df_regs_ever_live_p (CR3_REGNO)
14789 || df_regs_ever_live_p (CR4_REGNO))
14791 info_ptr->cr_save_p = 1;
14792 if (DEFAULT_ABI == ABI_V4)
14793 info_ptr->cr_size = reg_size;
14796 /* If the current function calls __builtin_eh_return, then we need
14797 to allocate stack space for registers that will hold data for
14798 the exception handler. */
14799 if (crtl->calls_eh_return)
14802 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14805 /* SPE saves EH registers in 64-bits. */
14806 ehrd_size = i * (TARGET_SPE_ABI
14807 && info_ptr->spe_64bit_regs_used != 0
14808 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14813 /* Determine various sizes. */
14814 info_ptr->reg_size = reg_size;
14815 info_ptr->fixed_size = RS6000_SAVE_AREA;
14816 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14817 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
14818 TARGET_ALTIVEC ? 16 : 8);
14819 if (FRAME_GROWS_DOWNWARD)
14820 info_ptr->vars_size
14821 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14822 + info_ptr->parm_size,
14823 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14824 - (info_ptr->fixed_size + info_ptr->vars_size
14825 + info_ptr->parm_size);
14827 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14828 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14830 info_ptr->spe_gp_size = 0;
14832 if (TARGET_ALTIVEC_ABI)
14833 info_ptr->vrsave_mask = compute_vrsave_mask ();
14835 info_ptr->vrsave_mask = 0;
14837 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14838 info_ptr->vrsave_size = 4;
14840 info_ptr->vrsave_size = 0;
14842 compute_save_world_info (info_ptr);
14844 /* Calculate the offsets. */
14845 switch (DEFAULT_ABI)
14849 gcc_unreachable ();
14853 info_ptr->fp_save_offset = - info_ptr->fp_size;
14854 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14856 if (TARGET_ALTIVEC_ABI)
14858 info_ptr->vrsave_save_offset
14859 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14861 /* Align stack so vector save area is on a quadword boundary.
14862 The padding goes above the vectors. */
14863 if (info_ptr->altivec_size != 0)
14864 info_ptr->altivec_padding_size
14865 = info_ptr->vrsave_save_offset & 0xF;
14867 info_ptr->altivec_padding_size = 0;
14869 info_ptr->altivec_save_offset
14870 = info_ptr->vrsave_save_offset
14871 - info_ptr->altivec_padding_size
14872 - info_ptr->altivec_size;
14873 gcc_assert (info_ptr->altivec_size == 0
14874 || info_ptr->altivec_save_offset % 16 == 0);
14876 /* Adjust for AltiVec case. */
14877 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14880 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14881 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14882 info_ptr->lr_save_offset = 2*reg_size;
14886 info_ptr->fp_save_offset = - info_ptr->fp_size;
14887 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14888 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14890 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14892 /* Align stack so SPE GPR save area is aligned on a
14893 double-word boundary. */
14894 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
14895 info_ptr->spe_padding_size
14896 = 8 - (-info_ptr->cr_save_offset % 8);
14898 info_ptr->spe_padding_size = 0;
14900 info_ptr->spe_gp_save_offset
14901 = info_ptr->cr_save_offset
14902 - info_ptr->spe_padding_size
14903 - info_ptr->spe_gp_size;
14905 /* Adjust for SPE case. */
14906 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14908 else if (TARGET_ALTIVEC_ABI)
14910 info_ptr->vrsave_save_offset
14911 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14913 /* Align stack so vector save area is on a quadword boundary. */
14914 if (info_ptr->altivec_size != 0)
14915 info_ptr->altivec_padding_size
14916 = 16 - (-info_ptr->vrsave_save_offset % 16);
14918 info_ptr->altivec_padding_size = 0;
14920 info_ptr->altivec_save_offset
14921 = info_ptr->vrsave_save_offset
14922 - info_ptr->altivec_padding_size
14923 - info_ptr->altivec_size;
14925 /* Adjust for AltiVec case. */
14926 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14929 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14930 info_ptr->ehrd_offset -= ehrd_size;
14931 info_ptr->lr_save_offset = reg_size;
14935 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14936 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14937 + info_ptr->gp_size
14938 + info_ptr->altivec_size
14939 + info_ptr->altivec_padding_size
14940 + info_ptr->spe_gp_size
14941 + info_ptr->spe_padding_size
14943 + info_ptr->cr_size
14944 + info_ptr->vrsave_size,
14947 non_fixed_size = (info_ptr->vars_size
14948 + info_ptr->parm_size
14949 + info_ptr->save_size);
14951 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14952 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14954 /* Determine if we need to allocate any stack frame:
14956 For AIX we need to push the stack if a frame pointer is needed
14957 (because the stack might be dynamically adjusted), if we are
14958 debugging, if we make calls, or if the sum of fp_save, gp_save,
14959 and local variables are more than the space needed to save all
14960 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14961 + 18*8 = 288 (GPR13 reserved).
14963 For V.4 we don't have the stack cushion that AIX uses, but assume
14964 that the debugger can handle stackless frames. */
14966 if (info_ptr->calls_p)
14967 info_ptr->push_p = 1;
14969 else if (DEFAULT_ABI == ABI_V4)
14970 info_ptr->push_p = non_fixed_size != 0;
14972 else if (frame_pointer_needed)
14973 info_ptr->push_p = 1;
14975 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14976 info_ptr->push_p = 1;
14979 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14981 /* Zero offsets if we're not saving those registers. */
14982 if (info_ptr->fp_size == 0)
14983 info_ptr->fp_save_offset = 0;
14985 if (info_ptr->gp_size == 0)
14986 info_ptr->gp_save_offset = 0;
14988 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14989 info_ptr->altivec_save_offset = 0;
14991 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14992 info_ptr->vrsave_save_offset = 0;
14994 if (! TARGET_SPE_ABI
14995 || info_ptr->spe_64bit_regs_used == 0
14996 || info_ptr->spe_gp_size == 0)
14997 info_ptr->spe_gp_save_offset = 0;
14999 if (! info_ptr->lr_save_p)
15000 info_ptr->lr_save_offset = 0;
15002 if (! info_ptr->cr_save_p)
15003 info_ptr->cr_save_offset = 0;
15008 /* Return true if the current function uses any GPRs in 64-bit SIMD
15012 spe_func_has_64bit_regs_p (void)
15016 /* Functions that save and restore all the call-saved registers will
15017 need to save/restore the registers in 64-bits. */
15018 if (crtl->calls_eh_return
15019 || cfun->calls_setjmp
15020 || crtl->has_nonlocal_goto)
15023 insns = get_insns ();
15025 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
15031 /* FIXME: This should be implemented with attributes...
15033 (set_attr "spe64" "true")....then,
15034 if (get_spe64(insn)) return true;
15036 It's the only reliable way to do the stuff below. */
15038 i = PATTERN (insn);
15039 if (GET_CODE (i) == SET)
15041 enum machine_mode mode = GET_MODE (SET_SRC (i));
15043 if (SPE_VECTOR_MODE (mode))
15045 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
15055 debug_stack_info (rs6000_stack_t *info)
15057 const char *abi_string;
15060 info = rs6000_stack_info ();
15062 fprintf (stderr, "\nStack information for function %s:\n",
15063 ((current_function_decl && DECL_NAME (current_function_decl))
15064 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
15069 default: abi_string = "Unknown"; break;
15070 case ABI_NONE: abi_string = "NONE"; break;
15071 case ABI_AIX: abi_string = "AIX"; break;
15072 case ABI_DARWIN: abi_string = "Darwin"; break;
15073 case ABI_V4: abi_string = "V.4"; break;
15076 fprintf (stderr, "\tABI = %5s\n", abi_string);
15078 if (TARGET_ALTIVEC_ABI)
15079 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
15081 if (TARGET_SPE_ABI)
15082 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
15084 if (info->first_gp_reg_save != 32)
15085 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
15087 if (info->first_fp_reg_save != 64)
15088 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
15090 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
15091 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
15092 info->first_altivec_reg_save);
15094 if (info->lr_save_p)
15095 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
15097 if (info->cr_save_p)
15098 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
15100 if (info->vrsave_mask)
15101 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
15104 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
15107 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
15109 if (info->gp_save_offset)
15110 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
15112 if (info->fp_save_offset)
15113 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
15115 if (info->altivec_save_offset)
15116 fprintf (stderr, "\taltivec_save_offset = %5d\n",
15117 info->altivec_save_offset);
15119 if (info->spe_gp_save_offset)
15120 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
15121 info->spe_gp_save_offset);
15123 if (info->vrsave_save_offset)
15124 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
15125 info->vrsave_save_offset);
15127 if (info->lr_save_offset)
15128 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
15130 if (info->cr_save_offset)
15131 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
15133 if (info->varargs_save_offset)
15134 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
15136 if (info->total_size)
15137 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
15140 if (info->vars_size)
15141 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
15144 if (info->parm_size)
15145 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
15147 if (info->fixed_size)
15148 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
15151 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
15153 if (info->spe_gp_size)
15154 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
15157 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
15159 if (info->altivec_size)
15160 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
15162 if (info->vrsave_size)
15163 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
15165 if (info->altivec_padding_size)
15166 fprintf (stderr, "\taltivec_padding_size= %5d\n",
15167 info->altivec_padding_size);
15169 if (info->spe_padding_size)
15170 fprintf (stderr, "\tspe_padding_size = %5d\n",
15171 info->spe_padding_size);
15174 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
15176 if (info->save_size)
15177 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
15179 if (info->reg_size != 4)
15180 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
15182 fprintf (stderr, "\n");
15186 rs6000_return_addr (int count, rtx frame)
15188 /* Currently we don't optimize very well between prolog and body
15189 code and for PIC code the code can be actually quite bad, so
15190 don't try to be too clever here. */
15191 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
15193 cfun->machine->ra_needs_full_frame = 1;
15200 plus_constant (copy_to_reg
15201 (gen_rtx_MEM (Pmode,
15202 memory_address (Pmode, frame))),
15203 RETURN_ADDRESS_OFFSET)));
15206 cfun->machine->ra_need_lr = 1;
15207 return get_hard_reg_initial_val (Pmode, LR_REGNO);
15210 /* Say whether a function is a candidate for sibcall handling or not.
15211 We do not allow indirect calls to be optimized into sibling calls.
15212 Also, we can't do it if there are any vector parameters; there's
15213 nowhere to put the VRsave code so it works; note that functions with
15214 vector parameters are required to have a prototype, so the argument
15215 type info must be available here. (The tail recursion case can work
15216 with vector parameters, but there's no way to distinguish here.) */
15218 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
15223 if (TARGET_ALTIVEC_VRSAVE)
15225 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
15226 type; type = TREE_CHAIN (type))
15228 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
15232 if (DEFAULT_ABI == ABI_DARWIN
15233 || ((*targetm.binds_local_p) (decl)
15234 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
15236 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
15238 if (!lookup_attribute ("longcall", attr_list)
15239 || lookup_attribute ("shortcall", attr_list))
15246 /* NULL if INSN insn is valid within a low-overhead loop.
15247 Otherwise return why doloop cannot be applied.
15248 PowerPC uses the COUNT register for branch on table instructions. */
15250 static const char *
15251 rs6000_invalid_within_doloop (const_rtx insn)
15254 return "Function call in the loop.";
15257 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
15258 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
15259 return "Computed branch in the loop.";
15265 rs6000_ra_ever_killed (void)
15271 if (cfun->is_thunk)
15274 /* regs_ever_live has LR marked as used if any sibcalls are present,
15275 but this should not force saving and restoring in the
15276 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15277 clobbers LR, so that is inappropriate. */
15279 /* Also, the prologue can generate a store into LR that
15280 doesn't really count, like this:
15283 bcl to set PIC register
15287 When we're called from the epilogue, we need to avoid counting
15288 this as a store. */
15290 push_topmost_sequence ();
15291 top = get_insns ();
15292 pop_topmost_sequence ();
15293 reg = gen_rtx_REG (Pmode, LR_REGNO);
15295 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
15301 if (!SIBLING_CALL_P (insn))
15304 else if (find_regno_note (insn, REG_INC, LR_REGNO))
15306 else if (set_of (reg, insn) != NULL_RTX
15307 && !prologue_epilogue_contains (insn))
15314 /* Emit instructions needed to load the TOC register.
15315 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15316 a constant pool; or for SVR4 -fpic. */
15319 rs6000_emit_load_toc_table (int fromprolog)
15322 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
15324 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
15327 rtx lab, tmp1, tmp2, got;
15329 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15330 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15332 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15334 got = rs6000_got_sym ();
15335 tmp1 = tmp2 = dest;
15338 tmp1 = gen_reg_rtx (Pmode);
15339 tmp2 = gen_reg_rtx (Pmode);
15341 emit_insn (gen_load_toc_v4_PIC_1 (lab));
15342 emit_move_insn (tmp1,
15343 gen_rtx_REG (Pmode, LR_REGNO));
15344 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
15345 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
15347 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
15349 emit_insn (gen_load_toc_v4_pic_si ());
15350 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
15352 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
15355 rtx temp0 = (fromprolog
15356 ? gen_rtx_REG (Pmode, 0)
15357 : gen_reg_rtx (Pmode));
15363 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15364 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15366 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
15367 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15369 emit_insn (gen_load_toc_v4_PIC_1 (symF));
15370 emit_move_insn (dest,
15371 gen_rtx_REG (Pmode, LR_REGNO));
15372 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
15378 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
15379 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
15380 emit_move_insn (dest,
15381 gen_rtx_REG (Pmode, LR_REGNO));
15382 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
15384 emit_insn (gen_addsi3 (dest, temp0, dest));
15386 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
15388 /* This is for AIX code running in non-PIC ELF32. */
15391 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15392 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
15394 emit_insn (gen_elf_high (dest, realsym));
15395 emit_insn (gen_elf_low (dest, dest, realsym));
15399 gcc_assert (DEFAULT_ABI == ABI_AIX);
15402 emit_insn (gen_load_toc_aix_si (dest));
15404 emit_insn (gen_load_toc_aix_di (dest));
15408 /* Emit instructions to restore the link register after determining where
15409 its value has been stored. */
15412 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
15414 rs6000_stack_t *info = rs6000_stack_info ();
15417 operands[0] = source;
15418 operands[1] = scratch;
15420 if (info->lr_save_p)
15422 rtx frame_rtx = stack_pointer_rtx;
15423 HOST_WIDE_INT sp_offset = 0;
15426 if (frame_pointer_needed
15427 || cfun->calls_alloca
15428 || info->total_size > 32767)
15430 tmp = gen_frame_mem (Pmode, frame_rtx);
15431 emit_move_insn (operands[1], tmp);
15432 frame_rtx = operands[1];
15434 else if (info->push_p)
15435 sp_offset = info->total_size;
15437 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
15438 tmp = gen_frame_mem (Pmode, tmp);
15439 emit_move_insn (tmp, operands[0]);
15442 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
15445 static GTY(()) alias_set_type set = -1;
15448 get_TOC_alias_set (void)
15451 set = new_alias_set ();
15455 /* This returns nonzero if the current function uses the TOC. This is
15456 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15457 is generated by the ABI_V4 load_toc_* patterns. */
15464 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15467 rtx pat = PATTERN (insn);
15470 if (GET_CODE (pat) == PARALLEL)
15471 for (i = 0; i < XVECLEN (pat, 0); i++)
15473 rtx sub = XVECEXP (pat, 0, i);
15474 if (GET_CODE (sub) == USE)
15476 sub = XEXP (sub, 0);
15477 if (GET_CODE (sub) == UNSPEC
15478 && XINT (sub, 1) == UNSPEC_TOC)
15488 create_TOC_reference (rtx symbol)
15490 if (!can_create_pseudo_p ())
15491 df_set_regs_ever_live (TOC_REGISTER, true);
15492 return gen_rtx_PLUS (Pmode,
15493 gen_rtx_REG (Pmode, TOC_REGISTER),
15494 gen_rtx_CONST (Pmode,
15495 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_TOCREL)));
15498 /* If _Unwind_* has been called from within the same module,
15499 toc register is not guaranteed to be saved to 40(1) on function
15500 entry. Save it there in that case. */
15503 rs6000_aix_emit_builtin_unwind_init (void)
15506 rtx stack_top = gen_reg_rtx (Pmode);
15507 rtx opcode_addr = gen_reg_rtx (Pmode);
15508 rtx opcode = gen_reg_rtx (SImode);
15509 rtx tocompare = gen_reg_rtx (SImode);
15510 rtx no_toc_save_needed = gen_label_rtx ();
15512 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
15513 emit_move_insn (stack_top, mem);
15515 mem = gen_frame_mem (Pmode,
15516 gen_rtx_PLUS (Pmode, stack_top,
15517 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
15518 emit_move_insn (opcode_addr, mem);
15519 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
15520 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
15521 : 0xE8410028, SImode));
15523 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
15524 SImode, NULL_RTX, NULL_RTX,
15525 no_toc_save_needed);
15527 mem = gen_frame_mem (Pmode,
15528 gen_rtx_PLUS (Pmode, stack_top,
15529 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
15530 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
15531 emit_label (no_toc_save_needed);
15534 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15535 and the change to the stack pointer. */
15538 rs6000_emit_stack_tie (void)
15540 rtx mem = gen_frame_mem (BLKmode,
15541 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
15543 emit_insn (gen_stack_tie (mem));
15546 /* Emit the correct code for allocating stack space, as insns.
15547 If COPY_R12, make sure a copy of the old frame is left in r12.
15548 If COPY_R11, make sure a copy of the old frame is left in r11,
15549 in preference to r12 if COPY_R12.
15550 The generated code may use hard register 0 as a temporary. */
15553 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12, int copy_r11)
15556 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15557 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
15558 rtx todec = gen_int_mode (-size, Pmode);
15561 if (INTVAL (todec) != -size)
15563 warning (0, "stack frame too large");
15564 emit_insn (gen_trap ());
15568 if (crtl->limit_stack)
15570 if (REG_P (stack_limit_rtx)
15571 && REGNO (stack_limit_rtx) > 1
15572 && REGNO (stack_limit_rtx) <= 31)
15574 emit_insn (TARGET_32BIT
15575 ? gen_addsi3 (tmp_reg,
15578 : gen_adddi3 (tmp_reg,
15582 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15585 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
15587 && DEFAULT_ABI == ABI_V4)
15589 rtx toload = gen_rtx_CONST (VOIDmode,
15590 gen_rtx_PLUS (Pmode,
15594 emit_insn (gen_elf_high (tmp_reg, toload));
15595 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
15596 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
15600 warning (0, "stack limit expression is not supported");
15603 if (copy_r12 || copy_r11)
15604 emit_move_insn (copy_r11
15605 ? gen_rtx_REG (Pmode, 11)
15606 : gen_rtx_REG (Pmode, 12),
15611 /* Need a note here so that try_split doesn't get confused. */
15612 if (get_last_insn () == NULL_RTX)
15613 emit_note (NOTE_INSN_DELETED);
15614 insn = emit_move_insn (tmp_reg, todec);
15615 try_split (PATTERN (insn), insn, 0);
15619 insn = emit_insn (TARGET_32BIT
15620 ? gen_movsi_update_stack (stack_reg, stack_reg,
15622 : gen_movdi_di_update_stack (stack_reg, stack_reg,
15623 todec, stack_reg));
15624 /* Since we didn't use gen_frame_mem to generate the MEM, grab
15625 it now and set the alias set/attributes. The above gen_*_update
15626 calls will generate a PARALLEL with the MEM set being the first
15628 par = PATTERN (insn);
15629 gcc_assert (GET_CODE (par) == PARALLEL);
15630 set = XVECEXP (par, 0, 0);
15631 gcc_assert (GET_CODE (set) == SET);
15632 mem = SET_DEST (set);
15633 gcc_assert (MEM_P (mem));
15634 MEM_NOTRAP_P (mem) = 1;
15635 set_mem_alias_set (mem, get_frame_alias_set ());
15637 RTX_FRAME_RELATED_P (insn) = 1;
15638 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
15639 gen_rtx_SET (VOIDmode, stack_reg,
15640 gen_rtx_PLUS (Pmode, stack_reg,
15641 GEN_INT (-size))));
15644 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15645 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15646 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15647 deduce these equivalences by itself so it wasn't necessary to hold
15648 its hand so much. */
15651 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
15652 rtx reg2, rtx rreg)
15656 /* copy_rtx will not make unique copies of registers, so we need to
15657 ensure we don't have unwanted sharing here. */
15659 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15662 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
15664 real = copy_rtx (PATTERN (insn));
15666 if (reg2 != NULL_RTX)
15667 real = replace_rtx (real, reg2, rreg);
15669 real = replace_rtx (real, reg,
15670 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
15671 STACK_POINTER_REGNUM),
15674 /* We expect that 'real' is either a SET or a PARALLEL containing
15675 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15676 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15678 if (GET_CODE (real) == SET)
15682 temp = simplify_rtx (SET_SRC (set));
15684 SET_SRC (set) = temp;
15685 temp = simplify_rtx (SET_DEST (set));
15687 SET_DEST (set) = temp;
15688 if (GET_CODE (SET_DEST (set)) == MEM)
15690 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15692 XEXP (SET_DEST (set), 0) = temp;
15699 gcc_assert (GET_CODE (real) == PARALLEL);
15700 for (i = 0; i < XVECLEN (real, 0); i++)
15701 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
15703 rtx set = XVECEXP (real, 0, i);
15705 temp = simplify_rtx (SET_SRC (set));
15707 SET_SRC (set) = temp;
15708 temp = simplify_rtx (SET_DEST (set));
15710 SET_DEST (set) = temp;
15711 if (GET_CODE (SET_DEST (set)) == MEM)
15713 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15715 XEXP (SET_DEST (set), 0) = temp;
15717 RTX_FRAME_RELATED_P (set) = 1;
15721 RTX_FRAME_RELATED_P (insn) = 1;
15722 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
15725 /* Returns an insn that has a vrsave set operation with the
15726 appropriate CLOBBERs. */
15729 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15732 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15733 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15736 = gen_rtx_SET (VOIDmode,
15738 gen_rtx_UNSPEC_VOLATILE (SImode,
15739 gen_rtvec (2, reg, vrsave),
15740 UNSPECV_SET_VRSAVE));
15744 /* We need to clobber the registers in the mask so the scheduler
15745 does not move sets to VRSAVE before sets of AltiVec registers.
15747 However, if the function receives nonlocal gotos, reload will set
15748 all call saved registers live. We will end up with:
15750 (set (reg 999) (mem))
15751 (parallel [ (set (reg vrsave) (unspec blah))
15752 (clobber (reg 999))])
15754 The clobber will cause the store into reg 999 to be dead, and
15755 flow will attempt to delete an epilogue insn. In this case, we
15756 need an unspec use/set of the register. */
15758 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15759 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15761 if (!epiloguep || call_used_regs [i])
15762 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15763 gen_rtx_REG (V4SImode, i));
15766 rtx reg = gen_rtx_REG (V4SImode, i);
15769 = gen_rtx_SET (VOIDmode,
15771 gen_rtx_UNSPEC (V4SImode,
15772 gen_rtvec (1, reg), 27));
15776 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15778 for (i = 0; i < nclobs; ++i)
15779 XVECEXP (insn, 0, i) = clobs[i];
15784 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15785 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15788 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15789 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15791 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15792 rtx replacea, replaceb;
15794 int_rtx = GEN_INT (offset);
15796 /* Some cases that need register indexed addressing. */
15797 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15798 || (TARGET_E500_DOUBLE && mode == DFmode)
15800 && SPE_VECTOR_MODE (mode)
15801 && !SPE_CONST_OFFSET_OK (offset)))
15803 /* Whomever calls us must make sure r11 is available in the
15804 flow path of instructions in the prologue. */
15805 offset_rtx = gen_rtx_REG (Pmode, 11);
15806 emit_move_insn (offset_rtx, int_rtx);
15808 replacea = offset_rtx;
15809 replaceb = int_rtx;
15813 offset_rtx = int_rtx;
15814 replacea = NULL_RTX;
15815 replaceb = NULL_RTX;
15818 reg = gen_rtx_REG (mode, regno);
15819 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15820 mem = gen_frame_mem (mode, addr);
15822 insn = emit_move_insn (mem, reg);
15824 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15827 /* Emit an offset memory reference suitable for a frame store, while
15828 converting to a valid addressing mode. */
15831 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15833 rtx int_rtx, offset_rtx;
15835 int_rtx = GEN_INT (offset);
15837 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15838 || (TARGET_E500_DOUBLE && mode == DFmode))
15840 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15841 emit_move_insn (offset_rtx, int_rtx);
15844 offset_rtx = int_rtx;
15846 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15849 /* Look for user-defined global regs. We should not save and restore these,
15850 and cannot use stmw/lmw if there are any in its range. */
15853 no_global_regs_above (int first, bool gpr)
15856 for (i = first; i < gpr ? 32 : 64 ; i++)
15857 if (global_regs[i])
15862 #ifndef TARGET_FIX_AND_CONTINUE
15863 #define TARGET_FIX_AND_CONTINUE 0
15866 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15867 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15868 #define LAST_SAVRES_REGISTER 31
15869 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15871 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
15873 /* Return the symbol for an out-of-line register save/restore routine.
15874 We are saving/restoring GPRs if GPR is true. */
15877 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep, bool gpr, bool exitp)
15879 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
15881 int select = ((savep ? 1 : 0) << 2
15883 /* On the SPE, we never have any FPRs, but we do have
15884 32/64-bit versions of the routines. */
15885 ? (TARGET_SPE_ABI && info->spe_64bit_regs_used ? 1 : 0)
15889 /* Don't generate bogus routine names. */
15890 gcc_assert (FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER);
15892 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
15897 const char *action;
15898 const char *regkind;
15899 const char *exit_suffix;
15901 action = savep ? "save" : "rest";
15903 /* SPE has slightly different names for its routines depending on
15904 whether we are saving 32-bit or 64-bit registers. */
15905 if (TARGET_SPE_ABI)
15907 /* No floating point saves on the SPE. */
15910 regkind = info->spe_64bit_regs_used ? "64gpr" : "32gpr";
15913 regkind = gpr ? "gpr" : "fpr";
15915 exit_suffix = exitp ? "_x" : "";
15917 sprintf (name, "_%s%s_%d%s", action, regkind, regno, exit_suffix);
15919 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
15920 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
15926 /* Emit a sequence of insns, including a stack tie if needed, for
15927 resetting the stack pointer. If SAVRES is true, then don't reset the
15928 stack pointer, but move the base of the frame into r11 for use by
15929 out-of-line register restore routines. */
15932 rs6000_emit_stack_reset (rs6000_stack_t *info,
15933 rtx sp_reg_rtx, rtx frame_reg_rtx,
15934 int sp_offset, bool savres)
15936 /* This blockage is needed so that sched doesn't decide to move
15937 the sp change before the register restores. */
15938 if (frame_reg_rtx != sp_reg_rtx
15940 && info->spe_64bit_regs_used != 0
15941 && info->first_gp_reg_save != 32))
15942 rs6000_emit_stack_tie ();
15944 if (frame_reg_rtx != sp_reg_rtx)
15946 if (sp_offset != 0)
15947 emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx,
15948 GEN_INT (sp_offset)));
15950 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15952 else if (sp_offset != 0)
15954 /* If we are restoring registers out-of-line, we will be using the
15955 "exit" variants of the restore routines, which will reset the
15956 stack for us. But we do need to point r11 into the right place
15957 for those routines. */
15958 rtx dest_reg = (savres
15959 ? gen_rtx_REG (Pmode, 11)
15962 emit_insn (TARGET_32BIT
15963 ? gen_addsi3 (dest_reg, sp_reg_rtx,
15964 GEN_INT (sp_offset))
15965 : gen_adddi3 (dest_reg, sp_reg_rtx,
15966 GEN_INT (sp_offset)));
15970 /* Construct a parallel rtx describing the effect of a call to an
15971 out-of-line register save/restore routine. */
15974 rs6000_make_savres_rtx (rs6000_stack_t *info,
15975 rtx frame_reg_rtx, int save_area_offset,
15976 enum machine_mode reg_mode,
15977 bool savep, bool gpr, bool exitp)
15980 int offset, start_reg, end_reg, n_regs;
15981 int reg_size = GET_MODE_SIZE (reg_mode);
15987 ? info->first_gp_reg_save
15988 : info->first_fp_reg_save);
15989 end_reg = gpr ? 32 : 64;
15990 n_regs = end_reg - start_reg;
15991 p = rtvec_alloc ((exitp ? 4 : 3) + n_regs);
15993 /* If we're saving registers, then we should never say we're exiting. */
15994 gcc_assert ((savep && !exitp) || !savep);
15997 RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode);
15999 RTVEC_ELT (p, offset++)
16000 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65));
16002 sym = rs6000_savres_routine_sym (info, savep, gpr, exitp);
16003 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
16004 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 11));
16006 for (i = 0; i < end_reg - start_reg; i++)
16008 rtx addr, reg, mem;
16009 reg = gen_rtx_REG (reg_mode, start_reg + i);
16010 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16011 GEN_INT (save_area_offset + reg_size*i));
16012 mem = gen_frame_mem (reg_mode, addr);
16014 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
16016 savep ? reg : mem);
16019 return gen_rtx_PARALLEL (VOIDmode, p);
16022 /* Determine whether the gp REG is really used. */
16025 rs6000_reg_live_or_pic_offset_p (int reg)
16027 return ((df_regs_ever_live_p (reg)
16028 && (!call_used_regs[reg]
16029 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
16030 && TARGET_TOC && TARGET_MINIMAL_TOC)))
16031 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
16032 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
16033 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
16037 SAVRES_MULTIPLE = 0x1,
16038 SAVRES_INLINE_FPRS = 0x2,
16039 SAVRES_INLINE_GPRS = 0x4
16042 /* Determine the strategy for savings/restoring registers. */
16045 rs6000_savres_strategy (rs6000_stack_t *info, bool savep,
16046 int using_static_chain_p, int sibcall)
16048 bool using_multiple_p;
16050 bool savres_fprs_inline;
16051 bool savres_gprs_inline;
16052 bool noclobber_global_gprs
16053 = no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true);
16055 using_multiple_p = (TARGET_MULTIPLE && ! TARGET_POWERPC64
16056 && (!TARGET_SPE_ABI
16057 || info->spe_64bit_regs_used == 0)
16058 && info->first_gp_reg_save < 31
16059 && noclobber_global_gprs);
16060 /* Don't bother to try to save things out-of-line if r11 is occupied
16061 by the static chain. It would require too much fiddling and the
16062 static chain is rarely used anyway. */
16063 common = (using_static_chain_p
16065 || crtl->calls_eh_return
16066 || !info->lr_save_p
16067 || cfun->machine->ra_need_lr
16068 || info->total_size > 32767);
16069 savres_fprs_inline = (common
16070 || info->first_fp_reg_save == 64
16071 || !no_global_regs_above (info->first_fp_reg_save,
16073 || FP_SAVE_INLINE (info->first_fp_reg_save));
16074 savres_gprs_inline = (common
16075 /* Saving CR interferes with the exit routines
16076 used on the SPE, so just punt here. */
16079 && info->spe_64bit_regs_used != 0
16080 && info->cr_save_p != 0)
16081 || info->first_gp_reg_save == 32
16082 || !noclobber_global_gprs
16083 || GP_SAVE_INLINE (info->first_gp_reg_save));
16086 /* If we are going to use store multiple, then don't even bother
16087 with the out-of-line routines, since the store-multiple instruction
16088 will always be smaller. */
16089 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
16092 /* The situation is more complicated with load multiple. We'd
16093 prefer to use the out-of-line routines for restores, since the
16094 "exit" out-of-line routines can handle the restore of LR and
16095 the frame teardown. But we can only use the out-of-line
16096 routines if we know that we've used store multiple or
16097 out-of-line routines in the prologue, i.e. if we've saved all
16098 the registers from first_gp_reg_save. Otherwise, we risk
16099 loading garbage from the stack. Furthermore, we can only use
16100 the "exit" out-of-line gpr restore if we haven't saved any
16102 bool saved_all = !savres_gprs_inline || using_multiple_p;
16104 if (saved_all && info->first_fp_reg_save != 64)
16105 /* We can't use the exit routine; use load multiple if it's
16107 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
16110 return (using_multiple_p
16111 | (savres_fprs_inline << 1)
16112 | (savres_gprs_inline << 2));
16115 /* Emit function prologue as insns. */
16118 rs6000_emit_prologue (void)
16120 rs6000_stack_t *info = rs6000_stack_info ();
16121 enum machine_mode reg_mode = Pmode;
16122 int reg_size = TARGET_32BIT ? 4 : 8;
16123 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
16124 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
16125 rtx frame_reg_rtx = sp_reg_rtx;
16126 rtx cr_save_rtx = NULL_RTX;
16129 int saving_FPRs_inline;
16130 int saving_GPRs_inline;
16131 int using_store_multiple;
16132 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
16133 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
16134 && !call_used_regs[STATIC_CHAIN_REGNUM]);
16135 HOST_WIDE_INT sp_offset = 0;
16137 if (TARGET_FIX_AND_CONTINUE)
16139 /* gdb on darwin arranges to forward a function from the old
16140 address by modifying the first 5 instructions of the function
16141 to branch to the overriding function. This is necessary to
16142 permit function pointers that point to the old function to
16143 actually forward to the new function. */
16144 emit_insn (gen_nop ());
16145 emit_insn (gen_nop ());
16146 emit_insn (gen_nop ());
16147 emit_insn (gen_nop ());
16148 emit_insn (gen_nop ());
16151 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
16153 reg_mode = V2SImode;
16157 strategy = rs6000_savres_strategy (info, /*savep=*/true,
16158 /*static_chain_p=*/using_static_chain_p,
16160 using_store_multiple = strategy & SAVRES_MULTIPLE;
16161 saving_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
16162 saving_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
16164 /* For V.4, update stack before we do any saving and set back pointer. */
16165 if (! WORLD_SAVE_P (info)
16167 && (DEFAULT_ABI == ABI_V4
16168 || crtl->calls_eh_return))
16170 bool need_r11 = (TARGET_SPE
16171 ? (!saving_GPRs_inline
16172 && info->spe_64bit_regs_used == 0)
16173 : (!saving_FPRs_inline || !saving_GPRs_inline));
16174 if (info->total_size < 32767)
16175 sp_offset = info->total_size;
16177 frame_reg_rtx = (need_r11
16178 ? gen_rtx_REG (Pmode, 11)
16180 rs6000_emit_allocate_stack (info->total_size,
16181 (frame_reg_rtx != sp_reg_rtx
16182 && (info->cr_save_p
16184 || info->first_fp_reg_save < 64
16185 || info->first_gp_reg_save < 32
16188 if (frame_reg_rtx != sp_reg_rtx)
16189 rs6000_emit_stack_tie ();
16192 /* Handle world saves specially here. */
16193 if (WORLD_SAVE_P (info))
16200 /* save_world expects lr in r0. */
16201 reg0 = gen_rtx_REG (Pmode, 0);
16202 if (info->lr_save_p)
16204 insn = emit_move_insn (reg0,
16205 gen_rtx_REG (Pmode, LR_REGNO));
16206 RTX_FRAME_RELATED_P (insn) = 1;
16209 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
16210 assumptions about the offsets of various bits of the stack
16212 gcc_assert (info->gp_save_offset == -220
16213 && info->fp_save_offset == -144
16214 && info->lr_save_offset == 8
16215 && info->cr_save_offset == 4
16218 && (!crtl->calls_eh_return
16219 || info->ehrd_offset == -432)
16220 && info->vrsave_save_offset == -224
16221 && info->altivec_save_offset == -416);
16223 treg = gen_rtx_REG (SImode, 11);
16224 emit_move_insn (treg, GEN_INT (-info->total_size));
16226 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
16227 in R11. It also clobbers R12, so beware! */
16229 /* Preserve CR2 for save_world prologues */
16231 sz += 32 - info->first_gp_reg_save;
16232 sz += 64 - info->first_fp_reg_save;
16233 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
16234 p = rtvec_alloc (sz);
16236 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
16237 gen_rtx_REG (SImode,
16239 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16240 gen_rtx_SYMBOL_REF (Pmode,
16242 /* We do floats first so that the instruction pattern matches
16244 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16246 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
16247 ? DFmode : SFmode),
16248 info->first_fp_reg_save + i);
16249 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16250 GEN_INT (info->fp_save_offset
16251 + sp_offset + 8 * i));
16252 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
16253 ? DFmode : SFmode), addr);
16255 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16257 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16259 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16260 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16261 GEN_INT (info->altivec_save_offset
16262 + sp_offset + 16 * i));
16263 rtx mem = gen_frame_mem (V4SImode, addr);
16265 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16267 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16269 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16270 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16271 GEN_INT (info->gp_save_offset
16272 + sp_offset + reg_size * i));
16273 rtx mem = gen_frame_mem (reg_mode, addr);
16275 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16279 /* CR register traditionally saved as CR2. */
16280 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16281 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16282 GEN_INT (info->cr_save_offset
16284 rtx mem = gen_frame_mem (reg_mode, addr);
16286 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
16288 /* Explain about use of R0. */
16289 if (info->lr_save_p)
16291 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16292 GEN_INT (info->lr_save_offset
16294 rtx mem = gen_frame_mem (reg_mode, addr);
16296 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
16298 /* Explain what happens to the stack pointer. */
16300 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
16301 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
16304 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16305 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16306 treg, GEN_INT (-info->total_size));
16307 sp_offset = info->total_size;
16310 /* If we use the link register, get it into r0. */
16311 if (!WORLD_SAVE_P (info) && info->lr_save_p)
16313 rtx addr, reg, mem;
16315 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
16316 gen_rtx_REG (Pmode, LR_REGNO));
16317 RTX_FRAME_RELATED_P (insn) = 1;
16319 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16320 GEN_INT (info->lr_save_offset + sp_offset));
16321 reg = gen_rtx_REG (Pmode, 0);
16322 mem = gen_rtx_MEM (Pmode, addr);
16323 /* This should not be of rs6000_sr_alias_set, because of
16324 __builtin_return_address. */
16326 insn = emit_move_insn (mem, reg);
16327 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16328 NULL_RTX, NULL_RTX);
16331 /* If we need to save CR, put it into r12. */
16332 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
16336 cr_save_rtx = gen_rtx_REG (SImode, 12);
16337 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16338 RTX_FRAME_RELATED_P (insn) = 1;
16339 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16340 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16341 But that's OK. All we have to do is specify that _one_ condition
16342 code register is saved in this stack slot. The thrower's epilogue
16343 will then restore all the call-saved registers.
16344 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16345 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
16346 gen_rtx_REG (SImode, CR2_REGNO));
16347 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
16350 /* Do any required saving of fpr's. If only one or two to save, do
16351 it ourselves. Otherwise, call function. */
16352 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
16355 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16356 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16357 && ! call_used_regs[info->first_fp_reg_save+i]))
16358 emit_frame_save (frame_reg_rtx, frame_ptr_rtx,
16359 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
16361 info->first_fp_reg_save + i,
16362 info->fp_save_offset + sp_offset + 8 * i,
16365 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
16369 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16370 info->fp_save_offset + sp_offset,
16372 /*savep=*/true, /*gpr=*/false,
16374 insn = emit_insn (par);
16375 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16376 NULL_RTX, NULL_RTX);
16379 /* Save GPRs. This is done as a PARALLEL if we are using
16380 the store-multiple instructions. */
16381 if (!WORLD_SAVE_P (info)
16383 && info->spe_64bit_regs_used != 0
16384 && info->first_gp_reg_save != 32)
16387 rtx spe_save_area_ptr;
16389 /* Determine whether we can address all of the registers that need
16390 to be saved with an offset from the stack pointer that fits in
16391 the small const field for SPE memory instructions. */
16392 int spe_regs_addressable_via_sp
16393 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16394 + (32 - info->first_gp_reg_save - 1) * reg_size)
16395 && saving_GPRs_inline);
16398 if (spe_regs_addressable_via_sp)
16400 spe_save_area_ptr = frame_reg_rtx;
16401 spe_offset = info->spe_gp_save_offset + sp_offset;
16405 /* Make r11 point to the start of the SPE save area. We need
16406 to be careful here if r11 is holding the static chain. If
16407 it is, then temporarily save it in r0. We would use r0 as
16408 our base register here, but using r0 as a base register in
16409 loads and stores means something different from what we
16411 int ool_adjust = (saving_GPRs_inline
16413 : (info->first_gp_reg_save
16414 - (FIRST_SAVRES_REGISTER+1))*8);
16415 HOST_WIDE_INT offset = (info->spe_gp_save_offset
16416 + sp_offset - ool_adjust);
16418 if (using_static_chain_p)
16420 rtx r0 = gen_rtx_REG (Pmode, 0);
16421 gcc_assert (info->first_gp_reg_save > 11);
16423 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
16426 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
16427 insn = emit_insn (gen_addsi3 (spe_save_area_ptr,
16429 GEN_INT (offset)));
16430 /* We need to make sure the move to r11 gets noted for
16431 properly outputting unwind information. */
16432 if (!saving_GPRs_inline)
16433 rs6000_frame_related (insn, frame_reg_rtx, offset,
16434 NULL_RTX, NULL_RTX);
16438 if (saving_GPRs_inline)
16440 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16441 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16443 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16444 rtx offset, addr, mem;
16446 /* We're doing all this to ensure that the offset fits into
16447 the immediate offset of 'evstdd'. */
16448 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
16450 offset = GEN_INT (reg_size * i + spe_offset);
16451 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
16452 mem = gen_rtx_MEM (V2SImode, addr);
16454 insn = emit_move_insn (mem, reg);
16456 rs6000_frame_related (insn, spe_save_area_ptr,
16457 info->spe_gp_save_offset
16458 + sp_offset + reg_size * i,
16459 offset, const0_rtx);
16466 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
16468 /*savep=*/true, /*gpr=*/true,
16470 insn = emit_insn (par);
16471 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16472 NULL_RTX, NULL_RTX);
16476 /* Move the static chain pointer back. */
16477 if (using_static_chain_p && !spe_regs_addressable_via_sp)
16478 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
16480 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
16484 /* Need to adjust r11 if we saved any FPRs. */
16485 if (info->first_fp_reg_save != 64)
16487 rtx r11 = gen_rtx_REG (reg_mode, 11);
16488 rtx offset = GEN_INT (info->total_size
16489 + (-8 * (64-info->first_fp_reg_save)));
16490 rtx ptr_reg = (sp_reg_rtx == frame_reg_rtx
16491 ? sp_reg_rtx : r11);
16493 emit_insn (TARGET_32BIT
16494 ? gen_addsi3 (r11, ptr_reg, offset)
16495 : gen_adddi3 (r11, ptr_reg, offset));
16498 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
16499 info->gp_save_offset + sp_offset,
16501 /*savep=*/true, /*gpr=*/true,
16503 insn = emit_insn (par);
16504 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16505 NULL_RTX, NULL_RTX);
16507 else if (!WORLD_SAVE_P (info) && using_store_multiple)
16511 p = rtvec_alloc (32 - info->first_gp_reg_save);
16512 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16514 rtx addr, reg, mem;
16515 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16516 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16517 GEN_INT (info->gp_save_offset
16520 mem = gen_frame_mem (reg_mode, addr);
16522 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
16524 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16525 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16526 NULL_RTX, NULL_RTX);
16528 else if (!WORLD_SAVE_P (info))
16531 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16532 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16534 rtx addr, reg, mem;
16535 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16537 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16538 GEN_INT (info->gp_save_offset
16541 mem = gen_frame_mem (reg_mode, addr);
16543 insn = emit_move_insn (mem, reg);
16544 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16545 NULL_RTX, NULL_RTX);
16549 /* ??? There's no need to emit actual instructions here, but it's the
16550 easiest way to get the frame unwind information emitted. */
16551 if (crtl->calls_eh_return)
16553 unsigned int i, regno;
16555 /* In AIX ABI we need to pretend we save r2 here. */
16558 rtx addr, reg, mem;
16560 reg = gen_rtx_REG (reg_mode, 2);
16561 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16562 GEN_INT (sp_offset + 5 * reg_size));
16563 mem = gen_frame_mem (reg_mode, addr);
16565 insn = emit_move_insn (mem, reg);
16566 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16567 NULL_RTX, NULL_RTX);
16568 PATTERN (insn) = gen_blockage ();
16573 regno = EH_RETURN_DATA_REGNO (i);
16574 if (regno == INVALID_REGNUM)
16577 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
16578 info->ehrd_offset + sp_offset
16579 + reg_size * (int) i,
16584 /* Save CR if we use any that must be preserved. */
16585 if (!WORLD_SAVE_P (info) && info->cr_save_p)
16587 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16588 GEN_INT (info->cr_save_offset + sp_offset));
16589 rtx mem = gen_frame_mem (SImode, addr);
16590 /* See the large comment above about why CR2_REGNO is used. */
16591 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
16593 /* If r12 was used to hold the original sp, copy cr into r0 now
16595 if (REGNO (frame_reg_rtx) == 12)
16599 cr_save_rtx = gen_rtx_REG (SImode, 0);
16600 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
16601 RTX_FRAME_RELATED_P (insn) = 1;
16602 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
16603 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
16605 insn = emit_move_insn (mem, cr_save_rtx);
16607 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16608 NULL_RTX, NULL_RTX);
16611 /* Update stack and set back pointer unless this is V.4,
16612 for which it was done previously. */
16613 if (!WORLD_SAVE_P (info) && info->push_p
16614 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
16616 if (info->total_size < 32767)
16617 sp_offset = info->total_size;
16619 frame_reg_rtx = frame_ptr_rtx;
16620 rs6000_emit_allocate_stack (info->total_size,
16621 (frame_reg_rtx != sp_reg_rtx
16622 && ((info->altivec_size != 0)
16623 || (info->vrsave_mask != 0)
16626 if (frame_reg_rtx != sp_reg_rtx)
16627 rs6000_emit_stack_tie ();
16630 /* Set frame pointer, if needed. */
16631 if (frame_pointer_needed)
16633 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
16635 RTX_FRAME_RELATED_P (insn) = 1;
16638 /* Save AltiVec registers if needed. Save here because the red zone does
16639 not include AltiVec registers. */
16640 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16644 /* There should be a non inline version of this, for when we
16645 are saving lots of vector registers. */
16646 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16647 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16649 rtx areg, savereg, mem;
16652 offset = info->altivec_save_offset + sp_offset
16653 + 16 * (i - info->first_altivec_reg_save);
16655 savereg = gen_rtx_REG (V4SImode, i);
16657 areg = gen_rtx_REG (Pmode, 0);
16658 emit_move_insn (areg, GEN_INT (offset));
16660 /* AltiVec addressing mode is [reg+reg]. */
16661 mem = gen_frame_mem (V4SImode,
16662 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
16664 insn = emit_move_insn (mem, savereg);
16666 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
16667 areg, GEN_INT (offset));
16671 /* VRSAVE is a bit vector representing which AltiVec registers
16672 are used. The OS uses this to determine which vector
16673 registers to save on a context switch. We need to save
16674 VRSAVE on the stack frame, add whatever AltiVec registers we
16675 used in this function, and do the corresponding magic in the
16678 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16679 && info->vrsave_mask != 0)
16681 rtx reg, mem, vrsave;
16684 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16685 as frame_reg_rtx and r11 as the static chain pointer for
16686 nested functions. */
16687 reg = gen_rtx_REG (SImode, 0);
16688 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
16690 emit_insn (gen_get_vrsave_internal (reg));
16692 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
16694 if (!WORLD_SAVE_P (info))
16697 offset = info->vrsave_save_offset + sp_offset;
16698 mem = gen_frame_mem (SImode,
16699 gen_rtx_PLUS (Pmode, frame_reg_rtx,
16700 GEN_INT (offset)));
16701 insn = emit_move_insn (mem, reg);
16704 /* Include the registers in the mask. */
16705 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
16707 insn = emit_insn (generate_set_vrsave (reg, info, 0));
16710 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16711 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
16712 || (DEFAULT_ABI == ABI_V4
16713 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
16714 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
16716 /* If emit_load_toc_table will use the link register, we need to save
16717 it. We use R12 for this purpose because emit_load_toc_table
16718 can use register 0. This allows us to use a plain 'blr' to return
16719 from the procedure more often. */
16720 int save_LR_around_toc_setup = (TARGET_ELF
16721 && DEFAULT_ABI != ABI_AIX
16723 && ! info->lr_save_p
16724 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
16725 if (save_LR_around_toc_setup)
16727 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16729 insn = emit_move_insn (frame_ptr_rtx, lr);
16730 RTX_FRAME_RELATED_P (insn) = 1;
16732 rs6000_emit_load_toc_table (TRUE);
16734 insn = emit_move_insn (lr, frame_ptr_rtx);
16735 RTX_FRAME_RELATED_P (insn) = 1;
16738 rs6000_emit_load_toc_table (TRUE);
16742 if (DEFAULT_ABI == ABI_DARWIN
16743 && flag_pic && crtl->uses_pic_offset_table)
16745 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
16746 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
16748 /* Save and restore LR locally around this call (in R0). */
16749 if (!info->lr_save_p)
16750 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
16752 emit_insn (gen_load_macho_picbase (src));
16754 emit_move_insn (gen_rtx_REG (Pmode,
16755 RS6000_PIC_OFFSET_TABLE_REGNUM),
16758 if (!info->lr_save_p)
16759 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
16764 /* Write function prologue. */
16767 rs6000_output_function_prologue (FILE *file,
16768 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16770 rs6000_stack_t *info = rs6000_stack_info ();
16772 if (TARGET_DEBUG_STACK)
16773 debug_stack_info (info);
16775 /* Write .extern for any function we will call to save and restore
16777 if (info->first_fp_reg_save < 64
16778 && !FP_SAVE_INLINE (info->first_fp_reg_save))
16779 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16780 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
16781 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16783 /* Write .extern for AIX common mode routines, if needed. */
16784 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
16786 fputs ("\t.extern __mulh\n", file);
16787 fputs ("\t.extern __mull\n", file);
16788 fputs ("\t.extern __divss\n", file);
16789 fputs ("\t.extern __divus\n", file);
16790 fputs ("\t.extern __quoss\n", file);
16791 fputs ("\t.extern __quous\n", file);
16792 common_mode_defined = 1;
16795 if (! HAVE_prologue)
16799 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16800 the "toplevel" insn chain. */
16801 emit_note (NOTE_INSN_DELETED);
16802 rs6000_emit_prologue ();
16803 emit_note (NOTE_INSN_DELETED);
16805 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16809 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16811 INSN_ADDRESSES_NEW (insn, addr);
16816 if (TARGET_DEBUG_STACK)
16817 debug_rtx_list (get_insns (), 100);
16818 final (get_insns (), file, FALSE);
16822 rs6000_pic_labelno++;
16825 /* Non-zero if vmx regs are restored before the frame pop, zero if
16826 we restore after the pop when possible. */
16827 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16829 /* Reload CR from REG. */
16832 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
16837 if (using_mfcr_multiple)
16839 for (i = 0; i < 8; i++)
16840 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16842 gcc_assert (count);
16845 if (using_mfcr_multiple && count > 1)
16850 p = rtvec_alloc (count);
16853 for (i = 0; i < 8; i++)
16854 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16856 rtvec r = rtvec_alloc (2);
16857 RTVEC_ELT (r, 0) = reg;
16858 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16859 RTVEC_ELT (p, ndx) =
16860 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16861 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16864 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16865 gcc_assert (ndx == count);
16868 for (i = 0; i < 8; i++)
16869 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16871 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16877 /* Emit function epilogue as insns.
16879 At present, dwarf2out_frame_debug_expr doesn't understand
16880 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16881 anywhere in the epilogue. Most of the insns below would in any case
16882 need special notes to explain where r11 is in relation to the stack. */
16885 rs6000_emit_epilogue (int sibcall)
16887 rs6000_stack_t *info;
16888 int restoring_GPRs_inline;
16889 int restoring_FPRs_inline;
16890 int using_load_multiple;
16891 int using_mtcr_multiple;
16892 int use_backchain_to_restore_sp;
16896 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
16897 rtx frame_reg_rtx = sp_reg_rtx;
16898 enum machine_mode reg_mode = Pmode;
16899 int reg_size = TARGET_32BIT ? 4 : 8;
16902 info = rs6000_stack_info ();
16904 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
16906 reg_mode = V2SImode;
16910 strategy = rs6000_savres_strategy (info, /*savep=*/false,
16911 /*static_chain_p=*/0, sibcall);
16912 using_load_multiple = strategy & SAVRES_MULTIPLE;
16913 restoring_FPRs_inline = strategy & SAVRES_INLINE_FPRS;
16914 restoring_GPRs_inline = strategy & SAVRES_INLINE_GPRS;
16915 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
16916 || rs6000_cpu == PROCESSOR_PPC603
16917 || rs6000_cpu == PROCESSOR_PPC750
16919 /* Restore via the backchain when we have a large frame, since this
16920 is more efficient than an addis, addi pair. The second condition
16921 here will not trigger at the moment; We don't actually need a
16922 frame pointer for alloca, but the generic parts of the compiler
16923 give us one anyway. */
16924 use_backchain_to_restore_sp = (info->total_size > 32767
16925 || info->total_size
16926 + (info->lr_save_p ? info->lr_save_offset : 0)
16928 || (cfun->calls_alloca
16929 && !frame_pointer_needed));
16930 restore_lr = (info->lr_save_p
16931 && restoring_GPRs_inline
16932 && restoring_FPRs_inline);
16934 if (WORLD_SAVE_P (info))
16938 const char *alloc_rname;
16941 /* eh_rest_world_r10 will return to the location saved in the LR
16942 stack slot (which is not likely to be our caller.)
16943 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16944 rest_world is similar, except any R10 parameter is ignored.
16945 The exception-handling stuff that was here in 2.95 is no
16946 longer necessary. */
16950 + 32 - info->first_gp_reg_save
16951 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
16952 + 63 + 1 - info->first_fp_reg_save);
16954 strcpy (rname, ((crtl->calls_eh_return) ?
16955 "*eh_rest_world_r10" : "*rest_world"));
16956 alloc_rname = ggc_strdup (rname);
16959 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
16960 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
16961 gen_rtx_REG (Pmode,
16964 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
16965 /* The instruction pattern requires a clobber here;
16966 it is shared with the restVEC helper. */
16968 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
16971 /* CR register traditionally saved as CR2. */
16972 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16973 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16974 GEN_INT (info->cr_save_offset));
16975 rtx mem = gen_frame_mem (reg_mode, addr);
16977 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16980 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16982 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16983 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16984 GEN_INT (info->gp_save_offset
16986 rtx mem = gen_frame_mem (reg_mode, addr);
16988 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16990 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16992 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16993 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16994 GEN_INT (info->altivec_save_offset
16996 rtx mem = gen_frame_mem (V4SImode, addr);
16998 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
17000 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
17002 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
17003 ? DFmode : SFmode),
17004 info->first_fp_reg_save + i);
17005 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17006 GEN_INT (info->fp_save_offset
17008 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
17009 ? DFmode : SFmode), addr);
17011 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
17014 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
17016 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
17018 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
17020 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
17022 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
17023 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
17028 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
17030 sp_offset = info->total_size;
17032 /* Restore AltiVec registers if we must do so before adjusting the
17034 if (TARGET_ALTIVEC_ABI
17035 && info->altivec_size != 0
17036 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17037 || (DEFAULT_ABI != ABI_V4
17038 && info->altivec_save_offset < (TARGET_32BIT ? -220 : -288))))
17042 if (use_backchain_to_restore_sp)
17044 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17045 emit_move_insn (frame_reg_rtx,
17046 gen_rtx_MEM (Pmode, sp_reg_rtx));
17049 else if (frame_pointer_needed)
17050 frame_reg_rtx = hard_frame_pointer_rtx;
17052 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
17053 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
17055 rtx addr, areg, mem;
17057 areg = gen_rtx_REG (Pmode, 0);
17059 (areg, GEN_INT (info->altivec_save_offset
17061 + 16 * (i - info->first_altivec_reg_save)));
17063 /* AltiVec addressing mode is [reg+reg]. */
17064 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
17065 mem = gen_frame_mem (V4SImode, addr);
17067 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
17071 /* Restore VRSAVE if we must do so before adjusting the stack. */
17073 && TARGET_ALTIVEC_VRSAVE
17074 && info->vrsave_mask != 0
17075 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17076 || (DEFAULT_ABI != ABI_V4
17077 && info->vrsave_save_offset < (TARGET_32BIT ? -220 : -288))))
17079 rtx addr, mem, reg;
17081 if (frame_reg_rtx == sp_reg_rtx)
17083 if (use_backchain_to_restore_sp)
17085 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17086 emit_move_insn (frame_reg_rtx,
17087 gen_rtx_MEM (Pmode, sp_reg_rtx));
17090 else if (frame_pointer_needed)
17091 frame_reg_rtx = hard_frame_pointer_rtx;
17094 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17095 GEN_INT (info->vrsave_save_offset + sp_offset));
17096 mem = gen_frame_mem (SImode, addr);
17097 reg = gen_rtx_REG (SImode, 12);
17098 emit_move_insn (reg, mem);
17100 emit_insn (generate_set_vrsave (reg, info, 1));
17103 /* If we have a large stack frame, restore the old stack pointer
17104 using the backchain. */
17105 if (use_backchain_to_restore_sp)
17107 if (frame_reg_rtx == sp_reg_rtx)
17109 /* Under V.4, don't reset the stack pointer until after we're done
17110 loading the saved registers. */
17111 if (DEFAULT_ABI == ABI_V4)
17112 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17114 emit_move_insn (frame_reg_rtx,
17115 gen_rtx_MEM (Pmode, sp_reg_rtx));
17118 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17119 && DEFAULT_ABI == ABI_V4)
17120 /* frame_reg_rtx has been set up by the altivec restore. */
17124 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
17125 frame_reg_rtx = sp_reg_rtx;
17128 /* If we have a frame pointer, we can restore the old stack pointer
17130 else if (frame_pointer_needed)
17132 frame_reg_rtx = sp_reg_rtx;
17133 if (DEFAULT_ABI == ABI_V4)
17134 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17136 emit_insn (TARGET_32BIT
17137 ? gen_addsi3 (frame_reg_rtx, hard_frame_pointer_rtx,
17138 GEN_INT (info->total_size))
17139 : gen_adddi3 (frame_reg_rtx, hard_frame_pointer_rtx,
17140 GEN_INT (info->total_size)));
17143 else if (info->push_p
17144 && DEFAULT_ABI != ABI_V4
17145 && !crtl->calls_eh_return)
17147 emit_insn (TARGET_32BIT
17148 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
17149 GEN_INT (info->total_size))
17150 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
17151 GEN_INT (info->total_size)));
17155 /* Restore AltiVec registers if we have not done so already. */
17156 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17157 && TARGET_ALTIVEC_ABI
17158 && info->altivec_size != 0
17159 && (DEFAULT_ABI == ABI_V4
17160 || info->altivec_save_offset >= (TARGET_32BIT ? -220 : -288)))
17164 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
17165 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
17167 rtx addr, areg, mem;
17169 areg = gen_rtx_REG (Pmode, 0);
17171 (areg, GEN_INT (info->altivec_save_offset
17173 + 16 * (i - info->first_altivec_reg_save)));
17175 /* AltiVec addressing mode is [reg+reg]. */
17176 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
17177 mem = gen_frame_mem (V4SImode, addr);
17179 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
17183 /* Restore VRSAVE if we have not done so already. */
17184 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17186 && TARGET_ALTIVEC_VRSAVE
17187 && info->vrsave_mask != 0
17188 && (DEFAULT_ABI == ABI_V4
17189 || info->vrsave_save_offset >= (TARGET_32BIT ? -220 : -288)))
17191 rtx addr, mem, reg;
17193 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17194 GEN_INT (info->vrsave_save_offset + sp_offset));
17195 mem = gen_frame_mem (SImode, addr);
17196 reg = gen_rtx_REG (SImode, 12);
17197 emit_move_insn (reg, mem);
17199 emit_insn (generate_set_vrsave (reg, info, 1));
17202 /* Get the old lr if we saved it. If we are restoring registers
17203 out-of-line, then the out-of-line routines can do this for us. */
17206 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
17207 info->lr_save_offset + sp_offset);
17209 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
17212 /* Get the old cr if we saved it. */
17213 if (info->cr_save_p)
17215 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17216 GEN_INT (info->cr_save_offset + sp_offset));
17217 rtx mem = gen_frame_mem (SImode, addr);
17219 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
17222 /* Set LR here to try to overlap restores below. */
17224 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
17225 gen_rtx_REG (Pmode, 0));
17227 /* Load exception handler data registers, if needed. */
17228 if (crtl->calls_eh_return)
17230 unsigned int i, regno;
17234 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17235 GEN_INT (sp_offset + 5 * reg_size));
17236 rtx mem = gen_frame_mem (reg_mode, addr);
17238 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
17245 regno = EH_RETURN_DATA_REGNO (i);
17246 if (regno == INVALID_REGNUM)
17249 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
17250 info->ehrd_offset + sp_offset
17251 + reg_size * (int) i);
17253 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
17257 /* Restore GPRs. This is done as a PARALLEL if we are using
17258 the load-multiple instructions. */
17260 && info->spe_64bit_regs_used != 0
17261 && info->first_gp_reg_save != 32)
17263 /* Determine whether we can address all of the registers that need
17264 to be saved with an offset from the stack pointer that fits in
17265 the small const field for SPE memory instructions. */
17266 int spe_regs_addressable_via_sp
17267 = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
17268 + (32 - info->first_gp_reg_save - 1) * reg_size)
17269 && restoring_GPRs_inline);
17272 if (spe_regs_addressable_via_sp)
17273 spe_offset = info->spe_gp_save_offset + sp_offset;
17276 rtx old_frame_reg_rtx = frame_reg_rtx;
17277 /* Make r11 point to the start of the SPE save area. We worried about
17278 not clobbering it when we were saving registers in the prologue.
17279 There's no need to worry here because the static chain is passed
17280 anew to every function. */
17281 int ool_adjust = (restoring_GPRs_inline
17283 : (info->first_gp_reg_save
17284 - (FIRST_SAVRES_REGISTER+1))*8);
17286 if (frame_reg_rtx == sp_reg_rtx)
17287 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
17288 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
17289 GEN_INT (info->spe_gp_save_offset
17292 /* Keep the invariant that frame_reg_rtx + sp_offset points
17293 at the top of the stack frame. */
17294 sp_offset = -info->spe_gp_save_offset;
17299 if (restoring_GPRs_inline)
17301 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17302 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17304 rtx offset, addr, mem;
17306 /* We're doing all this to ensure that the immediate offset
17307 fits into the immediate field of 'evldd'. */
17308 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
17310 offset = GEN_INT (spe_offset + reg_size * i);
17311 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
17312 mem = gen_rtx_MEM (V2SImode, addr);
17314 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17322 par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11),
17324 /*savep=*/false, /*gpr=*/true,
17326 emit_jump_insn (par);
17328 /* We don't want anybody else emitting things after we jumped
17333 else if (!restoring_GPRs_inline)
17335 /* We are jumping to an out-of-line function. */
17336 bool can_use_exit = info->first_fp_reg_save == 64;
17339 /* Emit stack reset code if we need it. */
17341 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17342 sp_offset, can_use_exit);
17344 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode, 11),
17346 GEN_INT (sp_offset - info->fp_size)));
17348 par = rs6000_make_savres_rtx (info, frame_reg_rtx,
17349 info->gp_save_offset, reg_mode,
17350 /*savep=*/false, /*gpr=*/true,
17351 /*exitp=*/can_use_exit);
17355 if (info->cr_save_p)
17356 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12),
17357 using_mtcr_multiple);
17359 emit_jump_insn (par);
17361 /* We don't want anybody else emitting things after we jumped
17368 else if (using_load_multiple)
17371 p = rtvec_alloc (32 - info->first_gp_reg_save);
17372 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17374 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17375 GEN_INT (info->gp_save_offset
17378 rtx mem = gen_frame_mem (reg_mode, addr);
17381 gen_rtx_SET (VOIDmode,
17382 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
17385 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
17389 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
17390 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
17392 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17393 GEN_INT (info->gp_save_offset
17396 rtx mem = gen_frame_mem (reg_mode, addr);
17398 emit_move_insn (gen_rtx_REG (reg_mode,
17399 info->first_gp_reg_save + i), mem);
17403 /* Restore fpr's if we need to do it without calling a function. */
17404 if (restoring_FPRs_inline)
17405 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17406 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
17407 && ! call_used_regs[info->first_fp_reg_save+i]))
17410 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
17411 GEN_INT (info->fp_save_offset
17414 mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
17415 ? DFmode : SFmode), addr);
17417 emit_move_insn (gen_rtx_REG (((TARGET_HARD_FLOAT
17418 && TARGET_DOUBLE_FLOAT)
17419 ? DFmode : SFmode),
17420 info->first_fp_reg_save + i),
17424 /* If we saved cr, restore it here. Just those that were used. */
17425 if (info->cr_save_p)
17426 rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12), using_mtcr_multiple);
17428 /* If this is V.4, unwind the stack pointer after all of the loads
17430 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
17431 sp_offset, !restoring_FPRs_inline);
17433 if (crtl->calls_eh_return)
17435 rtx sa = EH_RETURN_STACKADJ_RTX;
17436 emit_insn (TARGET_32BIT
17437 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
17438 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
17444 if (! restoring_FPRs_inline)
17445 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
17447 p = rtvec_alloc (2);
17449 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
17450 RTVEC_ELT (p, 1) = (restoring_FPRs_inline
17451 ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65))
17452 : gen_rtx_CLOBBER (VOIDmode,
17453 gen_rtx_REG (Pmode, 65)));
17455 /* If we have to restore more than two FP registers, branch to the
17456 restore function. It will return to our caller. */
17457 if (! restoring_FPRs_inline)
17462 sym = rs6000_savres_routine_sym (info,
17466 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
17467 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
17468 gen_rtx_REG (Pmode, 11));
17469 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
17472 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
17473 GEN_INT (info->fp_save_offset + 8*i));
17474 mem = gen_frame_mem (DFmode, addr);
17476 RTVEC_ELT (p, i+4) =
17477 gen_rtx_SET (VOIDmode,
17478 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
17483 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
17487 /* Write function epilogue. */
17490 rs6000_output_function_epilogue (FILE *file,
17491 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
17493 if (! HAVE_epilogue)
17495 rtx insn = get_last_insn ();
17496 /* If the last insn was a BARRIER, we don't have to write anything except
17497 the trace table. */
17498 if (GET_CODE (insn) == NOTE)
17499 insn = prev_nonnote_insn (insn);
17500 if (insn == 0 || GET_CODE (insn) != BARRIER)
17502 /* This is slightly ugly, but at least we don't have two
17503 copies of the epilogue-emitting code. */
17506 /* A NOTE_INSN_DELETED is supposed to be at the start
17507 and end of the "toplevel" insn chain. */
17508 emit_note (NOTE_INSN_DELETED);
17509 rs6000_emit_epilogue (FALSE);
17510 emit_note (NOTE_INSN_DELETED);
17512 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17516 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
17518 INSN_ADDRESSES_NEW (insn, addr);
17523 if (TARGET_DEBUG_STACK)
17524 debug_rtx_list (get_insns (), 100);
17525 final (get_insns (), file, FALSE);
17531 macho_branch_islands ();
17532 /* Mach-O doesn't support labels at the end of objects, so if
17533 it looks like we might want one, insert a NOP. */
17535 rtx insn = get_last_insn ();
17538 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
17539 insn = PREV_INSN (insn);
17543 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
17544 fputs ("\tnop\n", file);
17548 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17551 We don't output a traceback table if -finhibit-size-directive was
17552 used. The documentation for -finhibit-size-directive reads
17553 ``don't output a @code{.size} assembler directive, or anything
17554 else that would cause trouble if the function is split in the
17555 middle, and the two halves are placed at locations far apart in
17556 memory.'' The traceback table has this property, since it
17557 includes the offset from the start of the function to the
17558 traceback table itself.
17560 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17561 different traceback table. */
17562 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
17563 && rs6000_traceback != traceback_none && !cfun->is_thunk)
17565 const char *fname = NULL;
17566 const char *language_string = lang_hooks.name;
17567 int fixed_parms = 0, float_parms = 0, parm_info = 0;
17569 int optional_tbtab;
17570 rs6000_stack_t *info = rs6000_stack_info ();
17572 if (rs6000_traceback == traceback_full)
17573 optional_tbtab = 1;
17574 else if (rs6000_traceback == traceback_part)
17575 optional_tbtab = 0;
17577 optional_tbtab = !optimize_size && !TARGET_ELF;
17579 if (optional_tbtab)
17581 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
17582 while (*fname == '.') /* V.4 encodes . in the name */
17585 /* Need label immediately before tbtab, so we can compute
17586 its offset from the function start. */
17587 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17588 ASM_OUTPUT_LABEL (file, fname);
17591 /* The .tbtab pseudo-op can only be used for the first eight
17592 expressions, since it can't handle the possibly variable
17593 length fields that follow. However, if you omit the optional
17594 fields, the assembler outputs zeros for all optional fields
17595 anyways, giving each variable length field is minimum length
17596 (as defined in sys/debug.h). Thus we can not use the .tbtab
17597 pseudo-op at all. */
17599 /* An all-zero word flags the start of the tbtab, for debuggers
17600 that have to find it by searching forward from the entry
17601 point or from the current pc. */
17602 fputs ("\t.long 0\n", file);
17604 /* Tbtab format type. Use format type 0. */
17605 fputs ("\t.byte 0,", file);
17607 /* Language type. Unfortunately, there does not seem to be any
17608 official way to discover the language being compiled, so we
17609 use language_string.
17610 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17611 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17612 a number, so for now use 9. */
17613 if (! strcmp (language_string, "GNU C"))
17615 else if (! strcmp (language_string, "GNU F77")
17616 || ! strcmp (language_string, "GNU Fortran"))
17618 else if (! strcmp (language_string, "GNU Pascal"))
17620 else if (! strcmp (language_string, "GNU Ada"))
17622 else if (! strcmp (language_string, "GNU C++")
17623 || ! strcmp (language_string, "GNU Objective-C++"))
17625 else if (! strcmp (language_string, "GNU Java"))
17627 else if (! strcmp (language_string, "GNU Objective-C"))
17630 gcc_unreachable ();
17631 fprintf (file, "%d,", i);
17633 /* 8 single bit fields: global linkage (not set for C extern linkage,
17634 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17635 from start of procedure stored in tbtab, internal function, function
17636 has controlled storage, function has no toc, function uses fp,
17637 function logs/aborts fp operations. */
17638 /* Assume that fp operations are used if any fp reg must be saved. */
17639 fprintf (file, "%d,",
17640 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
17642 /* 6 bitfields: function is interrupt handler, name present in
17643 proc table, function calls alloca, on condition directives
17644 (controls stack walks, 3 bits), saves condition reg, saves
17646 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17647 set up as a frame pointer, even when there is no alloca call. */
17648 fprintf (file, "%d,",
17649 ((optional_tbtab << 6)
17650 | ((optional_tbtab & frame_pointer_needed) << 5)
17651 | (info->cr_save_p << 1)
17652 | (info->lr_save_p)));
17654 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17656 fprintf (file, "%d,",
17657 (info->push_p << 7) | (64 - info->first_fp_reg_save));
17659 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17660 fprintf (file, "%d,", (32 - first_reg_to_save ()));
17662 if (optional_tbtab)
17664 /* Compute the parameter info from the function decl argument
17667 int next_parm_info_bit = 31;
17669 for (decl = DECL_ARGUMENTS (current_function_decl);
17670 decl; decl = TREE_CHAIN (decl))
17672 rtx parameter = DECL_INCOMING_RTL (decl);
17673 enum machine_mode mode = GET_MODE (parameter);
17675 if (GET_CODE (parameter) == REG)
17677 if (SCALAR_FLOAT_MODE_P (mode))
17698 gcc_unreachable ();
17701 /* If only one bit will fit, don't or in this entry. */
17702 if (next_parm_info_bit > 0)
17703 parm_info |= (bits << (next_parm_info_bit - 1));
17704 next_parm_info_bit -= 2;
17708 fixed_parms += ((GET_MODE_SIZE (mode)
17709 + (UNITS_PER_WORD - 1))
17711 next_parm_info_bit -= 1;
17717 /* Number of fixed point parameters. */
17718 /* This is actually the number of words of fixed point parameters; thus
17719 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17720 fprintf (file, "%d,", fixed_parms);
17722 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17724 /* This is actually the number of fp registers that hold parameters;
17725 and thus the maximum value is 13. */
17726 /* Set parameters on stack bit if parameters are not in their original
17727 registers, regardless of whether they are on the stack? Xlc
17728 seems to set the bit when not optimizing. */
17729 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
17731 if (! optional_tbtab)
17734 /* Optional fields follow. Some are variable length. */
17736 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17737 11 double float. */
17738 /* There is an entry for each parameter in a register, in the order that
17739 they occur in the parameter list. Any intervening arguments on the
17740 stack are ignored. If the list overflows a long (max possible length
17741 34 bits) then completely leave off all elements that don't fit. */
17742 /* Only emit this long if there was at least one parameter. */
17743 if (fixed_parms || float_parms)
17744 fprintf (file, "\t.long %d\n", parm_info);
17746 /* Offset from start of code to tb table. */
17747 fputs ("\t.long ", file);
17748 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
17750 RS6000_OUTPUT_BASENAME (file, fname);
17752 assemble_name (file, fname);
17754 rs6000_output_function_entry (file, fname);
17757 /* Interrupt handler mask. */
17758 /* Omit this long, since we never set the interrupt handler bit
17761 /* Number of CTL (controlled storage) anchors. */
17762 /* Omit this long, since the has_ctl bit is never set above. */
17764 /* Displacement into stack of each CTL anchor. */
17765 /* Omit this list of longs, because there are no CTL anchors. */
17767 /* Length of function name. */
17770 fprintf (file, "\t.short %d\n", (int) strlen (fname));
17772 /* Function name. */
17773 assemble_string (fname, strlen (fname));
17775 /* Register for alloca automatic storage; this is always reg 31.
17776 Only emit this if the alloca bit was set above. */
17777 if (frame_pointer_needed)
17778 fputs ("\t.byte 31\n", file);
17780 fputs ("\t.align 2\n", file);
17784 /* A C compound statement that outputs the assembler code for a thunk
17785 function, used to implement C++ virtual function calls with
17786 multiple inheritance. The thunk acts as a wrapper around a virtual
17787 function, adjusting the implicit object parameter before handing
17788 control off to the real function.
17790 First, emit code to add the integer DELTA to the location that
17791 contains the incoming first argument. Assume that this argument
17792 contains a pointer, and is the one used to pass the `this' pointer
17793 in C++. This is the incoming argument *before* the function
17794 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17795 values of all other incoming arguments.
17797 After the addition, emit code to jump to FUNCTION, which is a
17798 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17799 not touch the return address. Hence returning from FUNCTION will
17800 return to whoever called the current `thunk'.
17802 The effect must be as if FUNCTION had been called directly with the
17803 adjusted first argument. This macro is responsible for emitting
17804 all of the code for a thunk function; output_function_prologue()
17805 and output_function_epilogue() are not invoked.
17807 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17808 been extracted from it.) It might possibly be useful on some
17809 targets, but probably not.
17811 If you do not define this macro, the target-independent code in the
17812 C++ frontend will generate a less efficient heavyweight thunk that
17813 calls FUNCTION instead of jumping to it. The generic approach does
17814 not support varargs. */
17817 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
17818 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
17821 rtx this_rtx, insn, funexp;
17823 reload_completed = 1;
17824 epilogue_completed = 1;
17826 /* Mark the end of the (empty) prologue. */
17827 emit_note (NOTE_INSN_PROLOGUE_END);
17829 /* Find the "this" pointer. If the function returns a structure,
17830 the structure return pointer is in r3. */
17831 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
17832 this_rtx = gen_rtx_REG (Pmode, 4);
17834 this_rtx = gen_rtx_REG (Pmode, 3);
17836 /* Apply the constant offset, if required. */
17839 rtx delta_rtx = GEN_INT (delta);
17840 emit_insn (TARGET_32BIT
17841 ? gen_addsi3 (this_rtx, this_rtx, delta_rtx)
17842 : gen_adddi3 (this_rtx, this_rtx, delta_rtx));
17845 /* Apply the offset from the vtable, if required. */
17848 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
17849 rtx tmp = gen_rtx_REG (Pmode, 12);
17851 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
17852 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
17854 emit_insn (TARGET_32BIT
17855 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
17856 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
17857 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
17861 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
17863 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
17865 emit_insn (TARGET_32BIT
17866 ? gen_addsi3 (this_rtx, this_rtx, tmp)
17867 : gen_adddi3 (this_rtx, this_rtx, tmp));
17870 /* Generate a tail call to the target function. */
17871 if (!TREE_USED (function))
17873 assemble_external (function);
17874 TREE_USED (function) = 1;
17876 funexp = XEXP (DECL_RTL (function), 0);
17877 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
17880 if (MACHOPIC_INDIRECT)
17881 funexp = machopic_indirect_call_target (funexp);
17884 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17885 generate sibcall RTL explicitly. */
17886 insn = emit_call_insn (
17887 gen_rtx_PARALLEL (VOIDmode,
17889 gen_rtx_CALL (VOIDmode,
17890 funexp, const0_rtx),
17891 gen_rtx_USE (VOIDmode, const0_rtx),
17892 gen_rtx_USE (VOIDmode,
17893 gen_rtx_REG (SImode,
17895 gen_rtx_RETURN (VOIDmode))));
17896 SIBLING_CALL_P (insn) = 1;
17899 /* Run just enough of rest_of_compilation to get the insns emitted.
17900 There's not really enough bulk here to make other passes such as
17901 instruction scheduling worth while. Note that use_thunk calls
17902 assemble_start_function and assemble_end_function. */
17903 insn = get_insns ();
17904 insn_locators_alloc ();
17905 shorten_branches (insn);
17906 final_start_function (insn, file, 1);
17907 final (insn, file, 1);
17908 final_end_function ();
17909 free_after_compilation (cfun);
17911 reload_completed = 0;
17912 epilogue_completed = 0;
17915 /* A quick summary of the various types of 'constant-pool tables'
17918 Target Flags Name One table per
17919 AIX (none) AIX TOC object file
17920 AIX -mfull-toc AIX TOC object file
17921 AIX -mminimal-toc AIX minimal TOC translation unit
17922 SVR4/EABI (none) SVR4 SDATA object file
17923 SVR4/EABI -fpic SVR4 pic object file
17924 SVR4/EABI -fPIC SVR4 PIC translation unit
17925 SVR4/EABI -mrelocatable EABI TOC function
17926 SVR4/EABI -maix AIX TOC object file
17927 SVR4/EABI -maix -mminimal-toc
17928 AIX minimal TOC translation unit
17930 Name Reg. Set by entries contains:
17931 made by addrs? fp? sum?
17933 AIX TOC 2 crt0 as Y option option
17934 AIX minimal TOC 30 prolog gcc Y Y option
17935 SVR4 SDATA 13 crt0 gcc N Y N
17936 SVR4 pic 30 prolog ld Y not yet N
17937 SVR4 PIC 30 prolog gcc Y option option
17938 EABI TOC 30 prolog gcc Y option option
17942 /* Hash functions for the hash table. */
17945 rs6000_hash_constant (rtx k)
17947 enum rtx_code code = GET_CODE (k);
17948 enum machine_mode mode = GET_MODE (k);
17949 unsigned result = (code << 3) ^ mode;
17950 const char *format;
17953 format = GET_RTX_FORMAT (code);
17954 flen = strlen (format);
17960 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
17963 if (mode != VOIDmode)
17964 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
17976 for (; fidx < flen; fidx++)
17977 switch (format[fidx])
17982 const char *str = XSTR (k, fidx);
17983 len = strlen (str);
17984 result = result * 613 + len;
17985 for (i = 0; i < len; i++)
17986 result = result * 613 + (unsigned) str[i];
17991 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
17995 result = result * 613 + (unsigned) XINT (k, fidx);
17998 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
17999 result = result * 613 + (unsigned) XWINT (k, fidx);
18003 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
18004 result = result * 613 + (unsigned) (XWINT (k, fidx)
18011 gcc_unreachable ();
18018 toc_hash_function (const void *hash_entry)
18020 const struct toc_hash_struct *thc =
18021 (const struct toc_hash_struct *) hash_entry;
18022 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
18025 /* Compare H1 and H2 for equivalence. */
18028 toc_hash_eq (const void *h1, const void *h2)
18030 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
18031 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
18033 if (((const struct toc_hash_struct *) h1)->key_mode
18034 != ((const struct toc_hash_struct *) h2)->key_mode)
18037 return rtx_equal_p (r1, r2);
18040 /* These are the names given by the C++ front-end to vtables, and
18041 vtable-like objects. Ideally, this logic should not be here;
18042 instead, there should be some programmatic way of inquiring as
18043 to whether or not an object is a vtable. */
18045 #define VTABLE_NAME_P(NAME) \
18046 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
18047 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
18048 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
18049 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
18050 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
18052 #ifdef NO_DOLLAR_IN_LABEL
18053 /* Return a GGC-allocated character string translating dollar signs in
18054 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
18057 rs6000_xcoff_strip_dollar (const char *name)
18062 p = strchr (name, '$');
18064 if (p == 0 || p == name)
18067 len = strlen (name);
18068 strip = (char *) alloca (len + 1);
18069 strcpy (strip, name);
18070 p = strchr (strip, '$');
18074 p = strchr (p + 1, '$');
18077 return ggc_alloc_string (strip, len);
18082 rs6000_output_symbol_ref (FILE *file, rtx x)
18084 /* Currently C++ toc references to vtables can be emitted before it
18085 is decided whether the vtable is public or private. If this is
18086 the case, then the linker will eventually complain that there is
18087 a reference to an unknown section. Thus, for vtables only,
18088 we emit the TOC reference to reference the symbol and not the
18090 const char *name = XSTR (x, 0);
18092 if (VTABLE_NAME_P (name))
18094 RS6000_OUTPUT_BASENAME (file, name);
18097 assemble_name (file, name);
18100 /* Output a TOC entry. We derive the entry name from what is being
18104 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
18107 const char *name = buf;
18109 HOST_WIDE_INT offset = 0;
18111 gcc_assert (!TARGET_NO_TOC);
18113 /* When the linker won't eliminate them, don't output duplicate
18114 TOC entries (this happens on AIX if there is any kind of TOC,
18115 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
18117 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
18119 struct toc_hash_struct *h;
18122 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
18123 time because GGC is not initialized at that point. */
18124 if (toc_hash_table == NULL)
18125 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
18126 toc_hash_eq, NULL);
18128 h = GGC_NEW (struct toc_hash_struct);
18130 h->key_mode = mode;
18131 h->labelno = labelno;
18133 found = htab_find_slot (toc_hash_table, h, INSERT);
18134 if (*found == NULL)
18136 else /* This is indeed a duplicate.
18137 Set this label equal to that label. */
18139 fputs ("\t.set ", file);
18140 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
18141 fprintf (file, "%d,", labelno);
18142 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
18143 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
18149 /* If we're going to put a double constant in the TOC, make sure it's
18150 aligned properly when strict alignment is on. */
18151 if (GET_CODE (x) == CONST_DOUBLE
18152 && STRICT_ALIGNMENT
18153 && GET_MODE_BITSIZE (mode) >= 64
18154 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
18155 ASM_OUTPUT_ALIGN (file, 3);
18158 (*targetm.asm_out.internal_label) (file, "LC", labelno);
18160 /* Handle FP constants specially. Note that if we have a minimal
18161 TOC, things we put here aren't actually in the TOC, so we can allow
18163 if (GET_CODE (x) == CONST_DOUBLE &&
18164 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
18166 REAL_VALUE_TYPE rv;
18169 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
18170 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
18171 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
18173 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
18177 if (TARGET_MINIMAL_TOC)
18178 fputs (DOUBLE_INT_ASM_OP, file);
18180 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
18181 k[0] & 0xffffffff, k[1] & 0xffffffff,
18182 k[2] & 0xffffffff, k[3] & 0xffffffff);
18183 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
18184 k[0] & 0xffffffff, k[1] & 0xffffffff,
18185 k[2] & 0xffffffff, k[3] & 0xffffffff);
18190 if (TARGET_MINIMAL_TOC)
18191 fputs ("\t.long ", file);
18193 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
18194 k[0] & 0xffffffff, k[1] & 0xffffffff,
18195 k[2] & 0xffffffff, k[3] & 0xffffffff);
18196 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
18197 k[0] & 0xffffffff, k[1] & 0xffffffff,
18198 k[2] & 0xffffffff, k[3] & 0xffffffff);
18202 else if (GET_CODE (x) == CONST_DOUBLE &&
18203 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
18205 REAL_VALUE_TYPE rv;
18208 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
18210 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
18211 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
18213 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
18217 if (TARGET_MINIMAL_TOC)
18218 fputs (DOUBLE_INT_ASM_OP, file);
18220 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
18221 k[0] & 0xffffffff, k[1] & 0xffffffff);
18222 fprintf (file, "0x%lx%08lx\n",
18223 k[0] & 0xffffffff, k[1] & 0xffffffff);
18228 if (TARGET_MINIMAL_TOC)
18229 fputs ("\t.long ", file);
18231 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
18232 k[0] & 0xffffffff, k[1] & 0xffffffff);
18233 fprintf (file, "0x%lx,0x%lx\n",
18234 k[0] & 0xffffffff, k[1] & 0xffffffff);
18238 else if (GET_CODE (x) == CONST_DOUBLE &&
18239 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
18241 REAL_VALUE_TYPE rv;
18244 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
18245 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
18246 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
18248 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
18252 if (TARGET_MINIMAL_TOC)
18253 fputs (DOUBLE_INT_ASM_OP, file);
18255 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
18256 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
18261 if (TARGET_MINIMAL_TOC)
18262 fputs ("\t.long ", file);
18264 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
18265 fprintf (file, "0x%lx\n", l & 0xffffffff);
18269 else if (GET_MODE (x) == VOIDmode
18270 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
18272 unsigned HOST_WIDE_INT low;
18273 HOST_WIDE_INT high;
18275 if (GET_CODE (x) == CONST_DOUBLE)
18277 low = CONST_DOUBLE_LOW (x);
18278 high = CONST_DOUBLE_HIGH (x);
18281 #if HOST_BITS_PER_WIDE_INT == 32
18284 high = (low & 0x80000000) ? ~0 : 0;
18288 low = INTVAL (x) & 0xffffffff;
18289 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
18293 /* TOC entries are always Pmode-sized, but since this
18294 is a bigendian machine then if we're putting smaller
18295 integer constants in the TOC we have to pad them.
18296 (This is still a win over putting the constants in
18297 a separate constant pool, because then we'd have
18298 to have both a TOC entry _and_ the actual constant.)
18300 For a 32-bit target, CONST_INT values are loaded and shifted
18301 entirely within `low' and can be stored in one TOC entry. */
18303 /* It would be easy to make this work, but it doesn't now. */
18304 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
18306 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
18308 #if HOST_BITS_PER_WIDE_INT == 32
18309 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
18310 POINTER_SIZE, &low, &high, 0);
18313 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
18314 high = (HOST_WIDE_INT) low >> 32;
18321 if (TARGET_MINIMAL_TOC)
18322 fputs (DOUBLE_INT_ASM_OP, file);
18324 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18325 (long) high & 0xffffffff, (long) low & 0xffffffff);
18326 fprintf (file, "0x%lx%08lx\n",
18327 (long) high & 0xffffffff, (long) low & 0xffffffff);
18332 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
18334 if (TARGET_MINIMAL_TOC)
18335 fputs ("\t.long ", file);
18337 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
18338 (long) high & 0xffffffff, (long) low & 0xffffffff);
18339 fprintf (file, "0x%lx,0x%lx\n",
18340 (long) high & 0xffffffff, (long) low & 0xffffffff);
18344 if (TARGET_MINIMAL_TOC)
18345 fputs ("\t.long ", file);
18347 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
18348 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
18354 if (GET_CODE (x) == CONST)
18356 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
18358 base = XEXP (XEXP (x, 0), 0);
18359 offset = INTVAL (XEXP (XEXP (x, 0), 1));
18362 switch (GET_CODE (base))
18365 name = XSTR (base, 0);
18369 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
18370 CODE_LABEL_NUMBER (XEXP (base, 0)));
18374 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
18378 gcc_unreachable ();
18381 if (TARGET_MINIMAL_TOC)
18382 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
18385 fputs ("\t.tc ", file);
18386 RS6000_OUTPUT_BASENAME (file, name);
18389 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
18391 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
18393 fputs ("[TC],", file);
18396 /* Currently C++ toc references to vtables can be emitted before it
18397 is decided whether the vtable is public or private. If this is
18398 the case, then the linker will eventually complain that there is
18399 a TOC reference to an unknown section. Thus, for vtables only,
18400 we emit the TOC reference to reference the symbol and not the
18402 if (VTABLE_NAME_P (name))
18404 RS6000_OUTPUT_BASENAME (file, name);
18406 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
18407 else if (offset > 0)
18408 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
18411 output_addr_const (file, x);
18415 /* Output an assembler pseudo-op to write an ASCII string of N characters
18416 starting at P to FILE.
18418 On the RS/6000, we have to do this using the .byte operation and
18419 write out special characters outside the quoted string.
18420 Also, the assembler is broken; very long strings are truncated,
18421 so we must artificially break them up early. */
18424 output_ascii (FILE *file, const char *p, int n)
18427 int i, count_string;
18428 const char *for_string = "\t.byte \"";
18429 const char *for_decimal = "\t.byte ";
18430 const char *to_close = NULL;
18433 for (i = 0; i < n; i++)
18436 if (c >= ' ' && c < 0177)
18439 fputs (for_string, file);
18442 /* Write two quotes to get one. */
18450 for_decimal = "\"\n\t.byte ";
18454 if (count_string >= 512)
18456 fputs (to_close, file);
18458 for_string = "\t.byte \"";
18459 for_decimal = "\t.byte ";
18467 fputs (for_decimal, file);
18468 fprintf (file, "%d", c);
18470 for_string = "\n\t.byte \"";
18471 for_decimal = ", ";
18477 /* Now close the string if we have written one. Then end the line. */
18479 fputs (to_close, file);
18482 /* Generate a unique section name for FILENAME for a section type
18483 represented by SECTION_DESC. Output goes into BUF.
18485 SECTION_DESC can be any string, as long as it is different for each
18486 possible section type.
18488 We name the section in the same manner as xlc. The name begins with an
18489 underscore followed by the filename (after stripping any leading directory
18490 names) with the last period replaced by the string SECTION_DESC. If
18491 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18495 rs6000_gen_section_name (char **buf, const char *filename,
18496 const char *section_desc)
18498 const char *q, *after_last_slash, *last_period = 0;
18502 after_last_slash = filename;
18503 for (q = filename; *q; q++)
18506 after_last_slash = q + 1;
18507 else if (*q == '.')
18511 len = strlen (after_last_slash) + strlen (section_desc) + 2;
18512 *buf = (char *) xmalloc (len);
18517 for (q = after_last_slash; *q; q++)
18519 if (q == last_period)
18521 strcpy (p, section_desc);
18522 p += strlen (section_desc);
18526 else if (ISALNUM (*q))
18530 if (last_period == 0)
18531 strcpy (p, section_desc);
18536 /* Emit profile function. */
18539 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
18541 /* Non-standard profiling for kernels, which just saves LR then calls
18542 _mcount without worrying about arg saves. The idea is to change
18543 the function prologue as little as possible as it isn't easy to
18544 account for arg save/restore code added just for _mcount. */
18545 if (TARGET_PROFILE_KERNEL)
18548 if (DEFAULT_ABI == ABI_AIX)
18550 #ifndef NO_PROFILE_COUNTERS
18551 # define NO_PROFILE_COUNTERS 0
18553 if (NO_PROFILE_COUNTERS)
18554 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
18555 LCT_NORMAL, VOIDmode, 0);
18559 const char *label_name;
18562 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18563 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
18564 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
18566 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
18567 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
18570 else if (DEFAULT_ABI == ABI_DARWIN)
18572 const char *mcount_name = RS6000_MCOUNT;
18573 int caller_addr_regno = LR_REGNO;
18575 /* Be conservative and always set this, at least for now. */
18576 crtl->uses_pic_offset_table = 1;
18579 /* For PIC code, set up a stub and collect the caller's address
18580 from r0, which is where the prologue puts it. */
18581 if (MACHOPIC_INDIRECT
18582 && crtl->uses_pic_offset_table)
18583 caller_addr_regno = 0;
18585 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
18586 LCT_NORMAL, VOIDmode, 1,
18587 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
18591 /* Write function profiler code. */
18594 output_function_profiler (FILE *file, int labelno)
18598 switch (DEFAULT_ABI)
18601 gcc_unreachable ();
18606 warning (0, "no profiling of 64-bit code for this ABI");
18609 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
18610 fprintf (file, "\tmflr %s\n", reg_names[0]);
18611 if (NO_PROFILE_COUNTERS)
18613 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18614 reg_names[0], reg_names[1]);
18616 else if (TARGET_SECURE_PLT && flag_pic)
18618 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18619 reg_names[0], reg_names[1]);
18620 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18621 asm_fprintf (file, "\t{cau|addis} %s,%s,",
18622 reg_names[12], reg_names[12]);
18623 assemble_name (file, buf);
18624 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
18625 assemble_name (file, buf);
18626 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
18628 else if (flag_pic == 1)
18630 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
18631 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18632 reg_names[0], reg_names[1]);
18633 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
18634 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
18635 assemble_name (file, buf);
18636 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
18638 else if (flag_pic > 1)
18640 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18641 reg_names[0], reg_names[1]);
18642 /* Now, we need to get the address of the label. */
18643 fputs ("\tbcl 20,31,1f\n\t.long ", file);
18644 assemble_name (file, buf);
18645 fputs ("-.\n1:", file);
18646 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
18647 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
18648 reg_names[0], reg_names[11]);
18649 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
18650 reg_names[0], reg_names[0], reg_names[11]);
18654 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
18655 assemble_name (file, buf);
18656 fputs ("@ha\n", file);
18657 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
18658 reg_names[0], reg_names[1]);
18659 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
18660 assemble_name (file, buf);
18661 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
18664 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18665 fprintf (file, "\tbl %s%s\n",
18666 RS6000_MCOUNT, flag_pic ? "@plt" : "");
18671 if (!TARGET_PROFILE_KERNEL)
18673 /* Don't do anything, done in output_profile_hook (). */
18677 gcc_assert (!TARGET_32BIT);
18679 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
18680 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
18682 if (cfun->static_chain_decl != NULL)
18684 asm_fprintf (file, "\tstd %s,24(%s)\n",
18685 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18686 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18687 asm_fprintf (file, "\tld %s,24(%s)\n",
18688 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
18691 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
18699 /* The following variable value is the last issued insn. */
18701 static rtx last_scheduled_insn;
18703 /* The following variable helps to balance issuing of load and
18704 store instructions */
18706 static int load_store_pendulum;
18708 /* Power4 load update and store update instructions are cracked into a
18709 load or store and an integer insn which are executed in the same cycle.
18710 Branches have their own dispatch slot which does not count against the
18711 GCC issue rate, but it changes the program flow so there are no other
18712 instructions to issue in this cycle. */
18715 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
18716 int verbose ATTRIBUTE_UNUSED,
18717 rtx insn, int more)
18719 last_scheduled_insn = insn;
18720 if (GET_CODE (PATTERN (insn)) == USE
18721 || GET_CODE (PATTERN (insn)) == CLOBBER)
18723 cached_can_issue_more = more;
18724 return cached_can_issue_more;
18727 if (insn_terminates_group_p (insn, current_group))
18729 cached_can_issue_more = 0;
18730 return cached_can_issue_more;
18733 /* If no reservation, but reach here */
18734 if (recog_memoized (insn) < 0)
18737 if (rs6000_sched_groups)
18739 if (is_microcoded_insn (insn))
18740 cached_can_issue_more = 0;
18741 else if (is_cracked_insn (insn))
18742 cached_can_issue_more = more > 2 ? more - 2 : 0;
18744 cached_can_issue_more = more - 1;
18746 return cached_can_issue_more;
18749 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
18752 cached_can_issue_more = more - 1;
18753 return cached_can_issue_more;
18756 /* Adjust the cost of a scheduling dependency. Return the new cost of
18757 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18760 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18762 enum attr_type attr_type;
18764 if (! recog_memoized (insn))
18767 switch (REG_NOTE_KIND (link))
18771 /* Data dependency; DEP_INSN writes a register that INSN reads
18772 some cycles later. */
18774 /* Separate a load from a narrower, dependent store. */
18775 if (rs6000_sched_groups
18776 && GET_CODE (PATTERN (insn)) == SET
18777 && GET_CODE (PATTERN (dep_insn)) == SET
18778 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
18779 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
18780 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
18781 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
18784 attr_type = get_attr_type (insn);
18789 /* Tell the first scheduling pass about the latency between
18790 a mtctr and bctr (and mtlr and br/blr). The first
18791 scheduling pass will not know about this latency since
18792 the mtctr instruction, which has the latency associated
18793 to it, will be generated by reload. */
18794 return TARGET_POWER ? 5 : 4;
18796 /* Leave some extra cycles between a compare and its
18797 dependent branch, to inhibit expensive mispredicts. */
18798 if ((rs6000_cpu_attr == CPU_PPC603
18799 || rs6000_cpu_attr == CPU_PPC604
18800 || rs6000_cpu_attr == CPU_PPC604E
18801 || rs6000_cpu_attr == CPU_PPC620
18802 || rs6000_cpu_attr == CPU_PPC630
18803 || rs6000_cpu_attr == CPU_PPC750
18804 || rs6000_cpu_attr == CPU_PPC7400
18805 || rs6000_cpu_attr == CPU_PPC7450
18806 || rs6000_cpu_attr == CPU_POWER4
18807 || rs6000_cpu_attr == CPU_POWER5
18808 || rs6000_cpu_attr == CPU_CELL)
18809 && recog_memoized (dep_insn)
18810 && (INSN_CODE (dep_insn) >= 0))
18812 switch (get_attr_type (dep_insn))
18816 case TYPE_DELAYED_COMPARE:
18817 case TYPE_IMUL_COMPARE:
18818 case TYPE_LMUL_COMPARE:
18819 case TYPE_FPCOMPARE:
18820 case TYPE_CR_LOGICAL:
18821 case TYPE_DELAYED_CR:
18830 case TYPE_STORE_UX:
18832 case TYPE_FPSTORE_U:
18833 case TYPE_FPSTORE_UX:
18834 if ((rs6000_cpu == PROCESSOR_POWER6)
18835 && recog_memoized (dep_insn)
18836 && (INSN_CODE (dep_insn) >= 0))
18839 if (GET_CODE (PATTERN (insn)) != SET)
18840 /* If this happens, we have to extend this to schedule
18841 optimally. Return default for now. */
18844 /* Adjust the cost for the case where the value written
18845 by a fixed point operation is used as the address
18846 gen value on a store. */
18847 switch (get_attr_type (dep_insn))
18854 if (! store_data_bypass_p (dep_insn, insn))
18858 case TYPE_LOAD_EXT:
18859 case TYPE_LOAD_EXT_U:
18860 case TYPE_LOAD_EXT_UX:
18861 case TYPE_VAR_SHIFT_ROTATE:
18862 case TYPE_VAR_DELAYED_COMPARE:
18864 if (! store_data_bypass_p (dep_insn, insn))
18870 case TYPE_FAST_COMPARE:
18873 case TYPE_INSERT_WORD:
18874 case TYPE_INSERT_DWORD:
18875 case TYPE_FPLOAD_U:
18876 case TYPE_FPLOAD_UX:
18878 case TYPE_STORE_UX:
18879 case TYPE_FPSTORE_U:
18880 case TYPE_FPSTORE_UX:
18882 if (! store_data_bypass_p (dep_insn, insn))
18890 case TYPE_IMUL_COMPARE:
18891 case TYPE_LMUL_COMPARE:
18893 if (! store_data_bypass_p (dep_insn, insn))
18899 if (! store_data_bypass_p (dep_insn, insn))
18905 if (! store_data_bypass_p (dep_insn, insn))
18918 case TYPE_LOAD_EXT:
18919 case TYPE_LOAD_EXT_U:
18920 case TYPE_LOAD_EXT_UX:
18921 if ((rs6000_cpu == PROCESSOR_POWER6)
18922 && recog_memoized (dep_insn)
18923 && (INSN_CODE (dep_insn) >= 0))
18926 /* Adjust the cost for the case where the value written
18927 by a fixed point instruction is used within the address
18928 gen portion of a subsequent load(u)(x) */
18929 switch (get_attr_type (dep_insn))
18936 if (set_to_load_agen (dep_insn, insn))
18940 case TYPE_LOAD_EXT:
18941 case TYPE_LOAD_EXT_U:
18942 case TYPE_LOAD_EXT_UX:
18943 case TYPE_VAR_SHIFT_ROTATE:
18944 case TYPE_VAR_DELAYED_COMPARE:
18946 if (set_to_load_agen (dep_insn, insn))
18952 case TYPE_FAST_COMPARE:
18955 case TYPE_INSERT_WORD:
18956 case TYPE_INSERT_DWORD:
18957 case TYPE_FPLOAD_U:
18958 case TYPE_FPLOAD_UX:
18960 case TYPE_STORE_UX:
18961 case TYPE_FPSTORE_U:
18962 case TYPE_FPSTORE_UX:
18964 if (set_to_load_agen (dep_insn, insn))
18972 case TYPE_IMUL_COMPARE:
18973 case TYPE_LMUL_COMPARE:
18975 if (set_to_load_agen (dep_insn, insn))
18981 if (set_to_load_agen (dep_insn, insn))
18987 if (set_to_load_agen (dep_insn, insn))
18998 if ((rs6000_cpu == PROCESSOR_POWER6)
18999 && recog_memoized (dep_insn)
19000 && (INSN_CODE (dep_insn) >= 0)
19001 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
19008 /* Fall out to return default cost. */
19012 case REG_DEP_OUTPUT:
19013 /* Output dependency; DEP_INSN writes a register that INSN writes some
19015 if ((rs6000_cpu == PROCESSOR_POWER6)
19016 && recog_memoized (dep_insn)
19017 && (INSN_CODE (dep_insn) >= 0))
19019 attr_type = get_attr_type (insn);
19024 if (get_attr_type (dep_insn) == TYPE_FP)
19028 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
19036 /* Anti dependency; DEP_INSN reads a register that INSN writes some
19041 gcc_unreachable ();
19047 /* The function returns a true if INSN is microcoded.
19048 Return false otherwise. */
19051 is_microcoded_insn (rtx insn)
19053 if (!insn || !INSN_P (insn)
19054 || GET_CODE (PATTERN (insn)) == USE
19055 || GET_CODE (PATTERN (insn)) == CLOBBER)
19058 if (rs6000_cpu_attr == CPU_CELL)
19059 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
19061 if (rs6000_sched_groups)
19063 enum attr_type type = get_attr_type (insn);
19064 if (type == TYPE_LOAD_EXT_U
19065 || type == TYPE_LOAD_EXT_UX
19066 || type == TYPE_LOAD_UX
19067 || type == TYPE_STORE_UX
19068 || type == TYPE_MFCR)
19075 /* The function returns true if INSN is cracked into 2 instructions
19076 by the processor (and therefore occupies 2 issue slots). */
19079 is_cracked_insn (rtx insn)
19081 if (!insn || !INSN_P (insn)
19082 || GET_CODE (PATTERN (insn)) == USE
19083 || GET_CODE (PATTERN (insn)) == CLOBBER)
19086 if (rs6000_sched_groups)
19088 enum attr_type type = get_attr_type (insn);
19089 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
19090 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
19091 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
19092 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
19093 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
19094 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
19095 || type == TYPE_IDIV || type == TYPE_LDIV
19096 || type == TYPE_INSERT_WORD)
19103 /* The function returns true if INSN can be issued only from
19104 the branch slot. */
19107 is_branch_slot_insn (rtx insn)
19109 if (!insn || !INSN_P (insn)
19110 || GET_CODE (PATTERN (insn)) == USE
19111 || GET_CODE (PATTERN (insn)) == CLOBBER)
19114 if (rs6000_sched_groups)
19116 enum attr_type type = get_attr_type (insn);
19117 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
19125 /* The function returns true if out_inst sets a value that is
19126 used in the address generation computation of in_insn */
19128 set_to_load_agen (rtx out_insn, rtx in_insn)
19130 rtx out_set, in_set;
19132 /* For performance reasons, only handle the simple case where
19133 both loads are a single_set. */
19134 out_set = single_set (out_insn);
19137 in_set = single_set (in_insn);
19139 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
19145 /* The function returns true if the target storage location of
19146 out_insn is adjacent to the target storage location of in_insn */
19147 /* Return 1 if memory locations are adjacent. */
19150 adjacent_mem_locations (rtx insn1, rtx insn2)
19153 rtx a = get_store_dest (PATTERN (insn1));
19154 rtx b = get_store_dest (PATTERN (insn2));
19156 if ((GET_CODE (XEXP (a, 0)) == REG
19157 || (GET_CODE (XEXP (a, 0)) == PLUS
19158 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
19159 && (GET_CODE (XEXP (b, 0)) == REG
19160 || (GET_CODE (XEXP (b, 0)) == PLUS
19161 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
19163 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
19166 if (GET_CODE (XEXP (a, 0)) == PLUS)
19168 reg0 = XEXP (XEXP (a, 0), 0);
19169 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
19172 reg0 = XEXP (a, 0);
19174 if (GET_CODE (XEXP (b, 0)) == PLUS)
19176 reg1 = XEXP (XEXP (b, 0), 0);
19177 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
19180 reg1 = XEXP (b, 0);
19182 val_diff = val1 - val0;
19184 return ((REGNO (reg0) == REGNO (reg1))
19185 && ((MEM_SIZE (a) && val_diff == INTVAL (MEM_SIZE (a)))
19186 || (MEM_SIZE (b) && val_diff == -INTVAL (MEM_SIZE (b)))));
19192 /* A C statement (sans semicolon) to update the integer scheduling
19193 priority INSN_PRIORITY (INSN). Increase the priority to execute the
19194 INSN earlier, reduce the priority to execute INSN later. Do not
19195 define this macro if you do not need to adjust the scheduling
19196 priorities of insns. */
19199 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
19201 /* On machines (like the 750) which have asymmetric integer units,
19202 where one integer unit can do multiply and divides and the other
19203 can't, reduce the priority of multiply/divide so it is scheduled
19204 before other integer operations. */
19207 if (! INSN_P (insn))
19210 if (GET_CODE (PATTERN (insn)) == USE)
19213 switch (rs6000_cpu_attr) {
19215 switch (get_attr_type (insn))
19222 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
19223 priority, priority);
19224 if (priority >= 0 && priority < 0x01000000)
19231 if (insn_must_be_first_in_group (insn)
19232 && reload_completed
19233 && current_sched_info->sched_max_insns_priority
19234 && rs6000_sched_restricted_insns_priority)
19237 /* Prioritize insns that can be dispatched only in the first
19239 if (rs6000_sched_restricted_insns_priority == 1)
19240 /* Attach highest priority to insn. This means that in
19241 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
19242 precede 'priority' (critical path) considerations. */
19243 return current_sched_info->sched_max_insns_priority;
19244 else if (rs6000_sched_restricted_insns_priority == 2)
19245 /* Increase priority of insn by a minimal amount. This means that in
19246 haifa-sched.c:ready_sort(), only 'priority' (critical path)
19247 considerations precede dispatch-slot restriction considerations. */
19248 return (priority + 1);
19251 if (rs6000_cpu == PROCESSOR_POWER6
19252 && ((load_store_pendulum == -2 && is_load_insn (insn))
19253 || (load_store_pendulum == 2 && is_store_insn (insn))))
19254 /* Attach highest priority to insn if the scheduler has just issued two
19255 stores and this instruction is a load, or two loads and this instruction
19256 is a store. Power6 wants loads and stores scheduled alternately
19258 return current_sched_info->sched_max_insns_priority;
19263 /* Return true if the instruction is nonpipelined on the Cell. */
19265 is_nonpipeline_insn (rtx insn)
19267 enum attr_type type;
19268 if (!insn || !INSN_P (insn)
19269 || GET_CODE (PATTERN (insn)) == USE
19270 || GET_CODE (PATTERN (insn)) == CLOBBER)
19273 type = get_attr_type (insn);
19274 if (type == TYPE_IMUL
19275 || type == TYPE_IMUL2
19276 || type == TYPE_IMUL3
19277 || type == TYPE_LMUL
19278 || type == TYPE_IDIV
19279 || type == TYPE_LDIV
19280 || type == TYPE_SDIV
19281 || type == TYPE_DDIV
19282 || type == TYPE_SSQRT
19283 || type == TYPE_DSQRT
19284 || type == TYPE_MFCR
19285 || type == TYPE_MFCRF
19286 || type == TYPE_MFJMPR)
19294 /* Return how many instructions the machine can issue per cycle. */
19297 rs6000_issue_rate (void)
19299 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19300 if (!reload_completed)
19303 switch (rs6000_cpu_attr) {
19304 case CPU_RIOS1: /* ? */
19306 case CPU_PPC601: /* ? */
19315 case CPU_PPCE300C2:
19316 case CPU_PPCE300C3:
19317 case CPU_PPCE500MC:
19334 /* Return how many instructions to look ahead for better insn
19338 rs6000_use_sched_lookahead (void)
19340 if (rs6000_cpu_attr == CPU_PPC8540)
19342 if (rs6000_cpu_attr == CPU_CELL)
19343 return (reload_completed ? 8 : 0);
19347 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19349 rs6000_use_sched_lookahead_guard (rtx insn)
19351 if (rs6000_cpu_attr != CPU_CELL)
19354 if (insn == NULL_RTX || !INSN_P (insn))
19357 if (!reload_completed
19358 || is_nonpipeline_insn (insn)
19359 || is_microcoded_insn (insn))
19365 /* Determine is PAT refers to memory. */
19368 is_mem_ref (rtx pat)
19374 /* stack_tie does not produce any real memory traffic. */
19375 if (GET_CODE (pat) == UNSPEC
19376 && XINT (pat, 1) == UNSPEC_TIE)
19379 if (GET_CODE (pat) == MEM)
19382 /* Recursively process the pattern. */
19383 fmt = GET_RTX_FORMAT (GET_CODE (pat));
19385 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
19388 ret |= is_mem_ref (XEXP (pat, i));
19389 else if (fmt[i] == 'E')
19390 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
19391 ret |= is_mem_ref (XVECEXP (pat, i, j));
19397 /* Determine if PAT is a PATTERN of a load insn. */
19400 is_load_insn1 (rtx pat)
19402 if (!pat || pat == NULL_RTX)
19405 if (GET_CODE (pat) == SET)
19406 return is_mem_ref (SET_SRC (pat));
19408 if (GET_CODE (pat) == PARALLEL)
19412 for (i = 0; i < XVECLEN (pat, 0); i++)
19413 if (is_load_insn1 (XVECEXP (pat, 0, i)))
19420 /* Determine if INSN loads from memory. */
19423 is_load_insn (rtx insn)
19425 if (!insn || !INSN_P (insn))
19428 if (GET_CODE (insn) == CALL_INSN)
19431 return is_load_insn1 (PATTERN (insn));
19434 /* Determine if PAT is a PATTERN of a store insn. */
19437 is_store_insn1 (rtx pat)
19439 if (!pat || pat == NULL_RTX)
19442 if (GET_CODE (pat) == SET)
19443 return is_mem_ref (SET_DEST (pat));
19445 if (GET_CODE (pat) == PARALLEL)
19449 for (i = 0; i < XVECLEN (pat, 0); i++)
19450 if (is_store_insn1 (XVECEXP (pat, 0, i)))
19457 /* Determine if INSN stores to memory. */
19460 is_store_insn (rtx insn)
19462 if (!insn || !INSN_P (insn))
19465 return is_store_insn1 (PATTERN (insn));
19468 /* Return the dest of a store insn. */
19471 get_store_dest (rtx pat)
19473 gcc_assert (is_store_insn1 (pat));
19475 if (GET_CODE (pat) == SET)
19476 return SET_DEST (pat);
19477 else if (GET_CODE (pat) == PARALLEL)
19481 for (i = 0; i < XVECLEN (pat, 0); i++)
19483 rtx inner_pat = XVECEXP (pat, 0, i);
19484 if (GET_CODE (inner_pat) == SET
19485 && is_mem_ref (SET_DEST (inner_pat)))
19489 /* We shouldn't get here, because we should have either a simple
19490 store insn or a store with update which are covered above. */
19494 /* Returns whether the dependence between INSN and NEXT is considered
19495 costly by the given target. */
19498 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
19503 /* If the flag is not enabled - no dependence is considered costly;
19504 allow all dependent insns in the same group.
19505 This is the most aggressive option. */
19506 if (rs6000_sched_costly_dep == no_dep_costly)
19509 /* If the flag is set to 1 - a dependence is always considered costly;
19510 do not allow dependent instructions in the same group.
19511 This is the most conservative option. */
19512 if (rs6000_sched_costly_dep == all_deps_costly)
19515 insn = DEP_PRO (dep);
19516 next = DEP_CON (dep);
19518 if (rs6000_sched_costly_dep == store_to_load_dep_costly
19519 && is_load_insn (next)
19520 && is_store_insn (insn))
19521 /* Prevent load after store in the same group. */
19524 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
19525 && is_load_insn (next)
19526 && is_store_insn (insn)
19527 && DEP_TYPE (dep) == REG_DEP_TRUE)
19528 /* Prevent load after store in the same group if it is a true
19532 /* The flag is set to X; dependences with latency >= X are considered costly,
19533 and will not be scheduled in the same group. */
19534 if (rs6000_sched_costly_dep <= max_dep_latency
19535 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
19541 /* Return the next insn after INSN that is found before TAIL is reached,
19542 skipping any "non-active" insns - insns that will not actually occupy
19543 an issue slot. Return NULL_RTX if such an insn is not found. */
19546 get_next_active_insn (rtx insn, rtx tail)
19548 if (insn == NULL_RTX || insn == tail)
19553 insn = NEXT_INSN (insn);
19554 if (insn == NULL_RTX || insn == tail)
19559 || (NONJUMP_INSN_P (insn)
19560 && GET_CODE (PATTERN (insn)) != USE
19561 && GET_CODE (PATTERN (insn)) != CLOBBER
19562 && INSN_CODE (insn) != CODE_FOR_stack_tie))
19568 /* We are about to begin issuing insns for this clock cycle. */
19571 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
19572 rtx *ready ATTRIBUTE_UNUSED,
19573 int *pn_ready ATTRIBUTE_UNUSED,
19574 int clock_var ATTRIBUTE_UNUSED)
19576 int n_ready = *pn_ready;
19579 fprintf (dump, "// rs6000_sched_reorder :\n");
19581 /* Reorder the ready list, if the second to last ready insn
19582 is a nonepipeline insn. */
19583 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
19585 if (is_nonpipeline_insn (ready[n_ready - 1])
19586 && (recog_memoized (ready[n_ready - 2]) > 0))
19587 /* Simply swap first two insns. */
19589 rtx tmp = ready[n_ready - 1];
19590 ready[n_ready - 1] = ready[n_ready - 2];
19591 ready[n_ready - 2] = tmp;
19595 if (rs6000_cpu == PROCESSOR_POWER6)
19596 load_store_pendulum = 0;
19598 return rs6000_issue_rate ();
19601 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19604 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
19605 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
19608 fprintf (dump, "// rs6000_sched_reorder2 :\n");
19610 /* For Power6, we need to handle some special cases to try and keep the
19611 store queue from overflowing and triggering expensive flushes.
19613 This code monitors how load and store instructions are being issued
19614 and skews the ready list one way or the other to increase the likelihood
19615 that a desired instruction is issued at the proper time.
19617 A couple of things are done. First, we maintain a "load_store_pendulum"
19618 to track the current state of load/store issue.
19620 - If the pendulum is at zero, then no loads or stores have been
19621 issued in the current cycle so we do nothing.
19623 - If the pendulum is 1, then a single load has been issued in this
19624 cycle and we attempt to locate another load in the ready list to
19627 - If the pendulum is -2, then two stores have already been
19628 issued in this cycle, so we increase the priority of the first load
19629 in the ready list to increase it's likelihood of being chosen first
19632 - If the pendulum is -1, then a single store has been issued in this
19633 cycle and we attempt to locate another store in the ready list to
19634 issue with it, preferring a store to an adjacent memory location to
19635 facilitate store pairing in the store queue.
19637 - If the pendulum is 2, then two loads have already been
19638 issued in this cycle, so we increase the priority of the first store
19639 in the ready list to increase it's likelihood of being chosen first
19642 - If the pendulum < -2 or > 2, then do nothing.
19644 Note: This code covers the most common scenarios. There exist non
19645 load/store instructions which make use of the LSU and which
19646 would need to be accounted for to strictly model the behavior
19647 of the machine. Those instructions are currently unaccounted
19648 for to help minimize compile time overhead of this code.
19650 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
19656 if (is_store_insn (last_scheduled_insn))
19657 /* Issuing a store, swing the load_store_pendulum to the left */
19658 load_store_pendulum--;
19659 else if (is_load_insn (last_scheduled_insn))
19660 /* Issuing a load, swing the load_store_pendulum to the right */
19661 load_store_pendulum++;
19663 return cached_can_issue_more;
19665 /* If the pendulum is balanced, or there is only one instruction on
19666 the ready list, then all is well, so return. */
19667 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
19668 return cached_can_issue_more;
19670 if (load_store_pendulum == 1)
19672 /* A load has been issued in this cycle. Scan the ready list
19673 for another load to issue with it */
19678 if (is_load_insn (ready[pos]))
19680 /* Found a load. Move it to the head of the ready list,
19681 and adjust it's priority so that it is more likely to
19684 for (i=pos; i<*pn_ready-1; i++)
19685 ready[i] = ready[i + 1];
19686 ready[*pn_ready-1] = tmp;
19688 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
19689 INSN_PRIORITY (tmp)++;
19695 else if (load_store_pendulum == -2)
19697 /* Two stores have been issued in this cycle. Increase the
19698 priority of the first load in the ready list to favor it for
19699 issuing in the next cycle. */
19704 if (is_load_insn (ready[pos])
19706 && INSN_PRIORITY_KNOWN (ready[pos]))
19708 INSN_PRIORITY (ready[pos])++;
19710 /* Adjust the pendulum to account for the fact that a load
19711 was found and increased in priority. This is to prevent
19712 increasing the priority of multiple loads */
19713 load_store_pendulum--;
19720 else if (load_store_pendulum == -1)
19722 /* A store has been issued in this cycle. Scan the ready list for
19723 another store to issue with it, preferring a store to an adjacent
19725 int first_store_pos = -1;
19731 if (is_store_insn (ready[pos]))
19733 /* Maintain the index of the first store found on the
19735 if (first_store_pos == -1)
19736 first_store_pos = pos;
19738 if (is_store_insn (last_scheduled_insn)
19739 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
19741 /* Found an adjacent store. Move it to the head of the
19742 ready list, and adjust it's priority so that it is
19743 more likely to stay there */
19745 for (i=pos; i<*pn_ready-1; i++)
19746 ready[i] = ready[i + 1];
19747 ready[*pn_ready-1] = tmp;
19749 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
19750 INSN_PRIORITY (tmp)++;
19752 first_store_pos = -1;
19760 if (first_store_pos >= 0)
19762 /* An adjacent store wasn't found, but a non-adjacent store was,
19763 so move the non-adjacent store to the front of the ready
19764 list, and adjust its priority so that it is more likely to
19766 tmp = ready[first_store_pos];
19767 for (i=first_store_pos; i<*pn_ready-1; i++)
19768 ready[i] = ready[i + 1];
19769 ready[*pn_ready-1] = tmp;
19770 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
19771 INSN_PRIORITY (tmp)++;
19774 else if (load_store_pendulum == 2)
19776 /* Two loads have been issued in this cycle. Increase the priority
19777 of the first store in the ready list to favor it for issuing in
19783 if (is_store_insn (ready[pos])
19785 && INSN_PRIORITY_KNOWN (ready[pos]))
19787 INSN_PRIORITY (ready[pos])++;
19789 /* Adjust the pendulum to account for the fact that a store
19790 was found and increased in priority. This is to prevent
19791 increasing the priority of multiple stores */
19792 load_store_pendulum++;
19801 return cached_can_issue_more;
19804 /* Return whether the presence of INSN causes a dispatch group termination
19805 of group WHICH_GROUP.
19807 If WHICH_GROUP == current_group, this function will return true if INSN
19808 causes the termination of the current group (i.e, the dispatch group to
19809 which INSN belongs). This means that INSN will be the last insn in the
19810 group it belongs to.
19812 If WHICH_GROUP == previous_group, this function will return true if INSN
19813 causes the termination of the previous group (i.e, the dispatch group that
19814 precedes the group to which INSN belongs). This means that INSN will be
19815 the first insn in the group it belongs to). */
19818 insn_terminates_group_p (rtx insn, enum group_termination which_group)
19825 first = insn_must_be_first_in_group (insn);
19826 last = insn_must_be_last_in_group (insn);
19831 if (which_group == current_group)
19833 else if (which_group == previous_group)
19841 insn_must_be_first_in_group (rtx insn)
19843 enum attr_type type;
19846 || insn == NULL_RTX
19847 || GET_CODE (insn) == NOTE
19848 || GET_CODE (PATTERN (insn)) == USE
19849 || GET_CODE (PATTERN (insn)) == CLOBBER)
19852 switch (rs6000_cpu)
19854 case PROCESSOR_POWER5:
19855 if (is_cracked_insn (insn))
19857 case PROCESSOR_POWER4:
19858 if (is_microcoded_insn (insn))
19861 if (!rs6000_sched_groups)
19864 type = get_attr_type (insn);
19871 case TYPE_DELAYED_CR:
19872 case TYPE_CR_LOGICAL:
19886 case PROCESSOR_POWER6:
19887 type = get_attr_type (insn);
19891 case TYPE_INSERT_DWORD:
19895 case TYPE_VAR_SHIFT_ROTATE:
19902 case TYPE_INSERT_WORD:
19903 case TYPE_DELAYED_COMPARE:
19904 case TYPE_IMUL_COMPARE:
19905 case TYPE_LMUL_COMPARE:
19906 case TYPE_FPCOMPARE:
19917 case TYPE_LOAD_EXT_UX:
19919 case TYPE_STORE_UX:
19920 case TYPE_FPLOAD_U:
19921 case TYPE_FPLOAD_UX:
19922 case TYPE_FPSTORE_U:
19923 case TYPE_FPSTORE_UX:
19937 insn_must_be_last_in_group (rtx insn)
19939 enum attr_type type;
19942 || insn == NULL_RTX
19943 || GET_CODE (insn) == NOTE
19944 || GET_CODE (PATTERN (insn)) == USE
19945 || GET_CODE (PATTERN (insn)) == CLOBBER)
19948 switch (rs6000_cpu) {
19949 case PROCESSOR_POWER4:
19950 case PROCESSOR_POWER5:
19951 if (is_microcoded_insn (insn))
19954 if (is_branch_slot_insn (insn))
19958 case PROCESSOR_POWER6:
19959 type = get_attr_type (insn);
19966 case TYPE_VAR_SHIFT_ROTATE:
19973 case TYPE_DELAYED_COMPARE:
19974 case TYPE_IMUL_COMPARE:
19975 case TYPE_LMUL_COMPARE:
19976 case TYPE_FPCOMPARE:
19997 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19998 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
20001 is_costly_group (rtx *group_insns, rtx next_insn)
20004 int issue_rate = rs6000_issue_rate ();
20006 for (i = 0; i < issue_rate; i++)
20008 sd_iterator_def sd_it;
20010 rtx insn = group_insns[i];
20015 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
20017 rtx next = DEP_CON (dep);
20019 if (next == next_insn
20020 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
20028 /* Utility of the function redefine_groups.
20029 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
20030 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
20031 to keep it "far" (in a separate group) from GROUP_INSNS, following
20032 one of the following schemes, depending on the value of the flag
20033 -minsert_sched_nops = X:
20034 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
20035 in order to force NEXT_INSN into a separate group.
20036 (2) X < sched_finish_regroup_exact: insert exactly X nops.
20037 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
20038 insertion (has a group just ended, how many vacant issue slots remain in the
20039 last group, and how many dispatch groups were encountered so far). */
20042 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
20043 rtx next_insn, bool *group_end, int can_issue_more,
20048 int issue_rate = rs6000_issue_rate ();
20049 bool end = *group_end;
20052 if (next_insn == NULL_RTX)
20053 return can_issue_more;
20055 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
20056 return can_issue_more;
20058 force = is_costly_group (group_insns, next_insn);
20060 return can_issue_more;
20062 if (sched_verbose > 6)
20063 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
20064 *group_count ,can_issue_more);
20066 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
20069 can_issue_more = 0;
20071 /* Since only a branch can be issued in the last issue_slot, it is
20072 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
20073 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
20074 in this case the last nop will start a new group and the branch
20075 will be forced to the new group. */
20076 if (can_issue_more && !is_branch_slot_insn (next_insn))
20079 while (can_issue_more > 0)
20082 emit_insn_before (nop, next_insn);
20090 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
20092 int n_nops = rs6000_sched_insert_nops;
20094 /* Nops can't be issued from the branch slot, so the effective
20095 issue_rate for nops is 'issue_rate - 1'. */
20096 if (can_issue_more == 0)
20097 can_issue_more = issue_rate;
20099 if (can_issue_more == 0)
20101 can_issue_more = issue_rate - 1;
20104 for (i = 0; i < issue_rate; i++)
20106 group_insns[i] = 0;
20113 emit_insn_before (nop, next_insn);
20114 if (can_issue_more == issue_rate - 1) /* new group begins */
20117 if (can_issue_more == 0)
20119 can_issue_more = issue_rate - 1;
20122 for (i = 0; i < issue_rate; i++)
20124 group_insns[i] = 0;
20130 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
20133 /* Is next_insn going to start a new group? */
20136 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
20137 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
20138 || (can_issue_more < issue_rate &&
20139 insn_terminates_group_p (next_insn, previous_group)));
20140 if (*group_end && end)
20143 if (sched_verbose > 6)
20144 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
20145 *group_count, can_issue_more);
20146 return can_issue_more;
20149 return can_issue_more;
20152 /* This function tries to synch the dispatch groups that the compiler "sees"
20153 with the dispatch groups that the processor dispatcher is expected to
20154 form in practice. It tries to achieve this synchronization by forcing the
20155 estimated processor grouping on the compiler (as opposed to the function
20156 'pad_goups' which tries to force the scheduler's grouping on the processor).
20158 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
20159 examines the (estimated) dispatch groups that will be formed by the processor
20160 dispatcher. It marks these group boundaries to reflect the estimated
20161 processor grouping, overriding the grouping that the scheduler had marked.
20162 Depending on the value of the flag '-minsert-sched-nops' this function can
20163 force certain insns into separate groups or force a certain distance between
20164 them by inserting nops, for example, if there exists a "costly dependence"
20167 The function estimates the group boundaries that the processor will form as
20168 follows: It keeps track of how many vacant issue slots are available after
20169 each insn. A subsequent insn will start a new group if one of the following
20171 - no more vacant issue slots remain in the current dispatch group.
20172 - only the last issue slot, which is the branch slot, is vacant, but the next
20173 insn is not a branch.
20174 - only the last 2 or less issue slots, including the branch slot, are vacant,
20175 which means that a cracked insn (which occupies two issue slots) can't be
20176 issued in this group.
20177 - less than 'issue_rate' slots are vacant, and the next insn always needs to
20178 start a new group. */
20181 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
20183 rtx insn, next_insn;
20185 int can_issue_more;
20188 int group_count = 0;
20192 issue_rate = rs6000_issue_rate ();
20193 group_insns = XALLOCAVEC (rtx, issue_rate);
20194 for (i = 0; i < issue_rate; i++)
20196 group_insns[i] = 0;
20198 can_issue_more = issue_rate;
20200 insn = get_next_active_insn (prev_head_insn, tail);
20203 while (insn != NULL_RTX)
20205 slot = (issue_rate - can_issue_more);
20206 group_insns[slot] = insn;
20208 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
20209 if (insn_terminates_group_p (insn, current_group))
20210 can_issue_more = 0;
20212 next_insn = get_next_active_insn (insn, tail);
20213 if (next_insn == NULL_RTX)
20214 return group_count + 1;
20216 /* Is next_insn going to start a new group? */
20218 = (can_issue_more == 0
20219 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
20220 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
20221 || (can_issue_more < issue_rate &&
20222 insn_terminates_group_p (next_insn, previous_group)));
20224 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
20225 next_insn, &group_end, can_issue_more,
20231 can_issue_more = 0;
20232 for (i = 0; i < issue_rate; i++)
20234 group_insns[i] = 0;
20238 if (GET_MODE (next_insn) == TImode && can_issue_more)
20239 PUT_MODE (next_insn, VOIDmode);
20240 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
20241 PUT_MODE (next_insn, TImode);
20244 if (can_issue_more == 0)
20245 can_issue_more = issue_rate;
20248 return group_count;
20251 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
20252 dispatch group boundaries that the scheduler had marked. Pad with nops
20253 any dispatch groups which have vacant issue slots, in order to force the
20254 scheduler's grouping on the processor dispatcher. The function
20255 returns the number of dispatch groups found. */
20258 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
20260 rtx insn, next_insn;
20263 int can_issue_more;
20265 int group_count = 0;
20267 /* Initialize issue_rate. */
20268 issue_rate = rs6000_issue_rate ();
20269 can_issue_more = issue_rate;
20271 insn = get_next_active_insn (prev_head_insn, tail);
20272 next_insn = get_next_active_insn (insn, tail);
20274 while (insn != NULL_RTX)
20277 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
20279 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
20281 if (next_insn == NULL_RTX)
20286 /* If the scheduler had marked group termination at this location
20287 (between insn and next_insn), and neither insn nor next_insn will
20288 force group termination, pad the group with nops to force group
20291 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
20292 && !insn_terminates_group_p (insn, current_group)
20293 && !insn_terminates_group_p (next_insn, previous_group))
20295 if (!is_branch_slot_insn (next_insn))
20298 while (can_issue_more)
20301 emit_insn_before (nop, next_insn);
20306 can_issue_more = issue_rate;
20311 next_insn = get_next_active_insn (insn, tail);
20314 return group_count;
20317 /* We're beginning a new block. Initialize data structures as necessary. */
20320 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
20321 int sched_verbose ATTRIBUTE_UNUSED,
20322 int max_ready ATTRIBUTE_UNUSED)
20324 last_scheduled_insn = NULL_RTX;
20325 load_store_pendulum = 0;
20328 /* The following function is called at the end of scheduling BB.
20329 After reload, it inserts nops at insn group bundling. */
20332 rs6000_sched_finish (FILE *dump, int sched_verbose)
20337 fprintf (dump, "=== Finishing schedule.\n");
20339 if (reload_completed && rs6000_sched_groups)
20341 /* Do not run sched_finish hook when selective scheduling enabled. */
20342 if (sel_sched_p ())
20345 if (rs6000_sched_insert_nops == sched_finish_none)
20348 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
20349 n_groups = pad_groups (dump, sched_verbose,
20350 current_sched_info->prev_head,
20351 current_sched_info->next_tail);
20353 n_groups = redefine_groups (dump, sched_verbose,
20354 current_sched_info->prev_head,
20355 current_sched_info->next_tail);
20357 if (sched_verbose >= 6)
20359 fprintf (dump, "ngroups = %d\n", n_groups);
20360 print_rtl (dump, current_sched_info->prev_head);
20361 fprintf (dump, "Done finish_sched\n");
20366 struct _rs6000_sched_context
20368 short cached_can_issue_more;
20369 rtx last_scheduled_insn;
20370 int load_store_pendulum;
20373 typedef struct _rs6000_sched_context rs6000_sched_context_def;
20374 typedef rs6000_sched_context_def *rs6000_sched_context_t;
20376 /* Allocate store for new scheduling context. */
20378 rs6000_alloc_sched_context (void)
20380 return xmalloc (sizeof (rs6000_sched_context_def));
20383 /* If CLEAN_P is true then initializes _SC with clean data,
20384 and from the global context otherwise. */
20386 rs6000_init_sched_context (void *_sc, bool clean_p)
20388 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
20392 sc->cached_can_issue_more = 0;
20393 sc->last_scheduled_insn = NULL_RTX;
20394 sc->load_store_pendulum = 0;
20398 sc->cached_can_issue_more = cached_can_issue_more;
20399 sc->last_scheduled_insn = last_scheduled_insn;
20400 sc->load_store_pendulum = load_store_pendulum;
20404 /* Sets the global scheduling context to the one pointed to by _SC. */
20406 rs6000_set_sched_context (void *_sc)
20408 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
20410 gcc_assert (sc != NULL);
20412 cached_can_issue_more = sc->cached_can_issue_more;
20413 last_scheduled_insn = sc->last_scheduled_insn;
20414 load_store_pendulum = sc->load_store_pendulum;
20419 rs6000_free_sched_context (void *_sc)
20421 gcc_assert (_sc != NULL);
20427 /* Length in units of the trampoline for entering a nested function. */
20430 rs6000_trampoline_size (void)
20434 switch (DEFAULT_ABI)
20437 gcc_unreachable ();
20440 ret = (TARGET_32BIT) ? 12 : 24;
20445 ret = (TARGET_32BIT) ? 40 : 48;
20452 /* Emit RTL insns to initialize the variable parts of a trampoline.
20453 FNADDR is an RTX for the address of the function's pure code.
20454 CXT is an RTX for the static chain value for the function. */
20457 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
20459 int regsize = (TARGET_32BIT) ? 4 : 8;
20460 rtx ctx_reg = force_reg (Pmode, cxt);
20462 switch (DEFAULT_ABI)
20465 gcc_unreachable ();
20467 /* Macros to shorten the code expansions below. */
20468 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20469 #define MEM_PLUS(addr,offset) \
20470 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20472 /* Under AIX, just build the 3 word function descriptor */
20475 rtx fn_reg = gen_reg_rtx (Pmode);
20476 rtx toc_reg = gen_reg_rtx (Pmode);
20477 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
20478 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
20479 emit_move_insn (MEM_DEREF (addr), fn_reg);
20480 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
20481 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
20485 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20488 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
20489 LCT_NORMAL, VOIDmode, 4,
20491 GEN_INT (rs6000_trampoline_size ()), SImode,
20501 /* Table of valid machine attributes. */
20503 const struct attribute_spec rs6000_attribute_table[] =
20505 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20506 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
20507 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20508 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
20509 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20510 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
20511 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20512 SUBTARGET_ATTRIBUTE_TABLE,
20514 { NULL, 0, 0, false, false, false, NULL }
20517 /* Handle the "altivec" attribute. The attribute may have
20518 arguments as follows:
20520 __attribute__((altivec(vector__)))
20521 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20522 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20524 and may appear more than once (e.g., 'vector bool char') in a
20525 given declaration. */
20528 rs6000_handle_altivec_attribute (tree *node,
20529 tree name ATTRIBUTE_UNUSED,
20531 int flags ATTRIBUTE_UNUSED,
20532 bool *no_add_attrs)
20534 tree type = *node, result = NULL_TREE;
20535 enum machine_mode mode;
20538 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
20539 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
20540 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
20543 while (POINTER_TYPE_P (type)
20544 || TREE_CODE (type) == FUNCTION_TYPE
20545 || TREE_CODE (type) == METHOD_TYPE
20546 || TREE_CODE (type) == ARRAY_TYPE)
20547 type = TREE_TYPE (type);
20549 mode = TYPE_MODE (type);
20551 /* Check for invalid AltiVec type qualifiers. */
20552 if (type == long_unsigned_type_node || type == long_integer_type_node)
20555 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20556 else if (rs6000_warn_altivec_long)
20557 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20559 else if (type == long_long_unsigned_type_node
20560 || type == long_long_integer_type_node)
20561 error ("use of %<long long%> in AltiVec types is invalid");
20562 else if (type == double_type_node)
20563 error ("use of %<double%> in AltiVec types is invalid");
20564 else if (type == long_double_type_node)
20565 error ("use of %<long double%> in AltiVec types is invalid");
20566 else if (type == boolean_type_node)
20567 error ("use of boolean types in AltiVec types is invalid");
20568 else if (TREE_CODE (type) == COMPLEX_TYPE)
20569 error ("use of %<complex%> in AltiVec types is invalid");
20570 else if (DECIMAL_FLOAT_MODE_P (mode))
20571 error ("use of decimal floating point types in AltiVec types is invalid");
20573 switch (altivec_type)
20576 unsigned_p = TYPE_UNSIGNED (type);
20580 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
20583 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
20586 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
20588 case SFmode: result = V4SF_type_node; break;
20589 /* If the user says 'vector int bool', we may be handed the 'bool'
20590 attribute _before_ the 'vector' attribute, and so select the
20591 proper type in the 'b' case below. */
20592 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
20600 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
20601 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
20602 case QImode: case V16QImode: result = bool_V16QI_type_node;
20609 case V8HImode: result = pixel_V8HI_type_node;
20615 /* Propagate qualifiers attached to the element type
20616 onto the vector type. */
20617 if (result && result != type && TYPE_QUALS (type))
20618 result = build_qualified_type (result, TYPE_QUALS (type));
20620 *no_add_attrs = true; /* No need to hang on to the attribute. */
20623 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
20628 /* AltiVec defines four built-in scalar types that serve as vector
20629 elements; we must teach the compiler how to mangle them. */
20631 static const char *
20632 rs6000_mangle_type (const_tree type)
20634 type = TYPE_MAIN_VARIANT (type);
20636 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
20637 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
20640 if (type == bool_char_type_node) return "U6__boolc";
20641 if (type == bool_short_type_node) return "U6__bools";
20642 if (type == pixel_type_node) return "u7__pixel";
20643 if (type == bool_int_type_node) return "U6__booli";
20645 /* Mangle IBM extended float long double as `g' (__float128) on
20646 powerpc*-linux where long-double-64 previously was the default. */
20647 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
20649 && TARGET_LONG_DOUBLE_128
20650 && !TARGET_IEEEQUAD)
20653 /* For all other types, use normal C++ mangling. */
20657 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20658 struct attribute_spec.handler. */
20661 rs6000_handle_longcall_attribute (tree *node, tree name,
20662 tree args ATTRIBUTE_UNUSED,
20663 int flags ATTRIBUTE_UNUSED,
20664 bool *no_add_attrs)
20666 if (TREE_CODE (*node) != FUNCTION_TYPE
20667 && TREE_CODE (*node) != FIELD_DECL
20668 && TREE_CODE (*node) != TYPE_DECL)
20670 warning (OPT_Wattributes, "%qs attribute only applies to functions",
20671 IDENTIFIER_POINTER (name));
20672 *no_add_attrs = true;
20678 /* Set longcall attributes on all functions declared when
20679 rs6000_default_long_calls is true. */
20681 rs6000_set_default_type_attributes (tree type)
20683 if (rs6000_default_long_calls
20684 && (TREE_CODE (type) == FUNCTION_TYPE
20685 || TREE_CODE (type) == METHOD_TYPE))
20686 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
20688 TYPE_ATTRIBUTES (type));
20691 darwin_set_default_type_attributes (type);
20695 /* Return a reference suitable for calling a function with the
20696 longcall attribute. */
20699 rs6000_longcall_ref (rtx call_ref)
20701 const char *call_name;
20704 if (GET_CODE (call_ref) != SYMBOL_REF)
20707 /* System V adds '.' to the internal name, so skip them. */
20708 call_name = XSTR (call_ref, 0);
20709 if (*call_name == '.')
20711 while (*call_name == '.')
20714 node = get_identifier (call_name);
20715 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
20718 return force_reg (Pmode, call_ref);
20721 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20722 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20725 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20726 struct attribute_spec.handler. */
20728 rs6000_handle_struct_attribute (tree *node, tree name,
20729 tree args ATTRIBUTE_UNUSED,
20730 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
20733 if (DECL_P (*node))
20735 if (TREE_CODE (*node) == TYPE_DECL)
20736 type = &TREE_TYPE (*node);
20741 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
20742 || TREE_CODE (*type) == UNION_TYPE)))
20744 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
20745 *no_add_attrs = true;
20748 else if ((is_attribute_p ("ms_struct", name)
20749 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
20750 || ((is_attribute_p ("gcc_struct", name)
20751 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
20753 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
20754 IDENTIFIER_POINTER (name));
20755 *no_add_attrs = true;
20762 rs6000_ms_bitfield_layout_p (const_tree record_type)
20764 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
20765 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
20766 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
20769 #ifdef USING_ELFOS_H
20771 /* A get_unnamed_section callback, used for switching to toc_section. */
20774 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20776 if (DEFAULT_ABI == ABI_AIX
20777 && TARGET_MINIMAL_TOC
20778 && !TARGET_RELOCATABLE)
20780 if (!toc_initialized)
20782 toc_initialized = 1;
20783 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20784 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
20785 fprintf (asm_out_file, "\t.tc ");
20786 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
20787 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20788 fprintf (asm_out_file, "\n");
20790 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20791 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20792 fprintf (asm_out_file, " = .+32768\n");
20795 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20797 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
20798 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
20801 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20802 if (!toc_initialized)
20804 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
20805 fprintf (asm_out_file, " = .+32768\n");
20806 toc_initialized = 1;
20811 /* Implement TARGET_ASM_INIT_SECTIONS. */
20814 rs6000_elf_asm_init_sections (void)
20817 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
20820 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
20821 SDATA2_SECTION_ASM_OP);
20824 /* Implement TARGET_SELECT_RTX_SECTION. */
20827 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
20828 unsigned HOST_WIDE_INT align)
20830 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20831 return toc_section;
20833 return default_elf_select_rtx_section (mode, x, align);
20836 /* For a SYMBOL_REF, set generic flags and then perform some
20837 target-specific processing.
20839 When the AIX ABI is requested on a non-AIX system, replace the
20840 function name with the real name (with a leading .) rather than the
20841 function descriptor name. This saves a lot of overriding code to
20842 read the prefixes. */
20845 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
20847 default_encode_section_info (decl, rtl, first);
20850 && TREE_CODE (decl) == FUNCTION_DECL
20852 && DEFAULT_ABI == ABI_AIX)
20854 rtx sym_ref = XEXP (rtl, 0);
20855 size_t len = strlen (XSTR (sym_ref, 0));
20856 char *str = XALLOCAVEC (char, len + 2);
20858 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
20859 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
20864 compare_section_name (const char *section, const char *templ)
20868 len = strlen (templ);
20869 return (strncmp (section, templ, len) == 0
20870 && (section[len] == 0 || section[len] == '.'));
20874 rs6000_elf_in_small_data_p (const_tree decl)
20876 if (rs6000_sdata == SDATA_NONE)
20879 /* We want to merge strings, so we never consider them small data. */
20880 if (TREE_CODE (decl) == STRING_CST)
20883 /* Functions are never in the small data area. */
20884 if (TREE_CODE (decl) == FUNCTION_DECL)
20887 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
20889 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
20890 if (compare_section_name (section, ".sdata")
20891 || compare_section_name (section, ".sdata2")
20892 || compare_section_name (section, ".gnu.linkonce.s")
20893 || compare_section_name (section, ".sbss")
20894 || compare_section_name (section, ".sbss2")
20895 || compare_section_name (section, ".gnu.linkonce.sb")
20896 || strcmp (section, ".PPC.EMB.sdata0") == 0
20897 || strcmp (section, ".PPC.EMB.sbss0") == 0)
20902 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
20905 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20906 /* If it's not public, and we're not going to reference it there,
20907 there's no need to put it in the small data section. */
20908 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
20915 #endif /* USING_ELFOS_H */
20917 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20920 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
20922 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
20925 /* Return a REG that occurs in ADDR with coefficient 1.
20926 ADDR can be effectively incremented by incrementing REG.
20928 r0 is special and we must not select it as an address
20929 register by this routine since our caller will try to
20930 increment the returned register via an "la" instruction. */
20933 find_addr_reg (rtx addr)
20935 while (GET_CODE (addr) == PLUS)
20937 if (GET_CODE (XEXP (addr, 0)) == REG
20938 && REGNO (XEXP (addr, 0)) != 0)
20939 addr = XEXP (addr, 0);
20940 else if (GET_CODE (XEXP (addr, 1)) == REG
20941 && REGNO (XEXP (addr, 1)) != 0)
20942 addr = XEXP (addr, 1);
20943 else if (CONSTANT_P (XEXP (addr, 0)))
20944 addr = XEXP (addr, 1);
20945 else if (CONSTANT_P (XEXP (addr, 1)))
20946 addr = XEXP (addr, 0);
20948 gcc_unreachable ();
20950 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
20955 rs6000_fatal_bad_address (rtx op)
20957 fatal_insn ("bad address", op);
20962 static tree branch_island_list = 0;
20964 /* Remember to generate a branch island for far calls to the given
20968 add_compiler_branch_island (tree label_name, tree function_name,
20971 tree branch_island = build_tree_list (function_name, label_name);
20972 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
20973 TREE_CHAIN (branch_island) = branch_island_list;
20974 branch_island_list = branch_island;
20977 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20978 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20979 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20980 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20982 /* Generate far-jump branch islands for everything on the
20983 branch_island_list. Invoked immediately after the last instruction
20984 of the epilogue has been emitted; the branch-islands must be
20985 appended to, and contiguous with, the function body. Mach-O stubs
20986 are generated in machopic_output_stub(). */
20989 macho_branch_islands (void)
20992 tree branch_island;
20994 for (branch_island = branch_island_list;
20996 branch_island = TREE_CHAIN (branch_island))
20998 const char *label =
20999 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
21001 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
21002 char name_buf[512];
21003 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
21004 if (name[0] == '*' || name[0] == '&')
21005 strcpy (name_buf, name+1);
21009 strcpy (name_buf+1, name);
21011 strcpy (tmp_buf, "\n");
21012 strcat (tmp_buf, label);
21013 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
21014 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
21015 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
21016 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
21019 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
21020 strcat (tmp_buf, label);
21021 strcat (tmp_buf, "_pic\n");
21022 strcat (tmp_buf, label);
21023 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
21025 strcat (tmp_buf, "\taddis r11,r11,ha16(");
21026 strcat (tmp_buf, name_buf);
21027 strcat (tmp_buf, " - ");
21028 strcat (tmp_buf, label);
21029 strcat (tmp_buf, "_pic)\n");
21031 strcat (tmp_buf, "\tmtlr r0\n");
21033 strcat (tmp_buf, "\taddi r12,r11,lo16(");
21034 strcat (tmp_buf, name_buf);
21035 strcat (tmp_buf, " - ");
21036 strcat (tmp_buf, label);
21037 strcat (tmp_buf, "_pic)\n");
21039 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
21043 strcat (tmp_buf, ":\nlis r12,hi16(");
21044 strcat (tmp_buf, name_buf);
21045 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
21046 strcat (tmp_buf, name_buf);
21047 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
21049 output_asm_insn (tmp_buf, 0);
21050 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
21051 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
21052 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
21053 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
21056 branch_island_list = 0;
21059 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
21060 already there or not. */
21063 no_previous_def (tree function_name)
21065 tree branch_island;
21066 for (branch_island = branch_island_list;
21068 branch_island = TREE_CHAIN (branch_island))
21069 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
21074 /* GET_PREV_LABEL gets the label name from the previous definition of
21078 get_prev_label (tree function_name)
21080 tree branch_island;
21081 for (branch_island = branch_island_list;
21083 branch_island = TREE_CHAIN (branch_island))
21084 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
21085 return BRANCH_ISLAND_LABEL_NAME (branch_island);
21089 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
21090 #define DARWIN_LINKER_GENERATES_ISLANDS 0
21093 /* KEXTs still need branch islands. */
21094 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
21095 || flag_mkernel || flag_apple_kext)
21097 /* INSN is either a function call or a millicode call. It may have an
21098 unconditional jump in its delay slot.
21100 CALL_DEST is the routine we are calling. */
21103 output_call (rtx insn, rtx *operands, int dest_operand_number,
21104 int cookie_operand_number)
21106 static char buf[256];
21107 if (DARWIN_GENERATE_ISLANDS
21108 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
21109 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
21112 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
21114 if (no_previous_def (funname))
21116 rtx label_rtx = gen_label_rtx ();
21117 char *label_buf, temp_buf[256];
21118 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
21119 CODE_LABEL_NUMBER (label_rtx));
21120 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
21121 labelname = get_identifier (label_buf);
21122 add_compiler_branch_island (labelname, funname, insn_line (insn));
21125 labelname = get_prev_label (funname);
21127 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21128 instruction will reach 'foo', otherwise link as 'bl L42'".
21129 "L42" should be a 'branch island', that will do a far jump to
21130 'foo'. Branch islands are generated in
21131 macho_branch_islands(). */
21132 sprintf (buf, "jbsr %%z%d,%.246s",
21133 dest_operand_number, IDENTIFIER_POINTER (labelname));
21136 sprintf (buf, "bl %%z%d", dest_operand_number);
21140 /* Generate PIC and indirect symbol stubs. */
21143 machopic_output_stub (FILE *file, const char *symb, const char *stub)
21145 unsigned int length;
21146 char *symbol_name, *lazy_ptr_name;
21147 char *local_label_0;
21148 static int label = 0;
21150 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
21151 symb = (*targetm.strip_name_encoding) (symb);
21154 length = strlen (symb);
21155 symbol_name = XALLOCAVEC (char, length + 32);
21156 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
21158 lazy_ptr_name = XALLOCAVEC (char, length + 32);
21159 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
21162 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
21164 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
21168 fprintf (file, "\t.align 5\n");
21170 fprintf (file, "%s:\n", stub);
21171 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
21174 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
21175 sprintf (local_label_0, "\"L%011d$spb\"", label);
21177 fprintf (file, "\tmflr r0\n");
21178 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
21179 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
21180 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
21181 lazy_ptr_name, local_label_0);
21182 fprintf (file, "\tmtlr r0\n");
21183 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
21184 (TARGET_64BIT ? "ldu" : "lwzu"),
21185 lazy_ptr_name, local_label_0);
21186 fprintf (file, "\tmtctr r12\n");
21187 fprintf (file, "\tbctr\n");
21191 fprintf (file, "\t.align 4\n");
21193 fprintf (file, "%s:\n", stub);
21194 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
21196 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
21197 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
21198 (TARGET_64BIT ? "ldu" : "lwzu"),
21200 fprintf (file, "\tmtctr r12\n");
21201 fprintf (file, "\tbctr\n");
21204 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
21205 fprintf (file, "%s:\n", lazy_ptr_name);
21206 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
21207 fprintf (file, "%sdyld_stub_binding_helper\n",
21208 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
21211 /* Legitimize PIC addresses. If the address is already
21212 position-independent, we return ORIG. Newly generated
21213 position-independent addresses go into a reg. This is REG if non
21214 zero, otherwise we allocate register(s) as necessary. */
21216 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
21219 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
21224 if (reg == NULL && ! reload_in_progress && ! reload_completed)
21225 reg = gen_reg_rtx (Pmode);
21227 if (GET_CODE (orig) == CONST)
21231 if (GET_CODE (XEXP (orig, 0)) == PLUS
21232 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
21235 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
21237 /* Use a different reg for the intermediate value, as
21238 it will be marked UNCHANGING. */
21239 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
21240 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
21243 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
21246 if (GET_CODE (offset) == CONST_INT)
21248 if (SMALL_INT (offset))
21249 return plus_constant (base, INTVAL (offset));
21250 else if (! reload_in_progress && ! reload_completed)
21251 offset = force_reg (Pmode, offset);
21254 rtx mem = force_const_mem (Pmode, orig);
21255 return machopic_legitimize_pic_address (mem, Pmode, reg);
21258 return gen_rtx_PLUS (Pmode, base, offset);
21261 /* Fall back on generic machopic code. */
21262 return machopic_legitimize_pic_address (orig, mode, reg);
21265 /* Output a .machine directive for the Darwin assembler, and call
21266 the generic start_file routine. */
21269 rs6000_darwin_file_start (void)
21271 static const struct
21277 { "ppc64", "ppc64", MASK_64BIT },
21278 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
21279 { "power4", "ppc970", 0 },
21280 { "G5", "ppc970", 0 },
21281 { "7450", "ppc7450", 0 },
21282 { "7400", "ppc7400", MASK_ALTIVEC },
21283 { "G4", "ppc7400", 0 },
21284 { "750", "ppc750", 0 },
21285 { "740", "ppc750", 0 },
21286 { "G3", "ppc750", 0 },
21287 { "604e", "ppc604e", 0 },
21288 { "604", "ppc604", 0 },
21289 { "603e", "ppc603", 0 },
21290 { "603", "ppc603", 0 },
21291 { "601", "ppc601", 0 },
21292 { NULL, "ppc", 0 } };
21293 const char *cpu_id = "";
21296 rs6000_file_start ();
21297 darwin_file_start ();
21299 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
21300 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
21301 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
21302 && rs6000_select[i].string[0] != '\0')
21303 cpu_id = rs6000_select[i].string;
21305 /* Look through the mapping array. Pick the first name that either
21306 matches the argument, has a bit set in IF_SET that is also set
21307 in the target flags, or has a NULL name. */
21310 while (mapping[i].arg != NULL
21311 && strcmp (mapping[i].arg, cpu_id) != 0
21312 && (mapping[i].if_set & target_flags) == 0)
21315 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
21318 #endif /* TARGET_MACHO */
21322 rs6000_elf_reloc_rw_mask (void)
21326 else if (DEFAULT_ABI == ABI_AIX)
21332 /* Record an element in the table of global constructors. SYMBOL is
21333 a SYMBOL_REF of the function to be called; PRIORITY is a number
21334 between 0 and MAX_INIT_PRIORITY.
21336 This differs from default_named_section_asm_out_constructor in
21337 that we have special handling for -mrelocatable. */
21340 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
21342 const char *section = ".ctors";
21345 if (priority != DEFAULT_INIT_PRIORITY)
21347 sprintf (buf, ".ctors.%.5u",
21348 /* Invert the numbering so the linker puts us in the proper
21349 order; constructors are run from right to left, and the
21350 linker sorts in increasing order. */
21351 MAX_INIT_PRIORITY - priority);
21355 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21356 assemble_align (POINTER_SIZE);
21358 if (TARGET_RELOCATABLE)
21360 fputs ("\t.long (", asm_out_file);
21361 output_addr_const (asm_out_file, symbol);
21362 fputs (")@fixup\n", asm_out_file);
21365 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21369 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
21371 const char *section = ".dtors";
21374 if (priority != DEFAULT_INIT_PRIORITY)
21376 sprintf (buf, ".dtors.%.5u",
21377 /* Invert the numbering so the linker puts us in the proper
21378 order; constructors are run from right to left, and the
21379 linker sorts in increasing order. */
21380 MAX_INIT_PRIORITY - priority);
21384 switch_to_section (get_section (section, SECTION_WRITE, NULL));
21385 assemble_align (POINTER_SIZE);
21387 if (TARGET_RELOCATABLE)
21389 fputs ("\t.long (", asm_out_file);
21390 output_addr_const (asm_out_file, symbol);
21391 fputs (")@fixup\n", asm_out_file);
21394 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
21398 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
21402 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
21403 ASM_OUTPUT_LABEL (file, name);
21404 fputs (DOUBLE_INT_ASM_OP, file);
21405 rs6000_output_function_entry (file, name);
21406 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
21409 fputs ("\t.size\t", file);
21410 assemble_name (file, name);
21411 fputs (",24\n\t.type\t.", file);
21412 assemble_name (file, name);
21413 fputs (",@function\n", file);
21414 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
21416 fputs ("\t.globl\t.", file);
21417 assemble_name (file, name);
21422 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21423 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21424 rs6000_output_function_entry (file, name);
21425 fputs (":\n", file);
21429 if (TARGET_RELOCATABLE
21430 && !TARGET_SECURE_PLT
21431 && (get_pool_size () != 0 || crtl->profile)
21436 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
21438 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
21439 fprintf (file, "\t.long ");
21440 assemble_name (file, buf);
21442 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
21443 assemble_name (file, buf);
21447 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
21448 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
21450 if (DEFAULT_ABI == ABI_AIX)
21452 const char *desc_name, *orig_name;
21454 orig_name = (*targetm.strip_name_encoding) (name);
21455 desc_name = orig_name;
21456 while (*desc_name == '.')
21459 if (TREE_PUBLIC (decl))
21460 fprintf (file, "\t.globl %s\n", desc_name);
21462 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
21463 fprintf (file, "%s:\n", desc_name);
21464 fprintf (file, "\t.long %s\n", orig_name);
21465 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
21466 if (DEFAULT_ABI == ABI_AIX)
21467 fputs ("\t.long 0\n", file);
21468 fprintf (file, "\t.previous\n");
21470 ASM_OUTPUT_LABEL (file, name);
21474 rs6000_elf_end_indicate_exec_stack (void)
21477 file_end_indicate_exec_stack ();
21483 rs6000_xcoff_asm_output_anchor (rtx symbol)
21487 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
21488 SYMBOL_REF_BLOCK_OFFSET (symbol));
21489 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
21493 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
21495 fputs (GLOBAL_ASM_OP, stream);
21496 RS6000_OUTPUT_BASENAME (stream, name);
21497 putc ('\n', stream);
21500 /* A get_unnamed_decl callback, used for read-only sections. PTR
21501 points to the section string variable. */
21504 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
21506 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
21507 *(const char *const *) directive,
21508 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21511 /* Likewise for read-write sections. */
21514 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
21516 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
21517 *(const char *const *) directive,
21518 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
21521 /* A get_unnamed_section callback, used for switching to toc_section. */
21524 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
21526 if (TARGET_MINIMAL_TOC)
21528 /* toc_section is always selected at least once from
21529 rs6000_xcoff_file_start, so this is guaranteed to
21530 always be defined once and only once in each file. */
21531 if (!toc_initialized)
21533 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
21534 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
21535 toc_initialized = 1;
21537 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
21538 (TARGET_32BIT ? "" : ",3"));
21541 fputs ("\t.toc\n", asm_out_file);
21544 /* Implement TARGET_ASM_INIT_SECTIONS. */
21547 rs6000_xcoff_asm_init_sections (void)
21549 read_only_data_section
21550 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21551 &xcoff_read_only_section_name);
21553 private_data_section
21554 = get_unnamed_section (SECTION_WRITE,
21555 rs6000_xcoff_output_readwrite_section_asm_op,
21556 &xcoff_private_data_section_name);
21558 read_only_private_data_section
21559 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
21560 &xcoff_private_data_section_name);
21563 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
21565 readonly_data_section = read_only_data_section;
21566 exception_section = data_section;
21570 rs6000_xcoff_reloc_rw_mask (void)
21576 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
21577 tree decl ATTRIBUTE_UNUSED)
21580 static const char * const suffix[3] = { "PR", "RO", "RW" };
21582 if (flags & SECTION_CODE)
21584 else if (flags & SECTION_WRITE)
21589 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
21590 (flags & SECTION_CODE) ? "." : "",
21591 name, suffix[smclass], flags & SECTION_ENTSIZE);
21595 rs6000_xcoff_select_section (tree decl, int reloc,
21596 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21598 if (decl_readonly_section (decl, reloc))
21600 if (TREE_PUBLIC (decl))
21601 return read_only_data_section;
21603 return read_only_private_data_section;
21607 if (TREE_PUBLIC (decl))
21608 return data_section;
21610 return private_data_section;
21615 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
21619 /* Use select_section for private and uninitialized data. */
21620 if (!TREE_PUBLIC (decl)
21621 || DECL_COMMON (decl)
21622 || DECL_INITIAL (decl) == NULL_TREE
21623 || DECL_INITIAL (decl) == error_mark_node
21624 || (flag_zero_initialized_in_bss
21625 && initializer_zerop (DECL_INITIAL (decl))))
21628 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
21629 name = (*targetm.strip_name_encoding) (name);
21630 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
21633 /* Select section for constant in constant pool.
21635 On RS/6000, all constants are in the private read-only data area.
21636 However, if this is being placed in the TOC it must be output as a
21640 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
21641 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
21643 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
21644 return toc_section;
21646 return read_only_private_data_section;
21649 /* Remove any trailing [DS] or the like from the symbol name. */
21651 static const char *
21652 rs6000_xcoff_strip_name_encoding (const char *name)
21657 len = strlen (name);
21658 if (name[len - 1] == ']')
21659 return ggc_alloc_string (name, len - 4);
21664 /* Section attributes. AIX is always PIC. */
21666 static unsigned int
21667 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
21669 unsigned int align;
21670 unsigned int flags = default_section_type_flags (decl, name, reloc);
21672 /* Align to at least UNIT size. */
21673 if (flags & SECTION_CODE)
21674 align = MIN_UNITS_PER_WORD;
21676 /* Increase alignment of large objects if not already stricter. */
21677 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
21678 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
21679 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
21681 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
21684 /* Output at beginning of assembler file.
21686 Initialize the section names for the RS/6000 at this point.
21688 Specify filename, including full path, to assembler.
21690 We want to go into the TOC section so at least one .toc will be emitted.
21691 Also, in order to output proper .bs/.es pairs, we need at least one static
21692 [RW] section emitted.
21694 Finally, declare mcount when profiling to make the assembler happy. */
21697 rs6000_xcoff_file_start (void)
21699 rs6000_gen_section_name (&xcoff_bss_section_name,
21700 main_input_filename, ".bss_");
21701 rs6000_gen_section_name (&xcoff_private_data_section_name,
21702 main_input_filename, ".rw_");
21703 rs6000_gen_section_name (&xcoff_read_only_section_name,
21704 main_input_filename, ".ro_");
21706 fputs ("\t.file\t", asm_out_file);
21707 output_quoted_string (asm_out_file, main_input_filename);
21708 fputc ('\n', asm_out_file);
21709 if (write_symbols != NO_DEBUG)
21710 switch_to_section (private_data_section);
21711 switch_to_section (text_section);
21713 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
21714 rs6000_file_start ();
21717 /* Output at end of assembler file.
21718 On the RS/6000, referencing data should automatically pull in text. */
21721 rs6000_xcoff_file_end (void)
21723 switch_to_section (text_section);
21724 fputs ("_section_.text:\n", asm_out_file);
21725 switch_to_section (data_section);
21726 fputs (TARGET_32BIT
21727 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21730 #endif /* TARGET_XCOFF */
21732 /* Compute a (partial) cost for rtx X. Return true if the complete
21733 cost has been computed, and false if subexpressions should be
21734 scanned. In either case, *TOTAL contains the cost result. */
21737 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total,
21740 enum machine_mode mode = GET_MODE (x);
21744 /* On the RS/6000, if it is valid in the insn, it is free. */
21746 if (((outer_code == SET
21747 || outer_code == PLUS
21748 || outer_code == MINUS)
21749 && (satisfies_constraint_I (x)
21750 || satisfies_constraint_L (x)))
21751 || (outer_code == AND
21752 && (satisfies_constraint_K (x)
21754 ? satisfies_constraint_L (x)
21755 : satisfies_constraint_J (x))
21756 || mask_operand (x, mode)
21758 && mask64_operand (x, DImode))))
21759 || ((outer_code == IOR || outer_code == XOR)
21760 && (satisfies_constraint_K (x)
21762 ? satisfies_constraint_L (x)
21763 : satisfies_constraint_J (x))))
21764 || outer_code == ASHIFT
21765 || outer_code == ASHIFTRT
21766 || outer_code == LSHIFTRT
21767 || outer_code == ROTATE
21768 || outer_code == ROTATERT
21769 || outer_code == ZERO_EXTRACT
21770 || (outer_code == MULT
21771 && satisfies_constraint_I (x))
21772 || ((outer_code == DIV || outer_code == UDIV
21773 || outer_code == MOD || outer_code == UMOD)
21774 && exact_log2 (INTVAL (x)) >= 0)
21775 || (outer_code == COMPARE
21776 && (satisfies_constraint_I (x)
21777 || satisfies_constraint_K (x)))
21778 || (outer_code == EQ
21779 && (satisfies_constraint_I (x)
21780 || satisfies_constraint_K (x)
21782 ? satisfies_constraint_L (x)
21783 : satisfies_constraint_J (x))))
21784 || (outer_code == GTU
21785 && satisfies_constraint_I (x))
21786 || (outer_code == LTU
21787 && satisfies_constraint_P (x)))
21792 else if ((outer_code == PLUS
21793 && reg_or_add_cint_operand (x, VOIDmode))
21794 || (outer_code == MINUS
21795 && reg_or_sub_cint_operand (x, VOIDmode))
21796 || ((outer_code == SET
21797 || outer_code == IOR
21798 || outer_code == XOR)
21800 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
21802 *total = COSTS_N_INSNS (1);
21808 if (mode == DImode && code == CONST_DOUBLE)
21810 if ((outer_code == IOR || outer_code == XOR)
21811 && CONST_DOUBLE_HIGH (x) == 0
21812 && (CONST_DOUBLE_LOW (x)
21813 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
21818 else if ((outer_code == AND && and64_2_operand (x, DImode))
21819 || ((outer_code == SET
21820 || outer_code == IOR
21821 || outer_code == XOR)
21822 && CONST_DOUBLE_HIGH (x) == 0))
21824 *total = COSTS_N_INSNS (1);
21834 /* When optimizing for size, MEM should be slightly more expensive
21835 than generating address, e.g., (plus (reg) (const)).
21836 L1 cache latency is about two instructions. */
21837 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21845 if (mode == DFmode)
21847 if (GET_CODE (XEXP (x, 0)) == MULT)
21849 /* FNMA accounted in outer NEG. */
21850 if (outer_code == NEG)
21851 *total = rs6000_cost->dmul - rs6000_cost->fp;
21853 *total = rs6000_cost->dmul;
21856 *total = rs6000_cost->fp;
21858 else if (mode == SFmode)
21860 /* FNMA accounted in outer NEG. */
21861 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21864 *total = rs6000_cost->fp;
21867 *total = COSTS_N_INSNS (1);
21871 if (mode == DFmode)
21873 if (GET_CODE (XEXP (x, 0)) == MULT
21874 || GET_CODE (XEXP (x, 1)) == MULT)
21876 /* FNMA accounted in outer NEG. */
21877 if (outer_code == NEG)
21878 *total = rs6000_cost->dmul - rs6000_cost->fp;
21880 *total = rs6000_cost->dmul;
21883 *total = rs6000_cost->fp;
21885 else if (mode == SFmode)
21887 /* FNMA accounted in outer NEG. */
21888 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
21891 *total = rs6000_cost->fp;
21894 *total = COSTS_N_INSNS (1);
21898 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21899 && satisfies_constraint_I (XEXP (x, 1)))
21901 if (INTVAL (XEXP (x, 1)) >= -256
21902 && INTVAL (XEXP (x, 1)) <= 255)
21903 *total = rs6000_cost->mulsi_const9;
21905 *total = rs6000_cost->mulsi_const;
21907 /* FMA accounted in outer PLUS/MINUS. */
21908 else if ((mode == DFmode || mode == SFmode)
21909 && (outer_code == PLUS || outer_code == MINUS))
21911 else if (mode == DFmode)
21912 *total = rs6000_cost->dmul;
21913 else if (mode == SFmode)
21914 *total = rs6000_cost->fp;
21915 else if (mode == DImode)
21916 *total = rs6000_cost->muldi;
21918 *total = rs6000_cost->mulsi;
21923 if (FLOAT_MODE_P (mode))
21925 *total = mode == DFmode ? rs6000_cost->ddiv
21926 : rs6000_cost->sdiv;
21933 if (GET_CODE (XEXP (x, 1)) == CONST_INT
21934 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
21936 if (code == DIV || code == MOD)
21938 *total = COSTS_N_INSNS (2);
21941 *total = COSTS_N_INSNS (1);
21945 if (GET_MODE (XEXP (x, 1)) == DImode)
21946 *total = rs6000_cost->divdi;
21948 *total = rs6000_cost->divsi;
21950 /* Add in shift and subtract for MOD. */
21951 if (code == MOD || code == UMOD)
21952 *total += COSTS_N_INSNS (2);
21957 *total = COSTS_N_INSNS (4);
21961 *total = COSTS_N_INSNS (6);
21965 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
21977 *total = COSTS_N_INSNS (1);
21985 /* Handle mul_highpart. */
21986 if (outer_code == TRUNCATE
21987 && GET_CODE (XEXP (x, 0)) == MULT)
21989 if (mode == DImode)
21990 *total = rs6000_cost->muldi;
21992 *total = rs6000_cost->mulsi;
21995 else if (outer_code == AND)
21998 *total = COSTS_N_INSNS (1);
22003 if (GET_CODE (XEXP (x, 0)) == MEM)
22006 *total = COSTS_N_INSNS (1);
22012 if (!FLOAT_MODE_P (mode))
22014 *total = COSTS_N_INSNS (1);
22020 case UNSIGNED_FLOAT:
22023 case FLOAT_TRUNCATE:
22024 *total = rs6000_cost->fp;
22028 if (mode == DFmode)
22031 *total = rs6000_cost->fp;
22035 switch (XINT (x, 1))
22038 *total = rs6000_cost->fp;
22050 *total = COSTS_N_INSNS (1);
22053 else if (FLOAT_MODE_P (mode)
22054 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
22056 *total = rs6000_cost->fp;
22064 /* Carry bit requires mode == Pmode.
22065 NEG or PLUS already counted so only add one. */
22067 && (outer_code == NEG || outer_code == PLUS))
22069 *total = COSTS_N_INSNS (1);
22072 if (outer_code == SET)
22074 if (XEXP (x, 1) == const0_rtx)
22076 *total = COSTS_N_INSNS (2);
22079 else if (mode == Pmode)
22081 *total = COSTS_N_INSNS (3);
22090 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
22092 *total = COSTS_N_INSNS (2);
22096 if (outer_code == COMPARE)
22110 /* A C expression returning the cost of moving data from a register of class
22111 CLASS1 to one of CLASS2. */
22114 rs6000_register_move_cost (enum machine_mode mode,
22115 enum reg_class from, enum reg_class to)
22117 /* Moves from/to GENERAL_REGS. */
22118 if (reg_classes_intersect_p (to, GENERAL_REGS)
22119 || reg_classes_intersect_p (from, GENERAL_REGS))
22121 if (! reg_classes_intersect_p (to, GENERAL_REGS))
22124 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
22125 return (rs6000_memory_move_cost (mode, from, 0)
22126 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
22128 /* It's more expensive to move CR_REGS than CR0_REGS because of the
22130 else if (from == CR_REGS)
22133 /* Power6 has slower LR/CTR moves so make them more expensive than
22134 memory in order to bias spills to memory .*/
22135 else if (rs6000_cpu == PROCESSOR_POWER6
22136 && reg_classes_intersect_p (from, LINK_OR_CTR_REGS))
22137 return 6 * hard_regno_nregs[0][mode];
22140 /* A move will cost one instruction per GPR moved. */
22141 return 2 * hard_regno_nregs[0][mode];
22144 /* Moving between two similar registers is just one instruction. */
22145 else if (reg_classes_intersect_p (to, from))
22146 return (mode == TFmode || mode == TDmode) ? 4 : 2;
22148 /* Everything else has to go through GENERAL_REGS. */
22150 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
22151 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
22154 /* A C expressions returning the cost of moving data of MODE from a register to
22158 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class rclass,
22159 int in ATTRIBUTE_UNUSED)
22161 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
22162 return 4 * hard_regno_nregs[0][mode];
22163 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
22164 return 4 * hard_regno_nregs[32][mode];
22165 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
22166 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
22168 return 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
22171 /* Returns a code for a target-specific builtin that implements
22172 reciprocal of the function, or NULL_TREE if not available. */
22175 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
22176 bool sqrt ATTRIBUTE_UNUSED)
22178 if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size
22179 && flag_finite_math_only && !flag_trapping_math
22180 && flag_unsafe_math_optimizations))
22188 case BUILT_IN_SQRTF:
22189 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
22196 /* Newton-Raphson approximation of single-precision floating point divide n/d.
22197 Assumes no trapping math and finite arguments. */
22200 rs6000_emit_swdivsf (rtx dst, rtx n, rtx d)
22202 rtx x0, e0, e1, y1, u0, v0, one;
22204 x0 = gen_reg_rtx (SFmode);
22205 e0 = gen_reg_rtx (SFmode);
22206 e1 = gen_reg_rtx (SFmode);
22207 y1 = gen_reg_rtx (SFmode);
22208 u0 = gen_reg_rtx (SFmode);
22209 v0 = gen_reg_rtx (SFmode);
22210 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
22212 /* x0 = 1./d estimate */
22213 emit_insn (gen_rtx_SET (VOIDmode, x0,
22214 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
22216 /* e0 = 1. - d * x0 */
22217 emit_insn (gen_rtx_SET (VOIDmode, e0,
22218 gen_rtx_MINUS (SFmode, one,
22219 gen_rtx_MULT (SFmode, d, x0))));
22220 /* e1 = e0 + e0 * e0 */
22221 emit_insn (gen_rtx_SET (VOIDmode, e1,
22222 gen_rtx_PLUS (SFmode,
22223 gen_rtx_MULT (SFmode, e0, e0), e0)));
22224 /* y1 = x0 + e1 * x0 */
22225 emit_insn (gen_rtx_SET (VOIDmode, y1,
22226 gen_rtx_PLUS (SFmode,
22227 gen_rtx_MULT (SFmode, e1, x0), x0)));
22229 emit_insn (gen_rtx_SET (VOIDmode, u0,
22230 gen_rtx_MULT (SFmode, n, y1)));
22231 /* v0 = n - d * u0 */
22232 emit_insn (gen_rtx_SET (VOIDmode, v0,
22233 gen_rtx_MINUS (SFmode, n,
22234 gen_rtx_MULT (SFmode, d, u0))));
22235 /* dst = u0 + v0 * y1 */
22236 emit_insn (gen_rtx_SET (VOIDmode, dst,
22237 gen_rtx_PLUS (SFmode,
22238 gen_rtx_MULT (SFmode, v0, y1), u0)));
22241 /* Newton-Raphson approximation of double-precision floating point divide n/d.
22242 Assumes no trapping math and finite arguments. */
22245 rs6000_emit_swdivdf (rtx dst, rtx n, rtx d)
22247 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
22249 x0 = gen_reg_rtx (DFmode);
22250 e0 = gen_reg_rtx (DFmode);
22251 e1 = gen_reg_rtx (DFmode);
22252 e2 = gen_reg_rtx (DFmode);
22253 y1 = gen_reg_rtx (DFmode);
22254 y2 = gen_reg_rtx (DFmode);
22255 y3 = gen_reg_rtx (DFmode);
22256 u0 = gen_reg_rtx (DFmode);
22257 v0 = gen_reg_rtx (DFmode);
22258 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
22260 /* x0 = 1./d estimate */
22261 emit_insn (gen_rtx_SET (VOIDmode, x0,
22262 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
22264 /* e0 = 1. - d * x0 */
22265 emit_insn (gen_rtx_SET (VOIDmode, e0,
22266 gen_rtx_MINUS (DFmode, one,
22267 gen_rtx_MULT (SFmode, d, x0))));
22268 /* y1 = x0 + e0 * x0 */
22269 emit_insn (gen_rtx_SET (VOIDmode, y1,
22270 gen_rtx_PLUS (DFmode,
22271 gen_rtx_MULT (DFmode, e0, x0), x0)));
22273 emit_insn (gen_rtx_SET (VOIDmode, e1,
22274 gen_rtx_MULT (DFmode, e0, e0)));
22275 /* y2 = y1 + e1 * y1 */
22276 emit_insn (gen_rtx_SET (VOIDmode, y2,
22277 gen_rtx_PLUS (DFmode,
22278 gen_rtx_MULT (DFmode, e1, y1), y1)));
22280 emit_insn (gen_rtx_SET (VOIDmode, e2,
22281 gen_rtx_MULT (DFmode, e1, e1)));
22282 /* y3 = y2 + e2 * y2 */
22283 emit_insn (gen_rtx_SET (VOIDmode, y3,
22284 gen_rtx_PLUS (DFmode,
22285 gen_rtx_MULT (DFmode, e2, y2), y2)));
22287 emit_insn (gen_rtx_SET (VOIDmode, u0,
22288 gen_rtx_MULT (DFmode, n, y3)));
22289 /* v0 = n - d * u0 */
22290 emit_insn (gen_rtx_SET (VOIDmode, v0,
22291 gen_rtx_MINUS (DFmode, n,
22292 gen_rtx_MULT (DFmode, d, u0))));
22293 /* dst = u0 + v0 * y3 */
22294 emit_insn (gen_rtx_SET (VOIDmode, dst,
22295 gen_rtx_PLUS (DFmode,
22296 gen_rtx_MULT (DFmode, v0, y3), u0)));
22300 /* Newton-Raphson approximation of single-precision floating point rsqrt.
22301 Assumes no trapping math and finite arguments. */
22304 rs6000_emit_swrsqrtsf (rtx dst, rtx src)
22306 rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0,
22307 half, one, halfthree, c1, cond, label;
22309 x0 = gen_reg_rtx (SFmode);
22310 x1 = gen_reg_rtx (SFmode);
22311 x2 = gen_reg_rtx (SFmode);
22312 y1 = gen_reg_rtx (SFmode);
22313 u0 = gen_reg_rtx (SFmode);
22314 u1 = gen_reg_rtx (SFmode);
22315 u2 = gen_reg_rtx (SFmode);
22316 v0 = gen_reg_rtx (SFmode);
22317 v1 = gen_reg_rtx (SFmode);
22318 v2 = gen_reg_rtx (SFmode);
22319 t0 = gen_reg_rtx (SFmode);
22320 halfthree = gen_reg_rtx (SFmode);
22321 cond = gen_rtx_REG (CCFPmode, CR1_REGNO);
22322 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
22324 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
22325 emit_insn (gen_rtx_SET (VOIDmode, t0,
22326 gen_rtx_MULT (SFmode, src, src)));
22328 emit_insn (gen_rtx_SET (VOIDmode, cond,
22329 gen_rtx_COMPARE (CCFPmode, t0, src)));
22330 c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx);
22331 emit_unlikely_jump (c1, label);
22333 half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode));
22334 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
22336 /* halfthree = 1.5 = 1.0 + 0.5 */
22337 emit_insn (gen_rtx_SET (VOIDmode, halfthree,
22338 gen_rtx_PLUS (SFmode, one, half)));
22340 /* x0 = rsqrt estimate */
22341 emit_insn (gen_rtx_SET (VOIDmode, x0,
22342 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src),
22345 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
22346 emit_insn (gen_rtx_SET (VOIDmode, y1,
22347 gen_rtx_MINUS (SFmode,
22348 gen_rtx_MULT (SFmode, src, halfthree),
22351 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
22352 emit_insn (gen_rtx_SET (VOIDmode, u0,
22353 gen_rtx_MULT (SFmode, x0, x0)));
22354 emit_insn (gen_rtx_SET (VOIDmode, v0,
22355 gen_rtx_MINUS (SFmode,
22357 gen_rtx_MULT (SFmode, y1, u0))));
22358 emit_insn (gen_rtx_SET (VOIDmode, x1,
22359 gen_rtx_MULT (SFmode, x0, v0)));
22361 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22362 emit_insn (gen_rtx_SET (VOIDmode, u1,
22363 gen_rtx_MULT (SFmode, x1, x1)));
22364 emit_insn (gen_rtx_SET (VOIDmode, v1,
22365 gen_rtx_MINUS (SFmode,
22367 gen_rtx_MULT (SFmode, y1, u1))));
22368 emit_insn (gen_rtx_SET (VOIDmode, x2,
22369 gen_rtx_MULT (SFmode, x1, v1)));
22371 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22372 emit_insn (gen_rtx_SET (VOIDmode, u2,
22373 gen_rtx_MULT (SFmode, x2, x2)));
22374 emit_insn (gen_rtx_SET (VOIDmode, v2,
22375 gen_rtx_MINUS (SFmode,
22377 gen_rtx_MULT (SFmode, y1, u2))));
22378 emit_insn (gen_rtx_SET (VOIDmode, dst,
22379 gen_rtx_MULT (SFmode, x2, v2)));
22381 emit_label (XEXP (label, 0));
22384 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22385 target, and SRC is the argument operand. */
22388 rs6000_emit_popcount (rtx dst, rtx src)
22390 enum machine_mode mode = GET_MODE (dst);
22393 tmp1 = gen_reg_rtx (mode);
22395 if (mode == SImode)
22397 emit_insn (gen_popcntbsi2 (tmp1, src));
22398 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
22400 tmp2 = force_reg (SImode, tmp2);
22401 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
22405 emit_insn (gen_popcntbdi2 (tmp1, src));
22406 tmp2 = expand_mult (DImode, tmp1,
22407 GEN_INT ((HOST_WIDE_INT)
22408 0x01010101 << 32 | 0x01010101),
22410 tmp2 = force_reg (DImode, tmp2);
22411 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
22416 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22417 target, and SRC is the argument operand. */
22420 rs6000_emit_parity (rtx dst, rtx src)
22422 enum machine_mode mode = GET_MODE (dst);
22425 tmp = gen_reg_rtx (mode);
22426 if (mode == SImode)
22428 /* Is mult+shift >= shift+xor+shift+xor? */
22429 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
22431 rtx tmp1, tmp2, tmp3, tmp4;
22433 tmp1 = gen_reg_rtx (SImode);
22434 emit_insn (gen_popcntbsi2 (tmp1, src));
22436 tmp2 = gen_reg_rtx (SImode);
22437 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
22438 tmp3 = gen_reg_rtx (SImode);
22439 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
22441 tmp4 = gen_reg_rtx (SImode);
22442 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
22443 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
22446 rs6000_emit_popcount (tmp, src);
22447 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
22451 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22452 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
22454 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
22456 tmp1 = gen_reg_rtx (DImode);
22457 emit_insn (gen_popcntbdi2 (tmp1, src));
22459 tmp2 = gen_reg_rtx (DImode);
22460 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
22461 tmp3 = gen_reg_rtx (DImode);
22462 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
22464 tmp4 = gen_reg_rtx (DImode);
22465 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
22466 tmp5 = gen_reg_rtx (DImode);
22467 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
22469 tmp6 = gen_reg_rtx (DImode);
22470 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
22471 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
22474 rs6000_emit_popcount (tmp, src);
22475 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
22479 /* Return an RTX representing where to find the function value of a
22480 function returning MODE. */
22482 rs6000_complex_function_value (enum machine_mode mode)
22484 unsigned int regno;
22486 enum machine_mode inner = GET_MODE_INNER (mode);
22487 unsigned int inner_bytes = GET_MODE_SIZE (inner);
22489 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22490 regno = FP_ARG_RETURN;
22493 regno = GP_ARG_RETURN;
22495 /* 32-bit is OK since it'll go in r3/r4. */
22496 if (TARGET_32BIT && inner_bytes >= 4)
22497 return gen_rtx_REG (mode, regno);
22500 if (inner_bytes >= 8)
22501 return gen_rtx_REG (mode, regno);
22503 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
22505 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
22506 GEN_INT (inner_bytes));
22507 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
22510 /* Define how to find the value returned by a function.
22511 VALTYPE is the data type of the value (as a tree).
22512 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22513 otherwise, FUNC is 0.
22515 On the SPE, both FPs and vectors are returned in r3.
22517 On RS/6000 an integer value is in r3 and a floating-point value is in
22518 fp1, unless -msoft-float. */
22521 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
22523 enum machine_mode mode;
22524 unsigned int regno;
22526 /* Special handling for structs in darwin64. */
22527 if (rs6000_darwin64_abi
22528 && TYPE_MODE (valtype) == BLKmode
22529 && TREE_CODE (valtype) == RECORD_TYPE
22530 && int_size_in_bytes (valtype) > 0)
22532 CUMULATIVE_ARGS valcum;
22536 valcum.fregno = FP_ARG_MIN_REG;
22537 valcum.vregno = ALTIVEC_ARG_MIN_REG;
22538 /* Do a trial code generation as if this were going to be passed as
22539 an argument; if any part goes in memory, we return NULL. */
22540 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
22543 /* Otherwise fall through to standard ABI rules. */
22546 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
22548 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22549 return gen_rtx_PARALLEL (DImode,
22551 gen_rtx_EXPR_LIST (VOIDmode,
22552 gen_rtx_REG (SImode, GP_ARG_RETURN),
22554 gen_rtx_EXPR_LIST (VOIDmode,
22555 gen_rtx_REG (SImode,
22556 GP_ARG_RETURN + 1),
22559 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
22561 return gen_rtx_PARALLEL (DCmode,
22563 gen_rtx_EXPR_LIST (VOIDmode,
22564 gen_rtx_REG (SImode, GP_ARG_RETURN),
22566 gen_rtx_EXPR_LIST (VOIDmode,
22567 gen_rtx_REG (SImode,
22568 GP_ARG_RETURN + 1),
22570 gen_rtx_EXPR_LIST (VOIDmode,
22571 gen_rtx_REG (SImode,
22572 GP_ARG_RETURN + 2),
22574 gen_rtx_EXPR_LIST (VOIDmode,
22575 gen_rtx_REG (SImode,
22576 GP_ARG_RETURN + 3),
22580 mode = TYPE_MODE (valtype);
22581 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
22582 || POINTER_TYPE_P (valtype))
22583 mode = TARGET_32BIT ? SImode : DImode;
22585 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22586 /* _Decimal128 must use an even/odd register pair. */
22587 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22588 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
22589 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
22590 regno = FP_ARG_RETURN;
22591 else if (TREE_CODE (valtype) == COMPLEX_TYPE
22592 && targetm.calls.split_complex_arg)
22593 return rs6000_complex_function_value (mode);
22594 else if (TREE_CODE (valtype) == VECTOR_TYPE
22595 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
22596 && ALTIVEC_VECTOR_MODE (mode))
22597 regno = ALTIVEC_ARG_RETURN;
22598 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22599 && (mode == DFmode || mode == DCmode
22600 || mode == TFmode || mode == TCmode))
22601 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22603 regno = GP_ARG_RETURN;
22605 return gen_rtx_REG (mode, regno);
22608 /* Define how to find the value returned by a library function
22609 assuming the value has mode MODE. */
22611 rs6000_libcall_value (enum machine_mode mode)
22613 unsigned int regno;
22615 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
22617 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22618 return gen_rtx_PARALLEL (DImode,
22620 gen_rtx_EXPR_LIST (VOIDmode,
22621 gen_rtx_REG (SImode, GP_ARG_RETURN),
22623 gen_rtx_EXPR_LIST (VOIDmode,
22624 gen_rtx_REG (SImode,
22625 GP_ARG_RETURN + 1),
22629 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
22630 /* _Decimal128 must use an even/odd register pair. */
22631 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
22632 else if (SCALAR_FLOAT_MODE_P (mode)
22633 && TARGET_HARD_FLOAT && TARGET_FPRS)
22634 regno = FP_ARG_RETURN;
22635 else if (ALTIVEC_VECTOR_MODE (mode)
22636 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
22637 regno = ALTIVEC_ARG_RETURN;
22638 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
22639 return rs6000_complex_function_value (mode);
22640 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
22641 && (mode == DFmode || mode == DCmode
22642 || mode == TFmode || mode == TCmode))
22643 return spe_build_register_parallel (mode, GP_ARG_RETURN);
22645 regno = GP_ARG_RETURN;
22647 return gen_rtx_REG (mode, regno);
22650 /* Define the offset between two registers, FROM to be eliminated and its
22651 replacement TO, at the start of a routine. */
22653 rs6000_initial_elimination_offset (int from, int to)
22655 rs6000_stack_t *info = rs6000_stack_info ();
22656 HOST_WIDE_INT offset;
22658 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22659 offset = info->push_p ? 0 : -info->total_size;
22660 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22662 offset = info->push_p ? 0 : -info->total_size;
22663 if (FRAME_GROWS_DOWNWARD)
22664 offset += info->fixed_size + info->vars_size + info->parm_size;
22666 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22667 offset = FRAME_GROWS_DOWNWARD
22668 ? info->fixed_size + info->vars_size + info->parm_size
22670 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
22671 offset = info->total_size;
22672 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
22673 offset = info->push_p ? info->total_size : 0;
22674 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
22677 gcc_unreachable ();
22683 rs6000_dwarf_register_span (rtx reg)
22687 unsigned regno = REGNO (reg);
22688 enum machine_mode mode = GET_MODE (reg);
22692 && (SPE_VECTOR_MODE (GET_MODE (reg))
22693 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
22694 && mode != SFmode && mode != SDmode && mode != SCmode)))
22699 regno = REGNO (reg);
22701 /* The duality of the SPE register size wreaks all kinds of havoc.
22702 This is a way of distinguishing r0 in 32-bits from r0 in
22704 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
22705 gcc_assert (words <= 4);
22706 for (i = 0; i < words; i++, regno++)
22708 if (BYTES_BIG_ENDIAN)
22710 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
22711 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
22715 parts[2 * i] = gen_rtx_REG (SImode, regno);
22716 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
22720 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
22723 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22726 rs6000_init_dwarf_reg_sizes_extra (tree address)
22731 enum machine_mode mode = TYPE_MODE (char_type_node);
22732 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
22733 rtx mem = gen_rtx_MEM (BLKmode, addr);
22734 rtx value = gen_int_mode (4, mode);
22736 for (i = 1201; i < 1232; i++)
22738 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
22739 HOST_WIDE_INT offset
22740 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
22742 emit_move_insn (adjust_address (mem, mode, offset), value);
22747 /* Map internal gcc register numbers to DWARF2 register numbers. */
22750 rs6000_dbx_register_number (unsigned int regno)
22752 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
22754 if (regno == MQ_REGNO)
22756 if (regno == LR_REGNO)
22758 if (regno == CTR_REGNO)
22760 if (CR_REGNO_P (regno))
22761 return regno - CR0_REGNO + 86;
22762 if (regno == XER_REGNO)
22764 if (ALTIVEC_REGNO_P (regno))
22765 return regno - FIRST_ALTIVEC_REGNO + 1124;
22766 if (regno == VRSAVE_REGNO)
22768 if (regno == VSCR_REGNO)
22770 if (regno == SPE_ACC_REGNO)
22772 if (regno == SPEFSCR_REGNO)
22774 /* SPE high reg number. We get these values of regno from
22775 rs6000_dwarf_register_span. */
22776 gcc_assert (regno >= 1200 && regno < 1232);
22780 /* target hook eh_return_filter_mode */
22781 static enum machine_mode
22782 rs6000_eh_return_filter_mode (void)
22784 return TARGET_32BIT ? SImode : word_mode;
22787 /* Target hook for scalar_mode_supported_p. */
22789 rs6000_scalar_mode_supported_p (enum machine_mode mode)
22791 if (DECIMAL_FLOAT_MODE_P (mode))
22794 return default_scalar_mode_supported_p (mode);
22797 /* Target hook for vector_mode_supported_p. */
22799 rs6000_vector_mode_supported_p (enum machine_mode mode)
22802 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
22805 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
22808 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
22815 /* Target hook for invalid_arg_for_unprototyped_fn. */
22816 static const char *
22817 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
22819 return (!rs6000_darwin64_abi
22821 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
22822 && (funcdecl == NULL_TREE
22823 || (TREE_CODE (funcdecl) == FUNCTION_DECL
22824 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
22825 ? N_("AltiVec argument passed to unprototyped function")
22829 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22830 setup by using __stack_chk_fail_local hidden function instead of
22831 calling __stack_chk_fail directly. Otherwise it is better to call
22832 __stack_chk_fail directly. */
22835 rs6000_stack_protect_fail (void)
22837 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
22838 ? default_hidden_stack_protect_fail ()
22839 : default_external_stack_protect_fail ();
22843 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
22844 int num_operands ATTRIBUTE_UNUSED)
22846 if (rs6000_warn_cell_microcode)
22849 int insn_code_number = recog_memoized (insn);
22850 location_t location = locator_location (INSN_LOCATOR (insn));
22852 /* Punt on insns we cannot recognize. */
22853 if (insn_code_number < 0)
22856 temp = get_insn_template (insn_code_number, insn);
22858 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
22859 warning_at (location, OPT_mwarn_cell_microcode,
22860 "emitting microcode insn %s\t[%s] #%d",
22861 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
22862 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
22863 warning_at (location, OPT_mwarn_cell_microcode,
22864 "emitting conditional microcode insn %s\t[%s] #%d",
22865 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
22869 #include "gt-rs6000.h"