1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "integrate.h"
48 #include "target-def.h"
50 #ifndef TARGET_NO_PROTOTYPE
51 #define TARGET_NO_PROTOTYPE 0
54 extern int profile_block_flag;
56 #define min(A,B) ((A) < (B) ? (A) : (B))
57 #define max(A,B) ((A) > (B) ? (A) : (B))
61 enum processor_type rs6000_cpu;
62 struct rs6000_cpu_select rs6000_select[3] =
64 /* switch name, tune arch */
65 { (const char *)0, "--with-cpu=", 1, 1 },
66 { (const char *)0, "-mcpu=", 1, 1 },
67 { (const char *)0, "-mtune=", 1, 0 },
70 /* Set to non-zero once AIX common-mode calls have been defined. */
71 static int common_mode_defined;
73 /* Save information from a "cmpxx" operation until the branch or scc is
75 rtx rs6000_compare_op0, rs6000_compare_op1;
76 int rs6000_compare_fp_p;
78 /* Label number of label created for -mrelocatable, to call to so we can
79 get the address of the GOT section */
80 int rs6000_pic_labelno;
83 /* Which abi to adhere to */
84 const char *rs6000_abi_name = RS6000_ABI_NAME;
86 /* Semantics of the small data area */
87 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
89 /* Which small data model to use */
90 const char *rs6000_sdata_name = (char *)0;
92 /* Counter for labels which are to be placed in .fixup. */
96 /* ABI enumeration available for subtarget to use. */
97 enum rs6000_abi rs6000_current_abi;
100 const char *rs6000_debug_name;
101 int rs6000_debug_stack; /* debug stack applications */
102 int rs6000_debug_arg; /* debug argument handling */
104 /* Flag to say the TOC is initialized */
106 char toc_label_name[10];
108 /* Alias set for saves and restores from the rs6000 stack. */
109 static int rs6000_sr_alias_set;
111 static void rs6000_add_gc_roots PARAMS ((void));
112 static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT));
113 static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx));
114 static void validate_condition_mode
115 PARAMS ((enum rtx_code, enum machine_mode));
116 static rtx rs6000_generate_compare PARAMS ((enum rtx_code));
117 static void rs6000_maybe_dead PARAMS ((rtx));
118 static void rs6000_emit_stack_tie PARAMS ((void));
119 static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx));
120 static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int));
121 static unsigned rs6000_hash_constant PARAMS ((rtx));
122 static unsigned toc_hash_function PARAMS ((const void *));
123 static int toc_hash_eq PARAMS ((const void *, const void *));
124 static int toc_hash_mark_entry PARAMS ((void **, void *));
125 static void toc_hash_mark_table PARAMS ((void *));
126 static int constant_pool_expr_1 PARAMS ((rtx, int *, int *));
127 static void rs6000_free_machine_status PARAMS ((struct function *));
128 static void rs6000_init_machine_status PARAMS ((struct function *));
129 static int rs6000_ra_ever_killed PARAMS ((void));
130 static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *));
131 const struct attribute_spec rs6000_attribute_table[];
132 static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
133 static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
134 static rtx rs6000_emit_set_long_const PARAMS ((rtx,
135 HOST_WIDE_INT, HOST_WIDE_INT));
137 static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *,
139 static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int));
140 static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int));
142 #ifdef OBJECT_FORMAT_COFF
143 static void xcoff_asm_named_section PARAMS ((const char *, unsigned int));
145 static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
146 static int rs6000_adjust_priority PARAMS ((rtx, int));
147 static int rs6000_issue_rate PARAMS ((void));
150 /* Default register names. */
151 char rs6000_reg_names[][8] =
153 "0", "1", "2", "3", "4", "5", "6", "7",
154 "8", "9", "10", "11", "12", "13", "14", "15",
155 "16", "17", "18", "19", "20", "21", "22", "23",
156 "24", "25", "26", "27", "28", "29", "30", "31",
157 "0", "1", "2", "3", "4", "5", "6", "7",
158 "8", "9", "10", "11", "12", "13", "14", "15",
159 "16", "17", "18", "19", "20", "21", "22", "23",
160 "24", "25", "26", "27", "28", "29", "30", "31",
161 "mq", "lr", "ctr","ap",
162 "0", "1", "2", "3", "4", "5", "6", "7",
166 #ifdef TARGET_REGNAMES
167 static const char alt_reg_names[][8] =
169 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
170 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
171 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
172 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
173 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
174 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
175 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
176 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
177 "mq", "lr", "ctr", "ap",
178 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
183 #ifndef MASK_STRICT_ALIGN
184 #define MASK_STRICT_ALIGN 0
187 /* Initialize the GCC target structure. */
188 #undef TARGET_ATTRIBUTE_TABLE
189 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
191 #undef TARGET_ASM_FUNCTION_PROLOGUE
192 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
193 #undef TARGET_ASM_FUNCTION_EPILOGUE
194 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
197 #undef TARGET_SECTION_TYPE_FLAGS
198 #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags
201 #undef TARGET_SCHED_ISSUE_RATE
202 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
203 #undef TARGET_SCHED_ADJUST_COST
204 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
205 #undef TARGET_SCHED_ADJUST_PRIORITY
206 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
208 struct gcc_target targetm = TARGET_INITIALIZER;
210 /* Override command line options. Mostly we process the processor
211 type and sometimes adjust other TARGET_ options. */
214 rs6000_override_options (default_cpu)
215 const char *default_cpu;
218 struct rs6000_cpu_select *ptr;
220 /* Simplify the entries below by making a mask for any POWER
221 variant and any PowerPC variant. */
223 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
224 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
225 | MASK_PPC_GFXOPT | MASK_POWERPC64)
226 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
230 const char *const name; /* Canonical processor name. */
231 const enum processor_type processor; /* Processor type enum value. */
232 const int target_enable; /* Target flags to enable. */
233 const int target_disable; /* Target flags to disable. */
234 } const processor_target_table[]
235 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
236 POWER_MASKS | POWERPC_MASKS},
237 {"power", PROCESSOR_POWER,
238 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
239 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
240 {"power2", PROCESSOR_POWER,
241 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
242 POWERPC_MASKS | MASK_NEW_MNEMONICS},
243 {"power3", PROCESSOR_PPC630,
244 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
245 POWER_MASKS | MASK_PPC_GPOPT},
246 {"powerpc", PROCESSOR_POWERPC,
247 MASK_POWERPC | MASK_NEW_MNEMONICS,
248 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
249 {"powerpc64", PROCESSOR_POWERPC64,
250 MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
251 POWER_MASKS | POWERPC_OPT_MASKS},
252 {"rios", PROCESSOR_RIOS1,
253 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
254 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
255 {"rios1", PROCESSOR_RIOS1,
256 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
257 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
258 {"rsc", PROCESSOR_PPC601,
259 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
260 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
261 {"rsc1", PROCESSOR_PPC601,
262 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
263 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
264 {"rios2", PROCESSOR_RIOS2,
265 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
266 POWERPC_MASKS | MASK_NEW_MNEMONICS},
267 {"rs64a", PROCESSOR_RS64A,
268 MASK_POWERPC | MASK_NEW_MNEMONICS,
269 POWER_MASKS | POWERPC_OPT_MASKS},
270 {"401", PROCESSOR_PPC403,
271 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
272 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
273 {"403", PROCESSOR_PPC403,
274 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
275 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
276 {"505", PROCESSOR_MPCCORE,
277 MASK_POWERPC | MASK_NEW_MNEMONICS,
278 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
279 {"601", PROCESSOR_PPC601,
280 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
281 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
282 {"602", PROCESSOR_PPC603,
283 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
284 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
285 {"603", PROCESSOR_PPC603,
286 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
287 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
288 {"603e", PROCESSOR_PPC603,
289 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
290 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
291 {"ec603e", PROCESSOR_PPC603,
292 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
293 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
294 {"604", PROCESSOR_PPC604,
295 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
296 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
297 {"604e", PROCESSOR_PPC604e,
298 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
299 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
300 {"620", PROCESSOR_PPC620,
301 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
302 POWER_MASKS | MASK_PPC_GPOPT},
303 {"630", PROCESSOR_PPC630,
304 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
305 POWER_MASKS | MASK_PPC_GPOPT},
306 {"740", PROCESSOR_PPC750,
307 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
308 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
309 {"750", PROCESSOR_PPC750,
310 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
311 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
312 {"7400", PROCESSOR_PPC7400,
313 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
314 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
315 {"7450", PROCESSOR_PPC7450,
316 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
317 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
318 {"801", PROCESSOR_MPCCORE,
319 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
320 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
321 {"821", PROCESSOR_MPCCORE,
322 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
323 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
324 {"823", PROCESSOR_MPCCORE,
325 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
326 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
327 {"860", PROCESSOR_MPCCORE,
328 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
329 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
331 size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
333 /* Save current -mmultiple/-mno-multiple status. */
334 int multiple = TARGET_MULTIPLE;
335 /* Save current -mstring/-mno-string status. */
336 int string = TARGET_STRING;
338 profile_block_flag = 0;
340 /* Identify the processor type. */
341 rs6000_select[0].string = default_cpu;
342 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
344 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
346 ptr = &rs6000_select[i];
347 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
349 for (j = 0; j < ptt_size; j++)
350 if (! strcmp (ptr->string, processor_target_table[j].name))
353 rs6000_cpu = processor_target_table[j].processor;
357 target_flags |= processor_target_table[j].target_enable;
358 target_flags &= ~processor_target_table[j].target_disable;
364 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
368 /* If we are optimizing big endian systems for space, use the store
369 multiple instructions. */
370 if (BYTES_BIG_ENDIAN && optimize_size)
371 target_flags |= MASK_MULTIPLE;
373 /* If -mmultiple or -mno-multiple was explicitly used, don't
374 override with the processor default */
375 if (TARGET_MULTIPLE_SET)
376 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
378 /* If -mstring or -mno-string was explicitly used, don't override
379 with the processor default. */
380 if (TARGET_STRING_SET)
381 target_flags = (target_flags & ~MASK_STRING) | string;
383 /* Don't allow -mmultiple or -mstring on little endian systems
384 unless the cpu is a 750, because the hardware doesn't support the
385 instructions used in little endian mode, and causes an alignment
386 trap. The 750 does not cause an alignment trap (except when the
387 target is unaligned). */
389 if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
393 target_flags &= ~MASK_MULTIPLE;
394 if (TARGET_MULTIPLE_SET)
395 warning ("-mmultiple is not supported on little endian systems");
400 target_flags &= ~MASK_STRING;
401 if (TARGET_STRING_SET)
402 warning ("-mstring is not supported on little endian systems");
406 if (flag_pic && DEFAULT_ABI == ABI_AIX)
408 warning ("-f%s ignored (all code is position independent)",
409 (flag_pic > 1) ? "PIC" : "pic");
413 #ifdef XCOFF_DEBUGGING_INFO
414 if (flag_function_sections && (write_symbols != NO_DEBUG)
415 && DEFAULT_ABI == ABI_AIX)
417 warning ("-ffunction-sections disabled on AIX when debugging");
418 flag_function_sections = 0;
421 if (flag_data_sections && (DEFAULT_ABI == ABI_AIX))
423 warning ("-fdata-sections not supported on AIX");
424 flag_data_sections = 0;
428 /* Set debug flags */
429 if (rs6000_debug_name)
431 if (! strcmp (rs6000_debug_name, "all"))
432 rs6000_debug_stack = rs6000_debug_arg = 1;
433 else if (! strcmp (rs6000_debug_name, "stack"))
434 rs6000_debug_stack = 1;
435 else if (! strcmp (rs6000_debug_name, "arg"))
436 rs6000_debug_arg = 1;
438 error ("Unknown -mdebug-%s switch", rs6000_debug_name);
441 #ifdef TARGET_REGNAMES
442 /* If the user desires alternate register names, copy in the
443 alternate names now. */
445 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
448 #ifdef SUBTARGET_OVERRIDE_OPTIONS
449 SUBTARGET_OVERRIDE_OPTIONS;
452 /* Register global variables with the garbage collector. */
453 rs6000_add_gc_roots ();
455 /* Allocate an alias set for register saves & restores from stack. */
456 rs6000_sr_alias_set = new_alias_set ();
459 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
461 /* Arrange to save and restore machine status around nested functions. */
462 init_machine_status = rs6000_init_machine_status;
463 free_machine_status = rs6000_free_machine_status;
467 optimization_options (level, size)
468 int level ATTRIBUTE_UNUSED;
469 int size ATTRIBUTE_UNUSED;
473 /* Do anything needed at the start of the asm file. */
476 rs6000_file_start (file, default_cpu)
478 const char *default_cpu;
482 const char *start = buffer;
483 struct rs6000_cpu_select *ptr;
485 if (flag_verbose_asm)
487 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
488 rs6000_select[0].string = default_cpu;
490 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
492 ptr = &rs6000_select[i];
493 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
495 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
501 switch (rs6000_sdata)
503 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
504 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
505 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
506 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
509 if (rs6000_sdata && g_switch_value)
511 fprintf (file, "%s -G %d", start, g_switch_value);
522 /* Create a CONST_DOUBLE from a string. */
525 rs6000_float_const (string, mode)
527 enum machine_mode mode;
529 REAL_VALUE_TYPE value;
530 value = REAL_VALUE_ATOF (string, mode);
531 return immed_real_const_1 (value, mode);
534 /* Return non-zero if this function is known to have a null epilogue. */
539 if (reload_completed)
541 rs6000_stack_t *info = rs6000_stack_info ();
543 if (info->first_gp_reg_save == 32
544 && info->first_fp_reg_save == 64
554 /* Returns 1 always. */
557 any_operand (op, mode)
558 rtx op ATTRIBUTE_UNUSED;
559 enum machine_mode mode ATTRIBUTE_UNUSED;
564 /* Returns 1 if op is the count register. */
566 count_register_operand (op, mode)
568 enum machine_mode mode ATTRIBUTE_UNUSED;
570 if (GET_CODE (op) != REG)
573 if (REGNO (op) == COUNT_REGISTER_REGNUM)
576 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
583 xer_operand (op, mode)
585 enum machine_mode mode ATTRIBUTE_UNUSED;
587 if (GET_CODE (op) != REG)
590 if (XER_REGNO_P (REGNO (op)))
596 /* Return 1 if OP is a constant that can fit in a D field. */
599 short_cint_operand (op, mode)
601 enum machine_mode mode ATTRIBUTE_UNUSED;
603 return (GET_CODE (op) == CONST_INT
604 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
607 /* Similar for a unsigned D field. */
610 u_short_cint_operand (op, mode)
612 enum machine_mode mode ATTRIBUTE_UNUSED;
614 return (GET_CODE (op) == CONST_INT
615 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'));
618 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
621 non_short_cint_operand (op, mode)
623 enum machine_mode mode ATTRIBUTE_UNUSED;
625 return (GET_CODE (op) == CONST_INT
626 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
629 /* Returns 1 if OP is a CONST_INT that is a positive value
630 and an exact power of 2. */
633 exact_log2_cint_operand (op, mode)
635 enum machine_mode mode ATTRIBUTE_UNUSED;
637 return (GET_CODE (op) == CONST_INT
639 && exact_log2 (INTVAL (op)) >= 0);
642 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
646 gpc_reg_operand (op, mode)
648 enum machine_mode mode;
650 return (register_operand (op, mode)
651 && (GET_CODE (op) != REG
652 || (REGNO (op) >= ARG_POINTER_REGNUM
653 && !XER_REGNO_P (REGNO (op)))
654 || REGNO (op) < MQ_REGNO));
657 /* Returns 1 if OP is either a pseudo-register or a register denoting a
661 cc_reg_operand (op, mode)
663 enum machine_mode mode;
665 return (register_operand (op, mode)
666 && (GET_CODE (op) != REG
667 || REGNO (op) >= FIRST_PSEUDO_REGISTER
668 || CR_REGNO_P (REGNO (op))));
671 /* Returns 1 if OP is either a pseudo-register or a register denoting a
672 CR field that isn't CR0. */
675 cc_reg_not_cr0_operand (op, mode)
677 enum machine_mode mode;
679 return (register_operand (op, mode)
680 && (GET_CODE (op) != REG
681 || REGNO (op) >= FIRST_PSEUDO_REGISTER
682 || CR_REGNO_NOT_CR0_P (REGNO (op))));
685 /* Returns 1 if OP is either a constant integer valid for a D-field or
686 a non-special register. If a register, it must be in the proper
687 mode unless MODE is VOIDmode. */
690 reg_or_short_operand (op, mode)
692 enum machine_mode mode;
694 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
697 /* Similar, except check if the negation of the constant would be
698 valid for a D-field. */
701 reg_or_neg_short_operand (op, mode)
703 enum machine_mode mode;
705 if (GET_CODE (op) == CONST_INT)
706 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
708 return gpc_reg_operand (op, mode);
711 /* Return 1 if the operand is either a register or an integer whose
712 high-order 16 bits are zero. */
715 reg_or_u_short_operand (op, mode)
717 enum machine_mode mode;
719 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
722 /* Return 1 is the operand is either a non-special register or ANY
726 reg_or_cint_operand (op, mode)
728 enum machine_mode mode;
730 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
733 /* Return 1 is the operand is either a non-special register or ANY
734 32-bit signed constant integer. */
737 reg_or_arith_cint_operand (op, mode)
739 enum machine_mode mode;
741 return (gpc_reg_operand (op, mode)
742 || (GET_CODE (op) == CONST_INT
743 #if HOST_BITS_PER_WIDE_INT != 32
744 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
745 < (unsigned HOST_WIDE_INT) 0x100000000ll)
750 /* Return 1 is the operand is either a non-special register or a 32-bit
751 signed constant integer valid for 64-bit addition. */
754 reg_or_add_cint64_operand (op, mode)
756 enum machine_mode mode;
758 return (gpc_reg_operand (op, mode)
759 || (GET_CODE (op) == CONST_INT
760 && INTVAL (op) < 0x7fff8000
761 #if HOST_BITS_PER_WIDE_INT != 32
762 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
768 /* Return 1 is the operand is either a non-special register or a 32-bit
769 signed constant integer valid for 64-bit subtraction. */
772 reg_or_sub_cint64_operand (op, mode)
774 enum machine_mode mode;
776 return (gpc_reg_operand (op, mode)
777 || (GET_CODE (op) == CONST_INT
778 && (- INTVAL (op)) < 0x7fff8000
779 #if HOST_BITS_PER_WIDE_INT != 32
780 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
786 /* Return 1 is the operand is either a non-special register or ANY
787 32-bit unsigned constant integer. */
790 reg_or_logical_cint_operand (op, mode)
792 enum machine_mode mode;
794 if (GET_CODE (op) == CONST_INT)
796 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
798 if (GET_MODE_BITSIZE (mode) <= 32)
805 return ((INTVAL (op) & GET_MODE_MASK (mode)
806 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
808 else if (GET_CODE (op) == CONST_DOUBLE)
810 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
814 return CONST_DOUBLE_HIGH (op) == 0;
817 return gpc_reg_operand (op, mode);
820 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
823 got_operand (op, mode)
825 enum machine_mode mode ATTRIBUTE_UNUSED;
827 return (GET_CODE (op) == SYMBOL_REF
828 || GET_CODE (op) == CONST
829 || GET_CODE (op) == LABEL_REF);
832 /* Return 1 if the operand is a simple references that can be loaded via
833 the GOT (labels involving addition aren't allowed). */
836 got_no_const_operand (op, mode)
838 enum machine_mode mode ATTRIBUTE_UNUSED;
840 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
843 /* Return the number of instructions it takes to form a constant in an
847 num_insns_constant_wide (value)
850 /* signed constant loadable with {cal|addi} */
851 if (CONST_OK_FOR_LETTER_P (value, 'I'))
854 /* constant loadable with {cau|addis} */
855 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
858 #if HOST_BITS_PER_WIDE_INT == 64
859 else if (TARGET_POWERPC64)
861 HOST_WIDE_INT low = value & 0xffffffff;
862 HOST_WIDE_INT high = value >> 32;
864 low = (low ^ 0x80000000) - 0x80000000; /* sign extend */
866 if (high == 0 && (low & 0x80000000) == 0)
869 else if (high == -1 && (low & 0x80000000) != 0)
873 return num_insns_constant_wide (high) + 1;
876 return (num_insns_constant_wide (high)
877 + num_insns_constant_wide (low) + 1);
886 num_insns_constant (op, mode)
888 enum machine_mode mode;
890 if (GET_CODE (op) == CONST_INT)
892 #if HOST_BITS_PER_WIDE_INT == 64
893 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
894 && mask64_operand (op, mode))
898 return num_insns_constant_wide (INTVAL (op));
901 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
906 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
907 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
908 return num_insns_constant_wide ((HOST_WIDE_INT)l);
911 else if (GET_CODE (op) == CONST_DOUBLE)
917 int endian = (WORDS_BIG_ENDIAN == 0);
919 if (mode == VOIDmode || mode == DImode)
921 high = CONST_DOUBLE_HIGH (op);
922 low = CONST_DOUBLE_LOW (op);
926 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
927 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
933 return (num_insns_constant_wide (low)
934 + num_insns_constant_wide (high));
938 if (high == 0 && (low & 0x80000000) == 0)
939 return num_insns_constant_wide (low);
941 else if (high == -1 && (low & 0x80000000) != 0)
942 return num_insns_constant_wide (low);
944 else if (mask64_operand (op, mode))
948 return num_insns_constant_wide (high) + 1;
951 return (num_insns_constant_wide (high)
952 + num_insns_constant_wide (low) + 1);
960 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
961 register with one instruction per word. We only do this if we can
962 safely read CONST_DOUBLE_{LOW,HIGH}. */
965 easy_fp_constant (op, mode)
967 enum machine_mode mode;
969 if (GET_CODE (op) != CONST_DOUBLE
970 || GET_MODE (op) != mode
971 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
974 /* Consider all constants with -msoft-float to be easy. */
975 if (TARGET_SOFT_FLOAT && mode != DImode)
978 /* If we are using V.4 style PIC, consider all constants to be hard. */
979 if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
982 #ifdef TARGET_RELOCATABLE
983 /* Similarly if we are using -mrelocatable, consider all constants
985 if (TARGET_RELOCATABLE)
994 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
995 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
997 return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1
998 && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1);
1001 else if (mode == SFmode)
1006 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1007 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1009 return num_insns_constant_wide (l) == 1;
1012 else if (mode == DImode)
1013 return ((TARGET_POWERPC64
1014 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1015 || (num_insns_constant (op, DImode) <= 2));
1017 else if (mode == SImode)
1023 /* Return 1 if the operand is 0.0. */
1025 zero_fp_constant (op, mode)
1027 enum machine_mode mode;
1029 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1032 /* Return 1 if the operand is in volatile memory. Note that during
1033 the RTL generation phase, memory_operand does not return TRUE for
1034 volatile memory references. So this function allows us to
1035 recognize volatile references where its safe. */
1038 volatile_mem_operand (op, mode)
1040 enum machine_mode mode;
1042 if (GET_CODE (op) != MEM)
1045 if (!MEM_VOLATILE_P (op))
1048 if (mode != GET_MODE (op))
1051 if (reload_completed)
1052 return memory_operand (op, mode);
1054 if (reload_in_progress)
1055 return strict_memory_address_p (mode, XEXP (op, 0));
1057 return memory_address_p (mode, XEXP (op, 0));
1060 /* Return 1 if the operand is an offsettable memory operand. */
1063 offsettable_mem_operand (op, mode)
1065 enum machine_mode mode;
1067 return ((GET_CODE (op) == MEM)
1068 && offsettable_address_p (reload_completed || reload_in_progress,
1069 mode, XEXP (op, 0)));
1072 /* Return 1 if the operand is either an easy FP constant (see above) or
1076 mem_or_easy_const_operand (op, mode)
1078 enum machine_mode mode;
1080 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1083 /* Return 1 if the operand is either a non-special register or an item
1084 that can be used as the operand of a `mode' add insn. */
1087 add_operand (op, mode)
1089 enum machine_mode mode;
1091 if (GET_CODE (op) == CONST_INT)
1092 return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I')
1093 || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'));
1095 return gpc_reg_operand (op, mode);
1098 /* Return 1 if OP is a constant but not a valid add_operand. */
1101 non_add_cint_operand (op, mode)
1103 enum machine_mode mode ATTRIBUTE_UNUSED;
1105 return (GET_CODE (op) == CONST_INT
1106 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
1107 && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1110 /* Return 1 if the operand is a non-special register or a constant that
1111 can be used as the operand of an OR or XOR insn on the RS/6000. */
1114 logical_operand (op, mode)
1116 enum machine_mode mode;
1118 HOST_WIDE_INT opl, oph;
1120 if (gpc_reg_operand (op, mode))
1123 if (GET_CODE (op) == CONST_INT)
1125 opl = INTVAL (op) & GET_MODE_MASK (mode);
1127 #if HOST_BITS_PER_WIDE_INT <= 32
1128 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1132 else if (GET_CODE (op) == CONST_DOUBLE)
1134 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1137 opl = CONST_DOUBLE_LOW (op);
1138 oph = CONST_DOUBLE_HIGH (op);
1145 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1146 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1149 /* Return 1 if C is a constant that is not a logical operand (as
1150 above), but could be split into one. */
1153 non_logical_cint_operand (op, mode)
1155 enum machine_mode mode;
1157 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1158 && ! logical_operand (op, mode)
1159 && reg_or_logical_cint_operand (op, mode));
1162 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1163 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1164 Reject all ones and all zeros, since these should have been optimized
1165 away and confuse the making of MB and ME. */
1168 mask_operand (op, mode)
1170 enum machine_mode mode ATTRIBUTE_UNUSED;
1172 HOST_WIDE_INT c, lsb;
1174 if (GET_CODE (op) != CONST_INT)
1179 /* We don't change the number of transitions by inverting,
1180 so make sure we start with the LS bit zero. */
1184 /* Reject all zeros or all ones. */
1188 /* Find the first transition. */
1191 /* Invert to look for a second transition. */
1194 /* Erase first transition. */
1197 /* Find the second transition (if any). */
1200 /* Match if all the bits above are 1's (or c is zero). */
1204 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1205 It is if there are no more than one 1->0 or 0->1 transitions.
1206 Reject all ones and all zeros, since these should have been optimized
1207 away and confuse the making of MB and ME. */
1210 mask64_operand (op, mode)
1212 enum machine_mode mode;
1214 if (GET_CODE (op) == CONST_INT)
1216 HOST_WIDE_INT c, lsb;
1218 /* We don't change the number of transitions by inverting,
1219 so make sure we start with the LS bit zero. */
1224 /* Reject all zeros or all ones. */
1228 /* Find the transition, and check that all bits above are 1's. */
1232 else if (GET_CODE (op) == CONST_DOUBLE
1233 && (mode == VOIDmode || mode == DImode))
1235 HOST_WIDE_INT low, high, lsb;
1237 if (HOST_BITS_PER_WIDE_INT < 64)
1238 high = CONST_DOUBLE_HIGH (op);
1240 low = CONST_DOUBLE_LOW (op);
1243 if (HOST_BITS_PER_WIDE_INT < 64)
1250 if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)
1254 return high == -lsb;
1258 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
1264 /* Return 1 if the operand is either a non-special register or a constant
1265 that can be used as the operand of a PowerPC64 logical AND insn. */
1268 and64_operand (op, mode)
1270 enum machine_mode mode;
1272 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1273 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
1275 return (logical_operand (op, mode) || mask64_operand (op, mode));
1278 /* Return 1 if the operand is either a non-special register or a
1279 constant that can be used as the operand of an RS/6000 logical AND insn. */
1282 and_operand (op, mode)
1284 enum machine_mode mode;
1286 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1287 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
1289 return (logical_operand (op, mode) || mask_operand (op, mode));
1292 /* Return 1 if the operand is a general register or memory operand. */
1295 reg_or_mem_operand (op, mode)
1297 enum machine_mode mode;
1299 return (gpc_reg_operand (op, mode)
1300 || memory_operand (op, mode)
1301 || volatile_mem_operand (op, mode));
1304 /* Return 1 if the operand is a general register or memory operand without
1305 pre_inc or pre_dec which produces invalid form of PowerPC lwa
1309 lwa_operand (op, mode)
1311 enum machine_mode mode;
1315 if (reload_completed && GET_CODE (inner) == SUBREG)
1316 inner = SUBREG_REG (inner);
1318 return gpc_reg_operand (inner, mode)
1319 || (memory_operand (inner, mode)
1320 && GET_CODE (XEXP (inner, 0)) != PRE_INC
1321 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
1322 && (GET_CODE (XEXP (inner, 0)) != PLUS
1323 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
1324 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
1327 /* Return 1 if the operand, used inside a MEM, is a valid first argument
1328 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
1332 call_operand (op, mode)
1334 enum machine_mode mode;
1336 if (mode != VOIDmode && GET_MODE (op) != mode)
1339 return (GET_CODE (op) == SYMBOL_REF
1340 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
1343 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
1344 this file and the function is not weakly defined. */
1347 current_file_function_operand (op, mode)
1349 enum machine_mode mode ATTRIBUTE_UNUSED;
1351 return (GET_CODE (op) == SYMBOL_REF
1352 && (SYMBOL_REF_FLAG (op)
1353 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1354 && ! DECL_WEAK (current_function_decl))));
1357 /* Return 1 if this operand is a valid input for a move insn. */
1360 input_operand (op, mode)
1362 enum machine_mode mode;
1364 /* Memory is always valid. */
1365 if (memory_operand (op, mode))
1368 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1369 if (GET_CODE (op) == CONSTANT_P_RTX)
1372 /* For floating-point, easy constants are valid. */
1373 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1375 && easy_fp_constant (op, mode))
1378 /* Allow any integer constant. */
1379 if (GET_MODE_CLASS (mode) == MODE_INT
1380 && (GET_CODE (op) == CONST_INT
1381 || GET_CODE (op) == CONST_DOUBLE))
1384 /* For floating-point or multi-word mode, the only remaining valid type
1386 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1387 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1388 return register_operand (op, mode);
1390 /* The only cases left are integral modes one word or smaller (we
1391 do not get called for MODE_CC values). These can be in any
1393 if (register_operand (op, mode))
1396 /* A SYMBOL_REF referring to the TOC is valid. */
1397 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
1400 /* A constant pool expression (relative to the TOC) is valid */
1401 if (TOC_RELATIVE_EXPR_P (op))
1404 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1406 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1407 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1408 && small_data_operand (op, Pmode))
1414 /* Return 1 for an operand in small memory on V.4/eabi. */
1417 small_data_operand (op, mode)
1418 rtx op ATTRIBUTE_UNUSED;
1419 enum machine_mode mode ATTRIBUTE_UNUSED;
1424 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
1427 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
1430 if (GET_CODE (op) == SYMBOL_REF)
1433 else if (GET_CODE (op) != CONST
1434 || GET_CODE (XEXP (op, 0)) != PLUS
1435 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
1436 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
1441 rtx sum = XEXP (op, 0);
1442 HOST_WIDE_INT summand;
1444 /* We have to be careful here, because it is the referenced address
1445 that must be 32k from _SDA_BASE_, not just the symbol. */
1446 summand = INTVAL (XEXP (sum, 1));
1447 if (summand < 0 || summand > g_switch_value)
1450 sym_ref = XEXP (sum, 0);
1453 if (*XSTR (sym_ref, 0) != '@')
1464 constant_pool_expr_1 (op, have_sym, have_toc)
1469 switch (GET_CODE(op))
1472 if (CONSTANT_POOL_ADDRESS_P (op))
1474 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
1482 else if (! strcmp (XSTR (op, 0), toc_label_name))
1491 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) &&
1492 constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc);
1494 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
1503 constant_pool_expr_p (op)
1508 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
1512 toc_relative_expr_p (op)
1517 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
1520 /* Try machine-dependent ways of modifying an illegitimate address
1521 to be legitimate. If we find one, return the new, valid address.
1522 This is used from only one place: `memory_address' in explow.c.
1524 OLDX is the address as it was before break_out_memory_refs was
1525 called. In some cases it is useful to look at this to decide what
1528 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
1530 It is always safe for this function to do nothing. It exists to
1531 recognize opportunities to optimize the output.
1533 On RS/6000, first check for the sum of a register with a constant
1534 integer that is out of range. If so, generate code to add the
1535 constant with the low-order 16 bits masked to the register and force
1536 this result into another register (this can be done with `cau').
1537 Then generate an address of REG+(CONST&0xffff), allowing for the
1538 possibility of bit 16 being a one.
1540 Then check for the sum of a register and something not constant, try to
1541 load the other things into a register and return the sum. */
1543 rs6000_legitimize_address (x, oldx, mode)
1545 rtx oldx ATTRIBUTE_UNUSED;
1546 enum machine_mode mode;
1548 if (GET_CODE (x) == PLUS
1549 && GET_CODE (XEXP (x, 0)) == REG
1550 && GET_CODE (XEXP (x, 1)) == CONST_INT
1551 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
1553 HOST_WIDE_INT high_int, low_int;
1555 high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff);
1556 low_int = INTVAL (XEXP (x, 1)) & 0xffff;
1557 if (low_int & 0x8000)
1558 high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;
1559 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
1560 GEN_INT (high_int)), 0);
1561 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
1563 else if (GET_CODE (x) == PLUS
1564 && GET_CODE (XEXP (x, 0)) == REG
1565 && GET_CODE (XEXP (x, 1)) != CONST_INT
1566 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
1567 && (TARGET_POWERPC64 || mode != DImode)
1570 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
1571 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
1573 else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic
1574 && GET_CODE (x) != CONST_INT
1575 && GET_CODE (x) != CONST_DOUBLE
1577 && (TARGET_HARD_FLOAT || mode != DFmode)
1581 rtx reg = gen_reg_rtx (Pmode);
1582 emit_insn (gen_elf_high (reg, (x)));
1583 return gen_rtx_LO_SUM (Pmode, reg, (x));
1585 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
1587 && GET_CODE (x) != CONST_INT
1588 && GET_CODE (x) != CONST_DOUBLE
1590 && (TARGET_HARD_FLOAT || mode != DFmode)
1594 rtx reg = gen_reg_rtx (Pmode);
1595 emit_insn (gen_macho_high (reg, (x)));
1596 return gen_rtx_LO_SUM (Pmode, reg, (x));
1599 && CONSTANT_POOL_EXPR_P (x)
1600 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
1602 return create_TOC_reference (x);
1608 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1609 that is a valid memory address for an instruction.
1610 The MODE argument is the machine mode for the MEM expression
1611 that wants to use this address.
1613 On the RS/6000, there are four valid address: a SYMBOL_REF that
1614 refers to a constant pool entry of an address (or the sum of it
1615 plus a constant), a short (16-bit signed) constant plus a register,
1616 the sum of two registers, or a register indirect, possibly with an
1617 auto-increment. For DFmode and DImode with an constant plus register,
1618 we must ensure that both words are addressable or PowerPC64 with offset
1621 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1622 32-bit DImode, TImode), indexed addressing cannot be used because
1623 adjacent memory cells are accessed by adding word-sized offsets
1624 during assembly output. */
1626 rs6000_legitimate_address (mode, x, reg_ok_strict)
1627 enum machine_mode mode;
1631 if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict))
1633 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
1635 && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict))
1637 if (LEGITIMATE_SMALL_DATA_P (mode, x))
1639 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
1641 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
1643 && GET_CODE (x) == PLUS
1644 && GET_CODE (XEXP (x, 0)) == REG
1645 && XEXP (x, 0) == virtual_stack_vars_rtx
1646 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1648 if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict))
1651 && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode)
1652 && (TARGET_POWERPC64 || mode != DImode)
1653 && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict))
1655 if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict))
1660 /* Try to output insns to set TARGET equal to the constant C if it can
1661 be done in less than N insns. Do all computations in MODE.
1662 Returns the place where the output has been placed if it can be
1663 done and the insns have been emitted. If it would take more than N
1664 insns, zero is returned and no insns and emitted. */
1667 rs6000_emit_set_const (dest, mode, source, n)
1669 enum machine_mode mode;
1670 int n ATTRIBUTE_UNUSED;
1672 HOST_WIDE_INT c0, c1;
1674 if (mode == QImode || mode == HImode || mode == SImode)
1677 dest = gen_reg_rtx (mode);
1678 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
1682 if (GET_CODE (source) == CONST_INT)
1684 c0 = INTVAL (source);
1687 else if (GET_CODE (source) == CONST_DOUBLE)
1689 #if HOST_BITS_PER_WIDE_INT >= 64
1690 c0 = CONST_DOUBLE_LOW (source);
1693 c0 = CONST_DOUBLE_LOW (source);
1694 c1 = CONST_DOUBLE_HIGH (source);
1700 return rs6000_emit_set_long_const (dest, c0, c1);
1703 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
1704 fall back to a straight forward decomposition. We do this to avoid
1705 exponential run times encountered when looking for longer sequences
1706 with rs6000_emit_set_const. */
1708 rs6000_emit_set_long_const (dest, c1, c2)
1710 HOST_WIDE_INT c1, c2;
1712 if (!TARGET_POWERPC64)
1714 rtx operand1, operand2;
1716 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
1718 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
1720 emit_move_insn (operand1, GEN_INT (c1));
1721 emit_move_insn (operand2, GEN_INT (c2));
1725 HOST_WIDE_INT d1, d2, d3, d4;
1727 /* Decompose the entire word */
1728 #if HOST_BITS_PER_WIDE_INT >= 64
1729 if (c2 != -(c1 < 0))
1731 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1733 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1734 c1 = (c1 - d2) >> 32;
1735 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1737 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1741 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1743 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1747 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
1749 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1754 /* Construct the high word */
1757 emit_move_insn (dest, GEN_INT (d4));
1759 emit_move_insn (dest,
1760 gen_rtx_PLUS (DImode, dest, GEN_INT (d3)));
1763 emit_move_insn (dest, GEN_INT (d3));
1765 /* Shift it into place */
1766 if (d3 != 0 || d4 != 0)
1767 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
1769 /* Add in the low bits. */
1771 emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2)));
1773 emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1)));
1779 /* Emit a move from SOURCE to DEST in mode MODE. */
1781 rs6000_emit_move (dest, source, mode)
1784 enum machine_mode mode;
1788 operands[1] = source;
1790 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
1791 if (GET_CODE (operands[1]) == CONST_DOUBLE
1792 && ! FLOAT_MODE_P (mode)
1793 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1795 /* FIXME. This should never happen. */
1796 /* Since it seems that it does, do the safe thing and convert
1799 GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode));
1801 if (GET_CODE (operands[1]) == CONST_DOUBLE
1802 && ! FLOAT_MODE_P (mode)
1803 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
1804 && CONST_DOUBLE_LOW (operands[1]) >= 0)
1805 || (CONST_DOUBLE_HIGH (operands[1]) == -1
1806 && CONST_DOUBLE_LOW (operands[1]) < 0)))
1809 if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
1810 operands[1] = force_reg (mode, operands[1]);
1812 if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT
1813 && GET_CODE (operands[0]) == MEM)
1817 if (reload_in_progress || reload_completed)
1818 regnum = true_regnum (operands[1]);
1819 else if (GET_CODE (operands[1]) == REG)
1820 regnum = REGNO (operands[1]);
1824 /* If operands[1] is a register, on POWER it may have
1825 double-precision data in it, so truncate it to single
1827 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
1830 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
1831 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
1832 operands[1] = newreg;
1836 /* Handle the case where reload calls us with an invalid address;
1837 and the case of CONSTANT_P_RTX. */
1838 if (! general_operand (operands[1], mode)
1839 || ! nonimmediate_operand (operands[0], mode)
1840 || GET_CODE (operands[1]) == CONSTANT_P_RTX)
1842 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1846 /* FIXME: In the long term, this switch statement should go away
1847 and be replaced by a sequence of tests based on things like
1853 if (CONSTANT_P (operands[1])
1854 && GET_CODE (operands[1]) != CONST_INT)
1855 operands[1] = force_const_mem (mode, operands[1]);
1860 if (CONSTANT_P (operands[1])
1861 && ! easy_fp_constant (operands[1], mode))
1862 operands[1] = force_const_mem (mode, operands[1]);
1867 /* Use default pattern for address of ELF small data */
1870 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1871 && (GET_CODE (operands[1]) == SYMBOL_REF
1872 || GET_CODE (operands[1]) == CONST)
1873 && small_data_operand (operands[1], mode))
1875 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1879 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1880 && mode == Pmode && mode == SImode
1881 && flag_pic == 1 && got_operand (operands[1], mode))
1883 emit_insn (gen_movsi_got (operands[0], operands[1]));
1887 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
1888 && TARGET_NO_TOC && ! flag_pic
1890 && CONSTANT_P (operands[1])
1891 && GET_CODE (operands[1]) != HIGH
1892 && GET_CODE (operands[1]) != CONST_INT)
1894 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
1896 /* If this is a function address on -mcall-aixdesc,
1897 convert it to the address of the descriptor. */
1898 if (DEFAULT_ABI == ABI_AIX
1899 && GET_CODE (operands[1]) == SYMBOL_REF
1900 && XSTR (operands[1], 0)[0] == '.')
1902 const char *name = XSTR (operands[1], 0);
1904 while (*name == '.')
1906 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
1907 CONSTANT_POOL_ADDRESS_P (new_ref)
1908 = CONSTANT_POOL_ADDRESS_P (operands[1]);
1909 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
1910 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
1911 operands[1] = new_ref;
1914 if (DEFAULT_ABI == ABI_DARWIN)
1916 emit_insn (gen_macho_high (target, operands[1]));
1917 emit_insn (gen_macho_low (operands[0], target, operands[1]));
1921 emit_insn (gen_elf_high (target, operands[1]));
1922 emit_insn (gen_elf_low (operands[0], target, operands[1]));
1926 /* If this is a SYMBOL_REF that refers to a constant pool entry,
1927 and we have put it in the TOC, we just need to make a TOC-relative
1930 && GET_CODE (operands[1]) == SYMBOL_REF
1931 && CONSTANT_POOL_EXPR_P (operands[1])
1932 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
1933 get_pool_mode (operands[1])))
1935 operands[1] = create_TOC_reference (operands[1]);
1937 else if (mode == Pmode
1938 && CONSTANT_P (operands[1])
1939 && ((GET_CODE (operands[1]) != CONST_INT
1940 && ! easy_fp_constant (operands[1], mode))
1941 || (GET_CODE (operands[1]) == CONST_INT
1942 && num_insns_constant (operands[1], mode) > 2)
1943 || (GET_CODE (operands[0]) == REG
1944 && FP_REGNO_P (REGNO (operands[0]))))
1945 && GET_CODE (operands[1]) != HIGH
1946 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])
1947 && ! TOC_RELATIVE_EXPR_P (operands[1]))
1949 /* Emit a USE operation so that the constant isn't deleted if
1950 expensive optimizations are turned on because nobody
1951 references it. This should only be done for operands that
1952 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
1953 This should not be done for operands that contain LABEL_REFs.
1954 For now, we just handle the obvious case. */
1955 if (GET_CODE (operands[1]) != LABEL_REF)
1956 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
1958 /* Darwin uses a special PIC legitimizer. */
1959 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
1962 rtx temp_reg = ((reload_in_progress || reload_completed)
1963 ? operands[0] : NULL);
1966 rs6000_machopic_legitimize_pic_address (operands[1], mode,
1969 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1973 /* If we are to limit the number of things we put in the TOC and
1974 this is a symbol plus a constant we can add in one insn,
1975 just put the symbol in the TOC and add the constant. Don't do
1976 this if reload is in progress. */
1977 if (GET_CODE (operands[1]) == CONST
1978 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
1979 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1980 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
1981 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
1982 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
1983 && ! side_effects_p (operands[0]))
1986 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
1987 rtx other = XEXP (XEXP (operands[1], 0), 1);
1989 sym = force_reg (mode, sym);
1991 emit_insn (gen_addsi3 (operands[0], sym, other));
1993 emit_insn (gen_adddi3 (operands[0], sym, other));
1997 operands[1] = force_const_mem (mode, operands[1]);
2000 && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0))
2001 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
2002 get_pool_constant (XEXP (operands[1], 0)),
2003 get_pool_mode (XEXP (operands[1], 0))))
2006 = gen_rtx_MEM (mode,
2007 create_TOC_reference (XEXP (operands[1], 0)));
2008 set_mem_alias_set (operands[1], get_TOC_alias_set ());
2009 RTX_UNCHANGING_P (operands[1]) = 1;
2015 if (GET_CODE (operands[0]) == MEM
2016 && GET_CODE (XEXP (operands[0], 0)) != REG
2017 && ! reload_in_progress)
2019 = replace_equiv_address (operands[0],
2020 copy_addr_to_reg (XEXP (operands[0], 0)));
2022 if (GET_CODE (operands[1]) == MEM
2023 && GET_CODE (XEXP (operands[1], 0)) != REG
2024 && ! reload_in_progress)
2026 = replace_equiv_address (operands[1],
2027 copy_addr_to_reg (XEXP (operands[1], 0)));
2034 /* Above, we may have called force_const_mem which may have returned
2035 an invalid address. If we can, fix this up; otherwise, reload will
2036 have to deal with it. */
2037 if (GET_CODE (operands[1]) == MEM
2038 && ! memory_address_p (mode, XEXP (operands[1], 0))
2039 && ! reload_in_progress)
2040 operands[1] = adjust_address (operands[1], mode, 0);
2042 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2046 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2047 for a call to a function whose data type is FNTYPE.
2048 For a library call, FNTYPE is 0.
2050 For incoming args we set the number of arguments in the prototype large
2051 so we never return a PARALLEL. */
2054 init_cumulative_args (cum, fntype, libname, incoming)
2055 CUMULATIVE_ARGS *cum;
2057 rtx libname ATTRIBUTE_UNUSED;
2060 static CUMULATIVE_ARGS zero_cumulative;
2062 *cum = zero_cumulative;
2064 cum->fregno = FP_ARG_MIN_REG;
2065 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
2066 cum->call_cookie = CALL_NORMAL;
2067 cum->sysv_gregno = GP_ARG_MIN_REG;
2070 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
2072 else if (cum->prototype)
2073 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
2074 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
2075 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
2078 cum->nargs_prototype = 0;
2080 cum->orig_nargs = cum->nargs_prototype;
2082 /* Check for longcall's */
2083 if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
2084 cum->call_cookie = CALL_LONG;
2086 if (TARGET_DEBUG_ARG)
2088 fprintf (stderr, "\ninit_cumulative_args:");
2091 tree ret_type = TREE_TYPE (fntype);
2092 fprintf (stderr, " ret code = %s,",
2093 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2096 if (cum->call_cookie & CALL_LONG)
2097 fprintf (stderr, " longcall,");
2099 fprintf (stderr, " proto = %d, nargs = %d\n",
2100 cum->prototype, cum->nargs_prototype);
2104 /* If defined, a C expression which determines whether, and in which
2105 direction, to pad out an argument with extra space. The value
2106 should be of type `enum direction': either `upward' to pad above
2107 the argument, `downward' to pad below, or `none' to inhibit
2110 For the AIX ABI structs are always stored left shifted in their
2114 function_arg_padding (mode, type)
2115 enum machine_mode mode;
2118 if (type != 0 && AGGREGATE_TYPE_P (type))
2121 /* This is the default definition. */
2122 return (! BYTES_BIG_ENDIAN
2125 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2126 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
2127 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
2128 ? downward : upward));
2131 /* If defined, a C expression that gives the alignment boundary, in bits,
2132 of an argument with the specified mode and type. If it is not defined,
2133 PARM_BOUNDARY is used for all arguments.
2135 V.4 wants long longs to be double word aligned. */
2138 function_arg_boundary (mode, type)
2139 enum machine_mode mode;
2140 tree type ATTRIBUTE_UNUSED;
2142 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2143 && (mode == DImode || mode == DFmode))
2146 return PARM_BOUNDARY;
2149 /* Update the data in CUM to advance over an argument
2150 of mode MODE and data type TYPE.
2151 (TYPE is null for libcalls where that information may not be available.) */
2154 function_arg_advance (cum, mode, type, named)
2155 CUMULATIVE_ARGS *cum;
2156 enum machine_mode mode;
2160 cum->nargs_prototype--;
2162 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2164 if (TARGET_HARD_FLOAT
2165 && (mode == SFmode || mode == DFmode))
2167 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2172 cum->words += cum->words & 1;
2173 cum->words += RS6000_ARG_SIZE (mode, type);
2179 int gregno = cum->sysv_gregno;
2181 /* Aggregates and IEEE quad get passed by reference. */
2182 if ((type && AGGREGATE_TYPE_P (type))
2186 n_words = RS6000_ARG_SIZE (mode, type);
2188 /* Long long is put in odd registers. */
2189 if (n_words == 2 && (gregno & 1) == 0)
2192 /* Long long is not split between registers and stack. */
2193 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
2195 /* Long long is aligned on the stack. */
2197 cum->words += cum->words & 1;
2198 cum->words += n_words;
2201 /* Note: continuing to accumulate gregno past when we've started
2202 spilling to the stack indicates the fact that we've started
2203 spilling to the stack to expand_builtin_saveregs. */
2204 cum->sysv_gregno = gregno + n_words;
2207 if (TARGET_DEBUG_ARG)
2209 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2210 cum->words, cum->fregno);
2211 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
2212 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
2213 fprintf (stderr, "mode = %4s, named = %d\n",
2214 GET_MODE_NAME (mode), named);
2219 int align = (TARGET_32BIT && (cum->words & 1) != 0
2220 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2222 cum->words += align + RS6000_ARG_SIZE (mode, type);
2224 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
2227 if (TARGET_DEBUG_ARG)
2229 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
2230 cum->words, cum->fregno);
2231 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
2232 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
2233 fprintf (stderr, "named = %d, align = %d\n", named, align);
2238 /* Determine where to put an argument to a function.
2239 Value is zero to push the argument on the stack,
2240 or a hard register in which to store the argument.
2242 MODE is the argument's machine mode.
2243 TYPE is the data type of the argument (as a tree).
2244 This is null for libcalls where that information may
2246 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2247 the preceding args and about the function being called.
2248 NAMED is nonzero if this argument is a named parameter
2249 (otherwise it is an extra parameter matching an ellipsis).
2251 On RS/6000 the first eight words of non-FP are normally in registers
2252 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
2253 Under V.4, the first 8 FP args are in registers.
2255 If this is floating-point and no prototype is specified, we use
2256 both an FP and integer register (or possibly FP reg and stack). Library
2257 functions (when TYPE is zero) always have the proper types for args,
2258 so we can pass the FP value just in one register. emit_library_function
2259 doesn't support PARALLEL anyway. */
2262 function_arg (cum, mode, type, named)
2263 CUMULATIVE_ARGS *cum;
2264 enum machine_mode mode;
2266 int named ATTRIBUTE_UNUSED;
2268 enum rs6000_abi abi = DEFAULT_ABI;
2270 /* Return a marker to indicate whether CR1 needs to set or clear the
2271 bit that V.4 uses to say fp args were passed in registers.
2272 Assume that we don't need the marker for software floating point,
2273 or compiler generated library calls. */
2274 if (mode == VOIDmode)
2276 if ((abi == ABI_V4 || abi == ABI_SOLARIS)
2277 && TARGET_HARD_FLOAT
2278 && cum->nargs_prototype < 0
2279 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
2281 return GEN_INT (cum->call_cookie
2282 | ((cum->fregno == FP_ARG_MIN_REG)
2283 ? CALL_V4_SET_FP_ARGS
2284 : CALL_V4_CLEAR_FP_ARGS));
2287 return GEN_INT (cum->call_cookie);
2290 if (abi == ABI_V4 || abi == ABI_SOLARIS)
2292 if (TARGET_HARD_FLOAT
2293 && (mode == SFmode || mode == DFmode))
2295 if (cum->fregno <= FP_ARG_V4_MAX_REG)
2296 return gen_rtx_REG (mode, cum->fregno);
2303 int gregno = cum->sysv_gregno;
2305 /* Aggregates and IEEE quad get passed by reference. */
2306 if ((type && AGGREGATE_TYPE_P (type))
2310 n_words = RS6000_ARG_SIZE (mode, type);
2312 /* Long long is put in odd registers. */
2313 if (n_words == 2 && (gregno & 1) == 0)
2316 /* Long long is not split between registers and stack. */
2317 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
2318 return gen_rtx_REG (mode, gregno);
2325 int align = (TARGET_32BIT && (cum->words & 1) != 0
2326 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
2327 int align_words = cum->words + align;
2329 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2332 if (USE_FP_FOR_ARG_P (*cum, mode, type))
2335 || ((cum->nargs_prototype > 0)
2336 /* IBM AIX extended its linkage convention definition always
2337 to require FP args after register save area hole on the
2339 && (DEFAULT_ABI != ABI_AIX
2341 || (align_words < GP_ARG_NUM_REG))))
2342 return gen_rtx_REG (mode, cum->fregno);
2344 return gen_rtx_PARALLEL (mode,
2346 gen_rtx_EXPR_LIST (VOIDmode,
2347 ((align_words >= GP_ARG_NUM_REG)
2350 + RS6000_ARG_SIZE (mode, type)
2352 /* If this is partially on the stack, then
2353 we only include the portion actually
2354 in registers here. */
2355 ? gen_rtx_REG (SImode,
2356 GP_ARG_MIN_REG + align_words)
2357 : gen_rtx_REG (mode,
2358 GP_ARG_MIN_REG + align_words))),
2360 gen_rtx_EXPR_LIST (VOIDmode,
2361 gen_rtx_REG (mode, cum->fregno),
2364 else if (align_words < GP_ARG_NUM_REG)
2365 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
2371 /* For an arg passed partly in registers and partly in memory,
2372 this is the number of registers used.
2373 For args passed entirely in registers or entirely in memory, zero. */
2376 function_arg_partial_nregs (cum, mode, type, named)
2377 CUMULATIVE_ARGS *cum;
2378 enum machine_mode mode;
2380 int named ATTRIBUTE_UNUSED;
2382 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2385 if (USE_FP_FOR_ARG_P (*cum, mode, type))
2387 if (cum->nargs_prototype >= 0)
2391 if (cum->words < GP_ARG_NUM_REG
2392 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
2394 int ret = GP_ARG_NUM_REG - cum->words;
2395 if (ret && TARGET_DEBUG_ARG)
2396 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2404 /* A C expression that indicates when an argument must be passed by
2405 reference. If nonzero for an argument, a copy of that argument is
2406 made in memory and a pointer to the argument is passed instead of
2407 the argument itself. The pointer is passed in whatever way is
2408 appropriate for passing a pointer to that type.
2410 Under V.4, structures and unions are passed by reference. */
2413 function_arg_pass_by_reference (cum, mode, type, named)
2414 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2415 enum machine_mode mode ATTRIBUTE_UNUSED;
2417 int named ATTRIBUTE_UNUSED;
2419 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2420 && ((type && AGGREGATE_TYPE_P (type))
2423 if (TARGET_DEBUG_ARG)
2424 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
2432 /* Perform any needed actions needed for a function that is receiving a
2433 variable number of arguments.
2437 MODE and TYPE are the mode and type of the current parameter.
2439 PRETEND_SIZE is a variable that should be set to the amount of stack
2440 that must be pushed by the prolog to pretend that our caller pushed
2443 Normally, this macro will push all remaining incoming registers on the
2444 stack and set PRETEND_SIZE to the length of the registers pushed. */
2447 setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2448 CUMULATIVE_ARGS *cum;
2449 enum machine_mode mode;
2455 CUMULATIVE_ARGS next_cum;
2456 int reg_size = TARGET_32BIT ? 4 : 8;
2457 rtx save_area = NULL_RTX, mem;
2458 int first_reg_offset, set;
2462 fntype = TREE_TYPE (current_function_decl);
2463 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
2464 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2465 != void_type_node));
2467 /* For varargs, we do not want to skip the dummy va_dcl argument.
2468 For stdargs, we do want to skip the last named argument. */
2471 function_arg_advance (&next_cum, mode, type, 1);
2473 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2475 /* Indicate to allocate space on the stack for varargs save area. */
2476 /* ??? Does this really have to be located at a magic spot on the
2477 stack, or can we allocate this with assign_stack_local instead. */
2478 cfun->machine->sysv_varargs_p = 1;
2480 save_area = plus_constant (virtual_stack_vars_rtx,
2481 - RS6000_VARARGS_SIZE);
2483 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
2487 first_reg_offset = next_cum.words;
2488 save_area = virtual_incoming_args_rtx;
2489 cfun->machine->sysv_varargs_p = 0;
2491 if (MUST_PASS_IN_STACK (mode, type))
2492 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
2495 set = get_varargs_alias_set ();
2496 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
2498 mem = gen_rtx_MEM (BLKmode,
2499 plus_constant (save_area,
2500 first_reg_offset * reg_size)),
2501 set_mem_alias_set (mem, set);
2502 set_mem_align (mem, BITS_PER_WORD);
2505 (GP_ARG_MIN_REG + first_reg_offset, mem,
2506 GP_ARG_NUM_REG - first_reg_offset,
2507 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
2509 /* ??? Does ABI_V4 need this at all? */
2510 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
2513 /* Save FP registers if needed. */
2514 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
2515 && TARGET_HARD_FLOAT && ! no_rtl
2516 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
2518 int fregno = next_cum.fregno;
2519 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
2520 rtx lab = gen_label_rtx ();
2521 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
2523 emit_jump_insn (gen_rtx_SET (VOIDmode,
2525 gen_rtx_IF_THEN_ELSE (VOIDmode,
2526 gen_rtx_NE (VOIDmode, cr1,
2528 gen_rtx_LABEL_REF (VOIDmode, lab),
2531 while (fregno <= FP_ARG_V4_MAX_REG)
2533 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
2534 set_mem_alias_set (mem, set);
2535 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
2544 /* Create the va_list data type. */
2547 rs6000_build_va_list ()
2549 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
2551 /* For AIX, prefer 'char *' because that's what the system
2552 header files like. */
2553 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2554 return build_pointer_type (char_type_node);
2556 record = make_lang_type (RECORD_TYPE);
2557 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2559 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
2560 unsigned_char_type_node);
2561 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
2562 unsigned_char_type_node);
2563 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
2565 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
2568 DECL_FIELD_CONTEXT (f_gpr) = record;
2569 DECL_FIELD_CONTEXT (f_fpr) = record;
2570 DECL_FIELD_CONTEXT (f_ovf) = record;
2571 DECL_FIELD_CONTEXT (f_sav) = record;
2573 TREE_CHAIN (record) = type_decl;
2574 TYPE_NAME (record) = type_decl;
2575 TYPE_FIELDS (record) = f_gpr;
2576 TREE_CHAIN (f_gpr) = f_fpr;
2577 TREE_CHAIN (f_fpr) = f_ovf;
2578 TREE_CHAIN (f_ovf) = f_sav;
2580 layout_type (record);
2582 /* The correct type is an array type of one element. */
2583 return build_array_type (record, build_index_type (size_zero_node));
2586 /* Implement va_start. */
2589 rs6000_va_start (stdarg_p, valist, nextarg)
2594 HOST_WIDE_INT words, n_gpr, n_fpr;
2595 tree f_gpr, f_fpr, f_ovf, f_sav;
2596 tree gpr, fpr, ovf, sav, t;
2598 /* Only SVR4 needs something special. */
2599 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2601 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
2605 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2606 f_fpr = TREE_CHAIN (f_gpr);
2607 f_ovf = TREE_CHAIN (f_fpr);
2608 f_sav = TREE_CHAIN (f_ovf);
2610 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2611 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
2612 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
2613 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
2614 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
2616 /* Count number of gp and fp argument registers used. */
2617 words = current_function_args_info.words;
2618 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
2619 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
2621 if (TARGET_DEBUG_ARG)
2623 fputs ("va_start: words = ", stderr);
2624 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words);
2625 fputs (", n_gpr = ", stderr);
2626 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr);
2627 fputs (", n_fpr = ", stderr);
2628 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr);
2629 putc ('\n', stderr);
2632 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
2633 TREE_SIDE_EFFECTS (t) = 1;
2634 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2636 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
2637 TREE_SIDE_EFFECTS (t) = 1;
2638 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2640 /* Find the overflow area. */
2641 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
2643 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
2644 build_int_2 (words * UNITS_PER_WORD, 0));
2645 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
2646 TREE_SIDE_EFFECTS (t) = 1;
2647 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2649 /* Find the register save area. */
2650 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
2651 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
2652 build_int_2 (-RS6000_VARARGS_SIZE, -1));
2653 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
2654 TREE_SIDE_EFFECTS (t) = 1;
2655 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2658 /* Implement va_arg. */
2661 rs6000_va_arg (valist, type)
2664 tree f_gpr, f_fpr, f_ovf, f_sav;
2665 tree gpr, fpr, ovf, sav, reg, t, u;
2666 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
2667 rtx lab_false, lab_over, addr_rtx, r;
2669 /* For AIX, the rule is that structures are passed left-aligned in
2670 their stack slot. However, GCC does not presently do this:
2671 structures which are the same size as integer types are passed
2672 right-aligned, as if they were in fact integers. This only
2673 matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */
2674 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
2676 HOST_WIDE_INT align, rounded_size;
2677 enum machine_mode mode;
2680 /* Compute the rounded size of the type. */
2681 align = PARM_BOUNDARY / BITS_PER_UNIT;
2682 rounded_size = (((int_size_in_bytes (type) + align - 1) / align)
2687 mode = TYPE_MODE (type);
2688 if (mode != BLKmode)
2691 adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT;
2692 if (rounded_size > align)
2695 addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree,
2696 build_int_2 (rounded_size - adj, 0));
2699 addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
2700 addr_rtx = copy_to_reg (addr_rtx);
2702 /* Compute new value for AP. */
2703 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2704 build (PLUS_EXPR, TREE_TYPE (valist), valist,
2705 build_int_2 (rounded_size, 0)));
2706 TREE_SIDE_EFFECTS (t) = 1;
2707 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2712 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2713 f_fpr = TREE_CHAIN (f_gpr);
2714 f_ovf = TREE_CHAIN (f_fpr);
2715 f_sav = TREE_CHAIN (f_ovf);
2717 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2718 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
2719 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
2720 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
2721 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
2723 size = int_size_in_bytes (type);
2724 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2726 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
2728 /* Aggregates and long doubles are passed by reference. */
2734 size = rsize = UNITS_PER_WORD;
2736 else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT)
2738 /* FP args go in FP registers, if present. */
2747 /* Otherwise into GP registers. */
2755 /* Pull the value out of the saved registers ... */
2757 lab_false = gen_label_rtx ();
2758 lab_over = gen_label_rtx ();
2759 addr_rtx = gen_reg_rtx (Pmode);
2761 emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
2762 GEN_INT (8 - n_reg + 1),
2763 GE, const1_rtx, QImode, 1, 1, lab_false);
2765 /* Long long is aligned in the registers. */
2768 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
2769 build_int_2 (n_reg - 1, 0));
2770 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
2771 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
2772 TREE_SIDE_EFFECTS (u) = 1;
2773 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
2777 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
2781 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0));
2782 TREE_SIDE_EFFECTS (u) = 1;
2784 u = build1 (CONVERT_EXPR, integer_type_node, u);
2785 TREE_SIDE_EFFECTS (u) = 1;
2787 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
2788 TREE_SIDE_EFFECTS (u) = 1;
2790 t = build (PLUS_EXPR, ptr_type_node, t, u);
2791 TREE_SIDE_EFFECTS (t) = 1;
2793 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2795 emit_move_insn (addr_rtx, r);
2797 emit_jump_insn (gen_jump (lab_over));
2799 emit_label (lab_false);
2801 /* ... otherwise out of the overflow area. */
2803 /* Make sure we don't find reg 7 for the next int arg. */
2806 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
2807 TREE_SIDE_EFFECTS (t) = 1;
2808 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2811 /* Care for on-stack alignment if needed. */
2816 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0));
2817 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1));
2821 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2823 emit_move_insn (addr_rtx, r);
2825 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
2826 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
2827 TREE_SIDE_EFFECTS (t) = 1;
2828 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2830 emit_label (lab_over);
2834 r = gen_rtx_MEM (Pmode, addr_rtx);
2835 set_mem_alias_set (r, get_varargs_alias_set ());
2836 emit_move_insn (addr_rtx, r);
2842 /* Generate a memory reference for expand_block_move, copying volatile,
2843 and other bits from an original memory reference. */
2846 expand_block_move_mem (mode, addr, orig_mem)
2847 enum machine_mode mode;
2851 rtx mem = gen_rtx_MEM (mode, addr);
2853 MEM_COPY_ATTRIBUTES (mem, orig_mem);
2857 /* Expand a block move operation, and return 1 if successful. Return 0
2858 if we should let the compiler generate normal code.
2860 operands[0] is the destination
2861 operands[1] is the source
2862 operands[2] is the length
2863 operands[3] is the alignment */
2865 #define MAX_MOVE_REG 4
2868 expand_block_move (operands)
2871 rtx orig_dest = operands[0];
2872 rtx orig_src = operands[1];
2873 rtx bytes_rtx = operands[2];
2874 rtx align_rtx = operands[3];
2875 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2886 rtx stores[MAX_MOVE_REG];
2889 /* If this is not a fixed size move, just call memcpy */
2893 /* If this is not a fixed size alignment, abort */
2894 if (GET_CODE (align_rtx) != CONST_INT)
2896 align = INTVAL (align_rtx);
2898 /* Anything to move? */
2899 bytes = INTVAL (bytes_rtx);
2903 /* Don't support real large moves. If string instructions are not used,
2904 then don't generate more than 8 loads. */
2910 else if (! STRICT_ALIGNMENT)
2912 if (TARGET_POWERPC64 && align >= 4)
2921 else if (bytes > 8*align)
2924 /* Move the address into scratch registers. */
2925 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2926 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2928 if (TARGET_STRING) /* string instructions are available */
2930 for ( ; bytes > 0; bytes -= move_bytes)
2932 if (bytes > 24 /* move up to 32 bytes at a time */
2940 && ! fixed_regs[12])
2942 move_bytes = (bytes > 32) ? 32 : bytes;
2943 emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode,
2946 expand_block_move_mem (BLKmode,
2949 GEN_INT ((move_bytes == 32)
2953 else if (bytes > 16 /* move up to 24 bytes at a time */
2959 && ! fixed_regs[10])
2961 move_bytes = (bytes > 24) ? 24 : bytes;
2962 emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode,
2965 expand_block_move_mem (BLKmode,
2968 GEN_INT (move_bytes),
2971 else if (bytes > 8 /* move up to 16 bytes at a time */
2977 move_bytes = (bytes > 16) ? 16 : bytes;
2978 emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode,
2981 expand_block_move_mem (BLKmode,
2984 GEN_INT (move_bytes),
2987 else if (bytes >= 8 && TARGET_POWERPC64
2988 /* 64-bit loads and stores require word-aligned
2990 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
2993 tmp_reg = gen_reg_rtx (DImode);
2994 emit_move_insn (tmp_reg,
2995 expand_block_move_mem (DImode,
2996 src_reg, orig_src));
2997 emit_move_insn (expand_block_move_mem (DImode,
2998 dest_reg, orig_dest),
3002 { /* move up to 8 bytes at a time */
3003 move_bytes = (bytes > 8) ? 8 : bytes;
3004 emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
3007 expand_block_move_mem (BLKmode,
3010 GEN_INT (move_bytes),
3013 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3014 { /* move 4 bytes */
3016 tmp_reg = gen_reg_rtx (SImode);
3017 emit_move_insn (tmp_reg,
3018 expand_block_move_mem (SImode,
3019 src_reg, orig_src));
3020 emit_move_insn (expand_block_move_mem (SImode,
3021 dest_reg, orig_dest),
3024 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3025 { /* move 2 bytes */
3027 tmp_reg = gen_reg_rtx (HImode);
3028 emit_move_insn (tmp_reg,
3029 expand_block_move_mem (HImode,
3030 src_reg, orig_src));
3031 emit_move_insn (expand_block_move_mem (HImode,
3032 dest_reg, orig_dest),
3035 else if (bytes == 1) /* move 1 byte */
3038 tmp_reg = gen_reg_rtx (QImode);
3039 emit_move_insn (tmp_reg,
3040 expand_block_move_mem (QImode,
3041 src_reg, orig_src));
3042 emit_move_insn (expand_block_move_mem (QImode,
3043 dest_reg, orig_dest),
3047 { /* move up to 4 bytes at a time */
3048 move_bytes = (bytes > 4) ? 4 : bytes;
3049 emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode,
3052 expand_block_move_mem (BLKmode,
3055 GEN_INT (move_bytes),
3059 if (bytes > move_bytes)
3061 if (! TARGET_POWERPC64)
3063 emit_insn (gen_addsi3 (src_reg, src_reg,
3064 GEN_INT (move_bytes)));
3065 emit_insn (gen_addsi3 (dest_reg, dest_reg,
3066 GEN_INT (move_bytes)));
3070 emit_insn (gen_adddi3 (src_reg, src_reg,
3071 GEN_INT (move_bytes)));
3072 emit_insn (gen_adddi3 (dest_reg, dest_reg,
3073 GEN_INT (move_bytes)));
3079 else /* string instructions not available */
3081 num_reg = offset = 0;
3082 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
3084 /* Calculate the correct offset for src/dest */
3088 dest_addr = dest_reg;
3092 src_addr = plus_constant (src_reg, offset);
3093 dest_addr = plus_constant (dest_reg, offset);
3096 /* Generate the appropriate load and store, saving the stores
3098 if (bytes >= 8 && TARGET_POWERPC64
3099 /* 64-bit loads and stores require word-aligned
3101 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
3104 tmp_reg = gen_reg_rtx (DImode);
3105 emit_insn (gen_movdi (tmp_reg,
3106 expand_block_move_mem (DImode,
3109 stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode,
3114 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3117 tmp_reg = gen_reg_rtx (SImode);
3118 emit_insn (gen_movsi (tmp_reg,
3119 expand_block_move_mem (SImode,
3122 stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode,
3127 else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3130 tmp_reg = gen_reg_rtx (HImode);
3131 emit_insn (gen_movhi (tmp_reg,
3132 expand_block_move_mem (HImode,
3135 stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode,
3143 tmp_reg = gen_reg_rtx (QImode);
3144 emit_insn (gen_movqi (tmp_reg,
3145 expand_block_move_mem (QImode,
3148 stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode,
3154 if (num_reg >= MAX_MOVE_REG)
3156 for (i = 0; i < num_reg; i++)
3157 emit_insn (stores[i]);
3162 for (i = 0; i < num_reg; i++)
3163 emit_insn (stores[i]);
3170 /* Return 1 if OP is a load multiple operation. It is known to be a
3171 PARALLEL and the first section will be tested. */
3174 load_multiple_operation (op, mode)
3176 enum machine_mode mode ATTRIBUTE_UNUSED;
3178 int count = XVECLEN (op, 0);
3179 unsigned int dest_regno;
3183 /* Perform a quick check so we don't blow up below. */
3185 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3186 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
3187 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
3190 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
3191 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
3193 for (i = 1; i < count; i++)
3195 rtx elt = XVECEXP (op, 0, i);
3197 if (GET_CODE (elt) != SET
3198 || GET_CODE (SET_DEST (elt)) != REG
3199 || GET_MODE (SET_DEST (elt)) != SImode
3200 || REGNO (SET_DEST (elt)) != dest_regno + i
3201 || GET_CODE (SET_SRC (elt)) != MEM
3202 || GET_MODE (SET_SRC (elt)) != SImode
3203 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3204 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3205 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3206 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
3213 /* Similar, but tests for store multiple. Here, the second vector element
3214 is a CLOBBER. It will be tested later. */
3217 store_multiple_operation (op, mode)
3219 enum machine_mode mode ATTRIBUTE_UNUSED;
3221 int count = XVECLEN (op, 0) - 1;
3222 unsigned int src_regno;
3226 /* Perform a quick check so we don't blow up below. */
3228 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3229 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
3230 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
3233 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
3234 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
3236 for (i = 1; i < count; i++)
3238 rtx elt = XVECEXP (op, 0, i + 1);
3240 if (GET_CODE (elt) != SET
3241 || GET_CODE (SET_SRC (elt)) != REG
3242 || GET_MODE (SET_SRC (elt)) != SImode
3243 || REGNO (SET_SRC (elt)) != src_regno + i
3244 || GET_CODE (SET_DEST (elt)) != MEM
3245 || GET_MODE (SET_DEST (elt)) != SImode
3246 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3247 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3248 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3249 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
3256 /* Return 1 for an PARALLEL suitable for mtcrf. */
3259 mtcrf_operation (op, mode)
3261 enum machine_mode mode ATTRIBUTE_UNUSED;
3263 int count = XVECLEN (op, 0);
3267 /* Perform a quick check so we don't blow up below. */
3269 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3270 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
3271 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
3273 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
3275 if (GET_CODE (src_reg) != REG
3276 || GET_MODE (src_reg) != SImode
3277 || ! INT_REGNO_P (REGNO (src_reg)))
3280 for (i = 0; i < count; i++)
3282 rtx exp = XVECEXP (op, 0, i);
3286 if (GET_CODE (exp) != SET
3287 || GET_CODE (SET_DEST (exp)) != REG
3288 || GET_MODE (SET_DEST (exp)) != CCmode
3289 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
3291 unspec = SET_SRC (exp);
3292 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
3294 if (GET_CODE (unspec) != UNSPEC
3295 || XINT (unspec, 1) != 20
3296 || XVECLEN (unspec, 0) != 2
3297 || XVECEXP (unspec, 0, 0) != src_reg
3298 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
3299 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
3305 /* Return 1 for an PARALLEL suitable for lmw. */
3308 lmw_operation (op, mode)
3310 enum machine_mode mode ATTRIBUTE_UNUSED;
3312 int count = XVECLEN (op, 0);
3313 unsigned int dest_regno;
3315 unsigned int base_regno;
3316 HOST_WIDE_INT offset;
3319 /* Perform a quick check so we don't blow up below. */
3321 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3322 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
3323 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
3326 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
3327 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
3330 || count != 32 - (int) dest_regno)
3333 if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0))
3336 base_regno = REGNO (src_addr);
3337 if (base_regno == 0)
3340 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0))
3342 offset = INTVAL (XEXP (src_addr, 1));
3343 base_regno = REGNO (XEXP (src_addr, 0));
3348 for (i = 0; i < count; i++)
3350 rtx elt = XVECEXP (op, 0, i);
3353 HOST_WIDE_INT newoffset;
3355 if (GET_CODE (elt) != SET
3356 || GET_CODE (SET_DEST (elt)) != REG
3357 || GET_MODE (SET_DEST (elt)) != SImode
3358 || REGNO (SET_DEST (elt)) != dest_regno + i
3359 || GET_CODE (SET_SRC (elt)) != MEM
3360 || GET_MODE (SET_SRC (elt)) != SImode)
3362 newaddr = XEXP (SET_SRC (elt), 0);
3363 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
3368 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
3370 addr_reg = XEXP (newaddr, 0);
3371 newoffset = INTVAL (XEXP (newaddr, 1));
3375 if (REGNO (addr_reg) != base_regno
3376 || newoffset != offset + 4 * i)
3383 /* Return 1 for an PARALLEL suitable for stmw. */
3386 stmw_operation (op, mode)
3388 enum machine_mode mode ATTRIBUTE_UNUSED;
3390 int count = XVECLEN (op, 0);
3391 unsigned int src_regno;
3393 unsigned int base_regno;
3394 HOST_WIDE_INT offset;
3397 /* Perform a quick check so we don't blow up below. */
3399 || GET_CODE (XVECEXP (op, 0, 0)) != SET
3400 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
3401 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
3404 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
3405 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
3408 || count != 32 - (int) src_regno)
3411 if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0))
3414 base_regno = REGNO (dest_addr);
3415 if (base_regno == 0)
3418 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0))
3420 offset = INTVAL (XEXP (dest_addr, 1));
3421 base_regno = REGNO (XEXP (dest_addr, 0));
3426 for (i = 0; i < count; i++)
3428 rtx elt = XVECEXP (op, 0, i);
3431 HOST_WIDE_INT newoffset;
3433 if (GET_CODE (elt) != SET
3434 || GET_CODE (SET_SRC (elt)) != REG
3435 || GET_MODE (SET_SRC (elt)) != SImode
3436 || REGNO (SET_SRC (elt)) != src_regno + i
3437 || GET_CODE (SET_DEST (elt)) != MEM
3438 || GET_MODE (SET_DEST (elt)) != SImode)
3440 newaddr = XEXP (SET_DEST (elt), 0);
3441 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
3446 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
3448 addr_reg = XEXP (newaddr, 0);
3449 newoffset = INTVAL (XEXP (newaddr, 1));
3453 if (REGNO (addr_reg) != base_regno
3454 || newoffset != offset + 4 * i)
3461 /* A validation routine: say whether CODE, a condition code, and MODE
3462 match. The other alternatives either don't make sense or should
3463 never be generated. */
3466 validate_condition_mode (code, mode)
3468 enum machine_mode mode;
3470 if (GET_RTX_CLASS (code) != '<'
3471 || GET_MODE_CLASS (mode) != MODE_CC)
3474 /* These don't make sense. */
3475 if ((code == GT || code == LT || code == GE || code == LE)
3476 && mode == CCUNSmode)
3479 if ((code == GTU || code == LTU || code == GEU || code == LEU)
3480 && mode != CCUNSmode)
3483 if (mode != CCFPmode
3484 && (code == ORDERED || code == UNORDERED
3485 || code == UNEQ || code == LTGT
3486 || code == UNGT || code == UNLT
3487 || code == UNGE || code == UNLE))
3490 /* These should never be generated except for
3491 flag_unsafe_math_optimizations. */
3492 if (mode == CCFPmode
3493 && ! flag_unsafe_math_optimizations
3494 && (code == LE || code == GE
3495 || code == UNEQ || code == LTGT
3496 || code == UNGT || code == UNLT))
3499 /* These are invalid; the information is not there. */
3500 if (mode == CCEQmode
3501 && code != EQ && code != NE)
3505 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
3506 We only check the opcode against the mode of the CC value here. */
3509 branch_comparison_operator (op, mode)
3511 enum machine_mode mode ATTRIBUTE_UNUSED;
3513 enum rtx_code code = GET_CODE (op);
3514 enum machine_mode cc_mode;
3516 if (GET_RTX_CLASS (code) != '<')
3519 cc_mode = GET_MODE (XEXP (op, 0));
3520 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
3523 validate_condition_mode (code, cc_mode);
3528 /* Return 1 if OP is a comparison operation that is valid for a branch
3529 insn and which is true if the corresponding bit in the CC register
3533 branch_positive_comparison_operator (op, mode)
3535 enum machine_mode mode;
3539 if (! branch_comparison_operator (op, mode))
3542 code = GET_CODE (op);
3543 return (code == EQ || code == LT || code == GT
3544 || code == LTU || code == GTU
3545 || code == UNORDERED);
3548 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
3549 We check the opcode against the mode of the CC value and disallow EQ or
3550 NE comparisons for integers. */
3553 scc_comparison_operator (op, mode)
3555 enum machine_mode mode;
3557 enum rtx_code code = GET_CODE (op);
3558 enum machine_mode cc_mode;
3560 if (GET_MODE (op) != mode && mode != VOIDmode)
3563 if (GET_RTX_CLASS (code) != '<')
3566 cc_mode = GET_MODE (XEXP (op, 0));
3567 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
3570 validate_condition_mode (code, cc_mode);
3572 if (code == NE && cc_mode != CCFPmode)
3579 trap_comparison_operator (op, mode)
3581 enum machine_mode mode;
3583 if (mode != VOIDmode && mode != GET_MODE (op))
3585 return GET_RTX_CLASS (GET_CODE (op)) == '<';
3589 boolean_operator (op, mode)
3591 enum machine_mode mode ATTRIBUTE_UNUSED;
3593 enum rtx_code code = GET_CODE (op);
3594 return (code == AND || code == IOR || code == XOR);
3598 boolean_or_operator (op, mode)
3600 enum machine_mode mode ATTRIBUTE_UNUSED;
3602 enum rtx_code code = GET_CODE (op);
3603 return (code == IOR || code == XOR);
3607 min_max_operator (op, mode)
3609 enum machine_mode mode ATTRIBUTE_UNUSED;
3611 enum rtx_code code = GET_CODE (op);
3612 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
3615 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
3616 mask required to convert the result of a rotate insn into a shift
3617 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
3620 includes_lshift_p (shiftop, andop)
3624 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
3626 shift_mask <<= INTVAL (shiftop);
3628 return (INTVAL (andop) & ~shift_mask) == 0;
3631 /* Similar, but for right shift. */
3634 includes_rshift_p (shiftop, andop)
3638 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
3640 shift_mask >>= INTVAL (shiftop);
3642 return (INTVAL (andop) & ~shift_mask) == 0;
3645 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
3646 to perform a left shift. It must have exactly SHIFTOP least
3647 signifigant 0's, then one or more 1's, then zero or more 0's. */
3650 includes_rldic_lshift_p (shiftop, andop)
3654 if (GET_CODE (andop) == CONST_INT)
3656 HOST_WIDE_INT c, lsb, shift_mask;
3659 if (c == 0 || c == ~0)
3663 shift_mask <<= INTVAL (shiftop);
3665 /* Find the least signifigant one bit. */
3668 /* It must coincide with the LSB of the shift mask. */
3669 if (-lsb != shift_mask)
3672 /* Invert to look for the next transition (if any). */
3675 /* Remove the low group of ones (originally low group of zeros). */
3678 /* Again find the lsb, and check we have all 1's above. */
3682 else if (GET_CODE (andop) == CONST_DOUBLE
3683 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
3685 HOST_WIDE_INT low, high, lsb;
3686 HOST_WIDE_INT shift_mask_low, shift_mask_high;
3688 low = CONST_DOUBLE_LOW (andop);
3689 if (HOST_BITS_PER_WIDE_INT < 64)
3690 high = CONST_DOUBLE_HIGH (andop);
3692 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
3693 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
3696 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
3698 shift_mask_high = ~0;
3699 if (INTVAL (shiftop) > 32)
3700 shift_mask_high <<= INTVAL (shiftop) - 32;
3704 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
3711 return high == -lsb;
3714 shift_mask_low = ~0;
3715 shift_mask_low <<= INTVAL (shiftop);
3719 if (-lsb != shift_mask_low)
3722 if (HOST_BITS_PER_WIDE_INT < 64)
3727 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
3730 return high == -lsb;
3734 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
3740 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
3741 to perform a left shift. It must have SHIFTOP or more least
3742 signifigant 0's, with the remainder of the word 1's. */
3745 includes_rldicr_lshift_p (shiftop, andop)
3749 if (GET_CODE (andop) == CONST_INT)
3751 HOST_WIDE_INT c, lsb, shift_mask;
3754 shift_mask <<= INTVAL (shiftop);
3757 /* Find the least signifigant one bit. */
3760 /* It must be covered by the shift mask.
3761 This test also rejects c == 0. */
3762 if ((lsb & shift_mask) == 0)
3765 /* Check we have all 1's above the transition, and reject all 1's. */
3766 return c == -lsb && lsb != 1;
3768 else if (GET_CODE (andop) == CONST_DOUBLE
3769 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
3771 HOST_WIDE_INT low, lsb, shift_mask_low;
3773 low = CONST_DOUBLE_LOW (andop);
3775 if (HOST_BITS_PER_WIDE_INT < 64)
3777 HOST_WIDE_INT high, shift_mask_high;
3779 high = CONST_DOUBLE_HIGH (andop);
3783 shift_mask_high = ~0;
3784 if (INTVAL (shiftop) > 32)
3785 shift_mask_high <<= INTVAL (shiftop) - 32;
3789 if ((lsb & shift_mask_high) == 0)
3792 return high == -lsb;
3798 shift_mask_low = ~0;
3799 shift_mask_low <<= INTVAL (shiftop);
3803 if ((lsb & shift_mask_low) == 0)
3806 return low == -lsb && lsb != 1;
3812 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
3813 for lfq and stfq insns.
3815 Note reg1 and reg2 *must* be hard registers. To be sure we will
3816 abort if we are passed pseudo registers. */
3819 registers_ok_for_quad_peep (reg1, reg2)
3822 /* We might have been passed a SUBREG. */
3823 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
3826 return (REGNO (reg1) == REGNO (reg2) - 1);
3829 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
3830 addr1 and addr2 must be in consecutive memory locations
3831 (addr2 == addr1 + 8). */
3834 addrs_ok_for_quad_peep (addr1, addr2)
3841 /* Extract an offset (if used) from the first addr. */
3842 if (GET_CODE (addr1) == PLUS)
3844 /* If not a REG, return zero. */
3845 if (GET_CODE (XEXP (addr1, 0)) != REG)
3849 reg1 = REGNO (XEXP (addr1, 0));
3850 /* The offset must be constant! */
3851 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
3853 offset1 = INTVAL (XEXP (addr1, 1));
3856 else if (GET_CODE (addr1) != REG)
3860 reg1 = REGNO (addr1);
3861 /* This was a simple (mem (reg)) expression. Offset is 0. */
3865 /* Make sure the second address is a (mem (plus (reg) (const_int))). */
3866 if (GET_CODE (addr2) != PLUS)
3869 if (GET_CODE (XEXP (addr2, 0)) != REG
3870 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
3873 if (reg1 != REGNO (XEXP (addr2, 0)))
3876 /* The offset for the second addr must be 8 more than the first addr. */
3877 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
3880 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
3885 /* Return the register class of a scratch register needed to copy IN into
3886 or out of a register in CLASS in MODE. If it can be done directly,
3887 NO_REGS is returned. */
3890 secondary_reload_class (class, mode, in)
3891 enum reg_class class;
3892 enum machine_mode mode ATTRIBUTE_UNUSED;
3897 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic))
3899 /* We cannot copy a symbolic operand directly into anything
3900 other than BASE_REGS for TARGET_ELF. So indicate that a
3901 register from BASE_REGS is needed as an intermediate
3904 On Darwin, pic addresses require a load from memory, which
3905 needs a base register. */
3906 if (class != BASE_REGS
3907 && (GET_CODE (in) == SYMBOL_REF
3908 || GET_CODE (in) == HIGH
3909 || GET_CODE (in) == LABEL_REF
3910 || GET_CODE (in) == CONST))
3914 if (GET_CODE (in) == REG)
3917 if (regno >= FIRST_PSEUDO_REGISTER)
3919 regno = true_regnum (in);
3920 if (regno >= FIRST_PSEUDO_REGISTER)
3924 else if (GET_CODE (in) == SUBREG)
3926 regno = true_regnum (in);
3927 if (regno >= FIRST_PSEUDO_REGISTER)
3933 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
3935 if (class == GENERAL_REGS || class == BASE_REGS
3936 || (regno >= 0 && INT_REGNO_P (regno)))
3939 /* Constants, memory, and FP registers can go into FP registers. */
3940 if ((regno == -1 || FP_REGNO_P (regno))
3941 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
3944 /* We can copy among the CR registers. */
3945 if ((class == CR_REGS || class == CR0_REGS)
3946 && regno >= 0 && CR_REGNO_P (regno))
3949 /* Otherwise, we need GENERAL_REGS. */
3950 return GENERAL_REGS;
3953 /* Given a comparison operation, return the bit number in CCR to test. We
3954 know this is a valid comparison.
3956 SCC_P is 1 if this is for an scc. That means that %D will have been
3957 used instead of %C, so the bits will be in different places.
3959 Return -1 if OP isn't a valid comparison for some reason. */
3966 enum rtx_code code = GET_CODE (op);
3967 enum machine_mode cc_mode;
3972 if (GET_RTX_CLASS (code) != '<')
3977 if (GET_CODE (reg) != REG
3978 || ! CR_REGNO_P (REGNO (reg)))
3981 cc_mode = GET_MODE (reg);
3982 cc_regnum = REGNO (reg);
3983 base_bit = 4 * (cc_regnum - CR0_REGNO);
3985 validate_condition_mode (code, cc_mode);
3990 return scc_p ? base_bit + 3 : base_bit + 2;
3992 return base_bit + 2;
3993 case GT: case GTU: case UNLE:
3994 return base_bit + 1;
3995 case LT: case LTU: case UNGE:
3997 case ORDERED: case UNORDERED:
3998 return base_bit + 3;
4001 /* If scc, we will have done a cror to put the bit in the
4002 unordered position. So test that bit. For integer, this is ! LT
4003 unless this is an scc insn. */
4004 return scc_p ? base_bit + 3 : base_bit;
4007 return scc_p ? base_bit + 3 : base_bit + 1;
4014 /* Return the GOT register. */
4017 rs6000_got_register (value)
4018 rtx value ATTRIBUTE_UNUSED;
4020 /* The second flow pass currently (June 1999) can't update
4021 regs_ever_live without disturbing other parts of the compiler, so
4022 update it here to make the prolog/epilogue code happy. */
4023 if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4024 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4026 current_function_uses_pic_offset_table = 1;
4028 return pic_offset_table_rtx;
4031 /* Functions to init, mark and free struct machine_function.
4032 These will be called, via pointer variables,
4033 from push_function_context and pop_function_context. */
4036 rs6000_init_machine_status (p)
4039 p->machine = (machine_function *) xcalloc (1, sizeof (machine_function));
4043 rs6000_free_machine_status (p)
4046 if (p->machine == NULL)
4054 /* Print an operand. Recognize special options, documented below. */
4057 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
4058 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
4060 #define SMALL_DATA_RELOC "sda21"
4061 #define SMALL_DATA_REG 0
4065 print_operand (file, x, code)
4073 /* These macros test for integers and extract the low-order bits. */
4075 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
4076 && GET_MODE (X) == VOIDmode)
4078 #define INT_LOWPART(X) \
4079 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
4084 /* Write out an instruction after the call which may be replaced
4085 with glue code by the loader. This depends on the AIX version. */
4086 asm_fprintf (file, RS6000_CALL_GLUE);
4090 /* Write out either a '.' or '$' for the current location, depending
4091 on whether this is Solaris or not. */
4092 putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file);
4095 /* %a is output_address. */
4098 /* If X is a constant integer whose low-order 5 bits are zero,
4099 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
4100 in the AIX assembler where "sri" with a zero shift count
4101 write a trash instruction. */
4102 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
4109 /* If constant, low-order 16 bits of constant, unsigned.
4110 Otherwise, write normally. */
4112 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
4114 print_operand (file, x, 0);
4118 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
4119 for 64-bit mask direction. */
4120 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
4123 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
4127 /* There used to be a comment for 'C' reading "This is an
4128 optional cror needed for certain floating-point
4129 comparisons. Otherwise write nothing." */
4131 /* Similar, except that this is for an scc, so we must be able to
4132 encode the test in a single bit that is one. We do the above
4133 for any LE, GE, GEU, or LEU and invert the bit for NE. */
4134 if (GET_CODE (x) == LE || GET_CODE (x) == GE
4135 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
4137 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
4139 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
4141 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
4144 else if (GET_CODE (x) == NE)
4146 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
4148 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
4149 base_bit + 2, base_bit + 2);
4154 /* X is a CR register. Print the number of the EQ bit of the CR */
4155 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4156 output_operand_lossage ("invalid %%E value");
4158 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
4162 /* X is a CR register. Print the shift count needed to move it
4163 to the high-order four bits. */
4164 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4165 output_operand_lossage ("invalid %%f value");
4167 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
4171 /* Similar, but print the count for the rotate in the opposite
4173 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4174 output_operand_lossage ("invalid %%F value");
4176 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
4180 /* X is a constant integer. If it is negative, print "m",
4181 otherwise print "z". This is to make a aze or ame insn. */
4182 if (GET_CODE (x) != CONST_INT)
4183 output_operand_lossage ("invalid %%G value");
4184 else if (INTVAL (x) >= 0)
4191 /* If constant, output low-order five bits. Otherwise, write
4194 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
4196 print_operand (file, x, 0);
4200 /* If constant, output low-order six bits. Otherwise, write
4203 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
4205 print_operand (file, x, 0);
4209 /* Print `i' if this is a constant, else nothing. */
4215 /* Write the bit number in CCR for jump. */
4218 output_operand_lossage ("invalid %%j code");
4220 fprintf (file, "%d", i);
4224 /* Similar, but add one for shift count in rlinm for scc and pass
4225 scc flag to `ccr_bit'. */
4228 output_operand_lossage ("invalid %%J code");
4230 /* If we want bit 31, write a shift count of zero, not 32. */
4231 fprintf (file, "%d", i == 31 ? 0 : i + 1);
4235 /* X must be a constant. Write the 1's complement of the
4238 output_operand_lossage ("invalid %%k value");
4240 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
4244 /* X must be a symbolic constant on ELF. Write an
4245 expression suitable for an 'addi' that adds in the low 16
4247 if (GET_CODE (x) != CONST)
4249 print_operand_address (file, x);
4254 if (GET_CODE (XEXP (x, 0)) != PLUS
4255 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
4256 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
4257 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
4258 output_operand_lossage ("invalid %%K value");
4259 print_operand_address (file, XEXP (XEXP (x, 0), 0));
4261 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
4265 /* %l is output_asm_label. */
4268 /* Write second word of DImode or DFmode reference. Works on register
4269 or non-indexed memory only. */
4270 if (GET_CODE (x) == REG)
4271 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
4272 else if (GET_CODE (x) == MEM)
4274 /* Handle possible auto-increment. Since it is pre-increment and
4275 we have already done it, we can just use an offset of word. */
4276 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4277 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4278 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
4281 output_address (XEXP (adjust_address_nv (x, SImode,
4285 if (small_data_operand (x, GET_MODE (x)))
4286 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4287 reg_names[SMALL_DATA_REG]);
4292 /* MB value for a mask operand. */
4293 if (! mask_operand (x, VOIDmode))
4294 output_operand_lossage ("invalid %%m value");
4296 val = INT_LOWPART (x);
4298 /* If the high bit is set and the low bit is not, the value is zero.
4299 If the high bit is zero, the value is the first 1 bit we find from
4301 if ((val & 0x80000000) && ((val & 1) == 0))
4306 else if ((val & 0x80000000) == 0)
4308 for (i = 1; i < 32; i++)
4309 if ((val <<= 1) & 0x80000000)
4311 fprintf (file, "%d", i);
4315 /* Otherwise, look for the first 0 bit from the right. The result is its
4316 number plus 1. We know the low-order bit is one. */
4317 for (i = 0; i < 32; i++)
4318 if (((val >>= 1) & 1) == 0)
4321 /* If we ended in ...01, i would be 0. The correct value is 31, so
4323 fprintf (file, "%d", 31 - i);
4327 /* ME value for a mask operand. */
4328 if (! mask_operand (x, VOIDmode))
4329 output_operand_lossage ("invalid %%M value");
4331 val = INT_LOWPART (x);
4333 /* If the low bit is set and the high bit is not, the value is 31.
4334 If the low bit is zero, the value is the first 1 bit we find from
4336 if ((val & 1) && ((val & 0x80000000) == 0))
4341 else if ((val & 1) == 0)
4343 for (i = 0; i < 32; i++)
4344 if ((val >>= 1) & 1)
4347 /* If we had ....10, i would be 0. The result should be
4348 30, so we need 30 - i. */
4349 fprintf (file, "%d", 30 - i);
4353 /* Otherwise, look for the first 0 bit from the left. The result is its
4354 number minus 1. We know the high-order bit is one. */
4355 for (i = 0; i < 32; i++)
4356 if (((val <<= 1) & 0x80000000) == 0)
4359 fprintf (file, "%d", i);
4362 /* %n outputs the negative of its operand. */
4365 /* Write the number of elements in the vector times 4. */
4366 if (GET_CODE (x) != PARALLEL)
4367 output_operand_lossage ("invalid %%N value");
4369 fprintf (file, "%d", XVECLEN (x, 0) * 4);
4373 /* Similar, but subtract 1 first. */
4374 if (GET_CODE (x) != PARALLEL)
4375 output_operand_lossage ("invalid %%O value");
4377 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
4381 /* X is a CONST_INT that is a power of two. Output the logarithm. */
4383 || INT_LOWPART (x) < 0
4384 || (i = exact_log2 (INT_LOWPART (x))) < 0)
4385 output_operand_lossage ("invalid %%p value");
4387 fprintf (file, "%d", i);
4391 /* The operand must be an indirect memory reference. The result
4392 is the register number. */
4393 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
4394 || REGNO (XEXP (x, 0)) >= 32)
4395 output_operand_lossage ("invalid %%P value");
4397 fprintf (file, "%d", REGNO (XEXP (x, 0)));
4401 /* This outputs the logical code corresponding to a boolean
4402 expression. The expression may have one or both operands
4403 negated (if one, only the first one). For condition register
4404 logical operations, it will also treat the negated
4405 CR codes as NOTs, but not handle NOTs of them. */
4407 const char *const *t = 0;
4409 enum rtx_code code = GET_CODE (x);
4410 static const char * const tbl[3][3] = {
4411 { "and", "andc", "nor" },
4412 { "or", "orc", "nand" },
4413 { "xor", "eqv", "xor" } };
4417 else if (code == IOR)
4419 else if (code == XOR)
4422 output_operand_lossage ("invalid %%q value");
4424 if (GET_CODE (XEXP (x, 0)) != NOT)
4428 if (GET_CODE (XEXP (x, 1)) == NOT)
4439 /* X is a CR register. Print the mask for `mtcrf'. */
4440 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
4441 output_operand_lossage ("invalid %%R value");
4443 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
4447 /* Low 5 bits of 32 - value */
4449 output_operand_lossage ("invalid %%s value");
4451 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
4455 /* PowerPC64 mask position. All 0's and all 1's are excluded.
4456 CONST_INT 32-bit mask is considered sign-extended so any
4457 transition must occur within the CONST_INT, not on the boundary. */
4458 if (! mask64_operand (x, VOIDmode))
4459 output_operand_lossage ("invalid %%S value");
4461 val = INT_LOWPART (x);
4463 if (val & 1) /* Clear Left */
4465 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4466 if (!((val >>= 1) & 1))
4469 #if HOST_BITS_PER_WIDE_INT == 32
4470 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4472 val = CONST_DOUBLE_HIGH (x);
4477 for (i = 32; i < 64; i++)
4478 if (!((val >>= 1) & 1))
4482 /* i = index of last set bit from right
4483 mask begins at 63 - i from left */
4485 output_operand_lossage ("%%S computed all 1's mask");
4487 fprintf (file, "%d", 63 - i);
4490 else /* Clear Right */
4492 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4493 if ((val >>= 1) & 1)
4496 #if HOST_BITS_PER_WIDE_INT == 32
4497 if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4499 val = CONST_DOUBLE_HIGH (x);
4501 if (val == (HOST_WIDE_INT) -1)
4504 for (i = 32; i < 64; i++)
4505 if ((val >>= 1) & 1)
4509 /* i = index of last clear bit from right
4510 mask ends at 62 - i from left */
4512 output_operand_lossage ("%%S computed all 0's mask");
4514 fprintf (file, "%d", 62 - i);
4519 /* Print the symbolic name of a branch target register. */
4520 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
4521 && REGNO (x) != COUNT_REGISTER_REGNUM))
4522 output_operand_lossage ("invalid %%T value");
4523 else if (REGNO (x) == LINK_REGISTER_REGNUM)
4524 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
4526 fputs ("ctr", file);
4530 /* High-order 16 bits of constant for use in unsigned operand. */
4532 output_operand_lossage ("invalid %%u value");
4534 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
4535 (INT_LOWPART (x) >> 16) & 0xffff);
4539 /* High-order 16 bits of constant for use in signed operand. */
4541 output_operand_lossage ("invalid %%v value");
4544 int value = (INT_LOWPART (x) >> 16) & 0xffff;
4546 /* Solaris assembler doesn't like lis 0,0x8000 */
4547 if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
4548 fprintf (file, "%d", value | (~0 << 16));
4550 fprintf (file, "0x%x", value);
4555 /* Print `u' if this has an auto-increment or auto-decrement. */
4556 if (GET_CODE (x) == MEM
4557 && (GET_CODE (XEXP (x, 0)) == PRE_INC
4558 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
4563 /* Print the trap code for this operand. */
4564 switch (GET_CODE (x))
4567 fputs ("eq", file); /* 4 */
4570 fputs ("ne", file); /* 24 */
4573 fputs ("lt", file); /* 16 */
4576 fputs ("le", file); /* 20 */
4579 fputs ("gt", file); /* 8 */
4582 fputs ("ge", file); /* 12 */
4585 fputs ("llt", file); /* 2 */
4588 fputs ("lle", file); /* 6 */
4591 fputs ("lgt", file); /* 1 */
4594 fputs ("lge", file); /* 5 */
4602 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
4605 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4606 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
4608 print_operand (file, x, 0);
4612 /* MB value for a PowerPC64 rldic operand. */
4613 val = (GET_CODE (x) == CONST_INT
4614 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
4619 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
4620 if ((val <<= 1) < 0)
4623 #if HOST_BITS_PER_WIDE_INT == 32
4624 if (GET_CODE (x) == CONST_INT && i >= 0)
4625 i += 32; /* zero-extend high-part was all 0's */
4626 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
4628 val = CONST_DOUBLE_LOW (x);
4635 for ( ; i < 64; i++)
4636 if ((val <<= 1) < 0)
4641 fprintf (file, "%d", i + 1);
4645 if (GET_CODE (x) == MEM
4646 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0))
4651 /* Like 'L', for third word of TImode */
4652 if (GET_CODE (x) == REG)
4653 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
4654 else if (GET_CODE (x) == MEM)
4656 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4657 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4658 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
4660 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
4661 if (small_data_operand (x, GET_MODE (x)))
4662 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4663 reg_names[SMALL_DATA_REG]);
4668 /* X is a SYMBOL_REF. Write out the name preceded by a
4669 period and without any trailing data in brackets. Used for function
4670 names. If we are configured for System V (or the embedded ABI) on
4671 the PowerPC, do not emit the period, since those systems do not use
4672 TOCs and the like. */
4673 if (GET_CODE (x) != SYMBOL_REF)
4676 if (XSTR (x, 0)[0] != '.')
4678 switch (DEFAULT_ABI)
4688 case ABI_AIX_NODESC:
4695 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
4697 assemble_name (file, XSTR (x, 0));
4702 /* Like 'L', for last word of TImode. */
4703 if (GET_CODE (x) == REG)
4704 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
4705 else if (GET_CODE (x) == MEM)
4707 if (GET_CODE (XEXP (x, 0)) == PRE_INC
4708 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
4709 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
4711 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
4712 if (small_data_operand (x, GET_MODE (x)))
4713 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4714 reg_names[SMALL_DATA_REG]);
4719 if (GET_CODE (x) == REG)
4720 fprintf (file, "%s", reg_names[REGNO (x)]);
4721 else if (GET_CODE (x) == MEM)
4723 /* We need to handle PRE_INC and PRE_DEC here, since we need to
4724 know the width from the mode. */
4725 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
4726 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
4727 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
4728 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
4729 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
4730 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
4732 output_address (XEXP (x, 0));
4735 output_addr_const (file, x);
4739 output_operand_lossage ("invalid %%xn code");
4743 /* Print the address of an operand. */
4746 print_operand_address (file, x)
4750 if (GET_CODE (x) == REG)
4751 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
4752 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
4753 || GET_CODE (x) == LABEL_REF)
4755 output_addr_const (file, x);
4756 if (small_data_operand (x, GET_MODE (x)))
4757 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
4758 reg_names[SMALL_DATA_REG]);
4759 else if (TARGET_TOC)
4762 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
4764 if (REGNO (XEXP (x, 0)) == 0)
4765 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
4766 reg_names[ REGNO (XEXP (x, 0)) ]);
4768 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
4769 reg_names[ REGNO (XEXP (x, 1)) ]);
4771 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4773 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
4774 fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
4777 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
4778 && CONSTANT_P (XEXP (x, 1)))
4780 output_addr_const (file, XEXP (x, 1));
4781 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
4784 else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
4786 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
4788 rtx contains_minus = XEXP (x, 1);
4792 /* Find the (minus (sym) (toc)) buried in X, and temporarily
4793 turn it into (sym) for output_addr_const. */
4794 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
4795 contains_minus = XEXP (contains_minus, 0);
4797 minus = XEXP (contains_minus, 0);
4798 symref = XEXP (minus, 0);
4799 XEXP (contains_minus, 0) = symref;
4804 name = XSTR (symref, 0);
4805 newname = alloca (strlen (name) + sizeof ("@toc"));
4806 strcpy (newname, name);
4807 strcat (newname, "@toc");
4808 XSTR (symref, 0) = newname;
4810 output_addr_const (file, XEXP (x, 1));
4812 XSTR (symref, 0) = name;
4813 XEXP (contains_minus, 0) = minus;
4816 output_addr_const (file, XEXP (x, 1));
4818 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
4825 rs6000_reverse_condition (mode, code)
4826 enum machine_mode mode;
4829 /* Reversal of FP compares takes care -- an ordered compare
4830 becomes an unordered compare and vice versa. */
4831 if (mode == CCFPmode)
4832 return reverse_condition_maybe_unordered (code);
4834 return reverse_condition (code);
4837 /* Generate a compare for CODE. Return a brand-new rtx that
4838 represents the result of the compare. */
4841 rs6000_generate_compare (code)
4844 enum machine_mode comp_mode;
4847 if (rs6000_compare_fp_p)
4848 comp_mode = CCFPmode;
4849 else if (code == GTU || code == LTU
4850 || code == GEU || code == LEU)
4851 comp_mode = CCUNSmode;
4855 /* First, the compare. */
4856 compare_result = gen_reg_rtx (comp_mode);
4857 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
4858 gen_rtx_COMPARE (comp_mode,
4860 rs6000_compare_op1)));
4862 /* Some kinds of FP comparisons need an OR operation;
4863 except for flag_unsafe_math_optimizations we don't bother. */
4864 if (rs6000_compare_fp_p
4865 && ! flag_unsafe_math_optimizations
4866 && (code == LE || code == GE
4867 || code == UNEQ || code == LTGT
4868 || code == UNGT || code == UNLT))
4870 enum rtx_code or1, or2;
4871 rtx or1_rtx, or2_rtx, compare2_rtx;
4872 rtx or_result = gen_reg_rtx (CCEQmode);
4876 case LE: or1 = LT; or2 = EQ; break;
4877 case GE: or1 = GT; or2 = EQ; break;
4878 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
4879 case LTGT: or1 = LT; or2 = GT; break;
4880 case UNGT: or1 = UNORDERED; or2 = GT; break;
4881 case UNLT: or1 = UNORDERED; or2 = LT; break;
4884 validate_condition_mode (or1, comp_mode);
4885 validate_condition_mode (or2, comp_mode);
4886 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
4887 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
4888 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
4889 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
4891 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
4893 compare_result = or_result;
4897 validate_condition_mode (code, GET_MODE (compare_result));
4899 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
4903 /* Emit the RTL for an sCOND pattern. */
4906 rs6000_emit_sCOND (code, result)
4911 enum machine_mode op_mode;
4913 condition_rtx = rs6000_generate_compare (code);
4915 op_mode = GET_MODE (rs6000_compare_op0);
4916 if (op_mode == VOIDmode)
4917 op_mode = GET_MODE (rs6000_compare_op1);
4919 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
4921 PUT_MODE (condition_rtx, DImode);
4922 convert_move (result, condition_rtx, 0);
4926 PUT_MODE (condition_rtx, SImode);
4927 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
4931 /* Emit a branch of kind CODE to location LOC. */
4934 rs6000_emit_cbranch (code, loc)
4938 rtx condition_rtx, loc_ref;
4940 condition_rtx = rs6000_generate_compare (code);
4941 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
4942 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4943 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
4947 /* Return the string to output a conditional branch to LABEL, which is
4948 the operand number of the label, or -1 if the branch is really a
4951 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
4952 condition code register and its mode specifies what kind of
4955 REVERSED is non-zero if we should reverse the sense of the comparison.
4957 INSN is the insn. */
4960 output_cbranch (op, label, reversed, insn)
4966 static char string[64];
4967 enum rtx_code code = GET_CODE (op);
4968 rtx cc_reg = XEXP (op, 0);
4969 enum machine_mode mode = GET_MODE (cc_reg);
4970 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
4971 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
4972 int really_reversed = reversed ^ need_longbranch;
4978 validate_condition_mode (code, mode);
4980 /* Work out which way this really branches. We could use
4981 reverse_condition_maybe_unordered here always but this
4982 makes the resulting assembler clearer. */
4983 if (really_reversed)
4984 code = rs6000_reverse_condition (mode, code);
4988 /* Not all of these are actually distinct opcodes, but
4989 we distinguish them for clarity of the resulting assembler. */
4991 ccode = "ne"; break;
4993 ccode = "eq"; break;
4995 ccode = "ge"; break;
4996 case GT: case GTU: case UNGT:
4997 ccode = "gt"; break;
4999 ccode = "le"; break;
5000 case LT: case LTU: case UNLT:
5001 ccode = "lt"; break;
5002 case UNORDERED: ccode = "un"; break;
5003 case ORDERED: ccode = "nu"; break;
5004 case UNGE: ccode = "nl"; break;
5005 case UNLE: ccode = "ng"; break;
5010 /* Maybe we have a guess as to how likely the branch is.
5011 The old mnemonics don't have a way to specify this information. */
5012 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
5013 if (note != NULL_RTX)
5015 /* PROB is the difference from 50%. */
5016 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
5018 /* For branches that are very close to 50%, assume not-taken. */
5019 if (abs (prob) > REG_BR_PROB_BASE / 20
5020 && ((prob > 0) ^ need_longbranch))
5029 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
5031 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
5033 /* We need to escape any '%' characters in the reg_names string.
5034 Assume they'd only be the first character... */
5035 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
5037 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
5041 /* If the branch distance was too far, we may have to use an
5042 unconditional branch to go the distance. */
5043 if (need_longbranch)
5044 s += sprintf (s, ",%c$+8\n\tb %s", '%', label);
5046 s += sprintf (s, ",%s", label);
5052 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
5053 operands of the last comparison is nonzero/true, FALSE_COND if it
5054 is zero/false. Return 0 if the hardware has no such operation. */
5057 rs6000_emit_cmove (dest, op, true_cond, false_cond)
5063 enum rtx_code code = GET_CODE (op);
5064 rtx op0 = rs6000_compare_op0;
5065 rtx op1 = rs6000_compare_op1;
5067 enum machine_mode mode = GET_MODE (op0);
5070 /* First, work out if the hardware can do this at all, or
5071 if it's too slow... */
5072 /* If the comparison is an integer one, since we only have fsel
5073 it'll be cheaper to use a branch. */
5074 if (! rs6000_compare_fp_p)
5077 /* Eliminate half of the comparisons by switching operands, this
5078 makes the remaining code simpler. */
5079 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
5080 || code == LTGT || code == LT)
5082 code = reverse_condition_maybe_unordered (code);
5084 true_cond = false_cond;
5088 /* UNEQ and LTGT take four instructions for a comparison with zero,
5089 it'll probably be faster to use a branch here too. */
5093 if (GET_CODE (op1) == CONST_DOUBLE)
5094 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
5096 /* We're going to try to implement comparions by performing
5097 a subtract, then comparing against zero. Unfortunately,
5098 Inf - Inf is NaN which is not zero, and so if we don't
5099 know that the the operand is finite and the comparison
5100 would treat EQ different to UNORDERED, we can't do it. */
5101 if (! flag_unsafe_math_optimizations
5102 && code != GT && code != UNGE
5103 && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1))
5104 /* Constructs of the form (a OP b ? a : b) are safe. */
5105 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
5106 || (! rtx_equal_p (op0, true_cond)
5107 && ! rtx_equal_p (op1, true_cond))))
5109 /* At this point we know we can use fsel. */
5111 /* Reduce the comparison to a comparison against zero. */
5112 temp = gen_reg_rtx (mode);
5113 emit_insn (gen_rtx_SET (VOIDmode, temp,
5114 gen_rtx_MINUS (mode, op0, op1)));
5116 op1 = CONST0_RTX (mode);
5118 /* If we don't care about NaNs we can reduce some of the comparisons
5119 down to faster ones. */
5120 if (flag_unsafe_math_optimizations)
5126 true_cond = false_cond;
5139 /* Now, reduce everything down to a GE. */
5146 temp = gen_reg_rtx (mode);
5147 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5152 temp = gen_reg_rtx (mode);
5153 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0)));
5158 temp = gen_reg_rtx (mode);
5159 emit_insn (gen_rtx_SET (VOIDmode, temp,
5161 gen_rtx_ABS (mode, op0))));
5166 temp = gen_reg_rtx (mode);
5167 emit_insn (gen_rtx_SET (VOIDmode, temp,
5168 gen_rtx_IF_THEN_ELSE (mode,
5169 gen_rtx_GE (VOIDmode,
5171 true_cond, false_cond)));
5173 true_cond = false_cond;
5175 temp = gen_reg_rtx (mode);
5176 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5181 temp = gen_reg_rtx (mode);
5182 emit_insn (gen_rtx_SET (VOIDmode, temp,
5183 gen_rtx_IF_THEN_ELSE (mode,
5184 gen_rtx_GE (VOIDmode,
5186 true_cond, false_cond)));
5188 false_cond = true_cond;
5190 temp = gen_reg_rtx (mode);
5191 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
5199 emit_insn (gen_rtx_SET (VOIDmode, dest,
5200 gen_rtx_IF_THEN_ELSE (mode,
5201 gen_rtx_GE (VOIDmode,
5203 true_cond, false_cond)));
5208 rs6000_emit_minmax (dest, code, op0, op1)
5214 enum machine_mode mode = GET_MODE (op0);
5216 if (code == SMAX || code == UMAX)
5217 target = emit_conditional_move (dest, GE, op0, op1, mode,
5220 target = emit_conditional_move (dest, GE, op0, op1, mode,
5222 if (target == NULL_RTX)
5225 emit_move_insn (dest, target);
5228 /* This page contains routines that are used to determine what the
5229 function prologue and epilogue code will do and write them out. */
5231 /* Return the first fixed-point register that is required to be
5232 saved. 32 if none. */
5235 first_reg_to_save ()
5239 /* Find lowest numbered live register. */
5240 for (first_reg = 13; first_reg <= 31; first_reg++)
5241 if (regs_ever_live[first_reg]
5242 && (! call_used_regs[first_reg]
5243 || (first_reg == PIC_OFFSET_TABLE_REGNUM
5244 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5246 || (DEFAULT_ABI == ABI_DARWIN
5252 /* AIX must save/restore every register that contains a parameter
5253 before/after the .__mcount call plus an additional register
5254 for the static chain, if needed; use registers from 30 down to 22
5256 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
5258 int last_parm_reg, profile_first_reg;
5260 /* Figure out last used parameter register. The proper thing
5261 to do is to walk incoming args of the function. A function
5262 might have live parameter registers even if it has no
5264 for (last_parm_reg = 10;
5265 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
5269 /* Calculate first reg for saving parameter registers
5271 Skip reg 31 which may contain the frame pointer. */
5272 profile_first_reg = (33 - last_parm_reg
5273 - (current_function_needs_context ? 1 : 0));
5275 /* Need to skip another reg to account for R31 being PICBASE
5276 (when flag_pic is set) or R30 being used as the frame
5277 pointer (when flag_pic is not set). */
5278 --profile_first_reg;
5280 /* Do not save frame pointer if no parameters needs to be saved. */
5281 if (profile_first_reg == 31)
5282 profile_first_reg = 32;
5284 if (first_reg > profile_first_reg)
5285 first_reg = profile_first_reg;
5288 /* SVR4 may need one register to preserve the static chain. */
5289 else if (current_function_needs_context)
5291 /* Skip reg 31 which may contain the frame pointer. */
5298 if (flag_pic && current_function_uses_pic_offset_table &&
5299 (first_reg > PIC_OFFSET_TABLE_REGNUM))
5300 return PIC_OFFSET_TABLE_REGNUM;
5306 /* Similar, for FP regs. */
5309 first_fp_reg_to_save ()
5313 /* Find lowest numbered live register. */
5314 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
5315 if (regs_ever_live[first_reg])
5321 /* Calculate the stack information for the current function. This is
5322 complicated by having two separate calling sequences, the AIX calling
5323 sequence and the V.4 calling sequence.
5325 AIX (and Darwin/Mac OS X) stack frames look like:
5327 SP----> +---------------------------------------+
5328 | back chain to caller | 0 0
5329 +---------------------------------------+
5330 | saved CR | 4 8 (8-11)
5331 +---------------------------------------+
5333 +---------------------------------------+
5334 | reserved for compilers | 12 24
5335 +---------------------------------------+
5336 | reserved for binders | 16 32
5337 +---------------------------------------+
5338 | saved TOC pointer | 20 40
5339 +---------------------------------------+
5340 | Parameter save area (P) | 24 48
5341 +---------------------------------------+
5342 | Alloca space (A) | 24+P etc.
5343 +---------------------------------------+
5344 | Local variable space (L) | 24+P+A
5345 +---------------------------------------+
5346 | Float/int conversion temporary (X) | 24+P+A+L
5347 +---------------------------------------+
5348 | Save area for GP registers (G) | 24+P+A+X+L
5349 +---------------------------------------+
5350 | Save area for FP registers (F) | 24+P+A+X+L+G
5351 +---------------------------------------+
5352 old SP->| back chain to caller's caller |
5353 +---------------------------------------+
5355 The required alignment for AIX configurations is two words (i.e., 8
5359 V.4 stack frames look like:
5361 SP----> +---------------------------------------+
5362 | back chain to caller | 0
5363 +---------------------------------------+
5364 | caller's saved LR | 4
5365 +---------------------------------------+
5366 | Parameter save area (P) | 8
5367 +---------------------------------------+
5368 | Alloca space (A) | 8+P
5369 +---------------------------------------+
5370 | Varargs save area (V) | 8+P+A
5371 +---------------------------------------+
5372 | Local variable space (L) | 8+P+A+V
5373 +---------------------------------------+
5374 | Float/int conversion temporary (X) | 8+P+A+V+L
5375 +---------------------------------------+
5376 | saved CR (C) | 8+P+A+V+L+X
5377 +---------------------------------------+
5378 | Save area for GP registers (G) | 8+P+A+V+L+X+C
5379 +---------------------------------------+
5380 | Save area for FP registers (F) | 8+P+A+V+L+X+C+G
5381 +---------------------------------------+
5382 old SP->| back chain to caller's caller |
5383 +---------------------------------------+
5385 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
5386 given. (But note below and in sysv4.h that we require only 8 and
5387 may round up the size of our stack frame anyways. The historical
5388 reason is early versions of powerpc-linux which didn't properly
5389 align the stack at program startup. A happy side-effect is that
5390 -mno-eabi libraries can be used with -meabi programs.)
5392 The EABI configuration defaults to the V.4 layout, unless
5393 -mcall-aix is used, in which case the AIX layout is used. However,
5394 the stack alignment requirements may differ. If -mno-eabi is not
5395 given, the required stack alignment is 8 bytes; if -mno-eabi is
5396 given, the required alignment is 16 bytes. (But see V.4 comment
5399 #ifndef ABI_STACK_BOUNDARY
5400 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
5404 rs6000_stack_info ()
5406 static rs6000_stack_t info, zero_info;
5407 rs6000_stack_t *info_ptr = &info;
5408 int reg_size = TARGET_POWERPC64 ? 8 : 4;
5409 enum rs6000_abi abi;
5413 /* Zero all fields portably. */
5416 /* Select which calling sequence. */
5417 info_ptr->abi = abi = DEFAULT_ABI;
5419 /* Calculate which registers need to be saved & save area size. */
5420 info_ptr->first_gp_reg_save = first_reg_to_save ();
5421 /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM,
5422 even if it currently looks like we won't. */
5423 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
5425 && (abi == ABI_V4 || abi == ABI_SOLARIS))
5428 && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM)
5429 info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM);
5431 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
5433 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
5434 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
5436 /* Does this function call anything? */
5437 info_ptr->calls_p = (! current_function_is_leaf
5438 || cfun->machine->ra_needs_full_frame);
5440 /* Determine if we need to save the link register. */
5441 if (rs6000_ra_ever_killed ()
5442 || (DEFAULT_ABI == ABI_AIX && profile_flag)
5443 #ifdef TARGET_RELOCATABLE
5444 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
5446 || (info_ptr->first_fp_reg_save != 64
5447 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
5448 || (abi == ABI_V4 && current_function_calls_alloca)
5449 || (abi == ABI_SOLARIS && current_function_calls_alloca)
5450 || (DEFAULT_ABI == ABI_DARWIN
5452 && current_function_uses_pic_offset_table)
5453 || info_ptr->calls_p)
5455 info_ptr->lr_save_p = 1;
5456 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
5459 /* Determine if we need to save the condition code registers. */
5460 if (regs_ever_live[CR2_REGNO]
5461 || regs_ever_live[CR3_REGNO]
5462 || regs_ever_live[CR4_REGNO])
5464 info_ptr->cr_save_p = 1;
5465 if (abi == ABI_V4 || abi == ABI_SOLARIS)
5466 info_ptr->cr_size = reg_size;
5469 /* If the current function calls __builtin_eh_return, then we need
5470 to allocate stack space for registers that will hold data for
5471 the exception handler. */
5472 if (current_function_calls_eh_return)
5475 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
5477 ehrd_size = i * UNITS_PER_WORD;
5482 /* Determine various sizes. */
5483 info_ptr->reg_size = reg_size;
5484 info_ptr->fixed_size = RS6000_SAVE_AREA;
5485 info_ptr->varargs_size = RS6000_VARARGS_AREA;
5486 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
5487 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
5489 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
5494 + info_ptr->toc_size, 8);
5495 if (DEFAULT_ABI == ABI_DARWIN)
5496 info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16);
5498 /* Calculate the offsets. */
5506 case ABI_AIX_NODESC:
5508 info_ptr->fp_save_offset = - info_ptr->fp_size;
5509 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
5510 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
5511 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
5512 info_ptr->lr_save_offset = 2*reg_size;
5517 info_ptr->fp_save_offset = - info_ptr->fp_size;
5518 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
5519 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
5520 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
5521 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
5522 info_ptr->lr_save_offset = reg_size;
5526 total_raw_size = (info_ptr->vars_size
5527 + info_ptr->parm_size
5528 + info_ptr->save_size
5529 + info_ptr->varargs_size
5530 + info_ptr->fixed_size);
5532 info_ptr->total_size =
5533 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
5535 /* Determine if we need to allocate any stack frame:
5537 For AIX we need to push the stack if a frame pointer is needed
5538 (because the stack might be dynamically adjusted), if we are
5539 debugging, if we make calls, or if the sum of fp_save, gp_save,
5540 and local variables are more than the space needed to save all
5541 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
5542 + 18*8 = 288 (GPR13 reserved).
5544 For V.4 we don't have the stack cushion that AIX uses, but assume
5545 that the debugger can handle stackless frames. */
5547 if (info_ptr->calls_p)
5548 info_ptr->push_p = 1;
5550 else if (abi == ABI_V4 || abi == ABI_SOLARIS)
5551 info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
5552 || info_ptr->calls_p);
5555 info_ptr->push_p = (frame_pointer_needed
5556 || (abi != ABI_DARWIN && write_symbols != NO_DEBUG)
5557 || ((total_raw_size - info_ptr->fixed_size)
5558 > (TARGET_32BIT ? 220 : 288)));
5560 /* Zero offsets if we're not saving those registers. */
5561 if (info_ptr->fp_size == 0)
5562 info_ptr->fp_save_offset = 0;
5564 if (info_ptr->gp_size == 0)
5565 info_ptr->gp_save_offset = 0;
5567 if (! info_ptr->lr_save_p)
5568 info_ptr->lr_save_offset = 0;
5570 if (! info_ptr->cr_save_p)
5571 info_ptr->cr_save_offset = 0;
5573 if (! info_ptr->toc_save_p)
5574 info_ptr->toc_save_offset = 0;
5580 debug_stack_info (info)
5581 rs6000_stack_t *info;
5583 const char *abi_string;
5586 info = rs6000_stack_info ();
5588 fprintf (stderr, "\nStack information for function %s:\n",
5589 ((current_function_decl && DECL_NAME (current_function_decl))
5590 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
5595 default: abi_string = "Unknown"; break;
5596 case ABI_NONE: abi_string = "NONE"; break;
5597 case ABI_AIX: abi_string = "AIX"; break;
5598 case ABI_AIX_NODESC: abi_string = "AIX"; break;
5599 case ABI_DARWIN: abi_string = "Darwin"; break;
5600 case ABI_V4: abi_string = "V.4"; break;
5601 case ABI_SOLARIS: abi_string = "Solaris"; break;
5604 fprintf (stderr, "\tABI = %5s\n", abi_string);
5606 if (info->first_gp_reg_save != 32)
5607 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
5609 if (info->first_fp_reg_save != 64)
5610 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
5612 if (info->lr_save_p)
5613 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
5615 if (info->cr_save_p)
5616 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
5618 if (info->toc_save_p)
5619 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
5622 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
5625 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
5627 if (info->gp_save_offset)
5628 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
5630 if (info->fp_save_offset)
5631 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
5633 if (info->lr_save_offset)
5634 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
5636 if (info->cr_save_offset)
5637 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
5639 if (info->toc_save_offset)
5640 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
5642 if (info->varargs_save_offset)
5643 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
5645 if (info->total_size)
5646 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
5648 if (info->varargs_size)
5649 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
5651 if (info->vars_size)
5652 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
5654 if (info->parm_size)
5655 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
5657 if (info->fixed_size)
5658 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
5661 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
5664 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
5667 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
5670 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
5673 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
5675 if (info->save_size)
5676 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
5678 if (info->reg_size != 4)
5679 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
5681 fprintf (stderr, "\n");
5685 rs6000_return_addr (count, frame)
5689 /* Currently we don't optimize very well between prolog and body
5690 code and for PIC code the code can be actually quite bad, so
5691 don't try to be too clever here. */
5694 || DEFAULT_ABI == ABI_AIX
5695 || DEFAULT_ABI == ABI_AIX_NODESC)
5697 cfun->machine->ra_needs_full_frame = 1;
5704 plus_constant (copy_to_reg
5705 (gen_rtx_MEM (Pmode,
5706 memory_address (Pmode, frame))),
5707 RETURN_ADDRESS_OFFSET)));
5710 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
5714 rs6000_ra_ever_killed ()
5718 #ifdef ASM_OUTPUT_MI_THUNK
5719 if (current_function_is_thunk)
5722 if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM)
5723 || cfun->machine->ra_needs_full_frame)
5724 return regs_ever_live[LINK_REGISTER_REGNUM];
5726 push_topmost_sequence ();
5728 pop_topmost_sequence ();
5730 return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
5734 /* Add a REG_MAYBE_DEAD note to the insn. */
5736 rs6000_maybe_dead (insn)
5739 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5744 /* Emit instructions needed to load the TOC register.
5745 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
5746 a constant pool; or for SVR4 -fpic. */
5749 rs6000_emit_load_toc_table (fromprolog)
5753 dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5755 if (TARGET_ELF && DEFAULT_ABI != ABI_AIX)
5757 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5760 rtx temp = (fromprolog
5761 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
5762 : gen_reg_rtx (Pmode));
5763 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp)));
5764 rs6000_maybe_dead (emit_move_insn (dest, temp));
5766 else if (flag_pic == 2)
5769 rtx tempLR = (fromprolog
5770 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
5771 : gen_reg_rtx (Pmode));
5772 rtx temp0 = (fromprolog
5773 ? gen_rtx_REG (Pmode, 0)
5774 : gen_reg_rtx (Pmode));
5777 /* possibly create the toc section */
5778 if (! toc_initialized)
5781 function_section (current_function_decl);
5788 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
5789 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5791 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
5792 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5794 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
5796 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
5797 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
5804 static int reload_toc_labelno = 0;
5806 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
5808 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
5809 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5811 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR,
5814 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
5815 rs6000_maybe_dead (emit_move_insn (temp0,
5816 gen_rtx_MEM (Pmode, dest)));
5818 rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest)));
5820 else if (flag_pic == 0 && TARGET_MINIMAL_TOC)
5822 /* This is for AIX code running in non-PIC ELF. */
5825 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
5826 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
5828 rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym)));
5829 rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym)));
5837 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest)));
5839 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest)));
5844 get_TOC_alias_set ()
5846 static int set = -1;
5848 set = new_alias_set ();
5852 /* This retuns nonzero if the current function uses the TOC. This is
5853 determined by the presence of (unspec ... 7), which is generated by
5854 the various load_toc_* patterns. */
5861 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5864 rtx pat = PATTERN (insn);
5867 if (GET_CODE (pat) == PARALLEL)
5868 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
5869 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC
5870 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7)
5877 create_TOC_reference (symbol)
5880 return gen_rtx_PLUS (Pmode,
5881 gen_rtx_REG (Pmode, TOC_REGISTER),
5882 gen_rtx_CONST (Pmode,
5883 gen_rtx_MINUS (Pmode, symbol,
5884 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
5888 /* __throw will restore its own return address to be the same as the
5889 return address of the function that the throw is being made to.
5890 This is unfortunate, because we want to check the original
5891 return address to see if we need to restore the TOC.
5892 So we have to squirrel it away here.
5893 This is used only in compiling __throw and __rethrow.
5895 Most of this code should be removed by CSE. */
5896 static rtx insn_after_throw;
5898 /* This does the saving... */
5900 rs6000_aix_emit_builtin_unwind_init ()
5903 rtx stack_top = gen_reg_rtx (Pmode);
5904 rtx opcode_addr = gen_reg_rtx (Pmode);
5906 insn_after_throw = gen_reg_rtx (SImode);
5908 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5909 emit_move_insn (stack_top, mem);
5911 mem = gen_rtx_MEM (Pmode,
5912 gen_rtx_PLUS (Pmode, stack_top,
5913 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
5914 emit_move_insn (opcode_addr, mem);
5915 emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr));
5918 /* Emit insns to _restore_ the TOC register, at runtime (specifically
5919 in _eh.o). Only used on AIX.
5921 The idea is that on AIX, function calls look like this:
5922 bl somefunction-trampoline
5926 somefunction-trampoline:
5928 ... load function address in the count register ...
5930 or like this, if the linker determines that this is not a cross-module call
5931 and so the TOC need not be restored:
5934 or like this, if the compiler could determine that this is not a
5937 now, the tricky bit here is that register 2 is saved and restored
5938 by the _linker_, so we can't readily generate debugging information
5939 for it. So we need to go back up the call chain looking at the
5940 insns at return addresses to see which calls saved the TOC register
5941 and so see where it gets restored from.
5943 Oh, and all this gets done in RTL inside the eh_epilogue pattern,
5944 just before the actual epilogue.
5946 On the bright side, this incurs no space or time overhead unless an
5947 exception is thrown, except for the extra code in libgcc.a.
5949 The parameter STACKSIZE is a register containing (at runtime)
5950 the amount to be popped off the stack in addition to the stack frame
5951 of this routine (which will be __throw or __rethrow, and so is
5952 guaranteed to have a stack frame). */
5955 rs6000_emit_eh_toc_restore (stacksize)
5959 rtx bottom_of_stack = gen_reg_rtx (Pmode);
5960 rtx tocompare = gen_reg_rtx (SImode);
5961 rtx opcode = gen_reg_rtx (SImode);
5962 rtx opcode_addr = gen_reg_rtx (Pmode);
5964 rtx loop_start = gen_label_rtx ();
5965 rtx no_toc_restore_needed = gen_label_rtx ();
5966 rtx loop_exit = gen_label_rtx ();
5968 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5969 set_mem_alias_set (mem, rs6000_sr_alias_set);
5970 emit_move_insn (bottom_of_stack, mem);
5972 top_of_stack = expand_binop (Pmode, add_optab,
5973 bottom_of_stack, stacksize,
5974 NULL_RTX, 1, OPTAB_WIDEN);
5976 emit_move_insn (tocompare,
5977 GEN_INT (trunc_int_for_mode (TARGET_32BIT
5979 : 0xE8410028, SImode)));
5981 if (insn_after_throw == NULL_RTX)
5983 emit_move_insn (opcode, insn_after_throw);
5985 emit_note (NULL, NOTE_INSN_LOOP_BEG);
5986 emit_label (loop_start);
5988 do_compare_rtx_and_jump (opcode, tocompare, NE, 1,
5989 SImode, NULL_RTX, 0, NULL_RTX,
5990 no_toc_restore_needed);
5992 mem = gen_rtx_MEM (Pmode,
5993 gen_rtx_PLUS (Pmode, bottom_of_stack,
5994 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
5995 emit_move_insn (gen_rtx_REG (Pmode, 2), mem);
5997 emit_label (no_toc_restore_needed);
5998 do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1,
5999 Pmode, NULL_RTX, 0, NULL_RTX,
6002 mem = gen_rtx_MEM (Pmode, bottom_of_stack);
6003 set_mem_alias_set (mem, rs6000_sr_alias_set);
6004 emit_move_insn (bottom_of_stack, mem);
6006 mem = gen_rtx_MEM (Pmode,
6007 gen_rtx_PLUS (Pmode, bottom_of_stack,
6008 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
6009 emit_move_insn (opcode_addr, mem);
6010 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
6012 emit_note (NULL, NOTE_INSN_LOOP_CONT);
6013 emit_jump (loop_start);
6014 emit_note (NULL, NOTE_INSN_LOOP_END);
6015 emit_label (loop_exit);
6017 #endif /* TARGET_AIX */
6019 /* This ties together stack memory (MEM with an alias set of
6020 rs6000_sr_alias_set) and the change to the stack pointer. */
6023 rs6000_emit_stack_tie ()
6025 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
6027 set_mem_alias_set (mem, rs6000_sr_alias_set);
6028 emit_insn (gen_stack_tie (mem));
6031 /* Emit the correct code for allocating stack space, as insns.
6032 If COPY_R12, make sure a copy of the old frame is left in r12.
6033 The generated code may use hard register 0 as a temporary. */
6036 rs6000_emit_allocate_stack (size, copy_r12)
6041 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
6042 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
6043 rtx todec = GEN_INT (-size);
6045 if (current_function_limit_stack)
6047 if (REG_P (stack_limit_rtx)
6048 && REGNO (stack_limit_rtx) > 1
6049 && REGNO (stack_limit_rtx) <= 31)
6051 emit_insn (Pmode == SImode
6052 ? gen_addsi3 (tmp_reg,
6055 : gen_adddi3 (tmp_reg,
6059 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
6062 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
6064 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
6066 rtx toload = gen_rtx_CONST (VOIDmode,
6067 gen_rtx_PLUS (Pmode,
6071 emit_insn (gen_elf_high (tmp_reg, toload));
6072 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
6073 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
6077 warning ("stack limit expression is not supported");
6080 if (copy_r12 || ! TARGET_UPDATE)
6081 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
6087 /* Need a note here so that try_split doesn't get confused. */
6088 if (get_last_insn() == NULL_RTX)
6089 emit_note (0, NOTE_INSN_DELETED);
6090 insn = emit_move_insn (tmp_reg, todec);
6091 try_split (PATTERN (insn), insn, 0);
6095 if (Pmode == SImode)
6096 insn = emit_insn (gen_movsi_update (stack_reg, stack_reg,
6099 insn = emit_insn (gen_movdi_update (stack_reg, stack_reg,
6104 if (Pmode == SImode)
6105 insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec));
6107 insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec));
6108 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
6109 gen_rtx_REG (Pmode, 12));
6112 RTX_FRAME_RELATED_P (insn) = 1;
6114 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6115 gen_rtx_SET (VOIDmode, stack_reg,
6116 gen_rtx_PLUS (Pmode, stack_reg,
6121 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
6122 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
6123 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
6124 deduce these equivalences by itself so it wasn't necessary to hold
6125 its hand so much. */
6128 rs6000_frame_related (insn, reg, val, reg2, rreg)
6137 real = copy_rtx (PATTERN (insn));
6139 real = replace_rtx (real, reg,
6140 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
6141 STACK_POINTER_REGNUM),
6144 /* We expect that 'real' is either a SET or a PARALLEL containing
6145 SETs (and possibly other stuff). In a PARALLEL, all the SETs
6146 are important so they all have to be marked RTX_FRAME_RELATED_P. */
6148 if (GET_CODE (real) == SET)
6152 temp = simplify_rtx (SET_SRC (set));
6154 SET_SRC (set) = temp;
6155 temp = simplify_rtx (SET_DEST (set));
6157 SET_DEST (set) = temp;
6158 if (GET_CODE (SET_DEST (set)) == MEM)
6160 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
6162 XEXP (SET_DEST (set), 0) = temp;
6165 else if (GET_CODE (real) == PARALLEL)
6168 for (i = 0; i < XVECLEN (real, 0); i++)
6169 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
6171 rtx set = XVECEXP (real, 0, i);
6173 temp = simplify_rtx (SET_SRC (set));
6175 SET_SRC (set) = temp;
6176 temp = simplify_rtx (SET_DEST (set));
6178 SET_DEST (set) = temp;
6179 if (GET_CODE (SET_DEST (set)) == MEM)
6181 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
6183 XEXP (SET_DEST (set), 0) = temp;
6185 RTX_FRAME_RELATED_P (set) = 1;
6191 if (reg2 != NULL_RTX)
6192 real = replace_rtx (real, reg2, rreg);
6194 RTX_FRAME_RELATED_P (insn) = 1;
6195 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6200 /* Emit function prologue as insns. */
6203 rs6000_emit_prologue ()
6205 rs6000_stack_t *info = rs6000_stack_info ();
6206 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
6207 int reg_size = TARGET_POWERPC64 ? 8 : 4;
6208 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
6209 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
6210 rtx frame_reg_rtx = sp_reg_rtx;
6211 rtx cr_save_rtx = NULL;
6213 int saving_FPRs_inline;
6214 int using_store_multiple;
6215 HOST_WIDE_INT sp_offset = 0;
6217 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
6218 && info->first_gp_reg_save < 31);
6219 saving_FPRs_inline = (info->first_fp_reg_save == 64
6220 || FP_SAVE_INLINE (info->first_fp_reg_save));
6222 /* For V.4, update stack before we do any saving and set back pointer. */
6223 if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
6225 if (info->total_size < 32767)
6226 sp_offset = info->total_size;
6228 frame_reg_rtx = frame_ptr_rtx;
6229 rs6000_emit_allocate_stack (info->total_size,
6230 (frame_reg_rtx != sp_reg_rtx
6233 || info->first_fp_reg_save < 64
6234 || info->first_gp_reg_save < 32
6236 if (frame_reg_rtx != sp_reg_rtx)
6237 rs6000_emit_stack_tie ();
6240 /* If we use the link register, get it into r0. */
6241 if (info->lr_save_p)
6242 emit_move_insn (gen_rtx_REG (Pmode, 0),
6243 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6245 /* If we need to save CR, put it into r12. */
6246 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
6248 cr_save_rtx = gen_rtx_REG (SImode, 12);
6249 emit_insn (gen_movesi_from_cr (cr_save_rtx));
6252 /* Do any required saving of fpr's. If only one or two to save, do
6253 it ourselves. Otherwise, call function. */
6254 if (saving_FPRs_inline)
6257 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6258 if ((regs_ever_live[info->first_fp_reg_save+i]
6259 && ! call_used_regs[info->first_fp_reg_save+i]))
6262 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
6263 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6264 GEN_INT (info->fp_save_offset
6267 mem = gen_rtx_MEM (DFmode, addr);
6268 set_mem_alias_set (mem, rs6000_sr_alias_set);
6270 insn = emit_move_insn (mem, reg);
6271 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6272 NULL_RTX, NULL_RTX);
6275 else if (info->first_fp_reg_save != 64)
6279 const char *alloc_rname;
6281 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
6283 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
6285 LINK_REGISTER_REGNUM));
6286 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
6287 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
6288 alloc_rname = ggc_strdup (rname);
6289 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
6290 gen_rtx_SYMBOL_REF (Pmode,
6292 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6295 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
6296 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6297 GEN_INT (info->fp_save_offset
6298 + sp_offset + 8*i));
6299 mem = gen_rtx_MEM (DFmode, addr);
6300 set_mem_alias_set (mem, rs6000_sr_alias_set);
6302 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
6304 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6305 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6306 NULL_RTX, NULL_RTX);
6309 /* Save GPRs. This is done as a PARALLEL if we are using
6310 the store-multiple instructions. */
6311 if (using_store_multiple)
6315 p = rtvec_alloc (32 - info->first_gp_reg_save);
6316 dwarfp = rtvec_alloc (32 - info->first_gp_reg_save);
6317 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6320 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
6321 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6322 GEN_INT (info->gp_save_offset
6325 mem = gen_rtx_MEM (reg_mode, addr);
6326 set_mem_alias_set (mem, rs6000_sr_alias_set);
6328 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
6330 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6331 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6332 NULL_RTX, NULL_RTX);
6337 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6338 if ((regs_ever_live[info->first_gp_reg_save+i]
6339 && ! call_used_regs[info->first_gp_reg_save+i])
6340 || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM
6341 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6343 || (DEFAULT_ABI == ABI_DARWIN
6347 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
6348 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6349 GEN_INT (info->gp_save_offset
6352 mem = gen_rtx_MEM (reg_mode, addr);
6353 set_mem_alias_set (mem, rs6000_sr_alias_set);
6355 insn = emit_move_insn (mem, reg);
6356 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6357 NULL_RTX, NULL_RTX);
6361 /* ??? There's no need to emit actual instructions here, but it's the
6362 easiest way to get the frame unwind information emitted. */
6363 if (current_function_calls_eh_return)
6365 unsigned int i, regno;
6371 regno = EH_RETURN_DATA_REGNO (i);
6372 if (regno == INVALID_REGNUM)
6375 reg = gen_rtx_REG (reg_mode, regno);
6376 addr = plus_constant (frame_reg_rtx,
6377 info->ehrd_offset + sp_offset
6378 + reg_size * (int) i);
6379 mem = gen_rtx_MEM (reg_mode, addr);
6380 set_mem_alias_set (mem, rs6000_sr_alias_set);
6382 insn = emit_move_insn (mem, reg);
6383 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6384 NULL_RTX, NULL_RTX);
6388 /* Save lr if we used it. */
6389 if (info->lr_save_p)
6391 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6392 GEN_INT (info->lr_save_offset + sp_offset));
6393 rtx reg = gen_rtx_REG (Pmode, 0);
6394 rtx mem = gen_rtx_MEM (Pmode, addr);
6395 /* This should not be of rs6000_sr_alias_set, because of
6396 __builtin_return_address. */
6398 insn = emit_move_insn (mem, reg);
6399 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6400 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6403 /* Save CR if we use any that must be preserved. */
6404 if (info->cr_save_p)
6406 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6407 GEN_INT (info->cr_save_offset + sp_offset));
6408 rtx mem = gen_rtx_MEM (SImode, addr);
6410 set_mem_alias_set (mem, rs6000_sr_alias_set);
6412 /* If r12 was used to hold the original sp, copy cr into r0 now
6414 if (REGNO (frame_reg_rtx) == 12)
6416 cr_save_rtx = gen_rtx_REG (SImode, 0);
6417 emit_insn (gen_movesi_from_cr (cr_save_rtx));
6419 insn = emit_move_insn (mem, cr_save_rtx);
6421 /* Now, there's no way that dwarf2out_frame_debug_expr is going
6422 to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's
6423 OK. All we have to do is specify that _one_ condition code
6424 register is saved in this stack slot. The thrower's epilogue
6425 will then restore all the call-saved registers.
6426 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
6427 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
6428 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
6431 /* Update stack and set back pointer unless this is V.4,
6432 for which it was done previously. */
6433 if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
6434 rs6000_emit_allocate_stack (info->total_size, FALSE);
6436 /* Set frame pointer, if needed. */
6437 if (frame_pointer_needed)
6439 insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM),
6441 RTX_FRAME_RELATED_P (insn) = 1;
6444 /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
6445 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
6446 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6447 && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]))
6449 /* If emit_load_toc_table will use the link register, we need to save
6450 it. We use R11 for this purpose because emit_load_toc_table
6451 can use register 0. This allows us to use a plain 'blr' to return
6452 from the procedure more often. */
6453 int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0
6454 && ! info->lr_save_p
6455 && EXIT_BLOCK_PTR->pred != NULL);
6456 if (save_LR_around_toc_setup)
6457 emit_move_insn (gen_rtx_REG (Pmode, 11),
6458 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
6460 rs6000_emit_load_toc_table (TRUE);
6462 if (save_LR_around_toc_setup)
6463 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
6464 gen_rtx_REG (Pmode, 11));
6467 if (DEFAULT_ABI == ABI_DARWIN
6468 && flag_pic && current_function_uses_pic_offset_table)
6470 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
6472 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest)));
6475 emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM),
6476 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
6480 /* Write function prologue. */
6483 rs6000_output_function_prologue (file, size)
6485 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6487 rs6000_stack_t *info = rs6000_stack_info ();
6489 if (TARGET_DEBUG_STACK)
6490 debug_stack_info (info);
6492 /* Write .extern for any function we will call to save and restore
6494 if (info->first_fp_reg_save < 64
6495 && !FP_SAVE_INLINE (info->first_fp_reg_save))
6496 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
6497 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
6498 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
6501 /* Write .extern for AIX common mode routines, if needed. */
6502 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
6504 fputs ("\t.extern __mulh\n", file);
6505 fputs ("\t.extern __mull\n", file);
6506 fputs ("\t.extern __divss\n", file);
6507 fputs ("\t.extern __divus\n", file);
6508 fputs ("\t.extern __quoss\n", file);
6509 fputs ("\t.extern __quous\n", file);
6510 common_mode_defined = 1;
6513 if (! HAVE_prologue)
6517 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
6518 the "toplevel" insn chain. */
6519 emit_note (0, NOTE_INSN_DELETED);
6520 rs6000_emit_prologue ();
6521 emit_note (0, NOTE_INSN_DELETED);
6523 if (TARGET_DEBUG_STACK)
6524 debug_rtx_list (get_insns (), 100);
6525 final (get_insns (), file, FALSE, FALSE);
6529 rs6000_pic_labelno++;
6532 /* Emit function epilogue as insns.
6534 At present, dwarf2out_frame_debug_expr doesn't understand
6535 register restores, so we don't bother setting RTX_FRAME_RELATED_P
6536 anywhere in the epilogue. Most of the insns below would in any case
6537 need special notes to explain where r11 is in relation to the stack. */
6540 rs6000_emit_epilogue (sibcall)
6543 rs6000_stack_t *info;
6544 int restoring_FPRs_inline;
6545 int using_load_multiple;
6546 int using_mfcr_multiple;
6547 int use_backchain_to_restore_sp;
6549 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
6550 rtx frame_reg_rtx = sp_reg_rtx;
6551 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
6552 int reg_size = TARGET_POWERPC64 ? 8 : 4;
6555 info = rs6000_stack_info ();
6556 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
6557 && info->first_gp_reg_save < 31);
6558 restoring_FPRs_inline = (sibcall
6559 || current_function_calls_eh_return
6560 || info->first_fp_reg_save == 64
6561 || FP_SAVE_INLINE (info->first_fp_reg_save));
6562 use_backchain_to_restore_sp = (frame_pointer_needed
6563 || current_function_calls_alloca
6564 || info->total_size > 32767);
6565 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
6566 || rs6000_cpu == PROCESSOR_PPC603
6567 || rs6000_cpu == PROCESSOR_PPC750
6570 /* If we have a frame pointer, a call to alloca, or a large stack
6571 frame, restore the old stack pointer using the backchain. Otherwise,
6572 we know what size to update it with. */
6573 if (use_backchain_to_restore_sp)
6575 /* Under V.4, don't reset the stack pointer until after we're done
6576 loading the saved registers. */
6577 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6578 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
6580 emit_move_insn (frame_reg_rtx,
6581 gen_rtx_MEM (Pmode, sp_reg_rtx));
6584 else if (info->push_p)
6586 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6587 sp_offset = info->total_size;
6590 emit_insn (TARGET_32BIT
6591 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
6592 GEN_INT (info->total_size))
6593 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
6594 GEN_INT (info->total_size)));
6598 /* Get the old lr if we saved it. */
6599 if (info->lr_save_p)
6601 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6602 GEN_INT (info->lr_save_offset + sp_offset));
6603 rtx mem = gen_rtx_MEM (Pmode, addr);
6605 set_mem_alias_set (mem, rs6000_sr_alias_set);
6607 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
6610 /* Get the old cr if we saved it. */
6611 if (info->cr_save_p)
6613 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6614 GEN_INT (info->cr_save_offset + sp_offset));
6615 rtx mem = gen_rtx_MEM (SImode, addr);
6617 set_mem_alias_set (mem, rs6000_sr_alias_set);
6619 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
6622 /* Set LR here to try to overlap restores below. */
6623 if (info->lr_save_p)
6624 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
6625 gen_rtx_REG (Pmode, 0));
6627 /* Load exception handler data registers, if needed. */
6628 if (current_function_calls_eh_return)
6630 unsigned int i, regno;
6636 regno = EH_RETURN_DATA_REGNO (i);
6637 if (regno == INVALID_REGNUM)
6640 addr = plus_constant (frame_reg_rtx,
6641 info->ehrd_offset + sp_offset
6642 + reg_size * (int) i);
6643 mem = gen_rtx_MEM (reg_mode, addr);
6644 set_mem_alias_set (mem, rs6000_sr_alias_set);
6646 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
6650 /* Restore GPRs. This is done as a PARALLEL if we are using
6651 the load-multiple instructions. */
6652 if (using_load_multiple)
6655 p = rtvec_alloc (32 - info->first_gp_reg_save);
6656 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6658 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6659 GEN_INT (info->gp_save_offset
6662 rtx mem = gen_rtx_MEM (reg_mode, addr);
6664 set_mem_alias_set (mem, rs6000_sr_alias_set);
6667 gen_rtx_SET (VOIDmode,
6668 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
6671 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6674 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6675 if ((regs_ever_live[info->first_gp_reg_save+i]
6676 && ! call_used_regs[info->first_gp_reg_save+i])
6677 || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM
6678 && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6680 || (DEFAULT_ABI == ABI_DARWIN
6683 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6684 GEN_INT (info->gp_save_offset
6687 rtx mem = gen_rtx_MEM (reg_mode, addr);
6689 set_mem_alias_set (mem, rs6000_sr_alias_set);
6691 emit_move_insn (gen_rtx_REG (reg_mode,
6692 info->first_gp_reg_save + i),
6696 /* Restore fpr's if we need to do it without calling a function. */
6697 if (restoring_FPRs_inline)
6698 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6699 if ((regs_ever_live[info->first_fp_reg_save+i]
6700 && ! call_used_regs[info->first_fp_reg_save+i]))
6703 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
6704 GEN_INT (info->fp_save_offset
6707 mem = gen_rtx_MEM (DFmode, addr);
6708 set_mem_alias_set (mem, rs6000_sr_alias_set);
6710 emit_move_insn (gen_rtx_REG (DFmode,
6711 info->first_fp_reg_save + i),
6715 /* If we saved cr, restore it here. Just those that were used. */
6716 if (info->cr_save_p)
6718 rtx r12_rtx = gen_rtx_REG (SImode, 12);
6721 if (using_mfcr_multiple)
6723 for (i = 0; i < 8; i++)
6724 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6730 if (using_mfcr_multiple && count > 1)
6735 p = rtvec_alloc (count);
6738 for (i = 0; i < 8; i++)
6739 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6741 rtvec r = rtvec_alloc (2);
6742 RTVEC_ELT (r, 0) = r12_rtx;
6743 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
6744 RTVEC_ELT (p, ndx) =
6745 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
6746 gen_rtx_UNSPEC (CCmode, r, 20));
6749 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
6754 for (i = 0; i < 8; i++)
6755 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
6757 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
6763 /* If this is V.4, unwind the stack pointer after all of the loads
6764 have been done. We need to emit a block here so that sched
6765 doesn't decide to move the sp change before the register restores
6766 (which may not have any obvious dependency on the stack). This
6767 doesn't hurt performance, because there is no scheduling that can
6768 be done after this point. */
6769 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
6771 if (frame_reg_rtx != sp_reg_rtx)
6772 rs6000_emit_stack_tie ();
6774 if (use_backchain_to_restore_sp)
6776 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
6778 else if (sp_offset != 0)
6780 emit_insn (Pmode == SImode
6781 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
6782 GEN_INT (sp_offset))
6783 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
6784 GEN_INT (sp_offset)));
6788 if (current_function_calls_eh_return)
6790 rtx sa = EH_RETURN_STACKADJ_RTX;
6791 emit_insn (Pmode == SImode
6792 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
6793 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
6799 if (! restoring_FPRs_inline)
6800 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
6802 p = rtvec_alloc (2);
6804 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
6805 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
6807 LINK_REGISTER_REGNUM));
6809 /* If we have to restore more than two FP registers, branch to the
6810 restore function. It will return to our caller. */
6811 if (! restoring_FPRs_inline)
6815 const char *alloc_rname;
6817 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
6818 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
6819 alloc_rname = ggc_strdup (rname);
6820 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
6821 gen_rtx_SYMBOL_REF (Pmode,
6824 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
6827 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
6828 GEN_INT (info->fp_save_offset + 8*i));
6829 mem = gen_rtx_MEM (DFmode, addr);
6830 set_mem_alias_set (mem, rs6000_sr_alias_set);
6832 RTVEC_ELT (p, i+3) =
6833 gen_rtx_SET (VOIDmode,
6834 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
6839 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
6843 /* Write function epilogue. */
6846 rs6000_output_function_epilogue (file, size)
6848 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6850 rs6000_stack_t *info = rs6000_stack_info ();
6852 if (! HAVE_epilogue)
6854 rtx insn = get_last_insn ();
6855 /* If the last insn was a BARRIER, we don't have to write anything except
6857 if (GET_CODE (insn) == NOTE)
6858 insn = prev_nonnote_insn (insn);
6859 if (insn == 0 || GET_CODE (insn) != BARRIER)
6861 /* This is slightly ugly, but at least we don't have two
6862 copies of the epilogue-emitting code. */
6865 /* A NOTE_INSN_DELETED is supposed to be at the start
6866 and end of the "toplevel" insn chain. */
6867 emit_note (0, NOTE_INSN_DELETED);
6868 rs6000_emit_epilogue (FALSE);
6869 emit_note (0, NOTE_INSN_DELETED);
6871 if (TARGET_DEBUG_STACK)
6872 debug_rtx_list (get_insns (), 100);
6873 final (get_insns (), file, FALSE, FALSE);
6878 /* Output a traceback table here. See /usr/include/sys/debug.h for info
6881 We don't output a traceback table if -finhibit-size-directive was
6882 used. The documentation for -finhibit-size-directive reads
6883 ``don't output a @code{.size} assembler directive, or anything
6884 else that would cause trouble if the function is split in the
6885 middle, and the two halves are placed at locations far apart in
6886 memory.'' The traceback table has this property, since it
6887 includes the offset from the start of the function to the
6888 traceback table itself.
6890 System V.4 Powerpc's (and the embedded ABI derived from it) use a
6891 different traceback table. */
6892 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
6894 const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6895 int fixed_parms, float_parms, parm_info;
6898 while (*fname == '.') /* V.4 encodes . in the name */
6901 /* Need label immediately before tbtab, so we can compute its offset
6902 from the function start. */
6905 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
6906 ASM_OUTPUT_LABEL (file, fname);
6908 /* The .tbtab pseudo-op can only be used for the first eight
6909 expressions, since it can't handle the possibly variable
6910 length fields that follow. However, if you omit the optional
6911 fields, the assembler outputs zeros for all optional fields
6912 anyways, giving each variable length field is minimum length
6913 (as defined in sys/debug.h). Thus we can not use the .tbtab
6914 pseudo-op at all. */
6916 /* An all-zero word flags the start of the tbtab, for debuggers
6917 that have to find it by searching forward from the entry
6918 point or from the current pc. */
6919 fputs ("\t.long 0\n", file);
6921 /* Tbtab format type. Use format type 0. */
6922 fputs ("\t.byte 0,", file);
6924 /* Language type. Unfortunately, there doesn't seem to be any
6925 official way to get this info, so we use language_string. C
6926 is 0. C++ is 9. No number defined for Obj-C, so use the
6927 value for C for now. There is no official value for Java,
6928 although IBM appears to be using 13. There is no official value
6929 for Chill, so we've chosen 44 pseudo-randomly. */
6930 if (! strcmp (language_string, "GNU C")
6931 || ! strcmp (language_string, "GNU Objective-C"))
6933 else if (! strcmp (language_string, "GNU F77"))
6935 else if (! strcmp (language_string, "GNU Ada"))
6937 else if (! strcmp (language_string, "GNU Pascal"))
6939 else if (! strcmp (language_string, "GNU C++"))
6941 else if (! strcmp (language_string, "GNU Java"))
6943 else if (! strcmp (language_string, "GNU CHILL"))
6947 fprintf (file, "%d,", i);
6949 /* 8 single bit fields: global linkage (not set for C extern linkage,
6950 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
6951 from start of procedure stored in tbtab, internal function, function
6952 has controlled storage, function has no toc, function uses fp,
6953 function logs/aborts fp operations. */
6954 /* Assume that fp operations are used if any fp reg must be saved. */
6955 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
6957 /* 6 bitfields: function is interrupt handler, name present in
6958 proc table, function calls alloca, on condition directives
6959 (controls stack walks, 3 bits), saves condition reg, saves
6961 /* The `function calls alloca' bit seems to be set whenever reg 31 is
6962 set up as a frame pointer, even when there is no alloca call. */
6963 fprintf (file, "%d,",
6964 ((1 << 6) | (frame_pointer_needed << 5)
6965 | (info->cr_save_p << 1) | (info->lr_save_p)));
6967 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
6969 fprintf (file, "%d,",
6970 (info->push_p << 7) | (64 - info->first_fp_reg_save));
6972 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
6973 fprintf (file, "%d,", (32 - first_reg_to_save ()));
6976 /* Compute the parameter info from the function decl argument
6979 int next_parm_info_bit;
6981 next_parm_info_bit = 31;
6986 for (decl = DECL_ARGUMENTS (current_function_decl);
6987 decl; decl = TREE_CHAIN (decl))
6989 rtx parameter = DECL_INCOMING_RTL (decl);
6990 enum machine_mode mode = GET_MODE (parameter);
6992 if (GET_CODE (parameter) == REG)
6994 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
7002 else if (mode == DFmode)
7007 /* If only one bit will fit, don't or in this entry. */
7008 if (next_parm_info_bit > 0)
7009 parm_info |= (bits << (next_parm_info_bit - 1));
7010 next_parm_info_bit -= 2;
7014 fixed_parms += ((GET_MODE_SIZE (mode)
7015 + (UNITS_PER_WORD - 1))
7017 next_parm_info_bit -= 1;
7023 /* Number of fixed point parameters. */
7024 /* This is actually the number of words of fixed point parameters; thus
7025 an 8 byte struct counts as 2; and thus the maximum value is 8. */
7026 fprintf (file, "%d,", fixed_parms);
7028 /* 2 bitfields: number of floating point parameters (7 bits), parameters
7030 /* This is actually the number of fp registers that hold parameters;
7031 and thus the maximum value is 13. */
7032 /* Set parameters on stack bit if parameters are not in their original
7033 registers, regardless of whether they are on the stack? Xlc
7034 seems to set the bit when not optimizing. */
7035 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
7037 /* Optional fields follow. Some are variable length. */
7039 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
7041 /* There is an entry for each parameter in a register, in the order that
7042 they occur in the parameter list. Any intervening arguments on the
7043 stack are ignored. If the list overflows a long (max possible length
7044 34 bits) then completely leave off all elements that don't fit. */
7045 /* Only emit this long if there was at least one parameter. */
7046 if (fixed_parms || float_parms)
7047 fprintf (file, "\t.long %d\n", parm_info);
7049 /* Offset from start of code to tb table. */
7050 fputs ("\t.long ", file);
7051 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
7053 RS6000_OUTPUT_BASENAME (file, fname);
7055 assemble_name (file, fname);
7059 RS6000_OUTPUT_BASENAME (file, fname);
7061 assemble_name (file, fname);
7065 /* Interrupt handler mask. */
7066 /* Omit this long, since we never set the interrupt handler bit
7069 /* Number of CTL (controlled storage) anchors. */
7070 /* Omit this long, since the has_ctl bit is never set above. */
7072 /* Displacement into stack of each CTL anchor. */
7073 /* Omit this list of longs, because there are no CTL anchors. */
7075 /* Length of function name. */
7076 fprintf (file, "\t.short %d\n", (int) strlen (fname));
7078 /* Function name. */
7079 assemble_string (fname, strlen (fname));
7081 /* Register for alloca automatic storage; this is always reg 31.
7082 Only emit this if the alloca bit was set above. */
7083 if (frame_pointer_needed)
7084 fputs ("\t.byte 31\n", file);
7088 /* A C compound statement that outputs the assembler code for a thunk
7089 function, used to implement C++ virtual function calls with
7090 multiple inheritance. The thunk acts as a wrapper around a virtual
7091 function, adjusting the implicit object parameter before handing
7092 control off to the real function.
7094 First, emit code to add the integer DELTA to the location that
7095 contains the incoming first argument. Assume that this argument
7096 contains a pointer, and is the one used to pass the `this' pointer
7097 in C++. This is the incoming argument *before* the function
7098 prologue, e.g. `%o0' on a sparc. The addition must preserve the
7099 values of all other incoming arguments.
7101 After the addition, emit code to jump to FUNCTION, which is a
7102 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
7103 not touch the return address. Hence returning from FUNCTION will
7104 return to whoever called the current `thunk'.
7106 The effect must be as if FUNCTION had been called directly with the
7107 adjusted first argument. This macro is responsible for emitting
7108 all of the code for a thunk function; output_function_prologue()
7109 and output_function_epilogue() are not invoked.
7111 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
7112 been extracted from it.) It might possibly be useful on some
7113 targets, but probably not.
7115 If you do not define this macro, the target-independent code in the
7116 C++ frontend will generate a less efficient heavyweight thunk that
7117 calls FUNCTION instead of jumping to it. The generic approach does
7118 not support varargs. */
7121 output_mi_thunk (file, thunk_fndecl, delta, function)
7123 tree thunk_fndecl ATTRIBUTE_UNUSED;
7127 const char *this_reg =
7128 reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ];
7131 const char *r0 = reg_names[0];
7132 const char *toc = reg_names[2];
7133 const char *schain = reg_names[11];
7134 const char *r12 = reg_names[12];
7136 static int labelno = 0;
7138 /* Small constants that can be done by one add instruction. */
7139 if (delta >= -32768 && delta <= 32767)
7141 if (! TARGET_NEW_MNEMONICS)
7142 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg);
7144 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta);
7147 /* Large constants that can be done by one addis instruction. */
7148 else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1)
7149 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
7152 /* 32-bit constants that can be done by an add and addis instruction. */
7153 else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1)
7155 /* Break into two pieces, propagating the sign bit from the low
7156 word to the upper word. */
7157 int delta_high = delta >> 16;
7158 int delta_low = delta & 0xffff;
7159 if ((delta_low & 0x8000) != 0)
7162 delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */
7165 asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
7168 if (! TARGET_NEW_MNEMONICS)
7169 fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg);
7171 fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low);
7174 /* 64-bit constants, fixme */
7178 /* Get the prefix in front of the names. */
7179 switch (DEFAULT_ABI)
7189 case ABI_AIX_NODESC:
7195 /* If the function is compiled in this module, jump to it directly.
7196 Otherwise, load up its address and jump to it. */
7198 fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7200 if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode)
7201 && ! lookup_attribute ("longcall",
7202 TYPE_ATTRIBUTES (TREE_TYPE (function))))
7204 fprintf (file, "\tb %s", prefix);
7205 assemble_name (file, fname);
7206 if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file);
7212 switch (DEFAULT_ABI)
7218 /* Set up a TOC entry for the function. */
7219 ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno);
7221 ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno);
7224 /* Note, MINIMAL_TOC doesn't make sense in the case of a
7225 thunk, since there will be only one TOC entry for this
7227 fputs ("\t.tc\t", file);
7228 assemble_name (file, buf);
7229 fputs ("[TC],", file);
7230 assemble_name (file, buf);
7233 asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12);
7234 assemble_name (file, buf);
7235 asm_fprintf (file, "(%s)\n", reg_names[2]);
7237 (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n",
7241 (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n",
7244 asm_fprintf (file, "\tmtctr %s\n", r0);
7246 (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n",
7249 asm_fprintf (file, "\tbctr\n");
7252 case ABI_AIX_NODESC:
7255 fprintf (file, "\tb %s", prefix);
7256 assemble_name (file, fname);
7257 if (flag_pic) fputs ("@plt", file);
7263 fprintf (file, "\tb %s", prefix);
7264 if (flag_pic && !machopic_name_defined_p (fname))
7265 assemble_name (file, machopic_stub_name (fname));
7267 assemble_name (file, fname);
7276 /* A quick summary of the various types of 'constant-pool tables'
7279 Target Flags Name One table per
7280 AIX (none) AIX TOC object file
7281 AIX -mfull-toc AIX TOC object file
7282 AIX -mminimal-toc AIX minimal TOC translation unit
7283 SVR4/EABI (none) SVR4 SDATA object file
7284 SVR4/EABI -fpic SVR4 pic object file
7285 SVR4/EABI -fPIC SVR4 PIC translation unit
7286 SVR4/EABI -mrelocatable EABI TOC function
7287 SVR4/EABI -maix AIX TOC object file
7288 SVR4/EABI -maix -mminimal-toc
7289 AIX minimal TOC translation unit
7291 Name Reg. Set by entries contains:
7292 made by addrs? fp? sum?
7294 AIX TOC 2 crt0 as Y option option
7295 AIX minimal TOC 30 prolog gcc Y Y option
7296 SVR4 SDATA 13 crt0 gcc N Y N
7297 SVR4 pic 30 prolog ld Y not yet N
7298 SVR4 PIC 30 prolog gcc Y option option
7299 EABI TOC 30 prolog gcc Y option option
7303 /* Hash table stuff for keeping track of TOC entries. */
7305 struct toc_hash_struct
7307 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
7308 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
7310 enum machine_mode key_mode;
7314 static htab_t toc_hash_table;
7316 /* Hash functions for the hash table. */
7319 rs6000_hash_constant (k)
7322 unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k);
7323 const char *format = GET_RTX_FORMAT (GET_CODE (k));
7324 int flen = strlen (format);
7327 if (GET_CODE (k) == LABEL_REF)
7328 return result * 1231 + X0INT (XEXP (k, 0), 3);
7330 if (GET_CODE (k) == CONST_DOUBLE)
7332 else if (GET_CODE (k) == CODE_LABEL)
7337 for (; fidx < flen; fidx++)
7338 switch (format[fidx])
7343 const char *str = XSTR (k, fidx);
7345 result = result * 613 + len;
7346 for (i = 0; i < len; i++)
7347 result = result * 613 + (unsigned) str[i];
7352 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
7356 result = result * 613 + (unsigned) XINT (k, fidx);
7359 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
7360 result = result * 613 + (unsigned) XWINT (k, fidx);
7364 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
7365 result = result * 613 + (unsigned) (XWINT (k, fidx)
7376 toc_hash_function (hash_entry)
7377 const void * hash_entry;
7379 const struct toc_hash_struct *thc =
7380 (const struct toc_hash_struct *) hash_entry;
7381 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
7384 /* Compare H1 and H2 for equivalence. */
7387 toc_hash_eq (h1, h2)
7391 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
7392 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
7394 if (((const struct toc_hash_struct *) h1)->key_mode
7395 != ((const struct toc_hash_struct *) h2)->key_mode)
7398 /* Gotcha: One of these const_doubles will be in memory.
7399 The other may be on the constant-pool chain.
7400 So rtx_equal_p will think they are different... */
7403 if (GET_CODE (r1) != GET_CODE (r2)
7404 || GET_MODE (r1) != GET_MODE (r2))
7406 if (GET_CODE (r1) == CONST_DOUBLE)
7408 int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE));
7410 for (i = 2; i < format_len; i++)
7411 if (XWINT (r1, i) != XWINT (r2, i))
7416 else if (GET_CODE (r1) == LABEL_REF)
7417 return (CODE_LABEL_NUMBER (XEXP (r1, 0))
7418 == CODE_LABEL_NUMBER (XEXP (r2, 0)));
7420 return rtx_equal_p (r1, r2);
7423 /* Mark the hash table-entry HASH_ENTRY. */
7426 toc_hash_mark_entry (hash_slot, unused)
7428 void * unused ATTRIBUTE_UNUSED;
7430 const struct toc_hash_struct * hash_entry =
7431 *(const struct toc_hash_struct **) hash_slot;
7432 rtx r = hash_entry->key;
7433 ggc_set_mark (hash_entry);
7434 /* For CODE_LABELS, we don't want to drag in the whole insn chain... */
7435 if (GET_CODE (r) == LABEL_REF)
7438 ggc_set_mark (XEXP (r, 0));
7445 /* Mark all the elements of the TOC hash-table *HT. */
7448 toc_hash_mark_table (vht)
7453 htab_traverse (*ht, toc_hash_mark_entry, (void *)0);
7456 /* These are the names given by the C++ front-end to vtables, and
7457 vtable-like objects. Ideally, this logic should not be here;
7458 instead, there should be some programmatic way of inquiring as
7459 to whether or not an object is a vtable. */
7461 #define VTABLE_NAME_P(NAME) \
7462 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
7463 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
7464 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
7465 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
7468 rs6000_output_symbol_ref (file, x)
7472 /* Currently C++ toc references to vtables can be emitted before it
7473 is decided whether the vtable is public or private. If this is
7474 the case, then the linker will eventually complain that there is
7475 a reference to an unknown section. Thus, for vtables only,
7476 we emit the TOC reference to reference the symbol and not the
7478 const char *name = XSTR (x, 0);
7480 if (VTABLE_NAME_P (name))
7482 RS6000_OUTPUT_BASENAME (file, name);
7485 assemble_name (file, name);
7488 /* Output a TOC entry. We derive the entry name from what is being
7492 output_toc (file, x, labelno, mode)
7496 enum machine_mode mode;
7499 const char *name = buf;
7500 const char *real_name;
7507 /* When the linker won't eliminate them, don't output duplicate
7508 TOC entries (this happens on AIX if there is any kind of TOC,
7509 and on SVR4 under -fPIC or -mrelocatable). */
7512 struct toc_hash_struct *h;
7515 h = ggc_alloc (sizeof (*h));
7518 h->labelno = labelno;
7520 found = htab_find_slot (toc_hash_table, h, 1);
7523 else /* This is indeed a duplicate.
7524 Set this label equal to that label. */
7526 fputs ("\t.set ", file);
7527 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
7528 fprintf (file, "%d,", labelno);
7529 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
7530 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
7536 /* If we're going to put a double constant in the TOC, make sure it's
7537 aligned properly when strict alignment is on. */
7538 if (GET_CODE (x) == CONST_DOUBLE
7540 && GET_MODE_BITSIZE (mode) >= 64
7541 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
7542 ASM_OUTPUT_ALIGN (file, 3);
7545 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
7547 /* Handle FP constants specially. Note that if we have a minimal
7548 TOC, things we put here aren't actually in the TOC, so we can allow
7550 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7555 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
7556 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
7560 if (TARGET_MINIMAL_TOC)
7561 fputs (DOUBLE_INT_ASM_OP, file);
7563 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
7564 fprintf (file, "0x%lx%08lx\n", k[0], k[1]);
7569 if (TARGET_MINIMAL_TOC)
7570 fputs ("\t.long ", file);
7572 fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
7573 fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]);
7577 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7582 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
7583 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7587 if (TARGET_MINIMAL_TOC)
7588 fputs (DOUBLE_INT_ASM_OP, file);
7590 fprintf (file, "\t.tc FS_%lx[TC],", l);
7591 fprintf (file, "0x%lx00000000\n", l);
7596 if (TARGET_MINIMAL_TOC)
7597 fputs ("\t.long ", file);
7599 fprintf (file, "\t.tc FS_%lx[TC],", l);
7600 fprintf (file, "0x%lx\n", l);
7604 else if (GET_MODE (x) == VOIDmode
7605 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
7607 unsigned HOST_WIDE_INT low;
7610 if (GET_CODE (x) == CONST_DOUBLE)
7612 low = CONST_DOUBLE_LOW (x);
7613 high = CONST_DOUBLE_HIGH (x);
7616 #if HOST_BITS_PER_WIDE_INT == 32
7619 high = (low & 0x80000000) ? ~0 : 0;
7623 low = INTVAL (x) & 0xffffffff;
7624 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
7628 /* TOC entries are always Pmode-sized, but since this
7629 is a bigendian machine then if we're putting smaller
7630 integer constants in the TOC we have to pad them.
7631 (This is still a win over putting the constants in
7632 a separate constant pool, because then we'd have
7633 to have both a TOC entry _and_ the actual constant.)
7635 For a 32-bit target, CONST_INT values are loaded and shifted
7636 entirely within `low' and can be stored in one TOC entry. */
7638 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
7639 abort ();/* It would be easy to make this work, but it doesn't now. */
7641 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
7642 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
7643 POINTER_SIZE, &low, &high, 0);
7647 if (TARGET_MINIMAL_TOC)
7648 fputs (DOUBLE_INT_ASM_OP, file);
7650 fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low);
7651 fprintf (file, "0x%lx%08lx\n", (long) high, (long) low);
7656 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
7658 if (TARGET_MINIMAL_TOC)
7659 fputs ("\t.long ", file);
7661 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
7662 (long)high, (long)low);
7663 fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low);
7667 if (TARGET_MINIMAL_TOC)
7668 fputs ("\t.long ", file);
7670 fprintf (file, "\t.tc IS_%lx[TC],", (long) low);
7671 fprintf (file, "0x%lx\n", (long) low);
7677 if (GET_CODE (x) == CONST)
7679 if (GET_CODE (XEXP (x, 0)) != PLUS)
7682 base = XEXP (XEXP (x, 0), 0);
7683 offset = INTVAL (XEXP (XEXP (x, 0), 1));
7686 if (GET_CODE (base) == SYMBOL_REF)
7687 name = XSTR (base, 0);
7688 else if (GET_CODE (base) == LABEL_REF)
7689 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
7690 else if (GET_CODE (base) == CODE_LABEL)
7691 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
7695 STRIP_NAME_ENCODING (real_name, name);
7696 if (TARGET_MINIMAL_TOC)
7697 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
7700 fprintf (file, "\t.tc %s", real_name);
7703 fprintf (file, ".N%d", - offset);
7705 fprintf (file, ".P%d", offset);
7707 fputs ("[TC],", file);
7710 /* Currently C++ toc references to vtables can be emitted before it
7711 is decided whether the vtable is public or private. If this is
7712 the case, then the linker will eventually complain that there is
7713 a TOC reference to an unknown section. Thus, for vtables only,
7714 we emit the TOC reference to reference the symbol and not the
7716 if (VTABLE_NAME_P (name))
7718 RS6000_OUTPUT_BASENAME (file, name);
7720 fprintf (file, "%d", offset);
7721 else if (offset > 0)
7722 fprintf (file, "+%d", offset);
7725 output_addr_const (file, x);
7729 /* Output an assembler pseudo-op to write an ASCII string of N characters
7730 starting at P to FILE.
7732 On the RS/6000, we have to do this using the .byte operation and
7733 write out special characters outside the quoted string.
7734 Also, the assembler is broken; very long strings are truncated,
7735 so we must artificially break them up early. */
7738 output_ascii (file, p, n)
7744 int i, count_string;
7745 const char *for_string = "\t.byte \"";
7746 const char *for_decimal = "\t.byte ";
7747 const char *to_close = NULL;
7750 for (i = 0; i < n; i++)
7753 if (c >= ' ' && c < 0177)
7756 fputs (for_string, file);
7759 /* Write two quotes to get one. */
7767 for_decimal = "\"\n\t.byte ";
7771 if (count_string >= 512)
7773 fputs (to_close, file);
7775 for_string = "\t.byte \"";
7776 for_decimal = "\t.byte ";
7784 fputs (for_decimal, file);
7785 fprintf (file, "%d", c);
7787 for_string = "\n\t.byte \"";
7794 /* Now close the string if we have written one. Then end the line. */
7796 fputs (to_close, file);
7799 /* Generate a unique section name for FILENAME for a section type
7800 represented by SECTION_DESC. Output goes into BUF.
7802 SECTION_DESC can be any string, as long as it is different for each
7803 possible section type.
7805 We name the section in the same manner as xlc. The name begins with an
7806 underscore followed by the filename (after stripping any leading directory
7807 names) with the last period replaced by the string SECTION_DESC. If
7808 FILENAME does not contain a period, SECTION_DESC is appended to the end of
7812 rs6000_gen_section_name (buf, filename, section_desc)
7814 const char *filename;
7815 const char *section_desc;
7817 const char *q, *after_last_slash, *last_period = 0;
7821 after_last_slash = filename;
7822 for (q = filename; *q; q++)
7825 after_last_slash = q + 1;
7830 len = strlen (after_last_slash) + strlen (section_desc) + 2;
7831 *buf = (char *) permalloc (len);
7836 for (q = after_last_slash; *q; q++)
7838 if (q == last_period)
7840 strcpy (p, section_desc);
7841 p += strlen (section_desc);
7844 else if (ISALNUM (*q))
7848 if (last_period == 0)
7849 strcpy (p, section_desc);
7854 /* Emit profile function. */
7857 output_profile_hook (labelno)
7860 if (DEFAULT_ABI == ABI_AIX)
7863 const char *label_name;
7868 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7869 STRIP_NAME_ENCODING (label_name, ggc_strdup (buf));
7870 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
7872 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
7875 else if (DEFAULT_ABI == ABI_DARWIN)
7877 const char *mcount_name = RS6000_MCOUNT;
7878 int caller_addr_regno = LINK_REGISTER_REGNUM;
7880 /* Be conservative and always set this, at least for now. */
7881 current_function_uses_pic_offset_table = 1;
7884 /* For PIC code, set up a stub and collect the caller's address
7885 from r0, which is where the prologue puts it. */
7888 mcount_name = machopic_stub_name (mcount_name);
7889 if (current_function_uses_pic_offset_table)
7890 caller_addr_regno = 0;
7893 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
7895 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
7899 /* Write function profiler code. */
7902 output_function_profiler (file, labelno)
7908 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7909 switch (DEFAULT_ABI)
7916 case ABI_AIX_NODESC:
7917 fprintf (file, "\tmflr %s\n", reg_names[0]);
7920 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
7921 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7922 reg_names[0], reg_names[1]);
7923 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
7924 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
7925 assemble_name (file, buf);
7926 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
7928 else if (flag_pic > 1)
7930 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7931 reg_names[0], reg_names[1]);
7932 /* Now, we need to get the address of the label. */
7933 fputs ("\tbl 1f\n\t.long ", file);
7934 assemble_name (file, buf);
7935 fputs ("-.\n1:", file);
7936 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
7937 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
7938 reg_names[0], reg_names[11]);
7939 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
7940 reg_names[0], reg_names[0], reg_names[11]);
7944 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
7945 assemble_name (file, buf);
7946 fputs ("@ha\n", file);
7947 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
7948 reg_names[0], reg_names[1]);
7949 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
7950 assemble_name (file, buf);
7951 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
7954 if (current_function_needs_context)
7955 asm_fprintf (file, "\tmr %s,%s\n",
7956 reg_names[30], reg_names[STATIC_CHAIN_REGNUM]);
7957 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
7958 if (current_function_needs_context)
7959 asm_fprintf (file, "\tmr %s,%s\n",
7960 reg_names[STATIC_CHAIN_REGNUM], reg_names[30]);
7965 /* Don't do anything, done in output_profile_hook (). */
7971 /* Adjust the cost of a scheduling dependency. Return the new cost of
7972 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7975 rs6000_adjust_cost (insn, link, dep_insn, cost)
7978 rtx dep_insn ATTRIBUTE_UNUSED;
7981 if (! recog_memoized (insn))
7984 if (REG_NOTE_KIND (link) != 0)
7987 if (REG_NOTE_KIND (link) == 0)
7989 /* Data dependency; DEP_INSN writes a register that INSN reads
7990 some cycles later. */
7991 switch (get_attr_type (insn))
7994 /* Tell the first scheduling pass about the latency between
7995 a mtctr and bctr (and mtlr and br/blr). The first
7996 scheduling pass will not know about this latency since
7997 the mtctr instruction, which has the latency associated
7998 to it, will be generated by reload. */
7999 return TARGET_POWER ? 5 : 4;
8001 /* Leave some extra cycles between a compare and its
8002 dependent branch, to inhibit expensive mispredicts. */
8003 if ((rs6000_cpu_attr == CPU_PPC750
8004 || rs6000_cpu_attr == CPU_PPC7400
8005 || rs6000_cpu_attr == CPU_PPC7450)
8006 && recog_memoized (dep_insn)
8007 && (INSN_CODE (dep_insn) >= 0)
8008 && (get_attr_type (dep_insn) == TYPE_COMPARE
8009 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
8010 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
8011 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL))
8016 /* Fall out to return default cost. */
8022 /* A C statement (sans semicolon) to update the integer scheduling
8023 priority INSN_PRIORITY (INSN). Reduce the priority to execute the
8024 INSN earlier, increase the priority to execute INSN later. Do not
8025 define this macro if you do not need to adjust the scheduling
8026 priorities of insns. */
8029 rs6000_adjust_priority (insn, priority)
8030 rtx insn ATTRIBUTE_UNUSED;
8033 /* On machines (like the 750) which have asymmetric integer units,
8034 where one integer unit can do multiply and divides and the other
8035 can't, reduce the priority of multiply/divide so it is scheduled
8036 before other integer operations. */
8039 if (! INSN_P (insn))
8042 if (GET_CODE (PATTERN (insn)) == USE)
8045 switch (rs6000_cpu_attr) {
8047 switch (get_attr_type (insn))
8054 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
8055 priority, priority);
8056 if (priority >= 0 && priority < 0x01000000)
8066 /* Return how many instructions the machine can issue per cycle. */
8069 rs6000_issue_rate ()
8071 switch (rs6000_cpu_attr) {
8072 case CPU_RIOS1: /* ? */
8074 case CPU_PPC601: /* ? */
8093 /* Length in units of the trampoline for entering a nested function. */
8096 rs6000_trampoline_size ()
8100 switch (DEFAULT_ABI)
8106 ret = (TARGET_32BIT) ? 12 : 24;
8111 case ABI_AIX_NODESC:
8112 ret = (TARGET_32BIT) ? 40 : 48;
8119 /* Emit RTL insns to initialize the variable parts of a trampoline.
8120 FNADDR is an RTX for the address of the function's pure code.
8121 CXT is an RTX for the static chain value for the function. */
8124 rs6000_initialize_trampoline (addr, fnaddr, cxt)
8129 enum machine_mode pmode = Pmode;
8130 int regsize = (TARGET_32BIT) ? 4 : 8;
8131 rtx ctx_reg = force_reg (pmode, cxt);
8133 switch (DEFAULT_ABI)
8138 /* Macros to shorten the code expansions below. */
8139 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
8140 #define MEM_PLUS(addr,offset) \
8141 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
8143 /* Under AIX, just build the 3 word function descriptor */
8146 rtx fn_reg = gen_reg_rtx (pmode);
8147 rtx toc_reg = gen_reg_rtx (pmode);
8148 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
8149 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8150 emit_move_insn (MEM_DEREF (addr), fn_reg);
8151 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
8152 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
8156 /* Under V.4/eabi, call __trampoline_setup to do the real work. */
8159 case ABI_AIX_NODESC:
8160 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
8163 GEN_INT (rs6000_trampoline_size ()), SImode,
8173 /* Table of valid machine attributes. */
8175 const struct attribute_spec rs6000_attribute_table[] =
8177 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8178 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
8179 { NULL, 0, 0, false, false, false, NULL }
8182 /* Handle a "longcall" attribute; arguments as in struct
8183 attribute_spec.handler. */
8186 rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs)
8189 tree args ATTRIBUTE_UNUSED;
8190 int flags ATTRIBUTE_UNUSED;
8193 if (TREE_CODE (*node) != FUNCTION_TYPE
8194 && TREE_CODE (*node) != FIELD_DECL
8195 && TREE_CODE (*node) != TYPE_DECL)
8197 warning ("`%s' attribute only applies to functions",
8198 IDENTIFIER_POINTER (name));
8199 *no_add_attrs = true;
8205 /* Return a reference suitable for calling a function with the
8206 longcall attribute. */
8209 rs6000_longcall_ref (call_ref)
8212 const char *call_name;
8215 if (GET_CODE (call_ref) != SYMBOL_REF)
8218 /* System V adds '.' to the internal name, so skip them. */
8219 call_name = XSTR (call_ref, 0);
8220 if (*call_name == '.')
8222 while (*call_name == '.')
8225 node = get_identifier (call_name);
8226 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
8229 return force_reg (Pmode, call_ref);
8233 /* A C statement or statements to switch to the appropriate section
8234 for output of RTX in mode MODE. You can assume that RTX is some
8235 kind of constant in RTL. The argument MODE is redundant except in
8236 the case of a `const_int' rtx. Select the section by calling
8237 `text_section' or one of the alternatives for other sections.
8239 Do not define this macro if you put all constants in the read-only
8245 rs6000_select_rtx_section (mode, x)
8246 enum machine_mode mode;
8249 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
8255 /* A C statement or statements to switch to the appropriate
8256 section for output of DECL. DECL is either a `VAR_DECL' node
8257 or a constant of some sort. RELOC indicates whether forming
8258 the initial value of DECL requires link-time relocations. */
8261 rs6000_select_section (decl, reloc)
8265 int size = int_size_in_bytes (TREE_TYPE (decl));
8268 static void (* const sec_funcs[4]) PARAMS ((void)) = {
8275 needs_sdata = (size > 0
8276 && size <= g_switch_value
8277 && rs6000_sdata != SDATA_NONE
8278 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
8280 if (TREE_CODE (decl) == STRING_CST)
8281 readonly = ! flag_writable_strings;
8282 else if (TREE_CODE (decl) == VAR_DECL)
8283 readonly = (! (flag_pic && reloc)
8284 && TREE_READONLY (decl)
8285 && ! TREE_SIDE_EFFECTS (decl)
8286 && DECL_INITIAL (decl)
8287 && DECL_INITIAL (decl) != error_mark_node
8288 && TREE_CONSTANT (DECL_INITIAL (decl)));
8291 if (needs_sdata && rs6000_sdata != SDATA_EABI)
8294 (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])();
8297 /* A C statement to build up a unique section name, expressed as a
8298 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
8299 RELOC indicates whether the initial value of EXP requires
8300 link-time relocations. If you do not define this macro, GCC will use
8301 the symbol name prefixed by `.' as the section name. Note - this
8302 macro can now be called for unitialised data items as well as
8303 initialised data and functions. */
8306 rs6000_unique_section (decl, reloc)
8310 int size = int_size_in_bytes (TREE_TYPE (decl));
8319 static const char *const prefixes[7][2] =
8321 { ".text.", ".gnu.linkonce.t." },
8322 { ".rodata.", ".gnu.linkonce.r." },
8323 { ".sdata2.", ".gnu.linkonce.s2." },
8324 { ".data.", ".gnu.linkonce.d." },
8325 { ".sdata.", ".gnu.linkonce.s." },
8326 { ".bss.", ".gnu.linkonce.b." },
8327 { ".sbss.", ".gnu.linkonce.sb." }
8330 needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL
8332 && size <= g_switch_value
8333 && rs6000_sdata != SDATA_NONE
8334 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)));
8336 if (TREE_CODE (decl) == STRING_CST)
8337 readonly = ! flag_writable_strings;
8338 else if (TREE_CODE (decl) == VAR_DECL)
8339 readonly = (! (flag_pic && reloc)
8340 && TREE_READONLY (decl)
8341 && ! TREE_SIDE_EFFECTS (decl)
8342 && DECL_INITIAL (decl)
8343 && DECL_INITIAL (decl) != error_mark_node
8344 && TREE_CONSTANT (DECL_INITIAL (decl)));
8347 if (needs_sdata && rs6000_sdata != SDATA_EABI)
8350 sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1)
8351 + (readonly ? 0 : 2)
8352 + (needs_sdata ? 1 : 0)
8353 + (DECL_INITIAL (decl) == 0
8354 || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0);
8356 STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)));
8357 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
8358 len = strlen (name) + strlen (prefix);
8359 string = alloca (len + 1);
8361 sprintf (string, "%s%s", prefix, name);
8363 DECL_SECTION_NAME (decl) = build_string (len, string);
8367 /* If we are referencing a function that is static or is known to be
8368 in this file, make the SYMBOL_REF special. We can use this to indicate
8369 that we can branch to this function without emitting a no-op after the
8370 call. For real AIX calling sequences, we also replace the
8371 function name with the real name (1 or 2 leading .'s), rather than
8372 the function descriptor name. This saves a lot of overriding code
8373 to read the prefixes. */
8376 rs6000_encode_section_info (decl)
8379 if (TREE_CODE (decl) == FUNCTION_DECL)
8381 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
8382 if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
8383 && ! DECL_WEAK (decl))
8384 SYMBOL_REF_FLAG (sym_ref) = 1;
8386 if (DEFAULT_ABI == ABI_AIX)
8388 size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2;
8389 size_t len2 = strlen (XSTR (sym_ref, 0));
8390 char *str = alloca (len1 + len2 + 1);
8393 memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1);
8395 XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2);
8398 else if (rs6000_sdata != SDATA_NONE
8399 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8400 && TREE_CODE (decl) == VAR_DECL)
8402 int size = int_size_in_bytes (TREE_TYPE (decl));
8403 tree section_name = DECL_SECTION_NAME (decl);
8404 const char *name = (char *)0;
8409 if (TREE_CODE (section_name) == STRING_CST)
8411 name = TREE_STRING_POINTER (section_name);
8412 len = TREE_STRING_LENGTH (section_name);
8418 if ((size > 0 && size <= g_switch_value)
8420 && ((len == sizeof (".sdata") - 1
8421 && strcmp (name, ".sdata") == 0)
8422 || (len == sizeof (".sdata2") - 1
8423 && strcmp (name, ".sdata2") == 0)
8424 || (len == sizeof (".sbss") - 1
8425 && strcmp (name, ".sbss") == 0)
8426 || (len == sizeof (".sbss2") - 1
8427 && strcmp (name, ".sbss2") == 0)
8428 || (len == sizeof (".PPC.EMB.sdata0") - 1
8429 && strcmp (name, ".PPC.EMB.sdata0") == 0)
8430 || (len == sizeof (".PPC.EMB.sbss0") - 1
8431 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
8433 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
8434 size_t len = strlen (XSTR (sym_ref, 0));
8435 char *str = alloca (len + 2);
8438 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
8439 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
8444 #endif /* USING_SVR4_H */
8447 /* Return a REG that occurs in ADDR with coefficient 1.
8448 ADDR can be effectively incremented by incrementing REG.
8450 r0 is special and we must not select it as an address
8451 register by this routine since our caller will try to
8452 increment the returned register via an "la" instruction. */
8455 find_addr_reg (addr)
8458 while (GET_CODE (addr) == PLUS)
8460 if (GET_CODE (XEXP (addr, 0)) == REG
8461 && REGNO (XEXP (addr, 0)) != 0)
8462 addr = XEXP (addr, 0);
8463 else if (GET_CODE (XEXP (addr, 1)) == REG
8464 && REGNO (XEXP (addr, 1)) != 0)
8465 addr = XEXP (addr, 1);
8466 else if (CONSTANT_P (XEXP (addr, 0)))
8467 addr = XEXP (addr, 1);
8468 else if (CONSTANT_P (XEXP (addr, 1)))
8469 addr = XEXP (addr, 0);
8473 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
8479 rs6000_fatal_bad_address (op)
8482 fatal_insn ("bad address", op);
8485 /* Called to register all of our global variables with the garbage
8489 rs6000_add_gc_roots ()
8491 ggc_add_rtx_root (&rs6000_compare_op0, 1);
8492 ggc_add_rtx_root (&rs6000_compare_op1, 1);
8494 toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL);
8495 ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table),
8496 toc_hash_mark_table);
8499 machopic_add_gc_roots ();
8506 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
8507 reference and a constant. */
8510 symbolic_operand (op)
8513 switch (GET_CODE (op))
8520 return (GET_CODE (op) == SYMBOL_REF ||
8521 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8522 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
8523 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8530 #ifdef RS6000_LONG_BRANCH
8532 static tree stub_list = 0;
8534 /* ADD_COMPILER_STUB adds the compiler generated stub for handling
8535 procedure calls to the linked list. */
8538 add_compiler_stub (label_name, function_name, line_number)
8543 tree stub = build_tree_list (function_name, label_name);
8544 TREE_TYPE (stub) = build_int_2 (line_number, 0);
8545 TREE_CHAIN (stub) = stub_list;
8549 #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB)
8550 #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB)
8551 #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB))
8553 /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for
8554 handling procedure calls from the linked list and initializes the
8558 output_compiler_stub ()
8561 char label_buf[256];
8563 tree tmp_stub, stub;
8566 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8568 fprintf (asm_out_file,
8569 "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub)));
8571 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
8572 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
8573 fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub));
8574 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
8576 if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*')
8578 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1);
8582 strcpy (label_buf+1,
8583 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub)));
8586 strcpy (tmp_buf, "lis r12,hi16(");
8587 strcat (tmp_buf, label_buf);
8588 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
8589 strcat (tmp_buf, label_buf);
8590 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
8591 output_asm_insn (tmp_buf, 0);
8593 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
8594 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
8595 fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub));
8596 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
8602 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
8603 already there or not. */
8606 no_previous_def (function_name)
8610 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8611 if (function_name == STUB_FUNCTION_NAME (stub))
8616 /* GET_PREV_LABEL gets the label name from the previous definition of
8620 get_prev_label (function_name)
8624 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
8625 if (function_name == STUB_FUNCTION_NAME (stub))
8626 return STUB_LABEL_NAME (stub);
8630 /* INSN is either a function call or a millicode call. It may have an
8631 unconditional jump in its delay slot.
8633 CALL_DEST is the routine we are calling. */
8636 output_call (insn, call_dest, operand_number)
8641 static char buf[256];
8642 if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic)
8645 tree funname = get_identifier (XSTR (call_dest, 0));
8647 if (no_previous_def (funname))
8650 rtx label_rtx = gen_label_rtx ();
8651 char *label_buf, temp_buf[256];
8652 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
8653 CODE_LABEL_NUMBER (label_rtx));
8654 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
8655 labelname = get_identifier (label_buf);
8656 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
8658 line_number = NOTE_LINE_NUMBER (insn);
8659 add_compiler_stub (labelname, funname, line_number);
8662 labelname = get_prev_label (funname);
8664 sprintf (buf, "jbsr %%z%d,%.246s",
8665 operand_number, IDENTIFIER_POINTER (labelname));
8670 sprintf (buf, "bl %%z%d", operand_number);
8675 #endif /* RS6000_LONG_BRANCH */
8677 #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \
8679 const char *const symbol_ = (SYMBOL); \
8680 char *buffer_ = (BUF); \
8681 if (symbol_[0] == '"') \
8683 sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \
8685 else if (name_needs_quotes(symbol_)) \
8687 sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \
8691 sprintf(buffer_, "L%d$%s", (N), symbol_); \
8696 /* Generate PIC and indirect symbol stubs. */
8699 machopic_output_stub (file, symb, stub)
8701 const char *symb, *stub;
8703 unsigned int length;
8704 char *symbol_name, *lazy_ptr_name;
8705 char *local_label_0;
8706 static int label = 0;
8708 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
8709 STRIP_NAME_ENCODING (symb, symb);
8713 length = strlen (symb);
8714 symbol_name = alloca (length + 32);
8715 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
8717 lazy_ptr_name = alloca (length + 32);
8718 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
8720 local_label_0 = alloca (length + 32);
8721 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0);
8724 machopic_picsymbol_stub_section ();
8726 machopic_symbol_stub_section ();
8728 fprintf (file, "%s:\n", stub);
8729 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
8733 fprintf (file, "\tmflr r0\n");
8734 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
8735 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
8736 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
8737 lazy_ptr_name, local_label_0);
8738 fprintf (file, "\tmtlr r0\n");
8739 fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n",
8740 lazy_ptr_name, local_label_0);
8741 fprintf (file, "\tmtctr r12\n");
8742 fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n",
8743 lazy_ptr_name, local_label_0);
8744 fprintf (file, "\tbctr\n");
8747 fprintf (file, "non-pure not supported\n");
8749 machopic_lazy_symbol_ptr_section ();
8750 fprintf (file, "%s:\n", lazy_ptr_name);
8751 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
8752 fprintf (file, "\t.long dyld_stub_binding_helper\n");
8755 /* Legitimize PIC addresses. If the address is already
8756 position-independent, we return ORIG. Newly generated
8757 position-independent addresses go into a reg. This is REG if non
8758 zero, otherwise we allocate register(s) as necessary. */
8760 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000)
8763 rs6000_machopic_legitimize_pic_address (orig, mode, reg)
8765 enum machine_mode mode;
8770 if (reg == NULL && ! reload_in_progress && ! reload_completed)
8771 reg = gen_reg_rtx (Pmode);
8773 if (GET_CODE (orig) == CONST)
8775 if (GET_CODE (XEXP (orig, 0)) == PLUS
8776 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
8779 if (GET_CODE (XEXP (orig, 0)) == PLUS)
8782 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
8785 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
8791 if (GET_CODE (offset) == CONST_INT)
8793 if (SMALL_INT (offset))
8794 return plus_constant (base, INTVAL (offset));
8795 else if (! reload_in_progress && ! reload_completed)
8796 offset = force_reg (Pmode, offset);
8800 return gen_rtx (PLUS, Pmode, base, offset);
8803 /* Fall back on generic machopic code. */
8804 return machopic_legitimize_pic_address (orig, mode, reg);
8807 /* This is just a placeholder to make linking work without having to
8808 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
8809 ever needed for Darwin (not too likely!) this would have to get a
8817 #endif /* TARGET_MACHO */
8821 rs6000_elf_section_type_flags (decl, name, reloc)
8826 unsigned int flags = default_section_type_flags (decl, name, reloc);
8828 if (TARGET_RELOCATABLE)
8829 flags |= SECTION_WRITE;
8831 /* Solaris doesn't like @nobits, and gas can handle .sbss without it. */
8832 flags &= ~SECTION_BSS;
8837 /* Record an element in the table of global constructors. SYMBOL is
8838 a SYMBOL_REF of the function to be called; PRIORITY is a number
8839 between 0 and MAX_INIT_PRIORITY.
8841 This differs from default_named_section_asm_out_constructor in
8842 that we have special handling for -mrelocatable. */
8845 rs6000_elf_asm_out_constructor (symbol, priority)
8849 const char *section = ".ctors";
8852 if (priority != DEFAULT_INIT_PRIORITY)
8854 sprintf (buf, ".ctors.%.5u",
8855 /* Invert the numbering so the linker puts us in the proper
8856 order; constructors are run from right to left, and the
8857 linker sorts in increasing order. */
8858 MAX_INIT_PRIORITY - priority);
8862 named_section_flags (section, SECTION_WRITE);
8863 assemble_align (POINTER_SIZE);
8865 if (TARGET_RELOCATABLE)
8867 fputs ("\t.long (", asm_out_file);
8868 output_addr_const (asm_out_file, symbol);
8869 fputs (")@fixup\n", asm_out_file);
8872 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
8876 rs6000_elf_asm_out_destructor (symbol, priority)
8880 const char *section = ".dtors";
8883 if (priority != DEFAULT_INIT_PRIORITY)
8885 sprintf (buf, ".dtors.%.5u",
8886 /* Invert the numbering so the linker puts us in the proper
8887 order; constructors are run from right to left, and the
8888 linker sorts in increasing order. */
8889 MAX_INIT_PRIORITY - priority);
8893 named_section_flags (section, SECTION_WRITE);
8894 assemble_align (POINTER_SIZE);
8896 if (TARGET_RELOCATABLE)
8898 fputs ("\t.long (", asm_out_file);
8899 output_addr_const (asm_out_file, symbol);
8900 fputs (")@fixup\n", asm_out_file);
8903 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
8907 #ifdef OBJECT_FORMAT_COFF
8909 xcoff_asm_named_section (name, flags)
8911 unsigned int flags ATTRIBUTE_UNUSED;
8913 fprintf (asm_out_file, "\t.csect %s\n", name);