1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_maybe_dead (rtx);
620 static void rs6000_emit_stack_tie (void);
621 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
622 static rtx spe_synthesize_frame_save (rtx);
623 static bool spe_func_has_64bit_regs_p (void);
624 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
626 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
627 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
628 static unsigned rs6000_hash_constant (rtx);
629 static unsigned toc_hash_function (const void *);
630 static int toc_hash_eq (const void *, const void *);
631 static int constant_pool_expr_1 (rtx, int *, int *);
632 static bool constant_pool_expr_p (rtx);
633 static bool legitimate_small_data_p (enum machine_mode, rtx);
634 static bool legitimate_indexed_address_p (rtx, int);
635 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
636 static struct machine_function * rs6000_init_machine_status (void);
637 static bool rs6000_assemble_integer (rtx, unsigned int, int);
638 static bool no_global_regs_above (int);
639 #ifdef HAVE_GAS_HIDDEN
640 static void rs6000_assemble_visibility (tree, int);
642 static int rs6000_ra_ever_killed (void);
643 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
644 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
645 static bool rs6000_ms_bitfield_layout_p (tree);
646 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
647 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
648 static const char *rs6000_mangle_fundamental_type (tree);
649 extern const struct attribute_spec rs6000_attribute_table[];
650 static void rs6000_set_default_type_attributes (tree);
651 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
652 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
653 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
655 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
656 static bool rs6000_return_in_memory (tree, tree);
657 static void rs6000_file_start (void);
659 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
660 static void rs6000_elf_asm_out_constructor (rtx, int);
661 static void rs6000_elf_asm_out_destructor (rtx, int);
662 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
663 static void rs6000_elf_asm_init_sections (void);
664 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
665 static void rs6000_elf_unique_section (tree, int);
666 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
667 unsigned HOST_WIDE_INT);
668 static void rs6000_elf_encode_section_info (tree, rtx, int)
671 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
673 static void rs6000_xcoff_asm_output_anchor (rtx);
674 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
675 static void rs6000_xcoff_asm_init_sections (void);
676 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
677 static section *rs6000_xcoff_select_section (tree, int,
678 unsigned HOST_WIDE_INT);
679 static void rs6000_xcoff_unique_section (tree, int);
680 static section *rs6000_xcoff_select_rtx_section
681 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
682 static const char * rs6000_xcoff_strip_name_encoding (const char *);
683 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
684 static void rs6000_xcoff_file_start (void);
685 static void rs6000_xcoff_file_end (void);
687 static int rs6000_variable_issue (FILE *, int, rtx, int);
688 static bool rs6000_rtx_costs (rtx, int, int, int *);
689 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
690 static void rs6000_sched_init (FILE *, int, int);
691 static bool is_microcoded_insn (rtx);
692 static bool is_nonpipeline_insn (rtx);
693 static bool is_cracked_insn (rtx);
694 static bool is_branch_slot_insn (rtx);
695 static bool is_load_insn (rtx);
696 static rtx get_store_dest (rtx pat);
697 static bool is_store_insn (rtx);
698 static bool set_to_load_agen (rtx,rtx);
699 static bool adjacent_mem_locations (rtx,rtx);
700 static int rs6000_adjust_priority (rtx, int);
701 static int rs6000_issue_rate (void);
702 static bool rs6000_is_costly_dependence (dep_t, int, int);
703 static rtx get_next_active_insn (rtx, rtx);
704 static bool insn_terminates_group_p (rtx , enum group_termination);
705 static bool insn_must_be_first_in_group (rtx);
706 static bool insn_must_be_last_in_group (rtx);
707 static bool is_costly_group (rtx *, rtx);
708 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
709 static int redefine_groups (FILE *, int, rtx, rtx);
710 static int pad_groups (FILE *, int, rtx, rtx);
711 static void rs6000_sched_finish (FILE *, int);
712 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
713 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
714 static int rs6000_use_sched_lookahead (void);
715 static int rs6000_use_sched_lookahead_guard (rtx);
716 static tree rs6000_builtin_mask_for_load (void);
717 static tree rs6000_builtin_mul_widen_even (tree);
718 static tree rs6000_builtin_mul_widen_odd (tree);
719 static tree rs6000_builtin_conversion (enum tree_code, tree);
721 static void def_builtin (int, const char *, tree, int);
722 static void rs6000_init_builtins (void);
723 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
725 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
726 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
727 static void altivec_init_builtins (void);
728 static void rs6000_common_init_builtins (void);
729 static void rs6000_init_libfuncs (void);
731 static void enable_mask_for_builtins (struct builtin_description *, int,
732 enum rs6000_builtins,
733 enum rs6000_builtins);
734 static tree build_opaque_vector_type (tree, int);
735 static void spe_init_builtins (void);
736 static rtx spe_expand_builtin (tree, rtx, bool *);
737 static rtx spe_expand_stv_builtin (enum insn_code, tree);
738 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
739 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
740 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
741 static rs6000_stack_t *rs6000_stack_info (void);
742 static void debug_stack_info (rs6000_stack_t *);
744 static rtx altivec_expand_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
747 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
748 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
749 static rtx altivec_expand_predicate_builtin (enum insn_code,
750 const char *, tree, rtx);
751 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
752 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
753 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
754 static rtx altivec_expand_vec_set_builtin (tree);
755 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
756 static int get_element_number (tree, tree);
757 static bool rs6000_handle_option (size_t, const char *, int);
758 static void rs6000_parse_tls_size_option (void);
759 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
760 static int first_altivec_reg_to_save (void);
761 static unsigned int compute_vrsave_mask (void);
762 static void compute_save_world_info (rs6000_stack_t *info_ptr);
763 static void is_altivec_return_reg (rtx, void *);
764 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
765 int easy_vector_constant (rtx, enum machine_mode);
766 static bool rs6000_is_opaque_type (tree);
767 static rtx rs6000_dwarf_register_span (rtx);
768 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
769 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
770 static rtx rs6000_tls_get_addr (void);
771 static rtx rs6000_got_sym (void);
772 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
773 static const char *rs6000_get_some_local_dynamic_name (void);
774 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
775 static rtx rs6000_complex_function_value (enum machine_mode);
776 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
777 enum machine_mode, tree);
778 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
780 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
781 tree, HOST_WIDE_INT);
782 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
785 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
788 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
789 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
790 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
791 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
792 enum machine_mode, tree,
794 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
796 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
798 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
800 static void macho_branch_islands (void);
801 static int no_previous_def (tree function_name);
802 static tree get_prev_label (tree function_name);
803 static void rs6000_darwin_file_start (void);
806 static tree rs6000_build_builtin_va_list (void);
807 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
808 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
809 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
810 static bool rs6000_vector_mode_supported_p (enum machine_mode);
811 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
813 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
815 static int get_vsel_insn (enum machine_mode);
816 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
817 static tree rs6000_stack_protect_fail (void);
819 const int INSN_NOT_AVAILABLE = -1;
820 static enum machine_mode rs6000_eh_return_filter_mode (void);
822 /* Hash table stuff for keeping track of TOC entries. */
824 struct toc_hash_struct GTY(())
826 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
827 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
829 enum machine_mode key_mode;
833 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
835 /* Default register names. */
836 char rs6000_reg_names[][8] =
838 "0", "1", "2", "3", "4", "5", "6", "7",
839 "8", "9", "10", "11", "12", "13", "14", "15",
840 "16", "17", "18", "19", "20", "21", "22", "23",
841 "24", "25", "26", "27", "28", "29", "30", "31",
842 "0", "1", "2", "3", "4", "5", "6", "7",
843 "8", "9", "10", "11", "12", "13", "14", "15",
844 "16", "17", "18", "19", "20", "21", "22", "23",
845 "24", "25", "26", "27", "28", "29", "30", "31",
846 "mq", "lr", "ctr","ap",
847 "0", "1", "2", "3", "4", "5", "6", "7",
849 /* AltiVec registers. */
850 "0", "1", "2", "3", "4", "5", "6", "7",
851 "8", "9", "10", "11", "12", "13", "14", "15",
852 "16", "17", "18", "19", "20", "21", "22", "23",
853 "24", "25", "26", "27", "28", "29", "30", "31",
856 "spe_acc", "spefscr",
857 /* Soft frame pointer. */
861 #ifdef TARGET_REGNAMES
862 static const char alt_reg_names[][8] =
864 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
865 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
866 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
867 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
868 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
869 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
870 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
871 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
872 "mq", "lr", "ctr", "ap",
873 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
875 /* AltiVec registers. */
876 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
877 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
878 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
879 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
882 "spe_acc", "spefscr",
883 /* Soft frame pointer. */
888 #ifndef MASK_STRICT_ALIGN
889 #define MASK_STRICT_ALIGN 0
891 #ifndef TARGET_PROFILE_KERNEL
892 #define TARGET_PROFILE_KERNEL 0
895 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
896 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
898 /* Initialize the GCC target structure. */
899 #undef TARGET_ATTRIBUTE_TABLE
900 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
901 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
902 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
904 #undef TARGET_ASM_ALIGNED_DI_OP
905 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
907 /* Default unaligned ops are only provided for ELF. Find the ops needed
908 for non-ELF systems. */
909 #ifndef OBJECT_FORMAT_ELF
911 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
913 #undef TARGET_ASM_UNALIGNED_HI_OP
914 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
915 #undef TARGET_ASM_UNALIGNED_SI_OP
916 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
917 #undef TARGET_ASM_UNALIGNED_DI_OP
918 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
921 #undef TARGET_ASM_UNALIGNED_HI_OP
922 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
923 #undef TARGET_ASM_UNALIGNED_SI_OP
924 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
925 #undef TARGET_ASM_UNALIGNED_DI_OP
926 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
927 #undef TARGET_ASM_ALIGNED_DI_OP
928 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
932 /* This hook deals with fixups for relocatable code and DI-mode objects
934 #undef TARGET_ASM_INTEGER
935 #define TARGET_ASM_INTEGER rs6000_assemble_integer
937 #ifdef HAVE_GAS_HIDDEN
938 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
939 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
942 #undef TARGET_HAVE_TLS
943 #define TARGET_HAVE_TLS HAVE_AS_TLS
945 #undef TARGET_CANNOT_FORCE_CONST_MEM
946 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
948 #undef TARGET_ASM_FUNCTION_PROLOGUE
949 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
950 #undef TARGET_ASM_FUNCTION_EPILOGUE
951 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
953 #undef TARGET_SCHED_VARIABLE_ISSUE
954 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
956 #undef TARGET_SCHED_ISSUE_RATE
957 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
958 #undef TARGET_SCHED_ADJUST_COST
959 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
960 #undef TARGET_SCHED_ADJUST_PRIORITY
961 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
962 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
963 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
964 #undef TARGET_SCHED_INIT
965 #define TARGET_SCHED_INIT rs6000_sched_init
966 #undef TARGET_SCHED_FINISH
967 #define TARGET_SCHED_FINISH rs6000_sched_finish
968 #undef TARGET_SCHED_REORDER
969 #define TARGET_SCHED_REORDER rs6000_sched_reorder
970 #undef TARGET_SCHED_REORDER2
971 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
973 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
974 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
976 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
977 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
979 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
980 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
981 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
982 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
983 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
984 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
985 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
986 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
988 #undef TARGET_INIT_BUILTINS
989 #define TARGET_INIT_BUILTINS rs6000_init_builtins
991 #undef TARGET_EXPAND_BUILTIN
992 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
994 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
995 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
997 #undef TARGET_INIT_LIBFUNCS
998 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1001 #undef TARGET_BINDS_LOCAL_P
1002 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1005 #undef TARGET_MS_BITFIELD_LAYOUT_P
1006 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1008 #undef TARGET_ASM_OUTPUT_MI_THUNK
1009 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1011 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1012 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1014 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1015 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1017 #undef TARGET_INVALID_WITHIN_DOLOOP
1018 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1020 #undef TARGET_RTX_COSTS
1021 #define TARGET_RTX_COSTS rs6000_rtx_costs
1022 #undef TARGET_ADDRESS_COST
1023 #define TARGET_ADDRESS_COST hook_int_rtx_0
1025 #undef TARGET_VECTOR_OPAQUE_P
1026 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1028 #undef TARGET_DWARF_REGISTER_SPAN
1029 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1031 /* On rs6000, function arguments are promoted, as are function return
1033 #undef TARGET_PROMOTE_FUNCTION_ARGS
1034 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1035 #undef TARGET_PROMOTE_FUNCTION_RETURN
1036 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1038 #undef TARGET_RETURN_IN_MEMORY
1039 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1041 #undef TARGET_SETUP_INCOMING_VARARGS
1042 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1044 /* Always strict argument naming on rs6000. */
1045 #undef TARGET_STRICT_ARGUMENT_NAMING
1046 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1047 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1048 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1049 #undef TARGET_SPLIT_COMPLEX_ARG
1050 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1051 #undef TARGET_MUST_PASS_IN_STACK
1052 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1053 #undef TARGET_PASS_BY_REFERENCE
1054 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1055 #undef TARGET_ARG_PARTIAL_BYTES
1056 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1058 #undef TARGET_BUILD_BUILTIN_VA_LIST
1059 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1061 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1062 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1064 #undef TARGET_EH_RETURN_FILTER_MODE
1065 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1067 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1068 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1070 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1071 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1073 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1074 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1076 #undef TARGET_HANDLE_OPTION
1077 #define TARGET_HANDLE_OPTION rs6000_handle_option
1079 #undef TARGET_DEFAULT_TARGET_FLAGS
1080 #define TARGET_DEFAULT_TARGET_FLAGS \
1083 #undef TARGET_STACK_PROTECT_FAIL
1084 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1086 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1087 The PowerPC architecture requires only weak consistency among
1088 processors--that is, memory accesses between processors need not be
1089 sequentially consistent and memory accesses among processors can occur
1090 in any order. The ability to order memory accesses weakly provides
1091 opportunities for more efficient use of the system bus. Unless a
1092 dependency exists, the 604e allows read operations to precede store
1094 #undef TARGET_RELAXED_ORDERING
1095 #define TARGET_RELAXED_ORDERING true
1098 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1099 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1102 /* Use a 32-bit anchor range. This leads to sequences like:
1104 addis tmp,anchor,high
1107 where tmp itself acts as an anchor, and can be shared between
1108 accesses to the same 64k page. */
1109 #undef TARGET_MIN_ANCHOR_OFFSET
1110 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1111 #undef TARGET_MAX_ANCHOR_OFFSET
1112 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1113 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1114 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1116 struct gcc_target targetm = TARGET_INITIALIZER;
1119 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1122 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1124 /* The GPRs can hold any mode, but values bigger than one register
1125 cannot go past R31. */
1126 if (INT_REGNO_P (regno))
1127 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1129 /* The float registers can only hold floating modes and DImode.
1130 This also excludes decimal float modes. */
1131 if (FP_REGNO_P (regno))
1133 (SCALAR_FLOAT_MODE_P (mode)
1134 && !DECIMAL_FLOAT_MODE_P (mode)
1135 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1136 || (GET_MODE_CLASS (mode) == MODE_INT
1137 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1139 /* The CR register can only hold CC modes. */
1140 if (CR_REGNO_P (regno))
1141 return GET_MODE_CLASS (mode) == MODE_CC;
1143 if (XER_REGNO_P (regno))
1144 return mode == PSImode;
1146 /* AltiVec only in AldyVec registers. */
1147 if (ALTIVEC_REGNO_P (regno))
1148 return ALTIVEC_VECTOR_MODE (mode);
1150 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1151 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1154 /* We cannot put TImode anywhere except general register and it must be
1155 able to fit within the register set. */
1157 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1160 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1162 rs6000_init_hard_regno_mode_ok (void)
1166 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1167 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1168 if (rs6000_hard_regno_mode_ok (r, m))
1169 rs6000_hard_regno_mode_ok_p[m][r] = true;
1173 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1176 darwin_rs6000_override_options (void)
1178 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1180 rs6000_altivec_abi = 1;
1181 TARGET_ALTIVEC_VRSAVE = 1;
1182 if (DEFAULT_ABI == ABI_DARWIN)
1184 if (MACHO_DYNAMIC_NO_PIC_P)
1187 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1190 else if (flag_pic == 1)
1195 if (TARGET_64BIT && ! TARGET_POWERPC64)
1197 target_flags |= MASK_POWERPC64;
1198 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1202 rs6000_default_long_calls = 1;
1203 target_flags |= MASK_SOFT_FLOAT;
1206 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1208 if (!flag_mkernel && !flag_apple_kext
1210 && ! (target_flags_explicit & MASK_ALTIVEC))
1211 target_flags |= MASK_ALTIVEC;
1213 /* Unless the user (not the configurer) has explicitly overridden
1214 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1215 G4 unless targetting the kernel. */
1218 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1219 && ! (target_flags_explicit & MASK_ALTIVEC)
1220 && ! rs6000_select[1].string)
1222 target_flags |= MASK_ALTIVEC;
1227 /* If not otherwise specified by a target, make 'long double' equivalent to
1230 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1231 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1234 /* Override command line options. Mostly we process the processor
1235 type and sometimes adjust other TARGET_ options. */
1238 rs6000_override_options (const char *default_cpu)
1241 struct rs6000_cpu_select *ptr;
1244 /* Simplifications for entries below. */
1247 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1248 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1251 /* This table occasionally claims that a processor does not support
1252 a particular feature even though it does, but the feature is slower
1253 than the alternative. Thus, it shouldn't be relied on as a
1254 complete description of the processor's support.
1256 Please keep this list in order, and don't forget to update the
1257 documentation in invoke.texi when adding a new processor or
1261 const char *const name; /* Canonical processor name. */
1262 const enum processor_type processor; /* Processor type enum value. */
1263 const int target_enable; /* Target flags to enable. */
1264 } const processor_target_table[]
1265 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1266 {"403", PROCESSOR_PPC403,
1267 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1268 {"405", PROCESSOR_PPC405,
1269 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1270 {"405fp", PROCESSOR_PPC405,
1271 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1272 {"440", PROCESSOR_PPC440,
1273 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1274 {"440fp", PROCESSOR_PPC440,
1275 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1276 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1277 {"601", PROCESSOR_PPC601,
1278 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1279 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1280 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1281 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1282 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1283 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1284 {"620", PROCESSOR_PPC620,
1285 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1286 {"630", PROCESSOR_PPC630,
1287 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1288 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1289 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1290 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1291 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1292 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1293 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1294 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1295 {"8540", PROCESSOR_PPC8540,
1296 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1297 /* 8548 has a dummy entry for now. */
1298 {"8548", PROCESSOR_PPC8540,
1299 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1300 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1301 {"970", PROCESSOR_POWER4,
1302 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1303 {"cell", PROCESSOR_CELL,
1304 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1305 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1306 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1307 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1308 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1309 {"G5", PROCESSOR_POWER4,
1310 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1311 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1312 {"power2", PROCESSOR_POWER,
1313 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1314 {"power3", PROCESSOR_PPC630,
1315 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1316 {"power4", PROCESSOR_POWER4,
1317 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1318 {"power5", PROCESSOR_POWER5,
1319 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1320 | MASK_MFCRF | MASK_POPCNTB},
1321 {"power5+", PROCESSOR_POWER5,
1322 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1323 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1324 {"power6", PROCESSOR_POWER6,
1325 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1327 {"power6x", PROCESSOR_POWER6,
1328 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1329 | MASK_FPRND | MASK_MFPGPR},
1330 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1331 {"powerpc64", PROCESSOR_POWERPC64,
1332 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1333 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1334 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1335 {"rios2", PROCESSOR_RIOS2,
1336 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1337 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1338 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1339 {"rs64", PROCESSOR_RS64A,
1340 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1343 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1345 /* Some OSs don't support saving the high part of 64-bit registers on
1346 context switch. Other OSs don't support saving Altivec registers.
1347 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1348 settings; if the user wants either, the user must explicitly specify
1349 them and we won't interfere with the user's specification. */
1352 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1353 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1354 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1355 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1356 | MASK_DLMZB | MASK_MFPGPR)
1359 rs6000_init_hard_regno_mode_ok ();
1361 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1362 #ifdef OS_MISSING_POWERPC64
1363 if (OS_MISSING_POWERPC64)
1364 set_masks &= ~MASK_POWERPC64;
1366 #ifdef OS_MISSING_ALTIVEC
1367 if (OS_MISSING_ALTIVEC)
1368 set_masks &= ~MASK_ALTIVEC;
1371 /* Don't override by the processor default if given explicitly. */
1372 set_masks &= ~target_flags_explicit;
1374 /* Identify the processor type. */
1375 rs6000_select[0].string = default_cpu;
1376 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1378 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1380 ptr = &rs6000_select[i];
1381 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1383 for (j = 0; j < ptt_size; j++)
1384 if (! strcmp (ptr->string, processor_target_table[j].name))
1386 if (ptr->set_tune_p)
1387 rs6000_cpu = processor_target_table[j].processor;
1389 if (ptr->set_arch_p)
1391 target_flags &= ~set_masks;
1392 target_flags |= (processor_target_table[j].target_enable
1399 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1406 /* If we are optimizing big endian systems for space, use the load/store
1407 multiple and string instructions. */
1408 if (BYTES_BIG_ENDIAN && optimize_size)
1409 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1411 /* Don't allow -mmultiple or -mstring on little endian systems
1412 unless the cpu is a 750, because the hardware doesn't support the
1413 instructions used in little endian mode, and causes an alignment
1414 trap. The 750 does not cause an alignment trap (except when the
1415 target is unaligned). */
1417 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1419 if (TARGET_MULTIPLE)
1421 target_flags &= ~MASK_MULTIPLE;
1422 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1423 warning (0, "-mmultiple is not supported on little endian systems");
1428 target_flags &= ~MASK_STRING;
1429 if ((target_flags_explicit & MASK_STRING) != 0)
1430 warning (0, "-mstring is not supported on little endian systems");
1434 /* Set debug flags */
1435 if (rs6000_debug_name)
1437 if (! strcmp (rs6000_debug_name, "all"))
1438 rs6000_debug_stack = rs6000_debug_arg = 1;
1439 else if (! strcmp (rs6000_debug_name, "stack"))
1440 rs6000_debug_stack = 1;
1441 else if (! strcmp (rs6000_debug_name, "arg"))
1442 rs6000_debug_arg = 1;
1444 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1447 if (rs6000_traceback_name)
1449 if (! strncmp (rs6000_traceback_name, "full", 4))
1450 rs6000_traceback = traceback_full;
1451 else if (! strncmp (rs6000_traceback_name, "part", 4))
1452 rs6000_traceback = traceback_part;
1453 else if (! strncmp (rs6000_traceback_name, "no", 2))
1454 rs6000_traceback = traceback_none;
1456 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1457 rs6000_traceback_name);
1460 if (!rs6000_explicit_options.long_double)
1461 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1463 #ifndef POWERPC_LINUX
1464 if (!rs6000_explicit_options.ieee)
1465 rs6000_ieeequad = 1;
1468 /* Set Altivec ABI as default for powerpc64 linux. */
1469 if (TARGET_ELF && TARGET_64BIT)
1471 rs6000_altivec_abi = 1;
1472 TARGET_ALTIVEC_VRSAVE = 1;
1475 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1476 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1478 rs6000_darwin64_abi = 1;
1480 darwin_one_byte_bool = 1;
1482 /* Default to natural alignment, for better performance. */
1483 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1486 /* Place FP constants in the constant pool instead of TOC
1487 if section anchors enabled. */
1488 if (flag_section_anchors)
1489 TARGET_NO_FP_IN_TOC = 1;
1491 /* Handle -mtls-size option. */
1492 rs6000_parse_tls_size_option ();
1494 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1495 SUBTARGET_OVERRIDE_OPTIONS;
1497 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1498 SUBSUBTARGET_OVERRIDE_OPTIONS;
1500 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1501 SUB3TARGET_OVERRIDE_OPTIONS;
1506 /* The e500 does not have string instructions, and we set
1507 MASK_STRING above when optimizing for size. */
1508 if ((target_flags & MASK_STRING) != 0)
1509 target_flags = target_flags & ~MASK_STRING;
1511 else if (rs6000_select[1].string != NULL)
1513 /* For the powerpc-eabispe configuration, we set all these by
1514 default, so let's unset them if we manually set another
1515 CPU that is not the E500. */
1516 if (!rs6000_explicit_options.abi)
1518 if (!rs6000_explicit_options.spe)
1520 if (!rs6000_explicit_options.float_gprs)
1521 rs6000_float_gprs = 0;
1522 if (!rs6000_explicit_options.isel)
1526 /* Detect invalid option combinations with E500. */
1529 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1530 && rs6000_cpu != PROCESSOR_POWER5
1531 && rs6000_cpu != PROCESSOR_POWER6
1532 && rs6000_cpu != PROCESSOR_CELL);
1533 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1534 || rs6000_cpu == PROCESSOR_POWER5);
1535 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1536 || rs6000_cpu == PROCESSOR_POWER5
1537 || rs6000_cpu == PROCESSOR_POWER6);
1539 rs6000_sched_restricted_insns_priority
1540 = (rs6000_sched_groups ? 1 : 0);
1542 /* Handle -msched-costly-dep option. */
1543 rs6000_sched_costly_dep
1544 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1546 if (rs6000_sched_costly_dep_str)
1548 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1549 rs6000_sched_costly_dep = no_dep_costly;
1550 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1551 rs6000_sched_costly_dep = all_deps_costly;
1552 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1553 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1554 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1555 rs6000_sched_costly_dep = store_to_load_dep_costly;
1557 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1560 /* Handle -minsert-sched-nops option. */
1561 rs6000_sched_insert_nops
1562 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1564 if (rs6000_sched_insert_nops_str)
1566 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1567 rs6000_sched_insert_nops = sched_finish_none;
1568 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1569 rs6000_sched_insert_nops = sched_finish_pad_groups;
1570 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1571 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1573 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1576 #ifdef TARGET_REGNAMES
1577 /* If the user desires alternate register names, copy in the
1578 alternate names now. */
1579 if (TARGET_REGNAMES)
1580 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1583 /* Set aix_struct_return last, after the ABI is determined.
1584 If -maix-struct-return or -msvr4-struct-return was explicitly
1585 used, don't override with the ABI default. */
1586 if (!rs6000_explicit_options.aix_struct_ret)
1587 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1589 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1590 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1593 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1595 /* We can only guarantee the availability of DI pseudo-ops when
1596 assembling for 64-bit targets. */
1599 targetm.asm_out.aligned_op.di = NULL;
1600 targetm.asm_out.unaligned_op.di = NULL;
1603 /* Set branch target alignment, if not optimizing for size. */
1606 /* Cell wants to be aligned 8byte for dual issue. */
1607 if (rs6000_cpu == PROCESSOR_CELL)
1609 if (align_functions <= 0)
1610 align_functions = 8;
1611 if (align_jumps <= 0)
1613 if (align_loops <= 0)
1616 if (rs6000_align_branch_targets)
1618 if (align_functions <= 0)
1619 align_functions = 16;
1620 if (align_jumps <= 0)
1622 if (align_loops <= 0)
1625 if (align_jumps_max_skip <= 0)
1626 align_jumps_max_skip = 15;
1627 if (align_loops_max_skip <= 0)
1628 align_loops_max_skip = 15;
1631 /* Arrange to save and restore machine status around nested functions. */
1632 init_machine_status = rs6000_init_machine_status;
1634 /* We should always be splitting complex arguments, but we can't break
1635 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1636 if (DEFAULT_ABI != ABI_AIX)
1637 targetm.calls.split_complex_arg = NULL;
1639 /* Initialize rs6000_cost with the appropriate target costs. */
1641 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1645 case PROCESSOR_RIOS1:
1646 rs6000_cost = &rios1_cost;
1649 case PROCESSOR_RIOS2:
1650 rs6000_cost = &rios2_cost;
1653 case PROCESSOR_RS64A:
1654 rs6000_cost = &rs64a_cost;
1657 case PROCESSOR_MPCCORE:
1658 rs6000_cost = &mpccore_cost;
1661 case PROCESSOR_PPC403:
1662 rs6000_cost = &ppc403_cost;
1665 case PROCESSOR_PPC405:
1666 rs6000_cost = &ppc405_cost;
1669 case PROCESSOR_PPC440:
1670 rs6000_cost = &ppc440_cost;
1673 case PROCESSOR_PPC601:
1674 rs6000_cost = &ppc601_cost;
1677 case PROCESSOR_PPC603:
1678 rs6000_cost = &ppc603_cost;
1681 case PROCESSOR_PPC604:
1682 rs6000_cost = &ppc604_cost;
1685 case PROCESSOR_PPC604e:
1686 rs6000_cost = &ppc604e_cost;
1689 case PROCESSOR_PPC620:
1690 rs6000_cost = &ppc620_cost;
1693 case PROCESSOR_PPC630:
1694 rs6000_cost = &ppc630_cost;
1697 case PROCESSOR_CELL:
1698 rs6000_cost = &ppccell_cost;
1701 case PROCESSOR_PPC750:
1702 case PROCESSOR_PPC7400:
1703 rs6000_cost = &ppc750_cost;
1706 case PROCESSOR_PPC7450:
1707 rs6000_cost = &ppc7450_cost;
1710 case PROCESSOR_PPC8540:
1711 rs6000_cost = &ppc8540_cost;
1714 case PROCESSOR_POWER4:
1715 case PROCESSOR_POWER5:
1716 rs6000_cost = &power4_cost;
1719 case PROCESSOR_POWER6:
1720 rs6000_cost = &power6_cost;
1728 /* Implement targetm.vectorize.builtin_mask_for_load. */
1730 rs6000_builtin_mask_for_load (void)
1733 return altivec_builtin_mask_for_load;
1738 /* Implement targetm.vectorize.builtin_conversion. */
1740 rs6000_builtin_conversion (enum tree_code code, tree type)
1742 if (!TARGET_ALTIVEC)
1748 switch (TYPE_MODE (type))
1751 return TYPE_UNSIGNED (type) ?
1752 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1753 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1762 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1764 rs6000_builtin_mul_widen_even (tree type)
1766 if (!TARGET_ALTIVEC)
1769 switch (TYPE_MODE (type))
1772 return TYPE_UNSIGNED (type) ?
1773 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1774 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1777 return TYPE_UNSIGNED (type) ?
1778 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1779 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1785 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1787 rs6000_builtin_mul_widen_odd (tree type)
1789 if (!TARGET_ALTIVEC)
1792 switch (TYPE_MODE (type))
1795 return TYPE_UNSIGNED (type) ?
1796 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1797 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1800 return TYPE_UNSIGNED (type) ?
1801 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1802 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1808 /* Handle generic options of the form -mfoo=yes/no.
1809 NAME is the option name.
1810 VALUE is the option value.
1811 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1812 whether the option value is 'yes' or 'no' respectively. */
1814 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1818 else if (!strcmp (value, "yes"))
1820 else if (!strcmp (value, "no"))
1823 error ("unknown -m%s= option specified: '%s'", name, value);
1826 /* Validate and record the size specified with the -mtls-size option. */
1829 rs6000_parse_tls_size_option (void)
1831 if (rs6000_tls_size_string == 0)
1833 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1834 rs6000_tls_size = 16;
1835 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1836 rs6000_tls_size = 32;
1837 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1838 rs6000_tls_size = 64;
1840 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1844 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1846 if (DEFAULT_ABI == ABI_DARWIN)
1847 /* The Darwin libraries never set errno, so we might as well
1848 avoid calling them when that's the only reason we would. */
1849 flag_errno_math = 0;
1851 /* Double growth factor to counter reduced min jump length. */
1852 set_param_value ("max-grow-copy-bb-insns", 16);
1854 /* Enable section anchors by default.
1855 Skip section anchors for Objective C and Objective C++
1856 until front-ends fixed. */
1857 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1858 flag_section_anchors = 1;
1861 /* Implement TARGET_HANDLE_OPTION. */
1864 rs6000_handle_option (size_t code, const char *arg, int value)
1869 target_flags &= ~(MASK_POWER | MASK_POWER2
1870 | MASK_MULTIPLE | MASK_STRING);
1871 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1872 | MASK_MULTIPLE | MASK_STRING);
1874 case OPT_mno_powerpc:
1875 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1876 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1877 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1878 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1881 target_flags &= ~MASK_MINIMAL_TOC;
1882 TARGET_NO_FP_IN_TOC = 0;
1883 TARGET_NO_SUM_IN_TOC = 0;
1884 target_flags_explicit |= MASK_MINIMAL_TOC;
1885 #ifdef TARGET_USES_SYSV4_OPT
1886 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1887 just the same as -mminimal-toc. */
1888 target_flags |= MASK_MINIMAL_TOC;
1889 target_flags_explicit |= MASK_MINIMAL_TOC;
1893 #ifdef TARGET_USES_SYSV4_OPT
1895 /* Make -mtoc behave like -mminimal-toc. */
1896 target_flags |= MASK_MINIMAL_TOC;
1897 target_flags_explicit |= MASK_MINIMAL_TOC;
1901 #ifdef TARGET_USES_AIX64_OPT
1906 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1907 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1908 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1911 #ifdef TARGET_USES_AIX64_OPT
1916 target_flags &= ~MASK_POWERPC64;
1917 target_flags_explicit |= MASK_POWERPC64;
1920 case OPT_minsert_sched_nops_:
1921 rs6000_sched_insert_nops_str = arg;
1924 case OPT_mminimal_toc:
1927 TARGET_NO_FP_IN_TOC = 0;
1928 TARGET_NO_SUM_IN_TOC = 0;
1935 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1936 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1943 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1944 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1948 case OPT_mpowerpc_gpopt:
1949 case OPT_mpowerpc_gfxopt:
1952 target_flags |= MASK_POWERPC;
1953 target_flags_explicit |= MASK_POWERPC;
1957 case OPT_maix_struct_return:
1958 case OPT_msvr4_struct_return:
1959 rs6000_explicit_options.aix_struct_ret = true;
1963 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1967 rs6000_explicit_options.isel = true;
1968 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1972 rs6000_explicit_options.spe = true;
1973 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1977 rs6000_debug_name = arg;
1980 #ifdef TARGET_USES_SYSV4_OPT
1982 rs6000_abi_name = arg;
1986 rs6000_sdata_name = arg;
1989 case OPT_mtls_size_:
1990 rs6000_tls_size_string = arg;
1993 case OPT_mrelocatable:
1996 target_flags |= MASK_MINIMAL_TOC;
1997 target_flags_explicit |= MASK_MINIMAL_TOC;
1998 TARGET_NO_FP_IN_TOC = 1;
2002 case OPT_mrelocatable_lib:
2005 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2006 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2007 TARGET_NO_FP_IN_TOC = 1;
2011 target_flags &= ~MASK_RELOCATABLE;
2012 target_flags_explicit |= MASK_RELOCATABLE;
2018 if (!strcmp (arg, "altivec"))
2020 rs6000_explicit_options.abi = true;
2021 rs6000_altivec_abi = 1;
2024 else if (! strcmp (arg, "no-altivec"))
2026 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2027 the default for rs6000_spe_abi to be chosen later. */
2028 rs6000_altivec_abi = 0;
2030 else if (! strcmp (arg, "spe"))
2032 rs6000_explicit_options.abi = true;
2034 rs6000_altivec_abi = 0;
2035 if (!TARGET_SPE_ABI)
2036 error ("not configured for ABI: '%s'", arg);
2038 else if (! strcmp (arg, "no-spe"))
2040 rs6000_explicit_options.abi = true;
2044 /* These are here for testing during development only, do not
2045 document in the manual please. */
2046 else if (! strcmp (arg, "d64"))
2048 rs6000_darwin64_abi = 1;
2049 warning (0, "Using darwin64 ABI");
2051 else if (! strcmp (arg, "d32"))
2053 rs6000_darwin64_abi = 0;
2054 warning (0, "Using old darwin ABI");
2057 else if (! strcmp (arg, "ibmlongdouble"))
2059 rs6000_explicit_options.ieee = true;
2060 rs6000_ieeequad = 0;
2061 warning (0, "Using IBM extended precision long double");
2063 else if (! strcmp (arg, "ieeelongdouble"))
2065 rs6000_explicit_options.ieee = true;
2066 rs6000_ieeequad = 1;
2067 warning (0, "Using IEEE extended precision long double");
2072 error ("unknown ABI specified: '%s'", arg);
2078 rs6000_select[1].string = arg;
2082 rs6000_select[2].string = arg;
2085 case OPT_mtraceback_:
2086 rs6000_traceback_name = arg;
2089 case OPT_mfloat_gprs_:
2090 rs6000_explicit_options.float_gprs = true;
2091 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2092 rs6000_float_gprs = 1;
2093 else if (! strcmp (arg, "double"))
2094 rs6000_float_gprs = 2;
2095 else if (! strcmp (arg, "no"))
2096 rs6000_float_gprs = 0;
2099 error ("invalid option for -mfloat-gprs: '%s'", arg);
2104 case OPT_mlong_double_:
2105 rs6000_explicit_options.long_double = true;
2106 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2107 if (value != 64 && value != 128)
2109 error ("Unknown switch -mlong-double-%s", arg);
2110 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2114 rs6000_long_double_type_size = value;
2117 case OPT_msched_costly_dep_:
2118 rs6000_sched_costly_dep_str = arg;
2122 rs6000_explicit_options.alignment = true;
2123 if (! strcmp (arg, "power"))
2125 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2126 some C library functions, so warn about it. The flag may be
2127 useful for performance studies from time to time though, so
2128 don't disable it entirely. */
2129 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2130 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2131 " it is incompatible with the installed C and C++ libraries");
2132 rs6000_alignment_flags = MASK_ALIGN_POWER;
2134 else if (! strcmp (arg, "natural"))
2135 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2138 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2146 /* Do anything needed at the start of the asm file. */
2149 rs6000_file_start (void)
2153 const char *start = buffer;
2154 struct rs6000_cpu_select *ptr;
2155 const char *default_cpu = TARGET_CPU_DEFAULT;
2156 FILE *file = asm_out_file;
2158 default_file_start ();
2160 #ifdef TARGET_BI_ARCH
2161 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2165 if (flag_verbose_asm)
2167 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2168 rs6000_select[0].string = default_cpu;
2170 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2172 ptr = &rs6000_select[i];
2173 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2175 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2180 if (PPC405_ERRATUM77)
2182 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2186 #ifdef USING_ELFOS_H
2187 switch (rs6000_sdata)
2189 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2190 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2191 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2192 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2195 if (rs6000_sdata && g_switch_value)
2197 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2207 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2209 switch_to_section (toc_section);
2210 switch_to_section (text_section);
2215 /* Return nonzero if this function is known to have a null epilogue. */
2218 direct_return (void)
2220 if (reload_completed)
2222 rs6000_stack_t *info = rs6000_stack_info ();
2224 if (info->first_gp_reg_save == 32
2225 && info->first_fp_reg_save == 64
2226 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2227 && ! info->lr_save_p
2228 && ! info->cr_save_p
2229 && info->vrsave_mask == 0
2237 /* Return the number of instructions it takes to form a constant in an
2238 integer register. */
2241 num_insns_constant_wide (HOST_WIDE_INT value)
2243 /* signed constant loadable with {cal|addi} */
2244 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2247 /* constant loadable with {cau|addis} */
2248 else if ((value & 0xffff) == 0
2249 && (value >> 31 == -1 || value >> 31 == 0))
2252 #if HOST_BITS_PER_WIDE_INT == 64
2253 else if (TARGET_POWERPC64)
2255 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2256 HOST_WIDE_INT high = value >> 31;
2258 if (high == 0 || high == -1)
2264 return num_insns_constant_wide (high) + 1;
2266 return (num_insns_constant_wide (high)
2267 + num_insns_constant_wide (low) + 1);
2276 num_insns_constant (rtx op, enum machine_mode mode)
2278 HOST_WIDE_INT low, high;
2280 switch (GET_CODE (op))
2283 #if HOST_BITS_PER_WIDE_INT == 64
2284 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2285 && mask64_operand (op, mode))
2289 return num_insns_constant_wide (INTVAL (op));
2297 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2298 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2299 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2302 if (mode == VOIDmode || mode == DImode)
2304 high = CONST_DOUBLE_HIGH (op);
2305 low = CONST_DOUBLE_LOW (op);
2312 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2313 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2314 high = l[WORDS_BIG_ENDIAN == 0];
2315 low = l[WORDS_BIG_ENDIAN != 0];
2319 return (num_insns_constant_wide (low)
2320 + num_insns_constant_wide (high));
2323 if ((high == 0 && low >= 0)
2324 || (high == -1 && low < 0))
2325 return num_insns_constant_wide (low);
2327 else if (mask64_operand (op, mode))
2331 return num_insns_constant_wide (high) + 1;
2334 return (num_insns_constant_wide (high)
2335 + num_insns_constant_wide (low) + 1);
2343 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2344 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2345 corresponding element of the vector, but for V4SFmode and V2SFmode,
2346 the corresponding "float" is interpreted as an SImode integer. */
2348 static HOST_WIDE_INT
2349 const_vector_elt_as_int (rtx op, unsigned int elt)
2351 rtx tmp = CONST_VECTOR_ELT (op, elt);
2352 if (GET_MODE (op) == V4SFmode
2353 || GET_MODE (op) == V2SFmode)
2354 tmp = gen_lowpart (SImode, tmp);
2355 return INTVAL (tmp);
2358 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2359 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2360 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2361 all items are set to the same value and contain COPIES replicas of the
2362 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2363 operand and the others are set to the value of the operand's msb. */
2366 vspltis_constant (rtx op, unsigned step, unsigned copies)
2368 enum machine_mode mode = GET_MODE (op);
2369 enum machine_mode inner = GET_MODE_INNER (mode);
2372 unsigned nunits = GET_MODE_NUNITS (mode);
2373 unsigned bitsize = GET_MODE_BITSIZE (inner);
2374 unsigned mask = GET_MODE_MASK (inner);
2376 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2377 HOST_WIDE_INT splat_val = val;
2378 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2380 /* Construct the value to be splatted, if possible. If not, return 0. */
2381 for (i = 2; i <= copies; i *= 2)
2383 HOST_WIDE_INT small_val;
2385 small_val = splat_val >> bitsize;
2387 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2389 splat_val = small_val;
2392 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2393 if (EASY_VECTOR_15 (splat_val))
2396 /* Also check if we can splat, and then add the result to itself. Do so if
2397 the value is positive, of if the splat instruction is using OP's mode;
2398 for splat_val < 0, the splat and the add should use the same mode. */
2399 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2400 && (splat_val >= 0 || (step == 1 && copies == 1)))
2406 /* Check if VAL is present in every STEP-th element, and the
2407 other elements are filled with its most significant bit. */
2408 for (i = 0; i < nunits - 1; ++i)
2410 HOST_WIDE_INT desired_val;
2411 if (((i + 1) & (step - 1)) == 0)
2414 desired_val = msb_val;
2416 if (desired_val != const_vector_elt_as_int (op, i))
2424 /* Return true if OP is of the given MODE and can be synthesized
2425 with a vspltisb, vspltish or vspltisw. */
2428 easy_altivec_constant (rtx op, enum machine_mode mode)
2430 unsigned step, copies;
2432 if (mode == VOIDmode)
2433 mode = GET_MODE (op);
2434 else if (mode != GET_MODE (op))
2437 /* Start with a vspltisw. */
2438 step = GET_MODE_NUNITS (mode) / 4;
2441 if (vspltis_constant (op, step, copies))
2444 /* Then try with a vspltish. */
2450 if (vspltis_constant (op, step, copies))
2453 /* And finally a vspltisb. */
2459 if (vspltis_constant (op, step, copies))
2465 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2466 result is OP. Abort if it is not possible. */
2469 gen_easy_altivec_constant (rtx op)
2471 enum machine_mode mode = GET_MODE (op);
2472 int nunits = GET_MODE_NUNITS (mode);
2473 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2474 unsigned step = nunits / 4;
2475 unsigned copies = 1;
2477 /* Start with a vspltisw. */
2478 if (vspltis_constant (op, step, copies))
2479 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2481 /* Then try with a vspltish. */
2487 if (vspltis_constant (op, step, copies))
2488 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2490 /* And finally a vspltisb. */
2496 if (vspltis_constant (op, step, copies))
2497 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2503 output_vec_const_move (rtx *operands)
2506 enum machine_mode mode;
2511 mode = GET_MODE (dest);
2516 if (zero_constant (vec, mode))
2517 return "vxor %0,%0,%0";
2519 splat_vec = gen_easy_altivec_constant (vec);
2520 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2521 operands[1] = XEXP (splat_vec, 0);
2522 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2525 switch (GET_MODE (splat_vec))
2528 return "vspltisw %0,%1";
2531 return "vspltish %0,%1";
2534 return "vspltisb %0,%1";
2541 gcc_assert (TARGET_SPE);
2543 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2544 pattern of V1DI, V4HI, and V2SF.
2546 FIXME: We should probably return # and add post reload
2547 splitters for these, but this way is so easy ;-). */
2548 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2549 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2550 operands[1] = CONST_VECTOR_ELT (vec, 0);
2551 operands[2] = CONST_VECTOR_ELT (vec, 1);
2553 return "li %0,%1\n\tevmergelo %0,%0,%0";
2555 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2558 /* Initialize vector TARGET to VALS. */
2561 rs6000_expand_vector_init (rtx target, rtx vals)
2563 enum machine_mode mode = GET_MODE (target);
2564 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2565 int n_elts = GET_MODE_NUNITS (mode);
2566 int n_var = 0, one_var = -1;
2567 bool all_same = true, all_const_zero = true;
2571 for (i = 0; i < n_elts; ++i)
2573 x = XVECEXP (vals, 0, i);
2574 if (!CONSTANT_P (x))
2575 ++n_var, one_var = i;
2576 else if (x != CONST0_RTX (inner_mode))
2577 all_const_zero = false;
2579 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2585 if (mode != V4SFmode && all_const_zero)
2587 /* Zero register. */
2588 emit_insn (gen_rtx_SET (VOIDmode, target,
2589 gen_rtx_XOR (mode, target, target)));
2592 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2594 /* Splat immediate. */
2595 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2599 ; /* Splat vector element. */
2602 /* Load from constant pool. */
2603 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2608 /* Store value to stack temp. Load vector element. Splat. */
2611 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2612 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2613 XVECEXP (vals, 0, 0));
2614 x = gen_rtx_UNSPEC (VOIDmode,
2615 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2616 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2618 gen_rtx_SET (VOIDmode,
2621 x = gen_rtx_VEC_SELECT (inner_mode, target,
2622 gen_rtx_PARALLEL (VOIDmode,
2623 gen_rtvec (1, const0_rtx)));
2624 emit_insn (gen_rtx_SET (VOIDmode, target,
2625 gen_rtx_VEC_DUPLICATE (mode, x)));
2629 /* One field is non-constant. Load constant then overwrite
2633 rtx copy = copy_rtx (vals);
2635 /* Load constant part of vector, substitute neighboring value for
2637 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2638 rs6000_expand_vector_init (target, copy);
2640 /* Insert variable. */
2641 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2645 /* Construct the vector in memory one field at a time
2646 and load the whole vector. */
2647 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2648 for (i = 0; i < n_elts; i++)
2649 emit_move_insn (adjust_address_nv (mem, inner_mode,
2650 i * GET_MODE_SIZE (inner_mode)),
2651 XVECEXP (vals, 0, i));
2652 emit_move_insn (target, mem);
2655 /* Set field ELT of TARGET to VAL. */
2658 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2660 enum machine_mode mode = GET_MODE (target);
2661 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2662 rtx reg = gen_reg_rtx (mode);
2664 int width = GET_MODE_SIZE (inner_mode);
2667 /* Load single variable value. */
2668 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2669 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2670 x = gen_rtx_UNSPEC (VOIDmode,
2671 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2672 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2674 gen_rtx_SET (VOIDmode,
2678 /* Linear sequence. */
2679 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2680 for (i = 0; i < 16; ++i)
2681 XVECEXP (mask, 0, i) = GEN_INT (i);
2683 /* Set permute mask to insert element into target. */
2684 for (i = 0; i < width; ++i)
2685 XVECEXP (mask, 0, elt*width + i)
2686 = GEN_INT (i + 0x10);
2687 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2688 x = gen_rtx_UNSPEC (mode,
2689 gen_rtvec (3, target, reg,
2690 force_reg (V16QImode, x)),
2692 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2695 /* Extract field ELT from VEC into TARGET. */
2698 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2700 enum machine_mode mode = GET_MODE (vec);
2701 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2704 /* Allocate mode-sized buffer. */
2705 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2707 /* Add offset to field within buffer matching vector element. */
2708 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2710 /* Store single field into mode-sized buffer. */
2711 x = gen_rtx_UNSPEC (VOIDmode,
2712 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2713 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2715 gen_rtx_SET (VOIDmode,
2718 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2721 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2722 implement ANDing by the mask IN. */
2724 build_mask64_2_operands (rtx in, rtx *out)
2726 #if HOST_BITS_PER_WIDE_INT >= 64
2727 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2730 gcc_assert (GET_CODE (in) == CONST_INT);
2735 /* Assume c initially something like 0x00fff000000fffff. The idea
2736 is to rotate the word so that the middle ^^^^^^ group of zeros
2737 is at the MS end and can be cleared with an rldicl mask. We then
2738 rotate back and clear off the MS ^^ group of zeros with a
2740 c = ~c; /* c == 0xff000ffffff00000 */
2741 lsb = c & -c; /* lsb == 0x0000000000100000 */
2742 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2743 c = ~c; /* c == 0x00fff000000fffff */
2744 c &= -lsb; /* c == 0x00fff00000000000 */
2745 lsb = c & -c; /* lsb == 0x0000100000000000 */
2746 c = ~c; /* c == 0xff000fffffffffff */
2747 c &= -lsb; /* c == 0xff00000000000000 */
2749 while ((lsb >>= 1) != 0)
2750 shift++; /* shift == 44 on exit from loop */
2751 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2752 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2753 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2757 /* Assume c initially something like 0xff000f0000000000. The idea
2758 is to rotate the word so that the ^^^ middle group of zeros
2759 is at the LS end and can be cleared with an rldicr mask. We then
2760 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2762 lsb = c & -c; /* lsb == 0x0000010000000000 */
2763 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2764 c = ~c; /* c == 0x00fff0ffffffffff */
2765 c &= -lsb; /* c == 0x00fff00000000000 */
2766 lsb = c & -c; /* lsb == 0x0000100000000000 */
2767 c = ~c; /* c == 0xff000fffffffffff */
2768 c &= -lsb; /* c == 0xff00000000000000 */
2770 while ((lsb >>= 1) != 0)
2771 shift++; /* shift == 44 on exit from loop */
2772 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2773 m1 >>= shift; /* m1 == 0x0000000000000fff */
2774 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2777 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2778 masks will be all 1's. We are guaranteed more than one transition. */
2779 out[0] = GEN_INT (64 - shift);
2780 out[1] = GEN_INT (m1);
2781 out[2] = GEN_INT (shift);
2782 out[3] = GEN_INT (m2);
2790 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2793 invalid_e500_subreg (rtx op, enum machine_mode mode)
2795 if (TARGET_E500_DOUBLE)
2797 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2798 subreg:TI and reg:TF. */
2799 if (GET_CODE (op) == SUBREG
2800 && (mode == SImode || mode == DImode || mode == TImode)
2801 && REG_P (SUBREG_REG (op))
2802 && (GET_MODE (SUBREG_REG (op)) == DFmode
2803 || GET_MODE (SUBREG_REG (op)) == TFmode))
2806 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2808 if (GET_CODE (op) == SUBREG
2809 && (mode == DFmode || mode == TFmode)
2810 && REG_P (SUBREG_REG (op))
2811 && (GET_MODE (SUBREG_REG (op)) == DImode
2812 || GET_MODE (SUBREG_REG (op)) == TImode))
2817 && GET_CODE (op) == SUBREG
2819 && REG_P (SUBREG_REG (op))
2820 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2826 /* AIX increases natural record alignment to doubleword if the first
2827 field is an FP double while the FP fields remain word aligned. */
2830 rs6000_special_round_type_align (tree type, unsigned int computed,
2831 unsigned int specified)
2833 unsigned int align = MAX (computed, specified);
2834 tree field = TYPE_FIELDS (type);
2836 /* Skip all non field decls */
2837 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2838 field = TREE_CHAIN (field);
2840 if (field != NULL && field != type)
2842 type = TREE_TYPE (field);
2843 while (TREE_CODE (type) == ARRAY_TYPE)
2844 type = TREE_TYPE (type);
2846 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2847 align = MAX (align, 64);
2853 /* Darwin increases record alignment to the natural alignment of
2857 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2858 unsigned int specified)
2860 unsigned int align = MAX (computed, specified);
2862 if (TYPE_PACKED (type))
2865 /* Find the first field, looking down into aggregates. */
2867 tree field = TYPE_FIELDS (type);
2868 /* Skip all non field decls */
2869 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2870 field = TREE_CHAIN (field);
2873 type = TREE_TYPE (field);
2874 while (TREE_CODE (type) == ARRAY_TYPE)
2875 type = TREE_TYPE (type);
2876 } while (AGGREGATE_TYPE_P (type));
2878 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2879 align = MAX (align, TYPE_ALIGN (type));
2884 /* Return 1 for an operand in small memory on V.4/eabi. */
2887 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2888 enum machine_mode mode ATTRIBUTE_UNUSED)
2893 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2896 if (DEFAULT_ABI != ABI_V4)
2899 if (GET_CODE (op) == SYMBOL_REF)
2902 else if (GET_CODE (op) != CONST
2903 || GET_CODE (XEXP (op, 0)) != PLUS
2904 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2905 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2910 rtx sum = XEXP (op, 0);
2911 HOST_WIDE_INT summand;
2913 /* We have to be careful here, because it is the referenced address
2914 that must be 32k from _SDA_BASE_, not just the symbol. */
2915 summand = INTVAL (XEXP (sum, 1));
2916 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2919 sym_ref = XEXP (sum, 0);
2922 return SYMBOL_REF_SMALL_P (sym_ref);
2928 /* Return true if either operand is a general purpose register. */
2931 gpr_or_gpr_p (rtx op0, rtx op1)
2933 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2934 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2938 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2941 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2943 switch (GET_CODE (op))
2946 if (RS6000_SYMBOL_REF_TLS_P (op))
2948 else if (CONSTANT_POOL_ADDRESS_P (op))
2950 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2958 else if (! strcmp (XSTR (op, 0), toc_label_name))
2967 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2968 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2970 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2979 constant_pool_expr_p (rtx op)
2983 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2987 toc_relative_expr_p (rtx op)
2991 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2995 legitimate_constant_pool_address_p (rtx x)
2998 && GET_CODE (x) == PLUS
2999 && GET_CODE (XEXP (x, 0)) == REG
3000 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3001 && constant_pool_expr_p (XEXP (x, 1)));
3005 legitimate_small_data_p (enum machine_mode mode, rtx x)
3007 return (DEFAULT_ABI == ABI_V4
3008 && !flag_pic && !TARGET_TOC
3009 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3010 && small_data_operand (x, mode));
3013 /* SPE offset addressing is limited to 5-bits worth of double words. */
3014 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3017 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3019 unsigned HOST_WIDE_INT offset, extra;
3021 if (GET_CODE (x) != PLUS)
3023 if (GET_CODE (XEXP (x, 0)) != REG)
3025 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3027 if (legitimate_constant_pool_address_p (x))
3029 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3032 offset = INTVAL (XEXP (x, 1));
3040 /* AltiVec vector modes. Only reg+reg addressing is valid and
3041 constant offset zero should not occur due to canonicalization.
3042 Allow any offset when not strict before reload. */
3049 /* SPE vector modes. */
3050 return SPE_CONST_OFFSET_OK (offset);
3053 if (TARGET_E500_DOUBLE)
3054 return SPE_CONST_OFFSET_OK (offset);
3057 /* On e500v2, we may have:
3059 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3061 Which gets addressed with evldd instructions. */
3062 if (TARGET_E500_DOUBLE)
3063 return SPE_CONST_OFFSET_OK (offset);
3065 if (mode == DFmode || !TARGET_POWERPC64)
3067 else if (offset & 3)
3072 if (TARGET_E500_DOUBLE)
3073 return (SPE_CONST_OFFSET_OK (offset)
3074 && SPE_CONST_OFFSET_OK (offset + 8));
3077 if (mode == TFmode || !TARGET_POWERPC64)
3079 else if (offset & 3)
3090 return (offset < 0x10000) && (offset + extra < 0x10000);
3094 legitimate_indexed_address_p (rtx x, int strict)
3098 if (GET_CODE (x) != PLUS)
3104 /* Recognize the rtl generated by reload which we know will later be
3105 replaced with proper base and index regs. */
3107 && reload_in_progress
3108 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3112 return (REG_P (op0) && REG_P (op1)
3113 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3114 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3115 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3116 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3120 legitimate_indirect_address_p (rtx x, int strict)
3122 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3126 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3128 if (!TARGET_MACHO || !flag_pic
3129 || mode != SImode || GET_CODE (x) != MEM)
3133 if (GET_CODE (x) != LO_SUM)
3135 if (GET_CODE (XEXP (x, 0)) != REG)
3137 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3141 return CONSTANT_P (x);
3145 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3147 if (GET_CODE (x) != LO_SUM)
3149 if (GET_CODE (XEXP (x, 0)) != REG)
3151 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3153 /* Restrict addressing for DI because of our SUBREG hackery. */
3154 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3159 if (TARGET_ELF || TARGET_MACHO)
3161 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3165 if (GET_MODE_NUNITS (mode) != 1)
3167 if (GET_MODE_BITSIZE (mode) > 64
3168 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3169 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3172 return CONSTANT_P (x);
3179 /* Try machine-dependent ways of modifying an illegitimate address
3180 to be legitimate. If we find one, return the new, valid address.
3181 This is used from only one place: `memory_address' in explow.c.
3183 OLDX is the address as it was before break_out_memory_refs was
3184 called. In some cases it is useful to look at this to decide what
3187 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3189 It is always safe for this function to do nothing. It exists to
3190 recognize opportunities to optimize the output.
3192 On RS/6000, first check for the sum of a register with a constant
3193 integer that is out of range. If so, generate code to add the
3194 constant with the low-order 16 bits masked to the register and force
3195 this result into another register (this can be done with `cau').
3196 Then generate an address of REG+(CONST&0xffff), allowing for the
3197 possibility of bit 16 being a one.
3199 Then check for the sum of a register and something not constant, try to
3200 load the other things into a register and return the sum. */
3203 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3204 enum machine_mode mode)
3206 if (GET_CODE (x) == SYMBOL_REF)
3208 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3210 return rs6000_legitimize_tls_address (x, model);
3213 if (GET_CODE (x) == PLUS
3214 && GET_CODE (XEXP (x, 0)) == REG
3215 && GET_CODE (XEXP (x, 1)) == CONST_INT
3216 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3218 HOST_WIDE_INT high_int, low_int;
3220 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3221 high_int = INTVAL (XEXP (x, 1)) - low_int;
3222 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3223 GEN_INT (high_int)), 0);
3224 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3226 else if (GET_CODE (x) == PLUS
3227 && GET_CODE (XEXP (x, 0)) == REG
3228 && GET_CODE (XEXP (x, 1)) != CONST_INT
3229 && GET_MODE_NUNITS (mode) == 1
3230 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3232 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
3234 && (TARGET_POWERPC64 || mode != DImode)
3237 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3238 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3240 else if (ALTIVEC_VECTOR_MODE (mode))
3244 /* Make sure both operands are registers. */
3245 if (GET_CODE (x) == PLUS)
3246 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3247 force_reg (Pmode, XEXP (x, 1)));
3249 reg = force_reg (Pmode, x);
3252 else if (SPE_VECTOR_MODE (mode)
3253 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3254 || mode == DImode)))
3258 /* We accept [reg + reg] and [reg + OFFSET]. */
3260 if (GET_CODE (x) == PLUS)
3262 rtx op1 = XEXP (x, 0);
3263 rtx op2 = XEXP (x, 1);
3265 op1 = force_reg (Pmode, op1);
3267 if (GET_CODE (op2) != REG
3268 && (GET_CODE (op2) != CONST_INT
3269 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3270 op2 = force_reg (Pmode, op2);
3272 return gen_rtx_PLUS (Pmode, op1, op2);
3275 return force_reg (Pmode, x);
3281 && GET_CODE (x) != CONST_INT
3282 && GET_CODE (x) != CONST_DOUBLE
3284 && GET_MODE_NUNITS (mode) == 1
3285 && (GET_MODE_BITSIZE (mode) <= 32
3286 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3288 rtx reg = gen_reg_rtx (Pmode);
3289 emit_insn (gen_elf_high (reg, x));
3290 return gen_rtx_LO_SUM (Pmode, reg, x);
3292 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3295 && ! MACHO_DYNAMIC_NO_PIC_P
3297 && GET_CODE (x) != CONST_INT
3298 && GET_CODE (x) != CONST_DOUBLE
3300 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3304 rtx reg = gen_reg_rtx (Pmode);
3305 emit_insn (gen_macho_high (reg, x));
3306 return gen_rtx_LO_SUM (Pmode, reg, x);
3309 && constant_pool_expr_p (x)
3310 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3312 return create_TOC_reference (x);
3318 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3319 We need to emit DTP-relative relocations. */
3322 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3327 fputs ("\t.long\t", file);
3330 fputs (DOUBLE_INT_ASM_OP, file);
3335 output_addr_const (file, x);
3336 fputs ("@dtprel+0x8000", file);
3339 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3341 static GTY(()) rtx rs6000_tls_symbol;
3343 rs6000_tls_get_addr (void)
3345 if (!rs6000_tls_symbol)
3346 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3348 return rs6000_tls_symbol;
3351 /* Construct the SYMBOL_REF for TLS GOT references. */
3353 static GTY(()) rtx rs6000_got_symbol;
3355 rs6000_got_sym (void)
3357 if (!rs6000_got_symbol)
3359 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3360 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3361 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3364 return rs6000_got_symbol;
3367 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3368 this (thread-local) address. */
3371 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3375 dest = gen_reg_rtx (Pmode);
3376 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3382 tlsreg = gen_rtx_REG (Pmode, 13);
3383 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3387 tlsreg = gen_rtx_REG (Pmode, 2);
3388 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3392 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3396 tmp = gen_reg_rtx (Pmode);
3399 tlsreg = gen_rtx_REG (Pmode, 13);
3400 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3404 tlsreg = gen_rtx_REG (Pmode, 2);
3405 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3409 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3411 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3416 rtx r3, got, tga, tmp1, tmp2, eqv;
3418 /* We currently use relocations like @got@tlsgd for tls, which
3419 means the linker will handle allocation of tls entries, placing
3420 them in the .got section. So use a pointer to the .got section,
3421 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3422 or to secondary GOT sections used by 32-bit -fPIC. */
3424 got = gen_rtx_REG (Pmode, 2);
3428 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3431 rtx gsym = rs6000_got_sym ();
3432 got = gen_reg_rtx (Pmode);
3434 rs6000_emit_move (got, gsym, Pmode);
3437 rtx tempLR, tmp3, mem;
3440 tempLR = gen_reg_rtx (Pmode);
3441 tmp1 = gen_reg_rtx (Pmode);
3442 tmp2 = gen_reg_rtx (Pmode);
3443 tmp3 = gen_reg_rtx (Pmode);
3444 mem = gen_const_mem (Pmode, tmp1);
3446 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3447 emit_move_insn (tmp1, tempLR);
3448 emit_move_insn (tmp2, mem);
3449 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3450 last = emit_move_insn (got, tmp3);
3451 set_unique_reg_note (last, REG_EQUAL, gsym);
3452 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3454 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3460 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3462 r3 = gen_rtx_REG (Pmode, 3);
3464 insn = gen_tls_gd_64 (r3, got, addr);
3466 insn = gen_tls_gd_32 (r3, got, addr);
3469 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3470 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3471 insn = emit_call_insn (insn);
3472 CONST_OR_PURE_CALL_P (insn) = 1;
3473 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3474 insn = get_insns ();
3476 emit_libcall_block (insn, dest, r3, addr);
3478 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3480 r3 = gen_rtx_REG (Pmode, 3);
3482 insn = gen_tls_ld_64 (r3, got);
3484 insn = gen_tls_ld_32 (r3, got);
3487 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3488 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3489 insn = emit_call_insn (insn);
3490 CONST_OR_PURE_CALL_P (insn) = 1;
3491 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3492 insn = get_insns ();
3494 tmp1 = gen_reg_rtx (Pmode);
3495 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3497 emit_libcall_block (insn, tmp1, r3, eqv);
3498 if (rs6000_tls_size == 16)
3501 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3503 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3505 else if (rs6000_tls_size == 32)
3507 tmp2 = gen_reg_rtx (Pmode);
3509 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3511 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3514 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3516 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3520 tmp2 = gen_reg_rtx (Pmode);
3522 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3524 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3526 insn = gen_rtx_SET (Pmode, dest,
3527 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3533 /* IE, or 64 bit offset LE. */
3534 tmp2 = gen_reg_rtx (Pmode);
3536 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3538 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3541 insn = gen_tls_tls_64 (dest, tmp2, addr);
3543 insn = gen_tls_tls_32 (dest, tmp2, addr);
3551 /* Return 1 if X contains a thread-local symbol. */
3554 rs6000_tls_referenced_p (rtx x)
3556 if (! TARGET_HAVE_TLS)
3559 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3562 /* Return 1 if *X is a thread-local symbol. This is the same as
3563 rs6000_tls_symbol_ref except for the type of the unused argument. */
3566 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3568 return RS6000_SYMBOL_REF_TLS_P (*x);
3571 /* The convention appears to be to define this wherever it is used.
3572 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3573 is now used here. */
3574 #ifndef REG_MODE_OK_FOR_BASE_P
3575 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3578 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3579 replace the input X, or the original X if no replacement is called for.
3580 The output parameter *WIN is 1 if the calling macro should goto WIN,
3583 For RS/6000, we wish to handle large displacements off a base
3584 register by splitting the addend across an addiu/addis and the mem insn.
3585 This cuts number of extra insns needed from 3 to 1.
3587 On Darwin, we use this to generate code for floating point constants.
3588 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3589 The Darwin code is inside #if TARGET_MACHO because only then is
3590 machopic_function_base_name() defined. */
3592 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3593 int opnum, int type,
3594 int ind_levels ATTRIBUTE_UNUSED, int *win)
3596 /* We must recognize output that we have already generated ourselves. */
3597 if (GET_CODE (x) == PLUS
3598 && GET_CODE (XEXP (x, 0)) == PLUS
3599 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3600 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3601 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3603 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3604 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3605 opnum, (enum reload_type)type);
3611 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3612 && GET_CODE (x) == LO_SUM
3613 && GET_CODE (XEXP (x, 0)) == PLUS
3614 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3615 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3616 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3617 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3618 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3619 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3620 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3622 /* Result of previous invocation of this function on Darwin
3623 floating point constant. */
3624 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3625 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3626 opnum, (enum reload_type)type);
3632 /* Force ld/std non-word aligned offset into base register by wrapping
3634 if (GET_CODE (x) == PLUS
3635 && GET_CODE (XEXP (x, 0)) == REG
3636 && REGNO (XEXP (x, 0)) < 32
3637 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3638 && GET_CODE (XEXP (x, 1)) == CONST_INT
3639 && (INTVAL (XEXP (x, 1)) & 3) != 0
3640 && !ALTIVEC_VECTOR_MODE (mode)
3641 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3642 && TARGET_POWERPC64)
3644 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3645 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3646 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3647 opnum, (enum reload_type) type);
3652 if (GET_CODE (x) == PLUS
3653 && GET_CODE (XEXP (x, 0)) == REG
3654 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3655 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3656 && GET_CODE (XEXP (x, 1)) == CONST_INT
3657 && !SPE_VECTOR_MODE (mode)
3658 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3660 && !ALTIVEC_VECTOR_MODE (mode))
3662 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3663 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3665 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3667 /* Check for 32-bit overflow. */
3668 if (high + low != val)
3674 /* Reload the high part into a base reg; leave the low part
3675 in the mem directly. */
3677 x = gen_rtx_PLUS (GET_MODE (x),
3678 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3682 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3683 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3684 opnum, (enum reload_type)type);
3689 if (GET_CODE (x) == SYMBOL_REF
3690 && !ALTIVEC_VECTOR_MODE (mode)
3691 && !SPE_VECTOR_MODE (mode)
3693 && DEFAULT_ABI == ABI_DARWIN
3694 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3696 && DEFAULT_ABI == ABI_V4
3699 /* Don't do this for TFmode, since the result isn't offsettable.
3700 The same goes for DImode without 64-bit gprs and DFmode
3703 && (mode != DImode || TARGET_POWERPC64)
3704 && (mode != DFmode || TARGET_POWERPC64
3705 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3710 rtx offset = gen_rtx_CONST (Pmode,
3711 gen_rtx_MINUS (Pmode, x,
3712 machopic_function_base_sym ()));
3713 x = gen_rtx_LO_SUM (GET_MODE (x),
3714 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3715 gen_rtx_HIGH (Pmode, offset)), offset);
3719 x = gen_rtx_LO_SUM (GET_MODE (x),
3720 gen_rtx_HIGH (Pmode, x), x);
3722 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3723 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3724 opnum, (enum reload_type)type);
3729 /* Reload an offset address wrapped by an AND that represents the
3730 masking of the lower bits. Strip the outer AND and let reload
3731 convert the offset address into an indirect address. */
3733 && ALTIVEC_VECTOR_MODE (mode)
3734 && GET_CODE (x) == AND
3735 && GET_CODE (XEXP (x, 0)) == PLUS
3736 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3737 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3738 && GET_CODE (XEXP (x, 1)) == CONST_INT
3739 && INTVAL (XEXP (x, 1)) == -16)
3747 && constant_pool_expr_p (x)
3748 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3750 x = create_TOC_reference (x);
3758 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3759 that is a valid memory address for an instruction.
3760 The MODE argument is the machine mode for the MEM expression
3761 that wants to use this address.
3763 On the RS/6000, there are four valid address: a SYMBOL_REF that
3764 refers to a constant pool entry of an address (or the sum of it
3765 plus a constant), a short (16-bit signed) constant plus a register,
3766 the sum of two registers, or a register indirect, possibly with an
3767 auto-increment. For DFmode and DImode with a constant plus register,
3768 we must ensure that both words are addressable or PowerPC64 with offset
3771 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3772 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3773 adjacent memory cells are accessed by adding word-sized offsets
3774 during assembly output. */
3776 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3778 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3780 && ALTIVEC_VECTOR_MODE (mode)
3781 && GET_CODE (x) == AND
3782 && GET_CODE (XEXP (x, 1)) == CONST_INT
3783 && INTVAL (XEXP (x, 1)) == -16)
3786 if (RS6000_SYMBOL_REF_TLS_P (x))
3788 if (legitimate_indirect_address_p (x, reg_ok_strict))
3790 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3791 && !ALTIVEC_VECTOR_MODE (mode)
3792 && !SPE_VECTOR_MODE (mode)
3794 /* Restrict addressing for DI because of our SUBREG hackery. */
3795 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3798 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3800 if (legitimate_small_data_p (mode, x))
3802 if (legitimate_constant_pool_address_p (x))
3804 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3806 && GET_CODE (x) == PLUS
3807 && GET_CODE (XEXP (x, 0)) == REG
3808 && (XEXP (x, 0) == virtual_stack_vars_rtx
3809 || XEXP (x, 0) == arg_pointer_rtx)
3810 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3812 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3816 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3818 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3819 && (TARGET_POWERPC64 || mode != DImode)
3820 && legitimate_indexed_address_p (x, reg_ok_strict))
3822 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3827 /* Go to LABEL if ADDR (a legitimate address expression)
3828 has an effect that depends on the machine mode it is used for.
3830 On the RS/6000 this is true of all integral offsets (since AltiVec
3831 modes don't allow them) or is a pre-increment or decrement.
3833 ??? Except that due to conceptual problems in offsettable_address_p
3834 we can't really report the problems of integral offsets. So leave
3835 this assuming that the adjustable offset must be valid for the
3836 sub-words of a TFmode operand, which is what we had before. */
3839 rs6000_mode_dependent_address (rtx addr)
3841 switch (GET_CODE (addr))
3844 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3846 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3847 return val + 12 + 0x8000 >= 0x10000;
3854 /* Auto-increment cases are now treated generically in recog.c. */
3863 /* More elaborate version of recog's offsettable_memref_p predicate
3864 that works around the ??? note of rs6000_mode_dependent_address.
3865 In particular it accepts
3867 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3869 in 32-bit mode, that the recog predicate rejects. */
3872 rs6000_offsettable_memref_p (rtx op)
3877 /* First mimic offsettable_memref_p. */
3878 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3881 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3882 the latter predicate knows nothing about the mode of the memory
3883 reference and, therefore, assumes that it is the largest supported
3884 mode (TFmode). As a consequence, legitimate offsettable memory
3885 references are rejected. rs6000_legitimate_offset_address_p contains
3886 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3887 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3890 /* Return number of consecutive hard regs needed starting at reg REGNO
3891 to hold something of mode MODE.
3892 This is ordinarily the length in words of a value of mode MODE
3893 but can be less for certain modes in special long registers.
3895 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3896 scalar instructions. The upper 32 bits are only available to the
3899 POWER and PowerPC GPRs hold 32 bits worth;
3900 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3903 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3905 if (FP_REGNO_P (regno))
3906 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3908 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3909 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3911 if (ALTIVEC_REGNO_P (regno))
3913 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3915 /* The value returned for SCmode in the E500 double case is 2 for
3916 ABI compatibility; storing an SCmode value in a single register
3917 would require function_arg and rs6000_spe_function_arg to handle
3918 SCmode so as to pass the value correctly in a pair of
3920 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3921 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3923 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3926 /* Change register usage conditional on target flags. */
3928 rs6000_conditional_register_usage (void)
3932 /* Set MQ register fixed (already call_used) if not POWER
3933 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3938 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3940 fixed_regs[13] = call_used_regs[13]
3941 = call_really_used_regs[13] = 1;
3943 /* Conditionally disable FPRs. */
3944 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3945 for (i = 32; i < 64; i++)
3946 fixed_regs[i] = call_used_regs[i]
3947 = call_really_used_regs[i] = 1;
3949 /* The TOC register is not killed across calls in a way that is
3950 visible to the compiler. */
3951 if (DEFAULT_ABI == ABI_AIX)
3952 call_really_used_regs[2] = 0;
3954 if (DEFAULT_ABI == ABI_V4
3955 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3957 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3959 if (DEFAULT_ABI == ABI_V4
3960 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3962 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3963 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3964 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3966 if (DEFAULT_ABI == ABI_DARWIN
3967 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3968 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3969 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3970 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3972 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3973 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3974 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3977 global_regs[VSCR_REGNO] = 1;
3981 global_regs[SPEFSCR_REGNO] = 1;
3982 fixed_regs[FIXED_SCRATCH]
3983 = call_used_regs[FIXED_SCRATCH]
3984 = call_really_used_regs[FIXED_SCRATCH] = 1;
3987 if (! TARGET_ALTIVEC)
3989 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3990 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3991 call_really_used_regs[VRSAVE_REGNO] = 1;
3994 if (TARGET_ALTIVEC_ABI)
3995 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3996 call_used_regs[i] = call_really_used_regs[i] = 1;
3999 /* Try to output insns to set TARGET equal to the constant C if it can
4000 be done in less than N insns. Do all computations in MODE.
4001 Returns the place where the output has been placed if it can be
4002 done and the insns have been emitted. If it would take more than N
4003 insns, zero is returned and no insns and emitted. */
4006 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4007 rtx source, int n ATTRIBUTE_UNUSED)
4009 rtx result, insn, set;
4010 HOST_WIDE_INT c0, c1;
4017 dest = gen_reg_rtx (mode);
4018 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4022 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4024 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4025 GEN_INT (INTVAL (source)
4026 & (~ (HOST_WIDE_INT) 0xffff))));
4027 emit_insn (gen_rtx_SET (VOIDmode, dest,
4028 gen_rtx_IOR (SImode, copy_rtx (result),
4029 GEN_INT (INTVAL (source) & 0xffff))));
4034 switch (GET_CODE (source))
4037 c0 = INTVAL (source);
4042 #if HOST_BITS_PER_WIDE_INT >= 64
4043 c0 = CONST_DOUBLE_LOW (source);
4046 c0 = CONST_DOUBLE_LOW (source);
4047 c1 = CONST_DOUBLE_HIGH (source);
4055 result = rs6000_emit_set_long_const (dest, c0, c1);
4062 insn = get_last_insn ();
4063 set = single_set (insn);
4064 if (! CONSTANT_P (SET_SRC (set)))
4065 set_unique_reg_note (insn, REG_EQUAL, source);
4070 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4071 fall back to a straight forward decomposition. We do this to avoid
4072 exponential run times encountered when looking for longer sequences
4073 with rs6000_emit_set_const. */
4075 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4077 if (!TARGET_POWERPC64)
4079 rtx operand1, operand2;
4081 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4083 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4085 emit_move_insn (operand1, GEN_INT (c1));
4086 emit_move_insn (operand2, GEN_INT (c2));
4090 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4093 ud2 = (c1 & 0xffff0000) >> 16;
4094 #if HOST_BITS_PER_WIDE_INT >= 64
4098 ud4 = (c2 & 0xffff0000) >> 16;
4100 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4101 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4104 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4106 emit_move_insn (dest, GEN_INT (ud1));
4109 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4110 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4113 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4116 emit_move_insn (dest, GEN_INT (ud2 << 16));
4118 emit_move_insn (copy_rtx (dest),
4119 gen_rtx_IOR (DImode, copy_rtx (dest),
4122 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4123 || (ud4 == 0 && ! (ud3 & 0x8000)))
4126 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4129 emit_move_insn (dest, GEN_INT (ud3 << 16));
4132 emit_move_insn (copy_rtx (dest),
4133 gen_rtx_IOR (DImode, copy_rtx (dest),
4135 emit_move_insn (copy_rtx (dest),
4136 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4139 emit_move_insn (copy_rtx (dest),
4140 gen_rtx_IOR (DImode, copy_rtx (dest),
4146 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4149 emit_move_insn (dest, GEN_INT (ud4 << 16));
4152 emit_move_insn (copy_rtx (dest),
4153 gen_rtx_IOR (DImode, copy_rtx (dest),
4156 emit_move_insn (copy_rtx (dest),
4157 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4160 emit_move_insn (copy_rtx (dest),
4161 gen_rtx_IOR (DImode, copy_rtx (dest),
4162 GEN_INT (ud2 << 16)));
4164 emit_move_insn (copy_rtx (dest),
4165 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4171 /* Helper for the following. Get rid of [r+r] memory refs
4172 in cases where it won't work (TImode, TFmode). */
4175 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4177 if (GET_CODE (operands[0]) == MEM
4178 && GET_CODE (XEXP (operands[0], 0)) != REG
4179 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4180 && ! reload_in_progress)
4182 = replace_equiv_address (operands[0],
4183 copy_addr_to_reg (XEXP (operands[0], 0)));
4185 if (GET_CODE (operands[1]) == MEM
4186 && GET_CODE (XEXP (operands[1], 0)) != REG
4187 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4188 && ! reload_in_progress)
4190 = replace_equiv_address (operands[1],
4191 copy_addr_to_reg (XEXP (operands[1], 0)));
4194 /* Emit a move from SOURCE to DEST in mode MODE. */
4196 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4200 operands[1] = source;
4202 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4203 if (GET_CODE (operands[1]) == CONST_DOUBLE
4204 && ! FLOAT_MODE_P (mode)
4205 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4207 /* FIXME. This should never happen. */
4208 /* Since it seems that it does, do the safe thing and convert
4210 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4212 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4213 || FLOAT_MODE_P (mode)
4214 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4215 || CONST_DOUBLE_LOW (operands[1]) < 0)
4216 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4217 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4219 /* Check if GCC is setting up a block move that will end up using FP
4220 registers as temporaries. We must make sure this is acceptable. */
4221 if (GET_CODE (operands[0]) == MEM
4222 && GET_CODE (operands[1]) == MEM
4224 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4225 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4226 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4227 ? 32 : MEM_ALIGN (operands[0])))
4228 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4230 : MEM_ALIGN (operands[1]))))
4231 && ! MEM_VOLATILE_P (operands [0])
4232 && ! MEM_VOLATILE_P (operands [1]))
4234 emit_move_insn (adjust_address (operands[0], SImode, 0),
4235 adjust_address (operands[1], SImode, 0));
4236 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4237 adjust_address (copy_rtx (operands[1]), SImode, 4));
4241 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4242 && !gpc_reg_operand (operands[1], mode))
4243 operands[1] = force_reg (mode, operands[1]);
4245 if (mode == SFmode && ! TARGET_POWERPC
4246 && TARGET_HARD_FLOAT && TARGET_FPRS
4247 && GET_CODE (operands[0]) == MEM)
4251 if (reload_in_progress || reload_completed)
4252 regnum = true_regnum (operands[1]);
4253 else if (GET_CODE (operands[1]) == REG)
4254 regnum = REGNO (operands[1]);
4258 /* If operands[1] is a register, on POWER it may have
4259 double-precision data in it, so truncate it to single
4261 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4264 newreg = (no_new_pseudos ? copy_rtx (operands[1])
4265 : gen_reg_rtx (mode));
4266 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4267 operands[1] = newreg;
4271 /* Recognize the case where operand[1] is a reference to thread-local
4272 data and load its address to a register. */
4273 if (rs6000_tls_referenced_p (operands[1]))
4275 enum tls_model model;
4276 rtx tmp = operands[1];
4279 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4281 addend = XEXP (XEXP (tmp, 0), 1);
4282 tmp = XEXP (XEXP (tmp, 0), 0);
4285 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4286 model = SYMBOL_REF_TLS_MODEL (tmp);
4287 gcc_assert (model != 0);
4289 tmp = rs6000_legitimize_tls_address (tmp, model);
4292 tmp = gen_rtx_PLUS (mode, tmp, addend);
4293 tmp = force_operand (tmp, operands[0]);
4298 /* Handle the case where reload calls us with an invalid address. */
4299 if (reload_in_progress && mode == Pmode
4300 && (! general_operand (operands[1], mode)
4301 || ! nonimmediate_operand (operands[0], mode)))
4304 /* 128-bit constant floating-point values on Darwin should really be
4305 loaded as two parts. */
4306 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4307 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4309 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4310 know how to get a DFmode SUBREG of a TFmode. */
4311 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4312 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4313 simplify_gen_subreg (imode, operands[1], mode, 0),
4315 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4316 GET_MODE_SIZE (imode)),
4317 simplify_gen_subreg (imode, operands[1], mode,
4318 GET_MODE_SIZE (imode)),
4323 /* FIXME: In the long term, this switch statement should go away
4324 and be replaced by a sequence of tests based on things like
4330 if (CONSTANT_P (operands[1])
4331 && GET_CODE (operands[1]) != CONST_INT)
4332 operands[1] = force_const_mem (mode, operands[1]);
4336 rs6000_eliminate_indexed_memrefs (operands);
4341 if (CONSTANT_P (operands[1])
4342 && ! easy_fp_constant (operands[1], mode))
4343 operands[1] = force_const_mem (mode, operands[1]);
4354 if (CONSTANT_P (operands[1])
4355 && !easy_vector_constant (operands[1], mode))
4356 operands[1] = force_const_mem (mode, operands[1]);
4361 /* Use default pattern for address of ELF small data */
4364 && DEFAULT_ABI == ABI_V4
4365 && (GET_CODE (operands[1]) == SYMBOL_REF
4366 || GET_CODE (operands[1]) == CONST)
4367 && small_data_operand (operands[1], mode))
4369 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4373 if (DEFAULT_ABI == ABI_V4
4374 && mode == Pmode && mode == SImode
4375 && flag_pic == 1 && got_operand (operands[1], mode))
4377 emit_insn (gen_movsi_got (operands[0], operands[1]));
4381 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4385 && CONSTANT_P (operands[1])
4386 && GET_CODE (operands[1]) != HIGH
4387 && GET_CODE (operands[1]) != CONST_INT)
4389 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4391 /* If this is a function address on -mcall-aixdesc,
4392 convert it to the address of the descriptor. */
4393 if (DEFAULT_ABI == ABI_AIX
4394 && GET_CODE (operands[1]) == SYMBOL_REF
4395 && XSTR (operands[1], 0)[0] == '.')
4397 const char *name = XSTR (operands[1], 0);
4399 while (*name == '.')
4401 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4402 CONSTANT_POOL_ADDRESS_P (new_ref)
4403 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4404 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4405 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4406 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4407 operands[1] = new_ref;
4410 if (DEFAULT_ABI == ABI_DARWIN)
4413 if (MACHO_DYNAMIC_NO_PIC_P)
4415 /* Take care of any required data indirection. */
4416 operands[1] = rs6000_machopic_legitimize_pic_address (
4417 operands[1], mode, operands[0]);
4418 if (operands[0] != operands[1])
4419 emit_insn (gen_rtx_SET (VOIDmode,
4420 operands[0], operands[1]));
4424 emit_insn (gen_macho_high (target, operands[1]));
4425 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4429 emit_insn (gen_elf_high (target, operands[1]));
4430 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4434 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4435 and we have put it in the TOC, we just need to make a TOC-relative
4438 && GET_CODE (operands[1]) == SYMBOL_REF
4439 && constant_pool_expr_p (operands[1])
4440 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4441 get_pool_mode (operands[1])))
4443 operands[1] = create_TOC_reference (operands[1]);
4445 else if (mode == Pmode
4446 && CONSTANT_P (operands[1])
4447 && ((GET_CODE (operands[1]) != CONST_INT
4448 && ! easy_fp_constant (operands[1], mode))
4449 || (GET_CODE (operands[1]) == CONST_INT
4450 && num_insns_constant (operands[1], mode) > 2)
4451 || (GET_CODE (operands[0]) == REG
4452 && FP_REGNO_P (REGNO (operands[0]))))
4453 && GET_CODE (operands[1]) != HIGH
4454 && ! legitimate_constant_pool_address_p (operands[1])
4455 && ! toc_relative_expr_p (operands[1]))
4457 /* Emit a USE operation so that the constant isn't deleted if
4458 expensive optimizations are turned on because nobody
4459 references it. This should only be done for operands that
4460 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4461 This should not be done for operands that contain LABEL_REFs.
4462 For now, we just handle the obvious case. */
4463 if (GET_CODE (operands[1]) != LABEL_REF)
4464 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4467 /* Darwin uses a special PIC legitimizer. */
4468 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4471 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4473 if (operands[0] != operands[1])
4474 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4479 /* If we are to limit the number of things we put in the TOC and
4480 this is a symbol plus a constant we can add in one insn,
4481 just put the symbol in the TOC and add the constant. Don't do
4482 this if reload is in progress. */
4483 if (GET_CODE (operands[1]) == CONST
4484 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4485 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4486 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4487 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4488 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4489 && ! side_effects_p (operands[0]))
4492 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4493 rtx other = XEXP (XEXP (operands[1], 0), 1);
4495 sym = force_reg (mode, sym);
4497 emit_insn (gen_addsi3 (operands[0], sym, other));
4499 emit_insn (gen_adddi3 (operands[0], sym, other));
4503 operands[1] = force_const_mem (mode, operands[1]);
4506 && constant_pool_expr_p (XEXP (operands[1], 0))
4507 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4508 get_pool_constant (XEXP (operands[1], 0)),
4509 get_pool_mode (XEXP (operands[1], 0))))
4512 = gen_const_mem (mode,
4513 create_TOC_reference (XEXP (operands[1], 0)));
4514 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4520 rs6000_eliminate_indexed_memrefs (operands);
4524 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4526 gen_rtx_SET (VOIDmode,
4527 operands[0], operands[1]),
4528 gen_rtx_CLOBBER (VOIDmode,
4529 gen_rtx_SCRATCH (SImode)))));
4538 /* Above, we may have called force_const_mem which may have returned
4539 an invalid address. If we can, fix this up; otherwise, reload will
4540 have to deal with it. */
4541 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4542 operands[1] = validize_mem (operands[1]);
4545 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4548 /* Nonzero if we can use a floating-point register to pass this arg. */
4549 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4550 (SCALAR_FLOAT_MODE_P (MODE) \
4551 && !DECIMAL_FLOAT_MODE_P (MODE) \
4552 && (CUM)->fregno <= FP_ARG_MAX_REG \
4553 && TARGET_HARD_FLOAT && TARGET_FPRS)
4555 /* Nonzero if we can use an AltiVec register to pass this arg. */
4556 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4557 (ALTIVEC_VECTOR_MODE (MODE) \
4558 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4559 && TARGET_ALTIVEC_ABI \
4562 /* Return a nonzero value to say to return the function value in
4563 memory, just as large structures are always returned. TYPE will be
4564 the data type of the value, and FNTYPE will be the type of the
4565 function doing the returning, or @code{NULL} for libcalls.
4567 The AIX ABI for the RS/6000 specifies that all structures are
4568 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4569 specifies that structures <= 8 bytes are returned in r3/r4, but a
4570 draft put them in memory, and GCC used to implement the draft
4571 instead of the final standard. Therefore, aix_struct_return
4572 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4573 compatibility can change DRAFT_V4_STRUCT_RET to override the
4574 default, and -m switches get the final word. See
4575 rs6000_override_options for more details.
4577 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4578 long double support is enabled. These values are returned in memory.
4580 int_size_in_bytes returns -1 for variable size objects, which go in
4581 memory always. The cast to unsigned makes -1 > 8. */
4584 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4586 /* In the darwin64 abi, try to use registers for larger structs
4588 if (rs6000_darwin64_abi
4589 && TREE_CODE (type) == RECORD_TYPE
4590 && int_size_in_bytes (type) > 0)
4592 CUMULATIVE_ARGS valcum;
4596 valcum.fregno = FP_ARG_MIN_REG;
4597 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4598 /* Do a trial code generation as if this were going to be passed
4599 as an argument; if any part goes in memory, we return NULL. */
4600 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4603 /* Otherwise fall through to more conventional ABI rules. */
4606 if (AGGREGATE_TYPE_P (type)
4607 && (aix_struct_return
4608 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4611 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4612 modes only exist for GCC vector types if -maltivec. */
4613 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4614 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4617 /* Return synthetic vectors in memory. */
4618 if (TREE_CODE (type) == VECTOR_TYPE
4619 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4621 static bool warned_for_return_big_vectors = false;
4622 if (!warned_for_return_big_vectors)
4624 warning (0, "GCC vector returned by reference: "
4625 "non-standard ABI extension with no compatibility guarantee");
4626 warned_for_return_big_vectors = true;
4631 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4637 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4638 for a call to a function whose data type is FNTYPE.
4639 For a library call, FNTYPE is 0.
4641 For incoming args we set the number of arguments in the prototype large
4642 so we never return a PARALLEL. */
4645 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4646 rtx libname ATTRIBUTE_UNUSED, int incoming,
4647 int libcall, int n_named_args)
4649 static CUMULATIVE_ARGS zero_cumulative;
4651 *cum = zero_cumulative;
4653 cum->fregno = FP_ARG_MIN_REG;
4654 cum->vregno = ALTIVEC_ARG_MIN_REG;
4655 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4656 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4657 ? CALL_LIBCALL : CALL_NORMAL);
4658 cum->sysv_gregno = GP_ARG_MIN_REG;
4659 cum->stdarg = fntype
4660 && (TYPE_ARG_TYPES (fntype) != 0
4661 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4662 != void_type_node));
4664 cum->nargs_prototype = 0;
4665 if (incoming || cum->prototype)
4666 cum->nargs_prototype = n_named_args;
4668 /* Check for a longcall attribute. */
4669 if ((!fntype && rs6000_default_long_calls)
4671 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4672 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4673 cum->call_cookie |= CALL_LONG;
4675 if (TARGET_DEBUG_ARG)
4677 fprintf (stderr, "\ninit_cumulative_args:");
4680 tree ret_type = TREE_TYPE (fntype);
4681 fprintf (stderr, " ret code = %s,",
4682 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4685 if (cum->call_cookie & CALL_LONG)
4686 fprintf (stderr, " longcall,");
4688 fprintf (stderr, " proto = %d, nargs = %d\n",
4689 cum->prototype, cum->nargs_prototype);
4694 && TARGET_ALTIVEC_ABI
4695 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4697 error ("cannot return value in vector register because"
4698 " altivec instructions are disabled, use -maltivec"
4703 /* Return true if TYPE must be passed on the stack and not in registers. */
4706 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4708 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4709 return must_pass_in_stack_var_size (mode, type);
4711 return must_pass_in_stack_var_size_or_pad (mode, type);
4714 /* If defined, a C expression which determines whether, and in which
4715 direction, to pad out an argument with extra space. The value
4716 should be of type `enum direction': either `upward' to pad above
4717 the argument, `downward' to pad below, or `none' to inhibit
4720 For the AIX ABI structs are always stored left shifted in their
4724 function_arg_padding (enum machine_mode mode, tree type)
4726 #ifndef AGGREGATE_PADDING_FIXED
4727 #define AGGREGATE_PADDING_FIXED 0
4729 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4730 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4733 if (!AGGREGATE_PADDING_FIXED)
4735 /* GCC used to pass structures of the same size as integer types as
4736 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4737 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4738 passed padded downward, except that -mstrict-align further
4739 muddied the water in that multi-component structures of 2 and 4
4740 bytes in size were passed padded upward.
4742 The following arranges for best compatibility with previous
4743 versions of gcc, but removes the -mstrict-align dependency. */
4744 if (BYTES_BIG_ENDIAN)
4746 HOST_WIDE_INT size = 0;
4748 if (mode == BLKmode)
4750 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4751 size = int_size_in_bytes (type);
4754 size = GET_MODE_SIZE (mode);
4756 if (size == 1 || size == 2 || size == 4)
4762 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4764 if (type != 0 && AGGREGATE_TYPE_P (type))
4768 /* Fall back to the default. */
4769 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4772 /* If defined, a C expression that gives the alignment boundary, in bits,
4773 of an argument with the specified mode and type. If it is not defined,
4774 PARM_BOUNDARY is used for all arguments.
4776 V.4 wants long longs and doubles to be double word aligned. Just
4777 testing the mode size is a boneheaded way to do this as it means
4778 that other types such as complex int are also double word aligned.
4779 However, we're stuck with this because changing the ABI might break
4780 existing library interfaces.
4782 Doubleword align SPE vectors.
4783 Quadword align Altivec vectors.
4784 Quadword align large synthetic vector types. */
4787 function_arg_boundary (enum machine_mode mode, tree type)
4789 if (DEFAULT_ABI == ABI_V4
4790 && (GET_MODE_SIZE (mode) == 8
4791 || (TARGET_HARD_FLOAT
4793 && mode == TFmode)))
4795 else if (SPE_VECTOR_MODE (mode)
4796 || (type && TREE_CODE (type) == VECTOR_TYPE
4797 && int_size_in_bytes (type) >= 8
4798 && int_size_in_bytes (type) < 16))
4800 else if (ALTIVEC_VECTOR_MODE (mode)
4801 || (type && TREE_CODE (type) == VECTOR_TYPE
4802 && int_size_in_bytes (type) >= 16))
4804 else if (rs6000_darwin64_abi && mode == BLKmode
4805 && type && TYPE_ALIGN (type) > 64)
4808 return PARM_BOUNDARY;
4811 /* For a function parm of MODE and TYPE, return the starting word in
4812 the parameter area. NWORDS of the parameter area are already used. */
4815 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4818 unsigned int parm_offset;
4820 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4821 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4822 return nwords + (-(parm_offset + nwords) & align);
4825 /* Compute the size (in words) of a function argument. */
4827 static unsigned long
4828 rs6000_arg_size (enum machine_mode mode, tree type)
4832 if (mode != BLKmode)
4833 size = GET_MODE_SIZE (mode);
4835 size = int_size_in_bytes (type);
4838 return (size + 3) >> 2;
4840 return (size + 7) >> 3;
4843 /* Use this to flush pending int fields. */
4846 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4847 HOST_WIDE_INT bitpos)
4849 unsigned int startbit, endbit;
4850 int intregs, intoffset;
4851 enum machine_mode mode;
4853 if (cum->intoffset == -1)
4856 intoffset = cum->intoffset;
4857 cum->intoffset = -1;
4859 if (intoffset % BITS_PER_WORD != 0)
4861 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4863 if (mode == BLKmode)
4865 /* We couldn't find an appropriate mode, which happens,
4866 e.g., in packed structs when there are 3 bytes to load.
4867 Back intoffset back to the beginning of the word in this
4869 intoffset = intoffset & -BITS_PER_WORD;
4873 startbit = intoffset & -BITS_PER_WORD;
4874 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4875 intregs = (endbit - startbit) / BITS_PER_WORD;
4876 cum->words += intregs;
4879 /* The darwin64 ABI calls for us to recurse down through structs,
4880 looking for elements passed in registers. Unfortunately, we have
4881 to track int register count here also because of misalignments
4882 in powerpc alignment mode. */
4885 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4887 HOST_WIDE_INT startbitpos)
4891 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4892 if (TREE_CODE (f) == FIELD_DECL)
4894 HOST_WIDE_INT bitpos = startbitpos;
4895 tree ftype = TREE_TYPE (f);
4896 enum machine_mode mode;
4897 if (ftype == error_mark_node)
4899 mode = TYPE_MODE (ftype);
4901 if (DECL_SIZE (f) != 0
4902 && host_integerp (bit_position (f), 1))
4903 bitpos += int_bit_position (f);
4905 /* ??? FIXME: else assume zero offset. */
4907 if (TREE_CODE (ftype) == RECORD_TYPE)
4908 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4909 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4911 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4912 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4913 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4915 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4917 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4921 else if (cum->intoffset == -1)
4922 cum->intoffset = bitpos;
4926 /* Update the data in CUM to advance over an argument
4927 of mode MODE and data type TYPE.
4928 (TYPE is null for libcalls where that information may not be available.)
4930 Note that for args passed by reference, function_arg will be called
4931 with MODE and TYPE set to that of the pointer to the arg, not the arg
4935 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4936 tree type, int named, int depth)
4940 /* Only tick off an argument if we're not recursing. */
4942 cum->nargs_prototype--;
4944 if (TARGET_ALTIVEC_ABI
4945 && (ALTIVEC_VECTOR_MODE (mode)
4946 || (type && TREE_CODE (type) == VECTOR_TYPE
4947 && int_size_in_bytes (type) == 16)))
4951 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4954 if (!TARGET_ALTIVEC)
4955 error ("cannot pass argument in vector register because"
4956 " altivec instructions are disabled, use -maltivec"
4959 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4960 even if it is going to be passed in a vector register.
4961 Darwin does the same for variable-argument functions. */
4962 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4963 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4973 /* Vector parameters must be 16-byte aligned. This places
4974 them at 2 mod 4 in terms of words in 32-bit mode, since
4975 the parameter save area starts at offset 24 from the
4976 stack. In 64-bit mode, they just have to start on an
4977 even word, since the parameter save area is 16-byte
4978 aligned. Space for GPRs is reserved even if the argument
4979 will be passed in memory. */
4981 align = (2 - cum->words) & 3;
4983 align = cum->words & 1;
4984 cum->words += align + rs6000_arg_size (mode, type);
4986 if (TARGET_DEBUG_ARG)
4988 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4990 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4991 cum->nargs_prototype, cum->prototype,
4992 GET_MODE_NAME (mode));
4996 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4998 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5001 else if (rs6000_darwin64_abi
5003 && TREE_CODE (type) == RECORD_TYPE
5004 && (size = int_size_in_bytes (type)) > 0)
5006 /* Variable sized types have size == -1 and are
5007 treated as if consisting entirely of ints.
5008 Pad to 16 byte boundary if needed. */
5009 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5010 && (cum->words % 2) != 0)
5012 /* For varargs, we can just go up by the size of the struct. */
5014 cum->words += (size + 7) / 8;
5017 /* It is tempting to say int register count just goes up by
5018 sizeof(type)/8, but this is wrong in a case such as
5019 { int; double; int; } [powerpc alignment]. We have to
5020 grovel through the fields for these too. */
5022 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5023 rs6000_darwin64_record_arg_advance_flush (cum,
5024 size * BITS_PER_UNIT);
5027 else if (DEFAULT_ABI == ABI_V4)
5029 if (TARGET_HARD_FLOAT && TARGET_FPRS
5030 && (mode == SFmode || mode == DFmode
5031 || (mode == TFmode && !TARGET_IEEEQUAD)))
5033 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5034 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5037 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5038 if (mode == DFmode || mode == TFmode)
5039 cum->words += cum->words & 1;
5040 cum->words += rs6000_arg_size (mode, type);
5045 int n_words = rs6000_arg_size (mode, type);
5046 int gregno = cum->sysv_gregno;
5048 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5049 (r7,r8) or (r9,r10). As does any other 2 word item such
5050 as complex int due to a historical mistake. */
5052 gregno += (1 - gregno) & 1;
5054 /* Multi-reg args are not split between registers and stack. */
5055 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5057 /* Long long and SPE vectors are aligned on the stack.
5058 So are other 2 word items such as complex int due to
5059 a historical mistake. */
5061 cum->words += cum->words & 1;
5062 cum->words += n_words;
5065 /* Note: continuing to accumulate gregno past when we've started
5066 spilling to the stack indicates the fact that we've started
5067 spilling to the stack to expand_builtin_saveregs. */
5068 cum->sysv_gregno = gregno + n_words;
5071 if (TARGET_DEBUG_ARG)
5073 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5074 cum->words, cum->fregno);
5075 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5076 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5077 fprintf (stderr, "mode = %4s, named = %d\n",
5078 GET_MODE_NAME (mode), named);
5083 int n_words = rs6000_arg_size (mode, type);
5084 int start_words = cum->words;
5085 int align_words = rs6000_parm_start (mode, type, start_words);
5087 cum->words = align_words + n_words;
5089 if (SCALAR_FLOAT_MODE_P (mode)
5090 && !DECIMAL_FLOAT_MODE_P (mode)
5091 && TARGET_HARD_FLOAT && TARGET_FPRS)
5092 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5094 if (TARGET_DEBUG_ARG)
5096 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5097 cum->words, cum->fregno);
5098 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5099 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5100 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5101 named, align_words - start_words, depth);
5107 spe_build_register_parallel (enum machine_mode mode, int gregno)
5114 r1 = gen_rtx_REG (DImode, gregno);
5115 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5116 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5120 r1 = gen_rtx_REG (DImode, gregno);
5121 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5122 r3 = gen_rtx_REG (DImode, gregno + 2);
5123 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5124 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5127 r1 = gen_rtx_REG (DImode, gregno);
5128 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5129 r3 = gen_rtx_REG (DImode, gregno + 2);
5130 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5131 r5 = gen_rtx_REG (DImode, gregno + 4);
5132 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5133 r7 = gen_rtx_REG (DImode, gregno + 6);
5134 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5135 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5142 /* Determine where to put a SIMD argument on the SPE. */
5144 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5147 int gregno = cum->sysv_gregno;
5149 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5150 are passed and returned in a pair of GPRs for ABI compatibility. */
5151 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5152 || mode == TFmode || mode == TCmode))
5154 int n_words = rs6000_arg_size (mode, type);
5156 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5158 gregno += (1 - gregno) & 1;
5160 /* Multi-reg args are not split between registers and stack. */
5161 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5164 return spe_build_register_parallel (mode, gregno);
5168 int n_words = rs6000_arg_size (mode, type);
5170 /* SPE vectors are put in odd registers. */
5171 if (n_words == 2 && (gregno & 1) == 0)
5174 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5177 enum machine_mode m = SImode;
5179 r1 = gen_rtx_REG (m, gregno);
5180 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5181 r2 = gen_rtx_REG (m, gregno + 1);
5182 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5183 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5190 if (gregno <= GP_ARG_MAX_REG)
5191 return gen_rtx_REG (mode, gregno);
5197 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5198 structure between cum->intoffset and bitpos to integer registers. */
5201 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5202 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5204 enum machine_mode mode;
5206 unsigned int startbit, endbit;
5207 int this_regno, intregs, intoffset;
5210 if (cum->intoffset == -1)
5213 intoffset = cum->intoffset;
5214 cum->intoffset = -1;
5216 /* If this is the trailing part of a word, try to only load that
5217 much into the register. Otherwise load the whole register. Note
5218 that in the latter case we may pick up unwanted bits. It's not a
5219 problem at the moment but may wish to revisit. */
5221 if (intoffset % BITS_PER_WORD != 0)
5223 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5225 if (mode == BLKmode)
5227 /* We couldn't find an appropriate mode, which happens,
5228 e.g., in packed structs when there are 3 bytes to load.
5229 Back intoffset back to the beginning of the word in this
5231 intoffset = intoffset & -BITS_PER_WORD;
5238 startbit = intoffset & -BITS_PER_WORD;
5239 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5240 intregs = (endbit - startbit) / BITS_PER_WORD;
5241 this_regno = cum->words + intoffset / BITS_PER_WORD;
5243 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5246 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5250 intoffset /= BITS_PER_UNIT;
5253 regno = GP_ARG_MIN_REG + this_regno;
5254 reg = gen_rtx_REG (mode, regno);
5256 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5259 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5263 while (intregs > 0);
5266 /* Recursive workhorse for the following. */
5269 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5270 HOST_WIDE_INT startbitpos, rtx rvec[],
5275 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5276 if (TREE_CODE (f) == FIELD_DECL)
5278 HOST_WIDE_INT bitpos = startbitpos;
5279 tree ftype = TREE_TYPE (f);
5280 enum machine_mode mode;
5281 if (ftype == error_mark_node)
5283 mode = TYPE_MODE (ftype);
5285 if (DECL_SIZE (f) != 0
5286 && host_integerp (bit_position (f), 1))
5287 bitpos += int_bit_position (f);
5289 /* ??? FIXME: else assume zero offset. */
5291 if (TREE_CODE (ftype) == RECORD_TYPE)
5292 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5293 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5298 case SCmode: mode = SFmode; break;
5299 case DCmode: mode = DFmode; break;
5300 case TCmode: mode = TFmode; break;
5304 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5306 = gen_rtx_EXPR_LIST (VOIDmode,
5307 gen_rtx_REG (mode, cum->fregno++),
5308 GEN_INT (bitpos / BITS_PER_UNIT));
5312 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5314 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5316 = gen_rtx_EXPR_LIST (VOIDmode,
5317 gen_rtx_REG (mode, cum->vregno++),
5318 GEN_INT (bitpos / BITS_PER_UNIT));
5320 else if (cum->intoffset == -1)
5321 cum->intoffset = bitpos;
5325 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5326 the register(s) to be used for each field and subfield of a struct
5327 being passed by value, along with the offset of where the
5328 register's value may be found in the block. FP fields go in FP
5329 register, vector fields go in vector registers, and everything
5330 else goes in int registers, packed as in memory.
5332 This code is also used for function return values. RETVAL indicates
5333 whether this is the case.
5335 Much of this is taken from the SPARC V9 port, which has a similar
5336 calling convention. */
5339 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5340 int named, bool retval)
5342 rtx rvec[FIRST_PSEUDO_REGISTER];
5343 int k = 1, kbase = 1;
5344 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5345 /* This is a copy; modifications are not visible to our caller. */
5346 CUMULATIVE_ARGS copy_cum = *orig_cum;
5347 CUMULATIVE_ARGS *cum = ©_cum;
5349 /* Pad to 16 byte boundary if needed. */
5350 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5351 && (cum->words % 2) != 0)
5358 /* Put entries into rvec[] for individual FP and vector fields, and
5359 for the chunks of memory that go in int regs. Note we start at
5360 element 1; 0 is reserved for an indication of using memory, and
5361 may or may not be filled in below. */
5362 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5363 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5365 /* If any part of the struct went on the stack put all of it there.
5366 This hack is because the generic code for
5367 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5368 parts of the struct are not at the beginning. */
5372 return NULL_RTX; /* doesn't go in registers at all */
5374 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5376 if (k > 1 || cum->use_stack)
5377 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5382 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5385 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5389 rtx rvec[GP_ARG_NUM_REG + 1];
5391 if (align_words >= GP_ARG_NUM_REG)
5394 n_units = rs6000_arg_size (mode, type);
5396 /* Optimize the simple case where the arg fits in one gpr, except in
5397 the case of BLKmode due to assign_parms assuming that registers are
5398 BITS_PER_WORD wide. */
5400 || (n_units == 1 && mode != BLKmode))
5401 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5404 if (align_words + n_units > GP_ARG_NUM_REG)
5405 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5406 using a magic NULL_RTX component.
5407 This is not strictly correct. Only some of the arg belongs in
5408 memory, not all of it. However, the normal scheme using
5409 function_arg_partial_nregs can result in unusual subregs, eg.
5410 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5411 store the whole arg to memory is often more efficient than code
5412 to store pieces, and we know that space is available in the right
5413 place for the whole arg. */
5414 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5419 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5420 rtx off = GEN_INT (i++ * 4);
5421 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5423 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5425 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5428 /* Determine where to put an argument to a function.
5429 Value is zero to push the argument on the stack,
5430 or a hard register in which to store the argument.
5432 MODE is the argument's machine mode.
5433 TYPE is the data type of the argument (as a tree).
5434 This is null for libcalls where that information may
5436 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5437 the preceding args and about the function being called. It is
5438 not modified in this routine.
5439 NAMED is nonzero if this argument is a named parameter
5440 (otherwise it is an extra parameter matching an ellipsis).
5442 On RS/6000 the first eight words of non-FP are normally in registers
5443 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5444 Under V.4, the first 8 FP args are in registers.
5446 If this is floating-point and no prototype is specified, we use
5447 both an FP and integer register (or possibly FP reg and stack). Library
5448 functions (when CALL_LIBCALL is set) always have the proper types for args,
5449 so we can pass the FP value just in one register. emit_library_function
5450 doesn't support PARALLEL anyway.
5452 Note that for args passed by reference, function_arg will be called
5453 with MODE and TYPE set to that of the pointer to the arg, not the arg
5457 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5458 tree type, int named)
5460 enum rs6000_abi abi = DEFAULT_ABI;
5462 /* Return a marker to indicate whether CR1 needs to set or clear the
5463 bit that V.4 uses to say fp args were passed in registers.
5464 Assume that we don't need the marker for software floating point,
5465 or compiler generated library calls. */
5466 if (mode == VOIDmode)
5469 && (cum->call_cookie & CALL_LIBCALL) == 0
5471 || (cum->nargs_prototype < 0
5472 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5474 /* For the SPE, we need to crxor CR6 always. */
5476 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5477 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5478 return GEN_INT (cum->call_cookie
5479 | ((cum->fregno == FP_ARG_MIN_REG)
5480 ? CALL_V4_SET_FP_ARGS
5481 : CALL_V4_CLEAR_FP_ARGS));
5484 return GEN_INT (cum->call_cookie);
5487 if (rs6000_darwin64_abi && mode == BLKmode
5488 && TREE_CODE (type) == RECORD_TYPE)
5490 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5491 if (rslt != NULL_RTX)
5493 /* Else fall through to usual handling. */
5496 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5497 if (TARGET_64BIT && ! cum->prototype)
5499 /* Vector parameters get passed in vector register
5500 and also in GPRs or memory, in absence of prototype. */
5503 align_words = (cum->words + 1) & ~1;
5505 if (align_words >= GP_ARG_NUM_REG)
5511 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5513 return gen_rtx_PARALLEL (mode,
5515 gen_rtx_EXPR_LIST (VOIDmode,
5517 gen_rtx_EXPR_LIST (VOIDmode,
5518 gen_rtx_REG (mode, cum->vregno),
5522 return gen_rtx_REG (mode, cum->vregno);
5523 else if (TARGET_ALTIVEC_ABI
5524 && (ALTIVEC_VECTOR_MODE (mode)
5525 || (type && TREE_CODE (type) == VECTOR_TYPE
5526 && int_size_in_bytes (type) == 16)))
5528 if (named || abi == ABI_V4)
5532 /* Vector parameters to varargs functions under AIX or Darwin
5533 get passed in memory and possibly also in GPRs. */
5534 int align, align_words, n_words;
5535 enum machine_mode part_mode;
5537 /* Vector parameters must be 16-byte aligned. This places them at
5538 2 mod 4 in terms of words in 32-bit mode, since the parameter
5539 save area starts at offset 24 from the stack. In 64-bit mode,
5540 they just have to start on an even word, since the parameter
5541 save area is 16-byte aligned. */
5543 align = (2 - cum->words) & 3;
5545 align = cum->words & 1;
5546 align_words = cum->words + align;
5548 /* Out of registers? Memory, then. */
5549 if (align_words >= GP_ARG_NUM_REG)
5552 if (TARGET_32BIT && TARGET_POWERPC64)
5553 return rs6000_mixed_function_arg (mode, type, align_words);
5555 /* The vector value goes in GPRs. Only the part of the
5556 value in GPRs is reported here. */
5558 n_words = rs6000_arg_size (mode, type);
5559 if (align_words + n_words > GP_ARG_NUM_REG)
5560 /* Fortunately, there are only two possibilities, the value
5561 is either wholly in GPRs or half in GPRs and half not. */
5564 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5567 else if (TARGET_SPE_ABI && TARGET_SPE
5568 && (SPE_VECTOR_MODE (mode)
5569 || (TARGET_E500_DOUBLE && (mode == DFmode
5572 || mode == TCmode))))
5573 return rs6000_spe_function_arg (cum, mode, type);
5575 else if (abi == ABI_V4)
5577 if (TARGET_HARD_FLOAT && TARGET_FPRS
5578 && (mode == SFmode || mode == DFmode
5579 || (mode == TFmode && !TARGET_IEEEQUAD)))
5581 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5582 return gen_rtx_REG (mode, cum->fregno);
5588 int n_words = rs6000_arg_size (mode, type);
5589 int gregno = cum->sysv_gregno;
5591 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5592 (r7,r8) or (r9,r10). As does any other 2 word item such
5593 as complex int due to a historical mistake. */
5595 gregno += (1 - gregno) & 1;
5597 /* Multi-reg args are not split between registers and stack. */
5598 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5601 if (TARGET_32BIT && TARGET_POWERPC64)
5602 return rs6000_mixed_function_arg (mode, type,
5603 gregno - GP_ARG_MIN_REG);
5604 return gen_rtx_REG (mode, gregno);
5609 int align_words = rs6000_parm_start (mode, type, cum->words);
5611 if (USE_FP_FOR_ARG_P (cum, mode, type))
5613 rtx rvec[GP_ARG_NUM_REG + 1];
5617 enum machine_mode fmode = mode;
5618 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5620 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5622 /* Currently, we only ever need one reg here because complex
5623 doubles are split. */
5624 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5626 /* Long double split over regs and memory. */
5630 /* Do we also need to pass this arg in the parameter save
5633 && (cum->nargs_prototype <= 0
5634 || (DEFAULT_ABI == ABI_AIX
5636 && align_words >= GP_ARG_NUM_REG)));
5638 if (!needs_psave && mode == fmode)
5639 return gen_rtx_REG (fmode, cum->fregno);
5644 /* Describe the part that goes in gprs or the stack.
5645 This piece must come first, before the fprs. */
5646 if (align_words < GP_ARG_NUM_REG)
5648 unsigned long n_words = rs6000_arg_size (mode, type);
5650 if (align_words + n_words > GP_ARG_NUM_REG
5651 || (TARGET_32BIT && TARGET_POWERPC64))
5653 /* If this is partially on the stack, then we only
5654 include the portion actually in registers here. */
5655 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5658 if (align_words + n_words > GP_ARG_NUM_REG)
5659 /* Not all of the arg fits in gprs. Say that it
5660 goes in memory too, using a magic NULL_RTX
5661 component. Also see comment in
5662 rs6000_mixed_function_arg for why the normal
5663 function_arg_partial_nregs scheme doesn't work
5665 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5669 r = gen_rtx_REG (rmode,
5670 GP_ARG_MIN_REG + align_words);
5671 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5672 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5674 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5678 /* The whole arg fits in gprs. */
5679 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5680 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5684 /* It's entirely in memory. */
5685 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5688 /* Describe where this piece goes in the fprs. */
5689 r = gen_rtx_REG (fmode, cum->fregno);
5690 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5692 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5694 else if (align_words < GP_ARG_NUM_REG)
5696 if (TARGET_32BIT && TARGET_POWERPC64)
5697 return rs6000_mixed_function_arg (mode, type, align_words);
5699 if (mode == BLKmode)
5702 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5709 /* For an arg passed partly in registers and partly in memory, this is
5710 the number of bytes passed in registers. For args passed entirely in
5711 registers or entirely in memory, zero. When an arg is described by a
5712 PARALLEL, perhaps using more than one register type, this function
5713 returns the number of bytes used by the first element of the PARALLEL. */
5716 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5717 tree type, bool named)
5722 if (DEFAULT_ABI == ABI_V4)
5725 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5726 && cum->nargs_prototype >= 0)
5729 /* In this complicated case we just disable the partial_nregs code. */
5730 if (rs6000_darwin64_abi && mode == BLKmode
5731 && TREE_CODE (type) == RECORD_TYPE
5732 && int_size_in_bytes (type) > 0)
5735 align_words = rs6000_parm_start (mode, type, cum->words);
5737 if (USE_FP_FOR_ARG_P (cum, mode, type))
5739 /* If we are passing this arg in the fixed parameter save area
5740 (gprs or memory) as well as fprs, then this function should
5741 return the number of partial bytes passed in the parameter
5742 save area rather than partial bytes passed in fprs. */
5744 && (cum->nargs_prototype <= 0
5745 || (DEFAULT_ABI == ABI_AIX
5747 && align_words >= GP_ARG_NUM_REG)))
5749 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5750 > FP_ARG_MAX_REG + 1)
5751 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5752 else if (cum->nargs_prototype >= 0)
5756 if (align_words < GP_ARG_NUM_REG
5757 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5758 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5760 if (ret != 0 && TARGET_DEBUG_ARG)
5761 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5766 /* A C expression that indicates when an argument must be passed by
5767 reference. If nonzero for an argument, a copy of that argument is
5768 made in memory and a pointer to the argument is passed instead of
5769 the argument itself. The pointer is passed in whatever way is
5770 appropriate for passing a pointer to that type.
5772 Under V.4, aggregates and long double are passed by reference.
5774 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5775 reference unless the AltiVec vector extension ABI is in force.
5777 As an extension to all ABIs, variable sized types are passed by
5781 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5782 enum machine_mode mode, tree type,
5783 bool named ATTRIBUTE_UNUSED)
5785 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5787 if (TARGET_DEBUG_ARG)
5788 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5795 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5797 if (TARGET_DEBUG_ARG)
5798 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5802 if (int_size_in_bytes (type) < 0)
5804 if (TARGET_DEBUG_ARG)
5805 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5809 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5810 modes only exist for GCC vector types if -maltivec. */
5811 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5813 if (TARGET_DEBUG_ARG)
5814 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5818 /* Pass synthetic vectors in memory. */
5819 if (TREE_CODE (type) == VECTOR_TYPE
5820 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5822 static bool warned_for_pass_big_vectors = false;
5823 if (TARGET_DEBUG_ARG)
5824 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5825 if (!warned_for_pass_big_vectors)
5827 warning (0, "GCC vector passed by reference: "
5828 "non-standard ABI extension with no compatibility guarantee");
5829 warned_for_pass_big_vectors = true;
5838 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5841 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5846 for (i = 0; i < nregs; i++)
5848 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5849 if (reload_completed)
5851 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5854 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5855 i * GET_MODE_SIZE (reg_mode));
5858 tem = replace_equiv_address (tem, XEXP (tem, 0));
5862 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5866 /* Perform any needed actions needed for a function that is receiving a
5867 variable number of arguments.
5871 MODE and TYPE are the mode and type of the current parameter.
5873 PRETEND_SIZE is a variable that should be set to the amount of stack
5874 that must be pushed by the prolog to pretend that our caller pushed
5877 Normally, this macro will push all remaining incoming registers on the
5878 stack and set PRETEND_SIZE to the length of the registers pushed. */
5881 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5882 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5885 CUMULATIVE_ARGS next_cum;
5886 int reg_size = TARGET_32BIT ? 4 : 8;
5887 rtx save_area = NULL_RTX, mem;
5888 int first_reg_offset, set;
5890 /* Skip the last named argument. */
5892 function_arg_advance (&next_cum, mode, type, 1, 0);
5894 if (DEFAULT_ABI == ABI_V4)
5896 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5900 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5901 HOST_WIDE_INT offset = 0;
5903 /* Try to optimize the size of the varargs save area.
5904 The ABI requires that ap.reg_save_area is doubleword
5905 aligned, but we don't need to allocate space for all
5906 the bytes, only those to which we actually will save
5908 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5909 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5910 if (TARGET_HARD_FLOAT && TARGET_FPRS
5911 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5912 && cfun->va_list_fpr_size)
5915 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5916 * UNITS_PER_FP_WORD;
5917 if (cfun->va_list_fpr_size
5918 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5919 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5921 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5922 * UNITS_PER_FP_WORD;
5926 offset = -((first_reg_offset * reg_size) & ~7);
5927 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5929 gpr_reg_num = cfun->va_list_gpr_size;
5930 if (reg_size == 4 && (first_reg_offset & 1))
5933 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5936 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5938 - (int) (GP_ARG_NUM_REG * reg_size);
5940 if (gpr_size + fpr_size)
5943 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5944 gcc_assert (GET_CODE (reg_save_area) == MEM);
5945 reg_save_area = XEXP (reg_save_area, 0);
5946 if (GET_CODE (reg_save_area) == PLUS)
5948 gcc_assert (XEXP (reg_save_area, 0)
5949 == virtual_stack_vars_rtx);
5950 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5951 offset += INTVAL (XEXP (reg_save_area, 1));
5954 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5957 cfun->machine->varargs_save_offset = offset;
5958 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5963 first_reg_offset = next_cum.words;
5964 save_area = virtual_incoming_args_rtx;
5966 if (targetm.calls.must_pass_in_stack (mode, type))
5967 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5970 set = get_varargs_alias_set ();
5971 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5972 && cfun->va_list_gpr_size)
5974 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5976 if (va_list_gpr_counter_field)
5978 /* V4 va_list_gpr_size counts number of registers needed. */
5979 if (nregs > cfun->va_list_gpr_size)
5980 nregs = cfun->va_list_gpr_size;
5984 /* char * va_list instead counts number of bytes needed. */
5985 if (nregs > cfun->va_list_gpr_size / reg_size)
5986 nregs = cfun->va_list_gpr_size / reg_size;
5989 mem = gen_rtx_MEM (BLKmode,
5990 plus_constant (save_area,
5991 first_reg_offset * reg_size));
5992 MEM_NOTRAP_P (mem) = 1;
5993 set_mem_alias_set (mem, set);
5994 set_mem_align (mem, BITS_PER_WORD);
5996 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6000 /* Save FP registers if needed. */
6001 if (DEFAULT_ABI == ABI_V4
6002 && TARGET_HARD_FLOAT && TARGET_FPRS
6004 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6005 && cfun->va_list_fpr_size)
6007 int fregno = next_cum.fregno, nregs;
6008 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6009 rtx lab = gen_label_rtx ();
6010 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6011 * UNITS_PER_FP_WORD);
6014 (gen_rtx_SET (VOIDmode,
6016 gen_rtx_IF_THEN_ELSE (VOIDmode,
6017 gen_rtx_NE (VOIDmode, cr1,
6019 gen_rtx_LABEL_REF (VOIDmode, lab),
6023 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6024 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6026 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6027 MEM_NOTRAP_P (mem) = 1;
6028 set_mem_alias_set (mem, set);
6029 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6030 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6037 /* Create the va_list data type. */
6040 rs6000_build_builtin_va_list (void)
6042 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6044 /* For AIX, prefer 'char *' because that's what the system
6045 header files like. */
6046 if (DEFAULT_ABI != ABI_V4)
6047 return build_pointer_type (char_type_node);
6049 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6050 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6052 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6053 unsigned_char_type_node);
6054 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6055 unsigned_char_type_node);
6056 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6058 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6059 short_unsigned_type_node);
6060 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6062 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6065 va_list_gpr_counter_field = f_gpr;
6066 va_list_fpr_counter_field = f_fpr;
6068 DECL_FIELD_CONTEXT (f_gpr) = record;
6069 DECL_FIELD_CONTEXT (f_fpr) = record;
6070 DECL_FIELD_CONTEXT (f_res) = record;
6071 DECL_FIELD_CONTEXT (f_ovf) = record;
6072 DECL_FIELD_CONTEXT (f_sav) = record;
6074 TREE_CHAIN (record) = type_decl;
6075 TYPE_NAME (record) = type_decl;
6076 TYPE_FIELDS (record) = f_gpr;
6077 TREE_CHAIN (f_gpr) = f_fpr;
6078 TREE_CHAIN (f_fpr) = f_res;
6079 TREE_CHAIN (f_res) = f_ovf;
6080 TREE_CHAIN (f_ovf) = f_sav;
6082 layout_type (record);
6084 /* The correct type is an array type of one element. */
6085 return build_array_type (record, build_index_type (size_zero_node));
6088 /* Implement va_start. */
6091 rs6000_va_start (tree valist, rtx nextarg)
6093 HOST_WIDE_INT words, n_gpr, n_fpr;
6094 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6095 tree gpr, fpr, ovf, sav, t;
6097 /* Only SVR4 needs something special. */
6098 if (DEFAULT_ABI != ABI_V4)
6100 std_expand_builtin_va_start (valist, nextarg);
6104 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6105 f_fpr = TREE_CHAIN (f_gpr);
6106 f_res = TREE_CHAIN (f_fpr);
6107 f_ovf = TREE_CHAIN (f_res);
6108 f_sav = TREE_CHAIN (f_ovf);
6110 valist = build_va_arg_indirect_ref (valist);
6111 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6112 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6113 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6114 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6116 /* Count number of gp and fp argument registers used. */
6117 words = current_function_args_info.words;
6118 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6120 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6123 if (TARGET_DEBUG_ARG)
6124 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6125 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6126 words, n_gpr, n_fpr);
6128 if (cfun->va_list_gpr_size)
6130 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6131 build_int_cst (NULL_TREE, n_gpr));
6132 TREE_SIDE_EFFECTS (t) = 1;
6133 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6136 if (cfun->va_list_fpr_size)
6138 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6139 build_int_cst (NULL_TREE, n_fpr));
6140 TREE_SIDE_EFFECTS (t) = 1;
6141 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6144 /* Find the overflow area. */
6145 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6147 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
6148 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
6149 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6150 TREE_SIDE_EFFECTS (t) = 1;
6151 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6153 /* If there were no va_arg invocations, don't set up the register
6155 if (!cfun->va_list_gpr_size
6156 && !cfun->va_list_fpr_size
6157 && n_gpr < GP_ARG_NUM_REG
6158 && n_fpr < FP_ARG_V4_MAX_REG)
6161 /* Find the register save area. */
6162 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6163 if (cfun->machine->varargs_save_offset)
6164 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
6165 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
6166 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6167 TREE_SIDE_EFFECTS (t) = 1;
6168 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6171 /* Implement va_arg. */
6174 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6176 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6177 tree gpr, fpr, ovf, sav, reg, t, u;
6178 int size, rsize, n_reg, sav_ofs, sav_scale;
6179 tree lab_false, lab_over, addr;
6181 tree ptrtype = build_pointer_type (type);
6183 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6185 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6186 return build_va_arg_indirect_ref (t);
6189 if (DEFAULT_ABI != ABI_V4)
6191 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6193 tree elem_type = TREE_TYPE (type);
6194 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6195 int elem_size = GET_MODE_SIZE (elem_mode);
6197 if (elem_size < UNITS_PER_WORD)
6199 tree real_part, imag_part;
6200 tree post = NULL_TREE;
6202 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6204 /* Copy the value into a temporary, lest the formal temporary
6205 be reused out from under us. */
6206 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6207 append_to_statement_list (post, pre_p);
6209 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6212 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6216 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6219 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6220 f_fpr = TREE_CHAIN (f_gpr);
6221 f_res = TREE_CHAIN (f_fpr);
6222 f_ovf = TREE_CHAIN (f_res);
6223 f_sav = TREE_CHAIN (f_ovf);
6225 valist = build_va_arg_indirect_ref (valist);
6226 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6227 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6228 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6229 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6231 size = int_size_in_bytes (type);
6232 rsize = (size + 3) / 4;
6235 if (TARGET_HARD_FLOAT && TARGET_FPRS
6236 && (TYPE_MODE (type) == SFmode
6237 || TYPE_MODE (type) == DFmode
6238 || TYPE_MODE (type) == TFmode))
6240 /* FP args go in FP registers, if present. */
6242 n_reg = (size + 7) / 8;
6245 if (TYPE_MODE (type) != SFmode)
6250 /* Otherwise into GP registers. */
6259 /* Pull the value out of the saved registers.... */
6262 addr = create_tmp_var (ptr_type_node, "addr");
6263 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6265 /* AltiVec vectors never go in registers when -mabi=altivec. */
6266 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6270 lab_false = create_artificial_label ();
6271 lab_over = create_artificial_label ();
6273 /* Long long and SPE vectors are aligned in the registers.
6274 As are any other 2 gpr item such as complex int due to a
6275 historical mistake. */
6277 if (n_reg == 2 && reg == gpr)
6279 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6280 size_int (n_reg - 1));
6281 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6284 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6285 t = build2 (GE_EXPR, boolean_type_node, u, t);
6286 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6287 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6288 gimplify_and_add (t, pre_p);
6292 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6294 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6295 u = build1 (CONVERT_EXPR, integer_type_node, u);
6296 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6297 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6299 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6300 gimplify_and_add (t, pre_p);
6302 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6303 gimplify_and_add (t, pre_p);
6305 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6306 append_to_statement_list (t, pre_p);
6308 if ((n_reg == 2 && reg != gpr) || n_reg > 2)
6310 /* Ensure that we don't find any more args in regs.
6311 Alignment has taken care of the n_reg == 2 gpr case. */
6312 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6313 gimplify_and_add (t, pre_p);
6317 /* ... otherwise out of the overflow area. */
6319 /* Care for on-stack alignment if needed. */
6323 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6324 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6325 build_int_cst (NULL_TREE, -align));
6327 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6329 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6330 gimplify_and_add (u, pre_p);
6332 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6333 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6334 gimplify_and_add (t, pre_p);
6338 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6339 append_to_statement_list (t, pre_p);
6342 if (STRICT_ALIGNMENT
6343 && (TYPE_ALIGN (type)
6344 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6346 /* The value (of type complex double, for example) may not be
6347 aligned in memory in the saved registers, so copy via a
6348 temporary. (This is the same code as used for SPARC.) */
6349 tree tmp = create_tmp_var (type, "va_arg_tmp");
6350 tree dest_addr = build_fold_addr_expr (tmp);
6352 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6353 3, dest_addr, addr, size_int (rsize * 4));
6355 gimplify_and_add (copy, pre_p);
6359 addr = fold_convert (ptrtype, addr);
6360 return build_va_arg_indirect_ref (addr);
6366 def_builtin (int mask, const char *name, tree type, int code)
6368 if (mask & target_flags)
6370 if (rs6000_builtin_decls[code])
6373 rs6000_builtin_decls[code] =
6374 add_builtin_function (name, type, code, BUILT_IN_MD,
6379 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6381 static const struct builtin_description bdesc_3arg[] =
6383 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6384 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6385 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6386 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6387 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6388 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6389 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6390 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6391 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6392 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6393 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6394 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6395 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6396 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6397 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6398 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6399 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6400 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6401 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6402 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6403 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6404 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6405 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6407 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6408 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6409 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6410 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6411 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6412 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6413 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6414 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6415 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6416 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6417 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6418 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6419 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6420 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6421 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6424 /* DST operations: void foo (void *, const int, const char). */
6426 static const struct builtin_description bdesc_dst[] =
6428 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6429 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6430 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6431 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6433 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6434 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6435 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6436 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6439 /* Simple binary operations: VECc = foo (VECa, VECb). */
6441 static struct builtin_description bdesc_2arg[] =
6443 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6444 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6445 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6446 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6447 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6448 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6449 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6450 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6451 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6452 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6453 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6454 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6455 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6457 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6461 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6468 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6469 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6470 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6471 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6472 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6473 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6474 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6475 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6476 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6477 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6478 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6479 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6480 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6481 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6482 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6483 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6484 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6485 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6486 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6487 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6488 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6489 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6490 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6491 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6492 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6493 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6494 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6495 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6496 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6497 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6498 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6499 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6500 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6501 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6502 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6503 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6504 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6505 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6506 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6507 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6508 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6509 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6511 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6512 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6523 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6529 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6530 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6531 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6532 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6533 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6534 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6537 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6538 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6539 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6540 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6541 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6542 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6543 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6545 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6546 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6552 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6553 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6555 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6556 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6557 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6558 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6559 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6560 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6561 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6562 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6563 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6564 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6565 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6566 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6567 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6568 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6569 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6572 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6573 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6574 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6575 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6576 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6577 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6578 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6579 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6580 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6581 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6582 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6583 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6584 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6585 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6586 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6587 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6588 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6589 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6590 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6591 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6592 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6593 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6594 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6595 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6596 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6597 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6598 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6599 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6600 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6601 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6602 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6603 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6604 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6605 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6606 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6607 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6608 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6609 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6610 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6611 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6612 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6613 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6614 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6615 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6616 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6617 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6618 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6619 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6620 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6621 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6622 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6623 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6624 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6625 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6626 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6627 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6628 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6629 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6635 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6668 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6669 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6670 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6675 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6683 /* Place holder, leave as first spe builtin. */
6684 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6685 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6686 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6687 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6688 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6689 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6690 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6691 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6692 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6693 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6694 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6695 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6696 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6697 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6698 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6699 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6700 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6701 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6702 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6703 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6704 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6705 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6706 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6707 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6708 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6709 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6710 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6711 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6712 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6713 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6714 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6715 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6716 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6717 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6718 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6719 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6720 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6721 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6722 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6723 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6724 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6725 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6726 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6727 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6728 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6729 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6730 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6731 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6732 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6733 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6734 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6735 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6736 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6737 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6738 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6739 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6740 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6741 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6742 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6743 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6744 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6745 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6746 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6747 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6748 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6749 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6750 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6751 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6752 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6753 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6754 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6755 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6756 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6757 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6758 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6759 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6760 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6761 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6762 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6763 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6764 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6765 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6766 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6767 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6768 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6769 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6770 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6771 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6772 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6773 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6774 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6775 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6776 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6777 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6778 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6779 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6780 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6781 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6782 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6783 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6784 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6785 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6786 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6787 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6788 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6789 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6790 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6791 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6792 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6794 /* SPE binary operations expecting a 5-bit unsigned literal. */
6795 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6797 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6798 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6799 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6800 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6801 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6802 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6803 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6804 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6805 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6806 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6807 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6808 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6809 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6810 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6811 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6812 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6813 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6814 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6815 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6816 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6817 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6818 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6819 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6820 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6821 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6822 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6824 /* Place-holder. Leave as last binary SPE builtin. */
6825 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6828 /* AltiVec predicates. */
6830 struct builtin_description_predicates
6832 const unsigned int mask;
6833 const enum insn_code icode;
6835 const char *const name;
6836 const enum rs6000_builtins code;
6839 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6841 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6842 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6843 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6844 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6845 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6846 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6847 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6848 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6849 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6850 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6851 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6852 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6853 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6855 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6856 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6857 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6860 /* SPE predicates. */
6861 static struct builtin_description bdesc_spe_predicates[] =
6863 /* Place-holder. Leave as first. */
6864 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6865 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6866 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6867 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6868 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6869 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6870 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6871 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6872 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6873 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6874 /* Place-holder. Leave as last. */
6875 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6878 /* SPE evsel predicates. */
6879 static struct builtin_description bdesc_spe_evsel[] =
6881 /* Place-holder. Leave as first. */
6882 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6883 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6884 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6885 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6886 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6887 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6888 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6889 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6890 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6891 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6892 /* Place-holder. Leave as last. */
6893 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6896 /* ABS* operations. */
6898 static const struct builtin_description bdesc_abs[] =
6900 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6901 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6902 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6903 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6904 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6905 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6906 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6909 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6912 static struct builtin_description bdesc_1arg[] =
6914 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6915 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6916 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6917 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6918 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6919 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6920 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6921 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6922 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6923 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6924 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6925 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6926 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6927 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6928 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6929 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6930 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6932 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6933 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6934 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6935 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6936 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6937 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6938 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6939 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6940 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6941 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6942 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6943 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6944 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6945 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6946 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6947 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6948 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6949 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6950 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6952 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6953 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6954 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6955 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6956 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6957 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6958 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6959 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6960 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6961 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6962 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6963 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6964 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6965 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6966 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6967 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6968 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6969 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6970 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6971 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6972 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6973 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6974 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6975 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6976 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6977 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6978 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6979 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6980 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6981 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6983 /* Place-holder. Leave as last unary SPE builtin. */
6984 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6988 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
6991 tree arg0 = CALL_EXPR_ARG (exp, 0);
6992 rtx op0 = expand_normal (arg0);
6993 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6994 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6996 if (icode == CODE_FOR_nothing)
6997 /* Builtin not supported on this processor. */
7000 /* If we got invalid arguments bail out before generating bad rtl. */
7001 if (arg0 == error_mark_node)
7004 if (icode == CODE_FOR_altivec_vspltisb
7005 || icode == CODE_FOR_altivec_vspltish
7006 || icode == CODE_FOR_altivec_vspltisw
7007 || icode == CODE_FOR_spe_evsplatfi
7008 || icode == CODE_FOR_spe_evsplati)
7010 /* Only allow 5-bit *signed* literals. */
7011 if (GET_CODE (op0) != CONST_INT
7012 || INTVAL (op0) > 15
7013 || INTVAL (op0) < -16)
7015 error ("argument 1 must be a 5-bit signed literal");
7021 || GET_MODE (target) != tmode
7022 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7023 target = gen_reg_rtx (tmode);
7025 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7026 op0 = copy_to_mode_reg (mode0, op0);
7028 pat = GEN_FCN (icode) (target, op0);
7037 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7039 rtx pat, scratch1, scratch2;
7040 tree arg0 = CALL_EXPR_ARG (exp, 0);
7041 rtx op0 = expand_normal (arg0);
7042 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7043 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7045 /* If we have invalid arguments, bail out before generating bad rtl. */
7046 if (arg0 == error_mark_node)
7050 || GET_MODE (target) != tmode
7051 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7052 target = gen_reg_rtx (tmode);
7054 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7055 op0 = copy_to_mode_reg (mode0, op0);
7057 scratch1 = gen_reg_rtx (mode0);
7058 scratch2 = gen_reg_rtx (mode0);
7060 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7069 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7072 tree arg0 = CALL_EXPR_ARG (exp, 0);
7073 tree arg1 = CALL_EXPR_ARG (exp, 1);
7074 rtx op0 = expand_normal (arg0);
7075 rtx op1 = expand_normal (arg1);
7076 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7077 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7078 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7080 if (icode == CODE_FOR_nothing)
7081 /* Builtin not supported on this processor. */
7084 /* If we got invalid arguments bail out before generating bad rtl. */
7085 if (arg0 == error_mark_node || arg1 == error_mark_node)
7088 if (icode == CODE_FOR_altivec_vcfux
7089 || icode == CODE_FOR_altivec_vcfsx
7090 || icode == CODE_FOR_altivec_vctsxs
7091 || icode == CODE_FOR_altivec_vctuxs
7092 || icode == CODE_FOR_altivec_vspltb
7093 || icode == CODE_FOR_altivec_vsplth
7094 || icode == CODE_FOR_altivec_vspltw
7095 || icode == CODE_FOR_spe_evaddiw
7096 || icode == CODE_FOR_spe_evldd
7097 || icode == CODE_FOR_spe_evldh
7098 || icode == CODE_FOR_spe_evldw
7099 || icode == CODE_FOR_spe_evlhhesplat
7100 || icode == CODE_FOR_spe_evlhhossplat
7101 || icode == CODE_FOR_spe_evlhhousplat
7102 || icode == CODE_FOR_spe_evlwhe
7103 || icode == CODE_FOR_spe_evlwhos
7104 || icode == CODE_FOR_spe_evlwhou
7105 || icode == CODE_FOR_spe_evlwhsplat
7106 || icode == CODE_FOR_spe_evlwwsplat
7107 || icode == CODE_FOR_spe_evrlwi
7108 || icode == CODE_FOR_spe_evslwi
7109 || icode == CODE_FOR_spe_evsrwis
7110 || icode == CODE_FOR_spe_evsubifw
7111 || icode == CODE_FOR_spe_evsrwiu)
7113 /* Only allow 5-bit unsigned literals. */
7115 if (TREE_CODE (arg1) != INTEGER_CST
7116 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7118 error ("argument 2 must be a 5-bit unsigned literal");
7124 || GET_MODE (target) != tmode
7125 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7126 target = gen_reg_rtx (tmode);
7128 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7129 op0 = copy_to_mode_reg (mode0, op0);
7130 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7131 op1 = copy_to_mode_reg (mode1, op1);
7133 pat = GEN_FCN (icode) (target, op0, op1);
7142 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7143 tree exp, rtx target)
7146 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7147 tree arg0 = CALL_EXPR_ARG (exp, 1);
7148 tree arg1 = CALL_EXPR_ARG (exp, 2);
7149 rtx op0 = expand_normal (arg0);
7150 rtx op1 = expand_normal (arg1);
7151 enum machine_mode tmode = SImode;
7152 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7153 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7156 if (TREE_CODE (cr6_form) != INTEGER_CST)
7158 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7162 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7164 gcc_assert (mode0 == mode1);
7166 /* If we have invalid arguments, bail out before generating bad rtl. */
7167 if (arg0 == error_mark_node || arg1 == error_mark_node)
7171 || GET_MODE (target) != tmode
7172 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7173 target = gen_reg_rtx (tmode);
7175 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7176 op0 = copy_to_mode_reg (mode0, op0);
7177 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7178 op1 = copy_to_mode_reg (mode1, op1);
7180 scratch = gen_reg_rtx (mode0);
7182 pat = GEN_FCN (icode) (scratch, op0, op1,
7183 gen_rtx_SYMBOL_REF (Pmode, opcode));
7188 /* The vec_any* and vec_all* predicates use the same opcodes for two
7189 different operations, but the bits in CR6 will be different
7190 depending on what information we want. So we have to play tricks
7191 with CR6 to get the right bits out.
7193 If you think this is disgusting, look at the specs for the
7194 AltiVec predicates. */
7196 switch (cr6_form_int)
7199 emit_insn (gen_cr6_test_for_zero (target));
7202 emit_insn (gen_cr6_test_for_zero_reverse (target));
7205 emit_insn (gen_cr6_test_for_lt (target));
7208 emit_insn (gen_cr6_test_for_lt_reverse (target));
7211 error ("argument 1 of __builtin_altivec_predicate is out of range");
7219 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7222 tree arg0 = CALL_EXPR_ARG (exp, 0);
7223 tree arg1 = CALL_EXPR_ARG (exp, 1);
7224 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7225 enum machine_mode mode0 = Pmode;
7226 enum machine_mode mode1 = Pmode;
7227 rtx op0 = expand_normal (arg0);
7228 rtx op1 = expand_normal (arg1);
7230 if (icode == CODE_FOR_nothing)
7231 /* Builtin not supported on this processor. */
7234 /* If we got invalid arguments bail out before generating bad rtl. */
7235 if (arg0 == error_mark_node || arg1 == error_mark_node)
7239 || GET_MODE (target) != tmode
7240 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7241 target = gen_reg_rtx (tmode);
7243 op1 = copy_to_mode_reg (mode1, op1);
7245 if (op0 == const0_rtx)
7247 addr = gen_rtx_MEM (tmode, op1);
7251 op0 = copy_to_mode_reg (mode0, op0);
7252 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7255 pat = GEN_FCN (icode) (target, addr);
7265 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7267 tree arg0 = CALL_EXPR_ARG (exp, 0);
7268 tree arg1 = CALL_EXPR_ARG (exp, 1);
7269 tree arg2 = CALL_EXPR_ARG (exp, 2);
7270 rtx op0 = expand_normal (arg0);
7271 rtx op1 = expand_normal (arg1);
7272 rtx op2 = expand_normal (arg2);
7274 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7275 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7276 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7278 /* Invalid arguments. Bail before doing anything stoopid! */
7279 if (arg0 == error_mark_node
7280 || arg1 == error_mark_node
7281 || arg2 == error_mark_node)
7284 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7285 op0 = copy_to_mode_reg (mode2, op0);
7286 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7287 op1 = copy_to_mode_reg (mode0, op1);
7288 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7289 op2 = copy_to_mode_reg (mode1, op2);
7291 pat = GEN_FCN (icode) (op1, op2, op0);
7298 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7300 tree arg0 = CALL_EXPR_ARG (exp, 0);
7301 tree arg1 = CALL_EXPR_ARG (exp, 1);
7302 tree arg2 = CALL_EXPR_ARG (exp, 2);
7303 rtx op0 = expand_normal (arg0);
7304 rtx op1 = expand_normal (arg1);
7305 rtx op2 = expand_normal (arg2);
7307 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7308 enum machine_mode mode1 = Pmode;
7309 enum machine_mode mode2 = Pmode;
7311 /* Invalid arguments. Bail before doing anything stoopid! */
7312 if (arg0 == error_mark_node
7313 || arg1 == error_mark_node
7314 || arg2 == error_mark_node)
7317 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7318 op0 = copy_to_mode_reg (tmode, op0);
7320 op2 = copy_to_mode_reg (mode2, op2);
7322 if (op1 == const0_rtx)
7324 addr = gen_rtx_MEM (tmode, op2);
7328 op1 = copy_to_mode_reg (mode1, op1);
7329 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7332 pat = GEN_FCN (icode) (addr, op0);
7339 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7342 tree arg0 = CALL_EXPR_ARG (exp, 0);
7343 tree arg1 = CALL_EXPR_ARG (exp, 1);
7344 tree arg2 = CALL_EXPR_ARG (exp, 2);
7345 rtx op0 = expand_normal (arg0);
7346 rtx op1 = expand_normal (arg1);
7347 rtx op2 = expand_normal (arg2);
7348 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7349 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7350 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7351 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7353 if (icode == CODE_FOR_nothing)
7354 /* Builtin not supported on this processor. */
7357 /* If we got invalid arguments bail out before generating bad rtl. */
7358 if (arg0 == error_mark_node
7359 || arg1 == error_mark_node
7360 || arg2 == error_mark_node)
7363 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7364 || icode == CODE_FOR_altivec_vsldoi_v4si
7365 || icode == CODE_FOR_altivec_vsldoi_v8hi
7366 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7368 /* Only allow 4-bit unsigned literals. */
7370 if (TREE_CODE (arg2) != INTEGER_CST
7371 || TREE_INT_CST_LOW (arg2) & ~0xf)
7373 error ("argument 3 must be a 4-bit unsigned literal");
7379 || GET_MODE (target) != tmode
7380 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7381 target = gen_reg_rtx (tmode);
7383 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7384 op0 = copy_to_mode_reg (mode0, op0);
7385 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7386 op1 = copy_to_mode_reg (mode1, op1);
7387 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7388 op2 = copy_to_mode_reg (mode2, op2);
7390 pat = GEN_FCN (icode) (target, op0, op1, op2);
7398 /* Expand the lvx builtins. */
7400 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7402 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7403 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7405 enum machine_mode tmode, mode0;
7407 enum insn_code icode;
7411 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7412 icode = CODE_FOR_altivec_lvx_v16qi;
7414 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7415 icode = CODE_FOR_altivec_lvx_v8hi;
7417 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7418 icode = CODE_FOR_altivec_lvx_v4si;
7420 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7421 icode = CODE_FOR_altivec_lvx_v4sf;
7430 arg0 = CALL_EXPR_ARG (exp, 0);
7431 op0 = expand_normal (arg0);
7432 tmode = insn_data[icode].operand[0].mode;
7433 mode0 = insn_data[icode].operand[1].mode;
7436 || GET_MODE (target) != tmode
7437 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7438 target = gen_reg_rtx (tmode);
7440 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7441 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7443 pat = GEN_FCN (icode) (target, op0);
7450 /* Expand the stvx builtins. */
7452 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7455 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7456 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7458 enum machine_mode mode0, mode1;
7460 enum insn_code icode;
7464 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7465 icode = CODE_FOR_altivec_stvx_v16qi;
7467 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7468 icode = CODE_FOR_altivec_stvx_v8hi;
7470 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7471 icode = CODE_FOR_altivec_stvx_v4si;
7473 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7474 icode = CODE_FOR_altivec_stvx_v4sf;
7481 arg0 = CALL_EXPR_ARG (exp, 0);
7482 arg1 = CALL_EXPR_ARG (exp, 1);
7483 op0 = expand_normal (arg0);
7484 op1 = expand_normal (arg1);
7485 mode0 = insn_data[icode].operand[0].mode;
7486 mode1 = insn_data[icode].operand[1].mode;
7488 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7489 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7490 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7491 op1 = copy_to_mode_reg (mode1, op1);
7493 pat = GEN_FCN (icode) (op0, op1);
7501 /* Expand the dst builtins. */
7503 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7506 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7507 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7508 tree arg0, arg1, arg2;
7509 enum machine_mode mode0, mode1, mode2;
7510 rtx pat, op0, op1, op2;
7511 struct builtin_description *d;
7516 /* Handle DST variants. */
7517 d = (struct builtin_description *) bdesc_dst;
7518 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7519 if (d->code == fcode)
7521 arg0 = CALL_EXPR_ARG (exp, 0);
7522 arg1 = CALL_EXPR_ARG (exp, 1);
7523 arg2 = CALL_EXPR_ARG (exp, 2);
7524 op0 = expand_normal (arg0);
7525 op1 = expand_normal (arg1);
7526 op2 = expand_normal (arg2);
7527 mode0 = insn_data[d->icode].operand[0].mode;
7528 mode1 = insn_data[d->icode].operand[1].mode;
7529 mode2 = insn_data[d->icode].operand[2].mode;
7531 /* Invalid arguments, bail out before generating bad rtl. */
7532 if (arg0 == error_mark_node
7533 || arg1 == error_mark_node
7534 || arg2 == error_mark_node)
7539 if (TREE_CODE (arg2) != INTEGER_CST
7540 || TREE_INT_CST_LOW (arg2) & ~0x3)
7542 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7546 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7547 op0 = copy_to_mode_reg (Pmode, op0);
7548 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7549 op1 = copy_to_mode_reg (mode1, op1);
7551 pat = GEN_FCN (d->icode) (op0, op1, op2);
7561 /* Expand vec_init builtin. */
7563 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7565 enum machine_mode tmode = TYPE_MODE (type);
7566 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7567 int i, n_elt = GET_MODE_NUNITS (tmode);
7568 rtvec v = rtvec_alloc (n_elt);
7570 gcc_assert (VECTOR_MODE_P (tmode));
7571 gcc_assert (n_elt == call_expr_nargs (exp));
7573 for (i = 0; i < n_elt; ++i)
7575 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7576 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7579 if (!target || !register_operand (target, tmode))
7580 target = gen_reg_rtx (tmode);
7582 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7586 /* Return the integer constant in ARG. Constrain it to be in the range
7587 of the subparts of VEC_TYPE; issue an error if not. */
7590 get_element_number (tree vec_type, tree arg)
7592 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7594 if (!host_integerp (arg, 1)
7595 || (elt = tree_low_cst (arg, 1), elt > max))
7597 error ("selector must be an integer constant in the range 0..%wi", max);
7604 /* Expand vec_set builtin. */
7606 altivec_expand_vec_set_builtin (tree exp)
7608 enum machine_mode tmode, mode1;
7609 tree arg0, arg1, arg2;
7613 arg0 = CALL_EXPR_ARG (exp, 0);
7614 arg1 = CALL_EXPR_ARG (exp, 1);
7615 arg2 = CALL_EXPR_ARG (exp, 2);
7617 tmode = TYPE_MODE (TREE_TYPE (arg0));
7618 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7619 gcc_assert (VECTOR_MODE_P (tmode));
7621 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7622 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7623 elt = get_element_number (TREE_TYPE (arg0), arg2);
7625 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7626 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7628 op0 = force_reg (tmode, op0);
7629 op1 = force_reg (mode1, op1);
7631 rs6000_expand_vector_set (op0, op1, elt);
7636 /* Expand vec_ext builtin. */
7638 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7640 enum machine_mode tmode, mode0;
7645 arg0 = CALL_EXPR_ARG (exp, 0);
7646 arg1 = CALL_EXPR_ARG (exp, 1);
7648 op0 = expand_normal (arg0);
7649 elt = get_element_number (TREE_TYPE (arg0), arg1);
7651 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7652 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7653 gcc_assert (VECTOR_MODE_P (mode0));
7655 op0 = force_reg (mode0, op0);
7657 if (optimize || !target || !register_operand (target, tmode))
7658 target = gen_reg_rtx (tmode);
7660 rs6000_expand_vector_extract (target, op0, elt);
7665 /* Expand the builtin in EXP and store the result in TARGET. Store
7666 true in *EXPANDEDP if we found a builtin to expand. */
7668 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7670 struct builtin_description *d;
7671 struct builtin_description_predicates *dp;
7673 enum insn_code icode;
7674 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7677 enum machine_mode tmode, mode0;
7678 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7680 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7681 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7684 error ("unresolved overload for Altivec builtin %qF", fndecl);
7688 target = altivec_expand_ld_builtin (exp, target, expandedp);
7692 target = altivec_expand_st_builtin (exp, target, expandedp);
7696 target = altivec_expand_dst_builtin (exp, target, expandedp);
7704 case ALTIVEC_BUILTIN_STVX:
7705 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7706 case ALTIVEC_BUILTIN_STVEBX:
7707 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7708 case ALTIVEC_BUILTIN_STVEHX:
7709 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7710 case ALTIVEC_BUILTIN_STVEWX:
7711 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7712 case ALTIVEC_BUILTIN_STVXL:
7713 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7715 case ALTIVEC_BUILTIN_MFVSCR:
7716 icode = CODE_FOR_altivec_mfvscr;
7717 tmode = insn_data[icode].operand[0].mode;
7720 || GET_MODE (target) != tmode
7721 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7722 target = gen_reg_rtx (tmode);
7724 pat = GEN_FCN (icode) (target);
7730 case ALTIVEC_BUILTIN_MTVSCR:
7731 icode = CODE_FOR_altivec_mtvscr;
7732 arg0 = CALL_EXPR_ARG (exp, 0);
7733 op0 = expand_normal (arg0);
7734 mode0 = insn_data[icode].operand[0].mode;
7736 /* If we got invalid arguments bail out before generating bad rtl. */
7737 if (arg0 == error_mark_node)
7740 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7741 op0 = copy_to_mode_reg (mode0, op0);
7743 pat = GEN_FCN (icode) (op0);
7748 case ALTIVEC_BUILTIN_DSSALL:
7749 emit_insn (gen_altivec_dssall ());
7752 case ALTIVEC_BUILTIN_DSS:
7753 icode = CODE_FOR_altivec_dss;
7754 arg0 = CALL_EXPR_ARG (exp, 0);
7756 op0 = expand_normal (arg0);
7757 mode0 = insn_data[icode].operand[0].mode;
7759 /* If we got invalid arguments bail out before generating bad rtl. */
7760 if (arg0 == error_mark_node)
7763 if (TREE_CODE (arg0) != INTEGER_CST
7764 || TREE_INT_CST_LOW (arg0) & ~0x3)
7766 error ("argument to dss must be a 2-bit unsigned literal");
7770 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7771 op0 = copy_to_mode_reg (mode0, op0);
7773 emit_insn (gen_altivec_dss (op0));
7776 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7777 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7778 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7779 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7780 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7782 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7783 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7784 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7785 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7786 return altivec_expand_vec_set_builtin (exp);
7788 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7789 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7790 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7791 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7792 return altivec_expand_vec_ext_builtin (exp, target);
7799 /* Expand abs* operations. */
7800 d = (struct builtin_description *) bdesc_abs;
7801 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7802 if (d->code == fcode)
7803 return altivec_expand_abs_builtin (d->icode, exp, target);
7805 /* Expand the AltiVec predicates. */
7806 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7807 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7808 if (dp->code == fcode)
7809 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7812 /* LV* are funky. We initialized them differently. */
7815 case ALTIVEC_BUILTIN_LVSL:
7816 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7818 case ALTIVEC_BUILTIN_LVSR:
7819 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7821 case ALTIVEC_BUILTIN_LVEBX:
7822 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7824 case ALTIVEC_BUILTIN_LVEHX:
7825 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7827 case ALTIVEC_BUILTIN_LVEWX:
7828 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7830 case ALTIVEC_BUILTIN_LVXL:
7831 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7833 case ALTIVEC_BUILTIN_LVX:
7834 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7845 /* Binops that need to be initialized manually, but can be expanded
7846 automagically by rs6000_expand_binop_builtin. */
7847 static struct builtin_description bdesc_2arg_spe[] =
7849 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7850 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7851 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7852 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7853 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7854 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7855 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7856 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7857 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7858 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7859 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7860 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7861 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7862 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7863 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7864 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7865 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7866 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7867 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7868 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7869 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7870 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7873 /* Expand the builtin in EXP and store the result in TARGET. Store
7874 true in *EXPANDEDP if we found a builtin to expand.
7876 This expands the SPE builtins that are not simple unary and binary
7879 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7881 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7883 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7884 enum insn_code icode;
7885 enum machine_mode tmode, mode0;
7887 struct builtin_description *d;
7892 /* Syntax check for a 5-bit unsigned immediate. */
7895 case SPE_BUILTIN_EVSTDD:
7896 case SPE_BUILTIN_EVSTDH:
7897 case SPE_BUILTIN_EVSTDW:
7898 case SPE_BUILTIN_EVSTWHE:
7899 case SPE_BUILTIN_EVSTWHO:
7900 case SPE_BUILTIN_EVSTWWE:
7901 case SPE_BUILTIN_EVSTWWO:
7902 arg1 = CALL_EXPR_ARG (exp, 2);
7903 if (TREE_CODE (arg1) != INTEGER_CST
7904 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7906 error ("argument 2 must be a 5-bit unsigned literal");
7914 /* The evsplat*i instructions are not quite generic. */
7917 case SPE_BUILTIN_EVSPLATFI:
7918 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7920 case SPE_BUILTIN_EVSPLATI:
7921 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7927 d = (struct builtin_description *) bdesc_2arg_spe;
7928 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7929 if (d->code == fcode)
7930 return rs6000_expand_binop_builtin (d->icode, exp, target);
7932 d = (struct builtin_description *) bdesc_spe_predicates;
7933 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7934 if (d->code == fcode)
7935 return spe_expand_predicate_builtin (d->icode, exp, target);
7937 d = (struct builtin_description *) bdesc_spe_evsel;
7938 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7939 if (d->code == fcode)
7940 return spe_expand_evsel_builtin (d->icode, exp, target);
7944 case SPE_BUILTIN_EVSTDDX:
7945 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
7946 case SPE_BUILTIN_EVSTDHX:
7947 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
7948 case SPE_BUILTIN_EVSTDWX:
7949 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
7950 case SPE_BUILTIN_EVSTWHEX:
7951 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
7952 case SPE_BUILTIN_EVSTWHOX:
7953 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
7954 case SPE_BUILTIN_EVSTWWEX:
7955 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
7956 case SPE_BUILTIN_EVSTWWOX:
7957 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
7958 case SPE_BUILTIN_EVSTDD:
7959 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
7960 case SPE_BUILTIN_EVSTDH:
7961 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
7962 case SPE_BUILTIN_EVSTDW:
7963 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
7964 case SPE_BUILTIN_EVSTWHE:
7965 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
7966 case SPE_BUILTIN_EVSTWHO:
7967 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
7968 case SPE_BUILTIN_EVSTWWE:
7969 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
7970 case SPE_BUILTIN_EVSTWWO:
7971 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
7972 case SPE_BUILTIN_MFSPEFSCR:
7973 icode = CODE_FOR_spe_mfspefscr;
7974 tmode = insn_data[icode].operand[0].mode;
7977 || GET_MODE (target) != tmode
7978 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7979 target = gen_reg_rtx (tmode);
7981 pat = GEN_FCN (icode) (target);
7986 case SPE_BUILTIN_MTSPEFSCR:
7987 icode = CODE_FOR_spe_mtspefscr;
7988 arg0 = CALL_EXPR_ARG (exp, 0);
7989 op0 = expand_normal (arg0);
7990 mode0 = insn_data[icode].operand[0].mode;
7992 if (arg0 == error_mark_node)
7995 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7996 op0 = copy_to_mode_reg (mode0, op0);
7998 pat = GEN_FCN (icode) (op0);
8011 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8013 rtx pat, scratch, tmp;
8014 tree form = CALL_EXPR_ARG (exp, 0);
8015 tree arg0 = CALL_EXPR_ARG (exp, 1);
8016 tree arg1 = CALL_EXPR_ARG (exp, 2);
8017 rtx op0 = expand_normal (arg0);
8018 rtx op1 = expand_normal (arg1);
8019 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8020 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8024 if (TREE_CODE (form) != INTEGER_CST)
8026 error ("argument 1 of __builtin_spe_predicate must be a constant");
8030 form_int = TREE_INT_CST_LOW (form);
8032 gcc_assert (mode0 == mode1);
8034 if (arg0 == error_mark_node || arg1 == error_mark_node)
8038 || GET_MODE (target) != SImode
8039 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8040 target = gen_reg_rtx (SImode);
8042 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8043 op0 = copy_to_mode_reg (mode0, op0);
8044 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8045 op1 = copy_to_mode_reg (mode1, op1);
8047 scratch = gen_reg_rtx (CCmode);
8049 pat = GEN_FCN (icode) (scratch, op0, op1);
8054 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8055 _lower_. We use one compare, but look in different bits of the
8056 CR for each variant.
8058 There are 2 elements in each SPE simd type (upper/lower). The CR
8059 bits are set as follows:
8061 BIT0 | BIT 1 | BIT 2 | BIT 3
8062 U | L | (U | L) | (U & L)
8064 So, for an "all" relationship, BIT 3 would be set.
8065 For an "any" relationship, BIT 2 would be set. Etc.
8067 Following traditional nomenclature, these bits map to:
8069 BIT0 | BIT 1 | BIT 2 | BIT 3
8072 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8077 /* All variant. OV bit. */
8079 /* We need to get to the OV bit, which is the ORDERED bit. We
8080 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8081 that's ugly and will make validate_condition_mode die.
8082 So let's just use another pattern. */
8083 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8085 /* Any variant. EQ bit. */
8089 /* Upper variant. LT bit. */
8093 /* Lower variant. GT bit. */
8098 error ("argument 1 of __builtin_spe_predicate is out of range");
8102 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8103 emit_move_insn (target, tmp);
8108 /* The evsel builtins look like this:
8110 e = __builtin_spe_evsel_OP (a, b, c, d);
8114 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8115 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8119 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8122 tree arg0 = CALL_EXPR_ARG (exp, 0);
8123 tree arg1 = CALL_EXPR_ARG (exp, 1);
8124 tree arg2 = CALL_EXPR_ARG (exp, 2);
8125 tree arg3 = CALL_EXPR_ARG (exp, 3);
8126 rtx op0 = expand_normal (arg0);
8127 rtx op1 = expand_normal (arg1);
8128 rtx op2 = expand_normal (arg2);
8129 rtx op3 = expand_normal (arg3);
8130 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8131 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8133 gcc_assert (mode0 == mode1);
8135 if (arg0 == error_mark_node || arg1 == error_mark_node
8136 || arg2 == error_mark_node || arg3 == error_mark_node)
8140 || GET_MODE (target) != mode0
8141 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8142 target = gen_reg_rtx (mode0);
8144 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8145 op0 = copy_to_mode_reg (mode0, op0);
8146 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8147 op1 = copy_to_mode_reg (mode0, op1);
8148 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8149 op2 = copy_to_mode_reg (mode0, op2);
8150 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8151 op3 = copy_to_mode_reg (mode0, op3);
8153 /* Generate the compare. */
8154 scratch = gen_reg_rtx (CCmode);
8155 pat = GEN_FCN (icode) (scratch, op0, op1);
8160 if (mode0 == V2SImode)
8161 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8163 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8168 /* Expand an expression EXP that calls a built-in function,
8169 with result going to TARGET if that's convenient
8170 (and in mode MODE if that's convenient).
8171 SUBTARGET may be used as the target for computing one of EXP's operands.
8172 IGNORE is nonzero if the value is to be ignored. */
8175 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8176 enum machine_mode mode ATTRIBUTE_UNUSED,
8177 int ignore ATTRIBUTE_UNUSED)
8179 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8180 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8181 struct builtin_description *d;
8186 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8187 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8189 int icode = (int) CODE_FOR_altivec_lvsr;
8190 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8191 enum machine_mode mode = insn_data[icode].operand[1].mode;
8195 gcc_assert (TARGET_ALTIVEC);
8197 arg = CALL_EXPR_ARG (exp, 0);
8198 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8199 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8200 addr = memory_address (mode, op);
8201 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8205 /* For the load case need to negate the address. */
8206 op = gen_reg_rtx (GET_MODE (addr));
8207 emit_insn (gen_rtx_SET (VOIDmode, op,
8208 gen_rtx_NEG (GET_MODE (addr), addr)));
8210 op = gen_rtx_MEM (mode, op);
8213 || GET_MODE (target) != tmode
8214 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8215 target = gen_reg_rtx (tmode);
8217 /*pat = gen_altivec_lvsr (target, op);*/
8218 pat = GEN_FCN (icode) (target, op);
8226 /* FIXME: There's got to be a nicer way to handle this case than
8227 constructing a new CALL_EXPR. */
8228 if (fcode == ALTIVEC_BUILTIN_VCFUX
8229 || fcode == ALTIVEC_BUILTIN_VCFSX)
8231 if (call_expr_nargs (exp) == 1)
8232 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8233 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8238 ret = altivec_expand_builtin (exp, target, &success);
8245 ret = spe_expand_builtin (exp, target, &success);
8251 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8253 /* Handle simple unary operations. */
8254 d = (struct builtin_description *) bdesc_1arg;
8255 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8256 if (d->code == fcode)
8257 return rs6000_expand_unop_builtin (d->icode, exp, target);
8259 /* Handle simple binary operations. */
8260 d = (struct builtin_description *) bdesc_2arg;
8261 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8262 if (d->code == fcode)
8263 return rs6000_expand_binop_builtin (d->icode, exp, target);
8265 /* Handle simple ternary operations. */
8266 d = (struct builtin_description *) bdesc_3arg;
8267 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8268 if (d->code == fcode)
8269 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8275 build_opaque_vector_type (tree node, int nunits)
8277 node = copy_node (node);
8278 TYPE_MAIN_VARIANT (node) = node;
8279 return build_vector_type (node, nunits);
8283 rs6000_init_builtins (void)
8285 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8286 V2SF_type_node = build_vector_type (float_type_node, 2);
8287 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8288 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8289 V4SF_type_node = build_vector_type (float_type_node, 4);
8290 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8291 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8293 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8294 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8295 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8297 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8298 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8299 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8300 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8302 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8303 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8304 'vector unsigned short'. */
8306 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8307 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8308 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8309 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8311 long_integer_type_internal_node = long_integer_type_node;
8312 long_unsigned_type_internal_node = long_unsigned_type_node;
8313 intQI_type_internal_node = intQI_type_node;
8314 uintQI_type_internal_node = unsigned_intQI_type_node;
8315 intHI_type_internal_node = intHI_type_node;
8316 uintHI_type_internal_node = unsigned_intHI_type_node;
8317 intSI_type_internal_node = intSI_type_node;
8318 uintSI_type_internal_node = unsigned_intSI_type_node;
8319 float_type_internal_node = float_type_node;
8320 void_type_internal_node = void_type_node;
8322 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8323 get_identifier ("__bool char"),
8324 bool_char_type_node));
8325 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8326 get_identifier ("__bool short"),
8327 bool_short_type_node));
8328 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8329 get_identifier ("__bool int"),
8330 bool_int_type_node));
8331 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8332 get_identifier ("__pixel"),
8335 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8336 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8337 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8338 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8340 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8341 get_identifier ("__vector unsigned char"),
8342 unsigned_V16QI_type_node));
8343 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8344 get_identifier ("__vector signed char"),
8346 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8347 get_identifier ("__vector __bool char"),
8348 bool_V16QI_type_node));
8350 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8351 get_identifier ("__vector unsigned short"),
8352 unsigned_V8HI_type_node));
8353 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8354 get_identifier ("__vector signed short"),
8356 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8357 get_identifier ("__vector __bool short"),
8358 bool_V8HI_type_node));
8360 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8361 get_identifier ("__vector unsigned int"),
8362 unsigned_V4SI_type_node));
8363 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8364 get_identifier ("__vector signed int"),
8366 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8367 get_identifier ("__vector __bool int"),
8368 bool_V4SI_type_node));
8370 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8371 get_identifier ("__vector float"),
8373 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8374 get_identifier ("__vector __pixel"),
8375 pixel_V8HI_type_node));
8378 spe_init_builtins ();
8380 altivec_init_builtins ();
8381 if (TARGET_ALTIVEC || TARGET_SPE)
8382 rs6000_common_init_builtins ();
8385 /* AIX libm provides clog as __clog. */
8386 if (built_in_decls [BUILT_IN_CLOG])
8387 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8391 /* Search through a set of builtins and enable the mask bits.
8392 DESC is an array of builtins.
8393 SIZE is the total number of builtins.
8394 START is the builtin enum at which to start.
8395 END is the builtin enum at which to end. */
8397 enable_mask_for_builtins (struct builtin_description *desc, int size,
8398 enum rs6000_builtins start,
8399 enum rs6000_builtins end)
8403 for (i = 0; i < size; ++i)
8404 if (desc[i].code == start)
8410 for (; i < size; ++i)
8412 /* Flip all the bits on. */
8413 desc[i].mask = target_flags;
8414 if (desc[i].code == end)
8420 spe_init_builtins (void)
8422 tree endlink = void_list_node;
8423 tree puint_type_node = build_pointer_type (unsigned_type_node);
8424 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8425 struct builtin_description *d;
8428 tree v2si_ftype_4_v2si
8429 = build_function_type
8430 (opaque_V2SI_type_node,
8431 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8432 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8433 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8434 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8437 tree v2sf_ftype_4_v2sf
8438 = build_function_type
8439 (opaque_V2SF_type_node,
8440 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8441 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8442 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8443 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8446 tree int_ftype_int_v2si_v2si
8447 = build_function_type
8449 tree_cons (NULL_TREE, integer_type_node,
8450 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8451 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8454 tree int_ftype_int_v2sf_v2sf
8455 = build_function_type
8457 tree_cons (NULL_TREE, integer_type_node,
8458 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8459 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8462 tree void_ftype_v2si_puint_int
8463 = build_function_type (void_type_node,
8464 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8465 tree_cons (NULL_TREE, puint_type_node,
8466 tree_cons (NULL_TREE,
8470 tree void_ftype_v2si_puint_char
8471 = build_function_type (void_type_node,
8472 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8473 tree_cons (NULL_TREE, puint_type_node,
8474 tree_cons (NULL_TREE,
8478 tree void_ftype_v2si_pv2si_int
8479 = build_function_type (void_type_node,
8480 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8481 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8482 tree_cons (NULL_TREE,
8486 tree void_ftype_v2si_pv2si_char
8487 = build_function_type (void_type_node,
8488 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8489 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8490 tree_cons (NULL_TREE,
8495 = build_function_type (void_type_node,
8496 tree_cons (NULL_TREE, integer_type_node, endlink));
8499 = build_function_type (integer_type_node, endlink);
8501 tree v2si_ftype_pv2si_int
8502 = build_function_type (opaque_V2SI_type_node,
8503 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8504 tree_cons (NULL_TREE, integer_type_node,
8507 tree v2si_ftype_puint_int
8508 = build_function_type (opaque_V2SI_type_node,
8509 tree_cons (NULL_TREE, puint_type_node,
8510 tree_cons (NULL_TREE, integer_type_node,
8513 tree v2si_ftype_pushort_int
8514 = build_function_type (opaque_V2SI_type_node,
8515 tree_cons (NULL_TREE, pushort_type_node,
8516 tree_cons (NULL_TREE, integer_type_node,
8519 tree v2si_ftype_signed_char
8520 = build_function_type (opaque_V2SI_type_node,
8521 tree_cons (NULL_TREE, signed_char_type_node,
8524 /* The initialization of the simple binary and unary builtins is
8525 done in rs6000_common_init_builtins, but we have to enable the
8526 mask bits here manually because we have run out of `target_flags'
8527 bits. We really need to redesign this mask business. */
8529 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8530 ARRAY_SIZE (bdesc_2arg),
8533 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8534 ARRAY_SIZE (bdesc_1arg),
8536 SPE_BUILTIN_EVSUBFUSIAAW);
8537 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8538 ARRAY_SIZE (bdesc_spe_predicates),
8539 SPE_BUILTIN_EVCMPEQ,
8540 SPE_BUILTIN_EVFSTSTLT);
8541 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8542 ARRAY_SIZE (bdesc_spe_evsel),
8543 SPE_BUILTIN_EVSEL_CMPGTS,
8544 SPE_BUILTIN_EVSEL_FSTSTEQ);
8546 (*lang_hooks.decls.pushdecl)
8547 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8548 opaque_V2SI_type_node));
8550 /* Initialize irregular SPE builtins. */
8552 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8553 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8554 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8555 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8556 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8557 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8558 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8559 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8560 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8561 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8562 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8563 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8564 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8565 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8566 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8567 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8568 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8569 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8572 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8573 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8574 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8575 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8576 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8577 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8578 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8579 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8580 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8581 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8582 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8583 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8584 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8585 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8586 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8587 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8588 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8589 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8590 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8591 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8592 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8593 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8596 d = (struct builtin_description *) bdesc_spe_predicates;
8597 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8601 switch (insn_data[d->icode].operand[1].mode)
8604 type = int_ftype_int_v2si_v2si;
8607 type = int_ftype_int_v2sf_v2sf;
8613 def_builtin (d->mask, d->name, type, d->code);
8616 /* Evsel predicates. */
8617 d = (struct builtin_description *) bdesc_spe_evsel;
8618 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8622 switch (insn_data[d->icode].operand[1].mode)
8625 type = v2si_ftype_4_v2si;
8628 type = v2sf_ftype_4_v2sf;
8634 def_builtin (d->mask, d->name, type, d->code);
8639 altivec_init_builtins (void)
8641 struct builtin_description *d;
8642 struct builtin_description_predicates *dp;
8646 tree pfloat_type_node = build_pointer_type (float_type_node);
8647 tree pint_type_node = build_pointer_type (integer_type_node);
8648 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8649 tree pchar_type_node = build_pointer_type (char_type_node);
8651 tree pvoid_type_node = build_pointer_type (void_type_node);
8653 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8654 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8655 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8656 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8658 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8660 tree int_ftype_opaque
8661 = build_function_type_list (integer_type_node,
8662 opaque_V4SI_type_node, NULL_TREE);
8664 tree opaque_ftype_opaque_int
8665 = build_function_type_list (opaque_V4SI_type_node,
8666 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8667 tree opaque_ftype_opaque_opaque_int
8668 = build_function_type_list (opaque_V4SI_type_node,
8669 opaque_V4SI_type_node, opaque_V4SI_type_node,
8670 integer_type_node, NULL_TREE);
8671 tree int_ftype_int_opaque_opaque
8672 = build_function_type_list (integer_type_node,
8673 integer_type_node, opaque_V4SI_type_node,
8674 opaque_V4SI_type_node, NULL_TREE);
8675 tree int_ftype_int_v4si_v4si
8676 = build_function_type_list (integer_type_node,
8677 integer_type_node, V4SI_type_node,
8678 V4SI_type_node, NULL_TREE);
8679 tree v4sf_ftype_pcfloat
8680 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8681 tree void_ftype_pfloat_v4sf
8682 = build_function_type_list (void_type_node,
8683 pfloat_type_node, V4SF_type_node, NULL_TREE);
8684 tree v4si_ftype_pcint
8685 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8686 tree void_ftype_pint_v4si
8687 = build_function_type_list (void_type_node,
8688 pint_type_node, V4SI_type_node, NULL_TREE);
8689 tree v8hi_ftype_pcshort
8690 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8691 tree void_ftype_pshort_v8hi
8692 = build_function_type_list (void_type_node,
8693 pshort_type_node, V8HI_type_node, NULL_TREE);
8694 tree v16qi_ftype_pcchar
8695 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8696 tree void_ftype_pchar_v16qi
8697 = build_function_type_list (void_type_node,
8698 pchar_type_node, V16QI_type_node, NULL_TREE);
8699 tree void_ftype_v4si
8700 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8701 tree v8hi_ftype_void
8702 = build_function_type (V8HI_type_node, void_list_node);
8703 tree void_ftype_void
8704 = build_function_type (void_type_node, void_list_node);
8706 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8708 tree opaque_ftype_long_pcvoid
8709 = build_function_type_list (opaque_V4SI_type_node,
8710 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8711 tree v16qi_ftype_long_pcvoid
8712 = build_function_type_list (V16QI_type_node,
8713 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8714 tree v8hi_ftype_long_pcvoid
8715 = build_function_type_list (V8HI_type_node,
8716 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8717 tree v4si_ftype_long_pcvoid
8718 = build_function_type_list (V4SI_type_node,
8719 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8721 tree void_ftype_opaque_long_pvoid
8722 = build_function_type_list (void_type_node,
8723 opaque_V4SI_type_node, long_integer_type_node,
8724 pvoid_type_node, NULL_TREE);
8725 tree void_ftype_v4si_long_pvoid
8726 = build_function_type_list (void_type_node,
8727 V4SI_type_node, long_integer_type_node,
8728 pvoid_type_node, NULL_TREE);
8729 tree void_ftype_v16qi_long_pvoid
8730 = build_function_type_list (void_type_node,
8731 V16QI_type_node, long_integer_type_node,
8732 pvoid_type_node, NULL_TREE);
8733 tree void_ftype_v8hi_long_pvoid
8734 = build_function_type_list (void_type_node,
8735 V8HI_type_node, long_integer_type_node,
8736 pvoid_type_node, NULL_TREE);
8737 tree int_ftype_int_v8hi_v8hi
8738 = build_function_type_list (integer_type_node,
8739 integer_type_node, V8HI_type_node,
8740 V8HI_type_node, NULL_TREE);
8741 tree int_ftype_int_v16qi_v16qi
8742 = build_function_type_list (integer_type_node,
8743 integer_type_node, V16QI_type_node,
8744 V16QI_type_node, NULL_TREE);
8745 tree int_ftype_int_v4sf_v4sf
8746 = build_function_type_list (integer_type_node,
8747 integer_type_node, V4SF_type_node,
8748 V4SF_type_node, NULL_TREE);
8749 tree v4si_ftype_v4si
8750 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8751 tree v8hi_ftype_v8hi
8752 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8753 tree v16qi_ftype_v16qi
8754 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8755 tree v4sf_ftype_v4sf
8756 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8757 tree void_ftype_pcvoid_int_int
8758 = build_function_type_list (void_type_node,
8759 pcvoid_type_node, integer_type_node,
8760 integer_type_node, NULL_TREE);
8762 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8763 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8764 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8765 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8766 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8767 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8768 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8769 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8770 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8771 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8772 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8773 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8774 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8775 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8776 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8777 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8778 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8779 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8780 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8781 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8782 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8783 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8784 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8785 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8786 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8787 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8788 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8789 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8790 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8791 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8792 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8793 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8794 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8795 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8796 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8797 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8798 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8799 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8800 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8801 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8802 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8803 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8804 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8805 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8806 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8807 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8809 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8811 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8812 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8813 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8814 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8815 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8816 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8817 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8818 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8819 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8820 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8822 /* Add the DST variants. */
8823 d = (struct builtin_description *) bdesc_dst;
8824 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8825 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8827 /* Initialize the predicates. */
8828 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8829 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8831 enum machine_mode mode1;
8833 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8834 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8839 mode1 = insn_data[dp->icode].operand[1].mode;
8844 type = int_ftype_int_opaque_opaque;
8847 type = int_ftype_int_v4si_v4si;
8850 type = int_ftype_int_v8hi_v8hi;
8853 type = int_ftype_int_v16qi_v16qi;
8856 type = int_ftype_int_v4sf_v4sf;
8862 def_builtin (dp->mask, dp->name, type, dp->code);
8865 /* Initialize the abs* operators. */
8866 d = (struct builtin_description *) bdesc_abs;
8867 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8869 enum machine_mode mode0;
8872 mode0 = insn_data[d->icode].operand[0].mode;
8877 type = v4si_ftype_v4si;
8880 type = v8hi_ftype_v8hi;
8883 type = v16qi_ftype_v16qi;
8886 type = v4sf_ftype_v4sf;
8892 def_builtin (d->mask, d->name, type, d->code);
8899 /* Initialize target builtin that implements
8900 targetm.vectorize.builtin_mask_for_load. */
8902 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
8903 v16qi_ftype_long_pcvoid,
8904 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8905 BUILT_IN_MD, NULL, NULL_TREE);
8906 TREE_READONLY (decl) = 1;
8907 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8908 altivec_builtin_mask_for_load = decl;
8911 /* Access to the vec_init patterns. */
8912 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8913 integer_type_node, integer_type_node,
8914 integer_type_node, NULL_TREE);
8915 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8916 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8918 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8919 short_integer_type_node,
8920 short_integer_type_node,
8921 short_integer_type_node,
8922 short_integer_type_node,
8923 short_integer_type_node,
8924 short_integer_type_node,
8925 short_integer_type_node, NULL_TREE);
8926 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8927 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8929 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8930 char_type_node, char_type_node,
8931 char_type_node, char_type_node,
8932 char_type_node, char_type_node,
8933 char_type_node, char_type_node,
8934 char_type_node, char_type_node,
8935 char_type_node, char_type_node,
8936 char_type_node, char_type_node,
8937 char_type_node, NULL_TREE);
8938 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8939 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8941 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8942 float_type_node, float_type_node,
8943 float_type_node, NULL_TREE);
8944 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8945 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8947 /* Access to the vec_set patterns. */
8948 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8950 integer_type_node, NULL_TREE);
8951 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8952 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8954 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8956 integer_type_node, NULL_TREE);
8957 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8958 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8960 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8962 integer_type_node, NULL_TREE);
8963 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8964 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8966 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8968 integer_type_node, NULL_TREE);
8969 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8970 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8972 /* Access to the vec_extract patterns. */
8973 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8974 integer_type_node, NULL_TREE);
8975 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8976 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8978 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8979 integer_type_node, NULL_TREE);
8980 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8981 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8983 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8984 integer_type_node, NULL_TREE);
8985 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8986 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8988 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8989 integer_type_node, NULL_TREE);
8990 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8991 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8995 rs6000_common_init_builtins (void)
8997 struct builtin_description *d;
9000 tree v4sf_ftype_v4sf_v4sf_v16qi
9001 = build_function_type_list (V4SF_type_node,
9002 V4SF_type_node, V4SF_type_node,
9003 V16QI_type_node, NULL_TREE);
9004 tree v4si_ftype_v4si_v4si_v16qi
9005 = build_function_type_list (V4SI_type_node,
9006 V4SI_type_node, V4SI_type_node,
9007 V16QI_type_node, NULL_TREE);
9008 tree v8hi_ftype_v8hi_v8hi_v16qi
9009 = build_function_type_list (V8HI_type_node,
9010 V8HI_type_node, V8HI_type_node,
9011 V16QI_type_node, NULL_TREE);
9012 tree v16qi_ftype_v16qi_v16qi_v16qi
9013 = build_function_type_list (V16QI_type_node,
9014 V16QI_type_node, V16QI_type_node,
9015 V16QI_type_node, NULL_TREE);
9017 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9019 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9020 tree v16qi_ftype_int
9021 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9022 tree v8hi_ftype_v16qi
9023 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9024 tree v4sf_ftype_v4sf
9025 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9027 tree v2si_ftype_v2si_v2si
9028 = build_function_type_list (opaque_V2SI_type_node,
9029 opaque_V2SI_type_node,
9030 opaque_V2SI_type_node, NULL_TREE);
9032 tree v2sf_ftype_v2sf_v2sf
9033 = build_function_type_list (opaque_V2SF_type_node,
9034 opaque_V2SF_type_node,
9035 opaque_V2SF_type_node, NULL_TREE);
9037 tree v2si_ftype_int_int
9038 = build_function_type_list (opaque_V2SI_type_node,
9039 integer_type_node, integer_type_node,
9042 tree opaque_ftype_opaque
9043 = build_function_type_list (opaque_V4SI_type_node,
9044 opaque_V4SI_type_node, NULL_TREE);
9046 tree v2si_ftype_v2si
9047 = build_function_type_list (opaque_V2SI_type_node,
9048 opaque_V2SI_type_node, NULL_TREE);
9050 tree v2sf_ftype_v2sf
9051 = build_function_type_list (opaque_V2SF_type_node,
9052 opaque_V2SF_type_node, NULL_TREE);
9054 tree v2sf_ftype_v2si
9055 = build_function_type_list (opaque_V2SF_type_node,
9056 opaque_V2SI_type_node, NULL_TREE);
9058 tree v2si_ftype_v2sf
9059 = build_function_type_list (opaque_V2SI_type_node,
9060 opaque_V2SF_type_node, NULL_TREE);
9062 tree v2si_ftype_v2si_char
9063 = build_function_type_list (opaque_V2SI_type_node,
9064 opaque_V2SI_type_node,
9065 char_type_node, NULL_TREE);
9067 tree v2si_ftype_int_char
9068 = build_function_type_list (opaque_V2SI_type_node,
9069 integer_type_node, char_type_node, NULL_TREE);
9071 tree v2si_ftype_char
9072 = build_function_type_list (opaque_V2SI_type_node,
9073 char_type_node, NULL_TREE);
9075 tree int_ftype_int_int
9076 = build_function_type_list (integer_type_node,
9077 integer_type_node, integer_type_node,
9080 tree opaque_ftype_opaque_opaque
9081 = build_function_type_list (opaque_V4SI_type_node,
9082 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9083 tree v4si_ftype_v4si_v4si
9084 = build_function_type_list (V4SI_type_node,
9085 V4SI_type_node, V4SI_type_node, NULL_TREE);
9086 tree v4sf_ftype_v4si_int
9087 = build_function_type_list (V4SF_type_node,
9088 V4SI_type_node, integer_type_node, NULL_TREE);
9089 tree v4si_ftype_v4sf_int
9090 = build_function_type_list (V4SI_type_node,
9091 V4SF_type_node, integer_type_node, NULL_TREE);
9092 tree v4si_ftype_v4si_int
9093 = build_function_type_list (V4SI_type_node,
9094 V4SI_type_node, integer_type_node, NULL_TREE);
9095 tree v8hi_ftype_v8hi_int
9096 = build_function_type_list (V8HI_type_node,
9097 V8HI_type_node, integer_type_node, NULL_TREE);
9098 tree v16qi_ftype_v16qi_int
9099 = build_function_type_list (V16QI_type_node,
9100 V16QI_type_node, integer_type_node, NULL_TREE);
9101 tree v16qi_ftype_v16qi_v16qi_int
9102 = build_function_type_list (V16QI_type_node,
9103 V16QI_type_node, V16QI_type_node,
9104 integer_type_node, NULL_TREE);
9105 tree v8hi_ftype_v8hi_v8hi_int
9106 = build_function_type_list (V8HI_type_node,
9107 V8HI_type_node, V8HI_type_node,
9108 integer_type_node, NULL_TREE);
9109 tree v4si_ftype_v4si_v4si_int
9110 = build_function_type_list (V4SI_type_node,
9111 V4SI_type_node, V4SI_type_node,
9112 integer_type_node, NULL_TREE);
9113 tree v4sf_ftype_v4sf_v4sf_int
9114 = build_function_type_list (V4SF_type_node,
9115 V4SF_type_node, V4SF_type_node,
9116 integer_type_node, NULL_TREE);
9117 tree v4sf_ftype_v4sf_v4sf
9118 = build_function_type_list (V4SF_type_node,
9119 V4SF_type_node, V4SF_type_node, NULL_TREE);
9120 tree opaque_ftype_opaque_opaque_opaque
9121 = build_function_type_list (opaque_V4SI_type_node,
9122 opaque_V4SI_type_node, opaque_V4SI_type_node,
9123 opaque_V4SI_type_node, NULL_TREE);
9124 tree v4sf_ftype_v4sf_v4sf_v4si
9125 = build_function_type_list (V4SF_type_node,
9126 V4SF_type_node, V4SF_type_node,
9127 V4SI_type_node, NULL_TREE);
9128 tree v4sf_ftype_v4sf_v4sf_v4sf
9129 = build_function_type_list (V4SF_type_node,
9130 V4SF_type_node, V4SF_type_node,
9131 V4SF_type_node, NULL_TREE);
9132 tree v4si_ftype_v4si_v4si_v4si
9133 = build_function_type_list (V4SI_type_node,
9134 V4SI_type_node, V4SI_type_node,
9135 V4SI_type_node, NULL_TREE);
9136 tree v8hi_ftype_v8hi_v8hi
9137 = build_function_type_list (V8HI_type_node,
9138 V8HI_type_node, V8HI_type_node, NULL_TREE);
9139 tree v8hi_ftype_v8hi_v8hi_v8hi
9140 = build_function_type_list (V8HI_type_node,
9141 V8HI_type_node, V8HI_type_node,
9142 V8HI_type_node, NULL_TREE);
9143 tree v4si_ftype_v8hi_v8hi_v4si
9144 = build_function_type_list (V4SI_type_node,
9145 V8HI_type_node, V8HI_type_node,
9146 V4SI_type_node, NULL_TREE);
9147 tree v4si_ftype_v16qi_v16qi_v4si
9148 = build_function_type_list (V4SI_type_node,
9149 V16QI_type_node, V16QI_type_node,
9150 V4SI_type_node, NULL_TREE);
9151 tree v16qi_ftype_v16qi_v16qi
9152 = build_function_type_list (V16QI_type_node,
9153 V16QI_type_node, V16QI_type_node, NULL_TREE);
9154 tree v4si_ftype_v4sf_v4sf
9155 = build_function_type_list (V4SI_type_node,
9156 V4SF_type_node, V4SF_type_node, NULL_TREE);
9157 tree v8hi_ftype_v16qi_v16qi
9158 = build_function_type_list (V8HI_type_node,
9159 V16QI_type_node, V16QI_type_node, NULL_TREE);
9160 tree v4si_ftype_v8hi_v8hi
9161 = build_function_type_list (V4SI_type_node,
9162 V8HI_type_node, V8HI_type_node, NULL_TREE);
9163 tree v8hi_ftype_v4si_v4si
9164 = build_function_type_list (V8HI_type_node,
9165 V4SI_type_node, V4SI_type_node, NULL_TREE);
9166 tree v16qi_ftype_v8hi_v8hi
9167 = build_function_type_list (V16QI_type_node,
9168 V8HI_type_node, V8HI_type_node, NULL_TREE);
9169 tree v4si_ftype_v16qi_v4si
9170 = build_function_type_list (V4SI_type_node,
9171 V16QI_type_node, V4SI_type_node, NULL_TREE);
9172 tree v4si_ftype_v16qi_v16qi
9173 = build_function_type_list (V4SI_type_node,
9174 V16QI_type_node, V16QI_type_node, NULL_TREE);
9175 tree v4si_ftype_v8hi_v4si
9176 = build_function_type_list (V4SI_type_node,
9177 V8HI_type_node, V4SI_type_node, NULL_TREE);
9178 tree v4si_ftype_v8hi
9179 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9180 tree int_ftype_v4si_v4si
9181 = build_function_type_list (integer_type_node,
9182 V4SI_type_node, V4SI_type_node, NULL_TREE);
9183 tree int_ftype_v4sf_v4sf
9184 = build_function_type_list (integer_type_node,
9185 V4SF_type_node, V4SF_type_node, NULL_TREE);
9186 tree int_ftype_v16qi_v16qi
9187 = build_function_type_list (integer_type_node,
9188 V16QI_type_node, V16QI_type_node, NULL_TREE);
9189 tree int_ftype_v8hi_v8hi
9190 = build_function_type_list (integer_type_node,
9191 V8HI_type_node, V8HI_type_node, NULL_TREE);
9193 /* Add the simple ternary operators. */
9194 d = (struct builtin_description *) bdesc_3arg;
9195 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9197 enum machine_mode mode0, mode1, mode2, mode3;
9199 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9200 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9211 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9214 mode0 = insn_data[d->icode].operand[0].mode;
9215 mode1 = insn_data[d->icode].operand[1].mode;
9216 mode2 = insn_data[d->icode].operand[2].mode;
9217 mode3 = insn_data[d->icode].operand[3].mode;
9220 /* When all four are of the same mode. */
9221 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9226 type = opaque_ftype_opaque_opaque_opaque;
9229 type = v4si_ftype_v4si_v4si_v4si;
9232 type = v4sf_ftype_v4sf_v4sf_v4sf;
9235 type = v8hi_ftype_v8hi_v8hi_v8hi;
9238 type = v16qi_ftype_v16qi_v16qi_v16qi;
9244 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9249 type = v4si_ftype_v4si_v4si_v16qi;
9252 type = v4sf_ftype_v4sf_v4sf_v16qi;
9255 type = v8hi_ftype_v8hi_v8hi_v16qi;
9258 type = v16qi_ftype_v16qi_v16qi_v16qi;
9264 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9265 && mode3 == V4SImode)
9266 type = v4si_ftype_v16qi_v16qi_v4si;
9267 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9268 && mode3 == V4SImode)
9269 type = v4si_ftype_v8hi_v8hi_v4si;
9270 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9271 && mode3 == V4SImode)
9272 type = v4sf_ftype_v4sf_v4sf_v4si;
9274 /* vchar, vchar, vchar, 4 bit literal. */
9275 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9277 type = v16qi_ftype_v16qi_v16qi_int;
9279 /* vshort, vshort, vshort, 4 bit literal. */
9280 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9282 type = v8hi_ftype_v8hi_v8hi_int;
9284 /* vint, vint, vint, 4 bit literal. */
9285 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9287 type = v4si_ftype_v4si_v4si_int;
9289 /* vfloat, vfloat, vfloat, 4 bit literal. */
9290 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9292 type = v4sf_ftype_v4sf_v4sf_int;
9297 def_builtin (d->mask, d->name, type, d->code);
9300 /* Add the simple binary operators. */
9301 d = (struct builtin_description *) bdesc_2arg;
9302 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9304 enum machine_mode mode0, mode1, mode2;
9306 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9307 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9317 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9320 mode0 = insn_data[d->icode].operand[0].mode;
9321 mode1 = insn_data[d->icode].operand[1].mode;
9322 mode2 = insn_data[d->icode].operand[2].mode;
9325 /* When all three operands are of the same mode. */
9326 if (mode0 == mode1 && mode1 == mode2)
9331 type = opaque_ftype_opaque_opaque;
9334 type = v4sf_ftype_v4sf_v4sf;
9337 type = v4si_ftype_v4si_v4si;
9340 type = v16qi_ftype_v16qi_v16qi;
9343 type = v8hi_ftype_v8hi_v8hi;
9346 type = v2si_ftype_v2si_v2si;
9349 type = v2sf_ftype_v2sf_v2sf;
9352 type = int_ftype_int_int;
9359 /* A few other combos we really don't want to do manually. */
9361 /* vint, vfloat, vfloat. */
9362 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9363 type = v4si_ftype_v4sf_v4sf;
9365 /* vshort, vchar, vchar. */
9366 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9367 type = v8hi_ftype_v16qi_v16qi;
9369 /* vint, vshort, vshort. */
9370 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9371 type = v4si_ftype_v8hi_v8hi;
9373 /* vshort, vint, vint. */
9374 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9375 type = v8hi_ftype_v4si_v4si;
9377 /* vchar, vshort, vshort. */
9378 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9379 type = v16qi_ftype_v8hi_v8hi;
9381 /* vint, vchar, vint. */
9382 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9383 type = v4si_ftype_v16qi_v4si;
9385 /* vint, vchar, vchar. */
9386 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9387 type = v4si_ftype_v16qi_v16qi;
9389 /* vint, vshort, vint. */
9390 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9391 type = v4si_ftype_v8hi_v4si;
9393 /* vint, vint, 5 bit literal. */
9394 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9395 type = v4si_ftype_v4si_int;
9397 /* vshort, vshort, 5 bit literal. */
9398 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9399 type = v8hi_ftype_v8hi_int;
9401 /* vchar, vchar, 5 bit literal. */
9402 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9403 type = v16qi_ftype_v16qi_int;
9405 /* vfloat, vint, 5 bit literal. */
9406 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9407 type = v4sf_ftype_v4si_int;
9409 /* vint, vfloat, 5 bit literal. */
9410 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9411 type = v4si_ftype_v4sf_int;
9413 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9414 type = v2si_ftype_int_int;
9416 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9417 type = v2si_ftype_v2si_char;
9419 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9420 type = v2si_ftype_int_char;
9425 gcc_assert (mode0 == SImode);
9429 type = int_ftype_v4si_v4si;
9432 type = int_ftype_v4sf_v4sf;
9435 type = int_ftype_v16qi_v16qi;
9438 type = int_ftype_v8hi_v8hi;
9445 def_builtin (d->mask, d->name, type, d->code);
9448 /* Add the simple unary operators. */
9449 d = (struct builtin_description *) bdesc_1arg;
9450 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9452 enum machine_mode mode0, mode1;
9454 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9455 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9464 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9467 mode0 = insn_data[d->icode].operand[0].mode;
9468 mode1 = insn_data[d->icode].operand[1].mode;
9471 if (mode0 == V4SImode && mode1 == QImode)
9472 type = v4si_ftype_int;
9473 else if (mode0 == V8HImode && mode1 == QImode)
9474 type = v8hi_ftype_int;
9475 else if (mode0 == V16QImode && mode1 == QImode)
9476 type = v16qi_ftype_int;
9477 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9478 type = opaque_ftype_opaque;
9479 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9480 type = v4sf_ftype_v4sf;
9481 else if (mode0 == V8HImode && mode1 == V16QImode)
9482 type = v8hi_ftype_v16qi;
9483 else if (mode0 == V4SImode && mode1 == V8HImode)
9484 type = v4si_ftype_v8hi;
9485 else if (mode0 == V2SImode && mode1 == V2SImode)
9486 type = v2si_ftype_v2si;
9487 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9488 type = v2sf_ftype_v2sf;
9489 else if (mode0 == V2SFmode && mode1 == V2SImode)
9490 type = v2sf_ftype_v2si;
9491 else if (mode0 == V2SImode && mode1 == V2SFmode)
9492 type = v2si_ftype_v2sf;
9493 else if (mode0 == V2SImode && mode1 == QImode)
9494 type = v2si_ftype_char;
9498 def_builtin (d->mask, d->name, type, d->code);
9503 rs6000_init_libfuncs (void)
9505 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9506 && !TARGET_POWER2 && !TARGET_POWERPC)
9508 /* AIX library routines for float->int conversion. */
9509 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9510 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9511 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9512 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9515 if (!TARGET_IEEEQUAD)
9516 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9517 if (!TARGET_XL_COMPAT)
9519 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9520 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9521 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9522 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9524 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9526 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9527 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9528 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9529 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9530 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9531 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9532 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9533 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9535 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9536 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9537 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9538 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9539 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9540 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9541 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9542 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9547 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9548 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9549 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9550 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9554 /* 32-bit SVR4 quad floating point routines. */
9556 set_optab_libfunc (add_optab, TFmode, "_q_add");
9557 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9558 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9559 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9560 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9561 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9562 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9564 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9565 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9566 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9567 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9568 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9569 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9571 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9572 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9573 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9574 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9575 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9576 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9577 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9578 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9583 /* Expand a block clear operation, and return 1 if successful. Return 0
9584 if we should let the compiler generate normal code.
9586 operands[0] is the destination
9587 operands[1] is the length
9588 operands[3] is the alignment */
9591 expand_block_clear (rtx operands[])
9593 rtx orig_dest = operands[0];
9594 rtx bytes_rtx = operands[1];
9595 rtx align_rtx = operands[3];
9596 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9597 HOST_WIDE_INT align;
9598 HOST_WIDE_INT bytes;
9603 /* If this is not a fixed size move, just call memcpy */
9607 /* This must be a fixed size alignment */
9608 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9609 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9611 /* Anything to clear? */
9612 bytes = INTVAL (bytes_rtx);
9616 /* Use the builtin memset after a point, to avoid huge code bloat.
9617 When optimize_size, avoid any significant code bloat; calling
9618 memset is about 4 instructions, so allow for one instruction to
9619 load zero and three to do clearing. */
9620 if (TARGET_ALTIVEC && align >= 128)
9622 else if (TARGET_POWERPC64 && align >= 32)
9627 if (optimize_size && bytes > 3 * clear_step)
9629 if (! optimize_size && bytes > 8 * clear_step)
9632 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9634 enum machine_mode mode = BLKmode;
9637 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9642 else if (bytes >= 8 && TARGET_POWERPC64
9643 /* 64-bit loads and stores require word-aligned
9645 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9650 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9651 { /* move 4 bytes */
9655 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9656 { /* move 2 bytes */
9660 else /* move 1 byte at a time */
9666 dest = adjust_address (orig_dest, mode, offset);
9668 emit_move_insn (dest, CONST0_RTX (mode));
9675 /* Expand a block move operation, and return 1 if successful. Return 0
9676 if we should let the compiler generate normal code.
9678 operands[0] is the destination
9679 operands[1] is the source
9680 operands[2] is the length
9681 operands[3] is the alignment */
9683 #define MAX_MOVE_REG 4
9686 expand_block_move (rtx operands[])
9688 rtx orig_dest = operands[0];
9689 rtx orig_src = operands[1];
9690 rtx bytes_rtx = operands[2];
9691 rtx align_rtx = operands[3];
9692 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9697 rtx stores[MAX_MOVE_REG];
9700 /* If this is not a fixed size move, just call memcpy */
9704 /* This must be a fixed size alignment */
9705 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9706 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9708 /* Anything to move? */
9709 bytes = INTVAL (bytes_rtx);
9713 /* store_one_arg depends on expand_block_move to handle at least the size of
9714 reg_parm_stack_space. */
9715 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9718 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9721 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9722 rtx (*mov) (rtx, rtx);
9724 enum machine_mode mode = BLKmode;
9727 /* Altivec first, since it will be faster than a string move
9728 when it applies, and usually not significantly larger. */
9729 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9733 gen_func.mov = gen_movv4si;
9735 else if (TARGET_STRING
9736 && bytes > 24 /* move up to 32 bytes at a time */
9744 && ! fixed_regs[12])
9746 move_bytes = (bytes > 32) ? 32 : bytes;
9747 gen_func.movmemsi = gen_movmemsi_8reg;
9749 else if (TARGET_STRING
9750 && bytes > 16 /* move up to 24 bytes at a time */
9756 && ! fixed_regs[10])
9758 move_bytes = (bytes > 24) ? 24 : bytes;
9759 gen_func.movmemsi = gen_movmemsi_6reg;
9761 else if (TARGET_STRING
9762 && bytes > 8 /* move up to 16 bytes at a time */
9768 move_bytes = (bytes > 16) ? 16 : bytes;
9769 gen_func.movmemsi = gen_movmemsi_4reg;
9771 else if (bytes >= 8 && TARGET_POWERPC64
9772 /* 64-bit loads and stores require word-aligned
9774 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9778 gen_func.mov = gen_movdi;
9780 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9781 { /* move up to 8 bytes at a time */
9782 move_bytes = (bytes > 8) ? 8 : bytes;
9783 gen_func.movmemsi = gen_movmemsi_2reg;
9785 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9786 { /* move 4 bytes */
9789 gen_func.mov = gen_movsi;
9791 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9792 { /* move 2 bytes */
9795 gen_func.mov = gen_movhi;
9797 else if (TARGET_STRING && bytes > 1)
9798 { /* move up to 4 bytes at a time */
9799 move_bytes = (bytes > 4) ? 4 : bytes;
9800 gen_func.movmemsi = gen_movmemsi_1reg;
9802 else /* move 1 byte at a time */
9806 gen_func.mov = gen_movqi;
9809 src = adjust_address (orig_src, mode, offset);
9810 dest = adjust_address (orig_dest, mode, offset);
9812 if (mode != BLKmode)
9814 rtx tmp_reg = gen_reg_rtx (mode);
9816 emit_insn ((*gen_func.mov) (tmp_reg, src));
9817 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9820 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9823 for (i = 0; i < num_reg; i++)
9824 emit_insn (stores[i]);
9828 if (mode == BLKmode)
9830 /* Move the address into scratch registers. The movmemsi
9831 patterns require zero offset. */
9832 if (!REG_P (XEXP (src, 0)))
9834 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9835 src = replace_equiv_address (src, src_reg);
9837 set_mem_size (src, GEN_INT (move_bytes));
9839 if (!REG_P (XEXP (dest, 0)))
9841 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9842 dest = replace_equiv_address (dest, dest_reg);
9844 set_mem_size (dest, GEN_INT (move_bytes));
9846 emit_insn ((*gen_func.movmemsi) (dest, src,
9847 GEN_INT (move_bytes & 31),
9856 /* Return a string to perform a load_multiple operation.
9857 operands[0] is the vector.
9858 operands[1] is the source address.
9859 operands[2] is the first destination register. */
9862 rs6000_output_load_multiple (rtx operands[3])
9864 /* We have to handle the case where the pseudo used to contain the address
9865 is assigned to one of the output registers. */
9867 int words = XVECLEN (operands[0], 0);
9870 if (XVECLEN (operands[0], 0) == 1)
9871 return "{l|lwz} %2,0(%1)";
9873 for (i = 0; i < words; i++)
9874 if (refers_to_regno_p (REGNO (operands[2]) + i,
9875 REGNO (operands[2]) + i + 1, operands[1], 0))
9879 xop[0] = GEN_INT (4 * (words-1));
9880 xop[1] = operands[1];
9881 xop[2] = operands[2];
9882 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9887 xop[0] = GEN_INT (4 * (words-1));
9888 xop[1] = operands[1];
9889 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9890 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9895 for (j = 0; j < words; j++)
9898 xop[0] = GEN_INT (j * 4);
9899 xop[1] = operands[1];
9900 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9901 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9903 xop[0] = GEN_INT (i * 4);
9904 xop[1] = operands[1];
9905 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9910 return "{lsi|lswi} %2,%1,%N0";
9914 /* A validation routine: say whether CODE, a condition code, and MODE
9915 match. The other alternatives either don't make sense or should
9916 never be generated. */
9919 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9921 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9922 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9923 && GET_MODE_CLASS (mode) == MODE_CC);
9925 /* These don't make sense. */
9926 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9927 || mode != CCUNSmode);
9929 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9930 || mode == CCUNSmode);
9932 gcc_assert (mode == CCFPmode
9933 || (code != ORDERED && code != UNORDERED
9934 && code != UNEQ && code != LTGT
9935 && code != UNGT && code != UNLT
9936 && code != UNGE && code != UNLE));
9938 /* These should never be generated except for
9939 flag_finite_math_only. */
9940 gcc_assert (mode != CCFPmode
9941 || flag_finite_math_only
9942 || (code != LE && code != GE
9943 && code != UNEQ && code != LTGT
9944 && code != UNGT && code != UNLT));
9946 /* These are invalid; the information is not there. */
9947 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9951 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9952 mask required to convert the result of a rotate insn into a shift
9953 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9956 includes_lshift_p (rtx shiftop, rtx andop)
9958 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9960 shift_mask <<= INTVAL (shiftop);
9962 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9965 /* Similar, but for right shift. */
9968 includes_rshift_p (rtx shiftop, rtx andop)
9970 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9972 shift_mask >>= INTVAL (shiftop);
9974 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9977 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9978 to perform a left shift. It must have exactly SHIFTOP least
9979 significant 0's, then one or more 1's, then zero or more 0's. */
9982 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9984 if (GET_CODE (andop) == CONST_INT)
9986 HOST_WIDE_INT c, lsb, shift_mask;
9989 if (c == 0 || c == ~0)
9993 shift_mask <<= INTVAL (shiftop);
9995 /* Find the least significant one bit. */
9998 /* It must coincide with the LSB of the shift mask. */
9999 if (-lsb != shift_mask)
10002 /* Invert to look for the next transition (if any). */
10005 /* Remove the low group of ones (originally low group of zeros). */
10008 /* Again find the lsb, and check we have all 1's above. */
10012 else if (GET_CODE (andop) == CONST_DOUBLE
10013 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10015 HOST_WIDE_INT low, high, lsb;
10016 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10018 low = CONST_DOUBLE_LOW (andop);
10019 if (HOST_BITS_PER_WIDE_INT < 64)
10020 high = CONST_DOUBLE_HIGH (andop);
10022 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10023 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10026 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10028 shift_mask_high = ~0;
10029 if (INTVAL (shiftop) > 32)
10030 shift_mask_high <<= INTVAL (shiftop) - 32;
10032 lsb = high & -high;
10034 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10040 lsb = high & -high;
10041 return high == -lsb;
10044 shift_mask_low = ~0;
10045 shift_mask_low <<= INTVAL (shiftop);
10049 if (-lsb != shift_mask_low)
10052 if (HOST_BITS_PER_WIDE_INT < 64)
10057 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10059 lsb = high & -high;
10060 return high == -lsb;
10064 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10070 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10071 to perform a left shift. It must have SHIFTOP or more least
10072 significant 0's, with the remainder of the word 1's. */
10075 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10077 if (GET_CODE (andop) == CONST_INT)
10079 HOST_WIDE_INT c, lsb, shift_mask;
10082 shift_mask <<= INTVAL (shiftop);
10083 c = INTVAL (andop);
10085 /* Find the least significant one bit. */
10088 /* It must be covered by the shift mask.
10089 This test also rejects c == 0. */
10090 if ((lsb & shift_mask) == 0)
10093 /* Check we have all 1's above the transition, and reject all 1's. */
10094 return c == -lsb && lsb != 1;
10096 else if (GET_CODE (andop) == CONST_DOUBLE
10097 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10099 HOST_WIDE_INT low, lsb, shift_mask_low;
10101 low = CONST_DOUBLE_LOW (andop);
10103 if (HOST_BITS_PER_WIDE_INT < 64)
10105 HOST_WIDE_INT high, shift_mask_high;
10107 high = CONST_DOUBLE_HIGH (andop);
10111 shift_mask_high = ~0;
10112 if (INTVAL (shiftop) > 32)
10113 shift_mask_high <<= INTVAL (shiftop) - 32;
10115 lsb = high & -high;
10117 if ((lsb & shift_mask_high) == 0)
10120 return high == -lsb;
10126 shift_mask_low = ~0;
10127 shift_mask_low <<= INTVAL (shiftop);
10131 if ((lsb & shift_mask_low) == 0)
10134 return low == -lsb && lsb != 1;
10140 /* Return 1 if operands will generate a valid arguments to rlwimi
10141 instruction for insert with right shift in 64-bit mode. The mask may
10142 not start on the first bit or stop on the last bit because wrap-around
10143 effects of instruction do not correspond to semantics of RTL insn. */
10146 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10148 if (INTVAL (startop) > 32
10149 && INTVAL (startop) < 64
10150 && INTVAL (sizeop) > 1
10151 && INTVAL (sizeop) + INTVAL (startop) < 64
10152 && INTVAL (shiftop) > 0
10153 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10154 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10160 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10161 for lfq and stfq insns iff the registers are hard registers. */
10164 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10166 /* We might have been passed a SUBREG. */
10167 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10170 /* We might have been passed non floating point registers. */
10171 if (!FP_REGNO_P (REGNO (reg1))
10172 || !FP_REGNO_P (REGNO (reg2)))
10175 return (REGNO (reg1) == REGNO (reg2) - 1);
10178 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10179 addr1 and addr2 must be in consecutive memory locations
10180 (addr2 == addr1 + 8). */
10183 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10186 unsigned int reg1, reg2;
10187 int offset1, offset2;
10189 /* The mems cannot be volatile. */
10190 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10193 addr1 = XEXP (mem1, 0);
10194 addr2 = XEXP (mem2, 0);
10196 /* Extract an offset (if used) from the first addr. */
10197 if (GET_CODE (addr1) == PLUS)
10199 /* If not a REG, return zero. */
10200 if (GET_CODE (XEXP (addr1, 0)) != REG)
10204 reg1 = REGNO (XEXP (addr1, 0));
10205 /* The offset must be constant! */
10206 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10208 offset1 = INTVAL (XEXP (addr1, 1));
10211 else if (GET_CODE (addr1) != REG)
10215 reg1 = REGNO (addr1);
10216 /* This was a simple (mem (reg)) expression. Offset is 0. */
10220 /* And now for the second addr. */
10221 if (GET_CODE (addr2) == PLUS)
10223 /* If not a REG, return zero. */
10224 if (GET_CODE (XEXP (addr2, 0)) != REG)
10228 reg2 = REGNO (XEXP (addr2, 0));
10229 /* The offset must be constant. */
10230 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10232 offset2 = INTVAL (XEXP (addr2, 1));
10235 else if (GET_CODE (addr2) != REG)
10239 reg2 = REGNO (addr2);
10240 /* This was a simple (mem (reg)) expression. Offset is 0. */
10244 /* Both of these must have the same base register. */
10248 /* The offset for the second addr must be 8 more than the first addr. */
10249 if (offset2 != offset1 + 8)
10252 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10257 /* Return the register class of a scratch register needed to copy IN into
10258 or out of a register in CLASS in MODE. If it can be done directly,
10259 NO_REGS is returned. */
10262 rs6000_secondary_reload_class (enum reg_class class,
10263 enum machine_mode mode ATTRIBUTE_UNUSED,
10268 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10270 && MACHOPIC_INDIRECT
10274 /* We cannot copy a symbolic operand directly into anything
10275 other than BASE_REGS for TARGET_ELF. So indicate that a
10276 register from BASE_REGS is needed as an intermediate
10279 On Darwin, pic addresses require a load from memory, which
10280 needs a base register. */
10281 if (class != BASE_REGS
10282 && (GET_CODE (in) == SYMBOL_REF
10283 || GET_CODE (in) == HIGH
10284 || GET_CODE (in) == LABEL_REF
10285 || GET_CODE (in) == CONST))
10289 if (GET_CODE (in) == REG)
10291 regno = REGNO (in);
10292 if (regno >= FIRST_PSEUDO_REGISTER)
10294 regno = true_regnum (in);
10295 if (regno >= FIRST_PSEUDO_REGISTER)
10299 else if (GET_CODE (in) == SUBREG)
10301 regno = true_regnum (in);
10302 if (regno >= FIRST_PSEUDO_REGISTER)
10308 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10310 if (class == GENERAL_REGS || class == BASE_REGS
10311 || (regno >= 0 && INT_REGNO_P (regno)))
10314 /* Constants, memory, and FP registers can go into FP registers. */
10315 if ((regno == -1 || FP_REGNO_P (regno))
10316 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10319 /* Memory, and AltiVec registers can go into AltiVec registers. */
10320 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10321 && class == ALTIVEC_REGS)
10324 /* We can copy among the CR registers. */
10325 if ((class == CR_REGS || class == CR0_REGS)
10326 && regno >= 0 && CR_REGNO_P (regno))
10329 /* Otherwise, we need GENERAL_REGS. */
10330 return GENERAL_REGS;
10333 /* Given a comparison operation, return the bit number in CCR to test. We
10334 know this is a valid comparison.
10336 SCC_P is 1 if this is for an scc. That means that %D will have been
10337 used instead of %C, so the bits will be in different places.
10339 Return -1 if OP isn't a valid comparison for some reason. */
10342 ccr_bit (rtx op, int scc_p)
10344 enum rtx_code code = GET_CODE (op);
10345 enum machine_mode cc_mode;
10350 if (!COMPARISON_P (op))
10353 reg = XEXP (op, 0);
10355 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10357 cc_mode = GET_MODE (reg);
10358 cc_regnum = REGNO (reg);
10359 base_bit = 4 * (cc_regnum - CR0_REGNO);
10361 validate_condition_mode (code, cc_mode);
10363 /* When generating a sCOND operation, only positive conditions are
10366 || code == EQ || code == GT || code == LT || code == UNORDERED
10367 || code == GTU || code == LTU);
10372 return scc_p ? base_bit + 3 : base_bit + 2;
10374 return base_bit + 2;
10375 case GT: case GTU: case UNLE:
10376 return base_bit + 1;
10377 case LT: case LTU: case UNGE:
10379 case ORDERED: case UNORDERED:
10380 return base_bit + 3;
10383 /* If scc, we will have done a cror to put the bit in the
10384 unordered position. So test that bit. For integer, this is ! LT
10385 unless this is an scc insn. */
10386 return scc_p ? base_bit + 3 : base_bit;
10389 return scc_p ? base_bit + 3 : base_bit + 1;
10392 gcc_unreachable ();
10396 /* Return the GOT register. */
10399 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10401 /* The second flow pass currently (June 1999) can't update
10402 regs_ever_live without disturbing other parts of the compiler, so
10403 update it here to make the prolog/epilogue code happy. */
10404 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10405 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10407 current_function_uses_pic_offset_table = 1;
10409 return pic_offset_table_rtx;
10412 /* Function to init struct machine_function.
10413 This will be called, via a pointer variable,
10414 from push_function_context. */
10416 static struct machine_function *
10417 rs6000_init_machine_status (void)
10419 return ggc_alloc_cleared (sizeof (machine_function));
10422 /* These macros test for integers and extract the low-order bits. */
10424 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10425 && GET_MODE (X) == VOIDmode)
10427 #define INT_LOWPART(X) \
10428 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10431 extract_MB (rtx op)
10434 unsigned long val = INT_LOWPART (op);
10436 /* If the high bit is zero, the value is the first 1 bit we find
10438 if ((val & 0x80000000) == 0)
10440 gcc_assert (val & 0xffffffff);
10443 while (((val <<= 1) & 0x80000000) == 0)
10448 /* If the high bit is set and the low bit is not, or the mask is all
10449 1's, the value is zero. */
10450 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10453 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10456 while (((val >>= 1) & 1) != 0)
10463 extract_ME (rtx op)
10466 unsigned long val = INT_LOWPART (op);
10468 /* If the low bit is zero, the value is the first 1 bit we find from
10470 if ((val & 1) == 0)
10472 gcc_assert (val & 0xffffffff);
10475 while (((val >>= 1) & 1) == 0)
10481 /* If the low bit is set and the high bit is not, or the mask is all
10482 1's, the value is 31. */
10483 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10486 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10489 while (((val <<= 1) & 0x80000000) != 0)
10495 /* Locate some local-dynamic symbol still in use by this function
10496 so that we can print its name in some tls_ld pattern. */
10498 static const char *
10499 rs6000_get_some_local_dynamic_name (void)
10503 if (cfun->machine->some_ld_name)
10504 return cfun->machine->some_ld_name;
10506 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10508 && for_each_rtx (&PATTERN (insn),
10509 rs6000_get_some_local_dynamic_name_1, 0))
10510 return cfun->machine->some_ld_name;
10512 gcc_unreachable ();
10515 /* Helper function for rs6000_get_some_local_dynamic_name. */
10518 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10522 if (GET_CODE (x) == SYMBOL_REF)
10524 const char *str = XSTR (x, 0);
10525 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10527 cfun->machine->some_ld_name = str;
10535 /* Write out a function code label. */
10538 rs6000_output_function_entry (FILE *file, const char *fname)
10540 if (fname[0] != '.')
10542 switch (DEFAULT_ABI)
10545 gcc_unreachable ();
10551 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10560 RS6000_OUTPUT_BASENAME (file, fname);
10562 assemble_name (file, fname);
10565 /* Print an operand. Recognize special options, documented below. */
10568 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10569 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10571 #define SMALL_DATA_RELOC "sda21"
10572 #define SMALL_DATA_REG 0
10576 print_operand (FILE *file, rtx x, int code)
10580 unsigned HOST_WIDE_INT uval;
10585 /* Write out an instruction after the call which may be replaced
10586 with glue code by the loader. This depends on the AIX version. */
10587 asm_fprintf (file, RS6000_CALL_GLUE);
10590 /* %a is output_address. */
10593 /* If X is a constant integer whose low-order 5 bits are zero,
10594 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10595 in the AIX assembler where "sri" with a zero shift count
10596 writes a trash instruction. */
10597 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10604 /* If constant, low-order 16 bits of constant, unsigned.
10605 Otherwise, write normally. */
10607 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10609 print_operand (file, x, 0);
10613 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10614 for 64-bit mask direction. */
10615 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10618 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10622 /* X is a CR register. Print the number of the GT bit of the CR. */
10623 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10624 output_operand_lossage ("invalid %%E value");
10626 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10630 /* Like 'J' but get to the GT bit only. */
10631 gcc_assert (GET_CODE (x) == REG);
10633 /* Bit 1 is GT bit. */
10634 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10636 /* Add one for shift count in rlinm for scc. */
10637 fprintf (file, "%d", i + 1);
10641 /* X is a CR register. Print the number of the EQ bit of the CR */
10642 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10643 output_operand_lossage ("invalid %%E value");
10645 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10649 /* X is a CR register. Print the shift count needed to move it
10650 to the high-order four bits. */
10651 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10652 output_operand_lossage ("invalid %%f value");
10654 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10658 /* Similar, but print the count for the rotate in the opposite
10660 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10661 output_operand_lossage ("invalid %%F value");
10663 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10667 /* X is a constant integer. If it is negative, print "m",
10668 otherwise print "z". This is to make an aze or ame insn. */
10669 if (GET_CODE (x) != CONST_INT)
10670 output_operand_lossage ("invalid %%G value");
10671 else if (INTVAL (x) >= 0)
10678 /* If constant, output low-order five bits. Otherwise, write
10681 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10683 print_operand (file, x, 0);
10687 /* If constant, output low-order six bits. Otherwise, write
10690 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10692 print_operand (file, x, 0);
10696 /* Print `i' if this is a constant, else nothing. */
10702 /* Write the bit number in CCR for jump. */
10703 i = ccr_bit (x, 0);
10705 output_operand_lossage ("invalid %%j code");
10707 fprintf (file, "%d", i);
10711 /* Similar, but add one for shift count in rlinm for scc and pass
10712 scc flag to `ccr_bit'. */
10713 i = ccr_bit (x, 1);
10715 output_operand_lossage ("invalid %%J code");
10717 /* If we want bit 31, write a shift count of zero, not 32. */
10718 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10722 /* X must be a constant. Write the 1's complement of the
10725 output_operand_lossage ("invalid %%k value");
10727 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10731 /* X must be a symbolic constant on ELF. Write an
10732 expression suitable for an 'addi' that adds in the low 16
10733 bits of the MEM. */
10734 if (GET_CODE (x) != CONST)
10736 print_operand_address (file, x);
10737 fputs ("@l", file);
10741 if (GET_CODE (XEXP (x, 0)) != PLUS
10742 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10743 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10744 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10745 output_operand_lossage ("invalid %%K value");
10746 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10747 fputs ("@l", file);
10748 /* For GNU as, there must be a non-alphanumeric character
10749 between 'l' and the number. The '-' is added by
10750 print_operand() already. */
10751 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10753 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10757 /* %l is output_asm_label. */
10760 /* Write second word of DImode or DFmode reference. Works on register
10761 or non-indexed memory only. */
10762 if (GET_CODE (x) == REG)
10763 fputs (reg_names[REGNO (x) + 1], file);
10764 else if (GET_CODE (x) == MEM)
10766 /* Handle possible auto-increment. Since it is pre-increment and
10767 we have already done it, we can just use an offset of word. */
10768 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10769 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10770 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10773 output_address (XEXP (adjust_address_nv (x, SImode,
10777 if (small_data_operand (x, GET_MODE (x)))
10778 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10779 reg_names[SMALL_DATA_REG]);
10784 /* MB value for a mask operand. */
10785 if (! mask_operand (x, SImode))
10786 output_operand_lossage ("invalid %%m value");
10788 fprintf (file, "%d", extract_MB (x));
10792 /* ME value for a mask operand. */
10793 if (! mask_operand (x, SImode))
10794 output_operand_lossage ("invalid %%M value");
10796 fprintf (file, "%d", extract_ME (x));
10799 /* %n outputs the negative of its operand. */
10802 /* Write the number of elements in the vector times 4. */
10803 if (GET_CODE (x) != PARALLEL)
10804 output_operand_lossage ("invalid %%N value");
10806 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10810 /* Similar, but subtract 1 first. */
10811 if (GET_CODE (x) != PARALLEL)
10812 output_operand_lossage ("invalid %%O value");
10814 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10818 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10820 || INT_LOWPART (x) < 0
10821 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10822 output_operand_lossage ("invalid %%p value");
10824 fprintf (file, "%d", i);
10828 /* The operand must be an indirect memory reference. The result
10829 is the register name. */
10830 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10831 || REGNO (XEXP (x, 0)) >= 32)
10832 output_operand_lossage ("invalid %%P value");
10834 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10838 /* This outputs the logical code corresponding to a boolean
10839 expression. The expression may have one or both operands
10840 negated (if one, only the first one). For condition register
10841 logical operations, it will also treat the negated
10842 CR codes as NOTs, but not handle NOTs of them. */
10844 const char *const *t = 0;
10846 enum rtx_code code = GET_CODE (x);
10847 static const char * const tbl[3][3] = {
10848 { "and", "andc", "nor" },
10849 { "or", "orc", "nand" },
10850 { "xor", "eqv", "xor" } };
10854 else if (code == IOR)
10856 else if (code == XOR)
10859 output_operand_lossage ("invalid %%q value");
10861 if (GET_CODE (XEXP (x, 0)) != NOT)
10865 if (GET_CODE (XEXP (x, 1)) == NOT)
10883 /* X is a CR register. Print the mask for `mtcrf'. */
10884 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10885 output_operand_lossage ("invalid %%R value");
10887 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10891 /* Low 5 bits of 32 - value */
10893 output_operand_lossage ("invalid %%s value");
10895 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10899 /* PowerPC64 mask position. All 0's is excluded.
10900 CONST_INT 32-bit mask is considered sign-extended so any
10901 transition must occur within the CONST_INT, not on the boundary. */
10902 if (! mask64_operand (x, DImode))
10903 output_operand_lossage ("invalid %%S value");
10905 uval = INT_LOWPART (x);
10907 if (uval & 1) /* Clear Left */
10909 #if HOST_BITS_PER_WIDE_INT > 64
10910 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10914 else /* Clear Right */
10917 #if HOST_BITS_PER_WIDE_INT > 64
10918 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10924 gcc_assert (i >= 0);
10925 fprintf (file, "%d", i);
10929 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10930 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10932 /* Bit 3 is OV bit. */
10933 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10935 /* If we want bit 31, write a shift count of zero, not 32. */
10936 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10940 /* Print the symbolic name of a branch target register. */
10941 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10942 && REGNO (x) != COUNT_REGISTER_REGNUM))
10943 output_operand_lossage ("invalid %%T value");
10944 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10945 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10947 fputs ("ctr", file);
10951 /* High-order 16 bits of constant for use in unsigned operand. */
10953 output_operand_lossage ("invalid %%u value");
10955 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10956 (INT_LOWPART (x) >> 16) & 0xffff);
10960 /* High-order 16 bits of constant for use in signed operand. */
10962 output_operand_lossage ("invalid %%v value");
10964 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10965 (INT_LOWPART (x) >> 16) & 0xffff);
10969 /* Print `u' if this has an auto-increment or auto-decrement. */
10970 if (GET_CODE (x) == MEM
10971 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10972 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10977 /* Print the trap code for this operand. */
10978 switch (GET_CODE (x))
10981 fputs ("eq", file); /* 4 */
10984 fputs ("ne", file); /* 24 */
10987 fputs ("lt", file); /* 16 */
10990 fputs ("le", file); /* 20 */
10993 fputs ("gt", file); /* 8 */
10996 fputs ("ge", file); /* 12 */
10999 fputs ("llt", file); /* 2 */
11002 fputs ("lle", file); /* 6 */
11005 fputs ("lgt", file); /* 1 */
11008 fputs ("lge", file); /* 5 */
11011 gcc_unreachable ();
11016 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11019 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11020 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11022 print_operand (file, x, 0);
11026 /* MB value for a PowerPC64 rldic operand. */
11027 val = (GET_CODE (x) == CONST_INT
11028 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11033 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11034 if ((val <<= 1) < 0)
11037 #if HOST_BITS_PER_WIDE_INT == 32
11038 if (GET_CODE (x) == CONST_INT && i >= 0)
11039 i += 32; /* zero-extend high-part was all 0's */
11040 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11042 val = CONST_DOUBLE_LOW (x);
11048 for ( ; i < 64; i++)
11049 if ((val <<= 1) < 0)
11054 fprintf (file, "%d", i + 1);
11058 if (GET_CODE (x) == MEM
11059 && legitimate_indexed_address_p (XEXP (x, 0), 0))
11064 /* Like 'L', for third word of TImode */
11065 if (GET_CODE (x) == REG)
11066 fputs (reg_names[REGNO (x) + 2], file);
11067 else if (GET_CODE (x) == MEM)
11069 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11070 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11071 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11073 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11074 if (small_data_operand (x, GET_MODE (x)))
11075 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11076 reg_names[SMALL_DATA_REG]);
11081 /* X is a SYMBOL_REF. Write out the name preceded by a
11082 period and without any trailing data in brackets. Used for function
11083 names. If we are configured for System V (or the embedded ABI) on
11084 the PowerPC, do not emit the period, since those systems do not use
11085 TOCs and the like. */
11086 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11088 /* Mark the decl as referenced so that cgraph will output the
11090 if (SYMBOL_REF_DECL (x))
11091 mark_decl_referenced (SYMBOL_REF_DECL (x));
11093 /* For macho, check to see if we need a stub. */
11096 const char *name = XSTR (x, 0);
11098 if (MACHOPIC_INDIRECT
11099 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11100 name = machopic_indirection_name (x, /*stub_p=*/true);
11102 assemble_name (file, name);
11104 else if (!DOT_SYMBOLS)
11105 assemble_name (file, XSTR (x, 0));
11107 rs6000_output_function_entry (file, XSTR (x, 0));
11111 /* Like 'L', for last word of TImode. */
11112 if (GET_CODE (x) == REG)
11113 fputs (reg_names[REGNO (x) + 3], file);
11114 else if (GET_CODE (x) == MEM)
11116 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11117 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11118 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11120 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11121 if (small_data_operand (x, GET_MODE (x)))
11122 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11123 reg_names[SMALL_DATA_REG]);
11127 /* Print AltiVec or SPE memory operand. */
11132 gcc_assert (GET_CODE (x) == MEM);
11136 /* Ugly hack because %y is overloaded. */
11137 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11138 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11139 || GET_MODE (x) == TFmode
11140 || GET_MODE (x) == TImode))
11142 /* Handle [reg]. */
11143 if (GET_CODE (tmp) == REG)
11145 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11148 /* Handle [reg+UIMM]. */
11149 else if (GET_CODE (tmp) == PLUS &&
11150 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11154 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11156 x = INTVAL (XEXP (tmp, 1));
11157 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11161 /* Fall through. Must be [reg+reg]. */
11164 && GET_CODE (tmp) == AND
11165 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11166 && INTVAL (XEXP (tmp, 1)) == -16)
11167 tmp = XEXP (tmp, 0);
11168 if (GET_CODE (tmp) == REG)
11169 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11172 gcc_assert (GET_CODE (tmp) == PLUS
11173 && REG_P (XEXP (tmp, 0))
11174 && REG_P (XEXP (tmp, 1)));
11176 if (REGNO (XEXP (tmp, 0)) == 0)
11177 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11178 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11180 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11181 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11187 if (GET_CODE (x) == REG)
11188 fprintf (file, "%s", reg_names[REGNO (x)]);
11189 else if (GET_CODE (x) == MEM)
11191 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11192 know the width from the mode. */
11193 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11194 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11195 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11196 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11197 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11198 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11200 output_address (XEXP (x, 0));
11203 output_addr_const (file, x);
11207 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11211 output_operand_lossage ("invalid %%xn code");
11215 /* Print the address of an operand. */
11218 print_operand_address (FILE *file, rtx x)
11220 if (GET_CODE (x) == REG)
11221 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11222 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11223 || GET_CODE (x) == LABEL_REF)
11225 output_addr_const (file, x);
11226 if (small_data_operand (x, GET_MODE (x)))
11227 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11228 reg_names[SMALL_DATA_REG]);
11230 gcc_assert (!TARGET_TOC);
11232 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11234 gcc_assert (REG_P (XEXP (x, 0)));
11235 if (REGNO (XEXP (x, 0)) == 0)
11236 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11237 reg_names[ REGNO (XEXP (x, 0)) ]);
11239 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11240 reg_names[ REGNO (XEXP (x, 1)) ]);
11242 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11243 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11244 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11246 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11247 && CONSTANT_P (XEXP (x, 1)))
11249 output_addr_const (file, XEXP (x, 1));
11250 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11254 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11255 && CONSTANT_P (XEXP (x, 1)))
11257 fprintf (file, "lo16(");
11258 output_addr_const (file, XEXP (x, 1));
11259 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11262 else if (legitimate_constant_pool_address_p (x))
11264 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11266 rtx contains_minus = XEXP (x, 1);
11270 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11271 turn it into (sym) for output_addr_const. */
11272 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11273 contains_minus = XEXP (contains_minus, 0);
11275 minus = XEXP (contains_minus, 0);
11276 symref = XEXP (minus, 0);
11277 XEXP (contains_minus, 0) = symref;
11282 name = XSTR (symref, 0);
11283 newname = alloca (strlen (name) + sizeof ("@toc"));
11284 strcpy (newname, name);
11285 strcat (newname, "@toc");
11286 XSTR (symref, 0) = newname;
11288 output_addr_const (file, XEXP (x, 1));
11290 XSTR (symref, 0) = name;
11291 XEXP (contains_minus, 0) = minus;
11294 output_addr_const (file, XEXP (x, 1));
11296 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11299 gcc_unreachable ();
11302 /* Target hook for assembling integer objects. The PowerPC version has
11303 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11304 is defined. It also needs to handle DI-mode objects on 64-bit
11308 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11310 #ifdef RELOCATABLE_NEEDS_FIXUP
11311 /* Special handling for SI values. */
11312 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11314 static int recurse = 0;
11316 /* For -mrelocatable, we mark all addresses that need to be fixed up
11317 in the .fixup section. */
11318 if (TARGET_RELOCATABLE
11319 && in_section != toc_section
11320 && in_section != text_section
11321 && !unlikely_text_section_p (in_section)
11323 && GET_CODE (x) != CONST_INT
11324 && GET_CODE (x) != CONST_DOUBLE
11330 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11332 ASM_OUTPUT_LABEL (asm_out_file, buf);
11333 fprintf (asm_out_file, "\t.long\t(");
11334 output_addr_const (asm_out_file, x);
11335 fprintf (asm_out_file, ")@fixup\n");
11336 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11337 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11338 fprintf (asm_out_file, "\t.long\t");
11339 assemble_name (asm_out_file, buf);
11340 fprintf (asm_out_file, "\n\t.previous\n");
11344 /* Remove initial .'s to turn a -mcall-aixdesc function
11345 address into the address of the descriptor, not the function
11347 else if (GET_CODE (x) == SYMBOL_REF
11348 && XSTR (x, 0)[0] == '.'
11349 && DEFAULT_ABI == ABI_AIX)
11351 const char *name = XSTR (x, 0);
11352 while (*name == '.')
11355 fprintf (asm_out_file, "\t.long\t%s\n", name);
11359 #endif /* RELOCATABLE_NEEDS_FIXUP */
11360 return default_assemble_integer (x, size, aligned_p);
11363 #ifdef HAVE_GAS_HIDDEN
11364 /* Emit an assembler directive to set symbol visibility for DECL to
11365 VISIBILITY_TYPE. */
11368 rs6000_assemble_visibility (tree decl, int vis)
11370 /* Functions need to have their entry point symbol visibility set as
11371 well as their descriptor symbol visibility. */
11372 if (DEFAULT_ABI == ABI_AIX
11374 && TREE_CODE (decl) == FUNCTION_DECL)
11376 static const char * const visibility_types[] = {
11377 NULL, "internal", "hidden", "protected"
11380 const char *name, *type;
11382 name = ((* targetm.strip_name_encoding)
11383 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11384 type = visibility_types[vis];
11386 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11387 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11390 default_assemble_visibility (decl, vis);
11395 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11397 /* Reversal of FP compares takes care -- an ordered compare
11398 becomes an unordered compare and vice versa. */
11399 if (mode == CCFPmode
11400 && (!flag_finite_math_only
11401 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11402 || code == UNEQ || code == LTGT))
11403 return reverse_condition_maybe_unordered (code);
11405 return reverse_condition (code);
11408 /* Generate a compare for CODE. Return a brand-new rtx that
11409 represents the result of the compare. */
11412 rs6000_generate_compare (enum rtx_code code)
11414 enum machine_mode comp_mode;
11415 rtx compare_result;
11417 if (rs6000_compare_fp_p)
11418 comp_mode = CCFPmode;
11419 else if (code == GTU || code == LTU
11420 || code == GEU || code == LEU)
11421 comp_mode = CCUNSmode;
11422 else if ((code == EQ || code == NE)
11423 && GET_CODE (rs6000_compare_op0) == SUBREG
11424 && GET_CODE (rs6000_compare_op1) == SUBREG
11425 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11426 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11427 /* These are unsigned values, perhaps there will be a later
11428 ordering compare that can be shared with this one.
11429 Unfortunately we cannot detect the signedness of the operands
11430 for non-subregs. */
11431 comp_mode = CCUNSmode;
11433 comp_mode = CCmode;
11435 /* First, the compare. */
11436 compare_result = gen_reg_rtx (comp_mode);
11438 /* E500 FP compare instructions on the GPRs. Yuck! */
11439 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11440 && rs6000_compare_fp_p)
11442 rtx cmp, or_result, compare_result2;
11443 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11445 if (op_mode == VOIDmode)
11446 op_mode = GET_MODE (rs6000_compare_op1);
11448 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11449 This explains the following mess. */
11453 case EQ: case UNEQ: case NE: case LTGT:
11457 cmp = flag_unsafe_math_optimizations
11458 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11459 rs6000_compare_op1)
11460 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11461 rs6000_compare_op1);
11465 cmp = flag_unsafe_math_optimizations
11466 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11467 rs6000_compare_op1)
11468 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11469 rs6000_compare_op1);
11473 cmp = flag_unsafe_math_optimizations
11474 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11475 rs6000_compare_op1)
11476 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11477 rs6000_compare_op1);
11481 gcc_unreachable ();
11485 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11489 cmp = flag_unsafe_math_optimizations
11490 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11491 rs6000_compare_op1)
11492 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11493 rs6000_compare_op1);
11497 cmp = flag_unsafe_math_optimizations
11498 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11499 rs6000_compare_op1)
11500 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11501 rs6000_compare_op1);
11505 cmp = flag_unsafe_math_optimizations
11506 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11507 rs6000_compare_op1)
11508 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11509 rs6000_compare_op1);
11513 gcc_unreachable ();
11517 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11521 cmp = flag_unsafe_math_optimizations
11522 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11523 rs6000_compare_op1)
11524 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11525 rs6000_compare_op1);
11529 cmp = flag_unsafe_math_optimizations
11530 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11531 rs6000_compare_op1)
11532 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11533 rs6000_compare_op1);
11537 cmp = flag_unsafe_math_optimizations
11538 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11539 rs6000_compare_op1)
11540 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11541 rs6000_compare_op1);
11545 gcc_unreachable ();
11549 gcc_unreachable ();
11552 /* Synthesize LE and GE from LT/GT || EQ. */
11553 if (code == LE || code == GE || code == LEU || code == GEU)
11559 case LE: code = LT; break;
11560 case GE: code = GT; break;
11561 case LEU: code = LT; break;
11562 case GEU: code = GT; break;
11563 default: gcc_unreachable ();
11566 compare_result2 = gen_reg_rtx (CCFPmode);
11572 cmp = flag_unsafe_math_optimizations
11573 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11574 rs6000_compare_op1)
11575 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11576 rs6000_compare_op1);
11580 cmp = flag_unsafe_math_optimizations
11581 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11582 rs6000_compare_op1)
11583 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11584 rs6000_compare_op1);
11588 cmp = flag_unsafe_math_optimizations
11589 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11590 rs6000_compare_op1)
11591 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11592 rs6000_compare_op1);
11596 gcc_unreachable ();
11600 /* OR them together. */
11601 or_result = gen_reg_rtx (CCFPmode);
11602 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11604 compare_result = or_result;
11609 if (code == NE || code == LTGT)
11619 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11620 CLOBBERs to match cmptf_internal2 pattern. */
11621 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11622 && GET_MODE (rs6000_compare_op0) == TFmode
11623 && !TARGET_IEEEQUAD
11624 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11625 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11627 gen_rtx_SET (VOIDmode,
11629 gen_rtx_COMPARE (comp_mode,
11630 rs6000_compare_op0,
11631 rs6000_compare_op1)),
11632 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11633 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11634 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11635 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11636 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11637 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11638 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11639 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11640 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11641 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11643 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11644 comp_mode = CCEQmode;
11645 compare_result = gen_reg_rtx (CCEQmode);
11647 emit_insn (gen_stack_protect_testdi (compare_result,
11648 rs6000_compare_op0, op1));
11650 emit_insn (gen_stack_protect_testsi (compare_result,
11651 rs6000_compare_op0, op1));
11654 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11655 gen_rtx_COMPARE (comp_mode,
11656 rs6000_compare_op0,
11657 rs6000_compare_op1)));
11660 /* Some kinds of FP comparisons need an OR operation;
11661 under flag_finite_math_only we don't bother. */
11662 if (rs6000_compare_fp_p
11663 && !flag_finite_math_only
11664 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11665 && (code == LE || code == GE
11666 || code == UNEQ || code == LTGT
11667 || code == UNGT || code == UNLT))
11669 enum rtx_code or1, or2;
11670 rtx or1_rtx, or2_rtx, compare2_rtx;
11671 rtx or_result = gen_reg_rtx (CCEQmode);
11675 case LE: or1 = LT; or2 = EQ; break;
11676 case GE: or1 = GT; or2 = EQ; break;
11677 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11678 case LTGT: or1 = LT; or2 = GT; break;
11679 case UNGT: or1 = UNORDERED; or2 = GT; break;
11680 case UNLT: or1 = UNORDERED; or2 = LT; break;
11681 default: gcc_unreachable ();
11683 validate_condition_mode (or1, comp_mode);
11684 validate_condition_mode (or2, comp_mode);
11685 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11686 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11687 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11688 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11690 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11692 compare_result = or_result;
11696 validate_condition_mode (code, GET_MODE (compare_result));
11698 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11702 /* Emit the RTL for an sCOND pattern. */
11705 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11708 enum machine_mode op_mode;
11709 enum rtx_code cond_code;
11711 condition_rtx = rs6000_generate_compare (code);
11712 cond_code = GET_CODE (condition_rtx);
11714 if (rs6000_compare_fp_p
11715 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11719 PUT_MODE (condition_rtx, SImode);
11720 t = XEXP (condition_rtx, 0);
11722 gcc_assert (cond_code == NE || cond_code == EQ);
11724 if (cond_code == NE)
11725 emit_insn (gen_e500_flip_gt_bit (t, t));
11727 emit_insn (gen_move_from_CR_gt_bit (result, t));
11731 if (cond_code == NE
11732 || cond_code == GE || cond_code == LE
11733 || cond_code == GEU || cond_code == LEU
11734 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11736 rtx not_result = gen_reg_rtx (CCEQmode);
11737 rtx not_op, rev_cond_rtx;
11738 enum machine_mode cc_mode;
11740 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11742 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11743 SImode, XEXP (condition_rtx, 0), const0_rtx);
11744 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11745 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11746 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11749 op_mode = GET_MODE (rs6000_compare_op0);
11750 if (op_mode == VOIDmode)
11751 op_mode = GET_MODE (rs6000_compare_op1);
11753 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11755 PUT_MODE (condition_rtx, DImode);
11756 convert_move (result, condition_rtx, 0);
11760 PUT_MODE (condition_rtx, SImode);
11761 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11765 /* Emit a branch of kind CODE to location LOC. */
11768 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11770 rtx condition_rtx, loc_ref;
11772 condition_rtx = rs6000_generate_compare (code);
11773 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11774 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11775 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11776 loc_ref, pc_rtx)));
11779 /* Return the string to output a conditional branch to LABEL, which is
11780 the operand number of the label, or -1 if the branch is really a
11781 conditional return.
11783 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11784 condition code register and its mode specifies what kind of
11785 comparison we made.
11787 REVERSED is nonzero if we should reverse the sense of the comparison.
11789 INSN is the insn. */
11792 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11794 static char string[64];
11795 enum rtx_code code = GET_CODE (op);
11796 rtx cc_reg = XEXP (op, 0);
11797 enum machine_mode mode = GET_MODE (cc_reg);
11798 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11799 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11800 int really_reversed = reversed ^ need_longbranch;
11806 validate_condition_mode (code, mode);
11808 /* Work out which way this really branches. We could use
11809 reverse_condition_maybe_unordered here always but this
11810 makes the resulting assembler clearer. */
11811 if (really_reversed)
11813 /* Reversal of FP compares takes care -- an ordered compare
11814 becomes an unordered compare and vice versa. */
11815 if (mode == CCFPmode)
11816 code = reverse_condition_maybe_unordered (code);
11818 code = reverse_condition (code);
11821 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11823 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11828 /* Opposite of GT. */
11837 gcc_unreachable ();
11843 /* Not all of these are actually distinct opcodes, but
11844 we distinguish them for clarity of the resulting assembler. */
11845 case NE: case LTGT:
11846 ccode = "ne"; break;
11847 case EQ: case UNEQ:
11848 ccode = "eq"; break;
11850 ccode = "ge"; break;
11851 case GT: case GTU: case UNGT:
11852 ccode = "gt"; break;
11854 ccode = "le"; break;
11855 case LT: case LTU: case UNLT:
11856 ccode = "lt"; break;
11857 case UNORDERED: ccode = "un"; break;
11858 case ORDERED: ccode = "nu"; break;
11859 case UNGE: ccode = "nl"; break;
11860 case UNLE: ccode = "ng"; break;
11862 gcc_unreachable ();
11865 /* Maybe we have a guess as to how likely the branch is.
11866 The old mnemonics don't have a way to specify this information. */
11868 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11869 if (note != NULL_RTX)
11871 /* PROB is the difference from 50%. */
11872 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11874 /* Only hint for highly probable/improbable branches on newer
11875 cpus as static prediction overrides processor dynamic
11876 prediction. For older cpus we may as well always hint, but
11877 assume not taken for branches that are very close to 50% as a
11878 mispredicted taken branch is more expensive than a
11879 mispredicted not-taken branch. */
11880 if (rs6000_always_hint
11881 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11882 && br_prob_note_reliable_p (note)))
11884 if (abs (prob) > REG_BR_PROB_BASE / 20
11885 && ((prob > 0) ^ need_longbranch))
11893 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11895 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11897 /* We need to escape any '%' characters in the reg_names string.
11898 Assume they'd only be the first character.... */
11899 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11901 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11905 /* If the branch distance was too far, we may have to use an
11906 unconditional branch to go the distance. */
11907 if (need_longbranch)
11908 s += sprintf (s, ",$+8\n\tb %s", label);
11910 s += sprintf (s, ",%s", label);
11916 /* Return the string to flip the GT bit on a CR. */
11918 output_e500_flip_gt_bit (rtx dst, rtx src)
11920 static char string[64];
11923 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11924 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11927 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11928 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11930 sprintf (string, "crnot %d,%d", a, b);
11934 /* Return insn index for the vector compare instruction for given CODE,
11935 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11939 get_vec_cmp_insn (enum rtx_code code,
11940 enum machine_mode dest_mode,
11941 enum machine_mode op_mode)
11943 if (!TARGET_ALTIVEC)
11944 return INSN_NOT_AVAILABLE;
11949 if (dest_mode == V16QImode && op_mode == V16QImode)
11950 return UNSPEC_VCMPEQUB;
11951 if (dest_mode == V8HImode && op_mode == V8HImode)
11952 return UNSPEC_VCMPEQUH;
11953 if (dest_mode == V4SImode && op_mode == V4SImode)
11954 return UNSPEC_VCMPEQUW;
11955 if (dest_mode == V4SImode && op_mode == V4SFmode)
11956 return UNSPEC_VCMPEQFP;
11959 if (dest_mode == V4SImode && op_mode == V4SFmode)
11960 return UNSPEC_VCMPGEFP;
11962 if (dest_mode == V16QImode && op_mode == V16QImode)
11963 return UNSPEC_VCMPGTSB;
11964 if (dest_mode == V8HImode && op_mode == V8HImode)
11965 return UNSPEC_VCMPGTSH;
11966 if (dest_mode == V4SImode && op_mode == V4SImode)
11967 return UNSPEC_VCMPGTSW;
11968 if (dest_mode == V4SImode && op_mode == V4SFmode)
11969 return UNSPEC_VCMPGTFP;
11972 if (dest_mode == V16QImode && op_mode == V16QImode)
11973 return UNSPEC_VCMPGTUB;
11974 if (dest_mode == V8HImode && op_mode == V8HImode)
11975 return UNSPEC_VCMPGTUH;
11976 if (dest_mode == V4SImode && op_mode == V4SImode)
11977 return UNSPEC_VCMPGTUW;
11982 return INSN_NOT_AVAILABLE;
11985 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11986 DMODE is expected destination mode. This is a recursive function. */
11989 rs6000_emit_vector_compare (enum rtx_code rcode,
11991 enum machine_mode dmode)
11995 enum machine_mode dest_mode;
11996 enum machine_mode op_mode = GET_MODE (op1);
11998 gcc_assert (TARGET_ALTIVEC);
11999 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12001 /* Floating point vector compare instructions uses destination V4SImode.
12002 Move destination to appropriate mode later. */
12003 if (dmode == V4SFmode)
12004 dest_mode = V4SImode;
12008 mask = gen_reg_rtx (dest_mode);
12009 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12011 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12013 bool swap_operands = false;
12014 bool try_again = false;
12019 swap_operands = true;
12024 swap_operands = true;
12032 /* Invert condition and try again.
12033 e.g., A != B becomes ~(A==B). */
12035 enum rtx_code rev_code;
12036 enum insn_code nor_code;
12039 rev_code = reverse_condition_maybe_unordered (rcode);
12040 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12043 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12044 gcc_assert (nor_code != CODE_FOR_nothing);
12045 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12047 if (dmode != dest_mode)
12049 rtx temp = gen_reg_rtx (dest_mode);
12050 convert_move (temp, mask, 0);
12060 /* Try GT/GTU/LT/LTU OR EQ */
12063 enum insn_code ior_code;
12064 enum rtx_code new_code;
12085 gcc_unreachable ();
12088 c_rtx = rs6000_emit_vector_compare (new_code,
12089 op0, op1, dest_mode);
12090 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12093 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12094 gcc_assert (ior_code != CODE_FOR_nothing);
12095 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12096 if (dmode != dest_mode)
12098 rtx temp = gen_reg_rtx (dest_mode);
12099 convert_move (temp, mask, 0);
12106 gcc_unreachable ();
12111 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12112 /* You only get two chances. */
12113 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12125 emit_insn (gen_rtx_SET (VOIDmode, mask,
12126 gen_rtx_UNSPEC (dest_mode,
12127 gen_rtvec (2, op0, op1),
12129 if (dmode != dest_mode)
12131 rtx temp = gen_reg_rtx (dest_mode);
12132 convert_move (temp, mask, 0);
12138 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12139 valid insn doesn exist for given mode. */
12142 get_vsel_insn (enum machine_mode mode)
12147 return UNSPEC_VSEL4SI;
12150 return UNSPEC_VSEL4SF;
12153 return UNSPEC_VSEL8HI;
12156 return UNSPEC_VSEL16QI;
12159 return INSN_NOT_AVAILABLE;
12162 return INSN_NOT_AVAILABLE;
12165 /* Emit vector select insn where DEST is destination using
12166 operands OP1, OP2 and MASK. */
12169 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12172 enum machine_mode dest_mode = GET_MODE (dest);
12173 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12175 temp = gen_reg_rtx (dest_mode);
12177 /* For each vector element, select op1 when mask is 1 otherwise
12179 t = gen_rtx_SET (VOIDmode, temp,
12180 gen_rtx_UNSPEC (dest_mode,
12181 gen_rtvec (3, op2, op1, mask),
12184 emit_move_insn (dest, temp);
12188 /* Emit vector conditional expression.
12189 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12190 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12193 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12194 rtx cond, rtx cc_op0, rtx cc_op1)
12196 enum machine_mode dest_mode = GET_MODE (dest);
12197 enum rtx_code rcode = GET_CODE (cond);
12200 if (!TARGET_ALTIVEC)
12203 /* Get the vector mask for the given relational operations. */
12204 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12206 rs6000_emit_vector_select (dest, op1, op2, mask);
12211 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12212 operands of the last comparison is nonzero/true, FALSE_COND if it
12213 is zero/false. Return 0 if the hardware has no such operation. */
12216 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12218 enum rtx_code code = GET_CODE (op);
12219 rtx op0 = rs6000_compare_op0;
12220 rtx op1 = rs6000_compare_op1;
12221 REAL_VALUE_TYPE c1;
12222 enum machine_mode compare_mode = GET_MODE (op0);
12223 enum machine_mode result_mode = GET_MODE (dest);
12225 bool is_against_zero;
12227 /* These modes should always match. */
12228 if (GET_MODE (op1) != compare_mode
12229 /* In the isel case however, we can use a compare immediate, so
12230 op1 may be a small constant. */
12231 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12233 if (GET_MODE (true_cond) != result_mode)
12235 if (GET_MODE (false_cond) != result_mode)
12238 /* First, work out if the hardware can do this at all, or
12239 if it's too slow.... */
12240 if (! rs6000_compare_fp_p)
12243 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12246 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12247 && SCALAR_FLOAT_MODE_P (compare_mode))
12250 is_against_zero = op1 == CONST0_RTX (compare_mode);
12252 /* A floating-point subtract might overflow, underflow, or produce
12253 an inexact result, thus changing the floating-point flags, so it
12254 can't be generated if we care about that. It's safe if one side
12255 of the construct is zero, since then no subtract will be
12257 if (SCALAR_FLOAT_MODE_P (compare_mode)
12258 && flag_trapping_math && ! is_against_zero)
12261 /* Eliminate half of the comparisons by switching operands, this
12262 makes the remaining code simpler. */
12263 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12264 || code == LTGT || code == LT || code == UNLE)
12266 code = reverse_condition_maybe_unordered (code);
12268 true_cond = false_cond;
12272 /* UNEQ and LTGT take four instructions for a comparison with zero,
12273 it'll probably be faster to use a branch here too. */
12274 if (code == UNEQ && HONOR_NANS (compare_mode))
12277 if (GET_CODE (op1) == CONST_DOUBLE)
12278 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12280 /* We're going to try to implement comparisons by performing
12281 a subtract, then comparing against zero. Unfortunately,
12282 Inf - Inf is NaN which is not zero, and so if we don't
12283 know that the operand is finite and the comparison
12284 would treat EQ different to UNORDERED, we can't do it. */
12285 if (HONOR_INFINITIES (compare_mode)
12286 && code != GT && code != UNGE
12287 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12288 /* Constructs of the form (a OP b ? a : b) are safe. */
12289 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12290 || (! rtx_equal_p (op0, true_cond)
12291 && ! rtx_equal_p (op1, true_cond))))
12294 /* At this point we know we can use fsel. */
12296 /* Reduce the comparison to a comparison against zero. */
12297 if (! is_against_zero)
12299 temp = gen_reg_rtx (compare_mode);
12300 emit_insn (gen_rtx_SET (VOIDmode, temp,
12301 gen_rtx_MINUS (compare_mode, op0, op1)));
12303 op1 = CONST0_RTX (compare_mode);
12306 /* If we don't care about NaNs we can reduce some of the comparisons
12307 down to faster ones. */
12308 if (! HONOR_NANS (compare_mode))
12314 true_cond = false_cond;
12327 /* Now, reduce everything down to a GE. */
12334 temp = gen_reg_rtx (compare_mode);
12335 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12340 temp = gen_reg_rtx (compare_mode);
12341 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12346 temp = gen_reg_rtx (compare_mode);
12347 emit_insn (gen_rtx_SET (VOIDmode, temp,
12348 gen_rtx_NEG (compare_mode,
12349 gen_rtx_ABS (compare_mode, op0))));
12354 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12355 temp = gen_reg_rtx (result_mode);
12356 emit_insn (gen_rtx_SET (VOIDmode, temp,
12357 gen_rtx_IF_THEN_ELSE (result_mode,
12358 gen_rtx_GE (VOIDmode,
12360 true_cond, false_cond)));
12361 false_cond = true_cond;
12364 temp = gen_reg_rtx (compare_mode);
12365 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12370 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12371 temp = gen_reg_rtx (result_mode);
12372 emit_insn (gen_rtx_SET (VOIDmode, temp,
12373 gen_rtx_IF_THEN_ELSE (result_mode,
12374 gen_rtx_GE (VOIDmode,
12376 true_cond, false_cond)));
12377 true_cond = false_cond;
12380 temp = gen_reg_rtx (compare_mode);
12381 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12386 gcc_unreachable ();
12389 emit_insn (gen_rtx_SET (VOIDmode, dest,
12390 gen_rtx_IF_THEN_ELSE (result_mode,
12391 gen_rtx_GE (VOIDmode,
12393 true_cond, false_cond)));
12397 /* Same as above, but for ints (isel). */
12400 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12402 rtx condition_rtx, cr;
12404 /* All isel implementations thus far are 32-bits. */
12405 if (GET_MODE (rs6000_compare_op0) != SImode)
12408 /* We still have to do the compare, because isel doesn't do a
12409 compare, it just looks at the CRx bits set by a previous compare
12411 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12412 cr = XEXP (condition_rtx, 0);
12414 if (GET_MODE (cr) == CCmode)
12415 emit_insn (gen_isel_signed (dest, condition_rtx,
12416 true_cond, false_cond, cr));
12418 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12419 true_cond, false_cond, cr));
12425 output_isel (rtx *operands)
12427 enum rtx_code code;
12429 code = GET_CODE (operands[1]);
12430 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12432 PUT_CODE (operands[1], reverse_condition (code));
12433 return "isel %0,%3,%2,%j1";
12436 return "isel %0,%2,%3,%j1";
12440 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12442 enum machine_mode mode = GET_MODE (op0);
12446 if (code == SMAX || code == SMIN)
12451 if (code == SMAX || code == UMAX)
12452 target = emit_conditional_move (dest, c, op0, op1, mode,
12453 op0, op1, mode, 0);
12455 target = emit_conditional_move (dest, c, op0, op1, mode,
12456 op1, op0, mode, 0);
12457 gcc_assert (target);
12458 if (target != dest)
12459 emit_move_insn (dest, target);
12462 /* Emit instructions to perform a load-reserved/store-conditional operation.
12463 The operation performed is an atomic
12464 (set M (CODE:MODE M OP))
12465 If not NULL, BEFORE is atomically set to M before the operation, and
12466 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12467 If SYNC_P then a memory barrier is emitted before the operation.
12468 Either OP or M may be wrapped in a NOT operation. */
12471 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12472 rtx m, rtx op, rtx before_param, rtx after_param,
12475 enum machine_mode used_mode;
12476 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12479 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12480 rtx shift = NULL_RTX;
12483 emit_insn (gen_memory_barrier ());
12485 if (GET_CODE (m) == NOT)
12486 used_m = XEXP (m, 0);
12490 /* If this is smaller than SImode, we'll have to use SImode with
12492 if (mode == QImode || mode == HImode)
12496 if (MEM_ALIGN (used_m) >= 32)
12499 if (BYTES_BIG_ENDIAN)
12500 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12502 shift = GEN_INT (ishift);
12506 rtx addrSI, aligned_addr;
12507 int shift_mask = mode == QImode ? 0x18 : 0x10;
12509 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12510 XEXP (used_m, 0)));
12511 shift = gen_reg_rtx (SImode);
12513 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12514 GEN_INT (shift_mask)));
12515 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12517 aligned_addr = expand_binop (Pmode, and_optab,
12519 GEN_INT (-4), NULL_RTX,
12520 1, OPTAB_LIB_WIDEN);
12521 used_m = change_address (used_m, SImode, aligned_addr);
12522 set_mem_align (used_m, 32);
12523 /* It's safe to keep the old alias set of USED_M, because
12524 the operation is atomic and only affects the original
12526 if (GET_CODE (m) == NOT)
12527 m = gen_rtx_NOT (SImode, used_m);
12532 if (GET_CODE (op) == NOT)
12534 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12535 oldop = gen_rtx_NOT (SImode, oldop);
12538 oldop = lowpart_subreg (SImode, op, mode);
12544 newop = expand_binop (SImode, and_optab,
12545 oldop, GEN_INT (imask), NULL_RTX,
12546 1, OPTAB_LIB_WIDEN);
12547 emit_insn (gen_ashlsi3 (newop, newop, shift));
12551 newop = expand_binop (SImode, ior_optab,
12552 oldop, GEN_INT (~imask), NULL_RTX,
12553 1, OPTAB_LIB_WIDEN);
12554 emit_insn (gen_rotlsi3 (newop, newop, shift));
12562 newop = expand_binop (SImode, and_optab,
12563 oldop, GEN_INT (imask), NULL_RTX,
12564 1, OPTAB_LIB_WIDEN);
12565 emit_insn (gen_ashlsi3 (newop, newop, shift));
12567 mask = gen_reg_rtx (SImode);
12568 emit_move_insn (mask, GEN_INT (imask));
12569 emit_insn (gen_ashlsi3 (mask, mask, shift));
12572 newop = gen_rtx_PLUS (SImode, m, newop);
12574 newop = gen_rtx_MINUS (SImode, m, newop);
12575 newop = gen_rtx_AND (SImode, newop, mask);
12576 newop = gen_rtx_IOR (SImode, newop,
12577 gen_rtx_AND (SImode,
12578 gen_rtx_NOT (SImode, mask),
12584 gcc_unreachable ();
12587 if (GET_CODE (m) == NOT)
12591 mask = gen_reg_rtx (SImode);
12592 emit_move_insn (mask, GEN_INT (imask));
12593 emit_insn (gen_ashlsi3 (mask, mask, shift));
12595 xorm = gen_rtx_XOR (SImode, used_m, mask);
12596 /* Depending on the value of 'op', the XOR or the operation might
12597 be able to be simplified away. */
12598 newop = simplify_gen_binary (code, SImode, xorm, newop);
12601 used_mode = SImode;
12602 before = gen_reg_rtx (used_mode);
12603 after = gen_reg_rtx (used_mode);
12608 before = before_param;
12609 after = after_param;
12611 if (before == NULL_RTX)
12612 before = gen_reg_rtx (used_mode);
12613 if (after == NULL_RTX)
12614 after = gen_reg_rtx (used_mode);
12617 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12618 && used_mode != mode)
12619 the_op = op; /* Computed above. */
12620 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12621 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12623 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12625 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12626 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12627 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12628 gen_rtx_UNSPEC (used_mode,
12629 gen_rtvec (1, the_op),
12631 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12633 if ((code == PLUS || code == MINUS) && used_mode != mode)
12634 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12635 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12637 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12638 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12640 /* Shift and mask the return values properly. */
12641 if (used_mode != mode && before_param)
12643 emit_insn (gen_lshrsi3 (before, before, shift));
12644 convert_move (before_param, before, 1);
12647 if (used_mode != mode && after_param)
12649 emit_insn (gen_lshrsi3 (after, after, shift));
12650 convert_move (after_param, after, 1);
12653 /* The previous sequence will end with a branch that's dependent on
12654 the conditional store, so placing an isync will ensure that no
12655 other instructions (especially, no load or store instructions)
12656 can start before the atomic operation completes. */
12658 emit_insn (gen_isync ());
12661 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12662 COND is true. Mark the jump as unlikely to be taken. */
12665 emit_unlikely_jump (rtx cond, rtx label)
12667 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12670 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12671 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12672 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12675 /* A subroutine of the atomic operation splitters. Emit a load-locked
12676 instruction in MODE. */
12679 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12681 rtx (*fn) (rtx, rtx) = NULL;
12682 if (mode == SImode)
12683 fn = gen_load_locked_si;
12684 else if (mode == DImode)
12685 fn = gen_load_locked_di;
12686 emit_insn (fn (reg, mem));
12689 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12690 instruction in MODE. */
12693 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12695 rtx (*fn) (rtx, rtx, rtx) = NULL;
12696 if (mode == SImode)
12697 fn = gen_store_conditional_si;
12698 else if (mode == DImode)
12699 fn = gen_store_conditional_di;
12701 /* Emit sync before stwcx. to address PPC405 Erratum. */
12702 if (PPC405_ERRATUM77)
12703 emit_insn (gen_memory_barrier ());
12705 emit_insn (fn (res, mem, val));
12708 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12709 to perform. MEM is the memory on which to operate. VAL is the second
12710 operand of the binary operator. BEFORE and AFTER are optional locations to
12711 return the value of MEM either before of after the operation. SCRATCH is
12712 a scratch register. */
12715 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12716 rtx before, rtx after, rtx scratch)
12718 enum machine_mode mode = GET_MODE (mem);
12719 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12721 emit_insn (gen_memory_barrier ());
12723 label = gen_label_rtx ();
12724 emit_label (label);
12725 label = gen_rtx_LABEL_REF (VOIDmode, label);
12727 if (before == NULL_RTX)
12729 emit_load_locked (mode, before, mem);
12732 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12733 else if (code == AND)
12734 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12736 x = gen_rtx_fmt_ee (code, mode, before, val);
12738 if (after != NULL_RTX)
12739 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12740 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12742 emit_store_conditional (mode, cond, mem, scratch);
12744 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12745 emit_unlikely_jump (x, label);
12747 emit_insn (gen_isync ());
12750 /* Expand an atomic compare and swap operation. MEM is the memory on which
12751 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12752 value to be stored. SCRATCH is a scratch GPR. */
12755 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12758 enum machine_mode mode = GET_MODE (mem);
12759 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12761 emit_insn (gen_memory_barrier ());
12763 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12764 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12765 emit_label (XEXP (label1, 0));
12767 emit_load_locked (mode, retval, mem);
12769 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12770 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12772 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12773 emit_unlikely_jump (x, label2);
12775 emit_move_insn (scratch, newval);
12776 emit_store_conditional (mode, cond, mem, scratch);
12778 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12779 emit_unlikely_jump (x, label1);
12781 emit_insn (gen_isync ());
12782 emit_label (XEXP (label2, 0));
12785 /* Expand an atomic test and set operation. MEM is the memory on which
12786 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12789 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12791 enum machine_mode mode = GET_MODE (mem);
12792 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12794 emit_insn (gen_memory_barrier ());
12796 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12797 emit_label (XEXP (label, 0));
12799 emit_load_locked (mode, retval, mem);
12800 emit_move_insn (scratch, val);
12801 emit_store_conditional (mode, cond, mem, scratch);
12803 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12804 emit_unlikely_jump (x, label);
12806 emit_insn (gen_isync ());
12810 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12812 enum machine_mode mode = GET_MODE (mem);
12813 rtx addrSI, align, wdst, shift, mask;
12814 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12815 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12817 /* Shift amount for subword relative to aligned word. */
12818 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12819 shift = gen_reg_rtx (SImode);
12820 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12821 GEN_INT (shift_mask)));
12822 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12824 /* Shift and mask old value into position within word. */
12825 oldval = convert_modes (SImode, mode, oldval, 1);
12826 oldval = expand_binop (SImode, and_optab,
12827 oldval, GEN_INT (imask), NULL_RTX,
12828 1, OPTAB_LIB_WIDEN);
12829 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12831 /* Shift and mask new value into position within word. */
12832 newval = convert_modes (SImode, mode, newval, 1);
12833 newval = expand_binop (SImode, and_optab,
12834 newval, GEN_INT (imask), NULL_RTX,
12835 1, OPTAB_LIB_WIDEN);
12836 emit_insn (gen_ashlsi3 (newval, newval, shift));
12838 /* Mask for insertion. */
12839 mask = gen_reg_rtx (SImode);
12840 emit_move_insn (mask, GEN_INT (imask));
12841 emit_insn (gen_ashlsi3 (mask, mask, shift));
12843 /* Address of aligned word containing subword. */
12844 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12845 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12846 mem = change_address (mem, SImode, align);
12847 set_mem_align (mem, 32);
12848 MEM_VOLATILE_P (mem) = 1;
12850 wdst = gen_reg_rtx (SImode);
12851 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12852 oldval, newval, mem));
12854 emit_move_insn (dst, gen_lowpart (mode, wdst));
12858 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12859 rtx oldval, rtx newval, rtx mem,
12862 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12864 emit_insn (gen_memory_barrier ());
12865 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12866 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12867 emit_label (XEXP (label1, 0));
12869 emit_load_locked (SImode, scratch, mem);
12871 /* Mask subword within loaded value for comparison with oldval.
12872 Use UNSPEC_AND to avoid clobber.*/
12873 emit_insn (gen_rtx_SET (SImode, dest,
12874 gen_rtx_UNSPEC (SImode,
12875 gen_rtvec (2, scratch, mask),
12878 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12879 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12881 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12882 emit_unlikely_jump (x, label2);
12884 /* Clear subword within loaded value for insertion of new value. */
12885 emit_insn (gen_rtx_SET (SImode, scratch,
12886 gen_rtx_AND (SImode,
12887 gen_rtx_NOT (SImode, mask), scratch)));
12888 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12889 emit_store_conditional (SImode, cond, mem, scratch);
12891 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12892 emit_unlikely_jump (x, label1);
12894 emit_insn (gen_isync ());
12895 emit_label (XEXP (label2, 0));
12899 /* Emit instructions to move SRC to DST. Called by splitters for
12900 multi-register moves. It will emit at most one instruction for
12901 each register that is accessed; that is, it won't emit li/lis pairs
12902 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12906 rs6000_split_multireg_move (rtx dst, rtx src)
12908 /* The register number of the first register being moved. */
12910 /* The mode that is to be moved. */
12911 enum machine_mode mode;
12912 /* The mode that the move is being done in, and its size. */
12913 enum machine_mode reg_mode;
12915 /* The number of registers that will be moved. */
12918 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12919 mode = GET_MODE (dst);
12920 nregs = hard_regno_nregs[reg][mode];
12921 if (FP_REGNO_P (reg))
12923 else if (ALTIVEC_REGNO_P (reg))
12924 reg_mode = V16QImode;
12925 else if (TARGET_E500_DOUBLE && mode == TFmode)
12928 reg_mode = word_mode;
12929 reg_mode_size = GET_MODE_SIZE (reg_mode);
12931 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12933 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12935 /* Move register range backwards, if we might have destructive
12938 for (i = nregs - 1; i >= 0; i--)
12939 emit_insn (gen_rtx_SET (VOIDmode,
12940 simplify_gen_subreg (reg_mode, dst, mode,
12941 i * reg_mode_size),
12942 simplify_gen_subreg (reg_mode, src, mode,
12943 i * reg_mode_size)));
12949 bool used_update = false;
12951 if (MEM_P (src) && INT_REGNO_P (reg))
12955 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12956 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12959 breg = XEXP (XEXP (src, 0), 0);
12960 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12961 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12962 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12963 emit_insn (TARGET_32BIT
12964 ? gen_addsi3 (breg, breg, delta_rtx)
12965 : gen_adddi3 (breg, breg, delta_rtx));
12966 src = replace_equiv_address (src, breg);
12968 else if (! rs6000_offsettable_memref_p (src))
12971 basereg = gen_rtx_REG (Pmode, reg);
12972 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12973 src = replace_equiv_address (src, basereg);
12976 breg = XEXP (src, 0);
12977 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12978 breg = XEXP (breg, 0);
12980 /* If the base register we are using to address memory is
12981 also a destination reg, then change that register last. */
12983 && REGNO (breg) >= REGNO (dst)
12984 && REGNO (breg) < REGNO (dst) + nregs)
12985 j = REGNO (breg) - REGNO (dst);
12988 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12992 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12993 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12996 breg = XEXP (XEXP (dst, 0), 0);
12997 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12998 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12999 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13001 /* We have to update the breg before doing the store.
13002 Use store with update, if available. */
13006 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13007 emit_insn (TARGET_32BIT
13008 ? (TARGET_POWERPC64
13009 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13010 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13011 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13012 used_update = true;
13015 emit_insn (TARGET_32BIT
13016 ? gen_addsi3 (breg, breg, delta_rtx)
13017 : gen_adddi3 (breg, breg, delta_rtx));
13018 dst = replace_equiv_address (dst, breg);
13021 gcc_assert (rs6000_offsettable_memref_p (dst));
13024 for (i = 0; i < nregs; i++)
13026 /* Calculate index to next subword. */
13031 /* If compiler already emitted move of first word by
13032 store with update, no need to do anything. */
13033 if (j == 0 && used_update)
13036 emit_insn (gen_rtx_SET (VOIDmode,
13037 simplify_gen_subreg (reg_mode, dst, mode,
13038 j * reg_mode_size),
13039 simplify_gen_subreg (reg_mode, src, mode,
13040 j * reg_mode_size)));
13046 /* This page contains routines that are used to determine what the
13047 function prologue and epilogue code will do and write them out. */
13049 /* Return the first fixed-point register that is required to be
13050 saved. 32 if none. */
13053 first_reg_to_save (void)
13057 /* Find lowest numbered live register. */
13058 for (first_reg = 13; first_reg <= 31; first_reg++)
13059 if (regs_ever_live[first_reg]
13060 && (! call_used_regs[first_reg]
13061 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13062 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13063 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13064 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13069 && current_function_uses_pic_offset_table
13070 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13071 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13077 /* Similar, for FP regs. */
13080 first_fp_reg_to_save (void)
13084 /* Find lowest numbered live register. */
13085 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13086 if (regs_ever_live[first_reg])
13092 /* Similar, for AltiVec regs. */
13095 first_altivec_reg_to_save (void)
13099 /* Stack frame remains as is unless we are in AltiVec ABI. */
13100 if (! TARGET_ALTIVEC_ABI)
13101 return LAST_ALTIVEC_REGNO + 1;
13103 /* On Darwin, the unwind routines are compiled without
13104 TARGET_ALTIVEC, and use save_world to save/restore the
13105 altivec registers when necessary. */
13106 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13107 && ! TARGET_ALTIVEC)
13108 return FIRST_ALTIVEC_REGNO + 20;
13110 /* Find lowest numbered live register. */
13111 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13112 if (regs_ever_live[i])
13118 /* Return a 32-bit mask of the AltiVec registers we need to set in
13119 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13120 the 32-bit word is 0. */
13122 static unsigned int
13123 compute_vrsave_mask (void)
13125 unsigned int i, mask = 0;
13127 /* On Darwin, the unwind routines are compiled without
13128 TARGET_ALTIVEC, and use save_world to save/restore the
13129 call-saved altivec registers when necessary. */
13130 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13131 && ! TARGET_ALTIVEC)
13134 /* First, find out if we use _any_ altivec registers. */
13135 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13136 if (regs_ever_live[i])
13137 mask |= ALTIVEC_REG_BIT (i);
13142 /* Next, remove the argument registers from the set. These must
13143 be in the VRSAVE mask set by the caller, so we don't need to add
13144 them in again. More importantly, the mask we compute here is
13145 used to generate CLOBBERs in the set_vrsave insn, and we do not
13146 wish the argument registers to die. */
13147 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13148 mask &= ~ALTIVEC_REG_BIT (i);
13150 /* Similarly, remove the return value from the set. */
13153 diddle_return_value (is_altivec_return_reg, &yes);
13155 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13161 /* For a very restricted set of circumstances, we can cut down the
13162 size of prologues/epilogues by calling our own save/restore-the-world
13166 compute_save_world_info (rs6000_stack_t *info_ptr)
13168 info_ptr->world_save_p = 1;
13169 info_ptr->world_save_p
13170 = (WORLD_SAVE_P (info_ptr)
13171 && DEFAULT_ABI == ABI_DARWIN
13172 && ! (current_function_calls_setjmp && flag_exceptions)
13173 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13174 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13175 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13176 && info_ptr->cr_save_p);
13178 /* This will not work in conjunction with sibcalls. Make sure there
13179 are none. (This check is expensive, but seldom executed.) */
13180 if (WORLD_SAVE_P (info_ptr))
13183 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13184 if ( GET_CODE (insn) == CALL_INSN
13185 && SIBLING_CALL_P (insn))
13187 info_ptr->world_save_p = 0;
13192 if (WORLD_SAVE_P (info_ptr))
13194 /* Even if we're not touching VRsave, make sure there's room on the
13195 stack for it, if it looks like we're calling SAVE_WORLD, which
13196 will attempt to save it. */
13197 info_ptr->vrsave_size = 4;
13199 /* "Save" the VRsave register too if we're saving the world. */
13200 if (info_ptr->vrsave_mask == 0)
13201 info_ptr->vrsave_mask = compute_vrsave_mask ();
13203 /* Because the Darwin register save/restore routines only handle
13204 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13206 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13207 && (info_ptr->first_altivec_reg_save
13208 >= FIRST_SAVED_ALTIVEC_REGNO));
13215 is_altivec_return_reg (rtx reg, void *xyes)
13217 bool *yes = (bool *) xyes;
13218 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13223 /* Calculate the stack information for the current function. This is
13224 complicated by having two separate calling sequences, the AIX calling
13225 sequence and the V.4 calling sequence.
13227 AIX (and Darwin/Mac OS X) stack frames look like:
13229 SP----> +---------------------------------------+
13230 | back chain to caller | 0 0
13231 +---------------------------------------+
13232 | saved CR | 4 8 (8-11)
13233 +---------------------------------------+
13235 +---------------------------------------+
13236 | reserved for compilers | 12 24
13237 +---------------------------------------+
13238 | reserved for binders | 16 32
13239 +---------------------------------------+
13240 | saved TOC pointer | 20 40
13241 +---------------------------------------+
13242 | Parameter save area (P) | 24 48
13243 +---------------------------------------+
13244 | Alloca space (A) | 24+P etc.
13245 +---------------------------------------+
13246 | Local variable space (L) | 24+P+A
13247 +---------------------------------------+
13248 | Float/int conversion temporary (X) | 24+P+A+L
13249 +---------------------------------------+
13250 | Save area for AltiVec registers (W) | 24+P+A+L+X
13251 +---------------------------------------+
13252 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13253 +---------------------------------------+
13254 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13255 +---------------------------------------+
13256 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13257 +---------------------------------------+
13258 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13259 +---------------------------------------+
13260 old SP->| back chain to caller's caller |
13261 +---------------------------------------+
13263 The required alignment for AIX configurations is two words (i.e., 8
13267 V.4 stack frames look like:
13269 SP----> +---------------------------------------+
13270 | back chain to caller | 0
13271 +---------------------------------------+
13272 | caller's saved LR | 4
13273 +---------------------------------------+
13274 | Parameter save area (P) | 8
13275 +---------------------------------------+
13276 | Alloca space (A) | 8+P
13277 +---------------------------------------+
13278 | Varargs save area (V) | 8+P+A
13279 +---------------------------------------+
13280 | Local variable space (L) | 8+P+A+V
13281 +---------------------------------------+
13282 | Float/int conversion temporary (X) | 8+P+A+V+L
13283 +---------------------------------------+
13284 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13285 +---------------------------------------+
13286 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13287 +---------------------------------------+
13288 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13289 +---------------------------------------+
13290 | SPE: area for 64-bit GP registers |
13291 +---------------------------------------+
13292 | SPE alignment padding |
13293 +---------------------------------------+
13294 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13295 +---------------------------------------+
13296 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13297 +---------------------------------------+
13298 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13299 +---------------------------------------+
13300 old SP->| back chain to caller's caller |
13301 +---------------------------------------+
13303 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13304 given. (But note below and in sysv4.h that we require only 8 and
13305 may round up the size of our stack frame anyways. The historical
13306 reason is early versions of powerpc-linux which didn't properly
13307 align the stack at program startup. A happy side-effect is that
13308 -mno-eabi libraries can be used with -meabi programs.)
13310 The EABI configuration defaults to the V.4 layout. However,
13311 the stack alignment requirements may differ. If -mno-eabi is not
13312 given, the required stack alignment is 8 bytes; if -mno-eabi is
13313 given, the required alignment is 16 bytes. (But see V.4 comment
13316 #ifndef ABI_STACK_BOUNDARY
13317 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13320 static rs6000_stack_t *
13321 rs6000_stack_info (void)
13323 static rs6000_stack_t info;
13324 rs6000_stack_t *info_ptr = &info;
13325 int reg_size = TARGET_32BIT ? 4 : 8;
13328 HOST_WIDE_INT non_fixed_size;
13330 memset (&info, 0, sizeof (info));
13334 /* Cache value so we don't rescan instruction chain over and over. */
13335 if (cfun->machine->insn_chain_scanned_p == 0)
13336 cfun->machine->insn_chain_scanned_p
13337 = spe_func_has_64bit_regs_p () + 1;
13338 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13341 /* Select which calling sequence. */
13342 info_ptr->abi = DEFAULT_ABI;
13344 /* Calculate which registers need to be saved & save area size. */
13345 info_ptr->first_gp_reg_save = first_reg_to_save ();
13346 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13347 even if it currently looks like we won't. */
13348 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13349 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13350 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13351 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13352 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13354 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13356 /* For the SPE, we have an additional upper 32-bits on each GPR.
13357 Ideally we should save the entire 64-bits only when the upper
13358 half is used in SIMD instructions. Since we only record
13359 registers live (not the size they are used in), this proves
13360 difficult because we'd have to traverse the instruction chain at
13361 the right time, taking reload into account. This is a real pain,
13362 so we opt to save the GPRs in 64-bits always if but one register
13363 gets used in 64-bits. Otherwise, all the registers in the frame
13364 get saved in 32-bits.
13366 So... since when we save all GPRs (except the SP) in 64-bits, the
13367 traditional GP save area will be empty. */
13368 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13369 info_ptr->gp_size = 0;
13371 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13372 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13374 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13375 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13376 - info_ptr->first_altivec_reg_save);
13378 /* Does this function call anything? */
13379 info_ptr->calls_p = (! current_function_is_leaf
13380 || cfun->machine->ra_needs_full_frame);
13382 /* Determine if we need to save the link register. */
13383 if ((DEFAULT_ABI == ABI_AIX
13384 && current_function_profile
13385 && !TARGET_PROFILE_KERNEL)
13386 #ifdef TARGET_RELOCATABLE
13387 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13389 || (info_ptr->first_fp_reg_save != 64
13390 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13391 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13392 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13393 || info_ptr->calls_p
13394 || rs6000_ra_ever_killed ())
13396 info_ptr->lr_save_p = 1;
13397 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13400 /* Determine if we need to save the condition code registers. */
13401 if (regs_ever_live[CR2_REGNO]
13402 || regs_ever_live[CR3_REGNO]
13403 || regs_ever_live[CR4_REGNO])
13405 info_ptr->cr_save_p = 1;
13406 if (DEFAULT_ABI == ABI_V4)
13407 info_ptr->cr_size = reg_size;
13410 /* If the current function calls __builtin_eh_return, then we need
13411 to allocate stack space for registers that will hold data for
13412 the exception handler. */
13413 if (current_function_calls_eh_return)
13416 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13419 /* SPE saves EH registers in 64-bits. */
13420 ehrd_size = i * (TARGET_SPE_ABI
13421 && info_ptr->spe_64bit_regs_used != 0
13422 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13427 /* Determine various sizes. */
13428 info_ptr->reg_size = reg_size;
13429 info_ptr->fixed_size = RS6000_SAVE_AREA;
13430 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13431 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13432 TARGET_ALTIVEC ? 16 : 8);
13433 if (FRAME_GROWS_DOWNWARD)
13434 info_ptr->vars_size
13435 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13436 + info_ptr->parm_size,
13437 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13438 - (info_ptr->fixed_size + info_ptr->vars_size
13439 + info_ptr->parm_size);
13441 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13442 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13444 info_ptr->spe_gp_size = 0;
13446 if (TARGET_ALTIVEC_ABI)
13447 info_ptr->vrsave_mask = compute_vrsave_mask ();
13449 info_ptr->vrsave_mask = 0;
13451 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13452 info_ptr->vrsave_size = 4;
13454 info_ptr->vrsave_size = 0;
13456 compute_save_world_info (info_ptr);
13458 /* Calculate the offsets. */
13459 switch (DEFAULT_ABI)
13463 gcc_unreachable ();
13467 info_ptr->fp_save_offset = - info_ptr->fp_size;
13468 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13470 if (TARGET_ALTIVEC_ABI)
13472 info_ptr->vrsave_save_offset
13473 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13475 /* Align stack so vector save area is on a quadword boundary.
13476 The padding goes above the vectors. */
13477 if (info_ptr->altivec_size != 0)
13478 info_ptr->altivec_padding_size
13479 = info_ptr->vrsave_save_offset & 0xF;
13481 info_ptr->altivec_padding_size = 0;
13483 info_ptr->altivec_save_offset
13484 = info_ptr->vrsave_save_offset
13485 - info_ptr->altivec_padding_size
13486 - info_ptr->altivec_size;
13487 gcc_assert (info_ptr->altivec_size == 0
13488 || info_ptr->altivec_save_offset % 16 == 0);
13490 /* Adjust for AltiVec case. */
13491 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13494 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13495 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13496 info_ptr->lr_save_offset = 2*reg_size;
13500 info_ptr->fp_save_offset = - info_ptr->fp_size;
13501 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13502 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13504 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13506 /* Align stack so SPE GPR save area is aligned on a
13507 double-word boundary. */
13508 if (info_ptr->spe_gp_size != 0)
13509 info_ptr->spe_padding_size
13510 = 8 - (-info_ptr->cr_save_offset % 8);
13512 info_ptr->spe_padding_size = 0;
13514 info_ptr->spe_gp_save_offset
13515 = info_ptr->cr_save_offset
13516 - info_ptr->spe_padding_size
13517 - info_ptr->spe_gp_size;
13519 /* Adjust for SPE case. */
13520 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13522 else if (TARGET_ALTIVEC_ABI)
13524 info_ptr->vrsave_save_offset
13525 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13527 /* Align stack so vector save area is on a quadword boundary. */
13528 if (info_ptr->altivec_size != 0)
13529 info_ptr->altivec_padding_size
13530 = 16 - (-info_ptr->vrsave_save_offset % 16);
13532 info_ptr->altivec_padding_size = 0;
13534 info_ptr->altivec_save_offset
13535 = info_ptr->vrsave_save_offset
13536 - info_ptr->altivec_padding_size
13537 - info_ptr->altivec_size;
13539 /* Adjust for AltiVec case. */
13540 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13543 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13544 info_ptr->ehrd_offset -= ehrd_size;
13545 info_ptr->lr_save_offset = reg_size;
13549 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13550 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13551 + info_ptr->gp_size
13552 + info_ptr->altivec_size
13553 + info_ptr->altivec_padding_size
13554 + info_ptr->spe_gp_size
13555 + info_ptr->spe_padding_size
13557 + info_ptr->cr_size
13558 + info_ptr->vrsave_size,
13561 non_fixed_size = (info_ptr->vars_size
13562 + info_ptr->parm_size
13563 + info_ptr->save_size);
13565 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13566 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13568 /* Determine if we need to allocate any stack frame:
13570 For AIX we need to push the stack if a frame pointer is needed
13571 (because the stack might be dynamically adjusted), if we are
13572 debugging, if we make calls, or if the sum of fp_save, gp_save,
13573 and local variables are more than the space needed to save all
13574 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13575 + 18*8 = 288 (GPR13 reserved).
13577 For V.4 we don't have the stack cushion that AIX uses, but assume
13578 that the debugger can handle stackless frames. */
13580 if (info_ptr->calls_p)
13581 info_ptr->push_p = 1;
13583 else if (DEFAULT_ABI == ABI_V4)
13584 info_ptr->push_p = non_fixed_size != 0;
13586 else if (frame_pointer_needed)
13587 info_ptr->push_p = 1;
13589 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13590 info_ptr->push_p = 1;
13593 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13595 /* Zero offsets if we're not saving those registers. */
13596 if (info_ptr->fp_size == 0)
13597 info_ptr->fp_save_offset = 0;
13599 if (info_ptr->gp_size == 0)
13600 info_ptr->gp_save_offset = 0;
13602 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13603 info_ptr->altivec_save_offset = 0;
13605 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13606 info_ptr->vrsave_save_offset = 0;
13608 if (! TARGET_SPE_ABI
13609 || info_ptr->spe_64bit_regs_used == 0
13610 || info_ptr->spe_gp_size == 0)
13611 info_ptr->spe_gp_save_offset = 0;
13613 if (! info_ptr->lr_save_p)
13614 info_ptr->lr_save_offset = 0;
13616 if (! info_ptr->cr_save_p)
13617 info_ptr->cr_save_offset = 0;
13622 /* Return true if the current function uses any GPRs in 64-bit SIMD
13626 spe_func_has_64bit_regs_p (void)
13630 /* Functions that save and restore all the call-saved registers will
13631 need to save/restore the registers in 64-bits. */
13632 if (current_function_calls_eh_return
13633 || current_function_calls_setjmp
13634 || current_function_has_nonlocal_goto)
13637 insns = get_insns ();
13639 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13645 /* FIXME: This should be implemented with attributes...
13647 (set_attr "spe64" "true")....then,
13648 if (get_spe64(insn)) return true;
13650 It's the only reliable way to do the stuff below. */
13652 i = PATTERN (insn);
13653 if (GET_CODE (i) == SET)
13655 enum machine_mode mode = GET_MODE (SET_SRC (i));
13657 if (SPE_VECTOR_MODE (mode))
13659 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13669 debug_stack_info (rs6000_stack_t *info)
13671 const char *abi_string;
13674 info = rs6000_stack_info ();
13676 fprintf (stderr, "\nStack information for function %s:\n",
13677 ((current_function_decl && DECL_NAME (current_function_decl))
13678 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13683 default: abi_string = "Unknown"; break;
13684 case ABI_NONE: abi_string = "NONE"; break;
13685 case ABI_AIX: abi_string = "AIX"; break;
13686 case ABI_DARWIN: abi_string = "Darwin"; break;
13687 case ABI_V4: abi_string = "V.4"; break;
13690 fprintf (stderr, "\tABI = %5s\n", abi_string);
13692 if (TARGET_ALTIVEC_ABI)
13693 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13695 if (TARGET_SPE_ABI)
13696 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13698 if (info->first_gp_reg_save != 32)
13699 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13701 if (info->first_fp_reg_save != 64)
13702 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13704 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13705 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13706 info->first_altivec_reg_save);
13708 if (info->lr_save_p)
13709 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13711 if (info->cr_save_p)
13712 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13714 if (info->vrsave_mask)
13715 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13718 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13721 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13723 if (info->gp_save_offset)
13724 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13726 if (info->fp_save_offset)
13727 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13729 if (info->altivec_save_offset)
13730 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13731 info->altivec_save_offset);
13733 if (info->spe_gp_save_offset)
13734 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13735 info->spe_gp_save_offset);
13737 if (info->vrsave_save_offset)
13738 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13739 info->vrsave_save_offset);
13741 if (info->lr_save_offset)
13742 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13744 if (info->cr_save_offset)
13745 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13747 if (info->varargs_save_offset)
13748 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13750 if (info->total_size)
13751 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13754 if (info->vars_size)
13755 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13758 if (info->parm_size)
13759 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13761 if (info->fixed_size)
13762 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13765 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13767 if (info->spe_gp_size)
13768 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13771 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13773 if (info->altivec_size)
13774 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13776 if (info->vrsave_size)
13777 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13779 if (info->altivec_padding_size)
13780 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13781 info->altivec_padding_size);
13783 if (info->spe_padding_size)
13784 fprintf (stderr, "\tspe_padding_size = %5d\n",
13785 info->spe_padding_size);
13788 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13790 if (info->save_size)
13791 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13793 if (info->reg_size != 4)
13794 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13796 fprintf (stderr, "\n");
13800 rs6000_return_addr (int count, rtx frame)
13802 /* Currently we don't optimize very well between prolog and body
13803 code and for PIC code the code can be actually quite bad, so
13804 don't try to be too clever here. */
13805 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13807 cfun->machine->ra_needs_full_frame = 1;
13814 plus_constant (copy_to_reg
13815 (gen_rtx_MEM (Pmode,
13816 memory_address (Pmode, frame))),
13817 RETURN_ADDRESS_OFFSET)));
13820 cfun->machine->ra_need_lr = 1;
13821 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13824 /* Say whether a function is a candidate for sibcall handling or not.
13825 We do not allow indirect calls to be optimized into sibling calls.
13826 Also, we can't do it if there are any vector parameters; there's
13827 nowhere to put the VRsave code so it works; note that functions with
13828 vector parameters are required to have a prototype, so the argument
13829 type info must be available here. (The tail recursion case can work
13830 with vector parameters, but there's no way to distinguish here.) */
13832 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13837 if (TARGET_ALTIVEC_VRSAVE)
13839 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13840 type; type = TREE_CHAIN (type))
13842 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13846 if (DEFAULT_ABI == ABI_DARWIN
13847 || (*targetm.binds_local_p) (decl))
13849 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13851 if (!lookup_attribute ("longcall", attr_list)
13852 || lookup_attribute ("shortcall", attr_list))
13859 /* NULL if INSN insn is valid within a low-overhead loop.
13860 Otherwise return why doloop cannot be applied.
13861 PowerPC uses the COUNT register for branch on table instructions. */
13863 static const char *
13864 rs6000_invalid_within_doloop (rtx insn)
13867 return "Function call in the loop.";
13870 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13871 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13872 return "Computed branch in the loop.";
13878 rs6000_ra_ever_killed (void)
13884 if (current_function_is_thunk)
13887 /* regs_ever_live has LR marked as used if any sibcalls are present,
13888 but this should not force saving and restoring in the
13889 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13890 clobbers LR, so that is inappropriate. */
13892 /* Also, the prologue can generate a store into LR that
13893 doesn't really count, like this:
13896 bcl to set PIC register
13900 When we're called from the epilogue, we need to avoid counting
13901 this as a store. */
13903 push_topmost_sequence ();
13904 top = get_insns ();
13905 pop_topmost_sequence ();
13906 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13908 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13914 if (!SIBLING_CALL_P (insn))
13917 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13919 else if (set_of (reg, insn) != NULL_RTX
13920 && !prologue_epilogue_contains (insn))
13927 /* Add a REG_MAYBE_DEAD note to the insn. */
13929 rs6000_maybe_dead (rtx insn)
13931 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13936 /* Emit instructions needed to load the TOC register.
13937 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13938 a constant pool; or for SVR4 -fpic. */
13941 rs6000_emit_load_toc_table (int fromprolog)
13944 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13946 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13949 rtx lab, tmp1, tmp2, got, tempLR;
13951 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13952 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13954 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13956 got = rs6000_got_sym ();
13957 tmp1 = tmp2 = dest;
13960 tmp1 = gen_reg_rtx (Pmode);
13961 tmp2 = gen_reg_rtx (Pmode);
13963 tempLR = (fromprolog
13964 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13965 : gen_reg_rtx (Pmode));
13966 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13968 rs6000_maybe_dead (insn);
13969 insn = emit_move_insn (tmp1, tempLR);
13971 rs6000_maybe_dead (insn);
13972 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13974 rs6000_maybe_dead (insn);
13975 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13977 rs6000_maybe_dead (insn);
13979 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13981 rtx tempLR = (fromprolog
13982 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13983 : gen_reg_rtx (Pmode));
13985 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13987 rs6000_maybe_dead (insn);
13988 insn = emit_move_insn (dest, tempLR);
13990 rs6000_maybe_dead (insn);
13992 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13995 rtx tempLR = (fromprolog
13996 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13997 : gen_reg_rtx (Pmode));
13998 rtx temp0 = (fromprolog
13999 ? gen_rtx_REG (Pmode, 0)
14000 : gen_reg_rtx (Pmode));
14006 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14007 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14009 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14010 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14012 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
14014 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
14015 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
14023 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14024 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
14025 emit_move_insn (dest, tempLR);
14026 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14028 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
14030 rs6000_maybe_dead (insn);
14032 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14034 /* This is for AIX code running in non-PIC ELF32. */
14037 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14038 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14040 insn = emit_insn (gen_elf_high (dest, realsym));
14042 rs6000_maybe_dead (insn);
14043 insn = emit_insn (gen_elf_low (dest, dest, realsym));
14045 rs6000_maybe_dead (insn);
14049 gcc_assert (DEFAULT_ABI == ABI_AIX);
14052 insn = emit_insn (gen_load_toc_aix_si (dest));
14054 insn = emit_insn (gen_load_toc_aix_di (dest));
14056 rs6000_maybe_dead (insn);
14060 /* Emit instructions to restore the link register after determining where
14061 its value has been stored. */
14064 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14066 rs6000_stack_t *info = rs6000_stack_info ();
14069 operands[0] = source;
14070 operands[1] = scratch;
14072 if (info->lr_save_p)
14074 rtx frame_rtx = stack_pointer_rtx;
14075 HOST_WIDE_INT sp_offset = 0;
14078 if (frame_pointer_needed
14079 || current_function_calls_alloca
14080 || info->total_size > 32767)
14082 tmp = gen_frame_mem (Pmode, frame_rtx);
14083 emit_move_insn (operands[1], tmp);
14084 frame_rtx = operands[1];
14086 else if (info->push_p)
14087 sp_offset = info->total_size;
14089 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14090 tmp = gen_frame_mem (Pmode, tmp);
14091 emit_move_insn (tmp, operands[0]);
14094 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14097 static GTY(()) int set = -1;
14100 get_TOC_alias_set (void)
14103 set = new_alias_set ();
14107 /* This returns nonzero if the current function uses the TOC. This is
14108 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14109 is generated by the ABI_V4 load_toc_* patterns. */
14116 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14119 rtx pat = PATTERN (insn);
14122 if (GET_CODE (pat) == PARALLEL)
14123 for (i = 0; i < XVECLEN (pat, 0); i++)
14125 rtx sub = XVECEXP (pat, 0, i);
14126 if (GET_CODE (sub) == USE)
14128 sub = XEXP (sub, 0);
14129 if (GET_CODE (sub) == UNSPEC
14130 && XINT (sub, 1) == UNSPEC_TOC)
14140 create_TOC_reference (rtx symbol)
14142 if (no_new_pseudos)
14143 regs_ever_live[TOC_REGISTER] = 1;
14144 return gen_rtx_PLUS (Pmode,
14145 gen_rtx_REG (Pmode, TOC_REGISTER),
14146 gen_rtx_CONST (Pmode,
14147 gen_rtx_MINUS (Pmode, symbol,
14148 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14151 /* If _Unwind_* has been called from within the same module,
14152 toc register is not guaranteed to be saved to 40(1) on function
14153 entry. Save it there in that case. */
14156 rs6000_aix_emit_builtin_unwind_init (void)
14159 rtx stack_top = gen_reg_rtx (Pmode);
14160 rtx opcode_addr = gen_reg_rtx (Pmode);
14161 rtx opcode = gen_reg_rtx (SImode);
14162 rtx tocompare = gen_reg_rtx (SImode);
14163 rtx no_toc_save_needed = gen_label_rtx ();
14165 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14166 emit_move_insn (stack_top, mem);
14168 mem = gen_frame_mem (Pmode,
14169 gen_rtx_PLUS (Pmode, stack_top,
14170 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14171 emit_move_insn (opcode_addr, mem);
14172 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14173 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14174 : 0xE8410028, SImode));
14176 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14177 SImode, NULL_RTX, NULL_RTX,
14178 no_toc_save_needed);
14180 mem = gen_frame_mem (Pmode,
14181 gen_rtx_PLUS (Pmode, stack_top,
14182 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14183 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14184 emit_label (no_toc_save_needed);
14187 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14188 and the change to the stack pointer. */
14191 rs6000_emit_stack_tie (void)
14193 rtx mem = gen_frame_mem (BLKmode,
14194 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14196 emit_insn (gen_stack_tie (mem));
14199 /* Emit the correct code for allocating stack space, as insns.
14200 If COPY_R12, make sure a copy of the old frame is left in r12.
14201 The generated code may use hard register 0 as a temporary. */
14204 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14207 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14208 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14209 rtx todec = gen_int_mode (-size, Pmode);
14211 if (INTVAL (todec) != -size)
14213 warning (0, "stack frame too large");
14214 emit_insn (gen_trap ());
14218 if (current_function_limit_stack)
14220 if (REG_P (stack_limit_rtx)
14221 && REGNO (stack_limit_rtx) > 1
14222 && REGNO (stack_limit_rtx) <= 31)
14224 emit_insn (TARGET_32BIT
14225 ? gen_addsi3 (tmp_reg,
14228 : gen_adddi3 (tmp_reg,
14232 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14235 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14237 && DEFAULT_ABI == ABI_V4)
14239 rtx toload = gen_rtx_CONST (VOIDmode,
14240 gen_rtx_PLUS (Pmode,
14244 emit_insn (gen_elf_high (tmp_reg, toload));
14245 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14246 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14250 warning (0, "stack limit expression is not supported");
14253 if (copy_r12 || ! TARGET_UPDATE)
14254 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14260 /* Need a note here so that try_split doesn't get confused. */
14261 if (get_last_insn () == NULL_RTX)
14262 emit_note (NOTE_INSN_DELETED);
14263 insn = emit_move_insn (tmp_reg, todec);
14264 try_split (PATTERN (insn), insn, 0);
14268 insn = emit_insn (TARGET_32BIT
14269 ? gen_movsi_update (stack_reg, stack_reg,
14271 : gen_movdi_di_update (stack_reg, stack_reg,
14272 todec, stack_reg));
14276 insn = emit_insn (TARGET_32BIT
14277 ? gen_addsi3 (stack_reg, stack_reg, todec)
14278 : gen_adddi3 (stack_reg, stack_reg, todec));
14279 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14280 gen_rtx_REG (Pmode, 12));
14283 RTX_FRAME_RELATED_P (insn) = 1;
14285 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14286 gen_rtx_SET (VOIDmode, stack_reg,
14287 gen_rtx_PLUS (Pmode, stack_reg,
14292 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14293 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14294 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14295 deduce these equivalences by itself so it wasn't necessary to hold
14296 its hand so much. */
14299 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14300 rtx reg2, rtx rreg)
14304 /* copy_rtx will not make unique copies of registers, so we need to
14305 ensure we don't have unwanted sharing here. */
14307 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14310 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14312 real = copy_rtx (PATTERN (insn));
14314 if (reg2 != NULL_RTX)
14315 real = replace_rtx (real, reg2, rreg);
14317 real = replace_rtx (real, reg,
14318 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14319 STACK_POINTER_REGNUM),
14322 /* We expect that 'real' is either a SET or a PARALLEL containing
14323 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14324 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14326 if (GET_CODE (real) == SET)
14330 temp = simplify_rtx (SET_SRC (set));
14332 SET_SRC (set) = temp;
14333 temp = simplify_rtx (SET_DEST (set));
14335 SET_DEST (set) = temp;
14336 if (GET_CODE (SET_DEST (set)) == MEM)
14338 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14340 XEXP (SET_DEST (set), 0) = temp;
14347 gcc_assert (GET_CODE (real) == PARALLEL);
14348 for (i = 0; i < XVECLEN (real, 0); i++)
14349 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14351 rtx set = XVECEXP (real, 0, i);
14353 temp = simplify_rtx (SET_SRC (set));
14355 SET_SRC (set) = temp;
14356 temp = simplify_rtx (SET_DEST (set));
14358 SET_DEST (set) = temp;
14359 if (GET_CODE (SET_DEST (set)) == MEM)
14361 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14363 XEXP (SET_DEST (set), 0) = temp;
14365 RTX_FRAME_RELATED_P (set) = 1;
14370 real = spe_synthesize_frame_save (real);
14372 RTX_FRAME_RELATED_P (insn) = 1;
14373 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14378 /* Given an SPE frame note, return a PARALLEL of SETs with the
14379 original note, plus a synthetic register save. */
14382 spe_synthesize_frame_save (rtx real)
14384 rtx synth, offset, reg, real2;
14386 if (GET_CODE (real) != SET
14387 || GET_MODE (SET_SRC (real)) != V2SImode)
14390 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14391 frame related note. The parallel contains a set of the register
14392 being saved, and another set to a synthetic register (n+1200).
14393 This is so we can differentiate between 64-bit and 32-bit saves.
14394 Words cannot describe this nastiness. */
14396 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14397 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14398 && GET_CODE (SET_SRC (real)) == REG);
14401 (set (mem (plus (reg x) (const y)))
14404 (set (mem (plus (reg x) (const y+4)))
14408 real2 = copy_rtx (real);
14409 PUT_MODE (SET_DEST (real2), SImode);
14410 reg = SET_SRC (real2);
14411 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14412 synth = copy_rtx (real2);
14414 if (BYTES_BIG_ENDIAN)
14416 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14417 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14420 reg = SET_SRC (synth);
14422 synth = replace_rtx (synth, reg,
14423 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14425 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14426 synth = replace_rtx (synth, offset,
14427 GEN_INT (INTVAL (offset)
14428 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14430 RTX_FRAME_RELATED_P (synth) = 1;
14431 RTX_FRAME_RELATED_P (real2) = 1;
14432 if (BYTES_BIG_ENDIAN)
14433 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14435 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14440 /* Returns an insn that has a vrsave set operation with the
14441 appropriate CLOBBERs. */
14444 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14447 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14448 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14451 = gen_rtx_SET (VOIDmode,
14453 gen_rtx_UNSPEC_VOLATILE (SImode,
14454 gen_rtvec (2, reg, vrsave),
14455 UNSPECV_SET_VRSAVE));
14459 /* We need to clobber the registers in the mask so the scheduler
14460 does not move sets to VRSAVE before sets of AltiVec registers.
14462 However, if the function receives nonlocal gotos, reload will set
14463 all call saved registers live. We will end up with:
14465 (set (reg 999) (mem))
14466 (parallel [ (set (reg vrsave) (unspec blah))
14467 (clobber (reg 999))])
14469 The clobber will cause the store into reg 999 to be dead, and
14470 flow will attempt to delete an epilogue insn. In this case, we
14471 need an unspec use/set of the register. */
14473 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14474 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14476 if (!epiloguep || call_used_regs [i])
14477 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14478 gen_rtx_REG (V4SImode, i));
14481 rtx reg = gen_rtx_REG (V4SImode, i);
14484 = gen_rtx_SET (VOIDmode,
14486 gen_rtx_UNSPEC (V4SImode,
14487 gen_rtvec (1, reg), 27));
14491 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14493 for (i = 0; i < nclobs; ++i)
14494 XVECEXP (insn, 0, i) = clobs[i];
14499 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14500 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14503 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14504 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14506 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14507 rtx replacea, replaceb;
14509 int_rtx = GEN_INT (offset);
14511 /* Some cases that need register indexed addressing. */
14512 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14513 || (TARGET_E500_DOUBLE && mode == DFmode)
14515 && SPE_VECTOR_MODE (mode)
14516 && !SPE_CONST_OFFSET_OK (offset)))
14518 /* Whomever calls us must make sure r11 is available in the
14519 flow path of instructions in the prologue. */
14520 offset_rtx = gen_rtx_REG (Pmode, 11);
14521 emit_move_insn (offset_rtx, int_rtx);
14523 replacea = offset_rtx;
14524 replaceb = int_rtx;
14528 offset_rtx = int_rtx;
14529 replacea = NULL_RTX;
14530 replaceb = NULL_RTX;
14533 reg = gen_rtx_REG (mode, regno);
14534 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14535 mem = gen_frame_mem (mode, addr);
14537 insn = emit_move_insn (mem, reg);
14539 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14542 /* Emit an offset memory reference suitable for a frame store, while
14543 converting to a valid addressing mode. */
14546 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14548 rtx int_rtx, offset_rtx;
14550 int_rtx = GEN_INT (offset);
14552 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14553 || (TARGET_E500_DOUBLE && mode == DFmode))
14555 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14556 emit_move_insn (offset_rtx, int_rtx);
14559 offset_rtx = int_rtx;
14561 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14564 /* Look for user-defined global regs. We should not save and restore these,
14565 and cannot use stmw/lmw if there are any in its range. */
14568 no_global_regs_above (int first_greg)
14571 for (i = 0; i < 32 - first_greg; i++)
14572 if (global_regs[first_greg + i])
14577 #ifndef TARGET_FIX_AND_CONTINUE
14578 #define TARGET_FIX_AND_CONTINUE 0
14581 /* Emit function prologue as insns. */
14584 rs6000_emit_prologue (void)
14586 rs6000_stack_t *info = rs6000_stack_info ();
14587 enum machine_mode reg_mode = Pmode;
14588 int reg_size = TARGET_32BIT ? 4 : 8;
14589 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14590 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14591 rtx frame_reg_rtx = sp_reg_rtx;
14592 rtx cr_save_rtx = NULL_RTX;
14594 int saving_FPRs_inline;
14595 int using_store_multiple;
14596 HOST_WIDE_INT sp_offset = 0;
14598 if (TARGET_FIX_AND_CONTINUE)
14600 /* gdb on darwin arranges to forward a function from the old
14601 address by modifying the first 5 instructions of the function
14602 to branch to the overriding function. This is necessary to
14603 permit function pointers that point to the old function to
14604 actually forward to the new function. */
14605 emit_insn (gen_nop ());
14606 emit_insn (gen_nop ());
14607 emit_insn (gen_nop ());
14608 emit_insn (gen_nop ());
14609 emit_insn (gen_nop ());
14612 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14614 reg_mode = V2SImode;
14618 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14619 && (!TARGET_SPE_ABI
14620 || info->spe_64bit_regs_used == 0)
14621 && info->first_gp_reg_save < 31
14622 && no_global_regs_above (info->first_gp_reg_save));
14623 saving_FPRs_inline = (info->first_fp_reg_save == 64
14624 || FP_SAVE_INLINE (info->first_fp_reg_save)
14625 || current_function_calls_eh_return
14626 || cfun->machine->ra_need_lr);
14628 /* For V.4, update stack before we do any saving and set back pointer. */
14629 if (! WORLD_SAVE_P (info)
14631 && (DEFAULT_ABI == ABI_V4
14632 || current_function_calls_eh_return))
14634 if (info->total_size < 32767)
14635 sp_offset = info->total_size;
14637 frame_reg_rtx = frame_ptr_rtx;
14638 rs6000_emit_allocate_stack (info->total_size,
14639 (frame_reg_rtx != sp_reg_rtx
14640 && (info->cr_save_p
14642 || info->first_fp_reg_save < 64
14643 || info->first_gp_reg_save < 32
14645 if (frame_reg_rtx != sp_reg_rtx)
14646 rs6000_emit_stack_tie ();
14649 /* Handle world saves specially here. */
14650 if (WORLD_SAVE_P (info))
14657 /* save_world expects lr in r0. */
14658 reg0 = gen_rtx_REG (Pmode, 0);
14659 if (info->lr_save_p)
14661 insn = emit_move_insn (reg0,
14662 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14663 RTX_FRAME_RELATED_P (insn) = 1;
14666 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14667 assumptions about the offsets of various bits of the stack
14669 gcc_assert (info->gp_save_offset == -220
14670 && info->fp_save_offset == -144
14671 && info->lr_save_offset == 8
14672 && info->cr_save_offset == 4
14675 && (!current_function_calls_eh_return
14676 || info->ehrd_offset == -432)
14677 && info->vrsave_save_offset == -224
14678 && info->altivec_save_offset == -416);
14680 treg = gen_rtx_REG (SImode, 11);
14681 emit_move_insn (treg, GEN_INT (-info->total_size));
14683 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14684 in R11. It also clobbers R12, so beware! */
14686 /* Preserve CR2 for save_world prologues */
14688 sz += 32 - info->first_gp_reg_save;
14689 sz += 64 - info->first_fp_reg_save;
14690 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14691 p = rtvec_alloc (sz);
14693 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14694 gen_rtx_REG (Pmode,
14695 LINK_REGISTER_REGNUM));
14696 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14697 gen_rtx_SYMBOL_REF (Pmode,
14699 /* We do floats first so that the instruction pattern matches
14701 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14703 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14704 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14705 GEN_INT (info->fp_save_offset
14706 + sp_offset + 8 * i));
14707 rtx mem = gen_frame_mem (DFmode, addr);
14709 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14711 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14713 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14714 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14715 GEN_INT (info->altivec_save_offset
14716 + sp_offset + 16 * i));
14717 rtx mem = gen_frame_mem (V4SImode, addr);
14719 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14721 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14723 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14724 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14725 GEN_INT (info->gp_save_offset
14726 + sp_offset + reg_size * i));
14727 rtx mem = gen_frame_mem (reg_mode, addr);
14729 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14733 /* CR register traditionally saved as CR2. */
14734 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14735 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14736 GEN_INT (info->cr_save_offset
14738 rtx mem = gen_frame_mem (reg_mode, addr);
14740 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14742 /* Explain about use of R0. */
14743 if (info->lr_save_p)
14745 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14746 GEN_INT (info->lr_save_offset
14748 rtx mem = gen_frame_mem (reg_mode, addr);
14750 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14752 /* Explain what happens to the stack pointer. */
14754 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14755 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14758 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14759 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14760 treg, GEN_INT (-info->total_size));
14761 sp_offset = info->total_size;
14764 /* Save AltiVec registers if needed. */
14765 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14769 /* There should be a non inline version of this, for when we
14770 are saving lots of vector registers. */
14771 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14772 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14774 rtx areg, savereg, mem;
14777 offset = info->altivec_save_offset + sp_offset
14778 + 16 * (i - info->first_altivec_reg_save);
14780 savereg = gen_rtx_REG (V4SImode, i);
14782 areg = gen_rtx_REG (Pmode, 0);
14783 emit_move_insn (areg, GEN_INT (offset));
14785 /* AltiVec addressing mode is [reg+reg]. */
14786 mem = gen_frame_mem (V4SImode,
14787 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14789 insn = emit_move_insn (mem, savereg);
14791 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14792 areg, GEN_INT (offset));
14796 /* VRSAVE is a bit vector representing which AltiVec registers
14797 are used. The OS uses this to determine which vector
14798 registers to save on a context switch. We need to save
14799 VRSAVE on the stack frame, add whatever AltiVec registers we
14800 used in this function, and do the corresponding magic in the
14803 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14804 && info->vrsave_mask != 0)
14806 rtx reg, mem, vrsave;
14809 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14810 as frame_reg_rtx and r11 as the static chain pointer for
14811 nested functions. */
14812 reg = gen_rtx_REG (SImode, 0);
14813 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14815 emit_insn (gen_get_vrsave_internal (reg));
14817 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14819 if (!WORLD_SAVE_P (info))
14822 offset = info->vrsave_save_offset + sp_offset;
14823 mem = gen_frame_mem (SImode,
14824 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14825 GEN_INT (offset)));
14826 insn = emit_move_insn (mem, reg);
14829 /* Include the registers in the mask. */
14830 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14832 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14835 /* If we use the link register, get it into r0. */
14836 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14838 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14839 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14840 RTX_FRAME_RELATED_P (insn) = 1;
14843 /* If we need to save CR, put it into r12. */
14844 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14848 cr_save_rtx = gen_rtx_REG (SImode, 12);
14849 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14850 RTX_FRAME_RELATED_P (insn) = 1;
14851 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14852 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14853 But that's OK. All we have to do is specify that _one_ condition
14854 code register is saved in this stack slot. The thrower's epilogue
14855 will then restore all the call-saved registers.
14856 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14857 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14858 gen_rtx_REG (SImode, CR2_REGNO));
14859 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14864 /* Do any required saving of fpr's. If only one or two to save, do
14865 it ourselves. Otherwise, call function. */
14866 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14869 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14870 if ((regs_ever_live[info->first_fp_reg_save+i]
14871 && ! call_used_regs[info->first_fp_reg_save+i]))
14872 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14873 info->first_fp_reg_save + i,
14874 info->fp_save_offset + sp_offset + 8 * i,
14877 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14881 const char *alloc_rname;
14883 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14885 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14886 gen_rtx_REG (Pmode,
14887 LINK_REGISTER_REGNUM));
14888 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14889 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14890 alloc_rname = ggc_strdup (rname);
14891 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14892 gen_rtx_SYMBOL_REF (Pmode,
14894 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14896 rtx addr, reg, mem;
14897 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14898 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14899 GEN_INT (info->fp_save_offset
14900 + sp_offset + 8*i));
14901 mem = gen_frame_mem (DFmode, addr);
14903 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14905 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14906 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14907 NULL_RTX, NULL_RTX);
14910 /* Save GPRs. This is done as a PARALLEL if we are using
14911 the store-multiple instructions. */
14912 if (!WORLD_SAVE_P (info) && using_store_multiple)
14916 p = rtvec_alloc (32 - info->first_gp_reg_save);
14917 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14919 rtx addr, reg, mem;
14920 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14921 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14922 GEN_INT (info->gp_save_offset
14925 mem = gen_frame_mem (reg_mode, addr);
14927 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14929 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14930 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14931 NULL_RTX, NULL_RTX);
14933 else if (!WORLD_SAVE_P (info))
14936 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14937 if ((regs_ever_live[info->first_gp_reg_save + i]
14938 && (!call_used_regs[info->first_gp_reg_save + i]
14939 || (i + info->first_gp_reg_save
14940 == RS6000_PIC_OFFSET_TABLE_REGNUM
14941 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14942 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14943 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14944 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14946 rtx addr, reg, mem;
14947 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14949 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14951 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14954 if (!SPE_CONST_OFFSET_OK (offset))
14956 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14957 emit_move_insn (b, GEN_INT (offset));
14960 b = GEN_INT (offset);
14962 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14963 mem = gen_frame_mem (V2SImode, addr);
14964 insn = emit_move_insn (mem, reg);
14966 if (GET_CODE (b) == CONST_INT)
14967 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14968 NULL_RTX, NULL_RTX);
14970 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14971 b, GEN_INT (offset));
14975 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14976 GEN_INT (info->gp_save_offset
14979 mem = gen_frame_mem (reg_mode, addr);
14981 insn = emit_move_insn (mem, reg);
14982 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14983 NULL_RTX, NULL_RTX);
14988 /* ??? There's no need to emit actual instructions here, but it's the
14989 easiest way to get the frame unwind information emitted. */
14990 if (current_function_calls_eh_return)
14992 unsigned int i, regno;
14994 /* In AIX ABI we need to pretend we save r2 here. */
14997 rtx addr, reg, mem;
14999 reg = gen_rtx_REG (reg_mode, 2);
15000 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15001 GEN_INT (sp_offset + 5 * reg_size));
15002 mem = gen_frame_mem (reg_mode, addr);
15004 insn = emit_move_insn (mem, reg);
15005 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15006 NULL_RTX, NULL_RTX);
15007 PATTERN (insn) = gen_blockage ();
15012 regno = EH_RETURN_DATA_REGNO (i);
15013 if (regno == INVALID_REGNUM)
15016 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15017 info->ehrd_offset + sp_offset
15018 + reg_size * (int) i,
15023 /* Save lr if we used it. */
15024 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15026 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15027 GEN_INT (info->lr_save_offset + sp_offset));
15028 rtx reg = gen_rtx_REG (Pmode, 0);
15029 rtx mem = gen_rtx_MEM (Pmode, addr);
15030 /* This should not be of frame_alias_set, because of
15031 __builtin_return_address. */
15033 insn = emit_move_insn (mem, reg);
15034 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15035 NULL_RTX, NULL_RTX);
15038 /* Save CR if we use any that must be preserved. */
15039 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15041 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15042 GEN_INT (info->cr_save_offset + sp_offset));
15043 rtx mem = gen_frame_mem (SImode, addr);
15044 /* See the large comment above about why CR2_REGNO is used. */
15045 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15047 /* If r12 was used to hold the original sp, copy cr into r0 now
15049 if (REGNO (frame_reg_rtx) == 12)
15053 cr_save_rtx = gen_rtx_REG (SImode, 0);
15054 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15055 RTX_FRAME_RELATED_P (insn) = 1;
15056 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15057 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15062 insn = emit_move_insn (mem, cr_save_rtx);
15064 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15065 NULL_RTX, NULL_RTX);
15068 /* Update stack and set back pointer unless this is V.4,
15069 for which it was done previously. */
15070 if (!WORLD_SAVE_P (info) && info->push_p
15071 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15072 rs6000_emit_allocate_stack (info->total_size, FALSE);
15074 /* Set frame pointer, if needed. */
15075 if (frame_pointer_needed)
15077 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15079 RTX_FRAME_RELATED_P (insn) = 1;
15082 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15083 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15084 || (DEFAULT_ABI == ABI_V4
15085 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15086 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
15088 /* If emit_load_toc_table will use the link register, we need to save
15089 it. We use R12 for this purpose because emit_load_toc_table
15090 can use register 0. This allows us to use a plain 'blr' to return
15091 from the procedure more often. */
15092 int save_LR_around_toc_setup = (TARGET_ELF
15093 && DEFAULT_ABI != ABI_AIX
15095 && ! info->lr_save_p
15096 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15097 if (save_LR_around_toc_setup)
15099 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15101 insn = emit_move_insn (frame_ptr_rtx, lr);
15102 rs6000_maybe_dead (insn);
15103 RTX_FRAME_RELATED_P (insn) = 1;
15105 rs6000_emit_load_toc_table (TRUE);
15107 insn = emit_move_insn (lr, frame_ptr_rtx);
15108 rs6000_maybe_dead (insn);
15109 RTX_FRAME_RELATED_P (insn) = 1;
15112 rs6000_emit_load_toc_table (TRUE);
15116 if (DEFAULT_ABI == ABI_DARWIN
15117 && flag_pic && current_function_uses_pic_offset_table)
15119 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15120 rtx src = machopic_function_base_sym ();
15122 /* Save and restore LR locally around this call (in R0). */
15123 if (!info->lr_save_p)
15124 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
15126 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
15128 insn = emit_move_insn (gen_rtx_REG (Pmode,
15129 RS6000_PIC_OFFSET_TABLE_REGNUM),
15131 rs6000_maybe_dead (insn);
15133 if (!info->lr_save_p)
15134 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
15139 /* Write function prologue. */
15142 rs6000_output_function_prologue (FILE *file,
15143 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15145 rs6000_stack_t *info = rs6000_stack_info ();
15147 if (TARGET_DEBUG_STACK)
15148 debug_stack_info (info);
15150 /* Write .extern for any function we will call to save and restore
15152 if (info->first_fp_reg_save < 64
15153 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15154 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15155 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15156 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15157 RESTORE_FP_SUFFIX);
15159 /* Write .extern for AIX common mode routines, if needed. */
15160 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15162 fputs ("\t.extern __mulh\n", file);
15163 fputs ("\t.extern __mull\n", file);
15164 fputs ("\t.extern __divss\n", file);
15165 fputs ("\t.extern __divus\n", file);
15166 fputs ("\t.extern __quoss\n", file);
15167 fputs ("\t.extern __quous\n", file);
15168 common_mode_defined = 1;
15171 if (! HAVE_prologue)
15175 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15176 the "toplevel" insn chain. */
15177 emit_note (NOTE_INSN_DELETED);
15178 rs6000_emit_prologue ();
15179 emit_note (NOTE_INSN_DELETED);
15181 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15185 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15187 INSN_ADDRESSES_NEW (insn, addr);
15192 if (TARGET_DEBUG_STACK)
15193 debug_rtx_list (get_insns (), 100);
15194 final (get_insns (), file, FALSE);
15198 rs6000_pic_labelno++;
15201 /* Emit function epilogue as insns.
15203 At present, dwarf2out_frame_debug_expr doesn't understand
15204 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15205 anywhere in the epilogue. Most of the insns below would in any case
15206 need special notes to explain where r11 is in relation to the stack. */
15209 rs6000_emit_epilogue (int sibcall)
15211 rs6000_stack_t *info;
15212 int restoring_FPRs_inline;
15213 int using_load_multiple;
15214 int using_mtcr_multiple;
15215 int use_backchain_to_restore_sp;
15217 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15218 rtx frame_reg_rtx = sp_reg_rtx;
15219 enum machine_mode reg_mode = Pmode;
15220 int reg_size = TARGET_32BIT ? 4 : 8;
15223 info = rs6000_stack_info ();
15225 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15227 reg_mode = V2SImode;
15231 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15232 && (!TARGET_SPE_ABI
15233 || info->spe_64bit_regs_used == 0)
15234 && info->first_gp_reg_save < 31
15235 && no_global_regs_above (info->first_gp_reg_save));
15236 restoring_FPRs_inline = (sibcall
15237 || current_function_calls_eh_return
15238 || info->first_fp_reg_save == 64
15239 || FP_SAVE_INLINE (info->first_fp_reg_save));
15240 use_backchain_to_restore_sp = (frame_pointer_needed
15241 || current_function_calls_alloca
15242 || info->total_size > 32767);
15243 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15244 || rs6000_cpu == PROCESSOR_PPC603
15245 || rs6000_cpu == PROCESSOR_PPC750
15248 if (WORLD_SAVE_P (info))
15252 const char *alloc_rname;
15255 /* eh_rest_world_r10 will return to the location saved in the LR
15256 stack slot (which is not likely to be our caller.)
15257 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15258 rest_world is similar, except any R10 parameter is ignored.
15259 The exception-handling stuff that was here in 2.95 is no
15260 longer necessary. */
15264 + 32 - info->first_gp_reg_save
15265 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15266 + 63 + 1 - info->first_fp_reg_save);
15268 strcpy (rname, ((current_function_calls_eh_return) ?
15269 "*eh_rest_world_r10" : "*rest_world"));
15270 alloc_rname = ggc_strdup (rname);
15273 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15274 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15275 gen_rtx_REG (Pmode,
15276 LINK_REGISTER_REGNUM));
15278 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15279 /* The instruction pattern requires a clobber here;
15280 it is shared with the restVEC helper. */
15282 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15285 /* CR register traditionally saved as CR2. */
15286 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15287 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15288 GEN_INT (info->cr_save_offset));
15289 rtx mem = gen_frame_mem (reg_mode, addr);
15291 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15294 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15296 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15297 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15298 GEN_INT (info->gp_save_offset
15300 rtx mem = gen_frame_mem (reg_mode, addr);
15302 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15304 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15306 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15307 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15308 GEN_INT (info->altivec_save_offset
15310 rtx mem = gen_frame_mem (V4SImode, addr);
15312 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15314 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15316 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15317 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15318 GEN_INT (info->fp_save_offset
15320 rtx mem = gen_frame_mem (DFmode, addr);
15322 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15325 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15327 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15329 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15331 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15333 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15334 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15339 /* If we have a frame pointer, a call to alloca, or a large stack
15340 frame, restore the old stack pointer using the backchain. Otherwise,
15341 we know what size to update it with. */
15342 if (use_backchain_to_restore_sp)
15344 /* Under V.4, don't reset the stack pointer until after we're done
15345 loading the saved registers. */
15346 if (DEFAULT_ABI == ABI_V4)
15347 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15349 emit_move_insn (frame_reg_rtx,
15350 gen_rtx_MEM (Pmode, sp_reg_rtx));
15352 else if (info->push_p)
15354 if (DEFAULT_ABI == ABI_V4
15355 || current_function_calls_eh_return)
15356 sp_offset = info->total_size;
15359 emit_insn (TARGET_32BIT
15360 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15361 GEN_INT (info->total_size))
15362 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15363 GEN_INT (info->total_size)));
15367 /* Restore AltiVec registers if needed. */
15368 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15372 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15373 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15375 rtx addr, areg, mem;
15377 areg = gen_rtx_REG (Pmode, 0);
15379 (areg, GEN_INT (info->altivec_save_offset
15381 + 16 * (i - info->first_altivec_reg_save)));
15383 /* AltiVec addressing mode is [reg+reg]. */
15384 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15385 mem = gen_frame_mem (V4SImode, addr);
15387 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15391 /* Restore VRSAVE if needed. */
15392 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15393 && info->vrsave_mask != 0)
15395 rtx addr, mem, reg;
15397 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15398 GEN_INT (info->vrsave_save_offset + sp_offset));
15399 mem = gen_frame_mem (SImode, addr);
15400 reg = gen_rtx_REG (SImode, 12);
15401 emit_move_insn (reg, mem);
15403 emit_insn (generate_set_vrsave (reg, info, 1));
15406 /* Get the old lr if we saved it. */
15407 if (info->lr_save_p)
15409 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15410 info->lr_save_offset + sp_offset);
15412 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15415 /* Get the old cr if we saved it. */
15416 if (info->cr_save_p)
15418 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15419 GEN_INT (info->cr_save_offset + sp_offset));
15420 rtx mem = gen_frame_mem (SImode, addr);
15422 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15425 /* Set LR here to try to overlap restores below. */
15426 if (info->lr_save_p)
15427 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15428 gen_rtx_REG (Pmode, 0));
15430 /* Load exception handler data registers, if needed. */
15431 if (current_function_calls_eh_return)
15433 unsigned int i, regno;
15437 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15438 GEN_INT (sp_offset + 5 * reg_size));
15439 rtx mem = gen_frame_mem (reg_mode, addr);
15441 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15448 regno = EH_RETURN_DATA_REGNO (i);
15449 if (regno == INVALID_REGNUM)
15452 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15453 info->ehrd_offset + sp_offset
15454 + reg_size * (int) i);
15456 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15460 /* Restore GPRs. This is done as a PARALLEL if we are using
15461 the load-multiple instructions. */
15462 if (using_load_multiple)
15465 p = rtvec_alloc (32 - info->first_gp_reg_save);
15466 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15468 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15469 GEN_INT (info->gp_save_offset
15472 rtx mem = gen_frame_mem (reg_mode, addr);
15475 gen_rtx_SET (VOIDmode,
15476 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15479 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15482 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15483 if ((regs_ever_live[info->first_gp_reg_save + i]
15484 && (!call_used_regs[info->first_gp_reg_save + i]
15485 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15486 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15487 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15488 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15489 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15491 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15492 GEN_INT (info->gp_save_offset
15495 rtx mem = gen_frame_mem (reg_mode, addr);
15497 /* Restore 64-bit quantities for SPE. */
15498 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15500 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15503 if (!SPE_CONST_OFFSET_OK (offset))
15505 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15506 emit_move_insn (b, GEN_INT (offset));
15509 b = GEN_INT (offset);
15511 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15512 mem = gen_frame_mem (V2SImode, addr);
15515 emit_move_insn (gen_rtx_REG (reg_mode,
15516 info->first_gp_reg_save + i), mem);
15519 /* Restore fpr's if we need to do it without calling a function. */
15520 if (restoring_FPRs_inline)
15521 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15522 if ((regs_ever_live[info->first_fp_reg_save+i]
15523 && ! call_used_regs[info->first_fp_reg_save+i]))
15526 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15527 GEN_INT (info->fp_save_offset
15530 mem = gen_frame_mem (DFmode, addr);
15532 emit_move_insn (gen_rtx_REG (DFmode,
15533 info->first_fp_reg_save + i),
15537 /* If we saved cr, restore it here. Just those that were used. */
15538 if (info->cr_save_p)
15540 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15543 if (using_mtcr_multiple)
15545 for (i = 0; i < 8; i++)
15546 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15548 gcc_assert (count);
15551 if (using_mtcr_multiple && count > 1)
15556 p = rtvec_alloc (count);
15559 for (i = 0; i < 8; i++)
15560 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15562 rtvec r = rtvec_alloc (2);
15563 RTVEC_ELT (r, 0) = r12_rtx;
15564 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15565 RTVEC_ELT (p, ndx) =
15566 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15567 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15570 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15571 gcc_assert (ndx == count);
15574 for (i = 0; i < 8; i++)
15575 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15577 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15583 /* If this is V.4, unwind the stack pointer after all of the loads
15585 if (frame_reg_rtx != sp_reg_rtx)
15587 /* This blockage is needed so that sched doesn't decide to move
15588 the sp change before the register restores. */
15589 rs6000_emit_stack_tie ();
15590 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15592 else if (sp_offset != 0)
15593 emit_insn (TARGET_32BIT
15594 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15595 GEN_INT (sp_offset))
15596 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15597 GEN_INT (sp_offset)));
15599 if (current_function_calls_eh_return)
15601 rtx sa = EH_RETURN_STACKADJ_RTX;
15602 emit_insn (TARGET_32BIT
15603 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15604 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15610 if (! restoring_FPRs_inline)
15611 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15613 p = rtvec_alloc (2);
15615 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15616 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15617 gen_rtx_REG (Pmode,
15618 LINK_REGISTER_REGNUM));
15620 /* If we have to restore more than two FP registers, branch to the
15621 restore function. It will return to our caller. */
15622 if (! restoring_FPRs_inline)
15626 const char *alloc_rname;
15628 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15629 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15630 alloc_rname = ggc_strdup (rname);
15631 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15632 gen_rtx_SYMBOL_REF (Pmode,
15635 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15638 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15639 GEN_INT (info->fp_save_offset + 8*i));
15640 mem = gen_frame_mem (DFmode, addr);
15642 RTVEC_ELT (p, i+3) =
15643 gen_rtx_SET (VOIDmode,
15644 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15649 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15653 /* Write function epilogue. */
15656 rs6000_output_function_epilogue (FILE *file,
15657 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15659 if (! HAVE_epilogue)
15661 rtx insn = get_last_insn ();
15662 /* If the last insn was a BARRIER, we don't have to write anything except
15663 the trace table. */
15664 if (GET_CODE (insn) == NOTE)
15665 insn = prev_nonnote_insn (insn);
15666 if (insn == 0 || GET_CODE (insn) != BARRIER)
15668 /* This is slightly ugly, but at least we don't have two
15669 copies of the epilogue-emitting code. */
15672 /* A NOTE_INSN_DELETED is supposed to be at the start
15673 and end of the "toplevel" insn chain. */
15674 emit_note (NOTE_INSN_DELETED);
15675 rs6000_emit_epilogue (FALSE);
15676 emit_note (NOTE_INSN_DELETED);
15678 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15682 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15684 INSN_ADDRESSES_NEW (insn, addr);
15689 if (TARGET_DEBUG_STACK)
15690 debug_rtx_list (get_insns (), 100);
15691 final (get_insns (), file, FALSE);
15697 macho_branch_islands ();
15698 /* Mach-O doesn't support labels at the end of objects, so if
15699 it looks like we might want one, insert a NOP. */
15701 rtx insn = get_last_insn ();
15704 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15705 insn = PREV_INSN (insn);
15709 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15710 fputs ("\tnop\n", file);
15714 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15717 We don't output a traceback table if -finhibit-size-directive was
15718 used. The documentation for -finhibit-size-directive reads
15719 ``don't output a @code{.size} assembler directive, or anything
15720 else that would cause trouble if the function is split in the
15721 middle, and the two halves are placed at locations far apart in
15722 memory.'' The traceback table has this property, since it
15723 includes the offset from the start of the function to the
15724 traceback table itself.
15726 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15727 different traceback table. */
15728 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15729 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15731 const char *fname = NULL;
15732 const char *language_string = lang_hooks.name;
15733 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15735 int optional_tbtab;
15736 rs6000_stack_t *info = rs6000_stack_info ();
15738 if (rs6000_traceback == traceback_full)
15739 optional_tbtab = 1;
15740 else if (rs6000_traceback == traceback_part)
15741 optional_tbtab = 0;
15743 optional_tbtab = !optimize_size && !TARGET_ELF;
15745 if (optional_tbtab)
15747 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15748 while (*fname == '.') /* V.4 encodes . in the name */
15751 /* Need label immediately before tbtab, so we can compute
15752 its offset from the function start. */
15753 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15754 ASM_OUTPUT_LABEL (file, fname);
15757 /* The .tbtab pseudo-op can only be used for the first eight
15758 expressions, since it can't handle the possibly variable
15759 length fields that follow. However, if you omit the optional
15760 fields, the assembler outputs zeros for all optional fields
15761 anyways, giving each variable length field is minimum length
15762 (as defined in sys/debug.h). Thus we can not use the .tbtab
15763 pseudo-op at all. */
15765 /* An all-zero word flags the start of the tbtab, for debuggers
15766 that have to find it by searching forward from the entry
15767 point or from the current pc. */
15768 fputs ("\t.long 0\n", file);
15770 /* Tbtab format type. Use format type 0. */
15771 fputs ("\t.byte 0,", file);
15773 /* Language type. Unfortunately, there does not seem to be any
15774 official way to discover the language being compiled, so we
15775 use language_string.
15776 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15777 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15778 a number, so for now use 9. */
15779 if (! strcmp (language_string, "GNU C"))
15781 else if (! strcmp (language_string, "GNU F77")
15782 || ! strcmp (language_string, "GNU F95"))
15784 else if (! strcmp (language_string, "GNU Pascal"))
15786 else if (! strcmp (language_string, "GNU Ada"))
15788 else if (! strcmp (language_string, "GNU C++")
15789 || ! strcmp (language_string, "GNU Objective-C++"))
15791 else if (! strcmp (language_string, "GNU Java"))
15793 else if (! strcmp (language_string, "GNU Objective-C"))
15796 gcc_unreachable ();
15797 fprintf (file, "%d,", i);
15799 /* 8 single bit fields: global linkage (not set for C extern linkage,
15800 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15801 from start of procedure stored in tbtab, internal function, function
15802 has controlled storage, function has no toc, function uses fp,
15803 function logs/aborts fp operations. */
15804 /* Assume that fp operations are used if any fp reg must be saved. */
15805 fprintf (file, "%d,",
15806 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15808 /* 6 bitfields: function is interrupt handler, name present in
15809 proc table, function calls alloca, on condition directives
15810 (controls stack walks, 3 bits), saves condition reg, saves
15812 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15813 set up as a frame pointer, even when there is no alloca call. */
15814 fprintf (file, "%d,",
15815 ((optional_tbtab << 6)
15816 | ((optional_tbtab & frame_pointer_needed) << 5)
15817 | (info->cr_save_p << 1)
15818 | (info->lr_save_p)));
15820 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15822 fprintf (file, "%d,",
15823 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15825 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15826 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15828 if (optional_tbtab)
15830 /* Compute the parameter info from the function decl argument
15833 int next_parm_info_bit = 31;
15835 for (decl = DECL_ARGUMENTS (current_function_decl);
15836 decl; decl = TREE_CHAIN (decl))
15838 rtx parameter = DECL_INCOMING_RTL (decl);
15839 enum machine_mode mode = GET_MODE (parameter);
15841 if (GET_CODE (parameter) == REG)
15843 if (SCALAR_FLOAT_MODE_P (mode))
15861 gcc_unreachable ();
15864 /* If only one bit will fit, don't or in this entry. */
15865 if (next_parm_info_bit > 0)
15866 parm_info |= (bits << (next_parm_info_bit - 1));
15867 next_parm_info_bit -= 2;
15871 fixed_parms += ((GET_MODE_SIZE (mode)
15872 + (UNITS_PER_WORD - 1))
15874 next_parm_info_bit -= 1;
15880 /* Number of fixed point parameters. */
15881 /* This is actually the number of words of fixed point parameters; thus
15882 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15883 fprintf (file, "%d,", fixed_parms);
15885 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15887 /* This is actually the number of fp registers that hold parameters;
15888 and thus the maximum value is 13. */
15889 /* Set parameters on stack bit if parameters are not in their original
15890 registers, regardless of whether they are on the stack? Xlc
15891 seems to set the bit when not optimizing. */
15892 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15894 if (! optional_tbtab)
15897 /* Optional fields follow. Some are variable length. */
15899 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15900 11 double float. */
15901 /* There is an entry for each parameter in a register, in the order that
15902 they occur in the parameter list. Any intervening arguments on the
15903 stack are ignored. If the list overflows a long (max possible length
15904 34 bits) then completely leave off all elements that don't fit. */
15905 /* Only emit this long if there was at least one parameter. */
15906 if (fixed_parms || float_parms)
15907 fprintf (file, "\t.long %d\n", parm_info);
15909 /* Offset from start of code to tb table. */
15910 fputs ("\t.long ", file);
15911 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15913 RS6000_OUTPUT_BASENAME (file, fname);
15915 assemble_name (file, fname);
15917 rs6000_output_function_entry (file, fname);
15920 /* Interrupt handler mask. */
15921 /* Omit this long, since we never set the interrupt handler bit
15924 /* Number of CTL (controlled storage) anchors. */
15925 /* Omit this long, since the has_ctl bit is never set above. */
15927 /* Displacement into stack of each CTL anchor. */
15928 /* Omit this list of longs, because there are no CTL anchors. */
15930 /* Length of function name. */
15933 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15935 /* Function name. */
15936 assemble_string (fname, strlen (fname));
15938 /* Register for alloca automatic storage; this is always reg 31.
15939 Only emit this if the alloca bit was set above. */
15940 if (frame_pointer_needed)
15941 fputs ("\t.byte 31\n", file);
15943 fputs ("\t.align 2\n", file);
15947 /* A C compound statement that outputs the assembler code for a thunk
15948 function, used to implement C++ virtual function calls with
15949 multiple inheritance. The thunk acts as a wrapper around a virtual
15950 function, adjusting the implicit object parameter before handing
15951 control off to the real function.
15953 First, emit code to add the integer DELTA to the location that
15954 contains the incoming first argument. Assume that this argument
15955 contains a pointer, and is the one used to pass the `this' pointer
15956 in C++. This is the incoming argument *before* the function
15957 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15958 values of all other incoming arguments.
15960 After the addition, emit code to jump to FUNCTION, which is a
15961 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15962 not touch the return address. Hence returning from FUNCTION will
15963 return to whoever called the current `thunk'.
15965 The effect must be as if FUNCTION had been called directly with the
15966 adjusted first argument. This macro is responsible for emitting
15967 all of the code for a thunk function; output_function_prologue()
15968 and output_function_epilogue() are not invoked.
15970 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15971 been extracted from it.) It might possibly be useful on some
15972 targets, but probably not.
15974 If you do not define this macro, the target-independent code in the
15975 C++ frontend will generate a less efficient heavyweight thunk that
15976 calls FUNCTION instead of jumping to it. The generic approach does
15977 not support varargs. */
15980 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15981 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15984 rtx this, insn, funexp;
15986 reload_completed = 1;
15987 epilogue_completed = 1;
15988 no_new_pseudos = 1;
15989 reset_block_changes ();
15991 /* Mark the end of the (empty) prologue. */
15992 emit_note (NOTE_INSN_PROLOGUE_END);
15994 /* Find the "this" pointer. If the function returns a structure,
15995 the structure return pointer is in r3. */
15996 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15997 this = gen_rtx_REG (Pmode, 4);
15999 this = gen_rtx_REG (Pmode, 3);
16001 /* Apply the constant offset, if required. */
16004 rtx delta_rtx = GEN_INT (delta);
16005 emit_insn (TARGET_32BIT
16006 ? gen_addsi3 (this, this, delta_rtx)
16007 : gen_adddi3 (this, this, delta_rtx));
16010 /* Apply the offset from the vtable, if required. */
16013 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16014 rtx tmp = gen_rtx_REG (Pmode, 12);
16016 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16017 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16019 emit_insn (TARGET_32BIT
16020 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16021 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16022 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16026 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16028 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16030 emit_insn (TARGET_32BIT
16031 ? gen_addsi3 (this, this, tmp)
16032 : gen_adddi3 (this, this, tmp));
16035 /* Generate a tail call to the target function. */
16036 if (!TREE_USED (function))
16038 assemble_external (function);
16039 TREE_USED (function) = 1;
16041 funexp = XEXP (DECL_RTL (function), 0);
16042 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16045 if (MACHOPIC_INDIRECT)
16046 funexp = machopic_indirect_call_target (funexp);
16049 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16050 generate sibcall RTL explicitly. */
16051 insn = emit_call_insn (
16052 gen_rtx_PARALLEL (VOIDmode,
16054 gen_rtx_CALL (VOIDmode,
16055 funexp, const0_rtx),
16056 gen_rtx_USE (VOIDmode, const0_rtx),
16057 gen_rtx_USE (VOIDmode,
16058 gen_rtx_REG (SImode,
16059 LINK_REGISTER_REGNUM)),
16060 gen_rtx_RETURN (VOIDmode))));
16061 SIBLING_CALL_P (insn) = 1;
16064 /* Run just enough of rest_of_compilation to get the insns emitted.
16065 There's not really enough bulk here to make other passes such as
16066 instruction scheduling worth while. Note that use_thunk calls
16067 assemble_start_function and assemble_end_function. */
16068 insn = get_insns ();
16069 insn_locators_initialize ();
16070 shorten_branches (insn);
16071 final_start_function (insn, file, 1);
16072 final (insn, file, 1);
16073 final_end_function ();
16075 reload_completed = 0;
16076 epilogue_completed = 0;
16077 no_new_pseudos = 0;
16080 /* A quick summary of the various types of 'constant-pool tables'
16083 Target Flags Name One table per
16084 AIX (none) AIX TOC object file
16085 AIX -mfull-toc AIX TOC object file
16086 AIX -mminimal-toc AIX minimal TOC translation unit
16087 SVR4/EABI (none) SVR4 SDATA object file
16088 SVR4/EABI -fpic SVR4 pic object file
16089 SVR4/EABI -fPIC SVR4 PIC translation unit
16090 SVR4/EABI -mrelocatable EABI TOC function
16091 SVR4/EABI -maix AIX TOC object file
16092 SVR4/EABI -maix -mminimal-toc
16093 AIX minimal TOC translation unit
16095 Name Reg. Set by entries contains:
16096 made by addrs? fp? sum?
16098 AIX TOC 2 crt0 as Y option option
16099 AIX minimal TOC 30 prolog gcc Y Y option
16100 SVR4 SDATA 13 crt0 gcc N Y N
16101 SVR4 pic 30 prolog ld Y not yet N
16102 SVR4 PIC 30 prolog gcc Y option option
16103 EABI TOC 30 prolog gcc Y option option
16107 /* Hash functions for the hash table. */
16110 rs6000_hash_constant (rtx k)
16112 enum rtx_code code = GET_CODE (k);
16113 enum machine_mode mode = GET_MODE (k);
16114 unsigned result = (code << 3) ^ mode;
16115 const char *format;
16118 format = GET_RTX_FORMAT (code);
16119 flen = strlen (format);
16125 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16128 if (mode != VOIDmode)
16129 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16141 for (; fidx < flen; fidx++)
16142 switch (format[fidx])
16147 const char *str = XSTR (k, fidx);
16148 len = strlen (str);
16149 result = result * 613 + len;
16150 for (i = 0; i < len; i++)
16151 result = result * 613 + (unsigned) str[i];
16156 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16160 result = result * 613 + (unsigned) XINT (k, fidx);
16163 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16164 result = result * 613 + (unsigned) XWINT (k, fidx);
16168 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16169 result = result * 613 + (unsigned) (XWINT (k, fidx)
16176 gcc_unreachable ();
16183 toc_hash_function (const void *hash_entry)
16185 const struct toc_hash_struct *thc =
16186 (const struct toc_hash_struct *) hash_entry;
16187 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16190 /* Compare H1 and H2 for equivalence. */
16193 toc_hash_eq (const void *h1, const void *h2)
16195 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16196 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16198 if (((const struct toc_hash_struct *) h1)->key_mode
16199 != ((const struct toc_hash_struct *) h2)->key_mode)
16202 return rtx_equal_p (r1, r2);
16205 /* These are the names given by the C++ front-end to vtables, and
16206 vtable-like objects. Ideally, this logic should not be here;
16207 instead, there should be some programmatic way of inquiring as
16208 to whether or not an object is a vtable. */
16210 #define VTABLE_NAME_P(NAME) \
16211 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16212 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16213 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16214 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16215 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16218 rs6000_output_symbol_ref (FILE *file, rtx x)
16220 /* Currently C++ toc references to vtables can be emitted before it
16221 is decided whether the vtable is public or private. If this is
16222 the case, then the linker will eventually complain that there is
16223 a reference to an unknown section. Thus, for vtables only,
16224 we emit the TOC reference to reference the symbol and not the
16226 const char *name = XSTR (x, 0);
16228 if (VTABLE_NAME_P (name))
16230 RS6000_OUTPUT_BASENAME (file, name);
16233 assemble_name (file, name);
16236 /* Output a TOC entry. We derive the entry name from what is being
16240 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16243 const char *name = buf;
16244 const char *real_name;
16246 HOST_WIDE_INT offset = 0;
16248 gcc_assert (!TARGET_NO_TOC);
16250 /* When the linker won't eliminate them, don't output duplicate
16251 TOC entries (this happens on AIX if there is any kind of TOC,
16252 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16254 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16256 struct toc_hash_struct *h;
16259 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16260 time because GGC is not initialized at that point. */
16261 if (toc_hash_table == NULL)
16262 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16263 toc_hash_eq, NULL);
16265 h = ggc_alloc (sizeof (*h));
16267 h->key_mode = mode;
16268 h->labelno = labelno;
16270 found = htab_find_slot (toc_hash_table, h, 1);
16271 if (*found == NULL)
16273 else /* This is indeed a duplicate.
16274 Set this label equal to that label. */
16276 fputs ("\t.set ", file);
16277 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16278 fprintf (file, "%d,", labelno);
16279 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16280 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16286 /* If we're going to put a double constant in the TOC, make sure it's
16287 aligned properly when strict alignment is on. */
16288 if (GET_CODE (x) == CONST_DOUBLE
16289 && STRICT_ALIGNMENT
16290 && GET_MODE_BITSIZE (mode) >= 64
16291 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16292 ASM_OUTPUT_ALIGN (file, 3);
16295 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16297 /* Handle FP constants specially. Note that if we have a minimal
16298 TOC, things we put here aren't actually in the TOC, so we can allow
16300 if (GET_CODE (x) == CONST_DOUBLE &&
16301 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16303 REAL_VALUE_TYPE rv;
16306 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16307 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16308 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16310 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16314 if (TARGET_MINIMAL_TOC)
16315 fputs (DOUBLE_INT_ASM_OP, file);
16317 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16318 k[0] & 0xffffffff, k[1] & 0xffffffff,
16319 k[2] & 0xffffffff, k[3] & 0xffffffff);
16320 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16321 k[0] & 0xffffffff, k[1] & 0xffffffff,
16322 k[2] & 0xffffffff, k[3] & 0xffffffff);
16327 if (TARGET_MINIMAL_TOC)
16328 fputs ("\t.long ", file);
16330 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16331 k[0] & 0xffffffff, k[1] & 0xffffffff,
16332 k[2] & 0xffffffff, k[3] & 0xffffffff);
16333 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16334 k[0] & 0xffffffff, k[1] & 0xffffffff,
16335 k[2] & 0xffffffff, k[3] & 0xffffffff);
16339 else if (GET_CODE (x) == CONST_DOUBLE &&
16340 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16342 REAL_VALUE_TYPE rv;
16345 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16347 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16348 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16350 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16354 if (TARGET_MINIMAL_TOC)
16355 fputs (DOUBLE_INT_ASM_OP, file);
16357 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16358 k[0] & 0xffffffff, k[1] & 0xffffffff);
16359 fprintf (file, "0x%lx%08lx\n",
16360 k[0] & 0xffffffff, k[1] & 0xffffffff);
16365 if (TARGET_MINIMAL_TOC)
16366 fputs ("\t.long ", file);
16368 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16369 k[0] & 0xffffffff, k[1] & 0xffffffff);
16370 fprintf (file, "0x%lx,0x%lx\n",
16371 k[0] & 0xffffffff, k[1] & 0xffffffff);
16375 else if (GET_CODE (x) == CONST_DOUBLE &&
16376 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16378 REAL_VALUE_TYPE rv;
16381 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16382 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16383 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16385 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16389 if (TARGET_MINIMAL_TOC)
16390 fputs (DOUBLE_INT_ASM_OP, file);
16392 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16393 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16398 if (TARGET_MINIMAL_TOC)
16399 fputs ("\t.long ", file);
16401 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16402 fprintf (file, "0x%lx\n", l & 0xffffffff);
16406 else if (GET_MODE (x) == VOIDmode
16407 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16409 unsigned HOST_WIDE_INT low;
16410 HOST_WIDE_INT high;
16412 if (GET_CODE (x) == CONST_DOUBLE)
16414 low = CONST_DOUBLE_LOW (x);
16415 high = CONST_DOUBLE_HIGH (x);
16418 #if HOST_BITS_PER_WIDE_INT == 32
16421 high = (low & 0x80000000) ? ~0 : 0;
16425 low = INTVAL (x) & 0xffffffff;
16426 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16430 /* TOC entries are always Pmode-sized, but since this
16431 is a bigendian machine then if we're putting smaller
16432 integer constants in the TOC we have to pad them.
16433 (This is still a win over putting the constants in
16434 a separate constant pool, because then we'd have
16435 to have both a TOC entry _and_ the actual constant.)
16437 For a 32-bit target, CONST_INT values are loaded and shifted
16438 entirely within `low' and can be stored in one TOC entry. */
16440 /* It would be easy to make this work, but it doesn't now. */
16441 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16443 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16445 #if HOST_BITS_PER_WIDE_INT == 32
16446 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16447 POINTER_SIZE, &low, &high, 0);
16450 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16451 high = (HOST_WIDE_INT) low >> 32;
16458 if (TARGET_MINIMAL_TOC)
16459 fputs (DOUBLE_INT_ASM_OP, file);
16461 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16462 (long) high & 0xffffffff, (long) low & 0xffffffff);
16463 fprintf (file, "0x%lx%08lx\n",
16464 (long) high & 0xffffffff, (long) low & 0xffffffff);
16469 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16471 if (TARGET_MINIMAL_TOC)
16472 fputs ("\t.long ", file);
16474 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16475 (long) high & 0xffffffff, (long) low & 0xffffffff);
16476 fprintf (file, "0x%lx,0x%lx\n",
16477 (long) high & 0xffffffff, (long) low & 0xffffffff);
16481 if (TARGET_MINIMAL_TOC)
16482 fputs ("\t.long ", file);
16484 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16485 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16491 if (GET_CODE (x) == CONST)
16493 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16495 base = XEXP (XEXP (x, 0), 0);
16496 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16499 switch (GET_CODE (base))
16502 name = XSTR (base, 0);
16506 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16507 CODE_LABEL_NUMBER (XEXP (base, 0)));
16511 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16515 gcc_unreachable ();
16518 real_name = (*targetm.strip_name_encoding) (name);
16519 if (TARGET_MINIMAL_TOC)
16520 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16523 fprintf (file, "\t.tc %s", real_name);
16526 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16528 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16530 fputs ("[TC],", file);
16533 /* Currently C++ toc references to vtables can be emitted before it
16534 is decided whether the vtable is public or private. If this is
16535 the case, then the linker will eventually complain that there is
16536 a TOC reference to an unknown section. Thus, for vtables only,
16537 we emit the TOC reference to reference the symbol and not the
16539 if (VTABLE_NAME_P (name))
16541 RS6000_OUTPUT_BASENAME (file, name);
16543 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16544 else if (offset > 0)
16545 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16548 output_addr_const (file, x);
16552 /* Output an assembler pseudo-op to write an ASCII string of N characters
16553 starting at P to FILE.
16555 On the RS/6000, we have to do this using the .byte operation and
16556 write out special characters outside the quoted string.
16557 Also, the assembler is broken; very long strings are truncated,
16558 so we must artificially break them up early. */
16561 output_ascii (FILE *file, const char *p, int n)
16564 int i, count_string;
16565 const char *for_string = "\t.byte \"";
16566 const char *for_decimal = "\t.byte ";
16567 const char *to_close = NULL;
16570 for (i = 0; i < n; i++)
16573 if (c >= ' ' && c < 0177)
16576 fputs (for_string, file);
16579 /* Write two quotes to get one. */
16587 for_decimal = "\"\n\t.byte ";
16591 if (count_string >= 512)
16593 fputs (to_close, file);
16595 for_string = "\t.byte \"";
16596 for_decimal = "\t.byte ";
16604 fputs (for_decimal, file);
16605 fprintf (file, "%d", c);
16607 for_string = "\n\t.byte \"";
16608 for_decimal = ", ";
16614 /* Now close the string if we have written one. Then end the line. */
16616 fputs (to_close, file);
16619 /* Generate a unique section name for FILENAME for a section type
16620 represented by SECTION_DESC. Output goes into BUF.
16622 SECTION_DESC can be any string, as long as it is different for each
16623 possible section type.
16625 We name the section in the same manner as xlc. The name begins with an
16626 underscore followed by the filename (after stripping any leading directory
16627 names) with the last period replaced by the string SECTION_DESC. If
16628 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16632 rs6000_gen_section_name (char **buf, const char *filename,
16633 const char *section_desc)
16635 const char *q, *after_last_slash, *last_period = 0;
16639 after_last_slash = filename;
16640 for (q = filename; *q; q++)
16643 after_last_slash = q + 1;
16644 else if (*q == '.')
16648 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16649 *buf = (char *) xmalloc (len);
16654 for (q = after_last_slash; *q; q++)
16656 if (q == last_period)
16658 strcpy (p, section_desc);
16659 p += strlen (section_desc);
16663 else if (ISALNUM (*q))
16667 if (last_period == 0)
16668 strcpy (p, section_desc);
16673 /* Emit profile function. */
16676 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16678 /* Non-standard profiling for kernels, which just saves LR then calls
16679 _mcount without worrying about arg saves. The idea is to change
16680 the function prologue as little as possible as it isn't easy to
16681 account for arg save/restore code added just for _mcount. */
16682 if (TARGET_PROFILE_KERNEL)
16685 if (DEFAULT_ABI == ABI_AIX)
16687 #ifndef NO_PROFILE_COUNTERS
16688 # define NO_PROFILE_COUNTERS 0
16690 if (NO_PROFILE_COUNTERS)
16691 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16695 const char *label_name;
16698 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16699 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16700 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16702 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16706 else if (DEFAULT_ABI == ABI_DARWIN)
16708 const char *mcount_name = RS6000_MCOUNT;
16709 int caller_addr_regno = LINK_REGISTER_REGNUM;
16711 /* Be conservative and always set this, at least for now. */
16712 current_function_uses_pic_offset_table = 1;
16715 /* For PIC code, set up a stub and collect the caller's address
16716 from r0, which is where the prologue puts it. */
16717 if (MACHOPIC_INDIRECT
16718 && current_function_uses_pic_offset_table)
16719 caller_addr_regno = 0;
16721 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16723 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16727 /* Write function profiler code. */
16730 output_function_profiler (FILE *file, int labelno)
16734 switch (DEFAULT_ABI)
16737 gcc_unreachable ();
16742 warning (0, "no profiling of 64-bit code for this ABI");
16745 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16746 fprintf (file, "\tmflr %s\n", reg_names[0]);
16747 if (NO_PROFILE_COUNTERS)
16749 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16750 reg_names[0], reg_names[1]);
16752 else if (TARGET_SECURE_PLT && flag_pic)
16754 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16755 reg_names[0], reg_names[1]);
16756 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16757 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16758 reg_names[12], reg_names[12]);
16759 assemble_name (file, buf);
16760 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16761 assemble_name (file, buf);
16762 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16764 else if (flag_pic == 1)
16766 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16767 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16768 reg_names[0], reg_names[1]);
16769 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16770 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16771 assemble_name (file, buf);
16772 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16774 else if (flag_pic > 1)
16776 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16777 reg_names[0], reg_names[1]);
16778 /* Now, we need to get the address of the label. */
16779 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16780 assemble_name (file, buf);
16781 fputs ("-.\n1:", file);
16782 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16783 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16784 reg_names[0], reg_names[11]);
16785 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16786 reg_names[0], reg_names[0], reg_names[11]);
16790 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16791 assemble_name (file, buf);
16792 fputs ("@ha\n", file);
16793 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16794 reg_names[0], reg_names[1]);
16795 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16796 assemble_name (file, buf);
16797 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16800 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16801 fprintf (file, "\tbl %s%s\n",
16802 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16807 if (!TARGET_PROFILE_KERNEL)
16809 /* Don't do anything, done in output_profile_hook (). */
16813 gcc_assert (!TARGET_32BIT);
16815 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16816 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16818 if (cfun->static_chain_decl != NULL)
16820 asm_fprintf (file, "\tstd %s,24(%s)\n",
16821 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16822 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16823 asm_fprintf (file, "\tld %s,24(%s)\n",
16824 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16827 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16835 /* The following variable value is the last issued insn. */
16837 static rtx last_scheduled_insn;
16839 /* The following variable helps to balance issuing of load and
16840 store instructions */
16842 static int load_store_pendulum;
16844 /* Power4 load update and store update instructions are cracked into a
16845 load or store and an integer insn which are executed in the same cycle.
16846 Branches have their own dispatch slot which does not count against the
16847 GCC issue rate, but it changes the program flow so there are no other
16848 instructions to issue in this cycle. */
16851 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16852 int verbose ATTRIBUTE_UNUSED,
16853 rtx insn, int more)
16855 last_scheduled_insn = insn;
16856 if (GET_CODE (PATTERN (insn)) == USE
16857 || GET_CODE (PATTERN (insn)) == CLOBBER)
16859 cached_can_issue_more = more;
16860 return cached_can_issue_more;
16863 if (insn_terminates_group_p (insn, current_group))
16865 cached_can_issue_more = 0;
16866 return cached_can_issue_more;
16869 /* If no reservation, but reach here */
16870 if (recog_memoized (insn) < 0)
16873 if (rs6000_sched_groups)
16875 if (is_microcoded_insn (insn))
16876 cached_can_issue_more = 0;
16877 else if (is_cracked_insn (insn))
16878 cached_can_issue_more = more > 2 ? more - 2 : 0;
16880 cached_can_issue_more = more - 1;
16882 return cached_can_issue_more;
16885 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
16888 cached_can_issue_more = more - 1;
16889 return cached_can_issue_more;
16892 /* Adjust the cost of a scheduling dependency. Return the new cost of
16893 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16896 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16898 enum attr_type attr_type;
16900 if (! recog_memoized (insn))
16903 switch (REG_NOTE_KIND (link))
16907 /* Data dependency; DEP_INSN writes a register that INSN reads
16908 some cycles later. */
16910 /* Separate a load from a narrower, dependent store. */
16911 if (rs6000_sched_groups
16912 && GET_CODE (PATTERN (insn)) == SET
16913 && GET_CODE (PATTERN (dep_insn)) == SET
16914 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16915 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16916 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16917 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16920 attr_type = get_attr_type (insn);
16925 /* Tell the first scheduling pass about the latency between
16926 a mtctr and bctr (and mtlr and br/blr). The first
16927 scheduling pass will not know about this latency since
16928 the mtctr instruction, which has the latency associated
16929 to it, will be generated by reload. */
16930 return TARGET_POWER ? 5 : 4;
16932 /* Leave some extra cycles between a compare and its
16933 dependent branch, to inhibit expensive mispredicts. */
16934 if ((rs6000_cpu_attr == CPU_PPC603
16935 || rs6000_cpu_attr == CPU_PPC604
16936 || rs6000_cpu_attr == CPU_PPC604E
16937 || rs6000_cpu_attr == CPU_PPC620
16938 || rs6000_cpu_attr == CPU_PPC630
16939 || rs6000_cpu_attr == CPU_PPC750
16940 || rs6000_cpu_attr == CPU_PPC7400
16941 || rs6000_cpu_attr == CPU_PPC7450
16942 || rs6000_cpu_attr == CPU_POWER4
16943 || rs6000_cpu_attr == CPU_POWER5
16944 || rs6000_cpu_attr == CPU_CELL)
16945 && recog_memoized (dep_insn)
16946 && (INSN_CODE (dep_insn) >= 0))
16948 switch (get_attr_type (dep_insn))
16952 case TYPE_DELAYED_COMPARE:
16953 case TYPE_IMUL_COMPARE:
16954 case TYPE_LMUL_COMPARE:
16955 case TYPE_FPCOMPARE:
16956 case TYPE_CR_LOGICAL:
16957 case TYPE_DELAYED_CR:
16966 case TYPE_STORE_UX:
16968 case TYPE_FPSTORE_U:
16969 case TYPE_FPSTORE_UX:
16970 if ((rs6000_cpu == PROCESSOR_POWER6)
16971 && recog_memoized (dep_insn)
16972 && (INSN_CODE (dep_insn) >= 0))
16975 if (GET_CODE (PATTERN (insn)) != SET)
16976 /* If this happens, we have to extend this to schedule
16977 optimally. Return default for now. */
16980 /* Adjust the cost for the case where the value written
16981 by a fixed point operation is used as the address
16982 gen value on a store. */
16983 switch (get_attr_type (dep_insn))
16990 if (! store_data_bypass_p (dep_insn, insn))
16994 case TYPE_LOAD_EXT:
16995 case TYPE_LOAD_EXT_U:
16996 case TYPE_LOAD_EXT_UX:
16997 case TYPE_VAR_SHIFT_ROTATE:
16998 case TYPE_VAR_DELAYED_COMPARE:
17000 if (! store_data_bypass_p (dep_insn, insn))
17006 case TYPE_FAST_COMPARE:
17009 case TYPE_INSERT_WORD:
17010 case TYPE_INSERT_DWORD:
17011 case TYPE_FPLOAD_U:
17012 case TYPE_FPLOAD_UX:
17014 case TYPE_STORE_UX:
17015 case TYPE_FPSTORE_U:
17016 case TYPE_FPSTORE_UX:
17018 if (! store_data_bypass_p (dep_insn, insn))
17026 case TYPE_IMUL_COMPARE:
17027 case TYPE_LMUL_COMPARE:
17029 if (! store_data_bypass_p (dep_insn, insn))
17035 if (! store_data_bypass_p (dep_insn, insn))
17041 if (! store_data_bypass_p (dep_insn, insn))
17054 case TYPE_LOAD_EXT:
17055 case TYPE_LOAD_EXT_U:
17056 case TYPE_LOAD_EXT_UX:
17057 if ((rs6000_cpu == PROCESSOR_POWER6)
17058 && recog_memoized (dep_insn)
17059 && (INSN_CODE (dep_insn) >= 0))
17062 /* Adjust the cost for the case where the value written
17063 by a fixed point instruction is used within the address
17064 gen portion of a subsequent load(u)(x) */
17065 switch (get_attr_type (dep_insn))
17072 if (set_to_load_agen (dep_insn, insn))
17076 case TYPE_LOAD_EXT:
17077 case TYPE_LOAD_EXT_U:
17078 case TYPE_LOAD_EXT_UX:
17079 case TYPE_VAR_SHIFT_ROTATE:
17080 case TYPE_VAR_DELAYED_COMPARE:
17082 if (set_to_load_agen (dep_insn, insn))
17088 case TYPE_FAST_COMPARE:
17091 case TYPE_INSERT_WORD:
17092 case TYPE_INSERT_DWORD:
17093 case TYPE_FPLOAD_U:
17094 case TYPE_FPLOAD_UX:
17096 case TYPE_STORE_UX:
17097 case TYPE_FPSTORE_U:
17098 case TYPE_FPSTORE_UX:
17100 if (set_to_load_agen (dep_insn, insn))
17108 case TYPE_IMUL_COMPARE:
17109 case TYPE_LMUL_COMPARE:
17111 if (set_to_load_agen (dep_insn, insn))
17117 if (set_to_load_agen (dep_insn, insn))
17123 if (set_to_load_agen (dep_insn, insn))
17134 if ((rs6000_cpu == PROCESSOR_POWER6)
17135 && recog_memoized (dep_insn)
17136 && (INSN_CODE (dep_insn) >= 0)
17137 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17144 /* Fall out to return default cost. */
17148 case REG_DEP_OUTPUT:
17149 /* Output dependency; DEP_INSN writes a register that INSN writes some
17151 if ((rs6000_cpu == PROCESSOR_POWER6)
17152 && recog_memoized (dep_insn)
17153 && (INSN_CODE (dep_insn) >= 0))
17155 attr_type = get_attr_type (insn);
17160 if (get_attr_type (dep_insn) == TYPE_FP)
17164 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17172 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17177 gcc_unreachable ();
17183 /* The function returns a true if INSN is microcoded.
17184 Return false otherwise. */
17187 is_microcoded_insn (rtx insn)
17189 if (!insn || !INSN_P (insn)
17190 || GET_CODE (PATTERN (insn)) == USE
17191 || GET_CODE (PATTERN (insn)) == CLOBBER)
17194 if (rs6000_cpu_attr == CPU_CELL)
17195 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17197 if (rs6000_sched_groups)
17199 enum attr_type type = get_attr_type (insn);
17200 if (type == TYPE_LOAD_EXT_U
17201 || type == TYPE_LOAD_EXT_UX
17202 || type == TYPE_LOAD_UX
17203 || type == TYPE_STORE_UX
17204 || type == TYPE_MFCR)
17211 /* The function returns true if INSN is cracked into 2 instructions
17212 by the processor (and therefore occupies 2 issue slots). */
17215 is_cracked_insn (rtx insn)
17217 if (!insn || !INSN_P (insn)
17218 || GET_CODE (PATTERN (insn)) == USE
17219 || GET_CODE (PATTERN (insn)) == CLOBBER)
17222 if (rs6000_sched_groups)
17224 enum attr_type type = get_attr_type (insn);
17225 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17226 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17227 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17228 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17229 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17230 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17231 || type == TYPE_IDIV || type == TYPE_LDIV
17232 || type == TYPE_INSERT_WORD)
17239 /* The function returns true if INSN can be issued only from
17240 the branch slot. */
17243 is_branch_slot_insn (rtx insn)
17245 if (!insn || !INSN_P (insn)
17246 || GET_CODE (PATTERN (insn)) == USE
17247 || GET_CODE (PATTERN (insn)) == CLOBBER)
17250 if (rs6000_sched_groups)
17252 enum attr_type type = get_attr_type (insn);
17253 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17261 /* The function returns true if out_inst sets a value that is
17262 used in the address generation computation of in_insn */
17264 set_to_load_agen (rtx out_insn, rtx in_insn)
17266 rtx out_set, in_set;
17268 /* For performance reasons, only handle the simple case where
17269 both loads are a single_set. */
17270 out_set = single_set (out_insn);
17273 in_set = single_set (in_insn);
17275 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17281 /* The function returns true if the target storage location of
17282 out_insn is adjacent to the target storage location of in_insn */
17283 /* Return 1 if memory locations are adjacent. */
17286 adjacent_mem_locations (rtx insn1, rtx insn2)
17289 rtx a = get_store_dest (PATTERN (insn1));
17290 rtx b = get_store_dest (PATTERN (insn2));
17292 if ((GET_CODE (XEXP (a, 0)) == REG
17293 || (GET_CODE (XEXP (a, 0)) == PLUS
17294 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17295 && (GET_CODE (XEXP (b, 0)) == REG
17296 || (GET_CODE (XEXP (b, 0)) == PLUS
17297 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17299 HOST_WIDE_INT val0 = 0, val1 = 0;
17303 if (GET_CODE (XEXP (a, 0)) == PLUS)
17305 reg0 = XEXP (XEXP (a, 0), 0);
17306 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17309 reg0 = XEXP (a, 0);
17311 if (GET_CODE (XEXP (b, 0)) == PLUS)
17313 reg1 = XEXP (XEXP (b, 0), 0);
17314 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17317 reg1 = XEXP (b, 0);
17319 val_diff = val1 - val0;
17321 return ((REGNO (reg0) == REGNO (reg1))
17322 && (val_diff == INTVAL (MEM_SIZE (a))
17323 || val_diff == -INTVAL (MEM_SIZE (b))));
17329 /* A C statement (sans semicolon) to update the integer scheduling
17330 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17331 INSN earlier, reduce the priority to execute INSN later. Do not
17332 define this macro if you do not need to adjust the scheduling
17333 priorities of insns. */
17336 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17338 /* On machines (like the 750) which have asymmetric integer units,
17339 where one integer unit can do multiply and divides and the other
17340 can't, reduce the priority of multiply/divide so it is scheduled
17341 before other integer operations. */
17344 if (! INSN_P (insn))
17347 if (GET_CODE (PATTERN (insn)) == USE)
17350 switch (rs6000_cpu_attr) {
17352 switch (get_attr_type (insn))
17359 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17360 priority, priority);
17361 if (priority >= 0 && priority < 0x01000000)
17368 if (insn_must_be_first_in_group (insn)
17369 && reload_completed
17370 && current_sched_info->sched_max_insns_priority
17371 && rs6000_sched_restricted_insns_priority)
17374 /* Prioritize insns that can be dispatched only in the first
17376 if (rs6000_sched_restricted_insns_priority == 1)
17377 /* Attach highest priority to insn. This means that in
17378 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17379 precede 'priority' (critical path) considerations. */
17380 return current_sched_info->sched_max_insns_priority;
17381 else if (rs6000_sched_restricted_insns_priority == 2)
17382 /* Increase priority of insn by a minimal amount. This means that in
17383 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17384 considerations precede dispatch-slot restriction considerations. */
17385 return (priority + 1);
17388 if (rs6000_cpu == PROCESSOR_POWER6
17389 && ((load_store_pendulum == -2 && is_load_insn (insn))
17390 || (load_store_pendulum == 2 && is_store_insn (insn))))
17391 /* Attach highest priority to insn if the scheduler has just issued two
17392 stores and this instruction is a load, or two loads and this instruction
17393 is a store. Power6 wants loads and stores scheduled alternately
17395 return current_sched_info->sched_max_insns_priority;
17400 /* Return true if the instruction is nonpipelined on the Cell. */
17402 is_nonpipeline_insn (rtx insn)
17404 enum attr_type type;
17405 if (!insn || !INSN_P (insn)
17406 || GET_CODE (PATTERN (insn)) == USE
17407 || GET_CODE (PATTERN (insn)) == CLOBBER)
17410 type = get_attr_type (insn);
17411 if (type == TYPE_IMUL
17412 || type == TYPE_IMUL2
17413 || type == TYPE_IMUL3
17414 || type == TYPE_LMUL
17415 || type == TYPE_IDIV
17416 || type == TYPE_LDIV
17417 || type == TYPE_SDIV
17418 || type == TYPE_DDIV
17419 || type == TYPE_SSQRT
17420 || type == TYPE_DSQRT
17421 || type == TYPE_MFCR
17422 || type == TYPE_MFCRF
17423 || type == TYPE_MFJMPR)
17431 /* Return how many instructions the machine can issue per cycle. */
17434 rs6000_issue_rate (void)
17436 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17437 if (!reload_completed)
17440 switch (rs6000_cpu_attr) {
17441 case CPU_RIOS1: /* ? */
17443 case CPU_PPC601: /* ? */
17468 /* Return how many instructions to look ahead for better insn
17472 rs6000_use_sched_lookahead (void)
17474 if (rs6000_cpu_attr == CPU_PPC8540)
17476 if (rs6000_cpu_attr == CPU_CELL)
17477 return (reload_completed ? 8 : 0);
17481 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17483 rs6000_use_sched_lookahead_guard (rtx insn)
17485 if (rs6000_cpu_attr != CPU_CELL)
17488 if (insn == NULL_RTX || !INSN_P (insn))
17491 if (!reload_completed
17492 || is_nonpipeline_insn (insn)
17493 || is_microcoded_insn (insn))
17499 /* Determine is PAT refers to memory. */
17502 is_mem_ref (rtx pat)
17508 if (GET_CODE (pat) == MEM)
17511 /* Recursively process the pattern. */
17512 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17514 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17517 ret |= is_mem_ref (XEXP (pat, i));
17518 else if (fmt[i] == 'E')
17519 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17520 ret |= is_mem_ref (XVECEXP (pat, i, j));
17526 /* Determine if PAT is a PATTERN of a load insn. */
17529 is_load_insn1 (rtx pat)
17531 if (!pat || pat == NULL_RTX)
17534 if (GET_CODE (pat) == SET)
17535 return is_mem_ref (SET_SRC (pat));
17537 if (GET_CODE (pat) == PARALLEL)
17541 for (i = 0; i < XVECLEN (pat, 0); i++)
17542 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17549 /* Determine if INSN loads from memory. */
17552 is_load_insn (rtx insn)
17554 if (!insn || !INSN_P (insn))
17557 if (GET_CODE (insn) == CALL_INSN)
17560 return is_load_insn1 (PATTERN (insn));
17563 /* Determine if PAT is a PATTERN of a store insn. */
17566 is_store_insn1 (rtx pat)
17568 if (!pat || pat == NULL_RTX)
17571 if (GET_CODE (pat) == SET)
17572 return is_mem_ref (SET_DEST (pat));
17574 if (GET_CODE (pat) == PARALLEL)
17578 for (i = 0; i < XVECLEN (pat, 0); i++)
17579 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17586 /* Determine if INSN stores to memory. */
17589 is_store_insn (rtx insn)
17591 if (!insn || !INSN_P (insn))
17594 return is_store_insn1 (PATTERN (insn));
17597 /* Return the dest of a store insn. */
17600 get_store_dest (rtx pat)
17602 gcc_assert (is_store_insn1 (pat));
17604 if (GET_CODE (pat) == SET)
17605 return SET_DEST (pat);
17606 else if (GET_CODE (pat) == PARALLEL)
17610 for (i = 0; i < XVECLEN (pat, 0); i++)
17612 rtx inner_pat = XVECEXP (pat, 0, i);
17613 if (GET_CODE (inner_pat) == SET
17614 && is_mem_ref (SET_DEST (inner_pat)))
17618 /* We shouldn't get here, because we should have either a simple
17619 store insn or a store with update which are covered above. */
17623 /* Returns whether the dependence between INSN and NEXT is considered
17624 costly by the given target. */
17627 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17632 /* If the flag is not enabled - no dependence is considered costly;
17633 allow all dependent insns in the same group.
17634 This is the most aggressive option. */
17635 if (rs6000_sched_costly_dep == no_dep_costly)
17638 /* If the flag is set to 1 - a dependence is always considered costly;
17639 do not allow dependent instructions in the same group.
17640 This is the most conservative option. */
17641 if (rs6000_sched_costly_dep == all_deps_costly)
17644 insn = DEP_PRO (dep);
17645 next = DEP_CON (dep);
17647 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17648 && is_load_insn (next)
17649 && is_store_insn (insn))
17650 /* Prevent load after store in the same group. */
17653 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17654 && is_load_insn (next)
17655 && is_store_insn (insn)
17656 && DEP_KIND (dep) == REG_DEP_TRUE)
17657 /* Prevent load after store in the same group if it is a true
17661 /* The flag is set to X; dependences with latency >= X are considered costly,
17662 and will not be scheduled in the same group. */
17663 if (rs6000_sched_costly_dep <= max_dep_latency
17664 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17670 /* Return the next insn after INSN that is found before TAIL is reached,
17671 skipping any "non-active" insns - insns that will not actually occupy
17672 an issue slot. Return NULL_RTX if such an insn is not found. */
17675 get_next_active_insn (rtx insn, rtx tail)
17677 if (insn == NULL_RTX || insn == tail)
17682 insn = NEXT_INSN (insn);
17683 if (insn == NULL_RTX || insn == tail)
17688 || (NONJUMP_INSN_P (insn)
17689 && GET_CODE (PATTERN (insn)) != USE
17690 && GET_CODE (PATTERN (insn)) != CLOBBER
17691 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17697 /* We are about to begin issuing insns for this clock cycle. */
17700 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17701 rtx *ready ATTRIBUTE_UNUSED,
17702 int *pn_ready ATTRIBUTE_UNUSED,
17703 int clock_var ATTRIBUTE_UNUSED)
17705 int n_ready = *pn_ready;
17708 fprintf (dump, "// rs6000_sched_reorder :\n");
17710 /* Reorder the ready list, if the second to last ready insn
17711 is a nonepipeline insn. */
17712 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17714 if (is_nonpipeline_insn (ready[n_ready - 1])
17715 && (recog_memoized (ready[n_ready - 2]) > 0))
17716 /* Simply swap first two insns. */
17718 rtx tmp = ready[n_ready - 1];
17719 ready[n_ready - 1] = ready[n_ready - 2];
17720 ready[n_ready - 2] = tmp;
17724 if (rs6000_cpu == PROCESSOR_POWER6)
17725 load_store_pendulum = 0;
17727 return rs6000_issue_rate ();
17730 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17733 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17734 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17737 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17739 /* For Power6, we need to handle some special cases to try and keep the
17740 store queue from overflowing and triggering expensive flushes.
17742 This code monitors how load and store instructions are being issued
17743 and skews the ready list one way or the other to increase the likelihood
17744 that a desired instruction is issued at the proper time.
17746 A couple of things are done. First, we maintain a "load_store_pendulum"
17747 to track the current state of load/store issue.
17749 - If the pendulum is at zero, then no loads or stores have been
17750 issued in the current cycle so we do nothing.
17752 - If the pendulum is 1, then a single load has been issued in this
17753 cycle and we attempt to locate another load in the ready list to
17756 - If the pendulum is -2, then two stores have already been
17757 issued in this cycle, so we increase the priority of the first load
17758 in the ready list to increase it's likelihood of being chosen first
17761 - If the pendulum is -1, then a single store has been issued in this
17762 cycle and we attempt to locate another store in the ready list to
17763 issue with it, preferring a store to an adjacent memory location to
17764 facilitate store pairing in the store queue.
17766 - If the pendulum is 2, then two loads have already been
17767 issued in this cycle, so we increase the priority of the first store
17768 in the ready list to increase it's likelihood of being chosen first
17771 - If the pendulum < -2 or > 2, then do nothing.
17773 Note: This code covers the most common scenarios. There exist non
17774 load/store instructions which make use of the LSU and which
17775 would need to be accounted for to strictly model the behavior
17776 of the machine. Those instructions are currently unaccounted
17777 for to help minimize compile time overhead of this code.
17779 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17785 if (is_store_insn (last_scheduled_insn))
17786 /* Issuing a store, swing the load_store_pendulum to the left */
17787 load_store_pendulum--;
17788 else if (is_load_insn (last_scheduled_insn))
17789 /* Issuing a load, swing the load_store_pendulum to the right */
17790 load_store_pendulum++;
17792 return cached_can_issue_more;
17794 /* If the pendulum is balanced, or there is only one instruction on
17795 the ready list, then all is well, so return. */
17796 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17797 return cached_can_issue_more;
17799 if (load_store_pendulum == 1)
17801 /* A load has been issued in this cycle. Scan the ready list
17802 for another load to issue with it */
17807 if (is_load_insn (ready[pos]))
17809 /* Found a load. Move it to the head of the ready list,
17810 and adjust it's priority so that it is more likely to
17813 for (i=pos; i<*pn_ready-1; i++)
17814 ready[i] = ready[i + 1];
17815 ready[*pn_ready-1] = tmp;
17816 if INSN_PRIORITY_KNOWN (tmp)
17817 INSN_PRIORITY (tmp)++;
17823 else if (load_store_pendulum == -2)
17825 /* Two stores have been issued in this cycle. Increase the
17826 priority of the first load in the ready list to favor it for
17827 issuing in the next cycle. */
17832 if (is_load_insn (ready[pos])
17833 && INSN_PRIORITY_KNOWN (ready[pos]))
17835 INSN_PRIORITY (ready[pos])++;
17837 /* Adjust the pendulum to account for the fact that a load
17838 was found and increased in priority. This is to prevent
17839 increasing the priority of multiple loads */
17840 load_store_pendulum--;
17847 else if (load_store_pendulum == -1)
17849 /* A store has been issued in this cycle. Scan the ready list for
17850 another store to issue with it, preferring a store to an adjacent
17852 int first_store_pos = -1;
17858 if (is_store_insn (ready[pos]))
17860 /* Maintain the index of the first store found on the
17862 if (first_store_pos == -1)
17863 first_store_pos = pos;
17865 if (is_store_insn (last_scheduled_insn)
17866 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
17868 /* Found an adjacent store. Move it to the head of the
17869 ready list, and adjust it's priority so that it is
17870 more likely to stay there */
17872 for (i=pos; i<*pn_ready-1; i++)
17873 ready[i] = ready[i + 1];
17874 ready[*pn_ready-1] = tmp;
17875 if INSN_PRIORITY_KNOWN (tmp)
17876 INSN_PRIORITY (tmp)++;
17877 first_store_pos = -1;
17885 if (first_store_pos >= 0)
17887 /* An adjacent store wasn't found, but a non-adjacent store was,
17888 so move the non-adjacent store to the front of the ready
17889 list, and adjust its priority so that it is more likely to
17891 tmp = ready[first_store_pos];
17892 for (i=first_store_pos; i<*pn_ready-1; i++)
17893 ready[i] = ready[i + 1];
17894 ready[*pn_ready-1] = tmp;
17895 if INSN_PRIORITY_KNOWN (tmp)
17896 INSN_PRIORITY (tmp)++;
17899 else if (load_store_pendulum == 2)
17901 /* Two loads have been issued in this cycle. Increase the priority
17902 of the first store in the ready list to favor it for issuing in
17908 if (is_store_insn (ready[pos])
17909 && INSN_PRIORITY_KNOWN (ready[pos]))
17911 INSN_PRIORITY (ready[pos])++;
17913 /* Adjust the pendulum to account for the fact that a store
17914 was found and increased in priority. This is to prevent
17915 increasing the priority of multiple stores */
17916 load_store_pendulum++;
17925 return cached_can_issue_more;
17928 /* Return whether the presence of INSN causes a dispatch group termination
17929 of group WHICH_GROUP.
17931 If WHICH_GROUP == current_group, this function will return true if INSN
17932 causes the termination of the current group (i.e, the dispatch group to
17933 which INSN belongs). This means that INSN will be the last insn in the
17934 group it belongs to.
17936 If WHICH_GROUP == previous_group, this function will return true if INSN
17937 causes the termination of the previous group (i.e, the dispatch group that
17938 precedes the group to which INSN belongs). This means that INSN will be
17939 the first insn in the group it belongs to). */
17942 insn_terminates_group_p (rtx insn, enum group_termination which_group)
17949 first = insn_must_be_first_in_group (insn);
17950 last = insn_must_be_last_in_group (insn);
17955 if (which_group == current_group)
17957 else if (which_group == previous_group)
17965 insn_must_be_first_in_group (rtx insn)
17967 enum attr_type type;
17970 || insn == NULL_RTX
17971 || GET_CODE (insn) == NOTE
17972 || GET_CODE (PATTERN (insn)) == USE
17973 || GET_CODE (PATTERN (insn)) == CLOBBER)
17976 switch (rs6000_cpu)
17978 case PROCESSOR_POWER5:
17979 if (is_cracked_insn (insn))
17981 case PROCESSOR_POWER4:
17982 if (is_microcoded_insn (insn))
17985 if (!rs6000_sched_groups)
17988 type = get_attr_type (insn);
17995 case TYPE_DELAYED_CR:
17996 case TYPE_CR_LOGICAL:
18010 case PROCESSOR_POWER6:
18011 type = get_attr_type (insn);
18015 case TYPE_INSERT_DWORD:
18019 case TYPE_VAR_SHIFT_ROTATE:
18026 case TYPE_INSERT_WORD:
18027 case TYPE_DELAYED_COMPARE:
18028 case TYPE_IMUL_COMPARE:
18029 case TYPE_LMUL_COMPARE:
18030 case TYPE_FPCOMPARE:
18041 case TYPE_LOAD_EXT_UX:
18043 case TYPE_STORE_UX:
18044 case TYPE_FPLOAD_U:
18045 case TYPE_FPLOAD_UX:
18046 case TYPE_FPSTORE_U:
18047 case TYPE_FPSTORE_UX:
18061 insn_must_be_last_in_group (rtx insn)
18063 enum attr_type type;
18066 || insn == NULL_RTX
18067 || GET_CODE (insn) == NOTE
18068 || GET_CODE (PATTERN (insn)) == USE
18069 || GET_CODE (PATTERN (insn)) == CLOBBER)
18072 switch (rs6000_cpu) {
18073 case PROCESSOR_POWER4:
18074 case PROCESSOR_POWER5:
18075 if (is_microcoded_insn (insn))
18078 if (is_branch_slot_insn (insn))
18082 case PROCESSOR_POWER6:
18083 type = get_attr_type (insn);
18090 case TYPE_VAR_SHIFT_ROTATE:
18097 case TYPE_DELAYED_COMPARE:
18098 case TYPE_IMUL_COMPARE:
18099 case TYPE_LMUL_COMPARE:
18100 case TYPE_FPCOMPARE:
18121 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18122 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18125 is_costly_group (rtx *group_insns, rtx next_insn)
18128 int issue_rate = rs6000_issue_rate ();
18130 for (i = 0; i < issue_rate; i++)
18133 rtx insn = group_insns[i];
18138 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18140 dep_t dep = DEP_LINK_DEP (link);
18141 rtx next = DEP_CON (dep);
18143 if (next == next_insn
18144 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18152 /* Utility of the function redefine_groups.
18153 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18154 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18155 to keep it "far" (in a separate group) from GROUP_INSNS, following
18156 one of the following schemes, depending on the value of the flag
18157 -minsert_sched_nops = X:
18158 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18159 in order to force NEXT_INSN into a separate group.
18160 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18161 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18162 insertion (has a group just ended, how many vacant issue slots remain in the
18163 last group, and how many dispatch groups were encountered so far). */
18166 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18167 rtx next_insn, bool *group_end, int can_issue_more,
18172 int issue_rate = rs6000_issue_rate ();
18173 bool end = *group_end;
18176 if (next_insn == NULL_RTX)
18177 return can_issue_more;
18179 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18180 return can_issue_more;
18182 force = is_costly_group (group_insns, next_insn);
18184 return can_issue_more;
18186 if (sched_verbose > 6)
18187 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18188 *group_count ,can_issue_more);
18190 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18193 can_issue_more = 0;
18195 /* Since only a branch can be issued in the last issue_slot, it is
18196 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18197 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18198 in this case the last nop will start a new group and the branch
18199 will be forced to the new group. */
18200 if (can_issue_more && !is_branch_slot_insn (next_insn))
18203 while (can_issue_more > 0)
18206 emit_insn_before (nop, next_insn);
18214 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18216 int n_nops = rs6000_sched_insert_nops;
18218 /* Nops can't be issued from the branch slot, so the effective
18219 issue_rate for nops is 'issue_rate - 1'. */
18220 if (can_issue_more == 0)
18221 can_issue_more = issue_rate;
18223 if (can_issue_more == 0)
18225 can_issue_more = issue_rate - 1;
18228 for (i = 0; i < issue_rate; i++)
18230 group_insns[i] = 0;
18237 emit_insn_before (nop, next_insn);
18238 if (can_issue_more == issue_rate - 1) /* new group begins */
18241 if (can_issue_more == 0)
18243 can_issue_more = issue_rate - 1;
18246 for (i = 0; i < issue_rate; i++)
18248 group_insns[i] = 0;
18254 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18257 /* Is next_insn going to start a new group? */
18260 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18261 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18262 || (can_issue_more < issue_rate &&
18263 insn_terminates_group_p (next_insn, previous_group)));
18264 if (*group_end && end)
18267 if (sched_verbose > 6)
18268 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18269 *group_count, can_issue_more);
18270 return can_issue_more;
18273 return can_issue_more;
18276 /* This function tries to synch the dispatch groups that the compiler "sees"
18277 with the dispatch groups that the processor dispatcher is expected to
18278 form in practice. It tries to achieve this synchronization by forcing the
18279 estimated processor grouping on the compiler (as opposed to the function
18280 'pad_goups' which tries to force the scheduler's grouping on the processor).
18282 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18283 examines the (estimated) dispatch groups that will be formed by the processor
18284 dispatcher. It marks these group boundaries to reflect the estimated
18285 processor grouping, overriding the grouping that the scheduler had marked.
18286 Depending on the value of the flag '-minsert-sched-nops' this function can
18287 force certain insns into separate groups or force a certain distance between
18288 them by inserting nops, for example, if there exists a "costly dependence"
18291 The function estimates the group boundaries that the processor will form as
18292 follows: It keeps track of how many vacant issue slots are available after
18293 each insn. A subsequent insn will start a new group if one of the following
18295 - no more vacant issue slots remain in the current dispatch group.
18296 - only the last issue slot, which is the branch slot, is vacant, but the next
18297 insn is not a branch.
18298 - only the last 2 or less issue slots, including the branch slot, are vacant,
18299 which means that a cracked insn (which occupies two issue slots) can't be
18300 issued in this group.
18301 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18302 start a new group. */
18305 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18307 rtx insn, next_insn;
18309 int can_issue_more;
18312 int group_count = 0;
18316 issue_rate = rs6000_issue_rate ();
18317 group_insns = alloca (issue_rate * sizeof (rtx));
18318 for (i = 0; i < issue_rate; i++)
18320 group_insns[i] = 0;
18322 can_issue_more = issue_rate;
18324 insn = get_next_active_insn (prev_head_insn, tail);
18327 while (insn != NULL_RTX)
18329 slot = (issue_rate - can_issue_more);
18330 group_insns[slot] = insn;
18332 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18333 if (insn_terminates_group_p (insn, current_group))
18334 can_issue_more = 0;
18336 next_insn = get_next_active_insn (insn, tail);
18337 if (next_insn == NULL_RTX)
18338 return group_count + 1;
18340 /* Is next_insn going to start a new group? */
18342 = (can_issue_more == 0
18343 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18344 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18345 || (can_issue_more < issue_rate &&
18346 insn_terminates_group_p (next_insn, previous_group)));
18348 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18349 next_insn, &group_end, can_issue_more,
18355 can_issue_more = 0;
18356 for (i = 0; i < issue_rate; i++)
18358 group_insns[i] = 0;
18362 if (GET_MODE (next_insn) == TImode && can_issue_more)
18363 PUT_MODE (next_insn, VOIDmode);
18364 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18365 PUT_MODE (next_insn, TImode);
18368 if (can_issue_more == 0)
18369 can_issue_more = issue_rate;
18372 return group_count;
18375 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18376 dispatch group boundaries that the scheduler had marked. Pad with nops
18377 any dispatch groups which have vacant issue slots, in order to force the
18378 scheduler's grouping on the processor dispatcher. The function
18379 returns the number of dispatch groups found. */
18382 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18384 rtx insn, next_insn;
18387 int can_issue_more;
18389 int group_count = 0;
18391 /* Initialize issue_rate. */
18392 issue_rate = rs6000_issue_rate ();
18393 can_issue_more = issue_rate;
18395 insn = get_next_active_insn (prev_head_insn, tail);
18396 next_insn = get_next_active_insn (insn, tail);
18398 while (insn != NULL_RTX)
18401 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18403 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18405 if (next_insn == NULL_RTX)
18410 /* If the scheduler had marked group termination at this location
18411 (between insn and next_indn), and neither insn nor next_insn will
18412 force group termination, pad the group with nops to force group
18415 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18416 && !insn_terminates_group_p (insn, current_group)
18417 && !insn_terminates_group_p (next_insn, previous_group))
18419 if (!is_branch_slot_insn (next_insn))
18422 while (can_issue_more)
18425 emit_insn_before (nop, next_insn);
18430 can_issue_more = issue_rate;
18435 next_insn = get_next_active_insn (insn, tail);
18438 return group_count;
18441 /* We're beginning a new block. Initialize data structures as necessary. */
18444 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18445 int sched_verbose ATTRIBUTE_UNUSED,
18446 int max_ready ATTRIBUTE_UNUSED)
18448 last_scheduled_insn = NULL_RTX;
18449 load_store_pendulum = 0;
18452 /* The following function is called at the end of scheduling BB.
18453 After reload, it inserts nops at insn group bundling. */
18456 rs6000_sched_finish (FILE *dump, int sched_verbose)
18461 fprintf (dump, "=== Finishing schedule.\n");
18463 if (reload_completed && rs6000_sched_groups)
18465 if (rs6000_sched_insert_nops == sched_finish_none)
18468 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18469 n_groups = pad_groups (dump, sched_verbose,
18470 current_sched_info->prev_head,
18471 current_sched_info->next_tail);
18473 n_groups = redefine_groups (dump, sched_verbose,
18474 current_sched_info->prev_head,
18475 current_sched_info->next_tail);
18477 if (sched_verbose >= 6)
18479 fprintf (dump, "ngroups = %d\n", n_groups);
18480 print_rtl (dump, current_sched_info->prev_head);
18481 fprintf (dump, "Done finish_sched\n");
18486 /* Length in units of the trampoline for entering a nested function. */
18489 rs6000_trampoline_size (void)
18493 switch (DEFAULT_ABI)
18496 gcc_unreachable ();
18499 ret = (TARGET_32BIT) ? 12 : 24;
18504 ret = (TARGET_32BIT) ? 40 : 48;
18511 /* Emit RTL insns to initialize the variable parts of a trampoline.
18512 FNADDR is an RTX for the address of the function's pure code.
18513 CXT is an RTX for the static chain value for the function. */
18516 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18518 int regsize = (TARGET_32BIT) ? 4 : 8;
18519 rtx ctx_reg = force_reg (Pmode, cxt);
18521 switch (DEFAULT_ABI)
18524 gcc_unreachable ();
18526 /* Macros to shorten the code expansions below. */
18527 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18528 #define MEM_PLUS(addr,offset) \
18529 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18531 /* Under AIX, just build the 3 word function descriptor */
18534 rtx fn_reg = gen_reg_rtx (Pmode);
18535 rtx toc_reg = gen_reg_rtx (Pmode);
18536 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18537 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18538 emit_move_insn (MEM_DEREF (addr), fn_reg);
18539 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18540 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18544 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18547 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18548 FALSE, VOIDmode, 4,
18550 GEN_INT (rs6000_trampoline_size ()), SImode,
18560 /* Table of valid machine attributes. */
18562 const struct attribute_spec rs6000_attribute_table[] =
18564 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18565 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18566 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18567 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18568 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18569 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18570 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18571 SUBTARGET_ATTRIBUTE_TABLE,
18573 { NULL, 0, 0, false, false, false, NULL }
18576 /* Handle the "altivec" attribute. The attribute may have
18577 arguments as follows:
18579 __attribute__((altivec(vector__)))
18580 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18581 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18583 and may appear more than once (e.g., 'vector bool char') in a
18584 given declaration. */
18587 rs6000_handle_altivec_attribute (tree *node,
18588 tree name ATTRIBUTE_UNUSED,
18590 int flags ATTRIBUTE_UNUSED,
18591 bool *no_add_attrs)
18593 tree type = *node, result = NULL_TREE;
18594 enum machine_mode mode;
18597 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18598 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18599 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18602 while (POINTER_TYPE_P (type)
18603 || TREE_CODE (type) == FUNCTION_TYPE
18604 || TREE_CODE (type) == METHOD_TYPE
18605 || TREE_CODE (type) == ARRAY_TYPE)
18606 type = TREE_TYPE (type);
18608 mode = TYPE_MODE (type);
18610 /* Check for invalid AltiVec type qualifiers. */
18611 if (type == long_unsigned_type_node || type == long_integer_type_node)
18614 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18615 else if (rs6000_warn_altivec_long)
18616 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18618 else if (type == long_long_unsigned_type_node
18619 || type == long_long_integer_type_node)
18620 error ("use of %<long long%> in AltiVec types is invalid");
18621 else if (type == double_type_node)
18622 error ("use of %<double%> in AltiVec types is invalid");
18623 else if (type == long_double_type_node)
18624 error ("use of %<long double%> in AltiVec types is invalid");
18625 else if (type == boolean_type_node)
18626 error ("use of boolean types in AltiVec types is invalid");
18627 else if (TREE_CODE (type) == COMPLEX_TYPE)
18628 error ("use of %<complex%> in AltiVec types is invalid");
18629 else if (DECIMAL_FLOAT_MODE_P (mode))
18630 error ("use of decimal floating point types in AltiVec types is invalid");
18632 switch (altivec_type)
18635 unsigned_p = TYPE_UNSIGNED (type);
18639 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18642 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18645 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18647 case SFmode: result = V4SF_type_node; break;
18648 /* If the user says 'vector int bool', we may be handed the 'bool'
18649 attribute _before_ the 'vector' attribute, and so select the
18650 proper type in the 'b' case below. */
18651 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18659 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18660 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18661 case QImode: case V16QImode: result = bool_V16QI_type_node;
18668 case V8HImode: result = pixel_V8HI_type_node;
18674 if (result && result != type && TYPE_READONLY (type))
18675 result = build_qualified_type (result, TYPE_QUAL_CONST);
18677 *no_add_attrs = true; /* No need to hang on to the attribute. */
18680 *node = reconstruct_complex_type (*node, result);
18685 /* AltiVec defines four built-in scalar types that serve as vector
18686 elements; we must teach the compiler how to mangle them. */
18688 static const char *
18689 rs6000_mangle_fundamental_type (tree type)
18691 if (type == bool_char_type_node) return "U6__boolc";
18692 if (type == bool_short_type_node) return "U6__bools";
18693 if (type == pixel_type_node) return "u7__pixel";
18694 if (type == bool_int_type_node) return "U6__booli";
18696 /* Mangle IBM extended float long double as `g' (__float128) on
18697 powerpc*-linux where long-double-64 previously was the default. */
18698 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18700 && TARGET_LONG_DOUBLE_128
18701 && !TARGET_IEEEQUAD)
18704 /* For all other types, use normal C++ mangling. */
18708 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18709 struct attribute_spec.handler. */
18712 rs6000_handle_longcall_attribute (tree *node, tree name,
18713 tree args ATTRIBUTE_UNUSED,
18714 int flags ATTRIBUTE_UNUSED,
18715 bool *no_add_attrs)
18717 if (TREE_CODE (*node) != FUNCTION_TYPE
18718 && TREE_CODE (*node) != FIELD_DECL
18719 && TREE_CODE (*node) != TYPE_DECL)
18721 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18722 IDENTIFIER_POINTER (name));
18723 *no_add_attrs = true;
18729 /* Set longcall attributes on all functions declared when
18730 rs6000_default_long_calls is true. */
18732 rs6000_set_default_type_attributes (tree type)
18734 if (rs6000_default_long_calls
18735 && (TREE_CODE (type) == FUNCTION_TYPE
18736 || TREE_CODE (type) == METHOD_TYPE))
18737 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18739 TYPE_ATTRIBUTES (type));
18742 darwin_set_default_type_attributes (type);
18746 /* Return a reference suitable for calling a function with the
18747 longcall attribute. */
18750 rs6000_longcall_ref (rtx call_ref)
18752 const char *call_name;
18755 if (GET_CODE (call_ref) != SYMBOL_REF)
18758 /* System V adds '.' to the internal name, so skip them. */
18759 call_name = XSTR (call_ref, 0);
18760 if (*call_name == '.')
18762 while (*call_name == '.')
18765 node = get_identifier (call_name);
18766 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18769 return force_reg (Pmode, call_ref);
18772 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18773 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18776 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18777 struct attribute_spec.handler. */
18779 rs6000_handle_struct_attribute (tree *node, tree name,
18780 tree args ATTRIBUTE_UNUSED,
18781 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18784 if (DECL_P (*node))
18786 if (TREE_CODE (*node) == TYPE_DECL)
18787 type = &TREE_TYPE (*node);
18792 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18793 || TREE_CODE (*type) == UNION_TYPE)))
18795 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18796 *no_add_attrs = true;
18799 else if ((is_attribute_p ("ms_struct", name)
18800 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18801 || ((is_attribute_p ("gcc_struct", name)
18802 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18804 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18805 IDENTIFIER_POINTER (name));
18806 *no_add_attrs = true;
18813 rs6000_ms_bitfield_layout_p (tree record_type)
18815 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
18816 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18817 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18820 #ifdef USING_ELFOS_H
18822 /* A get_unnamed_section callback, used for switching to toc_section. */
18825 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18827 if (DEFAULT_ABI == ABI_AIX
18828 && TARGET_MINIMAL_TOC
18829 && !TARGET_RELOCATABLE)
18831 if (!toc_initialized)
18833 toc_initialized = 1;
18834 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18835 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
18836 fprintf (asm_out_file, "\t.tc ");
18837 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
18838 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18839 fprintf (asm_out_file, "\n");
18841 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18842 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18843 fprintf (asm_out_file, " = .+32768\n");
18846 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18848 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
18849 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18852 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18853 if (!toc_initialized)
18855 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18856 fprintf (asm_out_file, " = .+32768\n");
18857 toc_initialized = 1;
18862 /* Implement TARGET_ASM_INIT_SECTIONS. */
18865 rs6000_elf_asm_init_sections (void)
18868 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
18871 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
18872 SDATA2_SECTION_ASM_OP);
18875 /* Implement TARGET_SELECT_RTX_SECTION. */
18878 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
18879 unsigned HOST_WIDE_INT align)
18881 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18882 return toc_section;
18884 return default_elf_select_rtx_section (mode, x, align);
18887 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
18890 rs6000_elf_select_section (tree decl, int reloc,
18891 unsigned HOST_WIDE_INT align)
18893 /* Pretend that we're always building for a shared library when
18894 ABI_AIX, because otherwise we end up with dynamic relocations
18895 in read-only sections. This happens for function pointers,
18896 references to vtables in typeinfo, and probably other cases. */
18897 return default_elf_select_section_1 (decl, reloc, align,
18898 flag_pic || DEFAULT_ABI == ABI_AIX);
18901 /* A C statement to build up a unique section name, expressed as a
18902 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
18903 RELOC indicates whether the initial value of EXP requires
18904 link-time relocations. If you do not define this macro, GCC will use
18905 the symbol name prefixed by `.' as the section name. Note - this
18906 macro can now be called for uninitialized data items as well as
18907 initialized data and functions. */
18910 rs6000_elf_unique_section (tree decl, int reloc)
18912 /* As above, pretend that we're always building for a shared library
18913 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
18914 default_unique_section_1 (decl, reloc,
18915 flag_pic || DEFAULT_ABI == ABI_AIX);
18918 /* For a SYMBOL_REF, set generic flags and then perform some
18919 target-specific processing.
18921 When the AIX ABI is requested on a non-AIX system, replace the
18922 function name with the real name (with a leading .) rather than the
18923 function descriptor name. This saves a lot of overriding code to
18924 read the prefixes. */
18927 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
18929 default_encode_section_info (decl, rtl, first);
18932 && TREE_CODE (decl) == FUNCTION_DECL
18934 && DEFAULT_ABI == ABI_AIX)
18936 rtx sym_ref = XEXP (rtl, 0);
18937 size_t len = strlen (XSTR (sym_ref, 0));
18938 char *str = alloca (len + 2);
18940 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
18941 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
18946 rs6000_elf_in_small_data_p (tree decl)
18948 if (rs6000_sdata == SDATA_NONE)
18951 /* We want to merge strings, so we never consider them small data. */
18952 if (TREE_CODE (decl) == STRING_CST)
18955 /* Functions are never in the small data area. */
18956 if (TREE_CODE (decl) == FUNCTION_DECL)
18959 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
18961 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
18962 if (strcmp (section, ".sdata") == 0
18963 || strcmp (section, ".sdata2") == 0
18964 || strcmp (section, ".sbss") == 0
18965 || strcmp (section, ".sbss2") == 0
18966 || strcmp (section, ".PPC.EMB.sdata0") == 0
18967 || strcmp (section, ".PPC.EMB.sbss0") == 0)
18972 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
18975 && (unsigned HOST_WIDE_INT) size <= g_switch_value
18976 /* If it's not public, and we're not going to reference it there,
18977 there's no need to put it in the small data section. */
18978 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
18985 #endif /* USING_ELFOS_H */
18987 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
18990 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
18992 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
18995 /* Return a REG that occurs in ADDR with coefficient 1.
18996 ADDR can be effectively incremented by incrementing REG.
18998 r0 is special and we must not select it as an address
18999 register by this routine since our caller will try to
19000 increment the returned register via an "la" instruction. */
19003 find_addr_reg (rtx addr)
19005 while (GET_CODE (addr) == PLUS)
19007 if (GET_CODE (XEXP (addr, 0)) == REG
19008 && REGNO (XEXP (addr, 0)) != 0)
19009 addr = XEXP (addr, 0);
19010 else if (GET_CODE (XEXP (addr, 1)) == REG
19011 && REGNO (XEXP (addr, 1)) != 0)
19012 addr = XEXP (addr, 1);
19013 else if (CONSTANT_P (XEXP (addr, 0)))
19014 addr = XEXP (addr, 1);
19015 else if (CONSTANT_P (XEXP (addr, 1)))
19016 addr = XEXP (addr, 0);
19018 gcc_unreachable ();
19020 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19025 rs6000_fatal_bad_address (rtx op)
19027 fatal_insn ("bad address", op);
19032 static tree branch_island_list = 0;
19034 /* Remember to generate a branch island for far calls to the given
19038 add_compiler_branch_island (tree label_name, tree function_name,
19041 tree branch_island = build_tree_list (function_name, label_name);
19042 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19043 TREE_CHAIN (branch_island) = branch_island_list;
19044 branch_island_list = branch_island;
19047 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19048 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19049 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19050 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19052 /* Generate far-jump branch islands for everything on the
19053 branch_island_list. Invoked immediately after the last instruction
19054 of the epilogue has been emitted; the branch-islands must be
19055 appended to, and contiguous with, the function body. Mach-O stubs
19056 are generated in machopic_output_stub(). */
19059 macho_branch_islands (void)
19062 tree branch_island;
19064 for (branch_island = branch_island_list;
19066 branch_island = TREE_CHAIN (branch_island))
19068 const char *label =
19069 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19071 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19072 char name_buf[512];
19073 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19074 if (name[0] == '*' || name[0] == '&')
19075 strcpy (name_buf, name+1);
19079 strcpy (name_buf+1, name);
19081 strcpy (tmp_buf, "\n");
19082 strcat (tmp_buf, label);
19083 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19084 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19085 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19086 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19089 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19090 strcat (tmp_buf, label);
19091 strcat (tmp_buf, "_pic\n");
19092 strcat (tmp_buf, label);
19093 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19095 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19096 strcat (tmp_buf, name_buf);
19097 strcat (tmp_buf, " - ");
19098 strcat (tmp_buf, label);
19099 strcat (tmp_buf, "_pic)\n");
19101 strcat (tmp_buf, "\tmtlr r0\n");
19103 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19104 strcat (tmp_buf, name_buf);
19105 strcat (tmp_buf, " - ");
19106 strcat (tmp_buf, label);
19107 strcat (tmp_buf, "_pic)\n");
19109 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19113 strcat (tmp_buf, ":\nlis r12,hi16(");
19114 strcat (tmp_buf, name_buf);
19115 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19116 strcat (tmp_buf, name_buf);
19117 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19119 output_asm_insn (tmp_buf, 0);
19120 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19121 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19122 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19123 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19126 branch_island_list = 0;
19129 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19130 already there or not. */
19133 no_previous_def (tree function_name)
19135 tree branch_island;
19136 for (branch_island = branch_island_list;
19138 branch_island = TREE_CHAIN (branch_island))
19139 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19144 /* GET_PREV_LABEL gets the label name from the previous definition of
19148 get_prev_label (tree function_name)
19150 tree branch_island;
19151 for (branch_island = branch_island_list;
19153 branch_island = TREE_CHAIN (branch_island))
19154 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19155 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19159 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19160 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19163 /* KEXTs still need branch islands. */
19164 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19165 || flag_mkernel || flag_apple_kext)
19167 /* INSN is either a function call or a millicode call. It may have an
19168 unconditional jump in its delay slot.
19170 CALL_DEST is the routine we are calling. */
19173 output_call (rtx insn, rtx *operands, int dest_operand_number,
19174 int cookie_operand_number)
19176 static char buf[256];
19177 if (DARWIN_GENERATE_ISLANDS
19178 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19179 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19182 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19184 if (no_previous_def (funname))
19186 int line_number = 0;
19187 rtx label_rtx = gen_label_rtx ();
19188 char *label_buf, temp_buf[256];
19189 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19190 CODE_LABEL_NUMBER (label_rtx));
19191 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19192 labelname = get_identifier (label_buf);
19193 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
19195 line_number = NOTE_LINE_NUMBER (insn);
19196 add_compiler_branch_island (labelname, funname, line_number);
19199 labelname = get_prev_label (funname);
19201 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19202 instruction will reach 'foo', otherwise link as 'bl L42'".
19203 "L42" should be a 'branch island', that will do a far jump to
19204 'foo'. Branch islands are generated in
19205 macho_branch_islands(). */
19206 sprintf (buf, "jbsr %%z%d,%.246s",
19207 dest_operand_number, IDENTIFIER_POINTER (labelname));
19210 sprintf (buf, "bl %%z%d", dest_operand_number);
19214 /* Generate PIC and indirect symbol stubs. */
19217 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19219 unsigned int length;
19220 char *symbol_name, *lazy_ptr_name;
19221 char *local_label_0;
19222 static int label = 0;
19224 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19225 symb = (*targetm.strip_name_encoding) (symb);
19228 length = strlen (symb);
19229 symbol_name = alloca (length + 32);
19230 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19232 lazy_ptr_name = alloca (length + 32);
19233 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19236 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19238 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19242 fprintf (file, "\t.align 5\n");
19244 fprintf (file, "%s:\n", stub);
19245 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19248 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19249 sprintf (local_label_0, "\"L%011d$spb\"", label);
19251 fprintf (file, "\tmflr r0\n");
19252 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19253 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19254 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19255 lazy_ptr_name, local_label_0);
19256 fprintf (file, "\tmtlr r0\n");
19257 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19258 (TARGET_64BIT ? "ldu" : "lwzu"),
19259 lazy_ptr_name, local_label_0);
19260 fprintf (file, "\tmtctr r12\n");
19261 fprintf (file, "\tbctr\n");
19265 fprintf (file, "\t.align 4\n");
19267 fprintf (file, "%s:\n", stub);
19268 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19270 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19271 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19272 (TARGET_64BIT ? "ldu" : "lwzu"),
19274 fprintf (file, "\tmtctr r12\n");
19275 fprintf (file, "\tbctr\n");
19278 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19279 fprintf (file, "%s:\n", lazy_ptr_name);
19280 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19281 fprintf (file, "%sdyld_stub_binding_helper\n",
19282 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19285 /* Legitimize PIC addresses. If the address is already
19286 position-independent, we return ORIG. Newly generated
19287 position-independent addresses go into a reg. This is REG if non
19288 zero, otherwise we allocate register(s) as necessary. */
19290 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19293 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19298 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19299 reg = gen_reg_rtx (Pmode);
19301 if (GET_CODE (orig) == CONST)
19305 if (GET_CODE (XEXP (orig, 0)) == PLUS
19306 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19309 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19311 /* Use a different reg for the intermediate value, as
19312 it will be marked UNCHANGING. */
19313 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
19314 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19317 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19320 if (GET_CODE (offset) == CONST_INT)
19322 if (SMALL_INT (offset))
19323 return plus_constant (base, INTVAL (offset));
19324 else if (! reload_in_progress && ! reload_completed)
19325 offset = force_reg (Pmode, offset);
19328 rtx mem = force_const_mem (Pmode, orig);
19329 return machopic_legitimize_pic_address (mem, Pmode, reg);
19332 return gen_rtx_PLUS (Pmode, base, offset);
19335 /* Fall back on generic machopic code. */
19336 return machopic_legitimize_pic_address (orig, mode, reg);
19339 /* Output a .machine directive for the Darwin assembler, and call
19340 the generic start_file routine. */
19343 rs6000_darwin_file_start (void)
19345 static const struct
19351 { "ppc64", "ppc64", MASK_64BIT },
19352 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19353 { "power4", "ppc970", 0 },
19354 { "G5", "ppc970", 0 },
19355 { "7450", "ppc7450", 0 },
19356 { "7400", "ppc7400", MASK_ALTIVEC },
19357 { "G4", "ppc7400", 0 },
19358 { "750", "ppc750", 0 },
19359 { "740", "ppc750", 0 },
19360 { "G3", "ppc750", 0 },
19361 { "604e", "ppc604e", 0 },
19362 { "604", "ppc604", 0 },
19363 { "603e", "ppc603", 0 },
19364 { "603", "ppc603", 0 },
19365 { "601", "ppc601", 0 },
19366 { NULL, "ppc", 0 } };
19367 const char *cpu_id = "";
19370 rs6000_file_start ();
19371 darwin_file_start ();
19373 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19374 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19375 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19376 && rs6000_select[i].string[0] != '\0')
19377 cpu_id = rs6000_select[i].string;
19379 /* Look through the mapping array. Pick the first name that either
19380 matches the argument, has a bit set in IF_SET that is also set
19381 in the target flags, or has a NULL name. */
19384 while (mapping[i].arg != NULL
19385 && strcmp (mapping[i].arg, cpu_id) != 0
19386 && (mapping[i].if_set & target_flags) == 0)
19389 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19392 #endif /* TARGET_MACHO */
19395 static unsigned int
19396 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
19398 return default_section_type_flags_1 (decl, name, reloc,
19399 flag_pic || DEFAULT_ABI == ABI_AIX);
19402 /* Record an element in the table of global constructors. SYMBOL is
19403 a SYMBOL_REF of the function to be called; PRIORITY is a number
19404 between 0 and MAX_INIT_PRIORITY.
19406 This differs from default_named_section_asm_out_constructor in
19407 that we have special handling for -mrelocatable. */
19410 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19412 const char *section = ".ctors";
19415 if (priority != DEFAULT_INIT_PRIORITY)
19417 sprintf (buf, ".ctors.%.5u",
19418 /* Invert the numbering so the linker puts us in the proper
19419 order; constructors are run from right to left, and the
19420 linker sorts in increasing order. */
19421 MAX_INIT_PRIORITY - priority);
19425 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19426 assemble_align (POINTER_SIZE);
19428 if (TARGET_RELOCATABLE)
19430 fputs ("\t.long (", asm_out_file);
19431 output_addr_const (asm_out_file, symbol);
19432 fputs (")@fixup\n", asm_out_file);
19435 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19439 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19441 const char *section = ".dtors";
19444 if (priority != DEFAULT_INIT_PRIORITY)
19446 sprintf (buf, ".dtors.%.5u",
19447 /* Invert the numbering so the linker puts us in the proper
19448 order; constructors are run from right to left, and the
19449 linker sorts in increasing order. */
19450 MAX_INIT_PRIORITY - priority);
19454 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19455 assemble_align (POINTER_SIZE);
19457 if (TARGET_RELOCATABLE)
19459 fputs ("\t.long (", asm_out_file);
19460 output_addr_const (asm_out_file, symbol);
19461 fputs (")@fixup\n", asm_out_file);
19464 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19468 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19472 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19473 ASM_OUTPUT_LABEL (file, name);
19474 fputs (DOUBLE_INT_ASM_OP, file);
19475 rs6000_output_function_entry (file, name);
19476 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19479 fputs ("\t.size\t", file);
19480 assemble_name (file, name);
19481 fputs (",24\n\t.type\t.", file);
19482 assemble_name (file, name);
19483 fputs (",@function\n", file);
19484 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19486 fputs ("\t.globl\t.", file);
19487 assemble_name (file, name);
19492 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19493 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19494 rs6000_output_function_entry (file, name);
19495 fputs (":\n", file);
19499 if (TARGET_RELOCATABLE
19500 && !TARGET_SECURE_PLT
19501 && (get_pool_size () != 0 || current_function_profile)
19506 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19508 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19509 fprintf (file, "\t.long ");
19510 assemble_name (file, buf);
19512 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19513 assemble_name (file, buf);
19517 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19518 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19520 if (DEFAULT_ABI == ABI_AIX)
19522 const char *desc_name, *orig_name;
19524 orig_name = (*targetm.strip_name_encoding) (name);
19525 desc_name = orig_name;
19526 while (*desc_name == '.')
19529 if (TREE_PUBLIC (decl))
19530 fprintf (file, "\t.globl %s\n", desc_name);
19532 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19533 fprintf (file, "%s:\n", desc_name);
19534 fprintf (file, "\t.long %s\n", orig_name);
19535 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19536 if (DEFAULT_ABI == ABI_AIX)
19537 fputs ("\t.long 0\n", file);
19538 fprintf (file, "\t.previous\n");
19540 ASM_OUTPUT_LABEL (file, name);
19544 rs6000_elf_end_indicate_exec_stack (void)
19547 file_end_indicate_exec_stack ();
19553 rs6000_xcoff_asm_output_anchor (rtx symbol)
19557 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19558 SYMBOL_REF_BLOCK_OFFSET (symbol));
19559 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19563 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19565 fputs (GLOBAL_ASM_OP, stream);
19566 RS6000_OUTPUT_BASENAME (stream, name);
19567 putc ('\n', stream);
19570 /* A get_unnamed_decl callback, used for read-only sections. PTR
19571 points to the section string variable. */
19574 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19576 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19577 *(const char *const *) directive);
19580 /* Likewise for read-write sections. */
19583 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19585 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19586 *(const char *const *) directive);
19589 /* A get_unnamed_section callback, used for switching to toc_section. */
19592 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19594 if (TARGET_MINIMAL_TOC)
19596 /* toc_section is always selected at least once from
19597 rs6000_xcoff_file_start, so this is guaranteed to
19598 always be defined once and only once in each file. */
19599 if (!toc_initialized)
19601 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19602 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19603 toc_initialized = 1;
19605 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19606 (TARGET_32BIT ? "" : ",3"));
19609 fputs ("\t.toc\n", asm_out_file);
19612 /* Implement TARGET_ASM_INIT_SECTIONS. */
19615 rs6000_xcoff_asm_init_sections (void)
19617 read_only_data_section
19618 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19619 &xcoff_read_only_section_name);
19621 private_data_section
19622 = get_unnamed_section (SECTION_WRITE,
19623 rs6000_xcoff_output_readwrite_section_asm_op,
19624 &xcoff_private_data_section_name);
19626 read_only_private_data_section
19627 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19628 &xcoff_private_data_section_name);
19631 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19633 readonly_data_section = read_only_data_section;
19634 exception_section = data_section;
19638 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19639 tree decl ATTRIBUTE_UNUSED)
19642 static const char * const suffix[3] = { "PR", "RO", "RW" };
19644 if (flags & SECTION_CODE)
19646 else if (flags & SECTION_WRITE)
19651 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19652 (flags & SECTION_CODE) ? "." : "",
19653 name, suffix[smclass], flags & SECTION_ENTSIZE);
19657 rs6000_xcoff_select_section (tree decl, int reloc,
19658 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19660 if (decl_readonly_section_1 (decl, reloc, 1))
19662 if (TREE_PUBLIC (decl))
19663 return read_only_data_section;
19665 return read_only_private_data_section;
19669 if (TREE_PUBLIC (decl))
19670 return data_section;
19672 return private_data_section;
19677 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19681 /* Use select_section for private and uninitialized data. */
19682 if (!TREE_PUBLIC (decl)
19683 || DECL_COMMON (decl)
19684 || DECL_INITIAL (decl) == NULL_TREE
19685 || DECL_INITIAL (decl) == error_mark_node
19686 || (flag_zero_initialized_in_bss
19687 && initializer_zerop (DECL_INITIAL (decl))))
19690 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19691 name = (*targetm.strip_name_encoding) (name);
19692 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19695 /* Select section for constant in constant pool.
19697 On RS/6000, all constants are in the private read-only data area.
19698 However, if this is being placed in the TOC it must be output as a
19702 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19703 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19705 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19706 return toc_section;
19708 return read_only_private_data_section;
19711 /* Remove any trailing [DS] or the like from the symbol name. */
19713 static const char *
19714 rs6000_xcoff_strip_name_encoding (const char *name)
19719 len = strlen (name);
19720 if (name[len - 1] == ']')
19721 return ggc_alloc_string (name, len - 4);
19726 /* Section attributes. AIX is always PIC. */
19728 static unsigned int
19729 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19731 unsigned int align;
19732 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
19734 /* Align to at least UNIT size. */
19735 if (flags & SECTION_CODE)
19736 align = MIN_UNITS_PER_WORD;
19738 /* Increase alignment of large objects if not already stricter. */
19739 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19740 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19741 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19743 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19746 /* Output at beginning of assembler file.
19748 Initialize the section names for the RS/6000 at this point.
19750 Specify filename, including full path, to assembler.
19752 We want to go into the TOC section so at least one .toc will be emitted.
19753 Also, in order to output proper .bs/.es pairs, we need at least one static
19754 [RW] section emitted.
19756 Finally, declare mcount when profiling to make the assembler happy. */
19759 rs6000_xcoff_file_start (void)
19761 rs6000_gen_section_name (&xcoff_bss_section_name,
19762 main_input_filename, ".bss_");
19763 rs6000_gen_section_name (&xcoff_private_data_section_name,
19764 main_input_filename, ".rw_");
19765 rs6000_gen_section_name (&xcoff_read_only_section_name,
19766 main_input_filename, ".ro_");
19768 fputs ("\t.file\t", asm_out_file);
19769 output_quoted_string (asm_out_file, main_input_filename);
19770 fputc ('\n', asm_out_file);
19771 if (write_symbols != NO_DEBUG)
19772 switch_to_section (private_data_section);
19773 switch_to_section (text_section);
19775 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19776 rs6000_file_start ();
19779 /* Output at end of assembler file.
19780 On the RS/6000, referencing data should automatically pull in text. */
19783 rs6000_xcoff_file_end (void)
19785 switch_to_section (text_section);
19786 fputs ("_section_.text:\n", asm_out_file);
19787 switch_to_section (data_section);
19788 fputs (TARGET_32BIT
19789 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19792 #endif /* TARGET_XCOFF */
19794 /* Compute a (partial) cost for rtx X. Return true if the complete
19795 cost has been computed, and false if subexpressions should be
19796 scanned. In either case, *TOTAL contains the cost result. */
19799 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19801 enum machine_mode mode = GET_MODE (x);
19805 /* On the RS/6000, if it is valid in the insn, it is free. */
19807 if (((outer_code == SET
19808 || outer_code == PLUS
19809 || outer_code == MINUS)
19810 && (satisfies_constraint_I (x)
19811 || satisfies_constraint_L (x)))
19812 || (outer_code == AND
19813 && (satisfies_constraint_K (x)
19815 ? satisfies_constraint_L (x)
19816 : satisfies_constraint_J (x))
19817 || mask_operand (x, mode)
19819 && mask64_operand (x, DImode))))
19820 || ((outer_code == IOR || outer_code == XOR)
19821 && (satisfies_constraint_K (x)
19823 ? satisfies_constraint_L (x)
19824 : satisfies_constraint_J (x))))
19825 || outer_code == ASHIFT
19826 || outer_code == ASHIFTRT
19827 || outer_code == LSHIFTRT
19828 || outer_code == ROTATE
19829 || outer_code == ROTATERT
19830 || outer_code == ZERO_EXTRACT
19831 || (outer_code == MULT
19832 && satisfies_constraint_I (x))
19833 || ((outer_code == DIV || outer_code == UDIV
19834 || outer_code == MOD || outer_code == UMOD)
19835 && exact_log2 (INTVAL (x)) >= 0)
19836 || (outer_code == COMPARE
19837 && (satisfies_constraint_I (x)
19838 || satisfies_constraint_K (x)))
19839 || (outer_code == EQ
19840 && (satisfies_constraint_I (x)
19841 || satisfies_constraint_K (x)
19843 ? satisfies_constraint_L (x)
19844 : satisfies_constraint_J (x))))
19845 || (outer_code == GTU
19846 && satisfies_constraint_I (x))
19847 || (outer_code == LTU
19848 && satisfies_constraint_P (x)))
19853 else if ((outer_code == PLUS
19854 && reg_or_add_cint_operand (x, VOIDmode))
19855 || (outer_code == MINUS
19856 && reg_or_sub_cint_operand (x, VOIDmode))
19857 || ((outer_code == SET
19858 || outer_code == IOR
19859 || outer_code == XOR)
19861 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
19863 *total = COSTS_N_INSNS (1);
19869 if (mode == DImode && code == CONST_DOUBLE)
19871 if ((outer_code == IOR || outer_code == XOR)
19872 && CONST_DOUBLE_HIGH (x) == 0
19873 && (CONST_DOUBLE_LOW (x)
19874 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
19879 else if ((outer_code == AND && and64_2_operand (x, DImode))
19880 || ((outer_code == SET
19881 || outer_code == IOR
19882 || outer_code == XOR)
19883 && CONST_DOUBLE_HIGH (x) == 0))
19885 *total = COSTS_N_INSNS (1);
19895 /* When optimizing for size, MEM should be slightly more expensive
19896 than generating address, e.g., (plus (reg) (const)).
19897 L1 cache latency is about two instructions. */
19898 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
19906 if (mode == DFmode)
19908 if (GET_CODE (XEXP (x, 0)) == MULT)
19910 /* FNMA accounted in outer NEG. */
19911 if (outer_code == NEG)
19912 *total = rs6000_cost->dmul - rs6000_cost->fp;
19914 *total = rs6000_cost->dmul;
19917 *total = rs6000_cost->fp;
19919 else if (mode == SFmode)
19921 /* FNMA accounted in outer NEG. */
19922 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19925 *total = rs6000_cost->fp;
19928 *total = COSTS_N_INSNS (1);
19932 if (mode == DFmode)
19934 if (GET_CODE (XEXP (x, 0)) == MULT
19935 || GET_CODE (XEXP (x, 1)) == MULT)
19937 /* FNMA accounted in outer NEG. */
19938 if (outer_code == NEG)
19939 *total = rs6000_cost->dmul - rs6000_cost->fp;
19941 *total = rs6000_cost->dmul;
19944 *total = rs6000_cost->fp;
19946 else if (mode == SFmode)
19948 /* FNMA accounted in outer NEG. */
19949 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19952 *total = rs6000_cost->fp;
19955 *total = COSTS_N_INSNS (1);
19959 if (GET_CODE (XEXP (x, 1)) == CONST_INT
19960 && satisfies_constraint_I (XEXP (x, 1)))
19962 if (INTVAL (XEXP (x, 1)) >= -256
19963 && INTVAL (XEXP (x, 1)) <= 255)
19964 *total = rs6000_cost->mulsi_const9;
19966 *total = rs6000_cost->mulsi_const;
19968 /* FMA accounted in outer PLUS/MINUS. */
19969 else if ((mode == DFmode || mode == SFmode)
19970 && (outer_code == PLUS || outer_code == MINUS))
19972 else if (mode == DFmode)
19973 *total = rs6000_cost->dmul;
19974 else if (mode == SFmode)
19975 *total = rs6000_cost->fp;
19976 else if (mode == DImode)
19977 *total = rs6000_cost->muldi;
19979 *total = rs6000_cost->mulsi;
19984 if (FLOAT_MODE_P (mode))
19986 *total = mode == DFmode ? rs6000_cost->ddiv
19987 : rs6000_cost->sdiv;
19994 if (GET_CODE (XEXP (x, 1)) == CONST_INT
19995 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
19997 if (code == DIV || code == MOD)
19999 *total = COSTS_N_INSNS (2);
20002 *total = COSTS_N_INSNS (1);
20006 if (GET_MODE (XEXP (x, 1)) == DImode)
20007 *total = rs6000_cost->divdi;
20009 *total = rs6000_cost->divsi;
20011 /* Add in shift and subtract for MOD. */
20012 if (code == MOD || code == UMOD)
20013 *total += COSTS_N_INSNS (2);
20017 *total = COSTS_N_INSNS (4);
20021 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20032 *total = COSTS_N_INSNS (1);
20040 /* Handle mul_highpart. */
20041 if (outer_code == TRUNCATE
20042 && GET_CODE (XEXP (x, 0)) == MULT)
20044 if (mode == DImode)
20045 *total = rs6000_cost->muldi;
20047 *total = rs6000_cost->mulsi;
20050 else if (outer_code == AND)
20053 *total = COSTS_N_INSNS (1);
20058 if (GET_CODE (XEXP (x, 0)) == MEM)
20061 *total = COSTS_N_INSNS (1);
20067 if (!FLOAT_MODE_P (mode))
20069 *total = COSTS_N_INSNS (1);
20075 case UNSIGNED_FLOAT:
20078 case FLOAT_TRUNCATE:
20079 *total = rs6000_cost->fp;
20083 if (mode == DFmode)
20086 *total = rs6000_cost->fp;
20090 switch (XINT (x, 1))
20093 *total = rs6000_cost->fp;
20105 *total = COSTS_N_INSNS (1);
20108 else if (FLOAT_MODE_P (mode)
20109 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20111 *total = rs6000_cost->fp;
20119 /* Carry bit requires mode == Pmode.
20120 NEG or PLUS already counted so only add one. */
20122 && (outer_code == NEG || outer_code == PLUS))
20124 *total = COSTS_N_INSNS (1);
20127 if (outer_code == SET)
20129 if (XEXP (x, 1) == const0_rtx)
20131 *total = COSTS_N_INSNS (2);
20134 else if (mode == Pmode)
20136 *total = COSTS_N_INSNS (3);
20145 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20147 *total = COSTS_N_INSNS (2);
20151 if (outer_code == COMPARE)
20165 /* A C expression returning the cost of moving data from a register of class
20166 CLASS1 to one of CLASS2. */
20169 rs6000_register_move_cost (enum machine_mode mode,
20170 enum reg_class from, enum reg_class to)
20172 /* Moves from/to GENERAL_REGS. */
20173 if (reg_classes_intersect_p (to, GENERAL_REGS)
20174 || reg_classes_intersect_p (from, GENERAL_REGS))
20176 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20179 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20180 return (rs6000_memory_move_cost (mode, from, 0)
20181 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20183 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20185 else if (from == CR_REGS)
20189 /* A move will cost one instruction per GPR moved. */
20190 return 2 * hard_regno_nregs[0][mode];
20193 /* Moving between two similar registers is just one instruction. */
20194 else if (reg_classes_intersect_p (to, from))
20195 return mode == TFmode ? 4 : 2;
20197 /* Everything else has to go through GENERAL_REGS. */
20199 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20200 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20203 /* A C expressions returning the cost of moving data of MODE from a register to
20207 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20208 int in ATTRIBUTE_UNUSED)
20210 if (reg_classes_intersect_p (class, GENERAL_REGS))
20211 return 4 * hard_regno_nregs[0][mode];
20212 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20213 return 4 * hard_regno_nregs[32][mode];
20214 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20215 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20217 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20220 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20221 Assumes no trapping math and finite arguments. */
20224 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20226 rtx x0, e0, e1, y1, u0, v0, one;
20228 x0 = gen_reg_rtx (SFmode);
20229 e0 = gen_reg_rtx (SFmode);
20230 e1 = gen_reg_rtx (SFmode);
20231 y1 = gen_reg_rtx (SFmode);
20232 u0 = gen_reg_rtx (SFmode);
20233 v0 = gen_reg_rtx (SFmode);
20234 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20236 /* x0 = 1./d estimate */
20237 emit_insn (gen_rtx_SET (VOIDmode, x0,
20238 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20240 /* e0 = 1. - d * x0 */
20241 emit_insn (gen_rtx_SET (VOIDmode, e0,
20242 gen_rtx_MINUS (SFmode, one,
20243 gen_rtx_MULT (SFmode, d, x0))));
20244 /* e1 = e0 + e0 * e0 */
20245 emit_insn (gen_rtx_SET (VOIDmode, e1,
20246 gen_rtx_PLUS (SFmode,
20247 gen_rtx_MULT (SFmode, e0, e0), e0)));
20248 /* y1 = x0 + e1 * x0 */
20249 emit_insn (gen_rtx_SET (VOIDmode, y1,
20250 gen_rtx_PLUS (SFmode,
20251 gen_rtx_MULT (SFmode, e1, x0), x0)));
20253 emit_insn (gen_rtx_SET (VOIDmode, u0,
20254 gen_rtx_MULT (SFmode, n, y1)));
20255 /* v0 = n - d * u0 */
20256 emit_insn (gen_rtx_SET (VOIDmode, v0,
20257 gen_rtx_MINUS (SFmode, n,
20258 gen_rtx_MULT (SFmode, d, u0))));
20259 /* res = u0 + v0 * y1 */
20260 emit_insn (gen_rtx_SET (VOIDmode, res,
20261 gen_rtx_PLUS (SFmode,
20262 gen_rtx_MULT (SFmode, v0, y1), u0)));
20265 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20266 Assumes no trapping math and finite arguments. */
20269 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20271 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20273 x0 = gen_reg_rtx (DFmode);
20274 e0 = gen_reg_rtx (DFmode);
20275 e1 = gen_reg_rtx (DFmode);
20276 e2 = gen_reg_rtx (DFmode);
20277 y1 = gen_reg_rtx (DFmode);
20278 y2 = gen_reg_rtx (DFmode);
20279 y3 = gen_reg_rtx (DFmode);
20280 u0 = gen_reg_rtx (DFmode);
20281 v0 = gen_reg_rtx (DFmode);
20282 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20284 /* x0 = 1./d estimate */
20285 emit_insn (gen_rtx_SET (VOIDmode, x0,
20286 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20288 /* e0 = 1. - d * x0 */
20289 emit_insn (gen_rtx_SET (VOIDmode, e0,
20290 gen_rtx_MINUS (DFmode, one,
20291 gen_rtx_MULT (SFmode, d, x0))));
20292 /* y1 = x0 + e0 * x0 */
20293 emit_insn (gen_rtx_SET (VOIDmode, y1,
20294 gen_rtx_PLUS (DFmode,
20295 gen_rtx_MULT (DFmode, e0, x0), x0)));
20297 emit_insn (gen_rtx_SET (VOIDmode, e1,
20298 gen_rtx_MULT (DFmode, e0, e0)));
20299 /* y2 = y1 + e1 * y1 */
20300 emit_insn (gen_rtx_SET (VOIDmode, y2,
20301 gen_rtx_PLUS (DFmode,
20302 gen_rtx_MULT (DFmode, e1, y1), y1)));
20304 emit_insn (gen_rtx_SET (VOIDmode, e2,
20305 gen_rtx_MULT (DFmode, e1, e1)));
20306 /* y3 = y2 + e2 * y2 */
20307 emit_insn (gen_rtx_SET (VOIDmode, y3,
20308 gen_rtx_PLUS (DFmode,
20309 gen_rtx_MULT (DFmode, e2, y2), y2)));
20311 emit_insn (gen_rtx_SET (VOIDmode, u0,
20312 gen_rtx_MULT (DFmode, n, y3)));
20313 /* v0 = n - d * u0 */
20314 emit_insn (gen_rtx_SET (VOIDmode, v0,
20315 gen_rtx_MINUS (DFmode, n,
20316 gen_rtx_MULT (DFmode, d, u0))));
20317 /* res = u0 + v0 * y3 */
20318 emit_insn (gen_rtx_SET (VOIDmode, res,
20319 gen_rtx_PLUS (DFmode,
20320 gen_rtx_MULT (DFmode, v0, y3), u0)));
20324 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20325 target, and SRC is the argument operand. */
20328 rs6000_emit_popcount (rtx dst, rtx src)
20330 enum machine_mode mode = GET_MODE (dst);
20333 tmp1 = gen_reg_rtx (mode);
20335 if (mode == SImode)
20337 emit_insn (gen_popcntbsi2 (tmp1, src));
20338 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20340 tmp2 = force_reg (SImode, tmp2);
20341 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20345 emit_insn (gen_popcntbdi2 (tmp1, src));
20346 tmp2 = expand_mult (DImode, tmp1,
20347 GEN_INT ((HOST_WIDE_INT)
20348 0x01010101 << 32 | 0x01010101),
20350 tmp2 = force_reg (DImode, tmp2);
20351 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20356 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20357 target, and SRC is the argument operand. */
20360 rs6000_emit_parity (rtx dst, rtx src)
20362 enum machine_mode mode = GET_MODE (dst);
20365 tmp = gen_reg_rtx (mode);
20366 if (mode == SImode)
20368 /* Is mult+shift >= shift+xor+shift+xor? */
20369 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20371 rtx tmp1, tmp2, tmp3, tmp4;
20373 tmp1 = gen_reg_rtx (SImode);
20374 emit_insn (gen_popcntbsi2 (tmp1, src));
20376 tmp2 = gen_reg_rtx (SImode);
20377 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20378 tmp3 = gen_reg_rtx (SImode);
20379 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20381 tmp4 = gen_reg_rtx (SImode);
20382 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20383 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20386 rs6000_emit_popcount (tmp, src);
20387 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20391 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20392 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20394 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20396 tmp1 = gen_reg_rtx (DImode);
20397 emit_insn (gen_popcntbdi2 (tmp1, src));
20399 tmp2 = gen_reg_rtx (DImode);
20400 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20401 tmp3 = gen_reg_rtx (DImode);
20402 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20404 tmp4 = gen_reg_rtx (DImode);
20405 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20406 tmp5 = gen_reg_rtx (DImode);
20407 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20409 tmp6 = gen_reg_rtx (DImode);
20410 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20411 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20414 rs6000_emit_popcount (tmp, src);
20415 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20419 /* Return an RTX representing where to find the function value of a
20420 function returning MODE. */
20422 rs6000_complex_function_value (enum machine_mode mode)
20424 unsigned int regno;
20426 enum machine_mode inner = GET_MODE_INNER (mode);
20427 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20429 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20430 regno = FP_ARG_RETURN;
20433 regno = GP_ARG_RETURN;
20435 /* 32-bit is OK since it'll go in r3/r4. */
20436 if (TARGET_32BIT && inner_bytes >= 4)
20437 return gen_rtx_REG (mode, regno);
20440 if (inner_bytes >= 8)
20441 return gen_rtx_REG (mode, regno);
20443 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20445 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20446 GEN_INT (inner_bytes));
20447 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20450 /* Define how to find the value returned by a function.
20451 VALTYPE is the data type of the value (as a tree).
20452 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20453 otherwise, FUNC is 0.
20455 On the SPE, both FPs and vectors are returned in r3.
20457 On RS/6000 an integer value is in r3 and a floating-point value is in
20458 fp1, unless -msoft-float. */
20461 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20463 enum machine_mode mode;
20464 unsigned int regno;
20466 /* Special handling for structs in darwin64. */
20467 if (rs6000_darwin64_abi
20468 && TYPE_MODE (valtype) == BLKmode
20469 && TREE_CODE (valtype) == RECORD_TYPE
20470 && int_size_in_bytes (valtype) > 0)
20472 CUMULATIVE_ARGS valcum;
20476 valcum.fregno = FP_ARG_MIN_REG;
20477 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20478 /* Do a trial code generation as if this were going to be passed as
20479 an argument; if any part goes in memory, we return NULL. */
20480 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20483 /* Otherwise fall through to standard ABI rules. */
20486 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20488 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20489 return gen_rtx_PARALLEL (DImode,
20491 gen_rtx_EXPR_LIST (VOIDmode,
20492 gen_rtx_REG (SImode, GP_ARG_RETURN),
20494 gen_rtx_EXPR_LIST (VOIDmode,
20495 gen_rtx_REG (SImode,
20496 GP_ARG_RETURN + 1),
20499 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20501 return gen_rtx_PARALLEL (DCmode,
20503 gen_rtx_EXPR_LIST (VOIDmode,
20504 gen_rtx_REG (SImode, GP_ARG_RETURN),
20506 gen_rtx_EXPR_LIST (VOIDmode,
20507 gen_rtx_REG (SImode,
20508 GP_ARG_RETURN + 1),
20510 gen_rtx_EXPR_LIST (VOIDmode,
20511 gen_rtx_REG (SImode,
20512 GP_ARG_RETURN + 2),
20514 gen_rtx_EXPR_LIST (VOIDmode,
20515 gen_rtx_REG (SImode,
20516 GP_ARG_RETURN + 3),
20520 if ((INTEGRAL_TYPE_P (valtype)
20521 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
20522 || POINTER_TYPE_P (valtype))
20523 mode = TARGET_32BIT ? SImode : DImode;
20525 mode = TYPE_MODE (valtype);
20527 if (DECIMAL_FLOAT_MODE_P (mode))
20528 regno = GP_ARG_RETURN;
20529 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20530 regno = FP_ARG_RETURN;
20531 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20532 && targetm.calls.split_complex_arg)
20533 return rs6000_complex_function_value (mode);
20534 else if (TREE_CODE (valtype) == VECTOR_TYPE
20535 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20536 && ALTIVEC_VECTOR_MODE (mode))
20537 regno = ALTIVEC_ARG_RETURN;
20538 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20539 && (mode == DFmode || mode == DCmode
20540 || mode == TFmode || mode == TCmode))
20541 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20543 regno = GP_ARG_RETURN;
20545 return gen_rtx_REG (mode, regno);
20548 /* Define how to find the value returned by a library function
20549 assuming the value has mode MODE. */
20551 rs6000_libcall_value (enum machine_mode mode)
20553 unsigned int regno;
20555 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20557 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20558 return gen_rtx_PARALLEL (DImode,
20560 gen_rtx_EXPR_LIST (VOIDmode,
20561 gen_rtx_REG (SImode, GP_ARG_RETURN),
20563 gen_rtx_EXPR_LIST (VOIDmode,
20564 gen_rtx_REG (SImode,
20565 GP_ARG_RETURN + 1),
20569 if (DECIMAL_FLOAT_MODE_P (mode))
20570 regno = GP_ARG_RETURN;
20571 else if (SCALAR_FLOAT_MODE_P (mode)
20572 && TARGET_HARD_FLOAT && TARGET_FPRS)
20573 regno = FP_ARG_RETURN;
20574 else if (ALTIVEC_VECTOR_MODE (mode)
20575 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20576 regno = ALTIVEC_ARG_RETURN;
20577 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20578 return rs6000_complex_function_value (mode);
20579 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20580 && (mode == DFmode || mode == DCmode
20581 || mode == TFmode || mode == TCmode))
20582 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20584 regno = GP_ARG_RETURN;
20586 return gen_rtx_REG (mode, regno);
20589 /* Define the offset between two registers, FROM to be eliminated and its
20590 replacement TO, at the start of a routine. */
20592 rs6000_initial_elimination_offset (int from, int to)
20594 rs6000_stack_t *info = rs6000_stack_info ();
20595 HOST_WIDE_INT offset;
20597 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20598 offset = info->push_p ? 0 : -info->total_size;
20599 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20601 offset = info->push_p ? 0 : -info->total_size;
20602 if (FRAME_GROWS_DOWNWARD)
20603 offset += info->fixed_size + info->vars_size + info->parm_size;
20605 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20606 offset = FRAME_GROWS_DOWNWARD
20607 ? info->fixed_size + info->vars_size + info->parm_size
20609 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20610 offset = info->total_size;
20611 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20612 offset = info->push_p ? info->total_size : 0;
20613 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20616 gcc_unreachable ();
20621 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20624 rs6000_is_opaque_type (tree type)
20626 return (type == opaque_V2SI_type_node
20627 || type == opaque_V2SF_type_node
20628 || type == opaque_p_V2SI_type_node
20629 || type == opaque_V4SI_type_node);
20633 rs6000_dwarf_register_span (rtx reg)
20638 && (SPE_VECTOR_MODE (GET_MODE (reg))
20639 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20644 regno = REGNO (reg);
20646 /* The duality of the SPE register size wreaks all kinds of havoc.
20647 This is a way of distinguishing r0 in 32-bits from r0 in
20650 gen_rtx_PARALLEL (VOIDmode,
20653 gen_rtx_REG (SImode, regno + 1200),
20654 gen_rtx_REG (SImode, regno))
20656 gen_rtx_REG (SImode, regno),
20657 gen_rtx_REG (SImode, regno + 1200)));
20660 /* Map internal gcc register numbers to DWARF2 register numbers. */
20663 rs6000_dbx_register_number (unsigned int regno)
20665 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20667 if (regno == MQ_REGNO)
20669 if (regno == LINK_REGISTER_REGNUM)
20671 if (regno == COUNT_REGISTER_REGNUM)
20673 if (CR_REGNO_P (regno))
20674 return regno - CR0_REGNO + 86;
20675 if (regno == XER_REGNO)
20677 if (ALTIVEC_REGNO_P (regno))
20678 return regno - FIRST_ALTIVEC_REGNO + 1124;
20679 if (regno == VRSAVE_REGNO)
20681 if (regno == VSCR_REGNO)
20683 if (regno == SPE_ACC_REGNO)
20685 if (regno == SPEFSCR_REGNO)
20687 /* SPE high reg number. We get these values of regno from
20688 rs6000_dwarf_register_span. */
20689 gcc_assert (regno >= 1200 && regno < 1232);
20693 /* target hook eh_return_filter_mode */
20694 static enum machine_mode
20695 rs6000_eh_return_filter_mode (void)
20697 return TARGET_32BIT ? SImode : word_mode;
20700 /* Target hook for scalar_mode_supported_p. */
20702 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20704 if (DECIMAL_FLOAT_MODE_P (mode))
20707 return default_scalar_mode_supported_p (mode);
20710 /* Target hook for vector_mode_supported_p. */
20712 rs6000_vector_mode_supported_p (enum machine_mode mode)
20715 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20718 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20725 /* Target hook for invalid_arg_for_unprototyped_fn. */
20726 static const char *
20727 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20729 return (!rs6000_darwin64_abi
20731 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20732 && (funcdecl == NULL_TREE
20733 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20734 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20735 ? N_("AltiVec argument passed to unprototyped function")
20739 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20740 setup by using __stack_chk_fail_local hidden function instead of
20741 calling __stack_chk_fail directly. Otherwise it is better to call
20742 __stack_chk_fail directly. */
20745 rs6000_stack_protect_fail (void)
20747 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20748 ? default_hidden_stack_protect_fail ()
20749 : default_external_stack_protect_fail ();
20752 #include "gt-rs6000.h"