1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 extern char *language_string;
40 extern int profile_block_flag;
42 #define min(A,B) ((A) < (B) ? (A) : (B))
43 #define max(A,B) ((A) > (B) ? (A) : (B))
47 enum processor_type rs6000_cpu;
48 char *rs6000_cpu_string;
50 /* Set to non-zero by "fix" operation to indicate that itrunc and
51 uitrunc must be defined. */
53 int rs6000_trunc_used;
55 /* Set to non-zero once they have been defined. */
57 static int trunc_defined;
59 /* Set to non-zero once AIX common-mode calls have been defined. */
60 static int common_mode_defined;
61 /* Save information from a "cmpxx" operation until the branch or scc is
64 rtx rs6000_compare_op0, rs6000_compare_op1;
65 int rs6000_compare_fp_p;
68 /* Label number of label created for -mrelocatable, to call to so we can
69 get the address of the GOT section */
70 int rs6000_pic_labelno;
73 /* Override command line options. Mostly we process the processor
74 type and sometimes adjust other TARGET_ options. */
77 rs6000_override_options ()
81 /* Simplify the entries below by making a mask for any POWER
82 variant and any PowerPC variant. */
84 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
85 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
86 | MASK_PPC_GFXOPT | MASK_POWERPC64)
87 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
91 char *name; /* Canonical processor name. */
92 enum processor_type processor; /* Processor type enum value. */
93 int target_enable; /* Target flags to enable. */
94 int target_disable; /* Target flags to disable. */
95 } processor_target_table[]
96 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
97 {"power", PROCESSOR_POWER,
98 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
99 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
100 {"powerpc", PROCESSOR_POWERPC,
101 MASK_POWERPC | MASK_NEW_MNEMONICS,
102 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
103 {"rios", PROCESSOR_RIOS1,
104 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
105 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
106 {"rios1", PROCESSOR_RIOS1,
107 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
108 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
109 {"rsc", PROCESSOR_PPC601,
110 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
111 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
112 {"rsc1", PROCESSOR_PPC601,
113 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
114 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
115 {"rios2", PROCESSOR_RIOS2,
116 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
117 POWERPC_MASKS | MASK_NEW_MNEMONICS},
118 {"403", PROCESSOR_PPC403,
119 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
120 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
121 {"mpc403", PROCESSOR_PPC403,
122 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
123 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
124 {"ppc403", PROCESSOR_PPC403,
125 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
126 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
127 {"601", PROCESSOR_PPC601,
128 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
129 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
130 {"mpc601", PROCESSOR_PPC601,
131 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
132 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
133 {"ppc601", PROCESSOR_PPC601,
134 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
135 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
136 {"603", PROCESSOR_PPC603,
137 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
138 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
139 {"mpc603", PROCESSOR_PPC603,
140 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
141 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
142 {"ppc603", PROCESSOR_PPC603,
143 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
144 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
145 {"604", PROCESSOR_PPC604,
146 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
147 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
148 {"mpc604", PROCESSOR_PPC604,
149 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
150 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
151 {"ppc604", PROCESSOR_PPC604,
152 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
153 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
155 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
157 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
158 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
160 profile_block_flag = 0;
162 /* Identify the processor type */
163 if (rs6000_cpu_string == 0)
164 rs6000_cpu = PROCESSOR_DEFAULT;
167 for (i = 0; i < ptt_size; i++)
168 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
170 rs6000_cpu = processor_target_table[i].processor;
171 target_flags |= processor_target_table[i].target_enable;
172 target_flags &= ~processor_target_table[i].target_disable;
178 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
179 rs6000_cpu_string = "default";
180 rs6000_cpu = PROCESSOR_DEFAULT;
184 /* If -mmultiple or -mno-multiple was explicitly used, don't
185 override with the processor default */
186 if (TARGET_MULTIPLE_SET)
187 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
189 /* If -mstring or -mno-string was explicitly used, don't
190 override with the processor default */
191 if (TARGET_STRING_SET)
192 target_flags = (target_flags & ~MASK_STRING) | string;
194 /* Don't allow -mmultiple or -mstring on little endian systems, because the
195 hardware doesn't support the instructions used in little endian mode */
196 if (!BYTES_BIG_ENDIAN)
200 target_flags &= ~MASK_MULTIPLE;
201 if (TARGET_MULTIPLE_SET)
202 warning ("-mmultiple is not supported on little endian systems");
207 target_flags &= ~MASK_STRING;
208 if (TARGET_STRING_SET)
209 warning ("-mstring is not supported on little endian systems");
213 #ifdef SUBTARGET_OVERRIDE_OPTIONS
214 SUBTARGET_OVERRIDE_OPTIONS;
218 /* Create a CONST_DOUBLE like immed_double_const, except reverse the
219 two parts of the constant if the target is little endian. */
221 struct rtx_def *rs6000_immed_double_const (i0, i1, mode)
222 HOST_WIDE_INT i0, i1;
223 enum machine_mode mode;
225 if (! WORDS_BIG_ENDIAN)
226 return immed_double_const (i1, i0, mode);
228 return immed_double_const (i0, i1, mode);
232 /* Return non-zero if this function is known to have a null epilogue. */
237 return (reload_completed
238 && first_reg_to_save () == 32
239 && first_fp_reg_to_save () == 64
240 && ! regs_ever_live[65]
241 && ! rs6000_pushes_stack ());
244 /* Returns 1 always. */
247 any_operand (op, mode)
249 enum machine_mode mode;
254 /* Return 1 if OP is a constant that can fit in a D field. */
257 short_cint_operand (op, mode)
259 enum machine_mode mode;
261 return (GET_CODE (op) == CONST_INT
262 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
265 /* Similar for a unsigned D field. */
268 u_short_cint_operand (op, mode)
270 enum machine_mode mode;
272 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
275 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
278 non_short_cint_operand (op, mode)
280 enum machine_mode mode;
282 return (GET_CODE (op) == CONST_INT
283 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
286 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
290 gpc_reg_operand (op, mode)
292 enum machine_mode mode;
294 return (register_operand (op, mode)
295 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
298 /* Returns 1 if OP is either a pseudo-register or a register denoting a
302 cc_reg_operand (op, mode)
304 enum machine_mode mode;
306 return (register_operand (op, mode)
307 && (GET_CODE (op) != REG
308 || REGNO (op) >= FIRST_PSEUDO_REGISTER
309 || CR_REGNO_P (REGNO (op))));
312 /* Returns 1 if OP is either a constant integer valid for a D-field or a
313 non-special register. If a register, it must be in the proper mode unless
317 reg_or_short_operand (op, mode)
319 enum machine_mode mode;
321 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
324 /* Similar, except check if the negation of the constant would be valid for
328 reg_or_neg_short_operand (op, mode)
330 enum machine_mode mode;
332 if (GET_CODE (op) == CONST_INT)
333 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
335 return gpc_reg_operand (op, mode);
338 /* Return 1 if the operand is either a register or an integer whose high-order
342 reg_or_u_short_operand (op, mode)
344 enum machine_mode mode;
346 if (GET_CODE (op) == CONST_INT
347 && (INTVAL (op) & 0xffff0000) == 0)
350 return gpc_reg_operand (op, mode);
353 /* Return 1 is the operand is either a non-special register or ANY
357 reg_or_cint_operand (op, mode)
359 enum machine_mode mode;
361 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
364 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
365 with one instruction per word. We only do this if we can safely read
366 CONST_DOUBLE_{LOW,HIGH}. */
369 easy_fp_constant (op, mode)
371 register enum machine_mode mode;
375 if (GET_CODE (op) != CONST_DOUBLE
376 || GET_MODE (op) != mode
377 || GET_MODE_CLASS (mode) != MODE_FLOAT)
380 high = operand_subword (op, 0, 0, mode);
381 low = operand_subword (op, 1, 0, mode);
383 if (high == 0 || ! input_operand (high, word_mode))
386 return (mode == SFmode
387 || (low != 0 && input_operand (low, word_mode)));
390 /* Return 1 if the operand is a constant whose low-order 32 bits are
394 low_32_bit_operand (op, mode)
396 enum machine_mode mode;
400 if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT)
403 low = operand_subword (op, 1, 0, mode);
404 return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0;
407 /* Return 1 if the operand is either a floating-point register, a pseudo
408 register, or memory. */
411 fp_reg_or_mem_operand (op, mode)
413 enum machine_mode mode;
415 return (memory_operand (op, mode)
416 || (register_operand (op, mode)
417 && (GET_CODE (op) != REG
418 || REGNO (op) >= FIRST_PSEUDO_REGISTER
419 || FP_REGNO_P (REGNO (op)))));
422 /* Return 1 if the operand is either an easy FP constant (see above) or
426 mem_or_easy_const_operand (op, mode)
428 enum machine_mode mode;
430 return memory_operand (op, mode) || easy_fp_constant (op, mode);
433 /* Return 1 if the operand is either a non-special register or an item
434 that can be used as the operand of an SI add insn. */
437 add_operand (op, mode)
439 enum machine_mode mode;
441 return (reg_or_short_operand (op, mode)
442 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
445 /* Return 1 if OP is a constant but not a valid add_operand. */
448 non_add_cint_operand (op, mode)
450 enum machine_mode mode;
452 return (GET_CODE (op) == CONST_INT
453 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
454 && (INTVAL (op) & 0xffff) != 0);
457 /* Return 1 if the operand is a non-special register or a constant that
458 can be used as the operand of an OR or XOR insn on the RS/6000. */
461 logical_operand (op, mode)
463 enum machine_mode mode;
465 return (gpc_reg_operand (op, mode)
466 || (GET_CODE (op) == CONST_INT
467 && ((INTVAL (op) & 0xffff0000) == 0
468 || (INTVAL (op) & 0xffff) == 0)));
471 /* Return 1 if C is a constant that is not a logical operand (as
475 non_logical_cint_operand (op, mode)
477 enum machine_mode mode;
479 return (GET_CODE (op) == CONST_INT
480 && (INTVAL (op) & 0xffff0000) != 0
481 && (INTVAL (op) & 0xffff) != 0);
484 /* Return 1 if C is a constant that can be encoded in a mask on the
485 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
486 Reject all ones and all zeros, since these should have been optimized
487 away and confuse the making of MB and ME. */
497 if (c == 0 || c == ~0)
500 last_bit_value = c & 1;
502 for (i = 1; i < 32; i++)
503 if (((c >>= 1) & 1) != last_bit_value)
504 last_bit_value ^= 1, transitions++;
506 return transitions <= 2;
509 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
512 mask_operand (op, mode)
514 enum machine_mode mode;
516 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
519 /* Return 1 if the operand is either a non-special register or a
520 constant that can be used as the operand of an RS/6000 logical AND insn. */
523 and_operand (op, mode)
525 enum machine_mode mode;
527 return (reg_or_short_operand (op, mode)
528 || logical_operand (op, mode)
529 || mask_operand (op, mode));
532 /* Return 1 if the operand is a constant but not a valid operand for an AND
536 non_and_cint_operand (op, mode)
538 enum machine_mode mode;
540 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
543 /* Return 1 if the operand is a general register or memory operand. */
546 reg_or_mem_operand (op, mode)
548 register enum machine_mode mode;
550 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
553 /* Return 1 if the operand is a general register or memory operand without
554 pre-inc or pre_dec which produces invalid form of PowerPC lwa
558 lwa_operand (op, mode)
560 register enum machine_mode mode;
564 if (reload_completed && GET_CODE (inner) == SUBREG)
565 inner = SUBREG_REG (inner);
567 return gpc_reg_operand (inner, mode)
568 || (memory_operand (inner, mode)
569 && GET_CODE (XEXP (inner, 0)) != PRE_INC
570 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
573 /* Return 1 if the operand, used inside a MEM, is a valid first argument
574 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
578 call_operand (op, mode)
580 enum machine_mode mode;
582 if (mode != VOIDmode && GET_MODE (op) != mode)
585 return (GET_CODE (op) == SYMBOL_REF
586 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
590 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
594 current_file_function_operand (op, mode)
596 enum machine_mode mode;
598 return (GET_CODE (op) == SYMBOL_REF
599 && (SYMBOL_REF_FLAG (op)
600 || op == XEXP (DECL_RTL (current_function_decl), 0)));
604 /* Return 1 if this operand is a valid input for a move insn. */
607 input_operand (op, mode)
609 enum machine_mode mode;
611 /* Memory is always valid. */
612 if (memory_operand (op, mode))
615 /* For floating-point, easy constants are valid. */
616 if (GET_MODE_CLASS (mode) == MODE_FLOAT
618 && easy_fp_constant (op, mode))
621 /* For floating-point or multi-word mode, the only remaining valid type
623 if (GET_MODE_CLASS (mode) == MODE_FLOAT
624 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
625 return register_operand (op, mode);
627 /* The only cases left are integral modes one word or smaller (we
628 do not get called for MODE_CC values). These can be in any
630 if (register_operand (op, mode))
633 /* For HImode and QImode, any constant is valid. */
634 if ((mode == HImode || mode == QImode)
635 && GET_CODE (op) == CONST_INT)
638 /* A SYMBOL_REF referring to the TOC is valid. */
639 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
642 /* Otherwise, we will be doing this SET with an add, so anything valid
643 for an add will be valid. */
644 return add_operand (op, mode);
647 /* Expand a block move operation, and return 1 if successful. Return 0
648 if we should let the compiler generate normal code.
650 operands[0] is the destination
651 operands[1] is the source
652 operands[2] is the length
653 operands[3] is the alignment */
655 #define MAX_MOVE_REG 4
658 expand_block_move (operands)
661 rtx bytes_rtx = operands[2];
662 rtx align_rtx = operands[3];
663 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
664 int align = XINT (align_rtx, 0);
674 rtx stores[MAX_MOVE_REG];
677 /* If this is not a fixed size move, just call memcpy */
681 /* Anything to move? */
682 bytes = INTVAL (bytes_rtx);
686 /* Don't support real large moves. If string instructions are not used,
687 then don't generate more than 8 loads. */
693 else if (!STRICT_ALIGNMENT)
698 else if (bytes > 8*align)
701 /* Move the address into scratch registers. */
702 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
703 src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
705 if (TARGET_STRING) /* string instructions are available */
707 for ( ; bytes > 0; bytes -= move_bytes)
710 /* XXX Don't move so many bytes right now, it causes the compiler to not bootstrap */
711 if (bytes > 24 /* move up to 32 bytes at a time */
721 move_bytes = (bytes > 32) ? 32 : bytes;
722 emit_insn (gen_movstrsi_8reg (dest_reg,
724 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
727 else if (bytes > 16 /* move up to 24 bytes at a time */
735 move_bytes = (bytes > 24) ? 24 : bytes;
736 emit_insn (gen_movstrsi_6reg (dest_reg,
738 GEN_INT (move_bytes),
741 else if (bytes > 8 /* move up to 16 bytes at a time */
747 move_bytes = (bytes > 16) ? 16 : bytes;
748 emit_insn (gen_movstrsi_4reg (dest_reg,
750 GEN_INT (move_bytes),
755 if (bytes > 4 && !TARGET_64BIT)
756 { /* move up to 8 bytes at a time */
757 move_bytes = (bytes > 8) ? 8 : bytes;
758 emit_insn (gen_movstrsi_2reg (dest_reg,
760 GEN_INT (move_bytes),
763 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
766 tmp_reg = gen_reg_rtx (SImode);
767 emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
768 emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
770 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
773 tmp_reg = gen_reg_rtx (HImode);
774 emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
775 emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
777 else if (bytes == 1) /* move 1 byte */
780 tmp_reg = gen_reg_rtx (QImode);
781 emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
782 emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
785 { /* move up to 4 bytes at a time */
786 move_bytes = (bytes > 4) ? 4 : bytes;
787 emit_insn (gen_movstrsi_1reg (dest_reg,
789 GEN_INT (move_bytes),
793 if (bytes > move_bytes)
795 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
796 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
801 else /* string instructions not available */
803 num_reg = offset = 0;
804 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
806 /* Calculate the correct offset for src/dest */
810 dest_addr = dest_reg;
814 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
815 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
818 /* Generate the appropriate load and store, saving the stores for later */
819 if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
822 tmp_reg = gen_reg_rtx (SImode);
823 emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
824 stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
826 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
829 tmp_reg = gen_reg_rtx (HImode);
830 emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
831 stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
836 tmp_reg = gen_reg_rtx (QImode);
837 emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
838 stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
841 if (num_reg >= MAX_MOVE_REG)
843 for (i = 0; i < num_reg; i++)
844 emit_insn (stores[i]);
851 for (i = 0; i < num_reg; i++)
852 emit_insn (stores[i]);
860 /* Return 1 if OP is a load multiple operation. It is known to be a
861 PARALLEL and the first section will be tested. */
864 load_multiple_operation (op, mode)
866 enum machine_mode mode;
868 int count = XVECLEN (op, 0);
873 /* Perform a quick check so we don't blow up below. */
875 || GET_CODE (XVECEXP (op, 0, 0)) != SET
876 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
877 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
880 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
881 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
883 for (i = 1; i < count; i++)
885 rtx elt = XVECEXP (op, 0, i);
887 if (GET_CODE (elt) != SET
888 || GET_CODE (SET_DEST (elt)) != REG
889 || GET_MODE (SET_DEST (elt)) != SImode
890 || REGNO (SET_DEST (elt)) != dest_regno + i
891 || GET_CODE (SET_SRC (elt)) != MEM
892 || GET_MODE (SET_SRC (elt)) != SImode
893 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
894 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
895 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
896 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
903 /* Similar, but tests for store multiple. Here, the second vector element
904 is a CLOBBER. It will be tested later. */
907 store_multiple_operation (op, mode)
909 enum machine_mode mode;
911 int count = XVECLEN (op, 0) - 1;
916 /* Perform a quick check so we don't blow up below. */
918 || GET_CODE (XVECEXP (op, 0, 0)) != SET
919 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
920 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
923 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
924 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
926 for (i = 1; i < count; i++)
928 rtx elt = XVECEXP (op, 0, i + 1);
930 if (GET_CODE (elt) != SET
931 || GET_CODE (SET_SRC (elt)) != REG
932 || GET_MODE (SET_SRC (elt)) != SImode
933 || REGNO (SET_SRC (elt)) != src_regno + i
934 || GET_CODE (SET_DEST (elt)) != MEM
935 || GET_MODE (SET_DEST (elt)) != SImode
936 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
937 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
938 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
939 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
946 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
947 We only check the opcode against the mode of the CC value here. */
950 branch_comparison_operator (op, mode)
952 enum machine_mode mode;
954 enum rtx_code code = GET_CODE (op);
955 enum machine_mode cc_mode;
957 if (GET_RTX_CLASS (code) != '<')
960 cc_mode = GET_MODE (XEXP (op, 0));
961 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
964 if ((code == GT || code == LT || code == GE || code == LE)
965 && cc_mode == CCUNSmode)
968 if ((code == GTU || code == LTU || code == GEU || code == LEU)
969 && (cc_mode != CCUNSmode))
975 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
976 We check the opcode against the mode of the CC value and disallow EQ or
977 NE comparisons for integers. */
980 scc_comparison_operator (op, mode)
982 enum machine_mode mode;
984 enum rtx_code code = GET_CODE (op);
985 enum machine_mode cc_mode;
987 if (GET_MODE (op) != mode && mode != VOIDmode)
990 if (GET_RTX_CLASS (code) != '<')
993 cc_mode = GET_MODE (XEXP (op, 0));
994 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
997 if (code == NE && cc_mode != CCFPmode)
1000 if ((code == GT || code == LT || code == GE || code == LE)
1001 && cc_mode == CCUNSmode)
1004 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1005 && (cc_mode != CCUNSmode))
1008 if (cc_mode == CCEQmode && code != EQ && code != NE)
1014 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
1015 mask required to convert the result of a rotate insn into a shift
1016 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1019 includes_lshift_p (shiftop, andop)
1020 register rtx shiftop;
1023 int shift_mask = (~0 << INTVAL (shiftop));
1025 return (INTVAL (andop) & ~shift_mask) == 0;
1028 /* Similar, but for right shift. */
1031 includes_rshift_p (shiftop, andop)
1032 register rtx shiftop;
1035 unsigned shift_mask = ~0;
1037 shift_mask >>= INTVAL (shiftop);
1039 return (INTVAL (andop) & ~ shift_mask) == 0;
1042 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1043 for lfq and stfq insns.
1045 Note reg1 and reg2 *must* be hard registers. To be sure we will
1046 abort if we are passed pseudo registers. */
1049 registers_ok_for_quad_peep (reg1, reg2)
1052 /* We might have been passed a SUBREG. */
1053 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1056 return (REGNO (reg1) == REGNO (reg2) - 1);
1059 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1060 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1063 addrs_ok_for_quad_peep (addr1, addr2)
1070 /* Extract an offset (if used) from the first addr. */
1071 if (GET_CODE (addr1) == PLUS)
1073 /* If not a REG, return zero. */
1074 if (GET_CODE (XEXP (addr1, 0)) != REG)
1078 reg1 = REGNO (XEXP (addr1, 0));
1079 /* The offset must be constant! */
1080 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1082 offset1 = INTVAL (XEXP (addr1, 1));
1085 else if (GET_CODE (addr1) != REG)
1089 reg1 = REGNO (addr1);
1090 /* This was a simple (mem (reg)) expression. Offset is 0. */
1094 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1095 if (GET_CODE (addr2) != PLUS)
1098 if (GET_CODE (XEXP (addr2, 0)) != REG
1099 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1102 if (reg1 != REGNO (XEXP (addr2, 0)))
1105 /* The offset for the second addr must be 8 more than the first addr. */
1106 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1109 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1114 /* Return the register class of a scratch register needed to copy IN into
1115 or out of a register in CLASS in MODE. If it can be done directly,
1116 NO_REGS is returned. */
1119 secondary_reload_class (class, mode, in)
1120 enum reg_class class;
1121 enum machine_mode mode;
1124 int regno = true_regnum (in);
1126 if (regno >= FIRST_PSEUDO_REGISTER)
1129 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1131 if (class == GENERAL_REGS || class == BASE_REGS
1132 || (regno >= 0 && INT_REGNO_P (regno)))
1135 /* Constants, memory, and FP registers can go into FP registers. */
1136 if ((regno == -1 || FP_REGNO_P (regno))
1137 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1140 /* We can copy among the CR registers. */
1141 if ((class == CR_REGS || class == CR0_REGS)
1142 && regno >= 0 && CR_REGNO_P (regno))
1145 /* Otherwise, we need GENERAL_REGS. */
1146 return GENERAL_REGS;
1149 /* Given a comparison operation, return the bit number in CCR to test. We
1150 know this is a valid comparison.
1152 SCC_P is 1 if this is for an scc. That means that %D will have been
1153 used instead of %C, so the bits will be in different places.
1155 Return -1 if OP isn't a valid comparison for some reason. */
1162 enum rtx_code code = GET_CODE (op);
1163 enum machine_mode cc_mode;
1167 if (GET_RTX_CLASS (code) != '<')
1170 cc_mode = GET_MODE (XEXP (op, 0));
1171 cc_regnum = REGNO (XEXP (op, 0));
1172 base_bit = 4 * (cc_regnum - 68);
1174 /* In CCEQmode cases we have made sure that the result is always in the
1175 third bit of the CR field. */
1177 if (cc_mode == CCEQmode)
1178 return base_bit + 3;
1183 return scc_p ? base_bit + 3 : base_bit + 2;
1185 return base_bit + 2;
1187 return base_bit + 1;
1192 /* If floating-point, we will have done a cror to put the bit in the
1193 unordered position. So test that bit. For integer, this is ! LT
1194 unless this is an scc insn. */
1195 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
1198 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
1205 /* Print an operand. Recognize special options, documented below. */
1208 print_operand (file, x, code)
1216 /* These macros test for integers and extract the low-order bits. */
1218 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
1219 && GET_MODE (X) == VOIDmode)
1221 #define INT_LOWPART(X) \
1222 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
1227 /* Write out an instruction after the call which may be replaced
1228 with glue code by the loader. This depends on the AIX version. */
1229 asm_fprintf (file, RS6000_CALL_GLUE);
1233 /* Write the register number of the TOC register. */
1234 fputs (TARGET_MINIMAL_TOC ? "30" : "2", file);
1238 /* If X is a constant integer whose low-order 5 bits are zero,
1239 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
1240 in the AIX assembler where "sri" with a zero shift count
1241 write a trash instruction. */
1242 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
1249 /* Low-order 16 bits of constant, unsigned. */
1251 output_operand_lossage ("invalid %%b value");
1253 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1257 /* This is an optional cror needed for LE or GE floating-point
1258 comparisons. Otherwise write nothing. */
1259 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
1260 && GET_MODE (XEXP (x, 0)) == CCFPmode)
1262 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1264 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1265 base_bit + 2, base_bit + (GET_CODE (x) == GE));
1270 /* Similar, except that this is for an scc, so we must be able to
1271 encode the test in a single bit that is one. We do the above
1272 for any LE, GE, GEU, or LEU and invert the bit for NE. */
1273 if (GET_CODE (x) == LE || GET_CODE (x) == GE
1274 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
1276 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1278 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1280 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
1283 else if (GET_CODE (x) == NE)
1285 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1287 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
1288 base_bit + 2, base_bit + 2);
1293 /* X is a CR register. Print the number of the third bit of the CR */
1294 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1295 output_operand_lossage ("invalid %%E value");
1297 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1301 /* X is a CR register. Print the shift count needed to move it
1302 to the high-order four bits. */
1303 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1304 output_operand_lossage ("invalid %%f value");
1306 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1310 /* Similar, but print the count for the rotate in the opposite
1312 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1313 output_operand_lossage ("invalid %%F value");
1315 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1319 /* X is a constant integer. If it is negative, print "m",
1320 otherwise print "z". This is to make a aze or ame insn. */
1321 if (GET_CODE (x) != CONST_INT)
1322 output_operand_lossage ("invalid %%G value");
1323 else if (INTVAL (x) >= 0)
1330 /* If constant, output low-order five bits. Otherwise,
1333 fprintf (file, "%d", INT_LOWPART (x) & 31);
1335 print_operand (file, x, 0);
1339 /* Print `i' if this is a constant, else nothing. */
1345 /* Write the bit number in CCR for jump. */
1348 output_operand_lossage ("invalid %%j code");
1350 fprintf (file, "%d", i);
1354 /* Similar, but add one for shift count in rlinm for scc and pass
1355 scc flag to `ccr_bit'. */
1358 output_operand_lossage ("invalid %%J code");
1360 /* If we want bit 31, write a shift count of zero, not 32. */
1361 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1365 /* X must be a constant. Write the 1's complement of the
1368 output_operand_lossage ("invalid %%k value");
1370 fprintf (file, "%d", ~ INT_LOWPART (x));
1374 /* Write second word of DImode or DFmode reference. Works on register
1375 or non-indexed memory only. */
1376 if (GET_CODE (x) == REG)
1377 fprintf (file, "%d", REGNO (x) + 1);
1378 else if (GET_CODE (x) == MEM)
1380 /* Handle possible auto-increment. Since it is pre-increment and
1381 we have already done it, we can just use an offset of four. */
1382 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1383 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1384 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1386 output_address (plus_constant (XEXP (x, 0), 4));
1391 /* MB value for a mask operand. */
1392 if (! mask_operand (x, VOIDmode))
1393 output_operand_lossage ("invalid %%m value");
1395 val = INT_LOWPART (x);
1397 /* If the high bit is set and the low bit is not, the value is zero.
1398 If the high bit is zero, the value is the first 1 bit we find from
1400 if (val < 0 && (val & 1) == 0)
1402 fprintf (file, "0");
1407 for (i = 1; i < 32; i++)
1408 if ((val <<= 1) < 0)
1410 fprintf (file, "%d", i);
1414 /* Otherwise, look for the first 0 bit from the right. The result is its
1415 number plus 1. We know the low-order bit is one. */
1416 for (i = 0; i < 32; i++)
1417 if (((val >>= 1) & 1) == 0)
1420 /* If we ended in ...01, I would be 0. The correct value is 31, so
1422 fprintf (file, "%d", 31 - i);
1426 /* ME value for a mask operand. */
1427 if (! mask_operand (x, VOIDmode))
1428 output_operand_lossage ("invalid %%m value");
1430 val = INT_LOWPART (x);
1432 /* If the low bit is set and the high bit is not, the value is 31.
1433 If the low bit is zero, the value is the first 1 bit we find from
1435 if ((val & 1) && val >= 0)
1440 else if ((val & 1) == 0)
1442 for (i = 0; i < 32; i++)
1443 if ((val >>= 1) & 1)
1446 /* If we had ....10, I would be 0. The result should be
1447 30, so we need 30 - i. */
1448 fprintf (file, "%d", 30 - i);
1452 /* Otherwise, look for the first 0 bit from the left. The result is its
1453 number minus 1. We know the high-order bit is one. */
1454 for (i = 0; i < 32; i++)
1455 if ((val <<= 1) >= 0)
1458 fprintf (file, "%d", i);
1462 /* Write the number of elements in the vector times 4. */
1463 if (GET_CODE (x) != PARALLEL)
1464 output_operand_lossage ("invalid %%N value");
1466 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1470 /* Similar, but subtract 1 first. */
1471 if (GET_CODE (x) != PARALLEL)
1472 output_operand_lossage ("invalid %%N value");
1474 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1478 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1480 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1481 output_operand_lossage ("invalid %%p value");
1483 fprintf (file, "%d", i);
1487 /* The operand must be an indirect memory reference. The result
1488 is the register number. */
1489 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1490 || REGNO (XEXP (x, 0)) >= 32)
1491 output_operand_lossage ("invalid %%P value");
1493 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1497 /* X is a CR register. Print the mask for `mtcrf'. */
1498 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1499 output_operand_lossage ("invalid %%R value");
1501 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1505 /* Low 5 bits of 32 - value */
1507 output_operand_lossage ("invalid %%s value");
1509 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1513 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1514 All floating-point operations except NE branch true and integer
1515 EQ, LT, GT, LTU and GTU also branch true. */
1516 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1517 output_operand_lossage ("invalid %%t value");
1519 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1520 && GET_CODE (x) != NE)
1521 || GET_CODE (x) == EQ
1522 || GET_CODE (x) == LT || GET_CODE (x) == GT
1523 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1530 /* Opposite of 't': write 4 if this jump operation will branch if true,
1532 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1533 output_operand_lossage ("invalid %%t value");
1535 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1536 && GET_CODE (x) != NE)
1537 || GET_CODE (x) == EQ
1538 || GET_CODE (x) == LT || GET_CODE (x) == GT
1539 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1546 /* High-order 16 bits of constant. */
1548 output_operand_lossage ("invalid %%u value");
1550 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1554 /* Print `u' if this has an auto-increment or auto-decrement. */
1555 if (GET_CODE (x) == MEM
1556 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1557 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1562 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1565 fprintf (file, "%d",
1566 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1568 print_operand (file, x, 0);
1572 /* If constant, low-order 16 bits of constant, unsigned.
1573 Otherwise, write normally. */
1575 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1577 print_operand (file, x, 0);
1581 if (GET_CODE (x) == MEM
1582 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1587 /* Like 'L', for third word of TImode */
1588 if (GET_CODE (x) == REG)
1589 fprintf (file, "%d", REGNO (x) + 2);
1590 else if (GET_CODE (x) == MEM)
1592 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1593 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1594 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1596 output_address (plus_constant (XEXP (x, 0), 8));
1601 /* X is a SYMBOL_REF. Write out the name preceded by a
1602 period and without any trailing data in brackets. Used for function
1603 names. If we are configured for System V (or the embedded ABI) on
1604 the PowerPC, do not emit the period, since those systems do not use
1605 TOCs and the like. */
1606 if (GET_CODE (x) != SYMBOL_REF)
1609 #ifndef USING_SVR4_H
1612 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1616 /* Like 'L', for last word of TImode. */
1617 if (GET_CODE (x) == REG)
1618 fprintf (file, "%d", REGNO (x) + 3);
1619 else if (GET_CODE (x) == MEM)
1621 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1622 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1623 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1625 output_address (plus_constant (XEXP (x, 0), 12));
1630 if (GET_CODE (x) == REG)
1631 fprintf (file, "%s", reg_names[REGNO (x)]);
1632 else if (GET_CODE (x) == MEM)
1634 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1635 know the width from the mode. */
1636 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1637 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
1638 REGNO (XEXP (XEXP (x, 0), 0)));
1639 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1640 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
1641 REGNO (XEXP (XEXP (x, 0), 0)));
1643 output_address (XEXP (x, 0));
1646 output_addr_const (file, x);
1650 output_operand_lossage ("invalid %%xn code");
1654 /* Print the address of an operand. */
1657 print_operand_address (file, x)
1661 if (GET_CODE (x) == REG)
1662 fprintf (file, "0(%d)", REGNO (x));
1663 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
1665 output_addr_const (file, x);
1666 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1667 of the toc pointer. */
1668 if (TARGET_MINIMAL_TOC)
1669 fprintf (file, "(30)");
1671 fprintf (file, "(2)");
1673 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
1675 if (REGNO (XEXP (x, 0)) == 0)
1676 fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1678 fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1)));
1680 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1681 fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1686 /* This page contains routines that are used to determine what the function
1687 prologue and epilogue code will do and write them out. */
1689 /* Return the first fixed-point register that is required to be saved. 32 if
1693 first_reg_to_save ()
1697 /* Find lowest numbered live register. */
1698 for (first_reg = 13; first_reg <= 31; first_reg++)
1699 if (regs_ever_live[first_reg])
1702 /* If profiling, then we must save/restore every register that contains
1703 a parameter before/after the .mcount call. Use registers from 30 down
1704 to 23 to do this. Don't use the frame pointer in reg 31.
1706 For now, save enough room for all of the parameter registers. */
1714 /* Similar, for FP regs. */
1717 first_fp_reg_to_save ()
1721 /* Find lowest numbered live register. */
1722 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
1723 if (regs_ever_live[first_reg])
1729 /* Return 1 if we need to save CR. */
1734 return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72];
1737 /* Compute the size of the save area in the stack, including the space for
1745 /* We have the six fixed words, plus the size of the register save
1746 areas, rounded to a double-word. */
1747 size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1754 /* Return non-zero if this function makes calls. */
1757 rs6000_makes_calls ()
1761 /* If we are profiling, we will be making a call to mcount. */
1765 for (insn = get_insns (); insn; insn = next_insn (insn))
1766 if (GET_CODE (insn) == CALL_INSN)
1772 /* Return non-zero if this function needs to push space on the stack. */
1775 rs6000_pushes_stack ()
1777 int total_size = (rs6000_sa_size () + get_frame_size ()
1778 + current_function_outgoing_args_size);
1780 /* We need to push the stack if a frame pointer is needed (because the
1781 stack might be dynamically adjusted), if we are debugging, if the
1782 total stack size is more than 220 bytes, or if we make calls. */
1784 return (frame_pointer_needed || write_symbols != NO_DEBUG
1786 || rs6000_makes_calls ());
1790 /* Write out a System V.4 style traceback table before the prologue
1792 At present, only emit the basic tag table (ie, do not emit tag_types other
1793 than 0, which might use more than 1 tag word).
1795 The first tag word looks like:
1798 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1799 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1800 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
1801 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1806 svr4_traceback (file, name, decl)
1811 int first_reg = first_reg_to_save ();
1812 int first_fp_reg = first_fp_reg_to_save ();
1813 int pushes_stack = rs6000_pushes_stack ();
1815 long version = 0; /* version number */
1816 long tag_type = 0; /* function type */
1817 long extended_tag = 0; /* additional tag words needed */
1818 long spare = 0; /* reserved for future use */
1819 long alloca_reg; /* stack/frame register */
1820 long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */
1821 long gpr_max = 32 - first_reg; /* # of general purpose registers saved */
1822 long sp_max; /* 1 if the function acquires a stack frame */
1823 long lr_max; /* 1 if the function stores the link register */
1824 long cr_max; /* 1 if the function has a CR save word */
1825 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
1827 if (frame_pointer_needed)
1830 else if (pushes_stack != 0)
1836 lr_max = (regs_ever_live[65] || first_fp_reg < 62 || profile_flag);
1837 cr_max = (must_save_cr () != 0);
1838 sp_max = (pushes_stack != 0);
1840 tag = (((version & 3) << 24)
1841 | ((tag_type & 7) << 21)
1842 | ((extended_tag & 1) << 20)
1843 | ((spare & 1) << 19)
1844 | ((alloca_reg & 0x1f) << 14)
1845 | ((fpr_max & 0x1f) << 9)
1846 | ((gpr_max & 0x1f) << 4)
1847 | ((sp_max & 1) << 3)
1848 | ((lr_max & 1) << 2)
1849 | ((cr_max & 1) << 1)
1850 | ((fpscr_max & 1) << 0));
1852 fprintf (file, "\t.long 0x%lx\n", tag);
1855 #endif /* USING_SVR4_H */
1857 /* Write function prologue. */
1860 output_prolog (file, size)
1864 int first_reg = first_reg_to_save ();
1865 int must_push = rs6000_pushes_stack ();
1866 int first_fp_reg = first_fp_reg_to_save ();
1867 int basic_size = rs6000_sa_size ();
1868 int total_size = (basic_size + size + current_function_outgoing_args_size);
1871 /* If this is eabi, call __eabi with main, but do so before the minimal TOC
1872 is setup, so we can't use the normal mechanism. */
1873 #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main)
1876 if (IDENTIFIER_LENGTH (DECL_NAME (current_function_decl)) == 4
1877 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main"))
1880 regs_ever_live[65] = 1;
1884 /* Round size to multiple of 8 bytes. */
1885 total_size = (total_size + 7) & ~7;
1887 /* Write .extern for any function we will call to save and restore fp
1889 if (first_fp_reg < 62)
1890 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
1891 SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX,
1892 RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
1894 /* Write .extern for truncation routines, if needed. */
1895 if (rs6000_trunc_used && ! trunc_defined)
1897 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
1898 RS6000_ITRUNC, RS6000_UITRUNC);
1901 /* Write .extern for AIX common mode routines, if needed. */
1902 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
1904 fputs ("\t.extern __mulh\n", file);
1905 fputs ("\t.extern __mull\n", file);
1906 fputs ("\t.extern __divss\n", file);
1907 fputs ("\t.extern __divus\n", file);
1908 fputs ("\t.extern __quoss\n", file);
1909 fputs ("\t.extern __quous\n", file);
1910 common_mode_defined = 1;
1914 /* If we have a relocatable GOT section, we need to save the LR. */
1915 if (TARGET_RELOCATABLE && get_pool_size () != 0)
1916 regs_ever_live[65] = 1;
1919 /* If we have to call a function to save fpr's, or if we are doing profiling,
1920 then we will be using LR. */
1921 if (first_fp_reg < 62 || profile_flag)
1922 regs_ever_live[65] = 1;
1924 /* If we use the link register, get it into r0. */
1925 if (regs_ever_live[65])
1926 asm_fprintf (file, "\tmflr 0\n");
1928 /* If we need to save CR, put it into r12. */
1929 if (must_save_cr ())
1930 asm_fprintf (file, "\tmfcr 12\n");
1932 /* Do any required saving of fpr's. If only one or two to save, do it
1933 ourself. Otherwise, call function. Note that since they are statically
1934 linked, we do not need a nop following them. */
1935 if (first_fp_reg == 62)
1936 asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1937 else if (first_fp_reg == 63)
1938 asm_fprintf (file, "\tstfd 31,-8(1)\n");
1939 else if (first_fp_reg != 64)
1940 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX);
1942 /* Now save gpr's. */
1943 if (! TARGET_MULTIPLE || first_reg == 31)
1947 for (regno = first_reg,
1948 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1951 asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc);
1954 else if (first_reg != 32)
1955 asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg,
1956 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1958 /* Save lr if we used it. */
1959 if (regs_ever_live[65])
1960 asm_fprintf (file, "\t{st|stw} 0,8(1)\n");
1962 /* Save CR if we use any that must be preserved. */
1963 if (must_save_cr ())
1964 asm_fprintf (file, "\t{st|stw} 12,4(1)\n");
1966 /* Update stack and set back pointer. */
1969 if (total_size < 32767)
1970 asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size);
1973 asm_fprintf (file, "\t{liu|lis} 0,%d\n\t{oril|ori} 0,0,%d\n",
1974 (total_size >> 16) & 0xffff, total_size & 0xffff);
1976 asm_fprintf (file, "\tsubf 12,0,1\n");
1978 asm_fprintf (file, "\t{sf|subfc} 12,0,1\n");
1979 asm_fprintf (file, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1983 /* Set frame pointer, if needed. */
1984 if (frame_pointer_needed)
1985 asm_fprintf (file, "\tmr 31,1\n");
1987 /* If this is eabi, call __eabi before loading up the minimal TOC */
1988 #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main)
1990 fprintf (file, "\tbl %s\n", NAME__MAIN);
1993 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1994 TOC_TABLE address into register 30. */
1995 if (TARGET_MINIMAL_TOC && get_pool_size () != 0)
2000 if (TARGET_RELOCATABLE)
2002 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2003 fprintf (file, "\tbl ");
2004 assemble_name (file, buf);
2005 fprintf (file, "\n");
2007 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
2008 fprintf (file, "\tmflr 30\n");
2010 if (TARGET_POWERPC64)
2011 fprintf (file, "\tld 0,");
2012 else if (TARGET_NEW_MNEMONICS)
2013 fprintf (file, "\tlwz 0,");
2015 fprintf (file, "\tl 0,");
2017 fprintf (file, "(");
2018 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
2019 assemble_name (file, buf);
2020 fprintf (file, "-");
2021 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2022 assemble_name (file, buf);
2023 fprintf (file, ")(30)\n");
2024 asm_fprintf (file, "\t{cax|add} 30,0,30\n");
2025 rs6000_pic_labelno++;
2027 else if (TARGET_NO_TOC)
2029 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
2030 asm_fprintf (file, "\t{cau|addis} 30,0,");
2031 assemble_name (file, buf);
2032 asm_fprintf (file, "@ha\n");
2033 asm_fprintf (file, "\t{cal|addi} 30,30,");
2034 assemble_name (file, buf);
2035 asm_fprintf (file, "@l\n");
2038 #endif /* USING_SVR4_H */
2040 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
2041 asm_fprintf (file, "\t{l|lwz} 30,");
2042 assemble_name (file, buf);
2043 asm_fprintf (file, "(2)\n");
2048 /* Write function epilogue. */
2051 output_epilog (file, size)
2055 int first_reg = first_reg_to_save ();
2056 int must_push = rs6000_pushes_stack ();
2057 int first_fp_reg = first_fp_reg_to_save ();
2058 int basic_size = rs6000_sa_size ();
2059 int total_size = (basic_size + size + current_function_outgoing_args_size);
2060 rtx insn = get_last_insn ();
2062 /* Round size to multiple of 8 bytes. */
2063 total_size = (total_size + 7) & ~7;
2065 /* If the last insn was a BARRIER, we don't have to write anything except
2067 if (GET_CODE (insn) == NOTE)
2068 insn = prev_nonnote_insn (insn);
2069 if (insn == 0 || GET_CODE (insn) != BARRIER)
2071 /* If we have a frame pointer, a call to alloca, or a large stack
2072 frame, restore the old stack pointer using the backchain. Otherwise,
2073 we know what size to update it with. */
2074 if (frame_pointer_needed || current_function_calls_alloca
2075 || total_size > 32767)
2076 asm_fprintf (file, "\t{l|lwz} 1,0(1)\n");
2078 asm_fprintf (file, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size);
2080 /* Get the old lr if we saved it. */
2081 if (regs_ever_live[65])
2082 asm_fprintf (file, "\t{l|lwz} 0,8(1)\n");
2084 /* Get the old cr if we saved it. */
2085 if (must_save_cr ())
2086 asm_fprintf (file, "\t{l|lwz} 12,4(1)\n");
2088 /* Set LR here to try to overlap restores below. */
2089 if (regs_ever_live[65])
2090 asm_fprintf (file, "\tmtlr 0\n");
2092 /* Restore gpr's. */
2093 if (! TARGET_MULTIPLE || first_reg == 31)
2097 for (regno = first_reg,
2098 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
2101 asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc);
2104 else if (first_reg != 32)
2105 asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg,
2106 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
2108 /* Restore fpr's if we can do it without calling a function. */
2109 if (first_fp_reg == 62)
2110 asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
2111 else if (first_fp_reg == 63)
2112 asm_fprintf (file, "\tlfd 31,-8(1)\n");
2114 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
2116 if (must_save_cr ())
2117 asm_fprintf (file, "\tmtcrf %d,12\n",
2118 (regs_ever_live[70] != 0) * 0x20
2119 + (regs_ever_live[71] != 0) * 0x10
2120 + (regs_ever_live[72] != 0) * 0x8);
2122 /* If we have to restore more than two FP registers, branch to the
2123 restore function. It will return to our caller. */
2124 if (first_fp_reg < 62)
2125 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
2127 asm_fprintf (file, "\t{br|blr}\n");
2130 /* Output a traceback table here. See /usr/include/sys/debug.h for info
2133 We don't output a traceback table if -finhibit-size-directive was
2134 used. The documentation for -finhibit-size-directive reads
2135 ``don't output a @code{.size} assembler directive, or anything
2136 else that would cause trouble if the function is split in the
2137 middle, and the two halves are placed at locations far apart in
2138 memory.'' The traceback table has this property, since it
2139 includes the offset from the start of the function to the
2140 traceback table itself.
2142 System V.4 Powerpc's (and the embedded ABI derived from it) use a
2143 different traceback table located before the prologue. */
2144 #ifndef USING_SVR4_H
2145 if (! flag_inhibit_size_directive)
2147 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
2148 int fixed_parms, float_parms, parm_info;
2151 /* Need label immediately before tbtab, so we can compute its offset
2152 from the function start. */
2155 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2156 ASM_OUTPUT_LABEL (file, fname);
2158 /* The .tbtab pseudo-op can only be used for the first eight
2159 expressions, since it can't handle the possibly variable
2160 length fields that follow. However, if you omit the optional
2161 fields, the assembler outputs zeros for all optional fields
2162 anyways, giving each variable length field is minimum length
2163 (as defined in sys/debug.h). Thus we can not use the .tbtab
2164 pseudo-op at all. */
2166 /* An all-zero word flags the start of the tbtab, for debuggers
2167 that have to find it by searching forward from the entry
2168 point or from the current pc. */
2169 fprintf (file, "\t.long 0\n");
2171 /* Tbtab format type. Use format type 0. */
2172 fprintf (file, "\t.byte 0,");
2174 /* Language type. Unfortunately, there doesn't seem to be any
2175 official way to get this info, so we use language_string. C
2176 is 0. C++ is 9. No number defined for Obj-C, so use the
2177 value for C for now. */
2178 if (! strcmp (language_string, "GNU C")
2179 || ! strcmp (language_string, "GNU Obj-C"))
2181 else if (! strcmp (language_string, "GNU F77"))
2183 else if (! strcmp (language_string, "GNU Ada"))
2185 else if (! strcmp (language_string, "GNU PASCAL"))
2187 else if (! strcmp (language_string, "GNU C++"))
2191 fprintf (file, "%d,", i);
2193 /* 8 single bit fields: global linkage (not set for C extern linkage,
2194 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
2195 from start of procedure stored in tbtab, internal function, function
2196 has controlled storage, function has no toc, function uses fp,
2197 function logs/aborts fp operations. */
2198 /* Assume that fp operations are used if any fp reg must be saved. */
2199 fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1));
2201 /* 6 bitfields: function is interrupt handler, name present in
2202 proc table, function calls alloca, on condition directives
2203 (controls stack walks, 3 bits), saves condition reg, saves
2205 /* The `function calls alloca' bit seems to be set whenever reg 31 is
2206 set up as a frame pointer, even when there is no alloca call. */
2207 fprintf (file, "%d,",
2208 ((1 << 6) | (frame_pointer_needed << 5)
2209 | (must_save_cr () << 1) | (regs_ever_live[65])));
2211 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
2213 fprintf (file, "%d,",
2214 (must_push << 7) | (64 - first_fp_reg_to_save ()));
2216 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
2217 fprintf (file, "%d,", (32 - first_reg_to_save ()));
2220 /* Compute the parameter info from the function decl argument
2223 int next_parm_info_bit;
2225 next_parm_info_bit = 31;
2230 for (decl = DECL_ARGUMENTS (current_function_decl);
2231 decl; decl = TREE_CHAIN (decl))
2233 rtx parameter = DECL_INCOMING_RTL (decl);
2234 enum machine_mode mode = GET_MODE (parameter);
2236 if (GET_CODE (parameter) == REG)
2238 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2246 else if (mode == DFmode)
2251 /* If only one bit will fit, don't or in this entry. */
2252 if (next_parm_info_bit > 0)
2253 parm_info |= (bits << (next_parm_info_bit - 1));
2254 next_parm_info_bit -= 2;
2258 fixed_parms += ((GET_MODE_SIZE (mode)
2259 + (UNITS_PER_WORD - 1))
2261 next_parm_info_bit -= 1;
2267 /* Number of fixed point parameters. */
2268 /* This is actually the number of words of fixed point parameters; thus
2269 an 8 byte struct counts as 2; and thus the maximum value is 8. */
2270 fprintf (file, "%d,", fixed_parms);
2272 /* 2 bitfields: number of floating point parameters (7 bits), parameters
2274 /* This is actually the number of fp registers that hold parameters;
2275 and thus the maximum value is 13. */
2276 /* Set parameters on stack bit if parameters are not in their original
2277 registers, regardless of whether they are on the stack? Xlc
2278 seems to set the bit when not optimizing. */
2279 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
2281 /* Optional fields follow. Some are variable length. */
2283 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
2285 /* There is an entry for each parameter in a register, in the order that
2286 they occur in the parameter list. Any intervening arguments on the
2287 stack are ignored. If the list overflows a long (max possible length
2288 34 bits) then completely leave off all elements that don't fit. */
2289 /* Only emit this long if there was at least one parameter. */
2290 if (fixed_parms || float_parms)
2291 fprintf (file, "\t.long %d\n", parm_info);
2293 /* Offset from start of code to tb table. */
2294 fprintf (file, "\t.long ");
2295 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2296 RS6000_OUTPUT_BASENAME (file, fname);
2297 fprintf (file, "-.");
2298 RS6000_OUTPUT_BASENAME (file, fname);
2299 fprintf (file, "\n");
2301 /* Interrupt handler mask. */
2302 /* Omit this long, since we never set the interrupt handler bit
2305 /* Number of CTL (controlled storage) anchors. */
2306 /* Omit this long, since the has_ctl bit is never set above. */
2308 /* Displacement into stack of each CTL anchor. */
2309 /* Omit this list of longs, because there are no CTL anchors. */
2311 /* Length of function name. */
2312 fprintf (file, "\t.short %d\n", strlen (fname));
2314 /* Function name. */
2315 assemble_string (fname, strlen (fname));
2317 /* Register for alloca automatic storage; this is always reg 31.
2318 Only emit this if the alloca bit was set above. */
2319 if (frame_pointer_needed)
2320 fprintf (file, "\t.byte 31\n");
2322 #endif /* !USING_SVR4_H */
2325 /* Output a TOC entry. We derive the entry name from what is
2329 output_toc (file, x, labelno)
2340 if (TARGET_MINIMAL_TOC)
2342 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
2343 fprintf (file, "%d = .-", labelno);
2344 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
2345 fprintf (file, "1\n");
2348 #endif /* USING_SVR4_H */
2349 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
2351 /* Handle FP constants specially. Note that if we have a minimal
2352 TOC, things we put here aren't actually in the TOC, so we can allow
2354 if (GET_CODE (x) == CONST_DOUBLE
2355 && GET_MODE (x) == DFmode
2356 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2361 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2362 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
2363 if (TARGET_MINIMAL_TOC)
2364 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
2366 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
2367 l[0], l[1], l[0], l[1]);
2370 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
2371 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2373 rtx val = operand_subword (x, 0, 0, SFmode);
2375 if (val == 0 || GET_CODE (val) != CONST_INT)
2378 if (TARGET_MINIMAL_TOC)
2379 fprintf (file, "\t.long %d\n", INTVAL (val));
2381 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
2385 if (GET_CODE (x) == CONST)
2387 base = XEXP (XEXP (x, 0), 0);
2388 offset = INTVAL (XEXP (XEXP (x, 0), 1));
2391 if (GET_CODE (base) == SYMBOL_REF)
2392 name = XSTR (base, 0);
2393 else if (GET_CODE (base) == LABEL_REF)
2394 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
2395 else if (GET_CODE (base) == CODE_LABEL)
2396 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
2400 if (TARGET_MINIMAL_TOC)
2401 fprintf (file, "\t.long ");
2404 fprintf (file, "\t.tc ");
2405 RS6000_OUTPUT_BASENAME (file, name);
2408 fprintf (file, ".N%d", - offset);
2410 fprintf (file, ".P%d", offset);
2412 fprintf (file, "[TC],");
2414 output_addr_const (file, x);
2415 fprintf (file, "\n");
2418 /* Output an assembler pseudo-op to write an ASCII string of N characters
2419 starting at P to FILE.
2421 On the RS/6000, we have to do this using the .byte operation and
2422 write out special characters outside the quoted string.
2423 Also, the assembler is broken; very long strings are truncated,
2424 so we must artificially break them up early. */
2427 output_ascii (file, p, n)
2433 int i, count_string;
2434 char *for_string = "\t.byte \"";
2435 char *for_decimal = "\t.byte ";
2436 char *to_close = NULL;
2439 for (i = 0; i < n; i++)
2442 if (c >= ' ' && c < 0177)
2445 fputs (for_string, file);
2448 /* Write two quotes to get one. */
2456 for_decimal = "\"\n\t.byte ";
2460 if (count_string >= 512)
2462 fputs (to_close, file);
2464 for_string = "\t.byte \"";
2465 for_decimal = "\t.byte ";
2473 fputs (for_decimal, file);
2474 fprintf (file, "%d", c);
2476 for_string = "\n\t.byte \"";
2483 /* Now close the string if we have written one. Then end the line. */
2485 fprintf (file, to_close);
2488 /* Generate a unique section name for FILENAME for a section type
2489 represented by SECTION_DESC. Output goes into BUF.
2491 SECTION_DESC can be any string, as long as it is different for each
2492 possible section type.
2494 We name the section in the same manner as xlc. The name begins with an
2495 underscore followed by the filename (after stripping any leading directory
2496 names) with the last period replaced by the string SECTION_DESC. If
2497 FILENAME does not contain a period, SECTION_DESC is appended to the end of
2501 rs6000_gen_section_name (buf, filename, section_desc)
2506 char *q, *after_last_slash, *last_period;
2510 after_last_slash = filename;
2511 for (q = filename; *q; q++)
2514 after_last_slash = q + 1;
2519 len = strlen (after_last_slash) + strlen (section_desc) + 2;
2520 *buf = (char *) permalloc (len);
2525 for (q = after_last_slash; *q; q++)
2527 if (q == last_period)
2529 strcpy (p, section_desc);
2530 p += strlen (section_desc);
2533 else if (isalnum (*q))
2537 if (last_period == 0)
2538 strcpy (p, section_desc);
2543 /* Write function profiler code. */
2546 output_function_profiler (file, labelno)
2553 /* The last used parameter register. */
2558 /* Set up a TOC entry for the profiler label. */
2560 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
2561 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
2562 if (TARGET_MINIMAL_TOC)
2564 fprintf (file, "\t.long ");
2565 assemble_name (file, buf);
2566 fprintf (file, "\n");
2570 fprintf (file, "\t.tc\t");
2571 assemble_name (file, buf);
2572 fprintf (file, "[TC],");
2573 assemble_name (file, buf);
2574 fprintf (file, "\n");
2578 /* Figure out last used parameter register. The proper thing to do is
2579 to walk incoming args of the function. A function might have live
2580 parameter registers even if it has no incoming args. */
2582 for (last_parm_reg = 10;
2583 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
2587 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2588 it might be set up as the frame pointer. */
2590 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2591 fprintf (file, "\tai %d,%d,0\n", j, i);
2593 /* Load location address into r3, and call mcount. */
2595 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
2596 fprintf (file, "\tl 3,");
2597 assemble_name (file, buf);
2598 fprintf (file, "(2)\n\tbl .mcount\n");
2600 /* Restore parameter registers. */
2602 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2603 fprintf (file, "\tai %d,%d,0\n", i, j);
2607 /* Adjust the cost of a scheduling dependency. Return the new cost of
2608 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2611 rs6000_adjust_cost (insn, link, dep_insn, cost)
2617 if (! recog_memoized (insn))
2620 if (REG_NOTE_KIND (link) != 0)
2623 if (REG_NOTE_KIND (link) == 0)
2625 /* Data dependency; DEP_INSN writes a register that INSN reads some
2628 /* Tell the first scheduling pass about the latency between a mtctr
2629 and bctr (and mtlr and br/blr). The first scheduling pass will not
2630 know about this latency since the mtctr instruction, which has the
2631 latency associated to it, will be generated by reload. */
2632 if (get_attr_type (insn) == TYPE_JMPREG)
2633 return TARGET_POWER ? 5 : 4;
2635 /* Fall out to return default cost. */