1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
38 extern char *language_string;
39 extern int profile_block_flag;
41 #define min(A,B) ((A) < (B) ? (A) : (B))
42 #define max(A,B) ((A) > (B) ? (A) : (B))
46 enum processor_type rs6000_cpu;
47 char *rs6000_cpu_string;
49 /* Set to non-zero by "fix" operation to indicate that itrunc and
50 uitrunc must be defined. */
52 int rs6000_trunc_used;
54 /* Set to non-zero once they have been defined. */
56 static int trunc_defined;
58 /* Save information from a "cmpxx" operation until the branch or scc is
61 rtx rs6000_compare_op0, rs6000_compare_op1;
62 int rs6000_compare_fp_p;
64 /* Override command line options. Mostly we process the processor
65 type and sometimes adjust other TARGET_ options. */
68 rs6000_override_options ()
72 /* Simplify the entries below by making a mask for any POWER
73 variant and any PowerPC variant. */
75 #define POWER_MASKS (MASK_POWER | MASK_POWER2)
76 #define POWERPC_MASKS (MASK_POWERPC | MASK_POWERPCSQR | MASK_POWERPC64)
80 char *name; /* Canonical processor name. */
81 enum processor_type processor; /* Processor type enum value. */
82 int target_enable; /* Target flags to enable. */
83 int target_disable; /* Target flags to disable. */
84 } processor_target_table[]
85 = {{"all", PROCESSOR_DEFAULT, 0, POWER_MASKS | POWERPC_MASKS},
86 {"rios", PROCESSOR_RIOS1, MASK_POWER, MASK_POWER2 | POWERPC_MASKS},
87 {"rios1", PROCESSOR_RIOS1, MASK_POWER, MASK_POWER2 | POWERPC_MASKS},
88 {"rsc", PROCESSOR_PPC601, MASK_POWER, MASK_POWER2 | POWERPC_MASKS},
89 {"rsc1", PROCESSOR_PPC601, MASK_POWER, MASK_POWER2 | POWERPC_MASKS},
90 {"rios2", PROCESSOR_RIOS2, MASK_POWER | MASK_POWER2 , POWERPC_MASKS},
91 {"601", PROCESSOR_PPC601,
92 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS,
93 MASK_POWER2 | MASK_POWERPCSQR | MASK_POWERPC64},
94 {"mpc601", PROCESSOR_PPC601,
95 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS,
96 MASK_POWER2 | MASK_POWERPCSQR | MASK_POWERPC64},
97 {"ppc601", PROCESSOR_PPC601,
98 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS,
99 MASK_POWER2 | MASK_POWERPCSQR | MASK_POWERPC64},
100 {"603", PROCESSOR_PPC603,
101 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
102 POWER_MASKS | MASK_POWERPC64},
103 {"mpc603", PROCESSOR_PPC603,
104 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
105 POWER_MASKS | MASK_POWERPC64},
106 {"ppc603", PROCESSOR_PPC603,
107 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
108 POWER_MASKS | MASK_POWERPC64},
109 {"604", PROCESSOR_PPC604,
110 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
111 POWER_MASKS | MASK_POWERPC64},
112 {"mpc604", PROCESSOR_PPC604,
113 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
114 POWER_MASKS | MASK_POWERPC64},
115 {"ppc604", PROCESSOR_PPC604,
116 MASK_POWERPC | MASK_POWERPCSQR | MASK_NEW_MNEMONICS,
117 POWER_MASKS | MASK_POWERPC64},
118 {"620", PROCESSOR_PPC620,
119 (MASK_POWERPC | MASK_POWERPCSQR | MASK_POWERPC64
120 | MASK_NEW_MNEMONICS),
122 {"mpc620", PROCESSOR_PPC620,
123 (MASK_POWERPC | MASK_POWERPCSQR | MASK_POWERPC64
124 | MASK_NEW_MNEMONICS),
126 {"ppc620", PROCESSOR_PPC620,
127 (MASK_POWERPC | MASK_POWERPCSQR | MASK_POWERPC64
128 | MASK_NEW_MNEMONICS),
131 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
133 profile_block_flag = 0;
135 /* Identify the processor type */
136 if (rs6000_cpu_string == 0)
137 rs6000_cpu = PROCESSOR_DEFAULT;
140 for (i = 0; i < ptt_size; i++)
141 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
143 rs6000_cpu = processor_target_table[i].processor;
144 target_flags |= processor_target_table[i].target_enable;
145 target_flags &= ~processor_target_table[i].target_disable;
151 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
152 rs6000_cpu_string = "default";
153 rs6000_cpu = PROCESSOR_DEFAULT;
158 /* Return non-zero if this function is known to have a null epilogue. */
163 return (reload_completed
164 && first_reg_to_save () == 32
165 && first_fp_reg_to_save () == 64
166 && ! regs_ever_live[65]
167 && ! rs6000_pushes_stack ());
170 /* Returns 1 always. */
173 any_operand (op, mode)
175 enum machine_mode mode;
180 /* Return 1 if OP is a constant that can fit in a D field. */
183 short_cint_operand (op, mode)
185 enum machine_mode mode;
187 return (GET_CODE (op) == CONST_INT
188 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
191 /* Similar for a unsigned D field. */
194 u_short_cint_operand (op, mode)
196 enum machine_mode mode;
198 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
201 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
204 non_short_cint_operand (op, mode)
206 enum machine_mode mode;
208 return (GET_CODE (op) == CONST_INT
209 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
212 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
216 gpc_reg_operand (op, mode)
218 enum machine_mode mode;
220 return (register_operand (op, mode)
221 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
224 /* Returns 1 if OP is either a pseudo-register or a register denoting a
228 cc_reg_operand (op, mode)
230 enum machine_mode mode;
232 return (register_operand (op, mode)
233 && (GET_CODE (op) != REG
234 || REGNO (op) >= FIRST_PSEUDO_REGISTER
235 || CR_REGNO_P (REGNO (op))));
238 /* Returns 1 if OP is either a constant integer valid for a D-field or a
239 non-special register. If a register, it must be in the proper mode unless
243 reg_or_short_operand (op, mode)
245 enum machine_mode mode;
247 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
250 /* Similar, except check if the negation of the constant would be valid for
254 reg_or_neg_short_operand (op, mode)
256 enum machine_mode mode;
258 if (GET_CODE (op) == CONST_INT)
259 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
261 return gpc_reg_operand (op, mode);
264 /* Return 1 if the operand is either a register or an integer whose high-order
268 reg_or_u_short_operand (op, mode)
270 enum machine_mode mode;
272 if (GET_CODE (op) == CONST_INT
273 && (INTVAL (op) & 0xffff0000) == 0)
276 return gpc_reg_operand (op, mode);
279 /* Return 1 is the operand is either a non-special register or ANY
283 reg_or_cint_operand (op, mode)
285 enum machine_mode mode;
287 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
290 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
291 register with one instruction per word. For SFmode, this means that
292 the low 16-bits are zero. For DFmode, it means the low 16-bits of
293 the first word are zero and the high 16 bits of the second word
294 are zero (usually all bits in the low-order word will be zero).
296 We only do this if we can safely read CONST_DOUBLE_{LOW,HIGH}. */
299 easy_fp_constant (op, mode)
301 register enum machine_mode mode;
305 if (GET_CODE (op) != CONST_DOUBLE
306 || GET_MODE (op) != mode
307 || GET_MODE_CLASS (mode) != MODE_FLOAT)
310 high = operand_subword (op, 0, 0, mode);
311 low = operand_subword (op, 1, 0, mode);
313 if (high == 0 || GET_CODE (high) != CONST_INT || (INTVAL (high) & 0xffff))
316 return (mode == SFmode
317 || (low != 0 && GET_CODE (low) == CONST_INT
318 && (INTVAL (low) & 0xffff0000) == 0));
321 /* Return 1 if the operand is either a floating-point register, a pseudo
322 register, or memory. */
325 fp_reg_or_mem_operand (op, mode)
327 enum machine_mode mode;
329 return (memory_operand (op, mode)
330 || (register_operand (op, mode)
331 && (GET_CODE (op) != REG
332 || REGNO (op) >= FIRST_PSEUDO_REGISTER
333 || FP_REGNO_P (REGNO (op)))));
336 /* Return 1 if the operand is either an easy FP constant (see above) or
340 mem_or_easy_const_operand (op, mode)
342 enum machine_mode mode;
344 return memory_operand (op, mode) || easy_fp_constant (op, mode);
347 /* Return 1 if the operand is either a non-special register or an item
348 that can be used as the operand of an SI add insn. */
351 add_operand (op, mode)
353 enum machine_mode mode;
355 return (reg_or_short_operand (op, mode)
356 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
359 /* Return 1 if OP is a constant but not a valid add_operand. */
362 non_add_cint_operand (op, mode)
364 enum machine_mode mode;
366 return (GET_CODE (op) == CONST_INT
367 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
368 && (INTVAL (op) & 0xffff) != 0);
371 /* Return 1 if the operand is a non-special register or a constant that
372 can be used as the operand of an OR or XOR insn on the RS/6000. */
375 logical_operand (op, mode)
377 enum machine_mode mode;
379 return (gpc_reg_operand (op, mode)
380 || (GET_CODE (op) == CONST_INT
381 && ((INTVAL (op) & 0xffff0000) == 0
382 || (INTVAL (op) & 0xffff) == 0)));
385 /* Return 1 if C is a constant that is not a logical operand (as
389 non_logical_cint_operand (op, mode)
391 enum machine_mode mode;
393 return (GET_CODE (op) == CONST_INT
394 && (INTVAL (op) & 0xffff0000) != 0
395 && (INTVAL (op) & 0xffff) != 0);
398 /* Return 1 if C is a constant that can be encoded in a mask on the
399 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
400 Reject all ones and all zeros, since these should have been optimized
401 away and confuse the making of MB and ME. */
411 if (c == 0 || c == ~0)
414 last_bit_value = c & 1;
416 for (i = 1; i < 32; i++)
417 if (((c >>= 1) & 1) != last_bit_value)
418 last_bit_value ^= 1, transitions++;
420 return transitions <= 2;
423 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
426 mask_operand (op, mode)
428 enum machine_mode mode;
430 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
433 /* Return 1 if the operand is either a non-special register or a
434 constant that can be used as the operand of an RS/6000 logical AND insn. */
437 and_operand (op, mode)
439 enum machine_mode mode;
441 return (reg_or_short_operand (op, mode)
442 || logical_operand (op, mode)
443 || mask_operand (op, mode));
446 /* Return 1 if the operand is a constant but not a valid operand for an AND
450 non_and_cint_operand (op, mode)
452 enum machine_mode mode;
454 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
457 /* Return 1 if the operand is a general register or memory operand. */
460 reg_or_mem_operand (op, mode)
462 register enum machine_mode mode;
464 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
467 /* Return 1 if the operand, used inside a MEM, is a valid first argument
468 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
472 call_operand (op, mode)
474 enum machine_mode mode;
476 if (mode != VOIDmode && GET_MODE (op) != mode)
479 return (GET_CODE (op) == SYMBOL_REF
480 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
484 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
488 current_file_function_operand (op, mode)
490 enum machine_mode mode;
492 return (GET_CODE (op) == SYMBOL_REF
493 && (SYMBOL_REF_FLAG (op)
494 || op == XEXP (DECL_RTL (current_function_decl), 0)));
498 /* Return 1 if this operand is a valid input for a move insn. */
501 input_operand (op, mode)
503 enum machine_mode mode;
505 /* Memory is always valid. */
506 if (memory_operand (op, mode))
509 /* For floating-point, easy constants are valid. */
510 if (GET_MODE_CLASS (mode) == MODE_FLOAT
512 && easy_fp_constant (op, mode))
515 /* For floating-point or multi-word mode, the only remaining valid type
517 if (GET_MODE_CLASS (mode) == MODE_FLOAT
518 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
519 return register_operand (op, mode);
521 /* The only cases left are integral modes one word or smaller (we
522 do not get called for MODE_CC values). These can be in any
524 if (register_operand (op, mode))
527 /* For HImode and QImode, any constant is valid. */
528 if ((mode == HImode || mode == QImode)
529 && GET_CODE (op) == CONST_INT)
532 /* Otherwise, we will be doing this SET with an add, so anything valid
533 for an add will be valid. */
534 return add_operand (op, mode);
537 /* Return 1 if OP is a load multiple operation. It is known to be a
538 PARALLEL and the first section will be tested. */
541 load_multiple_operation (op, mode)
543 enum machine_mode mode;
545 int count = XVECLEN (op, 0);
550 /* Perform a quick check so we don't blow up below. */
552 || GET_CODE (XVECEXP (op, 0, 0)) != SET
553 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
554 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
557 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
558 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
560 for (i = 1; i < count; i++)
562 rtx elt = XVECEXP (op, 0, i);
564 if (GET_CODE (elt) != SET
565 || GET_CODE (SET_DEST (elt)) != REG
566 || GET_MODE (SET_DEST (elt)) != SImode
567 || REGNO (SET_DEST (elt)) != dest_regno + i
568 || GET_CODE (SET_SRC (elt)) != MEM
569 || GET_MODE (SET_SRC (elt)) != SImode
570 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
571 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
572 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
573 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
580 /* Similar, but tests for store multiple. Here, the second vector element
581 is a CLOBBER. It will be tested later. */
584 store_multiple_operation (op, mode)
586 enum machine_mode mode;
588 int count = XVECLEN (op, 0) - 1;
593 /* Perform a quick check so we don't blow up below. */
595 || GET_CODE (XVECEXP (op, 0, 0)) != SET
596 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
597 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
600 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
601 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
603 for (i = 1; i < count; i++)
605 rtx elt = XVECEXP (op, 0, i + 1);
607 if (GET_CODE (elt) != SET
608 || GET_CODE (SET_SRC (elt)) != REG
609 || GET_MODE (SET_SRC (elt)) != SImode
610 || REGNO (SET_SRC (elt)) != src_regno + i
611 || GET_CODE (SET_DEST (elt)) != MEM
612 || GET_MODE (SET_DEST (elt)) != SImode
613 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
614 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
615 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
616 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
623 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
624 We only check the opcode against the mode of the CC value here. */
627 branch_comparison_operator (op, mode)
629 enum machine_mode mode;
631 enum rtx_code code = GET_CODE (op);
632 enum machine_mode cc_mode;
634 if (GET_RTX_CLASS (code) != '<')
637 cc_mode = GET_MODE (XEXP (op, 0));
638 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
641 if ((code == GT || code == LT || code == GE || code == LE)
642 && cc_mode == CCUNSmode)
645 if ((code == GTU || code == LTU || code == GEU || code == LEU)
646 && (cc_mode != CCUNSmode))
652 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
653 We check the opcode against the mode of the CC value and disallow EQ or
654 NE comparisons for integers. */
657 scc_comparison_operator (op, mode)
659 enum machine_mode mode;
661 enum rtx_code code = GET_CODE (op);
662 enum machine_mode cc_mode;
664 if (GET_MODE (op) != mode && mode != VOIDmode)
667 if (GET_RTX_CLASS (code) != '<')
670 cc_mode = GET_MODE (XEXP (op, 0));
671 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
674 if (code == NE && cc_mode != CCFPmode)
677 if ((code == GT || code == LT || code == GE || code == LE)
678 && cc_mode == CCUNSmode)
681 if ((code == GTU || code == LTU || code == GEU || code == LEU)
682 && (cc_mode != CCUNSmode))
685 if (cc_mode == CCEQmode && code != EQ && code != NE)
691 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
692 mask required to convert the result of a rotate insn into a shift
693 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
696 includes_lshift_p (shiftop, andop)
697 register rtx shiftop;
700 int shift_mask = (~0 << INTVAL (shiftop));
702 return (INTVAL (andop) & ~shift_mask) == 0;
705 /* Similar, but for right shift. */
708 includes_rshift_p (shiftop, andop)
709 register rtx shiftop;
712 unsigned shift_mask = ~0;
714 shift_mask >>= INTVAL (shiftop);
716 return (INTVAL (andop) & ~ shift_mask) == 0;
719 /* Return the register class of a scratch register needed to copy IN into
720 or out of a register in CLASS in MODE. If it can be done directly,
721 NO_REGS is returned. */
724 secondary_reload_class (class, mode, in)
725 enum reg_class class;
726 enum machine_mode mode;
729 int regno = true_regnum (in);
731 if (regno >= FIRST_PSEUDO_REGISTER)
734 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
736 if (class == GENERAL_REGS || class == BASE_REGS
737 || (regno >= 0 && INT_REGNO_P (regno)))
740 /* Constants, memory, and FP registers can go into FP registers. */
741 if ((regno == -1 || FP_REGNO_P (regno))
742 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
745 /* We can copy among the CR registers. */
746 if ((class == CR_REGS || class == CR0_REGS)
747 && regno >= 0 && CR_REGNO_P (regno))
750 /* Otherwise, we need GENERAL_REGS. */
754 /* Given a comparison operation, return the bit number in CCR to test. We
755 know this is a valid comparison.
757 SCC_P is 1 if this is for an scc. That means that %D will have been
758 used instead of %C, so the bits will be in different places.
760 Return -1 if OP isn't a valid comparison for some reason. */
767 enum rtx_code code = GET_CODE (op);
768 enum machine_mode cc_mode;
772 if (GET_RTX_CLASS (code) != '<')
775 cc_mode = GET_MODE (XEXP (op, 0));
776 cc_regnum = REGNO (XEXP (op, 0));
777 base_bit = 4 * (cc_regnum - 68);
779 /* In CCEQmode cases we have made sure that the result is always in the
780 third bit of the CR field. */
782 if (cc_mode == CCEQmode)
788 return scc_p ? base_bit + 3 : base_bit + 2;
797 /* If floating-point, we will have done a cror to put the bit in the
798 unordered position. So test that bit. For integer, this is ! LT
799 unless this is an scc insn. */
800 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
803 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
810 /* Print an operand. Recognize special options, documented below. */
813 print_operand (file, x, code)
821 /* These macros test for integers and extract the low-order bits. */
823 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
824 && GET_MODE (X) == VOIDmode)
826 #define INT_LOWPART(X) \
827 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
832 /* Write out an instruction after the call which may be replaced
833 with glue code by the loader. This depends on the AIX version. */
834 asm_fprintf (file, RS6000_CALL_GLUE);
838 /* If X is a constant integer whose low-order 5 bits are zero,
839 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
840 in the AIX assembler where "sri" with a zero shift count
841 write a trash instruction. */
842 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
849 /* Low-order 16 bits of constant, unsigned. */
851 output_operand_lossage ("invalid %%b value");
853 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
857 /* This is an optional cror needed for LE or GE floating-point
858 comparisons. Otherwise write nothing. */
859 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
860 && GET_MODE (XEXP (x, 0)) == CCFPmode)
862 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
864 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
865 base_bit + 2, base_bit + (GET_CODE (x) == GE));
870 /* Similar, except that this is for an scc, so we must be able to
871 encode the test in a single bit that is one. We do the above
872 for any LE, GE, GEU, or LEU and invert the bit for NE. */
873 if (GET_CODE (x) == LE || GET_CODE (x) == GE
874 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
876 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
878 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
880 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
883 else if (GET_CODE (x) == NE)
885 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
887 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
888 base_bit + 2, base_bit + 2);
893 /* X is a CR register. Print the number of the third bit of the CR */
894 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
895 output_operand_lossage ("invalid %%E value");
897 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
901 /* X is a CR register. Print the shift count needed to move it
902 to the high-order four bits. */
903 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
904 output_operand_lossage ("invalid %%f value");
906 fprintf (file, "%d", 4 * (REGNO (x) - 68));
910 /* Similar, but print the count for the rotate in the opposite
912 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
913 output_operand_lossage ("invalid %%F value");
915 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
919 /* X is a constant integer. If it is negative, print "m",
920 otherwise print "z". This is to make a aze or ame insn. */
921 if (GET_CODE (x) != CONST_INT)
922 output_operand_lossage ("invalid %%G value");
923 else if (INTVAL (x) >= 0)
930 /* If constant, output low-order five bits. Otherwise,
933 fprintf (file, "%d", INT_LOWPART (x) & 31);
935 print_operand (file, x, 0);
939 /* X must be a constant. Output the low order 5 bits plus 24. */
941 output_operand_lossage ("invalid %%H value");
943 fprintf (file, "%d", (INT_LOWPART (x) + 24) & 31);
947 /* Print `i' if this is a constant, else nothing. */
953 /* Write the bit number in CCR for jump. */
956 output_operand_lossage ("invalid %%j code");
958 fprintf (file, "%d", i);
962 /* Similar, but add one for shift count in rlinm for scc and pass
963 scc flag to `ccr_bit'. */
966 output_operand_lossage ("invalid %%J code");
968 /* If we want bit 31, write a shift count of zero, not 32. */
969 fprintf (file, "%d", i == 31 ? 0 : i + 1);
973 /* X must be a constant. Write the 1's complement of the
976 output_operand_lossage ("invalid %%k value");
978 fprintf (file, "%d", ~ INT_LOWPART (x));
982 /* Write second word of DImode or DFmode reference. Works on register
983 or non-indexed memory only. */
984 if (GET_CODE (x) == REG)
985 fprintf (file, "%d", REGNO (x) + 1);
986 else if (GET_CODE (x) == MEM)
988 /* Handle possible auto-increment. Since it is pre-increment and
989 we have already done it, we can just use an offset of four. */
990 if (GET_CODE (XEXP (x, 0)) == PRE_INC
991 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
992 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
994 output_address (plus_constant (XEXP (x, 0), 4));
999 /* MB value for a mask operand. */
1000 if (! mask_operand (x, VOIDmode))
1001 output_operand_lossage ("invalid %%m value");
1003 val = INT_LOWPART (x);
1005 /* If the high bit is set and the low bit is not, the value is zero.
1006 If the high bit is zero, the value is the first 1 bit we find from
1008 if (val < 0 && (val & 1) == 0)
1010 fprintf (file, "0");
1015 for (i = 1; i < 32; i++)
1016 if ((val <<= 1) < 0)
1018 fprintf (file, "%d", i);
1022 /* Otherwise, look for the first 0 bit from the right. The result is its
1023 number plus 1. We know the low-order bit is one. */
1024 for (i = 0; i < 32; i++)
1025 if (((val >>= 1) & 1) == 0)
1028 /* If we ended in ...01, I would be 0. The correct value is 31, so
1030 fprintf (file, "%d", 31 - i);
1034 /* ME value for a mask operand. */
1035 if (! mask_operand (x, VOIDmode))
1036 output_operand_lossage ("invalid %%m value");
1038 val = INT_LOWPART (x);
1040 /* If the low bit is set and the high bit is not, the value is 31.
1041 If the low bit is zero, the value is the first 1 bit we find from
1043 if ((val & 1) && val >= 0)
1048 else if ((val & 1) == 0)
1050 for (i = 0; i < 32; i++)
1051 if ((val >>= 1) & 1)
1054 /* If we had ....10, I would be 0. The result should be
1055 30, so we need 30 - i. */
1056 fprintf (file, "%d", 30 - i);
1060 /* Otherwise, look for the first 0 bit from the left. The result is its
1061 number minus 1. We know the high-order bit is one. */
1062 for (i = 0; i < 32; i++)
1063 if ((val <<= 1) >= 0)
1066 fprintf (file, "%d", i);
1070 /* Write the number of elements in the vector times 4. */
1071 if (GET_CODE (x) != PARALLEL)
1072 output_operand_lossage ("invalid %%N value");
1074 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1078 /* Similar, but subtract 1 first. */
1079 if (GET_CODE (x) != PARALLEL)
1080 output_operand_lossage ("invalid %%N value");
1082 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1086 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1088 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1089 output_operand_lossage ("invalid %%p value");
1091 fprintf (file, "%d", i);
1095 /* The operand must be an indirect memory reference. The result
1096 is the register number. */
1097 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1098 || REGNO (XEXP (x, 0)) >= 32)
1099 output_operand_lossage ("invalid %%P value");
1101 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1105 /* X is a CR register. Print the mask for `mtcrf'. */
1106 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1107 output_operand_lossage ("invalid %%R value");
1109 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1113 /* Low 5 bits of 32 - value */
1115 output_operand_lossage ("invalid %%s value");
1117 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1121 /* Low 5 bits of 31 - value */
1123 output_operand_lossage ("invalid %%S value");
1125 fprintf (file, "%d", (31 - INT_LOWPART (x)) & 31);
1129 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1130 All floating-point operations except NE branch true and integer
1131 EQ, LT, GT, LTU and GTU also branch true. */
1132 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1133 output_operand_lossage ("invalid %%t value");
1135 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1136 && GET_CODE (x) != NE)
1137 || GET_CODE (x) == EQ
1138 || GET_CODE (x) == LT || GET_CODE (x) == GT
1139 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1146 /* Opposite of 't': write 4 if this jump operation will branch if true,
1148 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1149 output_operand_lossage ("invalid %%t value");
1151 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1152 && GET_CODE (x) != NE)
1153 || GET_CODE (x) == EQ
1154 || GET_CODE (x) == LT || GET_CODE (x) == GT
1155 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1162 /* High-order 16 bits of constant. */
1164 output_operand_lossage ("invalid %%u value");
1166 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1170 /* Print `u' if this has an auto-increment or auto-decrement. */
1171 if (GET_CODE (x) == MEM
1172 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1173 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1178 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1181 fprintf (file, "%d",
1182 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1184 print_operand (file, x, 0);
1188 /* If constant, low-order 16 bits of constant, unsigned.
1189 Otherwise, write normally. */
1191 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1193 print_operand (file, x, 0);
1197 if (GET_CODE (x) == MEM
1198 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1203 /* Like 'L', for third word of TImode */
1204 if (GET_CODE (x) == REG)
1205 fprintf (file, "%d", REGNO (x) + 2);
1206 else if (GET_CODE (x) == MEM)
1208 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1209 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1210 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1212 output_address (plus_constant (XEXP (x, 0), 8));
1217 /* X is a SYMBOL_REF. Write out the name preceded by a
1218 period and without any trailing data in brackets. Used for function
1220 if (GET_CODE (x) != SYMBOL_REF)
1224 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1228 /* Like 'L', for last word of TImode. */
1229 if (GET_CODE (x) == REG)
1230 fprintf (file, "%d", REGNO (x) + 3);
1231 else if (GET_CODE (x) == MEM)
1233 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1234 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1235 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1237 output_address (plus_constant (XEXP (x, 0), 12));
1242 if (GET_CODE (x) == REG)
1243 fprintf (file, "%s", reg_names[REGNO (x)]);
1244 else if (GET_CODE (x) == MEM)
1246 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1247 know the width from the mode. */
1248 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1249 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
1250 REGNO (XEXP (XEXP (x, 0), 0)));
1251 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1252 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
1253 REGNO (XEXP (XEXP (x, 0), 0)));
1255 output_address (XEXP (x, 0));
1258 output_addr_const (file, x);
1262 output_operand_lossage ("invalid %%xn code");
1266 /* Print the address of an operand. */
1269 print_operand_address (file, x)
1273 if (GET_CODE (x) == REG)
1274 fprintf (file, "0(%d)", REGNO (x));
1275 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
1277 output_addr_const (file, x);
1278 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1279 of the toc pointer. */
1280 if (TARGET_MINIMAL_TOC)
1281 fprintf (file, "(30)");
1283 fprintf (file, "(2)");
1285 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
1287 if (REGNO (XEXP (x, 0)) == 0)
1288 fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1290 fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1)));
1292 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1293 fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1298 /* This page contains routines that are used to determine what the function
1299 prologue and epilogue code will do and write them out. */
1301 /* Return the first fixed-point register that is required to be saved. 32 if
1305 first_reg_to_save ()
1309 /* Find lowest numbered live register. */
1310 for (first_reg = 13; first_reg <= 31; first_reg++)
1311 if (regs_ever_live[first_reg])
1314 /* If profiling, then we must save/restore every register that contains
1315 a parameter before/after the .mcount call. Use registers from 30 down
1316 to 23 to do this. Don't use the frame pointer in reg 31.
1318 For now, save enough room for all of the parameter registers. */
1326 /* Similar, for FP regs. */
1329 first_fp_reg_to_save ()
1333 /* Find lowest numbered live register. */
1334 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
1335 if (regs_ever_live[first_reg])
1341 /* Return 1 if we need to save CR. */
1346 return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72];
1349 /* Compute the size of the save area in the stack, including the space for
1357 /* We have the six fixed words, plus the size of the register save
1358 areas, rounded to a double-word. */
1359 size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1366 /* Return non-zero if this function makes calls. */
1369 rs6000_makes_calls ()
1373 /* If we are profiling, we will be making a call to mcount. */
1377 for (insn = get_insns (); insn; insn = next_insn (insn))
1378 if (GET_CODE (insn) == CALL_INSN)
1384 /* Return non-zero if this function needs to push space on the stack. */
1387 rs6000_pushes_stack ()
1389 int total_size = (rs6000_sa_size () + get_frame_size ()
1390 + current_function_outgoing_args_size);
1392 /* We need to push the stack if a frame pointer is needed (because the
1393 stack might be dynamically adjusted), if we are debugging, if the
1394 total stack size is more than 220 bytes, or if we make calls. */
1396 return (frame_pointer_needed || write_symbols != NO_DEBUG
1398 || rs6000_makes_calls ());
1401 /* Write function prologue. */
1404 output_prolog (file, size)
1408 int first_reg = first_reg_to_save ();
1409 int must_push = rs6000_pushes_stack ();
1410 int first_fp_reg = first_fp_reg_to_save ();
1411 int basic_size = rs6000_sa_size ();
1412 int total_size = (basic_size + size + current_function_outgoing_args_size);
1414 /* Round size to multiple of 8 bytes. */
1415 total_size = (total_size + 7) & ~7;
1417 /* Write .extern for any function we will call to save and restore fp
1419 if (first_fp_reg < 62)
1420 fprintf (file, "\t.extern ._savef%d\n\t.extern ._restf%d\n",
1421 first_fp_reg - 32, first_fp_reg - 32);
1423 /* Write .extern for truncation routines, if needed. */
1424 if (rs6000_trunc_used && ! trunc_defined)
1426 fprintf (file, "\t.extern .itrunc\n\t.extern .uitrunc\n");
1430 /* If we have to call a function to save fpr's, or if we are doing profiling,
1431 then we will be using LR. */
1432 if (first_fp_reg < 62 || profile_flag)
1433 regs_ever_live[65] = 1;
1435 /* If we use the link register, get it into r0. */
1436 if (regs_ever_live[65])
1437 asm_fprintf (file, "\tmflr 0\n");
1439 /* If we need to save CR, put it into r12. */
1440 if (must_save_cr ())
1441 asm_fprintf (file, "\tmfcr 12\n");
1443 /* Do any required saving of fpr's. If only one or two to save, do it
1444 ourself. Otherwise, call function. Note that since they are statically
1445 linked, we do not need a nop following them. */
1446 if (first_fp_reg == 62)
1447 asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1448 else if (first_fp_reg == 63)
1449 asm_fprintf (file, "\tstfd 31,-8(1)\n");
1450 else if (first_fp_reg != 64)
1451 asm_fprintf (file, "\tbl ._savef%d\n", first_fp_reg - 32);
1453 /* Now save gpr's. */
1454 if (! TARGET_POWER || first_reg == 31)
1458 for (regno = first_reg,
1459 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1462 asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc);
1465 else if (first_reg != 32)
1466 asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg,
1467 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1469 /* Save lr if we used it. */
1470 if (regs_ever_live[65])
1471 asm_fprintf (file, "\t{st|stw} 0,8(1)\n");
1473 /* Save CR if we use any that must be preserved. */
1474 if (must_save_cr ())
1475 asm_fprintf (file, "\t{st|stw} 12,4(1)\n");
1477 /* Update stack and set back pointer. */
1480 if (total_size < 32767)
1481 asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size);
1484 asm_fprintf (file, "\t{cau|addis} 0,0,%d\n\t{oril|ori} 0,0,%d\n",
1485 (total_size >> 16) & 0xffff, total_size & 0xffff);
1486 asm_fprintf (file, "\t{sf|subfc} 12,0,1\n");
1487 asm_fprintf (file, "\t{st|stw} 1,0(12)\n\t{oril|ori} 1,12,0\n");
1491 /* Set frame pointer, if needed. */
1492 if (frame_pointer_needed)
1493 asm_fprintf (file, "\t{oril|ori} 31,1,0\n");
1495 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1496 TOC_TABLE address into register 30. */
1497 if (TARGET_MINIMAL_TOC && get_pool_size () != 0)
1498 asm_fprintf (file, "\t{l|lwz} 30,LCTOC..0(2)\n");
1501 /* Write function epilogue. */
1504 output_epilog (file, size)
1508 int first_reg = first_reg_to_save ();
1509 int must_push = rs6000_pushes_stack ();
1510 int first_fp_reg = first_fp_reg_to_save ();
1511 int basic_size = rs6000_sa_size ();
1512 int total_size = (basic_size + size + current_function_outgoing_args_size);
1513 rtx insn = get_last_insn ();
1515 /* Round size to multiple of 8 bytes. */
1516 total_size = (total_size + 7) & ~7;
1518 /* If the last insn was a BARRIER, we don't have to write anything except
1520 if (GET_CODE (insn) == NOTE)
1521 insn = prev_nonnote_insn (insn);
1522 if (insn == 0 || GET_CODE (insn) != BARRIER)
1524 /* If we have a frame pointer, a call to alloca, or a large stack
1525 frame, restore the old stack pointer using the backchain. Otherwise,
1526 we know what size to update it with. */
1527 if (frame_pointer_needed || current_function_calls_alloca
1528 || total_size > 32767)
1529 asm_fprintf (file, "\t{l|lwz} 1,0(1)\n");
1531 asm_fprintf (file, "\t{ai|addic} 1,1,%d\n", total_size);
1533 /* Get the old lr if we saved it. */
1534 if (regs_ever_live[65])
1535 asm_fprintf (file, "\t{l|lwz} 0,8(1)\n");
1537 /* Get the old cr if we saved it. */
1538 if (must_save_cr ())
1539 asm_fprintf (file, "\t{l|lwz} 12,4(1)\n");
1541 /* Set LR here to try to overlap restores below. */
1542 if (regs_ever_live[65])
1543 asm_fprintf (file, "\tmtlr 0\n");
1545 /* Restore gpr's. */
1546 if (! TARGET_POWER || first_reg == 31)
1550 for (regno = first_reg,
1551 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1554 asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc);
1557 else if (first_reg != 32)
1558 asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg,
1559 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1561 /* Restore fpr's if we can do it without calling a function. */
1562 if (first_fp_reg == 62)
1563 asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
1564 else if (first_fp_reg == 63)
1565 asm_fprintf (file, "\tlfd 31,-8(1)\n");
1567 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
1569 if (must_save_cr ())
1570 asm_fprintf (file, "\tmtcrf %d,12\n",
1571 (regs_ever_live[70] != 0) * 0x20
1572 + (regs_ever_live[71] != 0) * 0x10
1573 + (regs_ever_live[72] != 0) * 0x8);
1575 /* If we have to restore more than two FP registers, branch to the
1576 restore function. It will return to our caller. */
1577 if (first_fp_reg < 62)
1578 asm_fprintf (file, "\tb ._restf%d\n", first_fp_reg - 32);
1580 asm_fprintf (file, "\t{br|blr}\n");
1583 /* Output a traceback table here. See /usr/include/sys/debug.h for info
1586 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
1587 int fixed_parms, float_parms, parm_info;
1590 /* Need label immediately before tbtab, so we can compute its offset
1591 from the function start. */
1594 fprintf (file, "LT..");
1595 ASM_OUTPUT_LABEL (file, fname);
1597 /* The .tbtab pseudo-op can only be used for the first eight
1598 expressions, since it can't handle the possibly variable length
1599 fields that follow. However, if you omit the optional fields,
1600 the assembler outputs zeros for all optional fields anyways, giving each
1601 variable length field is minimum length (as defined in sys/debug.h).
1602 Thus we can not use the .tbtab pseudo-op at all. */
1604 /* An all-zero word flags the start of the tbtab, for debuggers that have
1605 to find it by searching forward from the entry point or from the
1607 fprintf (file, "\t.long 0\n");
1609 /* Tbtab format type. Use format type 0. */
1610 fprintf (file, "\t.byte 0,");
1612 /* Language type. Unfortunately, there doesn't seem to be any official way
1613 to get this info, so we use language_string. C is 0. C++ is 9.
1614 No number defined for Obj-C, so use the value for C for now. */
1615 if (! strcmp (language_string, "GNU C")
1616 || ! strcmp (language_string, "GNU Obj-C"))
1618 else if (! strcmp (language_string, "GNU F77"))
1620 else if (! strcmp (language_string, "GNU Ada"))
1622 else if (! strcmp (language_string, "GNU PASCAL"))
1624 else if (! strcmp (language_string, "GNU C++"))
1628 fprintf (file, "%d,", i);
1630 /* 8 single bit fields: global linkage (not set for C extern linkage,
1631 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
1632 from start of procedure stored in tbtab, internal function, function
1633 has controlled storage, function has no toc, function uses fp,
1634 function logs/aborts fp operations. */
1635 /* Assume that fp operations are used if any fp reg must be saved. */
1636 fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1));
1638 /* 6 bitfields: function is interrupt handler, name present in proc table,
1639 function calls alloca, on condition directives (controls stack walks,
1640 3 bits), saves condition reg, saves link reg. */
1641 /* The `function calls alloca' bit seems to be set whenever reg 31 is
1642 set up as a frame pointer, even when there is no alloca call. */
1643 fprintf (file, "%d,",
1644 ((1 << 6) | (frame_pointer_needed << 5)
1645 | (must_save_cr () << 1) | (regs_ever_live[65])));
1647 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
1649 fprintf (file, "%d,",
1650 (must_push << 7) | (64 - first_fp_reg_to_save ()));
1652 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
1653 fprintf (file, "%d,", (32 - first_reg_to_save ()));
1656 /* Compute the parameter info from the function decl argument list. */
1658 int next_parm_info_bit;
1660 next_parm_info_bit = 31;
1665 for (decl = DECL_ARGUMENTS (current_function_decl);
1666 decl; decl = TREE_CHAIN (decl))
1668 rtx parameter = DECL_INCOMING_RTL (decl);
1669 enum machine_mode mode = GET_MODE (parameter);
1671 if (GET_CODE (parameter) == REG)
1673 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1681 else if (mode == DFmode)
1686 /* If only one bit will fit, don't or in this entry. */
1687 if (next_parm_info_bit > 0)
1688 parm_info |= (bits << (next_parm_info_bit - 1));
1689 next_parm_info_bit -= 2;
1693 fixed_parms += ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1))
1695 next_parm_info_bit -= 1;
1701 /* Number of fixed point parameters. */
1702 /* This is actually the number of words of fixed point parameters; thus
1703 an 8 byte struct counts as 2; and thus the maximum value is 8. */
1704 fprintf (file, "%d,", fixed_parms);
1706 /* 2 bitfields: number of floating point parameters (7 bits), parameters
1708 /* This is actually the number of fp registers that hold parameters;
1709 and thus the maximum value is 13. */
1710 /* Set parameters on stack bit if parameters are not in their original
1711 registers, regardless of whether they are on the stack? Xlc
1712 seems to set the bit when not optimizing. */
1713 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
1715 /* Optional fields follow. Some are variable length. */
1717 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
1719 /* There is an entry for each parameter in a register, in the order that
1720 they occur in the parameter list. Any intervening arguments on the
1721 stack are ignored. If the list overflows a long (max possible length
1722 34 bits) then completely leave off all elements that don't fit. */
1723 /* Only emit this long if there was at least one parameter. */
1724 if (fixed_parms || float_parms)
1725 fprintf (file, "\t.long %d\n", parm_info);
1727 /* Offset from start of code to tb table. */
1728 fprintf (file, "\t.long LT..");
1729 RS6000_OUTPUT_BASENAME (file, fname);
1730 fprintf (file, "-.");
1731 RS6000_OUTPUT_BASENAME (file, fname);
1732 fprintf (file, "\n");
1734 /* Interrupt handler mask. */
1735 /* Omit this long, since we never set the interrupt handler bit above. */
1737 /* Number of CTL (controlled storage) anchors. */
1738 /* Omit this long, since the has_ctl bit is never set above. */
1740 /* Displacement into stack of each CTL anchor. */
1741 /* Omit this list of longs, because there are no CTL anchors. */
1743 /* Length of function name. */
1744 fprintf (file, "\t.short %d\n", strlen (fname));
1746 /* Function name. */
1747 assemble_string (fname, strlen (fname));
1749 /* Register for alloca automatic storage; this is always reg 31.
1750 Only emit this if the alloca bit was set above. */
1751 if (frame_pointer_needed)
1752 fprintf (file, "\t.byte 31\n");
1756 /* Output a TOC entry. We derive the entry name from what is
1760 output_toc (file, x, labelno)
1770 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
1772 /* Handle FP constants specially. Note that if we have a minimal
1773 TOC, things we put here aren't actually in the TOC, so we can allow
1775 if (GET_CODE (x) == CONST_DOUBLE
1776 && GET_MODE (x) == DFmode
1777 && TARGET_FLOAT_FORMAT == HOST_FLOAT_FORMAT
1778 && BITS_PER_WORD == HOST_BITS_PER_INT
1779 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
1781 if (TARGET_MINIMAL_TOC)
1782 fprintf (file, "\t.long %d\n\t.long %d\n",
1783 CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
1785 fprintf (file, "\t.tc FD_%x_%x[TC],%d,%d\n",
1786 CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x),
1787 CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
1790 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
1791 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
1793 rtx val = operand_subword (x, 0, 0, SFmode);
1795 if (val == 0 || GET_CODE (val) != CONST_INT)
1798 if (TARGET_MINIMAL_TOC)
1799 fprintf (file, "\t.long %d\n", INTVAL (val));
1801 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
1805 if (GET_CODE (x) == CONST)
1807 base = XEXP (XEXP (x, 0), 0);
1808 offset = INTVAL (XEXP (XEXP (x, 0), 1));
1811 if (GET_CODE (base) == SYMBOL_REF)
1812 name = XSTR (base, 0);
1813 else if (GET_CODE (base) == LABEL_REF)
1814 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
1815 else if (GET_CODE (base) == CODE_LABEL)
1816 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
1820 if (TARGET_MINIMAL_TOC)
1821 fprintf (file, "\t.long ");
1824 fprintf (file, "\t.tc ");
1825 RS6000_OUTPUT_BASENAME (file, name);
1828 fprintf (file, ".N%d", - offset);
1830 fprintf (file, ".P%d", offset);
1832 fprintf (file, "[TC],");
1834 output_addr_const (file, x);
1835 fprintf (file, "\n");
1838 /* Output an assembler pseudo-op to write an ASCII string of N characters
1839 starting at P to FILE.
1841 On the RS/6000, we have to do this using the .byte operation and
1842 write out special characters outside the quoted string.
1843 Also, the assembler is broken; very long strings are truncated,
1844 so we must artificially break them up early. */
1847 output_ascii (file, p, n)
1853 int i, count_string;
1854 char *for_string = "\t.byte \"";
1855 char *for_decimal = "\t.byte ";
1856 char *to_close = NULL;
1859 for (i = 0; i < n; i++)
1862 if (c >= ' ' && c < 0177)
1865 fputs (for_string, file);
1868 /* Write two quotes to get one. */
1876 for_decimal = "\"\n\t.byte ";
1880 if (count_string >= 512)
1882 fputs (to_close, file);
1884 for_string = "\t.byte \"";
1885 for_decimal = "\t.byte ";
1893 fputs (for_decimal, file);
1894 fprintf (file, "%d", c);
1896 for_string = "\n\t.byte \"";
1903 /* Now close the string if we have written one. Then end the line. */
1905 fprintf (file, to_close);
1908 /* Generate a unique section name for FILENAME for a section type
1909 represented by SECTION_DESC. Output goes into BUF.
1911 SECTION_DESC can be any string, as long as it is different for each
1912 possible section type.
1914 We name the section in the same manner as xlc. The name begins with an
1915 underscore followed by the filename (after stripping any leading directory
1916 names) with the last period replaced by the string SECTION_DESC. If
1917 FILENAME does not contain a period, SECTION_DESC is appended to the end of
1921 rs6000_gen_section_name (buf, filename, section_desc)
1926 char *q, *after_last_slash, *last_period;
1930 after_last_slash = filename;
1931 for (q = filename; *q; q++)
1934 after_last_slash = q + 1;
1939 len = strlen (after_last_slash) + strlen (section_desc) + 2;
1940 *buf = (char *) permalloc (len);
1945 for (q = after_last_slash; *q; q++)
1947 if (q == last_period)
1949 strcpy (p, section_desc);
1950 p += strlen (section_desc);
1953 else if (isalnum (*q))
1957 if (last_period == 0)
1958 strcpy (p, section_desc);
1963 /* Write function profiler code. */
1966 output_function_profiler (file, labelno)
1970 /* The last used parameter register. */
1974 /* Set up a TOC entry for the profiler label. */
1976 if (TARGET_MINIMAL_TOC)
1977 fprintf (file, "LPC..%d:\n\t.long LP..%d\n", labelno, labelno);
1979 fprintf (file, "LPC..%d:\n\t.tc\tLP..%d[TC],LP..%d\n",
1980 labelno, labelno, labelno);
1983 /* Figure out last used parameter register. The proper thing to do is
1984 to walk incoming args of the function. A function might have live
1985 parameter registers even if it has no incoming args. */
1987 for (last_parm_reg = 10;
1988 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
1992 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
1993 it might be set up as the frame pointer. */
1995 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
1996 fprintf (file, "\tai %d,%d,0\n", j, i);
1998 /* Load location address into r3, and call mcount. */
2000 fprintf (file, "\tl 3,LPC..%d(2)\n\tbl .mcount\n", labelno);
2002 /* Restore parameter registers. */
2004 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2005 fprintf (file, "\tai %d,%d,0\n", i, j);