1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define min(A,B) ((A) < (B) ? (A) : (B))
68 #define max(A,B) ((A) > (B) ? (A) : (B))
70 /* Structure used to define the rs6000 stack */
71 typedef struct rs6000_stack {
72 int first_gp_reg_save; /* first callee saved GP register used */
73 int first_fp_reg_save; /* first callee saved FP register used */
74 int first_altivec_reg_save; /* first callee saved AltiVec register used */
75 int lr_save_p; /* true if the link reg needs to be saved */
76 int cr_save_p; /* true if the CR reg needs to be saved */
77 unsigned int vrsave_mask; /* mask of vec registers to save */
78 int toc_save_p; /* true if the TOC needs to be saved */
79 int push_p; /* true if we need to allocate stack space */
80 int calls_p; /* true if the function makes any calls */
81 int world_save_p; /* true if we're saving *everything*:
82 r13-r31, cr, f14-f31, vrsave, v20-v31 */
83 enum rs6000_abi abi; /* which ABI to use */
84 int gp_save_offset; /* offset to save GP regs from initial SP */
85 int fp_save_offset; /* offset to save FP regs from initial SP */
86 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
87 int lr_save_offset; /* offset to save LR from initial SP */
88 int cr_save_offset; /* offset to save CR from initial SP */
89 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
90 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
91 int toc_save_offset; /* offset to save the TOC pointer */
92 int varargs_save_offset; /* offset to save the varargs registers */
93 int ehrd_offset; /* offset to EH return data */
94 int reg_size; /* register size (4 or 8) */
95 int varargs_size; /* size to hold V.4 args passed in regs */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int lr_size; /* size to hold LR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 int toc_size; /* size to hold TOC if not in save_size */
111 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
112 int spe_64bit_regs_used;
115 /* Target cpu type */
117 enum processor_type rs6000_cpu;
118 struct rs6000_cpu_select rs6000_select[3] =
120 /* switch name, tune arch */
121 { (const char *)0, "--with-cpu=", 1, 1 },
122 { (const char *)0, "-mcpu=", 1, 1 },
123 { (const char *)0, "-mtune=", 1, 0 },
126 /* Always emit branch hint bits. */
127 static GTY(()) bool rs6000_always_hint;
129 /* Schedule instructions for group formation. */
130 static GTY(()) bool rs6000_sched_groups;
132 /* Support adjust_priority scheduler hook
133 and -mprioritize-restricted-insns= option. */
134 const char *rs6000_sched_restricted_insns_priority_str;
135 int rs6000_sched_restricted_insns_priority;
137 /* Support for -msched-costly-dep option. */
138 const char *rs6000_sched_costly_dep_str;
139 enum rs6000_dependence_cost rs6000_sched_costly_dep;
141 /* Support for -minsert-sched-nops option. */
142 const char *rs6000_sched_insert_nops_str;
143 enum rs6000_nop_insertion rs6000_sched_insert_nops;
145 /* Support targetm.vectorize.builtin_mask_for_load. */
146 static GTY(()) tree altivec_builtin_mask_for_load;
148 /* Size of long double */
149 const char *rs6000_long_double_size_string;
150 int rs6000_long_double_type_size;
152 /* Whether -mabi=altivec has appeared */
153 int rs6000_altivec_abi;
155 /* Whether VRSAVE instructions should be generated. */
156 int rs6000_altivec_vrsave;
158 /* String from -mvrsave= option. */
159 const char *rs6000_altivec_vrsave_string;
161 /* Nonzero if we want SPE ABI extensions. */
164 /* Whether isel instructions should be generated. */
167 /* Whether SPE simd instructions should be generated. */
170 /* Nonzero if floating point operations are done in the GPRs. */
171 int rs6000_float_gprs = 0;
173 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
174 int rs6000_darwin64_abi;
176 /* String from -mfloat-gprs=. */
177 const char *rs6000_float_gprs_string;
179 /* String from -misel=. */
180 const char *rs6000_isel_string;
182 /* String from -mspe=. */
183 const char *rs6000_spe_string;
185 /* Set to nonzero once AIX common-mode calls have been defined. */
186 static GTY(()) int common_mode_defined;
188 /* Save information from a "cmpxx" operation until the branch or scc is
190 rtx rs6000_compare_op0, rs6000_compare_op1;
191 int rs6000_compare_fp_p;
193 /* Label number of label created for -mrelocatable, to call to so we can
194 get the address of the GOT section */
195 int rs6000_pic_labelno;
198 /* Which abi to adhere to */
199 const char *rs6000_abi_name;
201 /* Semantics of the small data area */
202 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
204 /* Which small data model to use */
205 const char *rs6000_sdata_name = (char *)0;
207 /* Counter for labels which are to be placed in .fixup. */
208 int fixuplabelno = 0;
211 /* Bit size of immediate TLS offsets and string from which it is decoded. */
212 int rs6000_tls_size = 32;
213 const char *rs6000_tls_size_string;
215 /* ABI enumeration available for subtarget to use. */
216 enum rs6000_abi rs6000_current_abi;
218 /* ABI string from -mabi= option. */
219 const char *rs6000_abi_string;
221 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
225 const char *rs6000_debug_name;
226 int rs6000_debug_stack; /* debug stack applications */
227 int rs6000_debug_arg; /* debug argument handling */
229 /* Value is TRUE if register/mode pair is accepatable. */
230 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
233 static GTY(()) tree opaque_V2SI_type_node;
234 static GTY(()) tree opaque_V2SF_type_node;
235 static GTY(()) tree opaque_p_V2SI_type_node;
236 static GTY(()) tree V16QI_type_node;
237 static GTY(()) tree V2SI_type_node;
238 static GTY(()) tree V2SF_type_node;
239 static GTY(()) tree V4HI_type_node;
240 static GTY(()) tree V4SI_type_node;
241 static GTY(()) tree V4SF_type_node;
242 static GTY(()) tree V8HI_type_node;
243 static GTY(()) tree unsigned_V16QI_type_node;
244 static GTY(()) tree unsigned_V8HI_type_node;
245 static GTY(()) tree unsigned_V4SI_type_node;
246 static GTY(()) tree bool_char_type_node; /* __bool char */
247 static GTY(()) tree bool_short_type_node; /* __bool short */
248 static GTY(()) tree bool_int_type_node; /* __bool int */
249 static GTY(()) tree pixel_type_node; /* __pixel */
250 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
251 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
252 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
253 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
255 int rs6000_warn_altivec_long = 1; /* On by default. */
256 const char *rs6000_warn_altivec_long_switch;
258 const char *rs6000_traceback_name;
260 traceback_default = 0,
266 /* Flag to say the TOC is initialized */
268 char toc_label_name[10];
270 /* Alias set for saves and restores from the rs6000 stack. */
271 static GTY(()) int rs6000_sr_alias_set;
273 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
274 The only place that looks at this is rs6000_set_default_type_attributes;
275 everywhere else should rely on the presence or absence of a longcall
276 attribute on the function declaration. Exception: init_cumulative_args
277 looks at it too, for libcalls. */
278 int rs6000_default_long_calls;
279 const char *rs6000_longcall_switch;
281 /* Control alignment for fields within structures. */
282 /* String from -malign-XXXXX. */
283 const char *rs6000_alignment_string;
284 int rs6000_alignment_flags;
286 struct builtin_description
288 /* mask is not const because we're going to alter it below. This
289 nonsense will go away when we rewrite the -march infrastructure
290 to give us more target flag bits. */
292 const enum insn_code icode;
293 const char *const name;
294 const enum rs6000_builtins code;
297 /* Target cpu costs. */
299 struct processor_costs {
300 const int mulsi; /* cost of SImode multiplication. */
301 const int mulsi_const; /* cost of SImode multiplication by constant. */
302 const int mulsi_const9; /* cost of SImode mult by short constant. */
303 const int muldi; /* cost of DImode multiplication. */
304 const int divsi; /* cost of SImode division. */
305 const int divdi; /* cost of DImode division. */
306 const int fp; /* cost of simple SFmode and DFmode insns. */
307 const int dmul; /* cost of DFmode multiplication (and fmadd). */
308 const int sdiv; /* cost of SFmode division (fdivs). */
309 const int ddiv; /* cost of DFmode division (fdiv). */
312 const struct processor_costs *rs6000_cost;
314 /* Processor costs (relative to an add) */
316 /* Instruction size costs on 32bit processors. */
318 struct processor_costs size32_cost = {
319 COSTS_N_INSNS (1), /* mulsi */
320 COSTS_N_INSNS (1), /* mulsi_const */
321 COSTS_N_INSNS (1), /* mulsi_const9 */
322 COSTS_N_INSNS (1), /* muldi */
323 COSTS_N_INSNS (1), /* divsi */
324 COSTS_N_INSNS (1), /* divdi */
325 COSTS_N_INSNS (1), /* fp */
326 COSTS_N_INSNS (1), /* dmul */
327 COSTS_N_INSNS (1), /* sdiv */
328 COSTS_N_INSNS (1), /* ddiv */
331 /* Instruction size costs on 64bit processors. */
333 struct processor_costs size64_cost = {
334 COSTS_N_INSNS (1), /* mulsi */
335 COSTS_N_INSNS (1), /* mulsi_const */
336 COSTS_N_INSNS (1), /* mulsi_const9 */
337 COSTS_N_INSNS (1), /* muldi */
338 COSTS_N_INSNS (1), /* divsi */
339 COSTS_N_INSNS (1), /* divdi */
340 COSTS_N_INSNS (1), /* fp */
341 COSTS_N_INSNS (1), /* dmul */
342 COSTS_N_INSNS (1), /* sdiv */
343 COSTS_N_INSNS (1), /* ddiv */
346 /* Instruction costs on RIOS1 processors. */
348 struct processor_costs rios1_cost = {
349 COSTS_N_INSNS (5), /* mulsi */
350 COSTS_N_INSNS (4), /* mulsi_const */
351 COSTS_N_INSNS (3), /* mulsi_const9 */
352 COSTS_N_INSNS (5), /* muldi */
353 COSTS_N_INSNS (19), /* divsi */
354 COSTS_N_INSNS (19), /* divdi */
355 COSTS_N_INSNS (2), /* fp */
356 COSTS_N_INSNS (2), /* dmul */
357 COSTS_N_INSNS (19), /* sdiv */
358 COSTS_N_INSNS (19), /* ddiv */
361 /* Instruction costs on RIOS2 processors. */
363 struct processor_costs rios2_cost = {
364 COSTS_N_INSNS (2), /* mulsi */
365 COSTS_N_INSNS (2), /* mulsi_const */
366 COSTS_N_INSNS (2), /* mulsi_const9 */
367 COSTS_N_INSNS (2), /* muldi */
368 COSTS_N_INSNS (13), /* divsi */
369 COSTS_N_INSNS (13), /* divdi */
370 COSTS_N_INSNS (2), /* fp */
371 COSTS_N_INSNS (2), /* dmul */
372 COSTS_N_INSNS (17), /* sdiv */
373 COSTS_N_INSNS (17), /* ddiv */
376 /* Instruction costs on RS64A processors. */
378 struct processor_costs rs64a_cost = {
379 COSTS_N_INSNS (20), /* mulsi */
380 COSTS_N_INSNS (12), /* mulsi_const */
381 COSTS_N_INSNS (8), /* mulsi_const9 */
382 COSTS_N_INSNS (34), /* muldi */
383 COSTS_N_INSNS (65), /* divsi */
384 COSTS_N_INSNS (67), /* divdi */
385 COSTS_N_INSNS (4), /* fp */
386 COSTS_N_INSNS (4), /* dmul */
387 COSTS_N_INSNS (31), /* sdiv */
388 COSTS_N_INSNS (31), /* ddiv */
391 /* Instruction costs on MPCCORE processors. */
393 struct processor_costs mpccore_cost = {
394 COSTS_N_INSNS (2), /* mulsi */
395 COSTS_N_INSNS (2), /* mulsi_const */
396 COSTS_N_INSNS (2), /* mulsi_const9 */
397 COSTS_N_INSNS (2), /* muldi */
398 COSTS_N_INSNS (6), /* divsi */
399 COSTS_N_INSNS (6), /* divdi */
400 COSTS_N_INSNS (4), /* fp */
401 COSTS_N_INSNS (5), /* dmul */
402 COSTS_N_INSNS (10), /* sdiv */
403 COSTS_N_INSNS (17), /* ddiv */
406 /* Instruction costs on PPC403 processors. */
408 struct processor_costs ppc403_cost = {
409 COSTS_N_INSNS (4), /* mulsi */
410 COSTS_N_INSNS (4), /* mulsi_const */
411 COSTS_N_INSNS (4), /* mulsi_const9 */
412 COSTS_N_INSNS (4), /* muldi */
413 COSTS_N_INSNS (33), /* divsi */
414 COSTS_N_INSNS (33), /* divdi */
415 COSTS_N_INSNS (11), /* fp */
416 COSTS_N_INSNS (11), /* dmul */
417 COSTS_N_INSNS (11), /* sdiv */
418 COSTS_N_INSNS (11), /* ddiv */
421 /* Instruction costs on PPC405 processors. */
423 struct processor_costs ppc405_cost = {
424 COSTS_N_INSNS (5), /* mulsi */
425 COSTS_N_INSNS (4), /* mulsi_const */
426 COSTS_N_INSNS (3), /* mulsi_const9 */
427 COSTS_N_INSNS (5), /* muldi */
428 COSTS_N_INSNS (35), /* divsi */
429 COSTS_N_INSNS (35), /* divdi */
430 COSTS_N_INSNS (11), /* fp */
431 COSTS_N_INSNS (11), /* dmul */
432 COSTS_N_INSNS (11), /* sdiv */
433 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC440 processors. */
438 struct processor_costs ppc440_cost = {
439 COSTS_N_INSNS (3), /* mulsi */
440 COSTS_N_INSNS (2), /* mulsi_const */
441 COSTS_N_INSNS (2), /* mulsi_const9 */
442 COSTS_N_INSNS (3), /* muldi */
443 COSTS_N_INSNS (34), /* divsi */
444 COSTS_N_INSNS (34), /* divdi */
445 COSTS_N_INSNS (5), /* fp */
446 COSTS_N_INSNS (5), /* dmul */
447 COSTS_N_INSNS (19), /* sdiv */
448 COSTS_N_INSNS (33), /* ddiv */
451 /* Instruction costs on PPC601 processors. */
453 struct processor_costs ppc601_cost = {
454 COSTS_N_INSNS (5), /* mulsi */
455 COSTS_N_INSNS (5), /* mulsi_const */
456 COSTS_N_INSNS (5), /* mulsi_const9 */
457 COSTS_N_INSNS (5), /* muldi */
458 COSTS_N_INSNS (36), /* divsi */
459 COSTS_N_INSNS (36), /* divdi */
460 COSTS_N_INSNS (4), /* fp */
461 COSTS_N_INSNS (5), /* dmul */
462 COSTS_N_INSNS (17), /* sdiv */
463 COSTS_N_INSNS (31), /* ddiv */
466 /* Instruction costs on PPC603 processors. */
468 struct processor_costs ppc603_cost = {
469 COSTS_N_INSNS (5), /* mulsi */
470 COSTS_N_INSNS (3), /* mulsi_const */
471 COSTS_N_INSNS (2), /* mulsi_const9 */
472 COSTS_N_INSNS (5), /* muldi */
473 COSTS_N_INSNS (37), /* divsi */
474 COSTS_N_INSNS (37), /* divdi */
475 COSTS_N_INSNS (3), /* fp */
476 COSTS_N_INSNS (4), /* dmul */
477 COSTS_N_INSNS (18), /* sdiv */
478 COSTS_N_INSNS (33), /* ddiv */
481 /* Instruction costs on PPC604 processors. */
483 struct processor_costs ppc604_cost = {
484 COSTS_N_INSNS (4), /* mulsi */
485 COSTS_N_INSNS (4), /* mulsi_const */
486 COSTS_N_INSNS (4), /* mulsi_const9 */
487 COSTS_N_INSNS (4), /* muldi */
488 COSTS_N_INSNS (20), /* divsi */
489 COSTS_N_INSNS (20), /* divdi */
490 COSTS_N_INSNS (3), /* fp */
491 COSTS_N_INSNS (3), /* dmul */
492 COSTS_N_INSNS (18), /* sdiv */
493 COSTS_N_INSNS (32), /* ddiv */
496 /* Instruction costs on PPC604e processors. */
498 struct processor_costs ppc604e_cost = {
499 COSTS_N_INSNS (2), /* mulsi */
500 COSTS_N_INSNS (2), /* mulsi_const */
501 COSTS_N_INSNS (2), /* mulsi_const9 */
502 COSTS_N_INSNS (2), /* muldi */
503 COSTS_N_INSNS (20), /* divsi */
504 COSTS_N_INSNS (20), /* divdi */
505 COSTS_N_INSNS (3), /* fp */
506 COSTS_N_INSNS (3), /* dmul */
507 COSTS_N_INSNS (18), /* sdiv */
508 COSTS_N_INSNS (32), /* ddiv */
511 /* Instruction costs on PPC620 processors. */
513 struct processor_costs ppc620_cost = {
514 COSTS_N_INSNS (5), /* mulsi */
515 COSTS_N_INSNS (4), /* mulsi_const */
516 COSTS_N_INSNS (3), /* mulsi_const9 */
517 COSTS_N_INSNS (7), /* muldi */
518 COSTS_N_INSNS (21), /* divsi */
519 COSTS_N_INSNS (37), /* divdi */
520 COSTS_N_INSNS (3), /* fp */
521 COSTS_N_INSNS (3), /* dmul */
522 COSTS_N_INSNS (18), /* sdiv */
523 COSTS_N_INSNS (32), /* ddiv */
526 /* Instruction costs on PPC630 processors. */
528 struct processor_costs ppc630_cost = {
529 COSTS_N_INSNS (5), /* mulsi */
530 COSTS_N_INSNS (4), /* mulsi_const */
531 COSTS_N_INSNS (3), /* mulsi_const9 */
532 COSTS_N_INSNS (7), /* muldi */
533 COSTS_N_INSNS (21), /* divsi */
534 COSTS_N_INSNS (37), /* divdi */
535 COSTS_N_INSNS (3), /* fp */
536 COSTS_N_INSNS (3), /* dmul */
537 COSTS_N_INSNS (17), /* sdiv */
538 COSTS_N_INSNS (21), /* ddiv */
541 /* Instruction costs on PPC750 and PPC7400 processors. */
543 struct processor_costs ppc750_cost = {
544 COSTS_N_INSNS (5), /* mulsi */
545 COSTS_N_INSNS (3), /* mulsi_const */
546 COSTS_N_INSNS (2), /* mulsi_const9 */
547 COSTS_N_INSNS (5), /* muldi */
548 COSTS_N_INSNS (17), /* divsi */
549 COSTS_N_INSNS (17), /* divdi */
550 COSTS_N_INSNS (3), /* fp */
551 COSTS_N_INSNS (3), /* dmul */
552 COSTS_N_INSNS (17), /* sdiv */
553 COSTS_N_INSNS (31), /* ddiv */
556 /* Instruction costs on PPC7450 processors. */
558 struct processor_costs ppc7450_cost = {
559 COSTS_N_INSNS (4), /* mulsi */
560 COSTS_N_INSNS (3), /* mulsi_const */
561 COSTS_N_INSNS (3), /* mulsi_const9 */
562 COSTS_N_INSNS (4), /* muldi */
563 COSTS_N_INSNS (23), /* divsi */
564 COSTS_N_INSNS (23), /* divdi */
565 COSTS_N_INSNS (5), /* fp */
566 COSTS_N_INSNS (5), /* dmul */
567 COSTS_N_INSNS (21), /* sdiv */
568 COSTS_N_INSNS (35), /* ddiv */
571 /* Instruction costs on PPC8540 processors. */
573 struct processor_costs ppc8540_cost = {
574 COSTS_N_INSNS (4), /* mulsi */
575 COSTS_N_INSNS (4), /* mulsi_const */
576 COSTS_N_INSNS (4), /* mulsi_const9 */
577 COSTS_N_INSNS (4), /* muldi */
578 COSTS_N_INSNS (19), /* divsi */
579 COSTS_N_INSNS (19), /* divdi */
580 COSTS_N_INSNS (4), /* fp */
581 COSTS_N_INSNS (4), /* dmul */
582 COSTS_N_INSNS (29), /* sdiv */
583 COSTS_N_INSNS (29), /* ddiv */
586 /* Instruction costs on POWER4 and POWER5 processors. */
588 struct processor_costs power4_cost = {
589 COSTS_N_INSNS (3), /* mulsi */
590 COSTS_N_INSNS (2), /* mulsi_const */
591 COSTS_N_INSNS (2), /* mulsi_const9 */
592 COSTS_N_INSNS (4), /* muldi */
593 COSTS_N_INSNS (18), /* divsi */
594 COSTS_N_INSNS (34), /* divdi */
595 COSTS_N_INSNS (3), /* fp */
596 COSTS_N_INSNS (3), /* dmul */
597 COSTS_N_INSNS (17), /* sdiv */
598 COSTS_N_INSNS (17), /* ddiv */
602 static bool rs6000_function_ok_for_sibcall (tree, tree);
603 static rtx rs6000_generate_compare (enum rtx_code);
604 static void rs6000_maybe_dead (rtx);
605 static void rs6000_emit_stack_tie (void);
606 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
607 static rtx spe_synthesize_frame_save (rtx);
608 static bool spe_func_has_64bit_regs_p (void);
609 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
611 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
612 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
613 static unsigned rs6000_hash_constant (rtx);
614 static unsigned toc_hash_function (const void *);
615 static int toc_hash_eq (const void *, const void *);
616 static int constant_pool_expr_1 (rtx, int *, int *);
617 static bool constant_pool_expr_p (rtx);
618 static bool legitimate_small_data_p (enum machine_mode, rtx);
619 static bool legitimate_indexed_address_p (rtx, int);
620 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
621 static struct machine_function * rs6000_init_machine_status (void);
622 static bool rs6000_assemble_integer (rtx, unsigned int, int);
623 #ifdef HAVE_GAS_HIDDEN
624 static void rs6000_assemble_visibility (tree, int);
626 static int rs6000_ra_ever_killed (void);
627 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
628 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
629 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
630 static const char *rs6000_mangle_fundamental_type (tree);
631 extern const struct attribute_spec rs6000_attribute_table[];
632 static void rs6000_set_default_type_attributes (tree);
633 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
634 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
635 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
637 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
638 static bool rs6000_return_in_memory (tree, tree);
639 static void rs6000_file_start (void);
641 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
642 static void rs6000_elf_asm_out_constructor (rtx, int);
643 static void rs6000_elf_asm_out_destructor (rtx, int);
644 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
645 static void rs6000_elf_unique_section (tree, int);
646 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
647 unsigned HOST_WIDE_INT);
648 static void rs6000_elf_encode_section_info (tree, rtx, int)
650 static bool rs6000_elf_in_small_data_p (tree);
653 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
654 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
655 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
656 static void rs6000_xcoff_unique_section (tree, int);
657 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
658 unsigned HOST_WIDE_INT);
659 static const char * rs6000_xcoff_strip_name_encoding (const char *);
660 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
661 static void rs6000_xcoff_file_start (void);
662 static void rs6000_xcoff_file_end (void);
665 static bool rs6000_binds_local_p (tree);
667 static int rs6000_variable_issue (FILE *, int, rtx, int);
668 static bool rs6000_rtx_costs (rtx, int, int, int *);
669 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
670 static bool is_microcoded_insn (rtx);
671 static int is_dispatch_slot_restricted (rtx);
672 static bool is_cracked_insn (rtx);
673 static bool is_branch_slot_insn (rtx);
674 static int rs6000_adjust_priority (rtx, int);
675 static int rs6000_issue_rate (void);
676 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
677 static rtx get_next_active_insn (rtx, rtx);
678 static bool insn_terminates_group_p (rtx , enum group_termination);
679 static bool is_costly_group (rtx *, rtx);
680 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
681 static int redefine_groups (FILE *, int, rtx, rtx);
682 static int pad_groups (FILE *, int, rtx, rtx);
683 static void rs6000_sched_finish (FILE *, int);
684 static int rs6000_use_sched_lookahead (void);
685 static tree rs6000_builtin_mask_for_load (void);
687 static void rs6000_init_builtins (void);
688 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
689 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
690 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
691 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
692 static void altivec_init_builtins (void);
693 static void rs6000_common_init_builtins (void);
694 static void rs6000_init_libfuncs (void);
696 static void enable_mask_for_builtins (struct builtin_description *, int,
697 enum rs6000_builtins,
698 enum rs6000_builtins);
699 static tree build_opaque_vector_type (tree, int);
700 static void spe_init_builtins (void);
701 static rtx spe_expand_builtin (tree, rtx, bool *);
702 static rtx spe_expand_stv_builtin (enum insn_code, tree);
703 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
704 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
705 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
706 static rs6000_stack_t *rs6000_stack_info (void);
707 static void debug_stack_info (rs6000_stack_t *);
709 static rtx altivec_expand_builtin (tree, rtx, bool *);
710 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
711 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
712 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
713 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
714 static rtx altivec_expand_predicate_builtin (enum insn_code,
715 const char *, tree, rtx);
716 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
717 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
718 static void rs6000_parse_abi_options (void);
719 static void rs6000_parse_alignment_option (void);
720 static void rs6000_parse_tls_size_option (void);
721 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
722 static void rs6000_parse_float_gprs_option (void);
723 static int first_altivec_reg_to_save (void);
724 static unsigned int compute_vrsave_mask (void);
725 static void compute_save_world_info(rs6000_stack_t *info_ptr);
726 static void is_altivec_return_reg (rtx, void *);
727 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
728 int easy_vector_constant (rtx, enum machine_mode);
729 static bool is_ev64_opaque_type (tree);
730 static rtx rs6000_dwarf_register_span (rtx);
731 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
732 static rtx rs6000_tls_get_addr (void);
733 static rtx rs6000_got_sym (void);
734 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
735 static const char *rs6000_get_some_local_dynamic_name (void);
736 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
737 static rtx rs6000_complex_function_value (enum machine_mode);
738 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
739 enum machine_mode, tree);
740 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
742 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
743 tree, HOST_WIDE_INT);
744 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
747 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
750 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
751 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
752 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
753 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
754 enum machine_mode, tree,
756 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
758 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
761 static void macho_branch_islands (void);
762 static void add_compiler_branch_island (tree, tree, int);
763 static int no_previous_def (tree function_name);
764 static tree get_prev_label (tree function_name);
765 static void rs6000_darwin_file_start (void);
768 static tree rs6000_build_builtin_va_list (void);
769 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
770 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
771 static bool rs6000_vector_mode_supported_p (enum machine_mode);
772 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
774 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
776 static int get_vsel_insn (enum machine_mode);
777 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
780 const int INSN_NOT_AVAILABLE = -1;
781 static enum machine_mode rs6000_eh_return_filter_mode (void);
783 /* Hash table stuff for keeping track of TOC entries. */
785 struct toc_hash_struct GTY(())
787 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
788 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
790 enum machine_mode key_mode;
794 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
796 /* Default register names. */
797 char rs6000_reg_names[][8] =
799 "0", "1", "2", "3", "4", "5", "6", "7",
800 "8", "9", "10", "11", "12", "13", "14", "15",
801 "16", "17", "18", "19", "20", "21", "22", "23",
802 "24", "25", "26", "27", "28", "29", "30", "31",
803 "0", "1", "2", "3", "4", "5", "6", "7",
804 "8", "9", "10", "11", "12", "13", "14", "15",
805 "16", "17", "18", "19", "20", "21", "22", "23",
806 "24", "25", "26", "27", "28", "29", "30", "31",
807 "mq", "lr", "ctr","ap",
808 "0", "1", "2", "3", "4", "5", "6", "7",
810 /* AltiVec registers. */
811 "0", "1", "2", "3", "4", "5", "6", "7",
812 "8", "9", "10", "11", "12", "13", "14", "15",
813 "16", "17", "18", "19", "20", "21", "22", "23",
814 "24", "25", "26", "27", "28", "29", "30", "31",
820 #ifdef TARGET_REGNAMES
821 static const char alt_reg_names[][8] =
823 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
824 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
825 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
826 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
827 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
828 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
829 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
830 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
831 "mq", "lr", "ctr", "ap",
832 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
834 /* AltiVec registers. */
835 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
836 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
837 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
838 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
845 #ifndef MASK_STRICT_ALIGN
846 #define MASK_STRICT_ALIGN 0
848 #ifndef TARGET_PROFILE_KERNEL
849 #define TARGET_PROFILE_KERNEL 0
852 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
853 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
855 /* Initialize the GCC target structure. */
856 #undef TARGET_ATTRIBUTE_TABLE
857 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
858 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
859 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
861 #undef TARGET_ASM_ALIGNED_DI_OP
862 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
864 /* Default unaligned ops are only provided for ELF. Find the ops needed
865 for non-ELF systems. */
866 #ifndef OBJECT_FORMAT_ELF
868 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
870 #undef TARGET_ASM_UNALIGNED_HI_OP
871 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
872 #undef TARGET_ASM_UNALIGNED_SI_OP
873 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
874 #undef TARGET_ASM_UNALIGNED_DI_OP
875 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
878 #undef TARGET_ASM_UNALIGNED_HI_OP
879 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
880 #undef TARGET_ASM_UNALIGNED_SI_OP
881 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
882 #undef TARGET_ASM_UNALIGNED_DI_OP
883 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
884 #undef TARGET_ASM_ALIGNED_DI_OP
885 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
889 /* This hook deals with fixups for relocatable code and DI-mode objects
891 #undef TARGET_ASM_INTEGER
892 #define TARGET_ASM_INTEGER rs6000_assemble_integer
894 #ifdef HAVE_GAS_HIDDEN
895 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
896 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
899 #undef TARGET_HAVE_TLS
900 #define TARGET_HAVE_TLS HAVE_AS_TLS
902 #undef TARGET_CANNOT_FORCE_CONST_MEM
903 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
905 #undef TARGET_ASM_FUNCTION_PROLOGUE
906 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
907 #undef TARGET_ASM_FUNCTION_EPILOGUE
908 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
910 #undef TARGET_SCHED_VARIABLE_ISSUE
911 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
913 #undef TARGET_SCHED_ISSUE_RATE
914 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
915 #undef TARGET_SCHED_ADJUST_COST
916 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
917 #undef TARGET_SCHED_ADJUST_PRIORITY
918 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
919 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
920 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
921 #undef TARGET_SCHED_FINISH
922 #define TARGET_SCHED_FINISH rs6000_sched_finish
924 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
925 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
927 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
928 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
930 #undef TARGET_INIT_BUILTINS
931 #define TARGET_INIT_BUILTINS rs6000_init_builtins
933 #undef TARGET_EXPAND_BUILTIN
934 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
936 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
937 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
939 #undef TARGET_INIT_LIBFUNCS
940 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
943 #undef TARGET_BINDS_LOCAL_P
944 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
947 #undef TARGET_ASM_OUTPUT_MI_THUNK
948 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
950 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
951 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
953 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
954 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
956 #undef TARGET_RTX_COSTS
957 #define TARGET_RTX_COSTS rs6000_rtx_costs
958 #undef TARGET_ADDRESS_COST
959 #define TARGET_ADDRESS_COST hook_int_rtx_0
961 #undef TARGET_VECTOR_OPAQUE_P
962 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
964 #undef TARGET_DWARF_REGISTER_SPAN
965 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
967 /* On rs6000, function arguments are promoted, as are function return
969 #undef TARGET_PROMOTE_FUNCTION_ARGS
970 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
971 #undef TARGET_PROMOTE_FUNCTION_RETURN
972 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
974 #undef TARGET_RETURN_IN_MEMORY
975 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
977 #undef TARGET_SETUP_INCOMING_VARARGS
978 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
980 /* Always strict argument naming on rs6000. */
981 #undef TARGET_STRICT_ARGUMENT_NAMING
982 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
983 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
984 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
985 #undef TARGET_SPLIT_COMPLEX_ARG
986 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
987 #undef TARGET_MUST_PASS_IN_STACK
988 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
989 #undef TARGET_PASS_BY_REFERENCE
990 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
991 #undef TARGET_ARG_PARTIAL_BYTES
992 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
994 #undef TARGET_BUILD_BUILTIN_VA_LIST
995 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
997 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
998 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1000 #undef TARGET_EH_RETURN_FILTER_MODE
1001 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1003 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1004 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1006 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1007 The PowerPC architecture requires only weak consistency among
1008 processors--that is, memory accesses between processors need not be
1009 sequentially consistent and memory accesses among processors can occur
1010 in any order. The ability to order memory accesses weakly provides
1011 opportunities for more efficient use of the system bus. Unless a
1012 dependency exists, the 604e allows read operations to precede store
1014 #undef TARGET_RELAXED_ORDERING
1015 #define TARGET_RELAXED_ORDERING true
1017 struct gcc_target targetm = TARGET_INITIALIZER;
1020 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1023 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1025 /* The GPRs can hold any mode, but values bigger than one register
1026 cannot go past R31. */
1027 if (INT_REGNO_P (regno))
1028 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1030 /* The float registers can only hold floating modes and DImode. */
1031 if (FP_REGNO_P (regno))
1033 (GET_MODE_CLASS (mode) == MODE_FLOAT
1034 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1035 || (GET_MODE_CLASS (mode) == MODE_INT
1036 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1038 /* The CR register can only hold CC modes. */
1039 if (CR_REGNO_P (regno))
1040 return GET_MODE_CLASS (mode) == MODE_CC;
1042 if (XER_REGNO_P (regno))
1043 return mode == PSImode;
1045 /* AltiVec only in AldyVec registers. */
1046 if (ALTIVEC_REGNO_P (regno))
1047 return ALTIVEC_VECTOR_MODE (mode);
1049 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1050 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1053 /* We cannot put TImode anywhere except general register and it must be
1054 able to fit within the register set. */
1056 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1059 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1061 rs6000_init_hard_regno_mode_ok (void)
1065 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1066 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1067 if (rs6000_hard_regno_mode_ok (r, m))
1068 rs6000_hard_regno_mode_ok_p[m][r] = true;
1071 /* If not otherwise specified by a target, make 'long double' equivalent to
1074 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1075 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1078 /* Override command line options. Mostly we process the processor
1079 type and sometimes adjust other TARGET_ options. */
1082 rs6000_override_options (const char *default_cpu)
1085 struct rs6000_cpu_select *ptr;
1088 /* Simplifications for entries below. */
1091 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1092 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1095 /* This table occasionally claims that a processor does not support
1096 a particular feature even though it does, but the feature is slower
1097 than the alternative. Thus, it shouldn't be relied on as a
1098 complete description of the processor's support.
1100 Please keep this list in order, and don't forget to update the
1101 documentation in invoke.texi when adding a new processor or
1105 const char *const name; /* Canonical processor name. */
1106 const enum processor_type processor; /* Processor type enum value. */
1107 const int target_enable; /* Target flags to enable. */
1108 } const processor_target_table[]
1109 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1110 {"403", PROCESSOR_PPC403,
1111 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1112 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1113 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1114 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1115 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1116 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1117 {"601", PROCESSOR_PPC601,
1118 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1119 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1120 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1123 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1124 {"620", PROCESSOR_PPC620,
1125 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1126 {"630", PROCESSOR_PPC630,
1127 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1128 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1130 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1131 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1132 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1133 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1134 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1135 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1136 /* 8548 has a dummy entry for now. */
1137 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1138 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"970", PROCESSOR_POWER4,
1140 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1141 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1142 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1143 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1144 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1145 {"G5", PROCESSOR_POWER4,
1146 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1147 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1148 {"power2", PROCESSOR_POWER,
1149 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1150 {"power3", PROCESSOR_PPC630,
1151 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1152 {"power4", PROCESSOR_POWER4,
1153 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1154 {"power5", PROCESSOR_POWER5,
1155 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1156 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1157 {"powerpc64", PROCESSOR_POWERPC64,
1158 POWERPC_BASE_MASK | MASK_POWERPC64},
1159 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1160 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1161 {"rios2", PROCESSOR_RIOS2,
1162 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1163 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1164 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1168 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1170 /* Some OSs don't support saving the high part of 64-bit registers on
1171 context switch. Other OSs don't support saving Altivec registers.
1172 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1173 settings; if the user wants either, the user must explicitly specify
1174 them and we won't interfere with the user's specification. */
1177 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1178 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1179 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1183 rs6000_init_hard_regno_mode_ok ();
1185 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1186 #ifdef OS_MISSING_POWERPC64
1187 if (OS_MISSING_POWERPC64)
1188 set_masks &= ~MASK_POWERPC64;
1190 #ifdef OS_MISSING_ALTIVEC
1191 if (OS_MISSING_ALTIVEC)
1192 set_masks &= ~MASK_ALTIVEC;
1195 /* Don't override by the processor default if given explicitly. */
1196 set_masks &= ~target_flags_explicit;
1198 /* Identify the processor type. */
1199 rs6000_select[0].string = default_cpu;
1200 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1202 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1204 ptr = &rs6000_select[i];
1205 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1207 for (j = 0; j < ptt_size; j++)
1208 if (! strcmp (ptr->string, processor_target_table[j].name))
1210 if (ptr->set_tune_p)
1211 rs6000_cpu = processor_target_table[j].processor;
1213 if (ptr->set_arch_p)
1215 target_flags &= ~set_masks;
1216 target_flags |= (processor_target_table[j].target_enable
1223 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1230 /* If we are optimizing big endian systems for space, use the load/store
1231 multiple and string instructions. */
1232 if (BYTES_BIG_ENDIAN && optimize_size)
1233 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1235 /* Don't allow -mmultiple or -mstring on little endian systems
1236 unless the cpu is a 750, because the hardware doesn't support the
1237 instructions used in little endian mode, and causes an alignment
1238 trap. The 750 does not cause an alignment trap (except when the
1239 target is unaligned). */
1241 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1243 if (TARGET_MULTIPLE)
1245 target_flags &= ~MASK_MULTIPLE;
1246 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1247 warning ("-mmultiple is not supported on little endian systems");
1252 target_flags &= ~MASK_STRING;
1253 if ((target_flags_explicit & MASK_STRING) != 0)
1254 warning ("-mstring is not supported on little endian systems");
1258 /* Set debug flags */
1259 if (rs6000_debug_name)
1261 if (! strcmp (rs6000_debug_name, "all"))
1262 rs6000_debug_stack = rs6000_debug_arg = 1;
1263 else if (! strcmp (rs6000_debug_name, "stack"))
1264 rs6000_debug_stack = 1;
1265 else if (! strcmp (rs6000_debug_name, "arg"))
1266 rs6000_debug_arg = 1;
1268 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1271 if (rs6000_traceback_name)
1273 if (! strncmp (rs6000_traceback_name, "full", 4))
1274 rs6000_traceback = traceback_full;
1275 else if (! strncmp (rs6000_traceback_name, "part", 4))
1276 rs6000_traceback = traceback_part;
1277 else if (! strncmp (rs6000_traceback_name, "no", 2))
1278 rs6000_traceback = traceback_none;
1280 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1281 rs6000_traceback_name);
1284 /* Set size of long double */
1285 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1286 if (rs6000_long_double_size_string)
1289 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1290 if (*tail != '\0' || (size != 64 && size != 128))
1291 error ("Unknown switch -mlong-double-%s",
1292 rs6000_long_double_size_string);
1294 rs6000_long_double_type_size = size;
1297 /* Set Altivec ABI as default for powerpc64 linux. */
1298 if (TARGET_ELF && TARGET_64BIT)
1300 rs6000_altivec_abi = 1;
1301 rs6000_altivec_vrsave = 1;
1304 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1305 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1307 rs6000_darwin64_abi = 1;
1308 /* Setting to empty string is same as "-mone-byte-bool". */
1310 darwin_one_byte_bool = "";
1312 /* Default to natural alignment, for better performance. */
1313 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1316 /* Handle -mabi= options. */
1317 rs6000_parse_abi_options ();
1319 /* Handle -malign-XXXXX option. */
1320 rs6000_parse_alignment_option ();
1322 rs6000_parse_float_gprs_option ();
1324 /* Handle generic -mFOO=YES/NO options. */
1325 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1326 &rs6000_altivec_vrsave);
1327 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1329 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1331 /* Handle -mtls-size option. */
1332 rs6000_parse_tls_size_option ();
1334 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1335 SUBTARGET_OVERRIDE_OPTIONS;
1337 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1338 SUBSUBTARGET_OVERRIDE_OPTIONS;
1340 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1341 SUB3TARGET_OVERRIDE_OPTIONS;
1347 error ("AltiVec and E500 instructions cannot coexist");
1349 /* The e500 does not have string instructions, and we set
1350 MASK_STRING above when optimizing for size. */
1351 if ((target_flags & MASK_STRING) != 0)
1352 target_flags = target_flags & ~MASK_STRING;
1354 /* No SPE means 64-bit long doubles, even if an E500. */
1355 if (rs6000_spe_string != 0
1356 && !strcmp (rs6000_spe_string, "no"))
1357 rs6000_long_double_type_size = 64;
1359 else if (rs6000_select[1].string != NULL)
1361 /* For the powerpc-eabispe configuration, we set all these by
1362 default, so let's unset them if we manually set another
1363 CPU that is not the E500. */
1364 if (rs6000_abi_string == 0)
1366 if (rs6000_spe_string == 0)
1368 if (rs6000_float_gprs_string == 0)
1369 rs6000_float_gprs = 0;
1370 if (rs6000_isel_string == 0)
1372 if (rs6000_long_double_size_string == 0)
1373 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1376 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1377 && rs6000_cpu != PROCESSOR_POWER5);
1378 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1379 || rs6000_cpu == PROCESSOR_POWER5);
1381 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1382 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1383 bits in target_flags so TARGET_SWITCHES cannot be used.
1384 Assumption here is that rs6000_longcall_switch points into the
1385 text of the complete option, rather than being a copy, so we can
1386 scan back for the presence or absence of the no- modifier. */
1387 if (rs6000_longcall_switch)
1389 const char *base = rs6000_longcall_switch;
1390 while (base[-1] != 'm') base--;
1392 if (*rs6000_longcall_switch != '\0')
1393 error ("invalid option %qs", base);
1394 rs6000_default_long_calls = (base[0] != 'n');
1397 /* Handle -m(no-)warn-altivec-long similarly. */
1398 if (rs6000_warn_altivec_long_switch)
1400 const char *base = rs6000_warn_altivec_long_switch;
1401 while (base[-1] != 'm') base--;
1403 if (*rs6000_warn_altivec_long_switch != '\0')
1404 error ("invalid option %qs", base);
1405 rs6000_warn_altivec_long = (base[0] != 'n');
1408 /* Handle -mprioritize-restricted-insns option. */
1409 rs6000_sched_restricted_insns_priority
1410 = (rs6000_sched_groups ? 1 : 0);
1411 if (rs6000_sched_restricted_insns_priority_str)
1412 rs6000_sched_restricted_insns_priority =
1413 atoi (rs6000_sched_restricted_insns_priority_str);
1415 /* Handle -msched-costly-dep option. */
1416 rs6000_sched_costly_dep
1417 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1418 if (rs6000_sched_costly_dep_str)
1420 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1421 rs6000_sched_costly_dep = no_dep_costly;
1422 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1423 rs6000_sched_costly_dep = all_deps_costly;
1424 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1425 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1426 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1427 rs6000_sched_costly_dep = store_to_load_dep_costly;
1429 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1432 /* Handle -minsert-sched-nops option. */
1433 rs6000_sched_insert_nops
1434 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1435 if (rs6000_sched_insert_nops_str)
1437 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1438 rs6000_sched_insert_nops = sched_finish_none;
1439 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1440 rs6000_sched_insert_nops = sched_finish_pad_groups;
1441 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1442 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1444 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1447 #ifdef TARGET_REGNAMES
1448 /* If the user desires alternate register names, copy in the
1449 alternate names now. */
1450 if (TARGET_REGNAMES)
1451 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1454 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1455 If -maix-struct-return or -msvr4-struct-return was explicitly
1456 used, don't override with the ABI default. */
1457 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1459 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1460 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1462 target_flags |= MASK_AIX_STRUCT_RET;
1465 if (TARGET_LONG_DOUBLE_128
1466 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1467 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1469 /* Allocate an alias set for register saves & restores from stack. */
1470 rs6000_sr_alias_set = new_alias_set ();
1473 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1475 /* We can only guarantee the availability of DI pseudo-ops when
1476 assembling for 64-bit targets. */
1479 targetm.asm_out.aligned_op.di = NULL;
1480 targetm.asm_out.unaligned_op.di = NULL;
1483 /* Set branch target alignment, if not optimizing for size. */
1486 if (rs6000_sched_groups)
1488 if (align_functions <= 0)
1489 align_functions = 16;
1490 if (align_jumps <= 0)
1492 if (align_loops <= 0)
1495 if (align_jumps_max_skip <= 0)
1496 align_jumps_max_skip = 15;
1497 if (align_loops_max_skip <= 0)
1498 align_loops_max_skip = 15;
1501 /* Arrange to save and restore machine status around nested functions. */
1502 init_machine_status = rs6000_init_machine_status;
1504 /* We should always be splitting complex arguments, but we can't break
1505 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1506 if (DEFAULT_ABI != ABI_AIX)
1507 targetm.calls.split_complex_arg = NULL;
1509 /* Initialize rs6000_cost with the appropriate target costs. */
1511 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1515 case PROCESSOR_RIOS1:
1516 rs6000_cost = &rios1_cost;
1519 case PROCESSOR_RIOS2:
1520 rs6000_cost = &rios2_cost;
1523 case PROCESSOR_RS64A:
1524 rs6000_cost = &rs64a_cost;
1527 case PROCESSOR_MPCCORE:
1528 rs6000_cost = &mpccore_cost;
1531 case PROCESSOR_PPC403:
1532 rs6000_cost = &ppc403_cost;
1535 case PROCESSOR_PPC405:
1536 rs6000_cost = &ppc405_cost;
1539 case PROCESSOR_PPC440:
1540 rs6000_cost = &ppc440_cost;
1543 case PROCESSOR_PPC601:
1544 rs6000_cost = &ppc601_cost;
1547 case PROCESSOR_PPC603:
1548 rs6000_cost = &ppc603_cost;
1551 case PROCESSOR_PPC604:
1552 rs6000_cost = &ppc604_cost;
1555 case PROCESSOR_PPC604e:
1556 rs6000_cost = &ppc604e_cost;
1559 case PROCESSOR_PPC620:
1560 rs6000_cost = &ppc620_cost;
1563 case PROCESSOR_PPC630:
1564 rs6000_cost = &ppc630_cost;
1567 case PROCESSOR_PPC750:
1568 case PROCESSOR_PPC7400:
1569 rs6000_cost = &ppc750_cost;
1572 case PROCESSOR_PPC7450:
1573 rs6000_cost = &ppc7450_cost;
1576 case PROCESSOR_PPC8540:
1577 rs6000_cost = &ppc8540_cost;
1580 case PROCESSOR_POWER4:
1581 case PROCESSOR_POWER5:
1582 rs6000_cost = &power4_cost;
1590 /* Implement targetm.vectorize.builtin_mask_for_load. */
1592 rs6000_builtin_mask_for_load (void)
1595 return altivec_builtin_mask_for_load;
1600 /* Handle generic options of the form -mfoo=yes/no.
1601 NAME is the option name.
1602 VALUE is the option value.
1603 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1604 whether the option value is 'yes' or 'no' respectively. */
1606 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1610 else if (!strcmp (value, "yes"))
1612 else if (!strcmp (value, "no"))
1615 error ("unknown -m%s= option specified: '%s'", name, value);
1618 /* Handle -mabi= options. */
1620 rs6000_parse_abi_options (void)
1622 if (rs6000_abi_string == 0)
1624 else if (! strcmp (rs6000_abi_string, "altivec"))
1626 rs6000_altivec_abi = 1;
1629 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1630 rs6000_altivec_abi = 0;
1631 else if (! strcmp (rs6000_abi_string, "spe"))
1634 rs6000_altivec_abi = 0;
1635 if (!TARGET_SPE_ABI)
1636 error ("not configured for ABI: '%s'", rs6000_abi_string);
1639 /* These are here for testing during development only, do not
1640 document in the manual please. */
1641 else if (! strcmp (rs6000_abi_string, "d64"))
1643 rs6000_darwin64_abi = 1;
1644 warning ("Using darwin64 ABI");
1646 else if (! strcmp (rs6000_abi_string, "d32"))
1648 rs6000_darwin64_abi = 0;
1649 warning ("Using old darwin ABI");
1652 else if (! strcmp (rs6000_abi_string, "no-spe"))
1655 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1658 /* Handle -mfloat-gprs= options. */
1660 rs6000_parse_float_gprs_option (void)
1662 if (rs6000_float_gprs_string == 0)
1664 else if (! strcmp (rs6000_float_gprs_string, "yes")
1665 || ! strcmp (rs6000_float_gprs_string, "single"))
1666 rs6000_float_gprs = 1;
1667 else if (! strcmp (rs6000_float_gprs_string, "double"))
1668 rs6000_float_gprs = 2;
1669 else if (! strcmp (rs6000_float_gprs_string, "no"))
1670 rs6000_float_gprs = 0;
1672 error ("invalid option for -mfloat-gprs");
1675 /* Handle -malign-XXXXXX options. */
1677 rs6000_parse_alignment_option (void)
1679 if (rs6000_alignment_string == 0)
1681 else if (! strcmp (rs6000_alignment_string, "power"))
1683 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1684 some C library functions, so warn about it. The flag may be
1685 useful for performance studies from time to time though, so
1686 don't disable it entirely. */
1687 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1688 warning ("-malign-power is not supported for 64-bit Darwin;"
1689 " it is incompatible with the installed C and C++ libraries");
1690 rs6000_alignment_flags = MASK_ALIGN_POWER;
1692 else if (! strcmp (rs6000_alignment_string, "natural"))
1693 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1695 error ("unknown -malign-XXXXX option specified: '%s'",
1696 rs6000_alignment_string);
1699 /* Validate and record the size specified with the -mtls-size option. */
1702 rs6000_parse_tls_size_option (void)
1704 if (rs6000_tls_size_string == 0)
1706 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1707 rs6000_tls_size = 16;
1708 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1709 rs6000_tls_size = 32;
1710 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1711 rs6000_tls_size = 64;
1713 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1717 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1721 /* Do anything needed at the start of the asm file. */
1724 rs6000_file_start (void)
1728 const char *start = buffer;
1729 struct rs6000_cpu_select *ptr;
1730 const char *default_cpu = TARGET_CPU_DEFAULT;
1731 FILE *file = asm_out_file;
1733 default_file_start ();
1735 #ifdef TARGET_BI_ARCH
1736 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1740 if (flag_verbose_asm)
1742 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1743 rs6000_select[0].string = default_cpu;
1745 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1747 ptr = &rs6000_select[i];
1748 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1750 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1755 #ifdef USING_ELFOS_H
1756 switch (rs6000_sdata)
1758 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1759 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1760 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1761 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1764 if (rs6000_sdata && g_switch_value)
1766 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1776 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1784 /* Return nonzero if this function is known to have a null epilogue. */
1787 direct_return (void)
1789 if (reload_completed)
1791 rs6000_stack_t *info = rs6000_stack_info ();
1793 if (info->first_gp_reg_save == 32
1794 && info->first_fp_reg_save == 64
1795 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1796 && ! info->lr_save_p
1797 && ! info->cr_save_p
1798 && info->vrsave_mask == 0
1806 /* Return the number of instructions it takes to form a constant in an
1807 integer register. */
1810 num_insns_constant_wide (HOST_WIDE_INT value)
1812 /* signed constant loadable with {cal|addi} */
1813 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1816 /* constant loadable with {cau|addis} */
1817 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1820 #if HOST_BITS_PER_WIDE_INT == 64
1821 else if (TARGET_POWERPC64)
1823 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1824 HOST_WIDE_INT high = value >> 31;
1826 if (high == 0 || high == -1)
1832 return num_insns_constant_wide (high) + 1;
1834 return (num_insns_constant_wide (high)
1835 + num_insns_constant_wide (low) + 1);
1844 num_insns_constant (rtx op, enum machine_mode mode)
1846 if (GET_CODE (op) == CONST_INT)
1848 #if HOST_BITS_PER_WIDE_INT == 64
1849 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1850 && mask64_operand (op, mode))
1854 return num_insns_constant_wide (INTVAL (op));
1857 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1862 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1863 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1864 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1867 else if (GET_CODE (op) == CONST_DOUBLE)
1873 int endian = (WORDS_BIG_ENDIAN == 0);
1875 if (mode == VOIDmode || mode == DImode)
1877 high = CONST_DOUBLE_HIGH (op);
1878 low = CONST_DOUBLE_LOW (op);
1882 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1883 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1885 low = l[1 - endian];
1889 return (num_insns_constant_wide (low)
1890 + num_insns_constant_wide (high));
1894 if (high == 0 && low >= 0)
1895 return num_insns_constant_wide (low);
1897 else if (high == -1 && low < 0)
1898 return num_insns_constant_wide (low);
1900 else if (mask64_operand (op, mode))
1904 return num_insns_constant_wide (high) + 1;
1907 return (num_insns_constant_wide (high)
1908 + num_insns_constant_wide (low) + 1);
1916 /* Returns the constant for the splat instruction, if exists. */
1919 easy_vector_splat_const (int cst, enum machine_mode mode)
1924 if (EASY_VECTOR_15 (cst)
1925 || EASY_VECTOR_15_ADD_SELF (cst))
1927 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1933 if (EASY_VECTOR_15 (cst)
1934 || EASY_VECTOR_15_ADD_SELF (cst))
1936 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1942 if (EASY_VECTOR_15 (cst)
1943 || EASY_VECTOR_15_ADD_SELF (cst))
1951 /* Return nonzero if all elements of a vector have the same value. */
1954 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1958 units = CONST_VECTOR_NUNITS (op);
1960 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1961 for (i = 1; i < units; ++i)
1962 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1964 if (i == units && easy_vector_splat_const (cst, mode))
1969 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1972 gen_easy_vector_constant_add_self (rtx op)
1976 units = GET_MODE_NUNITS (GET_MODE (op));
1977 v = rtvec_alloc (units);
1979 for (i = 0; i < units; i++)
1981 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1982 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1986 output_vec_const_move (rtx *operands)
1989 enum machine_mode mode;
1995 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1996 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1997 mode = GET_MODE (dest);
2001 if (zero_constant (vec, mode))
2002 return "vxor %0,%0,%0";
2003 else if (easy_vector_constant (vec, mode))
2005 operands[1] = GEN_INT (cst);
2009 if (EASY_VECTOR_15 (cst))
2011 operands[1] = GEN_INT (cst);
2012 return "vspltisw %0,%1";
2014 else if (EASY_VECTOR_15_ADD_SELF (cst))
2020 if (EASY_VECTOR_15 (cst))
2022 operands[1] = GEN_INT (cst);
2023 return "vspltish %0,%1";
2025 else if (EASY_VECTOR_15_ADD_SELF (cst))
2031 if (EASY_VECTOR_15 (cst))
2033 operands[1] = GEN_INT (cst);
2034 return "vspltisb %0,%1";
2036 else if (EASY_VECTOR_15_ADD_SELF (cst))
2049 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2050 pattern of V1DI, V4HI, and V2SF.
2052 FIXME: We should probably return # and add post reload
2053 splitters for these, but this way is so easy ;-). */
2054 operands[1] = GEN_INT (cst);
2055 operands[2] = GEN_INT (cst2);
2057 return "li %0,%1\n\tevmergelo %0,%0,%0";
2059 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2066 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2069 if (GET_CODE (op) == CONST_INT)
2071 HOST_WIDE_INT c, lsb;
2076 /* Disallow all zeros. */
2080 /* We can use a single rlwinm insn if no upper bits of C are set
2081 AND there are zero, one or two transitions in the _whole_ of
2083 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2085 /* We don't change the number of transitions by inverting,
2086 so make sure we start with the LS bit zero. */
2090 /* Find the first transition. */
2093 /* Invert to look for a second transition. */
2096 /* Erase first transition. */
2099 /* Find the second transition. */
2102 /* Invert to look for a third transition. */
2105 /* Erase second transition. */
2108 if (one_ok && !(allow_one || c))
2111 /* Find the third transition (if any). */
2114 /* Match if all the bits above are 1's (or c is zero). */
2120 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2121 implement ANDing by the mask IN. */
2123 build_mask64_2_operands (rtx in, rtx *out)
2125 #if HOST_BITS_PER_WIDE_INT >= 64
2126 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2129 if (GET_CODE (in) != CONST_INT)
2135 /* Assume c initially something like 0x00fff000000fffff. The idea
2136 is to rotate the word so that the middle ^^^^^^ group of zeros
2137 is at the MS end and can be cleared with an rldicl mask. We then
2138 rotate back and clear off the MS ^^ group of zeros with a
2140 c = ~c; /* c == 0xff000ffffff00000 */
2141 lsb = c & -c; /* lsb == 0x0000000000100000 */
2142 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2143 c = ~c; /* c == 0x00fff000000fffff */
2144 c &= -lsb; /* c == 0x00fff00000000000 */
2145 lsb = c & -c; /* lsb == 0x0000100000000000 */
2146 c = ~c; /* c == 0xff000fffffffffff */
2147 c &= -lsb; /* c == 0xff00000000000000 */
2149 while ((lsb >>= 1) != 0)
2150 shift++; /* shift == 44 on exit from loop */
2151 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2152 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2153 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2157 /* Assume c initially something like 0xff000f0000000000. The idea
2158 is to rotate the word so that the ^^^ middle group of zeros
2159 is at the LS end and can be cleared with an rldicr mask. We then
2160 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2162 lsb = c & -c; /* lsb == 0x0000010000000000 */
2163 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2164 c = ~c; /* c == 0x00fff0ffffffffff */
2165 c &= -lsb; /* c == 0x00fff00000000000 */
2166 lsb = c & -c; /* lsb == 0x0000100000000000 */
2167 c = ~c; /* c == 0xff000fffffffffff */
2168 c &= -lsb; /* c == 0xff00000000000000 */
2170 while ((lsb >>= 1) != 0)
2171 shift++; /* shift == 44 on exit from loop */
2172 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2173 m1 >>= shift; /* m1 == 0x0000000000000fff */
2174 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2177 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2178 masks will be all 1's. We are guaranteed more than one transition. */
2179 out[0] = GEN_INT (64 - shift);
2180 out[1] = GEN_INT (m1);
2181 out[2] = GEN_INT (shift);
2182 out[3] = GEN_INT (m2);
2190 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2193 invalid_e500_subreg (rtx op, enum machine_mode mode)
2195 /* Reject (subreg:SI (reg:DF)). */
2196 if (GET_CODE (op) == SUBREG
2198 && REG_P (SUBREG_REG (op))
2199 && GET_MODE (SUBREG_REG (op)) == DFmode)
2202 /* Reject (subreg:DF (reg:DI)). */
2203 if (GET_CODE (op) == SUBREG
2205 && REG_P (SUBREG_REG (op))
2206 && GET_MODE (SUBREG_REG (op)) == DImode)
2212 /* Darwin, AIX increases natural record alignment to doubleword if the first
2213 field is an FP double while the FP fields remain word aligned. */
2216 rs6000_special_round_type_align (tree type, int computed, int specified)
2218 tree field = TYPE_FIELDS (type);
2220 /* Skip all non field decls */
2221 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2222 field = TREE_CHAIN (field);
2224 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2225 return MAX (computed, specified);
2227 return MAX (MAX (computed, specified), 64);
2230 /* Return 1 for an operand in small memory on V.4/eabi. */
2233 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2234 enum machine_mode mode ATTRIBUTE_UNUSED)
2239 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2242 if (DEFAULT_ABI != ABI_V4)
2245 if (GET_CODE (op) == SYMBOL_REF)
2248 else if (GET_CODE (op) != CONST
2249 || GET_CODE (XEXP (op, 0)) != PLUS
2250 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2251 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2256 rtx sum = XEXP (op, 0);
2257 HOST_WIDE_INT summand;
2259 /* We have to be careful here, because it is the referenced address
2260 that must be 32k from _SDA_BASE_, not just the symbol. */
2261 summand = INTVAL (XEXP (sum, 1));
2262 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2265 sym_ref = XEXP (sum, 0);
2268 return SYMBOL_REF_SMALL_P (sym_ref);
2274 /* Return true, if operand is a memory operand and has a
2275 displacement divisible by 4. */
2278 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2283 if (!memory_operand (op, mode))
2286 addr = XEXP (op, 0);
2287 if (GET_CODE (addr) == PLUS
2288 && GET_CODE (XEXP (addr, 0)) == REG
2289 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2290 off = INTVAL (XEXP (addr, 1));
2292 return (off % 4) == 0;
2295 /* Return true if either operand is a general purpose register. */
2298 gpr_or_gpr_p (rtx op0, rtx op1)
2300 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2301 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2305 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2308 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2310 switch (GET_CODE(op))
2313 if (RS6000_SYMBOL_REF_TLS_P (op))
2315 else if (CONSTANT_POOL_ADDRESS_P (op))
2317 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2325 else if (! strcmp (XSTR (op, 0), toc_label_name))
2334 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2335 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2337 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2346 constant_pool_expr_p (rtx op)
2350 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2354 toc_relative_expr_p (rtx op)
2358 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2362 legitimate_constant_pool_address_p (rtx x)
2365 && GET_CODE (x) == PLUS
2366 && GET_CODE (XEXP (x, 0)) == REG
2367 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2368 && constant_pool_expr_p (XEXP (x, 1)));
2372 legitimate_small_data_p (enum machine_mode mode, rtx x)
2374 return (DEFAULT_ABI == ABI_V4
2375 && !flag_pic && !TARGET_TOC
2376 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2377 && small_data_operand (x, mode));
2380 /* SPE offset addressing is limited to 5-bits worth of double words. */
2381 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2384 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2386 unsigned HOST_WIDE_INT offset, extra;
2388 if (GET_CODE (x) != PLUS)
2390 if (GET_CODE (XEXP (x, 0)) != REG)
2392 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2394 if (legitimate_constant_pool_address_p (x))
2396 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2399 offset = INTVAL (XEXP (x, 1));
2407 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2408 which leaves the only valid constant offset of zero, which by
2409 canonicalization rules is also invalid. */
2416 /* SPE vector modes. */
2417 return SPE_CONST_OFFSET_OK (offset);
2420 if (TARGET_E500_DOUBLE)
2421 return SPE_CONST_OFFSET_OK (offset);
2424 /* On e500v2, we may have:
2426 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2428 Which gets addressed with evldd instructions. */
2429 if (TARGET_E500_DOUBLE)
2430 return SPE_CONST_OFFSET_OK (offset);
2432 if (mode == DFmode || !TARGET_POWERPC64)
2434 else if (offset & 3)
2440 if (mode == TFmode || !TARGET_POWERPC64)
2442 else if (offset & 3)
2453 return (offset < 0x10000) && (offset + extra < 0x10000);
2457 legitimate_indexed_address_p (rtx x, int strict)
2461 if (GET_CODE (x) != PLUS)
2467 if (!REG_P (op0) || !REG_P (op1))
2470 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2471 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2472 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2473 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2477 legitimate_indirect_address_p (rtx x, int strict)
2479 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2483 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2485 if (!TARGET_MACHO || !flag_pic
2486 || mode != SImode || GET_CODE(x) != MEM)
2490 if (GET_CODE (x) != LO_SUM)
2492 if (GET_CODE (XEXP (x, 0)) != REG)
2494 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2498 return CONSTANT_P (x);
2502 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2504 if (GET_CODE (x) != LO_SUM)
2506 if (GET_CODE (XEXP (x, 0)) != REG)
2508 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2510 /* Restrict addressing for DI because of our SUBREG hackery. */
2511 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2515 if (TARGET_ELF || TARGET_MACHO)
2517 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2521 if (GET_MODE_NUNITS (mode) != 1)
2523 if (GET_MODE_BITSIZE (mode) > 64
2524 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2525 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2528 return CONSTANT_P (x);
2535 /* Try machine-dependent ways of modifying an illegitimate address
2536 to be legitimate. If we find one, return the new, valid address.
2537 This is used from only one place: `memory_address' in explow.c.
2539 OLDX is the address as it was before break_out_memory_refs was
2540 called. In some cases it is useful to look at this to decide what
2543 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2545 It is always safe for this function to do nothing. It exists to
2546 recognize opportunities to optimize the output.
2548 On RS/6000, first check for the sum of a register with a constant
2549 integer that is out of range. If so, generate code to add the
2550 constant with the low-order 16 bits masked to the register and force
2551 this result into another register (this can be done with `cau').
2552 Then generate an address of REG+(CONST&0xffff), allowing for the
2553 possibility of bit 16 being a one.
2555 Then check for the sum of a register and something not constant, try to
2556 load the other things into a register and return the sum. */
2559 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2560 enum machine_mode mode)
2562 if (GET_CODE (x) == SYMBOL_REF)
2564 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2566 return rs6000_legitimize_tls_address (x, model);
2569 if (GET_CODE (x) == PLUS
2570 && GET_CODE (XEXP (x, 0)) == REG
2571 && GET_CODE (XEXP (x, 1)) == CONST_INT
2572 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2574 HOST_WIDE_INT high_int, low_int;
2576 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2577 high_int = INTVAL (XEXP (x, 1)) - low_int;
2578 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2579 GEN_INT (high_int)), 0);
2580 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2582 else if (GET_CODE (x) == PLUS
2583 && GET_CODE (XEXP (x, 0)) == REG
2584 && GET_CODE (XEXP (x, 1)) != CONST_INT
2585 && GET_MODE_NUNITS (mode) == 1
2586 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2588 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2590 && (TARGET_POWERPC64 || mode != DImode)
2593 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2594 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2596 else if (ALTIVEC_VECTOR_MODE (mode))
2600 /* Make sure both operands are registers. */
2601 if (GET_CODE (x) == PLUS)
2602 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2603 force_reg (Pmode, XEXP (x, 1)));
2605 reg = force_reg (Pmode, x);
2608 else if (SPE_VECTOR_MODE (mode)
2609 || (TARGET_E500_DOUBLE && (mode == DFmode
2610 || mode == DImode)))
2614 /* We accept [reg + reg] and [reg + OFFSET]. */
2616 if (GET_CODE (x) == PLUS)
2618 rtx op1 = XEXP (x, 0);
2619 rtx op2 = XEXP (x, 1);
2621 op1 = force_reg (Pmode, op1);
2623 if (GET_CODE (op2) != REG
2624 && (GET_CODE (op2) != CONST_INT
2625 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2626 op2 = force_reg (Pmode, op2);
2628 return gen_rtx_PLUS (Pmode, op1, op2);
2631 return force_reg (Pmode, x);
2637 && GET_CODE (x) != CONST_INT
2638 && GET_CODE (x) != CONST_DOUBLE
2640 && GET_MODE_NUNITS (mode) == 1
2641 && (GET_MODE_BITSIZE (mode) <= 32
2642 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2644 rtx reg = gen_reg_rtx (Pmode);
2645 emit_insn (gen_elf_high (reg, x));
2646 return gen_rtx_LO_SUM (Pmode, reg, x);
2648 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2651 && ! MACHO_DYNAMIC_NO_PIC_P
2653 && GET_CODE (x) != CONST_INT
2654 && GET_CODE (x) != CONST_DOUBLE
2656 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2660 rtx reg = gen_reg_rtx (Pmode);
2661 emit_insn (gen_macho_high (reg, x));
2662 return gen_rtx_LO_SUM (Pmode, reg, x);
2665 && constant_pool_expr_p (x)
2666 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2668 return create_TOC_reference (x);
2674 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2675 We need to emit DTP-relative relocations. */
2678 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2683 fputs ("\t.long\t", file);
2686 fputs (DOUBLE_INT_ASM_OP, file);
2691 output_addr_const (file, x);
2692 fputs ("@dtprel+0x8000", file);
2695 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2697 static GTY(()) rtx rs6000_tls_symbol;
2699 rs6000_tls_get_addr (void)
2701 if (!rs6000_tls_symbol)
2702 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2704 return rs6000_tls_symbol;
2707 /* Construct the SYMBOL_REF for TLS GOT references. */
2709 static GTY(()) rtx rs6000_got_symbol;
2711 rs6000_got_sym (void)
2713 if (!rs6000_got_symbol)
2715 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2716 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2717 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2720 return rs6000_got_symbol;
2723 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2724 this (thread-local) address. */
2727 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2731 dest = gen_reg_rtx (Pmode);
2732 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2738 tlsreg = gen_rtx_REG (Pmode, 13);
2739 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2743 tlsreg = gen_rtx_REG (Pmode, 2);
2744 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2748 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2752 tmp = gen_reg_rtx (Pmode);
2755 tlsreg = gen_rtx_REG (Pmode, 13);
2756 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2760 tlsreg = gen_rtx_REG (Pmode, 2);
2761 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2765 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2767 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2772 rtx r3, got, tga, tmp1, tmp2, eqv;
2775 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2779 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2782 rtx gsym = rs6000_got_sym ();
2783 got = gen_reg_rtx (Pmode);
2785 rs6000_emit_move (got, gsym, Pmode);
2789 static int tls_got_labelno = 0;
2790 rtx tempLR, lab, tmp3, mem;
2793 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2794 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2795 tempLR = gen_reg_rtx (Pmode);
2796 tmp1 = gen_reg_rtx (Pmode);
2797 tmp2 = gen_reg_rtx (Pmode);
2798 tmp3 = gen_reg_rtx (Pmode);
2799 mem = gen_const_mem (Pmode, tmp1);
2801 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2803 emit_move_insn (tmp1, tempLR);
2804 emit_move_insn (tmp2, mem);
2805 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2806 last = emit_move_insn (got, tmp3);
2807 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2809 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2811 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2817 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2819 r3 = gen_rtx_REG (Pmode, 3);
2821 insn = gen_tls_gd_64 (r3, got, addr);
2823 insn = gen_tls_gd_32 (r3, got, addr);
2826 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2827 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2828 insn = emit_call_insn (insn);
2829 CONST_OR_PURE_CALL_P (insn) = 1;
2830 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2831 insn = get_insns ();
2833 emit_libcall_block (insn, dest, r3, addr);
2835 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2837 r3 = gen_rtx_REG (Pmode, 3);
2839 insn = gen_tls_ld_64 (r3, got);
2841 insn = gen_tls_ld_32 (r3, got);
2844 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2845 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2846 insn = emit_call_insn (insn);
2847 CONST_OR_PURE_CALL_P (insn) = 1;
2848 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2849 insn = get_insns ();
2851 tmp1 = gen_reg_rtx (Pmode);
2852 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2854 emit_libcall_block (insn, tmp1, r3, eqv);
2855 if (rs6000_tls_size == 16)
2858 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2860 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2862 else if (rs6000_tls_size == 32)
2864 tmp2 = gen_reg_rtx (Pmode);
2866 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2868 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2871 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2873 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2877 tmp2 = gen_reg_rtx (Pmode);
2879 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2881 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2883 insn = gen_rtx_SET (Pmode, dest,
2884 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2890 /* IE, or 64 bit offset LE. */
2891 tmp2 = gen_reg_rtx (Pmode);
2893 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2895 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2898 insn = gen_tls_tls_64 (dest, tmp2, addr);
2900 insn = gen_tls_tls_32 (dest, tmp2, addr);
2908 /* Return 1 if X contains a thread-local symbol. */
2911 rs6000_tls_referenced_p (rtx x)
2913 if (! TARGET_HAVE_TLS)
2916 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2919 /* Return 1 if *X is a thread-local symbol. This is the same as
2920 rs6000_tls_symbol_ref except for the type of the unused argument. */
2923 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2925 return RS6000_SYMBOL_REF_TLS_P (*x);
2928 /* The convention appears to be to define this wherever it is used.
2929 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2930 is now used here. */
2931 #ifndef REG_MODE_OK_FOR_BASE_P
2932 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2935 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2936 replace the input X, or the original X if no replacement is called for.
2937 The output parameter *WIN is 1 if the calling macro should goto WIN,
2940 For RS/6000, we wish to handle large displacements off a base
2941 register by splitting the addend across an addiu/addis and the mem insn.
2942 This cuts number of extra insns needed from 3 to 1.
2944 On Darwin, we use this to generate code for floating point constants.
2945 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2946 The Darwin code is inside #if TARGET_MACHO because only then is
2947 machopic_function_base_name() defined. */
2949 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2950 int opnum, int type,
2951 int ind_levels ATTRIBUTE_UNUSED, int *win)
2953 /* We must recognize output that we have already generated ourselves. */
2954 if (GET_CODE (x) == PLUS
2955 && GET_CODE (XEXP (x, 0)) == PLUS
2956 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2957 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2958 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2960 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2961 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2962 opnum, (enum reload_type)type);
2968 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2969 && GET_CODE (x) == LO_SUM
2970 && GET_CODE (XEXP (x, 0)) == PLUS
2971 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2972 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2973 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2974 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2975 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2976 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2977 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2979 /* Result of previous invocation of this function on Darwin
2980 floating point constant. */
2981 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2982 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2983 opnum, (enum reload_type)type);
2989 /* Force ld/std non-word aligned offset into base register by wrapping
2991 if (GET_CODE (x) == PLUS
2992 && GET_CODE (XEXP (x, 0)) == REG
2993 && REGNO (XEXP (x, 0)) < 32
2994 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2995 && GET_CODE (XEXP (x, 1)) == CONST_INT
2996 && (INTVAL (XEXP (x, 1)) & 3) != 0
2997 && !ALTIVEC_VECTOR_MODE (mode)
2998 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
2999 && TARGET_POWERPC64)
3001 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3002 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3003 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3004 opnum, (enum reload_type) type);
3009 if (GET_CODE (x) == PLUS
3010 && GET_CODE (XEXP (x, 0)) == REG
3011 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3012 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3013 && GET_CODE (XEXP (x, 1)) == CONST_INT
3014 && !SPE_VECTOR_MODE (mode)
3015 && !(TARGET_E500_DOUBLE && (mode == DFmode
3017 && !ALTIVEC_VECTOR_MODE (mode))
3019 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3020 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3022 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3024 /* Check for 32-bit overflow. */
3025 if (high + low != val)
3031 /* Reload the high part into a base reg; leave the low part
3032 in the mem directly. */
3034 x = gen_rtx_PLUS (GET_MODE (x),
3035 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3039 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3040 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3041 opnum, (enum reload_type)type);
3047 if (GET_CODE (x) == SYMBOL_REF
3048 && DEFAULT_ABI == ABI_DARWIN
3049 && !ALTIVEC_VECTOR_MODE (mode)
3050 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3051 /* Don't do this for TFmode, since the result isn't offsettable.
3052 The same goes for DImode without 64-bit gprs. */
3054 && (mode != DImode || TARGET_POWERPC64))
3058 rtx offset = gen_rtx_CONST (Pmode,
3059 gen_rtx_MINUS (Pmode, x,
3060 machopic_function_base_sym ()));
3061 x = gen_rtx_LO_SUM (GET_MODE (x),
3062 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3063 gen_rtx_HIGH (Pmode, offset)), offset);
3066 x = gen_rtx_LO_SUM (GET_MODE (x),
3067 gen_rtx_HIGH (Pmode, x), x);
3069 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3070 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3071 opnum, (enum reload_type)type);
3078 && constant_pool_expr_p (x)
3079 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3081 (x) = create_TOC_reference (x);
3089 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3090 that is a valid memory address for an instruction.
3091 The MODE argument is the machine mode for the MEM expression
3092 that wants to use this address.
3094 On the RS/6000, there are four valid address: a SYMBOL_REF that
3095 refers to a constant pool entry of an address (or the sum of it
3096 plus a constant), a short (16-bit signed) constant plus a register,
3097 the sum of two registers, or a register indirect, possibly with an
3098 auto-increment. For DFmode and DImode with a constant plus register,
3099 we must ensure that both words are addressable or PowerPC64 with offset
3102 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3103 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3104 adjacent memory cells are accessed by adding word-sized offsets
3105 during assembly output. */
3107 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3109 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3111 && ALTIVEC_VECTOR_MODE (mode)
3112 && GET_CODE (x) == AND
3113 && GET_CODE (XEXP (x, 1)) == CONST_INT
3114 && INTVAL (XEXP (x, 1)) == -16)
3117 if (RS6000_SYMBOL_REF_TLS_P (x))
3119 if (legitimate_indirect_address_p (x, reg_ok_strict))
3121 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3122 && !ALTIVEC_VECTOR_MODE (mode)
3123 && !SPE_VECTOR_MODE (mode)
3124 /* Restrict addressing for DI because of our SUBREG hackery. */
3125 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3127 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3129 if (legitimate_small_data_p (mode, x))
3131 if (legitimate_constant_pool_address_p (x))
3133 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3135 && GET_CODE (x) == PLUS
3136 && GET_CODE (XEXP (x, 0)) == REG
3137 && (XEXP (x, 0) == virtual_stack_vars_rtx
3138 || XEXP (x, 0) == arg_pointer_rtx)
3139 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3141 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3145 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3147 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3148 && (TARGET_POWERPC64 || mode != DImode)
3149 && legitimate_indexed_address_p (x, reg_ok_strict))
3151 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3156 /* Go to LABEL if ADDR (a legitimate address expression)
3157 has an effect that depends on the machine mode it is used for.
3159 On the RS/6000 this is true of all integral offsets (since AltiVec
3160 modes don't allow them) or is a pre-increment or decrement.
3162 ??? Except that due to conceptual problems in offsettable_address_p
3163 we can't really report the problems of integral offsets. So leave
3164 this assuming that the adjustable offset must be valid for the
3165 sub-words of a TFmode operand, which is what we had before. */
3168 rs6000_mode_dependent_address (rtx addr)
3170 switch (GET_CODE (addr))
3173 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3175 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3176 return val + 12 + 0x8000 >= 0x10000;
3185 return TARGET_UPDATE;
3194 /* Return number of consecutive hard regs needed starting at reg REGNO
3195 to hold something of mode MODE.
3196 This is ordinarily the length in words of a value of mode MODE
3197 but can be less for certain modes in special long registers.
3199 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3200 scalar instructions. The upper 32 bits are only available to the
3203 POWER and PowerPC GPRs hold 32 bits worth;
3204 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3207 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3209 if (FP_REGNO_P (regno))
3210 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3212 if (TARGET_E500_DOUBLE && mode == DFmode)
3215 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3216 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3218 if (ALTIVEC_REGNO_P (regno))
3220 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3222 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3225 /* Change register usage conditional on target flags. */
3227 rs6000_conditional_register_usage (void)
3231 /* Set MQ register fixed (already call_used) if not POWER
3232 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3237 /* 64-bit AIX reserves GPR13 for thread-private data. */
3239 fixed_regs[13] = call_used_regs[13]
3240 = call_really_used_regs[13] = 1;
3242 /* Conditionally disable FPRs. */
3243 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3244 for (i = 32; i < 64; i++)
3245 fixed_regs[i] = call_used_regs[i]
3246 = call_really_used_regs[i] = 1;
3248 if (DEFAULT_ABI == ABI_V4
3249 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3251 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3253 if (DEFAULT_ABI == ABI_V4
3254 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3256 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3257 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3258 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3260 if (DEFAULT_ABI == ABI_DARWIN
3261 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3262 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3263 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3264 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3265 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3267 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3268 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3269 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3272 global_regs[VSCR_REGNO] = 1;
3276 global_regs[SPEFSCR_REGNO] = 1;
3277 fixed_regs[FIXED_SCRATCH]
3278 = call_used_regs[FIXED_SCRATCH]
3279 = call_really_used_regs[FIXED_SCRATCH] = 1;
3282 if (! TARGET_ALTIVEC)
3284 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3285 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3286 call_really_used_regs[VRSAVE_REGNO] = 1;
3289 if (TARGET_ALTIVEC_ABI)
3290 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3291 call_used_regs[i] = call_really_used_regs[i] = 1;
3294 /* Try to output insns to set TARGET equal to the constant C if it can
3295 be done in less than N insns. Do all computations in MODE.
3296 Returns the place where the output has been placed if it can be
3297 done and the insns have been emitted. If it would take more than N
3298 insns, zero is returned and no insns and emitted. */
3301 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3302 rtx source, int n ATTRIBUTE_UNUSED)
3304 rtx result, insn, set;
3305 HOST_WIDE_INT c0, c1;
3307 if (mode == QImode || mode == HImode)
3310 dest = gen_reg_rtx (mode);
3311 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3314 else if (mode == SImode)
3316 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3318 emit_insn (gen_rtx_SET (VOIDmode, result,
3319 GEN_INT (INTVAL (source)
3320 & (~ (HOST_WIDE_INT) 0xffff))));
3321 emit_insn (gen_rtx_SET (VOIDmode, dest,
3322 gen_rtx_IOR (SImode, result,
3323 GEN_INT (INTVAL (source) & 0xffff))));
3326 else if (mode == DImode)
3328 if (GET_CODE (source) == CONST_INT)
3330 c0 = INTVAL (source);
3333 else if (GET_CODE (source) == CONST_DOUBLE)
3335 #if HOST_BITS_PER_WIDE_INT >= 64
3336 c0 = CONST_DOUBLE_LOW (source);
3339 c0 = CONST_DOUBLE_LOW (source);
3340 c1 = CONST_DOUBLE_HIGH (source);
3346 result = rs6000_emit_set_long_const (dest, c0, c1);
3351 insn = get_last_insn ();
3352 set = single_set (insn);
3353 if (! CONSTANT_P (SET_SRC (set)))
3354 set_unique_reg_note (insn, REG_EQUAL, source);
3359 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3360 fall back to a straight forward decomposition. We do this to avoid
3361 exponential run times encountered when looking for longer sequences
3362 with rs6000_emit_set_const. */
3364 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3366 if (!TARGET_POWERPC64)
3368 rtx operand1, operand2;
3370 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3372 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3374 emit_move_insn (operand1, GEN_INT (c1));
3375 emit_move_insn (operand2, GEN_INT (c2));
3379 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3382 ud2 = (c1 & 0xffff0000) >> 16;
3383 #if HOST_BITS_PER_WIDE_INT >= 64
3387 ud4 = (c2 & 0xffff0000) >> 16;
3389 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3390 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3393 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3395 emit_move_insn (dest, GEN_INT (ud1));
3398 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3399 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3402 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3405 emit_move_insn (dest, GEN_INT (ud2 << 16));
3407 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3409 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3410 || (ud4 == 0 && ! (ud3 & 0x8000)))
3413 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3416 emit_move_insn (dest, GEN_INT (ud3 << 16));
3419 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3420 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3422 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3427 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3430 emit_move_insn (dest, GEN_INT (ud4 << 16));
3433 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3435 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3437 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3438 GEN_INT (ud2 << 16)));
3440 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3446 /* Helper for the following. Get rid of [r+r] memory refs
3447 in cases where it won't work (TImode, TFmode). */
3450 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3452 if (GET_CODE (operands[0]) == MEM
3453 && GET_CODE (XEXP (operands[0], 0)) != REG
3454 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3455 && ! reload_in_progress)
3457 = replace_equiv_address (operands[0],
3458 copy_addr_to_reg (XEXP (operands[0], 0)));
3460 if (GET_CODE (operands[1]) == MEM
3461 && GET_CODE (XEXP (operands[1], 0)) != REG
3462 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3463 && ! reload_in_progress)
3465 = replace_equiv_address (operands[1],
3466 copy_addr_to_reg (XEXP (operands[1], 0)));
3469 /* Emit a move from SOURCE to DEST in mode MODE. */
3471 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3475 operands[1] = source;
3477 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3478 if (GET_CODE (operands[1]) == CONST_DOUBLE
3479 && ! FLOAT_MODE_P (mode)
3480 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3482 /* FIXME. This should never happen. */
3483 /* Since it seems that it does, do the safe thing and convert
3485 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3487 if (GET_CODE (operands[1]) == CONST_DOUBLE
3488 && ! FLOAT_MODE_P (mode)
3489 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3490 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3491 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3492 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3495 /* Check if GCC is setting up a block move that will end up using FP
3496 registers as temporaries. We must make sure this is acceptable. */
3497 if (GET_CODE (operands[0]) == MEM
3498 && GET_CODE (operands[1]) == MEM
3500 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3501 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3502 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3503 ? 32 : MEM_ALIGN (operands[0])))
3504 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3506 : MEM_ALIGN (operands[1]))))
3507 && ! MEM_VOLATILE_P (operands [0])
3508 && ! MEM_VOLATILE_P (operands [1]))
3510 emit_move_insn (adjust_address (operands[0], SImode, 0),
3511 adjust_address (operands[1], SImode, 0));
3512 emit_move_insn (adjust_address (operands[0], SImode, 4),
3513 adjust_address (operands[1], SImode, 4));
3517 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3518 && !gpc_reg_operand (operands[1], mode))
3519 operands[1] = force_reg (mode, operands[1]);
3521 if (mode == SFmode && ! TARGET_POWERPC
3522 && TARGET_HARD_FLOAT && TARGET_FPRS
3523 && GET_CODE (operands[0]) == MEM)
3527 if (reload_in_progress || reload_completed)
3528 regnum = true_regnum (operands[1]);
3529 else if (GET_CODE (operands[1]) == REG)
3530 regnum = REGNO (operands[1]);
3534 /* If operands[1] is a register, on POWER it may have
3535 double-precision data in it, so truncate it to single
3537 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3540 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3541 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3542 operands[1] = newreg;
3546 /* Recognize the case where operand[1] is a reference to thread-local
3547 data and load its address to a register. */
3548 if (GET_CODE (operands[1]) == SYMBOL_REF)
3550 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3552 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3555 /* Handle the case where reload calls us with an invalid address. */
3556 if (reload_in_progress && mode == Pmode
3557 && (! general_operand (operands[1], mode)
3558 || ! nonimmediate_operand (operands[0], mode)))
3561 /* 128-bit constant floating-point values on Darwin should really be
3562 loaded as two parts. */
3563 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3564 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3565 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3567 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3568 know how to get a DFmode SUBREG of a TFmode. */
3569 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3570 simplify_gen_subreg (DImode, operands[1], mode, 0),
3572 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3573 GET_MODE_SIZE (DImode)),
3574 simplify_gen_subreg (DImode, operands[1], mode,
3575 GET_MODE_SIZE (DImode)),
3580 /* FIXME: In the long term, this switch statement should go away
3581 and be replaced by a sequence of tests based on things like
3587 if (CONSTANT_P (operands[1])
3588 && GET_CODE (operands[1]) != CONST_INT)
3589 operands[1] = force_const_mem (mode, operands[1]);
3593 rs6000_eliminate_indexed_memrefs (operands);
3598 if (CONSTANT_P (operands[1])
3599 && ! easy_fp_constant (operands[1], mode))
3600 operands[1] = force_const_mem (mode, operands[1]);
3611 if (CONSTANT_P (operands[1])
3612 && !easy_vector_constant (operands[1], mode))
3613 operands[1] = force_const_mem (mode, operands[1]);
3618 /* Use default pattern for address of ELF small data */
3621 && DEFAULT_ABI == ABI_V4
3622 && (GET_CODE (operands[1]) == SYMBOL_REF
3623 || GET_CODE (operands[1]) == CONST)
3624 && small_data_operand (operands[1], mode))
3626 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3630 if (DEFAULT_ABI == ABI_V4
3631 && mode == Pmode && mode == SImode
3632 && flag_pic == 1 && got_operand (operands[1], mode))
3634 emit_insn (gen_movsi_got (operands[0], operands[1]));
3638 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3642 && CONSTANT_P (operands[1])
3643 && GET_CODE (operands[1]) != HIGH
3644 && GET_CODE (operands[1]) != CONST_INT)
3646 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3648 /* If this is a function address on -mcall-aixdesc,
3649 convert it to the address of the descriptor. */
3650 if (DEFAULT_ABI == ABI_AIX
3651 && GET_CODE (operands[1]) == SYMBOL_REF
3652 && XSTR (operands[1], 0)[0] == '.')
3654 const char *name = XSTR (operands[1], 0);
3656 while (*name == '.')
3658 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3659 CONSTANT_POOL_ADDRESS_P (new_ref)
3660 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3661 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3662 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3663 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3664 operands[1] = new_ref;
3667 if (DEFAULT_ABI == ABI_DARWIN)
3670 if (MACHO_DYNAMIC_NO_PIC_P)
3672 /* Take care of any required data indirection. */
3673 operands[1] = rs6000_machopic_legitimize_pic_address (
3674 operands[1], mode, operands[0]);
3675 if (operands[0] != operands[1])
3676 emit_insn (gen_rtx_SET (VOIDmode,
3677 operands[0], operands[1]));
3681 emit_insn (gen_macho_high (target, operands[1]));
3682 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3686 emit_insn (gen_elf_high (target, operands[1]));
3687 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3691 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3692 and we have put it in the TOC, we just need to make a TOC-relative
3695 && GET_CODE (operands[1]) == SYMBOL_REF
3696 && constant_pool_expr_p (operands[1])
3697 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3698 get_pool_mode (operands[1])))
3700 operands[1] = create_TOC_reference (operands[1]);
3702 else if (mode == Pmode
3703 && CONSTANT_P (operands[1])
3704 && ((GET_CODE (operands[1]) != CONST_INT
3705 && ! easy_fp_constant (operands[1], mode))
3706 || (GET_CODE (operands[1]) == CONST_INT
3707 && num_insns_constant (operands[1], mode) > 2)
3708 || (GET_CODE (operands[0]) == REG
3709 && FP_REGNO_P (REGNO (operands[0]))))
3710 && GET_CODE (operands[1]) != HIGH
3711 && ! legitimate_constant_pool_address_p (operands[1])
3712 && ! toc_relative_expr_p (operands[1]))
3714 /* Emit a USE operation so that the constant isn't deleted if
3715 expensive optimizations are turned on because nobody
3716 references it. This should only be done for operands that
3717 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3718 This should not be done for operands that contain LABEL_REFs.
3719 For now, we just handle the obvious case. */
3720 if (GET_CODE (operands[1]) != LABEL_REF)
3721 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3724 /* Darwin uses a special PIC legitimizer. */
3725 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3728 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3730 if (operands[0] != operands[1])
3731 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3736 /* If we are to limit the number of things we put in the TOC and
3737 this is a symbol plus a constant we can add in one insn,
3738 just put the symbol in the TOC and add the constant. Don't do
3739 this if reload is in progress. */
3740 if (GET_CODE (operands[1]) == CONST
3741 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3742 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3743 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3744 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3745 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3746 && ! side_effects_p (operands[0]))
3749 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3750 rtx other = XEXP (XEXP (operands[1], 0), 1);
3752 sym = force_reg (mode, sym);
3754 emit_insn (gen_addsi3 (operands[0], sym, other));
3756 emit_insn (gen_adddi3 (operands[0], sym, other));
3760 operands[1] = force_const_mem (mode, operands[1]);
3763 && constant_pool_expr_p (XEXP (operands[1], 0))
3764 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3765 get_pool_constant (XEXP (operands[1], 0)),
3766 get_pool_mode (XEXP (operands[1], 0))))
3769 = gen_const_mem (mode,
3770 create_TOC_reference (XEXP (operands[1], 0)));
3771 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3777 rs6000_eliminate_indexed_memrefs (operands);
3781 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3783 gen_rtx_SET (VOIDmode,
3784 operands[0], operands[1]),
3785 gen_rtx_CLOBBER (VOIDmode,
3786 gen_rtx_SCRATCH (SImode)))));
3795 /* Above, we may have called force_const_mem which may have returned
3796 an invalid address. If we can, fix this up; otherwise, reload will
3797 have to deal with it. */
3798 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3799 operands[1] = validize_mem (operands[1]);
3802 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3805 /* Nonzero if we can use a floating-point register to pass this arg. */
3806 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3807 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3808 && (CUM)->fregno <= FP_ARG_MAX_REG \
3809 && TARGET_HARD_FLOAT && TARGET_FPRS)
3811 /* Nonzero if we can use an AltiVec register to pass this arg. */
3812 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3813 (ALTIVEC_VECTOR_MODE (MODE) \
3814 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3815 && TARGET_ALTIVEC_ABI \
3818 /* Return a nonzero value to say to return the function value in
3819 memory, just as large structures are always returned. TYPE will be
3820 the data type of the value, and FNTYPE will be the type of the
3821 function doing the returning, or @code{NULL} for libcalls.
3823 The AIX ABI for the RS/6000 specifies that all structures are
3824 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3825 specifies that structures <= 8 bytes are returned in r3/r4, but a
3826 draft put them in memory, and GCC used to implement the draft
3827 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3828 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3829 compatibility can change DRAFT_V4_STRUCT_RET to override the
3830 default, and -m switches get the final word. See
3831 rs6000_override_options for more details.
3833 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3834 long double support is enabled. These values are returned in memory.
3836 int_size_in_bytes returns -1 for variable size objects, which go in
3837 memory always. The cast to unsigned makes -1 > 8. */
3840 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3842 /* In the darwin64 abi, try to use registers for larger structs
3844 if (rs6000_darwin64_abi
3845 && TREE_CODE (type) == RECORD_TYPE
3846 && int_size_in_bytes (type) > 0)
3848 CUMULATIVE_ARGS valcum;
3852 valcum.fregno = FP_ARG_MIN_REG;
3853 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3854 /* Do a trial code generation as if this were going to be passed
3855 as an argument; if any part goes in memory, we return NULL. */
3856 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3859 /* Otherwise fall through to more conventional ABI rules. */
3862 if (AGGREGATE_TYPE_P (type)
3863 && (TARGET_AIX_STRUCT_RET
3864 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3867 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3868 modes only exist for GCC vector types if -maltivec. */
3869 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3870 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3873 /* Return synthetic vectors in memory. */
3874 if (TREE_CODE (type) == VECTOR_TYPE
3875 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
3877 static bool warned_for_return_big_vectors = false;
3878 if (!warned_for_return_big_vectors)
3880 warning ("GCC vector returned by reference: "
3881 "non-standard ABI extension with no compatibility guarantee");
3882 warned_for_return_big_vectors = true;
3887 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3893 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3894 for a call to a function whose data type is FNTYPE.
3895 For a library call, FNTYPE is 0.
3897 For incoming args we set the number of arguments in the prototype large
3898 so we never return a PARALLEL. */
3901 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3902 rtx libname ATTRIBUTE_UNUSED, int incoming,
3903 int libcall, int n_named_args)
3905 static CUMULATIVE_ARGS zero_cumulative;
3907 *cum = zero_cumulative;
3909 cum->fregno = FP_ARG_MIN_REG;
3910 cum->vregno = ALTIVEC_ARG_MIN_REG;
3911 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3912 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3913 ? CALL_LIBCALL : CALL_NORMAL);
3914 cum->sysv_gregno = GP_ARG_MIN_REG;
3915 cum->stdarg = fntype
3916 && (TYPE_ARG_TYPES (fntype) != 0
3917 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3918 != void_type_node));
3920 cum->nargs_prototype = 0;
3921 if (incoming || cum->prototype)
3922 cum->nargs_prototype = n_named_args;
3924 /* Check for a longcall attribute. */
3925 if ((!fntype && rs6000_default_long_calls)
3927 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3928 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3929 cum->call_cookie |= CALL_LONG;
3931 if (TARGET_DEBUG_ARG)
3933 fprintf (stderr, "\ninit_cumulative_args:");
3936 tree ret_type = TREE_TYPE (fntype);
3937 fprintf (stderr, " ret code = %s,",
3938 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3941 if (cum->call_cookie & CALL_LONG)
3942 fprintf (stderr, " longcall,");
3944 fprintf (stderr, " proto = %d, nargs = %d\n",
3945 cum->prototype, cum->nargs_prototype);
3950 && TARGET_ALTIVEC_ABI
3951 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3953 error ("Cannot return value in vector register because"
3954 " altivec instructions are disabled, use -maltivec"
3955 " to enable them.");
3959 /* Return true if TYPE must be passed on the stack and not in registers. */
3962 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3964 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3965 return must_pass_in_stack_var_size (mode, type);
3967 return must_pass_in_stack_var_size_or_pad (mode, type);
3970 /* If defined, a C expression which determines whether, and in which
3971 direction, to pad out an argument with extra space. The value
3972 should be of type `enum direction': either `upward' to pad above
3973 the argument, `downward' to pad below, or `none' to inhibit
3976 For the AIX ABI structs are always stored left shifted in their
3980 function_arg_padding (enum machine_mode mode, tree type)
3982 #ifndef AGGREGATE_PADDING_FIXED
3983 #define AGGREGATE_PADDING_FIXED 0
3985 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3986 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3989 if (!AGGREGATE_PADDING_FIXED)
3991 /* GCC used to pass structures of the same size as integer types as
3992 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3993 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3994 passed padded downward, except that -mstrict-align further
3995 muddied the water in that multi-component structures of 2 and 4
3996 bytes in size were passed padded upward.
3998 The following arranges for best compatibility with previous
3999 versions of gcc, but removes the -mstrict-align dependency. */
4000 if (BYTES_BIG_ENDIAN)
4002 HOST_WIDE_INT size = 0;
4004 if (mode == BLKmode)
4006 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4007 size = int_size_in_bytes (type);
4010 size = GET_MODE_SIZE (mode);
4012 if (size == 1 || size == 2 || size == 4)
4018 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4020 if (type != 0 && AGGREGATE_TYPE_P (type))
4024 /* Fall back to the default. */
4025 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4028 /* If defined, a C expression that gives the alignment boundary, in bits,
4029 of an argument with the specified mode and type. If it is not defined,
4030 PARM_BOUNDARY is used for all arguments.
4032 V.4 wants long longs to be double word aligned.
4033 Doubleword align SPE vectors.
4034 Quadword align Altivec vectors.
4035 Quadword align large synthetic vector types. */
4038 function_arg_boundary (enum machine_mode mode, tree type)
4040 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4042 else if (SPE_VECTOR_MODE (mode)
4043 || (type && TREE_CODE (type) == VECTOR_TYPE
4044 && int_size_in_bytes (type) >= 8
4045 && int_size_in_bytes (type) < 16))
4047 else if (ALTIVEC_VECTOR_MODE (mode)
4048 || (type && TREE_CODE (type) == VECTOR_TYPE
4049 && int_size_in_bytes (type) >= 16))
4051 else if (rs6000_darwin64_abi && mode == BLKmode
4052 && type && TYPE_ALIGN (type) > 64)
4055 return PARM_BOUNDARY;
4058 /* Compute the size (in words) of a function argument. */
4060 static unsigned long
4061 rs6000_arg_size (enum machine_mode mode, tree type)
4065 if (mode != BLKmode)
4066 size = GET_MODE_SIZE (mode);
4068 size = int_size_in_bytes (type);
4071 return (size + 3) >> 2;
4073 return (size + 7) >> 3;
4076 /* Use this to flush pending int fields. */
4079 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4080 HOST_WIDE_INT bitpos)
4082 unsigned int startbit, endbit;
4083 int intregs, intoffset;
4084 enum machine_mode mode;
4086 if (cum->intoffset == -1)
4089 intoffset = cum->intoffset;
4090 cum->intoffset = -1;
4092 if (intoffset % BITS_PER_WORD != 0)
4094 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4096 if (mode == BLKmode)
4098 /* We couldn't find an appropriate mode, which happens,
4099 e.g., in packed structs when there are 3 bytes to load.
4100 Back intoffset back to the beginning of the word in this
4102 intoffset = intoffset & -BITS_PER_WORD;
4106 startbit = intoffset & -BITS_PER_WORD;
4107 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4108 intregs = (endbit - startbit) / BITS_PER_WORD;
4109 cum->words += intregs;
4112 /* The darwin64 ABI calls for us to recurse down through structs,
4113 looking for elements passed in registers. Unfortunately, we have
4114 to track int register count here also because of misalignments
4115 in powerpc alignment mode. */
4118 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4120 HOST_WIDE_INT startbitpos)
4124 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4125 if (TREE_CODE (f) == FIELD_DECL)
4127 HOST_WIDE_INT bitpos = startbitpos;
4128 tree ftype = TREE_TYPE (f);
4129 enum machine_mode mode = TYPE_MODE (ftype);
4131 if (DECL_SIZE (f) != 0
4132 && host_integerp (bit_position (f), 1))
4133 bitpos += int_bit_position (f);
4135 /* ??? FIXME: else assume zero offset. */
4137 if (TREE_CODE (ftype) == RECORD_TYPE)
4138 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4139 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4141 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4142 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4143 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4145 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4147 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4151 else if (cum->intoffset == -1)
4152 cum->intoffset = bitpos;
4156 /* Update the data in CUM to advance over an argument
4157 of mode MODE and data type TYPE.
4158 (TYPE is null for libcalls where that information may not be available.)
4160 Note that for args passed by reference, function_arg will be called
4161 with MODE and TYPE set to that of the pointer to the arg, not the arg
4165 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4166 tree type, int named, int depth)
4170 /* Only tick off an argument if we're not recursing. */
4172 cum->nargs_prototype--;
4174 if (TARGET_ALTIVEC_ABI
4175 && (ALTIVEC_VECTOR_MODE (mode)
4176 || (type && TREE_CODE (type) == VECTOR_TYPE
4177 && int_size_in_bytes (type) == 16)))
4181 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4184 if (!TARGET_ALTIVEC)
4185 error ("Cannot pass argument in vector register because"
4186 " altivec instructions are disabled, use -maltivec"
4187 " to enable them.");
4189 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4190 even if it is going to be passed in a vector register.
4191 Darwin does the same for variable-argument functions. */
4192 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4193 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4203 /* Vector parameters must be 16-byte aligned. This places
4204 them at 2 mod 4 in terms of words in 32-bit mode, since
4205 the parameter save area starts at offset 24 from the
4206 stack. In 64-bit mode, they just have to start on an
4207 even word, since the parameter save area is 16-byte
4208 aligned. Space for GPRs is reserved even if the argument
4209 will be passed in memory. */
4211 align = (2 - cum->words) & 3;
4213 align = cum->words & 1;
4214 cum->words += align + rs6000_arg_size (mode, type);
4216 if (TARGET_DEBUG_ARG)
4218 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4220 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4221 cum->nargs_prototype, cum->prototype,
4222 GET_MODE_NAME (mode));
4226 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4228 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4231 else if (rs6000_darwin64_abi
4233 && TREE_CODE (type) == RECORD_TYPE
4234 && (size = int_size_in_bytes (type)) > 0)
4236 /* Variable sized types have size == -1 and are
4237 treated as if consisting entirely of ints.
4238 Pad to 16 byte boundary if needed. */
4239 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4240 && (cum->words % 2) != 0)
4242 /* For varargs, we can just go up by the size of the struct. */
4244 cum->words += (size + 7) / 8;
4247 /* It is tempting to say int register count just goes up by
4248 sizeof(type)/8, but this is wrong in a case such as
4249 { int; double; int; } [powerpc alignment]. We have to
4250 grovel through the fields for these too. */
4252 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4253 rs6000_darwin64_record_arg_advance_flush (cum,
4254 size * BITS_PER_UNIT);
4257 else if (DEFAULT_ABI == ABI_V4)
4259 if (TARGET_HARD_FLOAT && TARGET_FPRS
4260 && (mode == SFmode || mode == DFmode))
4262 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4267 cum->words += cum->words & 1;
4268 cum->words += rs6000_arg_size (mode, type);
4273 int n_words = rs6000_arg_size (mode, type);
4274 int gregno = cum->sysv_gregno;
4276 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4277 (r7,r8) or (r9,r10). As does any other 2 word item such
4278 as complex int due to a historical mistake. */
4280 gregno += (1 - gregno) & 1;
4282 /* Multi-reg args are not split between registers and stack. */
4283 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4285 /* Long long and SPE vectors are aligned on the stack.
4286 So are other 2 word items such as complex int due to
4287 a historical mistake. */
4289 cum->words += cum->words & 1;
4290 cum->words += n_words;
4293 /* Note: continuing to accumulate gregno past when we've started
4294 spilling to the stack indicates the fact that we've started
4295 spilling to the stack to expand_builtin_saveregs. */
4296 cum->sysv_gregno = gregno + n_words;
4299 if (TARGET_DEBUG_ARG)
4301 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4302 cum->words, cum->fregno);
4303 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4304 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4305 fprintf (stderr, "mode = %4s, named = %d\n",
4306 GET_MODE_NAME (mode), named);
4311 int n_words = rs6000_arg_size (mode, type);
4312 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4314 /* The simple alignment calculation here works because
4315 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4316 If we ever want to handle alignments larger than 8 bytes for
4317 32-bit or 16 bytes for 64-bit, then we'll need to take into
4318 account the offset to the start of the parm save area. */
4319 align &= cum->words;
4320 cum->words += align + n_words;
4322 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4323 && TARGET_HARD_FLOAT && TARGET_FPRS)
4324 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4326 if (TARGET_DEBUG_ARG)
4328 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4329 cum->words, cum->fregno);
4330 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4331 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4332 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4333 named, align, depth);
4339 spe_build_register_parallel (enum machine_mode mode, int gregno)
4345 r1 = gen_rtx_REG (DImode, gregno);
4346 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4347 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4349 else if (mode == DCmode)
4351 r1 = gen_rtx_REG (DImode, gregno);
4352 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4353 r3 = gen_rtx_REG (DImode, gregno + 2);
4354 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4355 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4361 /* Determine where to put a SIMD argument on the SPE. */
4363 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4366 int gregno = cum->sysv_gregno;
4368 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4369 are passed and returned in a pair of GPRs for ABI compatibility. */
4370 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4372 int n_words = rs6000_arg_size (mode, type);
4374 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4376 gregno += (1 - gregno) & 1;
4378 /* Multi-reg args are not split between registers and stack. */
4379 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4382 return spe_build_register_parallel (mode, gregno);
4386 int n_words = rs6000_arg_size (mode, type);
4388 /* SPE vectors are put in odd registers. */
4389 if (n_words == 2 && (gregno & 1) == 0)
4392 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4395 enum machine_mode m = SImode;
4397 r1 = gen_rtx_REG (m, gregno);
4398 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4399 r2 = gen_rtx_REG (m, gregno + 1);
4400 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4401 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4408 if (gregno <= GP_ARG_MAX_REG)
4409 return gen_rtx_REG (mode, gregno);
4415 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4416 structure between cum->intoffset and bitpos to integer registers. */
4419 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4420 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4422 enum machine_mode mode;
4424 unsigned int startbit, endbit;
4425 int this_regno, intregs, intoffset;
4428 if (cum->intoffset == -1)
4431 intoffset = cum->intoffset;
4432 cum->intoffset = -1;
4434 /* If this is the trailing part of a word, try to only load that
4435 much into the register. Otherwise load the whole register. Note
4436 that in the latter case we may pick up unwanted bits. It's not a
4437 problem at the moment but may wish to revisit. */
4439 if (intoffset % BITS_PER_WORD != 0)
4441 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4443 if (mode == BLKmode)
4445 /* We couldn't find an appropriate mode, which happens,
4446 e.g., in packed structs when there are 3 bytes to load.
4447 Back intoffset back to the beginning of the word in this
4449 intoffset = intoffset & -BITS_PER_WORD;
4456 startbit = intoffset & -BITS_PER_WORD;
4457 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4458 intregs = (endbit - startbit) / BITS_PER_WORD;
4459 this_regno = cum->words + intoffset / BITS_PER_WORD;
4461 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4464 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4468 intoffset /= BITS_PER_UNIT;
4471 regno = GP_ARG_MIN_REG + this_regno;
4472 reg = gen_rtx_REG (mode, regno);
4474 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4477 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4481 while (intregs > 0);
4484 /* Recursive workhorse for the following. */
4487 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4488 HOST_WIDE_INT startbitpos, rtx rvec[],
4493 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4494 if (TREE_CODE (f) == FIELD_DECL)
4496 HOST_WIDE_INT bitpos = startbitpos;
4497 tree ftype = TREE_TYPE (f);
4498 enum machine_mode mode = TYPE_MODE (ftype);
4500 if (DECL_SIZE (f) != 0
4501 && host_integerp (bit_position (f), 1))
4502 bitpos += int_bit_position (f);
4504 /* ??? FIXME: else assume zero offset. */
4506 if (TREE_CODE (ftype) == RECORD_TYPE)
4507 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4508 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4513 case SCmode: mode = SFmode; break;
4514 case DCmode: mode = DFmode; break;
4515 case TCmode: mode = TFmode; break;
4519 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4521 = gen_rtx_EXPR_LIST (VOIDmode,
4522 gen_rtx_REG (mode, cum->fregno++),
4523 GEN_INT (bitpos / BITS_PER_UNIT));
4527 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4529 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4531 = gen_rtx_EXPR_LIST (VOIDmode,
4532 gen_rtx_REG (mode, cum->vregno++),
4533 GEN_INT (bitpos / BITS_PER_UNIT));
4535 else if (cum->intoffset == -1)
4536 cum->intoffset = bitpos;
4540 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4541 the register(s) to be used for each field and subfield of a struct
4542 being passed by value, along with the offset of where the
4543 register's value may be found in the block. FP fields go in FP
4544 register, vector fields go in vector registers, and everything
4545 else goes in int registers, packed as in memory.
4547 This code is also used for function return values. RETVAL indicates
4548 whether this is the case.
4550 Much of this is taken from the Sparc V9 port, which has a similar
4551 calling convention. */
4554 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4555 int named, bool retval)
4557 rtx rvec[FIRST_PSEUDO_REGISTER];
4558 int k = 1, kbase = 1;
4559 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4560 /* This is a copy; modifications are not visible to our caller. */
4561 CUMULATIVE_ARGS copy_cum = *orig_cum;
4562 CUMULATIVE_ARGS *cum = ©_cum;
4564 /* Pad to 16 byte boundary if needed. */
4565 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4566 && (cum->words % 2) != 0)
4573 /* Put entries into rvec[] for individual FP and vector fields, and
4574 for the chunks of memory that go in int regs. Note we start at
4575 element 1; 0 is reserved for an indication of using memory, and
4576 may or may not be filled in below. */
4577 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4578 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4580 /* If any part of the struct went on the stack put all of it there.
4581 This hack is because the generic code for
4582 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4583 parts of the struct are not at the beginning. */
4587 return NULL_RTX; /* doesn't go in registers at all */
4589 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4591 if (k > 1 || cum->use_stack)
4592 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4597 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4600 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4604 rtx rvec[GP_ARG_NUM_REG + 1];
4606 if (align_words >= GP_ARG_NUM_REG)
4609 n_units = rs6000_arg_size (mode, type);
4611 /* Optimize the simple case where the arg fits in one gpr, except in
4612 the case of BLKmode due to assign_parms assuming that registers are
4613 BITS_PER_WORD wide. */
4615 || (n_units == 1 && mode != BLKmode))
4616 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4619 if (align_words + n_units > GP_ARG_NUM_REG)
4620 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4621 using a magic NULL_RTX component.
4622 FIXME: This is not strictly correct. Only some of the arg
4623 belongs in memory, not all of it. However, there isn't any way
4624 to do this currently, apart from building rtx descriptions for
4625 the pieces of memory we want stored. Due to bugs in the generic
4626 code we can't use the normal function_arg_partial_nregs scheme
4627 with the PARALLEL arg description we emit here.
4628 In any case, the code to store the whole arg to memory is often
4629 more efficient than code to store pieces, and we know that space
4630 is available in the right place for the whole arg. */
4631 /* FIXME: This should be fixed since the conversion to
4632 TARGET_ARG_PARTIAL_BYTES. */
4633 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4638 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4639 rtx off = GEN_INT (i++ * 4);
4640 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4642 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4644 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4647 /* Determine where to put an argument to a function.
4648 Value is zero to push the argument on the stack,
4649 or a hard register in which to store the argument.
4651 MODE is the argument's machine mode.
4652 TYPE is the data type of the argument (as a tree).
4653 This is null for libcalls where that information may
4655 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4656 the preceding args and about the function being called. It is
4657 not modified in this routine.
4658 NAMED is nonzero if this argument is a named parameter
4659 (otherwise it is an extra parameter matching an ellipsis).
4661 On RS/6000 the first eight words of non-FP are normally in registers
4662 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4663 Under V.4, the first 8 FP args are in registers.
4665 If this is floating-point and no prototype is specified, we use
4666 both an FP and integer register (or possibly FP reg and stack). Library
4667 functions (when CALL_LIBCALL is set) always have the proper types for args,
4668 so we can pass the FP value just in one register. emit_library_function
4669 doesn't support PARALLEL anyway.
4671 Note that for args passed by reference, function_arg will be called
4672 with MODE and TYPE set to that of the pointer to the arg, not the arg
4676 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4677 tree type, int named)
4679 enum rs6000_abi abi = DEFAULT_ABI;
4681 /* Return a marker to indicate whether CR1 needs to set or clear the
4682 bit that V.4 uses to say fp args were passed in registers.
4683 Assume that we don't need the marker for software floating point,
4684 or compiler generated library calls. */
4685 if (mode == VOIDmode)
4688 && cum->nargs_prototype < 0
4689 && (cum->call_cookie & CALL_LIBCALL) == 0
4690 && (cum->prototype || TARGET_NO_PROTOTYPE))
4692 /* For the SPE, we need to crxor CR6 always. */
4694 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4695 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4696 return GEN_INT (cum->call_cookie
4697 | ((cum->fregno == FP_ARG_MIN_REG)
4698 ? CALL_V4_SET_FP_ARGS
4699 : CALL_V4_CLEAR_FP_ARGS));
4702 return GEN_INT (cum->call_cookie);
4705 if (rs6000_darwin64_abi && mode == BLKmode
4706 && TREE_CODE (type) == RECORD_TYPE)
4708 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4709 if (rslt != NULL_RTX)
4711 /* Else fall through to usual handling. */
4714 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4715 if (TARGET_64BIT && ! cum->prototype)
4717 /* Vector parameters get passed in vector register
4718 and also in GPRs or memory, in absence of prototype. */
4721 align_words = (cum->words + 1) & ~1;
4723 if (align_words >= GP_ARG_NUM_REG)
4729 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4731 return gen_rtx_PARALLEL (mode,
4733 gen_rtx_EXPR_LIST (VOIDmode,
4735 gen_rtx_EXPR_LIST (VOIDmode,
4736 gen_rtx_REG (mode, cum->vregno),
4740 return gen_rtx_REG (mode, cum->vregno);
4741 else if (TARGET_ALTIVEC_ABI
4742 && (ALTIVEC_VECTOR_MODE (mode)
4743 || (type && TREE_CODE (type) == VECTOR_TYPE
4744 && int_size_in_bytes (type) == 16)))
4746 if (named || abi == ABI_V4)
4750 /* Vector parameters to varargs functions under AIX or Darwin
4751 get passed in memory and possibly also in GPRs. */
4752 int align, align_words, n_words;
4753 enum machine_mode part_mode;
4755 /* Vector parameters must be 16-byte aligned. This places them at
4756 2 mod 4 in terms of words in 32-bit mode, since the parameter
4757 save area starts at offset 24 from the stack. In 64-bit mode,
4758 they just have to start on an even word, since the parameter
4759 save area is 16-byte aligned. */
4761 align = (2 - cum->words) & 3;
4763 align = cum->words & 1;
4764 align_words = cum->words + align;
4766 /* Out of registers? Memory, then. */
4767 if (align_words >= GP_ARG_NUM_REG)
4770 if (TARGET_32BIT && TARGET_POWERPC64)
4771 return rs6000_mixed_function_arg (mode, type, align_words);
4773 /* The vector value goes in GPRs. Only the part of the
4774 value in GPRs is reported here. */
4776 n_words = rs6000_arg_size (mode, type);
4777 if (align_words + n_words > GP_ARG_NUM_REG)
4778 /* Fortunately, there are only two possibilities, the value
4779 is either wholly in GPRs or half in GPRs and half not. */
4782 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4785 else if (TARGET_SPE_ABI && TARGET_SPE
4786 && (SPE_VECTOR_MODE (mode)
4787 || (TARGET_E500_DOUBLE && (mode == DFmode
4788 || mode == DCmode))))
4789 return rs6000_spe_function_arg (cum, mode, type);
4791 else if (abi == ABI_V4)
4793 if (TARGET_HARD_FLOAT && TARGET_FPRS
4794 && (mode == SFmode || mode == DFmode))
4796 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4797 return gen_rtx_REG (mode, cum->fregno);
4803 int n_words = rs6000_arg_size (mode, type);
4804 int gregno = cum->sysv_gregno;
4806 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4807 (r7,r8) or (r9,r10). As does any other 2 word item such
4808 as complex int due to a historical mistake. */
4810 gregno += (1 - gregno) & 1;
4812 /* Multi-reg args are not split between registers and stack. */
4813 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4816 if (TARGET_32BIT && TARGET_POWERPC64)
4817 return rs6000_mixed_function_arg (mode, type,
4818 gregno - GP_ARG_MIN_REG);
4819 return gen_rtx_REG (mode, gregno);
4824 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4825 int align_words = cum->words + (cum->words & align);
4827 if (USE_FP_FOR_ARG_P (cum, mode, type))
4829 rtx rvec[GP_ARG_NUM_REG + 1];
4833 enum machine_mode fmode = mode;
4834 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4836 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4838 /* Currently, we only ever need one reg here because complex
4839 doubles are split. */
4840 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
4843 /* Long double split over regs and memory. */
4847 /* Do we also need to pass this arg in the parameter save
4850 && (cum->nargs_prototype <= 0
4851 || (DEFAULT_ABI == ABI_AIX
4853 && align_words >= GP_ARG_NUM_REG)));
4855 if (!needs_psave && mode == fmode)
4856 return gen_rtx_REG (fmode, cum->fregno);
4861 /* Describe the part that goes in gprs or the stack.
4862 This piece must come first, before the fprs. */
4863 if (align_words < GP_ARG_NUM_REG)
4865 unsigned long n_words = rs6000_arg_size (mode, type);
4867 if (align_words + n_words > GP_ARG_NUM_REG
4868 || (TARGET_32BIT && TARGET_POWERPC64))
4870 /* If this is partially on the stack, then we only
4871 include the portion actually in registers here. */
4872 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4875 if (align_words + n_words > GP_ARG_NUM_REG
4876 && (TARGET_32BIT && TARGET_POWERPC64))
4877 /* Not all of the arg fits in gprs. Say that it
4878 goes in memory too, using a magic NULL_RTX
4879 component. Also see comment in
4880 rs6000_mixed_function_arg for why the normal
4881 function_arg_partial_nregs scheme doesn't work
4883 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4887 r = gen_rtx_REG (rmode,
4888 GP_ARG_MIN_REG + align_words);
4889 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
4890 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4892 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4896 /* The whole arg fits in gprs. */
4897 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4898 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4902 /* It's entirely in memory. */
4903 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4906 /* Describe where this piece goes in the fprs. */
4907 r = gen_rtx_REG (fmode, cum->fregno);
4908 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4910 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4912 else if (align_words < GP_ARG_NUM_REG)
4914 if (TARGET_32BIT && TARGET_POWERPC64)
4915 return rs6000_mixed_function_arg (mode, type, align_words);
4917 if (mode == BLKmode)
4920 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4927 /* For an arg passed partly in registers and partly in memory, this is
4928 the number of registers used. For args passed entirely in registers
4929 or entirely in memory, zero. When an arg is described by a PARALLEL,
4930 perhaps using more than one register type, this function returns the
4931 number of bytes of registers used by the PARALLEL. */
4934 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4935 tree type, bool named)
4942 if (DEFAULT_ABI == ABI_V4)
4945 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4946 && cum->nargs_prototype >= 0)
4949 /* In this complicated case we just disable the partial_nregs code. */
4950 if (rs6000_darwin64_abi && mode == BLKmode
4951 && TREE_CODE (type) == RECORD_TYPE
4952 && int_size_in_bytes (type) > 0)
4955 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4956 parm_offset = TARGET_32BIT ? 2 : 0;
4957 align_words = cum->words + ((parm_offset - cum->words) & align);
4959 if (USE_FP_FOR_ARG_P (cum, mode, type)
4960 /* If we are passing this arg in gprs as well, then this function
4961 should return the number of gprs (or memory) partially passed,
4962 *not* the number of fprs. */
4964 && (cum->nargs_prototype <= 0
4965 || (DEFAULT_ABI == ABI_AIX
4967 && align_words >= GP_ARG_NUM_REG))))
4969 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4970 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
4971 else if (cum->nargs_prototype >= 0)
4975 if (align_words < GP_ARG_NUM_REG
4976 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
4977 ret = GP_ARG_NUM_REG - align_words;
4979 ret *= (TARGET_32BIT ? 4 : 8);
4981 if (ret != 0 && TARGET_DEBUG_ARG)
4982 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4987 /* A C expression that indicates when an argument must be passed by
4988 reference. If nonzero for an argument, a copy of that argument is
4989 made in memory and a pointer to the argument is passed instead of
4990 the argument itself. The pointer is passed in whatever way is
4991 appropriate for passing a pointer to that type.
4993 Under V.4, aggregates and long double are passed by reference.
4995 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
4996 reference unless the AltiVec vector extension ABI is in force.
4998 As an extension to all ABIs, variable sized types are passed by
5002 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5003 enum machine_mode mode, tree type,
5004 bool named ATTRIBUTE_UNUSED)
5006 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5008 if (TARGET_DEBUG_ARG)
5009 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5016 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5018 if (TARGET_DEBUG_ARG)
5019 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5023 if (int_size_in_bytes (type) < 0)
5025 if (TARGET_DEBUG_ARG)
5026 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5030 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5031 modes only exist for GCC vector types if -maltivec. */
5032 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5034 if (TARGET_DEBUG_ARG)
5035 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5039 /* Pass synthetic vectors in memory. */
5040 if (TREE_CODE (type) == VECTOR_TYPE
5041 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5043 static bool warned_for_pass_big_vectors = false;
5044 if (TARGET_DEBUG_ARG)
5045 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5046 if (!warned_for_pass_big_vectors)
5048 warning ("GCC vector passed by reference: "
5049 "non-standard ABI extension with no compatibility guarantee");
5050 warned_for_pass_big_vectors = true;
5059 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5062 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5067 for (i = 0; i < nregs; i++)
5069 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5070 if (reload_completed)
5072 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5075 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5076 i * GET_MODE_SIZE(reg_mode));
5079 tem = replace_equiv_address (tem, XEXP (tem, 0));
5081 if (tem == NULL_RTX)
5084 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5088 /* Perform any needed actions needed for a function that is receiving a
5089 variable number of arguments.
5093 MODE and TYPE are the mode and type of the current parameter.
5095 PRETEND_SIZE is a variable that should be set to the amount of stack
5096 that must be pushed by the prolog to pretend that our caller pushed
5099 Normally, this macro will push all remaining incoming registers on the
5100 stack and set PRETEND_SIZE to the length of the registers pushed. */
5103 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5104 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5107 CUMULATIVE_ARGS next_cum;
5108 int reg_size = TARGET_32BIT ? 4 : 8;
5109 rtx save_area = NULL_RTX, mem;
5110 int first_reg_offset, set;
5112 /* Skip the last named argument. */
5114 function_arg_advance (&next_cum, mode, type, 1, 0);
5116 if (DEFAULT_ABI == ABI_V4)
5119 save_area = plus_constant (virtual_stack_vars_rtx,
5120 - RS6000_VARARGS_SIZE);
5122 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5126 first_reg_offset = next_cum.words;
5127 save_area = virtual_incoming_args_rtx;
5129 if (targetm.calls.must_pass_in_stack (mode, type))
5130 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5133 set = get_varargs_alias_set ();
5134 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5136 mem = gen_rtx_MEM (BLKmode,
5137 plus_constant (save_area,
5138 first_reg_offset * reg_size)),
5139 set_mem_alias_set (mem, set);
5140 set_mem_align (mem, BITS_PER_WORD);
5142 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5143 GP_ARG_NUM_REG - first_reg_offset);
5146 /* Save FP registers if needed. */
5147 if (DEFAULT_ABI == ABI_V4
5148 && TARGET_HARD_FLOAT && TARGET_FPRS
5150 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5152 int fregno = next_cum.fregno;
5153 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5154 rtx lab = gen_label_rtx ();
5155 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5158 (gen_rtx_SET (VOIDmode,
5160 gen_rtx_IF_THEN_ELSE (VOIDmode,
5161 gen_rtx_NE (VOIDmode, cr1,
5163 gen_rtx_LABEL_REF (VOIDmode, lab),
5166 while (fregno <= FP_ARG_V4_MAX_REG)
5168 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5169 set_mem_alias_set (mem, set);
5170 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5171 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5180 /* Create the va_list data type. */
5183 rs6000_build_builtin_va_list (void)
5185 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5187 /* For AIX, prefer 'char *' because that's what the system
5188 header files like. */
5189 if (DEFAULT_ABI != ABI_V4)
5190 return build_pointer_type (char_type_node);
5192 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5193 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5195 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5196 unsigned_char_type_node);
5197 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5198 unsigned_char_type_node);
5199 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5201 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5202 short_unsigned_type_node);
5203 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5205 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5208 DECL_FIELD_CONTEXT (f_gpr) = record;
5209 DECL_FIELD_CONTEXT (f_fpr) = record;
5210 DECL_FIELD_CONTEXT (f_res) = record;
5211 DECL_FIELD_CONTEXT (f_ovf) = record;
5212 DECL_FIELD_CONTEXT (f_sav) = record;
5214 TREE_CHAIN (record) = type_decl;
5215 TYPE_NAME (record) = type_decl;
5216 TYPE_FIELDS (record) = f_gpr;
5217 TREE_CHAIN (f_gpr) = f_fpr;
5218 TREE_CHAIN (f_fpr) = f_res;
5219 TREE_CHAIN (f_res) = f_ovf;
5220 TREE_CHAIN (f_ovf) = f_sav;
5222 layout_type (record);
5224 /* The correct type is an array type of one element. */
5225 return build_array_type (record, build_index_type (size_zero_node));
5228 /* Implement va_start. */
5231 rs6000_va_start (tree valist, rtx nextarg)
5233 HOST_WIDE_INT words, n_gpr, n_fpr;
5234 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5235 tree gpr, fpr, ovf, sav, t;
5237 /* Only SVR4 needs something special. */
5238 if (DEFAULT_ABI != ABI_V4)
5240 std_expand_builtin_va_start (valist, nextarg);
5244 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5245 f_fpr = TREE_CHAIN (f_gpr);
5246 f_res = TREE_CHAIN (f_fpr);
5247 f_ovf = TREE_CHAIN (f_res);
5248 f_sav = TREE_CHAIN (f_ovf);
5250 valist = build_va_arg_indirect_ref (valist);
5251 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5252 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5253 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5254 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5256 /* Count number of gp and fp argument registers used. */
5257 words = current_function_args_info.words;
5258 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5260 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5263 if (TARGET_DEBUG_ARG)
5264 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5265 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5266 words, n_gpr, n_fpr);
5268 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5269 build_int_cst (NULL_TREE, n_gpr));
5270 TREE_SIDE_EFFECTS (t) = 1;
5271 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5273 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5274 build_int_cst (NULL_TREE, n_fpr));
5275 TREE_SIDE_EFFECTS (t) = 1;
5276 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5278 /* Find the overflow area. */
5279 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5281 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5282 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5283 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5284 TREE_SIDE_EFFECTS (t) = 1;
5285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5287 /* Find the register save area. */
5288 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5289 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5290 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5291 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5292 TREE_SIDE_EFFECTS (t) = 1;
5293 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5296 /* Implement va_arg. */
5299 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5301 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5302 tree gpr, fpr, ovf, sav, reg, t, u;
5303 int size, rsize, n_reg, sav_ofs, sav_scale;
5304 tree lab_false, lab_over, addr;
5306 tree ptrtype = build_pointer_type (type);
5308 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5310 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5311 return build_va_arg_indirect_ref (t);
5314 if (DEFAULT_ABI != ABI_V4)
5316 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5318 tree elem_type = TREE_TYPE (type);
5319 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5320 int elem_size = GET_MODE_SIZE (elem_mode);
5322 if (elem_size < UNITS_PER_WORD)
5324 tree real_part, imag_part;
5325 tree post = NULL_TREE;
5327 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5329 /* Copy the value into a temporary, lest the formal temporary
5330 be reused out from under us. */
5331 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5332 append_to_statement_list (post, pre_p);
5334 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5337 return build (COMPLEX_EXPR, type, real_part, imag_part);
5341 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5344 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5345 f_fpr = TREE_CHAIN (f_gpr);
5346 f_res = TREE_CHAIN (f_fpr);
5347 f_ovf = TREE_CHAIN (f_res);
5348 f_sav = TREE_CHAIN (f_ovf);
5350 valist = build_va_arg_indirect_ref (valist);
5351 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5352 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5353 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5354 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5356 size = int_size_in_bytes (type);
5357 rsize = (size + 3) / 4;
5360 if (TARGET_HARD_FLOAT && TARGET_FPRS
5361 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5363 /* FP args go in FP registers, if present. */
5368 if (TYPE_MODE (type) == DFmode)
5373 /* Otherwise into GP registers. */
5382 /* Pull the value out of the saved registers.... */
5385 addr = create_tmp_var (ptr_type_node, "addr");
5386 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5388 /* AltiVec vectors never go in registers when -mabi=altivec. */
5389 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5393 lab_false = create_artificial_label ();
5394 lab_over = create_artificial_label ();
5396 /* Long long and SPE vectors are aligned in the registers.
5397 As are any other 2 gpr item such as complex int due to a
5398 historical mistake. */
5402 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5403 size_int (n_reg - 1));
5404 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5407 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5408 t = build2 (GE_EXPR, boolean_type_node, u, t);
5409 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5410 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5411 gimplify_and_add (t, pre_p);
5415 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5417 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5418 u = build1 (CONVERT_EXPR, integer_type_node, u);
5419 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5420 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5422 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5423 gimplify_and_add (t, pre_p);
5425 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5426 gimplify_and_add (t, pre_p);
5428 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5429 append_to_statement_list (t, pre_p);
5433 /* Ensure that we don't find any more args in regs.
5434 Alignment has taken care of the n_reg == 2 case. */
5435 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5436 gimplify_and_add (t, pre_p);
5440 /* ... otherwise out of the overflow area. */
5442 /* Care for on-stack alignment if needed. */
5446 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5447 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5448 build_int_cst (NULL_TREE, -align));
5450 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5452 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5453 gimplify_and_add (u, pre_p);
5455 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5456 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5457 gimplify_and_add (t, pre_p);
5461 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5462 append_to_statement_list (t, pre_p);
5465 addr = fold_convert (ptrtype, addr);
5466 return build_va_arg_indirect_ref (addr);
5471 #define def_builtin(MASK, NAME, TYPE, CODE) \
5473 if ((MASK) & target_flags) \
5474 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5478 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5480 static const struct builtin_description bdesc_3arg[] =
5482 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5483 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5484 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5485 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5486 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5487 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5488 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5489 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5490 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5491 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5492 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5493 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5494 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5495 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5496 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5497 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5498 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5499 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5500 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5501 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5502 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5503 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5504 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5507 /* DST operations: void foo (void *, const int, const char). */
5509 static const struct builtin_description bdesc_dst[] =
5511 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5512 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5514 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5517 /* Simple binary operations: VECc = foo (VECa, VECb). */
5519 static struct builtin_description bdesc_2arg[] =
5521 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5522 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5523 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5524 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5525 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5526 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5527 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5528 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5529 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5530 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5532 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5533 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5534 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5535 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5536 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5537 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5538 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5539 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5540 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5541 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5542 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5543 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5544 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5545 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5546 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5547 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5548 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5549 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5550 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5551 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5552 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5553 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5554 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5557 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5558 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5559 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5560 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5561 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5562 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5563 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5570 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5571 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5572 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5573 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5574 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5575 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5576 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5578 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5579 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5580 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5581 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5582 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5584 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5585 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5586 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5587 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5588 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5589 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5590 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5591 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5592 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5593 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5594 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5595 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5596 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5597 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5598 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5599 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5600 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5601 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5602 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5603 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5604 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5606 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5614 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5615 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5617 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5618 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5619 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5620 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5633 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5635 /* Place holder, leave as first spe builtin. */
5636 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5637 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5638 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5639 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5640 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5641 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5642 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5643 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5644 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5645 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5646 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5647 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5648 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5649 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5650 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5651 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5652 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5653 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5654 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5655 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5656 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5657 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5658 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5659 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5660 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5661 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5662 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5663 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5664 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5665 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5666 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5667 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5668 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5669 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5670 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5671 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5672 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5673 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5674 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5675 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5676 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5677 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5678 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5679 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5680 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5681 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5682 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5683 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5684 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5685 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5686 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5687 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5688 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5689 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5690 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5691 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5692 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5693 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5694 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5695 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5696 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5697 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5698 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5699 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5700 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5701 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5702 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5703 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5704 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5705 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5706 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5707 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5708 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5709 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5710 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5711 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5712 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5713 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5714 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5715 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5716 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5717 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5718 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5719 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5720 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5721 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5722 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5723 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5724 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5725 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5726 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5727 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5728 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5729 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5730 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5731 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5732 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5733 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5734 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5735 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5736 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5737 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5738 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5739 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5740 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5741 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5742 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5743 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5744 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5746 /* SPE binary operations expecting a 5-bit unsigned literal. */
5747 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5749 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5750 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5751 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5752 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5753 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5754 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5755 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5756 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5757 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5758 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5759 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5760 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5761 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5762 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5763 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5764 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5765 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5766 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5767 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5768 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5769 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5770 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5771 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5772 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5773 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5774 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5776 /* Place-holder. Leave as last binary SPE builtin. */
5777 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5780 /* AltiVec predicates. */
5782 struct builtin_description_predicates
5784 const unsigned int mask;
5785 const enum insn_code icode;
5787 const char *const name;
5788 const enum rs6000_builtins code;
5791 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5793 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5794 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5795 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5796 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5797 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5798 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5799 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5800 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5801 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5802 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5803 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5804 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5805 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5808 /* SPE predicates. */
5809 static struct builtin_description bdesc_spe_predicates[] =
5811 /* Place-holder. Leave as first. */
5812 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5813 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5814 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5815 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5816 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5817 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5818 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5819 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5820 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5821 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5822 /* Place-holder. Leave as last. */
5823 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5826 /* SPE evsel predicates. */
5827 static struct builtin_description bdesc_spe_evsel[] =
5829 /* Place-holder. Leave as first. */
5830 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5831 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5832 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5833 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5834 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5835 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5836 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5837 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5838 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5839 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5840 /* Place-holder. Leave as last. */
5841 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5844 /* ABS* operations. */
5846 static const struct builtin_description bdesc_abs[] =
5848 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5849 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5850 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5851 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5852 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5853 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5854 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5857 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5860 static struct builtin_description bdesc_1arg[] =
5862 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5863 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5864 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5865 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5866 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5867 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5868 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5869 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5870 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5871 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5872 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5873 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5874 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5875 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5876 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5877 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5878 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5880 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5881 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5882 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5883 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5884 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5885 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5886 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5887 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5888 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5889 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5890 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5891 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5892 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5893 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5894 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5895 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5896 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5897 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5898 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5899 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5900 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5901 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5902 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5903 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5904 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5905 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5906 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5907 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5908 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5909 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5911 /* Place-holder. Leave as last unary SPE builtin. */
5912 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5916 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5919 tree arg0 = TREE_VALUE (arglist);
5920 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5921 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5922 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5924 if (icode == CODE_FOR_nothing)
5925 /* Builtin not supported on this processor. */
5928 /* If we got invalid arguments bail out before generating bad rtl. */
5929 if (arg0 == error_mark_node)
5932 if (icode == CODE_FOR_altivec_vspltisb
5933 || icode == CODE_FOR_altivec_vspltish
5934 || icode == CODE_FOR_altivec_vspltisw
5935 || icode == CODE_FOR_spe_evsplatfi
5936 || icode == CODE_FOR_spe_evsplati)
5938 /* Only allow 5-bit *signed* literals. */
5939 if (GET_CODE (op0) != CONST_INT
5940 || INTVAL (op0) > 0x1f
5941 || INTVAL (op0) < -0x1f)
5943 error ("argument 1 must be a 5-bit signed literal");
5949 || GET_MODE (target) != tmode
5950 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5951 target = gen_reg_rtx (tmode);
5953 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5954 op0 = copy_to_mode_reg (mode0, op0);
5956 pat = GEN_FCN (icode) (target, op0);
5965 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5967 rtx pat, scratch1, scratch2;
5968 tree arg0 = TREE_VALUE (arglist);
5969 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5970 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5971 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5973 /* If we have invalid arguments, bail out before generating bad rtl. */
5974 if (arg0 == error_mark_node)
5978 || GET_MODE (target) != tmode
5979 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5980 target = gen_reg_rtx (tmode);
5982 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5983 op0 = copy_to_mode_reg (mode0, op0);
5985 scratch1 = gen_reg_rtx (mode0);
5986 scratch2 = gen_reg_rtx (mode0);
5988 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5997 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6000 tree arg0 = TREE_VALUE (arglist);
6001 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6002 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6003 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6004 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6005 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6006 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6008 if (icode == CODE_FOR_nothing)
6009 /* Builtin not supported on this processor. */
6012 /* If we got invalid arguments bail out before generating bad rtl. */
6013 if (arg0 == error_mark_node || arg1 == error_mark_node)
6016 if (icode == CODE_FOR_altivec_vcfux
6017 || icode == CODE_FOR_altivec_vcfsx
6018 || icode == CODE_FOR_altivec_vctsxs
6019 || icode == CODE_FOR_altivec_vctuxs
6020 || icode == CODE_FOR_altivec_vspltb
6021 || icode == CODE_FOR_altivec_vsplth
6022 || icode == CODE_FOR_altivec_vspltw
6023 || icode == CODE_FOR_spe_evaddiw
6024 || icode == CODE_FOR_spe_evldd
6025 || icode == CODE_FOR_spe_evldh
6026 || icode == CODE_FOR_spe_evldw
6027 || icode == CODE_FOR_spe_evlhhesplat
6028 || icode == CODE_FOR_spe_evlhhossplat
6029 || icode == CODE_FOR_spe_evlhhousplat
6030 || icode == CODE_FOR_spe_evlwhe
6031 || icode == CODE_FOR_spe_evlwhos
6032 || icode == CODE_FOR_spe_evlwhou
6033 || icode == CODE_FOR_spe_evlwhsplat
6034 || icode == CODE_FOR_spe_evlwwsplat
6035 || icode == CODE_FOR_spe_evrlwi
6036 || icode == CODE_FOR_spe_evslwi
6037 || icode == CODE_FOR_spe_evsrwis
6038 || icode == CODE_FOR_spe_evsubifw
6039 || icode == CODE_FOR_spe_evsrwiu)
6041 /* Only allow 5-bit unsigned literals. */
6043 if (TREE_CODE (arg1) != INTEGER_CST
6044 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6046 error ("argument 2 must be a 5-bit unsigned literal");
6052 || GET_MODE (target) != tmode
6053 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6054 target = gen_reg_rtx (tmode);
6056 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6057 op0 = copy_to_mode_reg (mode0, op0);
6058 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6059 op1 = copy_to_mode_reg (mode1, op1);
6061 pat = GEN_FCN (icode) (target, op0, op1);
6070 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6071 tree arglist, rtx target)
6074 tree cr6_form = TREE_VALUE (arglist);
6075 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6076 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6077 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6078 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6079 enum machine_mode tmode = SImode;
6080 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6081 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6084 if (TREE_CODE (cr6_form) != INTEGER_CST)
6086 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6090 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6095 /* If we have invalid arguments, bail out before generating bad rtl. */
6096 if (arg0 == error_mark_node || arg1 == error_mark_node)
6100 || GET_MODE (target) != tmode
6101 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6102 target = gen_reg_rtx (tmode);
6104 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6105 op0 = copy_to_mode_reg (mode0, op0);
6106 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6107 op1 = copy_to_mode_reg (mode1, op1);
6109 scratch = gen_reg_rtx (mode0);
6111 pat = GEN_FCN (icode) (scratch, op0, op1,
6112 gen_rtx_SYMBOL_REF (Pmode, opcode));
6117 /* The vec_any* and vec_all* predicates use the same opcodes for two
6118 different operations, but the bits in CR6 will be different
6119 depending on what information we want. So we have to play tricks
6120 with CR6 to get the right bits out.
6122 If you think this is disgusting, look at the specs for the
6123 AltiVec predicates. */
6125 switch (cr6_form_int)
6128 emit_insn (gen_cr6_test_for_zero (target));
6131 emit_insn (gen_cr6_test_for_zero_reverse (target));
6134 emit_insn (gen_cr6_test_for_lt (target));
6137 emit_insn (gen_cr6_test_for_lt_reverse (target));
6140 error ("argument 1 of __builtin_altivec_predicate is out of range");
6148 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6151 tree arg0 = TREE_VALUE (arglist);
6152 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6153 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6154 enum machine_mode mode0 = Pmode;
6155 enum machine_mode mode1 = Pmode;
6156 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6157 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6159 if (icode == CODE_FOR_nothing)
6160 /* Builtin not supported on this processor. */
6163 /* If we got invalid arguments bail out before generating bad rtl. */
6164 if (arg0 == error_mark_node || arg1 == error_mark_node)
6168 || GET_MODE (target) != tmode
6169 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6170 target = gen_reg_rtx (tmode);
6172 op1 = copy_to_mode_reg (mode1, op1);
6174 if (op0 == const0_rtx)
6176 addr = gen_rtx_MEM (tmode, op1);
6180 op0 = copy_to_mode_reg (mode0, op0);
6181 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6184 pat = GEN_FCN (icode) (target, addr);
6194 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6196 tree arg0 = TREE_VALUE (arglist);
6197 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6198 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6199 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6200 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6201 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6203 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6204 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6205 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6207 /* Invalid arguments. Bail before doing anything stoopid! */
6208 if (arg0 == error_mark_node
6209 || arg1 == error_mark_node
6210 || arg2 == error_mark_node)
6213 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6214 op0 = copy_to_mode_reg (mode2, op0);
6215 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6216 op1 = copy_to_mode_reg (mode0, op1);
6217 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6218 op2 = copy_to_mode_reg (mode1, op2);
6220 pat = GEN_FCN (icode) (op1, op2, op0);
6227 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6229 tree arg0 = TREE_VALUE (arglist);
6230 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6231 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6232 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6233 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6234 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6236 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6237 enum machine_mode mode1 = Pmode;
6238 enum machine_mode mode2 = Pmode;
6240 /* Invalid arguments. Bail before doing anything stoopid! */
6241 if (arg0 == error_mark_node
6242 || arg1 == error_mark_node
6243 || arg2 == error_mark_node)
6246 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6247 op0 = copy_to_mode_reg (tmode, op0);
6249 op2 = copy_to_mode_reg (mode2, op2);
6251 if (op1 == const0_rtx)
6253 addr = gen_rtx_MEM (tmode, op2);
6257 op1 = copy_to_mode_reg (mode1, op1);
6258 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6261 pat = GEN_FCN (icode) (addr, op0);
6268 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6271 tree arg0 = TREE_VALUE (arglist);
6272 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6273 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6274 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6275 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6276 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6277 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6278 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6279 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6280 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6282 if (icode == CODE_FOR_nothing)
6283 /* Builtin not supported on this processor. */
6286 /* If we got invalid arguments bail out before generating bad rtl. */
6287 if (arg0 == error_mark_node
6288 || arg1 == error_mark_node
6289 || arg2 == error_mark_node)
6292 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6293 || icode == CODE_FOR_altivec_vsldoi_v4si
6294 || icode == CODE_FOR_altivec_vsldoi_v8hi
6295 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6297 /* Only allow 4-bit unsigned literals. */
6299 if (TREE_CODE (arg2) != INTEGER_CST
6300 || TREE_INT_CST_LOW (arg2) & ~0xf)
6302 error ("argument 3 must be a 4-bit unsigned literal");
6308 || GET_MODE (target) != tmode
6309 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6310 target = gen_reg_rtx (tmode);
6312 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6313 op0 = copy_to_mode_reg (mode0, op0);
6314 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6315 op1 = copy_to_mode_reg (mode1, op1);
6316 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6317 op2 = copy_to_mode_reg (mode2, op2);
6319 pat = GEN_FCN (icode) (target, op0, op1, op2);
6327 /* Expand the lvx builtins. */
6329 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6331 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6332 tree arglist = TREE_OPERAND (exp, 1);
6333 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6335 enum machine_mode tmode, mode0;
6337 enum insn_code icode;
6341 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6342 icode = CODE_FOR_altivec_lvx_v16qi;
6344 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6345 icode = CODE_FOR_altivec_lvx_v8hi;
6347 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6348 icode = CODE_FOR_altivec_lvx_v4si;
6350 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6351 icode = CODE_FOR_altivec_lvx_v4sf;
6360 arg0 = TREE_VALUE (arglist);
6361 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6362 tmode = insn_data[icode].operand[0].mode;
6363 mode0 = insn_data[icode].operand[1].mode;
6366 || GET_MODE (target) != tmode
6367 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6368 target = gen_reg_rtx (tmode);
6370 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6371 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6373 pat = GEN_FCN (icode) (target, op0);
6380 /* Expand the stvx builtins. */
6382 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6385 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6386 tree arglist = TREE_OPERAND (exp, 1);
6387 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6389 enum machine_mode mode0, mode1;
6391 enum insn_code icode;
6395 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6396 icode = CODE_FOR_altivec_stvx_v16qi;
6398 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6399 icode = CODE_FOR_altivec_stvx_v8hi;
6401 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6402 icode = CODE_FOR_altivec_stvx_v4si;
6404 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6405 icode = CODE_FOR_altivec_stvx_v4sf;
6412 arg0 = TREE_VALUE (arglist);
6413 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6414 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6415 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6416 mode0 = insn_data[icode].operand[0].mode;
6417 mode1 = insn_data[icode].operand[1].mode;
6419 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6420 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6421 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6422 op1 = copy_to_mode_reg (mode1, op1);
6424 pat = GEN_FCN (icode) (op0, op1);
6432 /* Expand the dst builtins. */
6434 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6437 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6438 tree arglist = TREE_OPERAND (exp, 1);
6439 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6440 tree arg0, arg1, arg2;
6441 enum machine_mode mode0, mode1, mode2;
6442 rtx pat, op0, op1, op2;
6443 struct builtin_description *d;
6448 /* Handle DST variants. */
6449 d = (struct builtin_description *) bdesc_dst;
6450 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6451 if (d->code == fcode)
6453 arg0 = TREE_VALUE (arglist);
6454 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6455 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6456 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6457 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6458 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6459 mode0 = insn_data[d->icode].operand[0].mode;
6460 mode1 = insn_data[d->icode].operand[1].mode;
6461 mode2 = insn_data[d->icode].operand[2].mode;
6463 /* Invalid arguments, bail out before generating bad rtl. */
6464 if (arg0 == error_mark_node
6465 || arg1 == error_mark_node
6466 || arg2 == error_mark_node)
6471 if (TREE_CODE (arg2) != INTEGER_CST
6472 || TREE_INT_CST_LOW (arg2) & ~0x3)
6474 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6478 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6479 op0 = copy_to_mode_reg (Pmode, op0);
6480 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6481 op1 = copy_to_mode_reg (mode1, op1);
6483 pat = GEN_FCN (d->icode) (op0, op1, op2);
6493 /* Expand the builtin in EXP and store the result in TARGET. Store
6494 true in *EXPANDEDP if we found a builtin to expand. */
6496 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6498 struct builtin_description *d;
6499 struct builtin_description_predicates *dp;
6501 enum insn_code icode;
6502 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6503 tree arglist = TREE_OPERAND (exp, 1);
6506 enum machine_mode tmode, mode0;
6507 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6509 target = altivec_expand_ld_builtin (exp, target, expandedp);
6513 target = altivec_expand_st_builtin (exp, target, expandedp);
6517 target = altivec_expand_dst_builtin (exp, target, expandedp);
6525 case ALTIVEC_BUILTIN_STVX:
6526 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6527 case ALTIVEC_BUILTIN_STVEBX:
6528 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6529 case ALTIVEC_BUILTIN_STVEHX:
6530 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6531 case ALTIVEC_BUILTIN_STVEWX:
6532 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6533 case ALTIVEC_BUILTIN_STVXL:
6534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6536 case ALTIVEC_BUILTIN_MFVSCR:
6537 icode = CODE_FOR_altivec_mfvscr;
6538 tmode = insn_data[icode].operand[0].mode;
6541 || GET_MODE (target) != tmode
6542 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6543 target = gen_reg_rtx (tmode);
6545 pat = GEN_FCN (icode) (target);
6551 case ALTIVEC_BUILTIN_MTVSCR:
6552 icode = CODE_FOR_altivec_mtvscr;
6553 arg0 = TREE_VALUE (arglist);
6554 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6555 mode0 = insn_data[icode].operand[0].mode;
6557 /* If we got invalid arguments bail out before generating bad rtl. */
6558 if (arg0 == error_mark_node)
6561 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6562 op0 = copy_to_mode_reg (mode0, op0);
6564 pat = GEN_FCN (icode) (op0);
6569 case ALTIVEC_BUILTIN_DSSALL:
6570 emit_insn (gen_altivec_dssall ());
6573 case ALTIVEC_BUILTIN_DSS:
6574 icode = CODE_FOR_altivec_dss;
6575 arg0 = TREE_VALUE (arglist);
6577 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6578 mode0 = insn_data[icode].operand[0].mode;
6580 /* If we got invalid arguments bail out before generating bad rtl. */
6581 if (arg0 == error_mark_node)
6584 if (TREE_CODE (arg0) != INTEGER_CST
6585 || TREE_INT_CST_LOW (arg0) & ~0x3)
6587 error ("argument to dss must be a 2-bit unsigned literal");
6591 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6592 op0 = copy_to_mode_reg (mode0, op0);
6594 emit_insn (gen_altivec_dss (op0));
6597 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6598 arg0 = TREE_VALUE (arglist);
6599 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6600 || TREE_CODE (arg0) == ARRAY_REF)
6601 arg0 = TREE_OPERAND (arg0, 0);
6602 error ("invalid parameter combination for %qs AltiVec intrinsic",
6603 TREE_STRING_POINTER (arg0));
6608 /* Expand abs* operations. */
6609 d = (struct builtin_description *) bdesc_abs;
6610 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6611 if (d->code == fcode)
6612 return altivec_expand_abs_builtin (d->icode, arglist, target);
6614 /* Expand the AltiVec predicates. */
6615 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6616 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6617 if (dp->code == fcode)
6618 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6621 /* LV* are funky. We initialized them differently. */
6624 case ALTIVEC_BUILTIN_LVSL:
6625 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6627 case ALTIVEC_BUILTIN_LVSR:
6628 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6630 case ALTIVEC_BUILTIN_LVEBX:
6631 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6633 case ALTIVEC_BUILTIN_LVEHX:
6634 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6636 case ALTIVEC_BUILTIN_LVEWX:
6637 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6639 case ALTIVEC_BUILTIN_LVXL:
6640 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6642 case ALTIVEC_BUILTIN_LVX:
6643 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6654 /* Binops that need to be initialized manually, but can be expanded
6655 automagically by rs6000_expand_binop_builtin. */
6656 static struct builtin_description bdesc_2arg_spe[] =
6658 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6659 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6660 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6661 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6662 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6663 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6664 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6665 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6666 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6667 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6668 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6669 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6670 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6671 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6672 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6673 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6674 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6675 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6676 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6677 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6678 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6679 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6682 /* Expand the builtin in EXP and store the result in TARGET. Store
6683 true in *EXPANDEDP if we found a builtin to expand.
6685 This expands the SPE builtins that are not simple unary and binary
6688 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6690 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6691 tree arglist = TREE_OPERAND (exp, 1);
6693 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6694 enum insn_code icode;
6695 enum machine_mode tmode, mode0;
6697 struct builtin_description *d;
6702 /* Syntax check for a 5-bit unsigned immediate. */
6705 case SPE_BUILTIN_EVSTDD:
6706 case SPE_BUILTIN_EVSTDH:
6707 case SPE_BUILTIN_EVSTDW:
6708 case SPE_BUILTIN_EVSTWHE:
6709 case SPE_BUILTIN_EVSTWHO:
6710 case SPE_BUILTIN_EVSTWWE:
6711 case SPE_BUILTIN_EVSTWWO:
6712 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6713 if (TREE_CODE (arg1) != INTEGER_CST
6714 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6716 error ("argument 2 must be a 5-bit unsigned literal");
6724 /* The evsplat*i instructions are not quite generic. */
6727 case SPE_BUILTIN_EVSPLATFI:
6728 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6730 case SPE_BUILTIN_EVSPLATI:
6731 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6737 d = (struct builtin_description *) bdesc_2arg_spe;
6738 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6739 if (d->code == fcode)
6740 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6742 d = (struct builtin_description *) bdesc_spe_predicates;
6743 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6744 if (d->code == fcode)
6745 return spe_expand_predicate_builtin (d->icode, arglist, target);
6747 d = (struct builtin_description *) bdesc_spe_evsel;
6748 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6749 if (d->code == fcode)
6750 return spe_expand_evsel_builtin (d->icode, arglist, target);
6754 case SPE_BUILTIN_EVSTDDX:
6755 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6756 case SPE_BUILTIN_EVSTDHX:
6757 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6758 case SPE_BUILTIN_EVSTDWX:
6759 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6760 case SPE_BUILTIN_EVSTWHEX:
6761 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6762 case SPE_BUILTIN_EVSTWHOX:
6763 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6764 case SPE_BUILTIN_EVSTWWEX:
6765 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6766 case SPE_BUILTIN_EVSTWWOX:
6767 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6768 case SPE_BUILTIN_EVSTDD:
6769 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6770 case SPE_BUILTIN_EVSTDH:
6771 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6772 case SPE_BUILTIN_EVSTDW:
6773 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6774 case SPE_BUILTIN_EVSTWHE:
6775 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6776 case SPE_BUILTIN_EVSTWHO:
6777 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6778 case SPE_BUILTIN_EVSTWWE:
6779 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6780 case SPE_BUILTIN_EVSTWWO:
6781 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6782 case SPE_BUILTIN_MFSPEFSCR:
6783 icode = CODE_FOR_spe_mfspefscr;
6784 tmode = insn_data[icode].operand[0].mode;
6787 || GET_MODE (target) != tmode
6788 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6789 target = gen_reg_rtx (tmode);
6791 pat = GEN_FCN (icode) (target);
6796 case SPE_BUILTIN_MTSPEFSCR:
6797 icode = CODE_FOR_spe_mtspefscr;
6798 arg0 = TREE_VALUE (arglist);
6799 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6800 mode0 = insn_data[icode].operand[0].mode;
6802 if (arg0 == error_mark_node)
6805 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6806 op0 = copy_to_mode_reg (mode0, op0);
6808 pat = GEN_FCN (icode) (op0);
6821 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6823 rtx pat, scratch, tmp;
6824 tree form = TREE_VALUE (arglist);
6825 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6826 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6827 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6828 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6829 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6830 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6834 if (TREE_CODE (form) != INTEGER_CST)
6836 error ("argument 1 of __builtin_spe_predicate must be a constant");
6840 form_int = TREE_INT_CST_LOW (form);
6845 if (arg0 == error_mark_node || arg1 == error_mark_node)
6849 || GET_MODE (target) != SImode
6850 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6851 target = gen_reg_rtx (SImode);
6853 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6854 op0 = copy_to_mode_reg (mode0, op0);
6855 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6856 op1 = copy_to_mode_reg (mode1, op1);
6858 scratch = gen_reg_rtx (CCmode);
6860 pat = GEN_FCN (icode) (scratch, op0, op1);
6865 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6866 _lower_. We use one compare, but look in different bits of the
6867 CR for each variant.
6869 There are 2 elements in each SPE simd type (upper/lower). The CR
6870 bits are set as follows:
6872 BIT0 | BIT 1 | BIT 2 | BIT 3
6873 U | L | (U | L) | (U & L)
6875 So, for an "all" relationship, BIT 3 would be set.
6876 For an "any" relationship, BIT 2 would be set. Etc.
6878 Following traditional nomenclature, these bits map to:
6880 BIT0 | BIT 1 | BIT 2 | BIT 3
6883 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6888 /* All variant. OV bit. */
6890 /* We need to get to the OV bit, which is the ORDERED bit. We
6891 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6892 that's ugly and will trigger a validate_condition_mode abort.
6893 So let's just use another pattern. */
6894 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6896 /* Any variant. EQ bit. */
6900 /* Upper variant. LT bit. */
6904 /* Lower variant. GT bit. */
6909 error ("argument 1 of __builtin_spe_predicate is out of range");
6913 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6914 emit_move_insn (target, tmp);
6919 /* The evsel builtins look like this:
6921 e = __builtin_spe_evsel_OP (a, b, c, d);
6925 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6926 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6930 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6933 tree arg0 = TREE_VALUE (arglist);
6934 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6935 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6936 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6937 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6938 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6939 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6940 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6941 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6942 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6947 if (arg0 == error_mark_node || arg1 == error_mark_node
6948 || arg2 == error_mark_node || arg3 == error_mark_node)
6952 || GET_MODE (target) != mode0
6953 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6954 target = gen_reg_rtx (mode0);
6956 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6957 op0 = copy_to_mode_reg (mode0, op0);
6958 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6959 op1 = copy_to_mode_reg (mode0, op1);
6960 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6961 op2 = copy_to_mode_reg (mode0, op2);
6962 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6963 op3 = copy_to_mode_reg (mode0, op3);
6965 /* Generate the compare. */
6966 scratch = gen_reg_rtx (CCmode);
6967 pat = GEN_FCN (icode) (scratch, op0, op1);
6972 if (mode0 == V2SImode)
6973 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6975 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6980 /* Expand an expression EXP that calls a built-in function,
6981 with result going to TARGET if that's convenient
6982 (and in mode MODE if that's convenient).
6983 SUBTARGET may be used as the target for computing one of EXP's operands.
6984 IGNORE is nonzero if the value is to be ignored. */
6987 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6988 enum machine_mode mode ATTRIBUTE_UNUSED,
6989 int ignore ATTRIBUTE_UNUSED)
6991 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6992 tree arglist = TREE_OPERAND (exp, 1);
6993 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6994 struct builtin_description *d;
6999 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7000 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7002 int icode = (int) CODE_FOR_altivec_lvsr;
7003 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7004 enum machine_mode mode = insn_data[icode].operand[1].mode;
7008 if (!TARGET_ALTIVEC)
7011 arg = TREE_VALUE (arglist);
7012 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7014 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7015 addr = memory_address (mode, op);
7016 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7020 /* For the load case need to negate the address. */
7021 op = gen_reg_rtx (GET_MODE (addr));
7022 emit_insn (gen_rtx_SET (VOIDmode, op,
7023 gen_rtx_NEG (GET_MODE (addr), addr)));
7025 op = gen_rtx_MEM (mode, op);
7028 || GET_MODE (target) != tmode
7029 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7030 target = gen_reg_rtx (tmode);
7032 /*pat = gen_altivec_lvsr (target, op);*/
7033 pat = GEN_FCN (icode) (target, op);
7043 ret = altivec_expand_builtin (exp, target, &success);
7050 ret = spe_expand_builtin (exp, target, &success);
7056 if (TARGET_ALTIVEC || TARGET_SPE)
7058 /* Handle simple unary operations. */
7059 d = (struct builtin_description *) bdesc_1arg;
7060 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7061 if (d->code == fcode)
7062 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7064 /* Handle simple binary operations. */
7065 d = (struct builtin_description *) bdesc_2arg;
7066 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7067 if (d->code == fcode)
7068 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7070 /* Handle simple ternary operations. */
7071 d = (struct builtin_description *) bdesc_3arg;
7072 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7073 if (d->code == fcode)
7074 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7082 build_opaque_vector_type (tree node, int nunits)
7084 node = copy_node (node);
7085 TYPE_MAIN_VARIANT (node) = node;
7086 return build_vector_type (node, nunits);
7090 rs6000_init_builtins (void)
7092 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7093 V2SF_type_node = build_vector_type (float_type_node, 2);
7094 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7095 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7096 V4SF_type_node = build_vector_type (float_type_node, 4);
7097 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7098 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7100 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7101 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7102 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7104 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7105 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7106 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7108 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7109 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7110 'vector unsigned short'. */
7112 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7113 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7114 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7115 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7117 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7118 get_identifier ("__bool char"),
7119 bool_char_type_node));
7120 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7121 get_identifier ("__bool short"),
7122 bool_short_type_node));
7123 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7124 get_identifier ("__bool int"),
7125 bool_int_type_node));
7126 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7127 get_identifier ("__pixel"),
7130 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7131 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7132 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7133 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7135 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7136 get_identifier ("__vector unsigned char"),
7137 unsigned_V16QI_type_node));
7138 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7139 get_identifier ("__vector signed char"),
7141 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7142 get_identifier ("__vector __bool char"),
7143 bool_V16QI_type_node));
7145 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7146 get_identifier ("__vector unsigned short"),
7147 unsigned_V8HI_type_node));
7148 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7149 get_identifier ("__vector signed short"),
7151 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7152 get_identifier ("__vector __bool short"),
7153 bool_V8HI_type_node));
7155 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7156 get_identifier ("__vector unsigned int"),
7157 unsigned_V4SI_type_node));
7158 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7159 get_identifier ("__vector signed int"),
7161 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7162 get_identifier ("__vector __bool int"),
7163 bool_V4SI_type_node));
7165 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7166 get_identifier ("__vector float"),
7168 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7169 get_identifier ("__vector __pixel"),
7170 pixel_V8HI_type_node));
7173 spe_init_builtins ();
7175 altivec_init_builtins ();
7176 if (TARGET_ALTIVEC || TARGET_SPE)
7177 rs6000_common_init_builtins ();
7180 /* Search through a set of builtins and enable the mask bits.
7181 DESC is an array of builtins.
7182 SIZE is the total number of builtins.
7183 START is the builtin enum at which to start.
7184 END is the builtin enum at which to end. */
7186 enable_mask_for_builtins (struct builtin_description *desc, int size,
7187 enum rs6000_builtins start,
7188 enum rs6000_builtins end)
7192 for (i = 0; i < size; ++i)
7193 if (desc[i].code == start)
7199 for (; i < size; ++i)
7201 /* Flip all the bits on. */
7202 desc[i].mask = target_flags;
7203 if (desc[i].code == end)
7209 spe_init_builtins (void)
7211 tree endlink = void_list_node;
7212 tree puint_type_node = build_pointer_type (unsigned_type_node);
7213 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7214 struct builtin_description *d;
7217 tree v2si_ftype_4_v2si
7218 = build_function_type
7219 (opaque_V2SI_type_node,
7220 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7221 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7222 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7223 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7226 tree v2sf_ftype_4_v2sf
7227 = build_function_type
7228 (opaque_V2SF_type_node,
7229 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7230 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7231 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7232 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7235 tree int_ftype_int_v2si_v2si
7236 = build_function_type
7238 tree_cons (NULL_TREE, integer_type_node,
7239 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7240 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7243 tree int_ftype_int_v2sf_v2sf
7244 = build_function_type
7246 tree_cons (NULL_TREE, integer_type_node,
7247 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7248 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7251 tree void_ftype_v2si_puint_int
7252 = build_function_type (void_type_node,
7253 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7254 tree_cons (NULL_TREE, puint_type_node,
7255 tree_cons (NULL_TREE,
7259 tree void_ftype_v2si_puint_char
7260 = build_function_type (void_type_node,
7261 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7262 tree_cons (NULL_TREE, puint_type_node,
7263 tree_cons (NULL_TREE,
7267 tree void_ftype_v2si_pv2si_int
7268 = build_function_type (void_type_node,
7269 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7270 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7271 tree_cons (NULL_TREE,
7275 tree void_ftype_v2si_pv2si_char
7276 = build_function_type (void_type_node,
7277 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7278 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7279 tree_cons (NULL_TREE,
7284 = build_function_type (void_type_node,
7285 tree_cons (NULL_TREE, integer_type_node, endlink));
7288 = build_function_type (integer_type_node, endlink);
7290 tree v2si_ftype_pv2si_int
7291 = build_function_type (opaque_V2SI_type_node,
7292 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7293 tree_cons (NULL_TREE, integer_type_node,
7296 tree v2si_ftype_puint_int
7297 = build_function_type (opaque_V2SI_type_node,
7298 tree_cons (NULL_TREE, puint_type_node,
7299 tree_cons (NULL_TREE, integer_type_node,
7302 tree v2si_ftype_pushort_int
7303 = build_function_type (opaque_V2SI_type_node,
7304 tree_cons (NULL_TREE, pushort_type_node,
7305 tree_cons (NULL_TREE, integer_type_node,
7308 tree v2si_ftype_signed_char
7309 = build_function_type (opaque_V2SI_type_node,
7310 tree_cons (NULL_TREE, signed_char_type_node,
7313 /* The initialization of the simple binary and unary builtins is
7314 done in rs6000_common_init_builtins, but we have to enable the
7315 mask bits here manually because we have run out of `target_flags'
7316 bits. We really need to redesign this mask business. */
7318 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7319 ARRAY_SIZE (bdesc_2arg),
7322 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7323 ARRAY_SIZE (bdesc_1arg),
7325 SPE_BUILTIN_EVSUBFUSIAAW);
7326 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7327 ARRAY_SIZE (bdesc_spe_predicates),
7328 SPE_BUILTIN_EVCMPEQ,
7329 SPE_BUILTIN_EVFSTSTLT);
7330 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7331 ARRAY_SIZE (bdesc_spe_evsel),
7332 SPE_BUILTIN_EVSEL_CMPGTS,
7333 SPE_BUILTIN_EVSEL_FSTSTEQ);
7335 (*lang_hooks.decls.pushdecl)
7336 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7337 opaque_V2SI_type_node));
7339 /* Initialize irregular SPE builtins. */
7341 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7342 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7343 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7344 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7345 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7346 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7347 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7348 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7349 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7350 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7351 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7352 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7353 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7354 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7355 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7356 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7357 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7358 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7361 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7362 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7363 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7364 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7365 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7366 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7367 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7368 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7369 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7370 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7371 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7372 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7373 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7374 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7375 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7376 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7377 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7378 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7379 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7380 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7381 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7382 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7385 d = (struct builtin_description *) bdesc_spe_predicates;
7386 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7390 switch (insn_data[d->icode].operand[1].mode)
7393 type = int_ftype_int_v2si_v2si;
7396 type = int_ftype_int_v2sf_v2sf;
7402 def_builtin (d->mask, d->name, type, d->code);
7405 /* Evsel predicates. */
7406 d = (struct builtin_description *) bdesc_spe_evsel;
7407 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7411 switch (insn_data[d->icode].operand[1].mode)
7414 type = v2si_ftype_4_v2si;
7417 type = v2sf_ftype_4_v2sf;
7423 def_builtin (d->mask, d->name, type, d->code);
7428 altivec_init_builtins (void)
7430 struct builtin_description *d;
7431 struct builtin_description_predicates *dp;
7433 tree pfloat_type_node = build_pointer_type (float_type_node);
7434 tree pint_type_node = build_pointer_type (integer_type_node);
7435 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7436 tree pchar_type_node = build_pointer_type (char_type_node);
7438 tree pvoid_type_node = build_pointer_type (void_type_node);
7440 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7441 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7442 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7443 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7445 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7447 tree int_ftype_int_v4si_v4si
7448 = build_function_type_list (integer_type_node,
7449 integer_type_node, V4SI_type_node,
7450 V4SI_type_node, NULL_TREE);
7451 tree v4sf_ftype_pcfloat
7452 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7453 tree void_ftype_pfloat_v4sf
7454 = build_function_type_list (void_type_node,
7455 pfloat_type_node, V4SF_type_node, NULL_TREE);
7456 tree v4si_ftype_pcint
7457 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7458 tree void_ftype_pint_v4si
7459 = build_function_type_list (void_type_node,
7460 pint_type_node, V4SI_type_node, NULL_TREE);
7461 tree v8hi_ftype_pcshort
7462 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7463 tree void_ftype_pshort_v8hi
7464 = build_function_type_list (void_type_node,
7465 pshort_type_node, V8HI_type_node, NULL_TREE);
7466 tree v16qi_ftype_pcchar
7467 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7468 tree void_ftype_pchar_v16qi
7469 = build_function_type_list (void_type_node,
7470 pchar_type_node, V16QI_type_node, NULL_TREE);
7471 tree void_ftype_v4si
7472 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7473 tree v8hi_ftype_void
7474 = build_function_type (V8HI_type_node, void_list_node);
7475 tree void_ftype_void
7476 = build_function_type (void_type_node, void_list_node);
7478 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7480 tree v16qi_ftype_long_pcvoid
7481 = build_function_type_list (V16QI_type_node,
7482 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7483 tree v8hi_ftype_long_pcvoid
7484 = build_function_type_list (V8HI_type_node,
7485 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7486 tree v4si_ftype_long_pcvoid
7487 = build_function_type_list (V4SI_type_node,
7488 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7490 tree void_ftype_v4si_long_pvoid
7491 = build_function_type_list (void_type_node,
7492 V4SI_type_node, long_integer_type_node,
7493 pvoid_type_node, NULL_TREE);
7494 tree void_ftype_v16qi_long_pvoid
7495 = build_function_type_list (void_type_node,
7496 V16QI_type_node, long_integer_type_node,
7497 pvoid_type_node, NULL_TREE);
7498 tree void_ftype_v8hi_long_pvoid
7499 = build_function_type_list (void_type_node,
7500 V8HI_type_node, long_integer_type_node,
7501 pvoid_type_node, NULL_TREE);
7502 tree int_ftype_int_v8hi_v8hi
7503 = build_function_type_list (integer_type_node,
7504 integer_type_node, V8HI_type_node,
7505 V8HI_type_node, NULL_TREE);
7506 tree int_ftype_int_v16qi_v16qi
7507 = build_function_type_list (integer_type_node,
7508 integer_type_node, V16QI_type_node,
7509 V16QI_type_node, NULL_TREE);
7510 tree int_ftype_int_v4sf_v4sf
7511 = build_function_type_list (integer_type_node,
7512 integer_type_node, V4SF_type_node,
7513 V4SF_type_node, NULL_TREE);
7514 tree v4si_ftype_v4si
7515 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7516 tree v8hi_ftype_v8hi
7517 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7518 tree v16qi_ftype_v16qi
7519 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7520 tree v4sf_ftype_v4sf
7521 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7522 tree void_ftype_pcvoid_int_int
7523 = build_function_type_list (void_type_node,
7524 pcvoid_type_node, integer_type_node,
7525 integer_type_node, NULL_TREE);
7526 tree int_ftype_pcchar
7527 = build_function_type_list (integer_type_node,
7528 pcchar_type_node, NULL_TREE);
7530 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7531 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7532 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7533 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7534 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7535 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7536 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7537 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7538 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7539 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7540 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7541 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7542 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7543 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7544 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7545 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7546 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7547 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7548 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7549 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7550 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7551 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7552 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7553 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7554 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7555 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7556 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7557 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7558 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7559 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7560 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7561 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7563 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7564 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7565 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7567 /* Add the DST variants. */
7568 d = (struct builtin_description *) bdesc_dst;
7569 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7570 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7572 /* Initialize the predicates. */
7573 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7574 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7576 enum machine_mode mode1;
7579 mode1 = insn_data[dp->icode].operand[1].mode;
7584 type = int_ftype_int_v4si_v4si;
7587 type = int_ftype_int_v8hi_v8hi;
7590 type = int_ftype_int_v16qi_v16qi;
7593 type = int_ftype_int_v4sf_v4sf;
7599 def_builtin (dp->mask, dp->name, type, dp->code);
7602 /* Initialize the abs* operators. */
7603 d = (struct builtin_description *) bdesc_abs;
7604 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7606 enum machine_mode mode0;
7609 mode0 = insn_data[d->icode].operand[0].mode;
7614 type = v4si_ftype_v4si;
7617 type = v8hi_ftype_v8hi;
7620 type = v16qi_ftype_v16qi;
7623 type = v4sf_ftype_v4sf;
7629 def_builtin (d->mask, d->name, type, d->code);
7636 /* Initialize target builtin that implements
7637 targetm.vectorize.builtin_mask_for_load. */
7639 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7640 v16qi_ftype_long_pcvoid,
7641 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7642 BUILT_IN_MD, NULL, NULL_TREE);
7643 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7644 altivec_builtin_mask_for_load = decl;
7649 rs6000_common_init_builtins (void)
7651 struct builtin_description *d;
7654 tree v4sf_ftype_v4sf_v4sf_v16qi
7655 = build_function_type_list (V4SF_type_node,
7656 V4SF_type_node, V4SF_type_node,
7657 V16QI_type_node, NULL_TREE);
7658 tree v4si_ftype_v4si_v4si_v16qi
7659 = build_function_type_list (V4SI_type_node,
7660 V4SI_type_node, V4SI_type_node,
7661 V16QI_type_node, NULL_TREE);
7662 tree v8hi_ftype_v8hi_v8hi_v16qi
7663 = build_function_type_list (V8HI_type_node,
7664 V8HI_type_node, V8HI_type_node,
7665 V16QI_type_node, NULL_TREE);
7666 tree v16qi_ftype_v16qi_v16qi_v16qi
7667 = build_function_type_list (V16QI_type_node,
7668 V16QI_type_node, V16QI_type_node,
7669 V16QI_type_node, NULL_TREE);
7671 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7673 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7674 tree v16qi_ftype_int
7675 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7676 tree v8hi_ftype_v16qi
7677 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7678 tree v4sf_ftype_v4sf
7679 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7681 tree v2si_ftype_v2si_v2si
7682 = build_function_type_list (opaque_V2SI_type_node,
7683 opaque_V2SI_type_node,
7684 opaque_V2SI_type_node, NULL_TREE);
7686 tree v2sf_ftype_v2sf_v2sf
7687 = build_function_type_list (opaque_V2SF_type_node,
7688 opaque_V2SF_type_node,
7689 opaque_V2SF_type_node, NULL_TREE);
7691 tree v2si_ftype_int_int
7692 = build_function_type_list (opaque_V2SI_type_node,
7693 integer_type_node, integer_type_node,
7696 tree v2si_ftype_v2si
7697 = build_function_type_list (opaque_V2SI_type_node,
7698 opaque_V2SI_type_node, NULL_TREE);
7700 tree v2sf_ftype_v2sf
7701 = build_function_type_list (opaque_V2SF_type_node,
7702 opaque_V2SF_type_node, NULL_TREE);
7704 tree v2sf_ftype_v2si
7705 = build_function_type_list (opaque_V2SF_type_node,
7706 opaque_V2SI_type_node, NULL_TREE);
7708 tree v2si_ftype_v2sf
7709 = build_function_type_list (opaque_V2SI_type_node,
7710 opaque_V2SF_type_node, NULL_TREE);
7712 tree v2si_ftype_v2si_char
7713 = build_function_type_list (opaque_V2SI_type_node,
7714 opaque_V2SI_type_node,
7715 char_type_node, NULL_TREE);
7717 tree v2si_ftype_int_char
7718 = build_function_type_list (opaque_V2SI_type_node,
7719 integer_type_node, char_type_node, NULL_TREE);
7721 tree v2si_ftype_char
7722 = build_function_type_list (opaque_V2SI_type_node,
7723 char_type_node, NULL_TREE);
7725 tree int_ftype_int_int
7726 = build_function_type_list (integer_type_node,
7727 integer_type_node, integer_type_node,
7730 tree v4si_ftype_v4si_v4si
7731 = build_function_type_list (V4SI_type_node,
7732 V4SI_type_node, V4SI_type_node, NULL_TREE);
7733 tree v4sf_ftype_v4si_int
7734 = build_function_type_list (V4SF_type_node,
7735 V4SI_type_node, integer_type_node, NULL_TREE);
7736 tree v4si_ftype_v4sf_int
7737 = build_function_type_list (V4SI_type_node,
7738 V4SF_type_node, integer_type_node, NULL_TREE);
7739 tree v4si_ftype_v4si_int
7740 = build_function_type_list (V4SI_type_node,
7741 V4SI_type_node, integer_type_node, NULL_TREE);
7742 tree v8hi_ftype_v8hi_int
7743 = build_function_type_list (V8HI_type_node,
7744 V8HI_type_node, integer_type_node, NULL_TREE);
7745 tree v16qi_ftype_v16qi_int
7746 = build_function_type_list (V16QI_type_node,
7747 V16QI_type_node, integer_type_node, NULL_TREE);
7748 tree v16qi_ftype_v16qi_v16qi_int
7749 = build_function_type_list (V16QI_type_node,
7750 V16QI_type_node, V16QI_type_node,
7751 integer_type_node, NULL_TREE);
7752 tree v8hi_ftype_v8hi_v8hi_int
7753 = build_function_type_list (V8HI_type_node,
7754 V8HI_type_node, V8HI_type_node,
7755 integer_type_node, NULL_TREE);
7756 tree v4si_ftype_v4si_v4si_int
7757 = build_function_type_list (V4SI_type_node,
7758 V4SI_type_node, V4SI_type_node,
7759 integer_type_node, NULL_TREE);
7760 tree v4sf_ftype_v4sf_v4sf_int
7761 = build_function_type_list (V4SF_type_node,
7762 V4SF_type_node, V4SF_type_node,
7763 integer_type_node, NULL_TREE);
7764 tree v4sf_ftype_v4sf_v4sf
7765 = build_function_type_list (V4SF_type_node,
7766 V4SF_type_node, V4SF_type_node, NULL_TREE);
7767 tree v4sf_ftype_v4sf_v4sf_v4si
7768 = build_function_type_list (V4SF_type_node,
7769 V4SF_type_node, V4SF_type_node,
7770 V4SI_type_node, NULL_TREE);
7771 tree v4sf_ftype_v4sf_v4sf_v4sf
7772 = build_function_type_list (V4SF_type_node,
7773 V4SF_type_node, V4SF_type_node,
7774 V4SF_type_node, NULL_TREE);
7775 tree v4si_ftype_v4si_v4si_v4si
7776 = build_function_type_list (V4SI_type_node,
7777 V4SI_type_node, V4SI_type_node,
7778 V4SI_type_node, NULL_TREE);
7779 tree v8hi_ftype_v8hi_v8hi
7780 = build_function_type_list (V8HI_type_node,
7781 V8HI_type_node, V8HI_type_node, NULL_TREE);
7782 tree v8hi_ftype_v8hi_v8hi_v8hi
7783 = build_function_type_list (V8HI_type_node,
7784 V8HI_type_node, V8HI_type_node,
7785 V8HI_type_node, NULL_TREE);
7786 tree v4si_ftype_v8hi_v8hi_v4si
7787 = build_function_type_list (V4SI_type_node,
7788 V8HI_type_node, V8HI_type_node,
7789 V4SI_type_node, NULL_TREE);
7790 tree v4si_ftype_v16qi_v16qi_v4si
7791 = build_function_type_list (V4SI_type_node,
7792 V16QI_type_node, V16QI_type_node,
7793 V4SI_type_node, NULL_TREE);
7794 tree v16qi_ftype_v16qi_v16qi
7795 = build_function_type_list (V16QI_type_node,
7796 V16QI_type_node, V16QI_type_node, NULL_TREE);
7797 tree v4si_ftype_v4sf_v4sf
7798 = build_function_type_list (V4SI_type_node,
7799 V4SF_type_node, V4SF_type_node, NULL_TREE);
7800 tree v8hi_ftype_v16qi_v16qi
7801 = build_function_type_list (V8HI_type_node,
7802 V16QI_type_node, V16QI_type_node, NULL_TREE);
7803 tree v4si_ftype_v8hi_v8hi
7804 = build_function_type_list (V4SI_type_node,
7805 V8HI_type_node, V8HI_type_node, NULL_TREE);
7806 tree v8hi_ftype_v4si_v4si
7807 = build_function_type_list (V8HI_type_node,
7808 V4SI_type_node, V4SI_type_node, NULL_TREE);
7809 tree v16qi_ftype_v8hi_v8hi
7810 = build_function_type_list (V16QI_type_node,
7811 V8HI_type_node, V8HI_type_node, NULL_TREE);
7812 tree v4si_ftype_v16qi_v4si
7813 = build_function_type_list (V4SI_type_node,
7814 V16QI_type_node, V4SI_type_node, NULL_TREE);
7815 tree v4si_ftype_v16qi_v16qi
7816 = build_function_type_list (V4SI_type_node,
7817 V16QI_type_node, V16QI_type_node, NULL_TREE);
7818 tree v4si_ftype_v8hi_v4si
7819 = build_function_type_list (V4SI_type_node,
7820 V8HI_type_node, V4SI_type_node, NULL_TREE);
7821 tree v4si_ftype_v8hi
7822 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7823 tree int_ftype_v4si_v4si
7824 = build_function_type_list (integer_type_node,
7825 V4SI_type_node, V4SI_type_node, NULL_TREE);
7826 tree int_ftype_v4sf_v4sf
7827 = build_function_type_list (integer_type_node,
7828 V4SF_type_node, V4SF_type_node, NULL_TREE);
7829 tree int_ftype_v16qi_v16qi
7830 = build_function_type_list (integer_type_node,
7831 V16QI_type_node, V16QI_type_node, NULL_TREE);
7832 tree int_ftype_v8hi_v8hi
7833 = build_function_type_list (integer_type_node,
7834 V8HI_type_node, V8HI_type_node, NULL_TREE);
7836 /* Add the simple ternary operators. */
7837 d = (struct builtin_description *) bdesc_3arg;
7838 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7841 enum machine_mode mode0, mode1, mode2, mode3;
7844 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7847 mode0 = insn_data[d->icode].operand[0].mode;
7848 mode1 = insn_data[d->icode].operand[1].mode;
7849 mode2 = insn_data[d->icode].operand[2].mode;
7850 mode3 = insn_data[d->icode].operand[3].mode;
7852 /* When all four are of the same mode. */
7853 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7858 type = v4si_ftype_v4si_v4si_v4si;
7861 type = v4sf_ftype_v4sf_v4sf_v4sf;
7864 type = v8hi_ftype_v8hi_v8hi_v8hi;
7867 type = v16qi_ftype_v16qi_v16qi_v16qi;
7873 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7878 type = v4si_ftype_v4si_v4si_v16qi;
7881 type = v4sf_ftype_v4sf_v4sf_v16qi;
7884 type = v8hi_ftype_v8hi_v8hi_v16qi;
7887 type = v16qi_ftype_v16qi_v16qi_v16qi;
7893 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7894 && mode3 == V4SImode)
7895 type = v4si_ftype_v16qi_v16qi_v4si;
7896 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7897 && mode3 == V4SImode)
7898 type = v4si_ftype_v8hi_v8hi_v4si;
7899 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7900 && mode3 == V4SImode)
7901 type = v4sf_ftype_v4sf_v4sf_v4si;
7903 /* vchar, vchar, vchar, 4 bit literal. */
7904 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7906 type = v16qi_ftype_v16qi_v16qi_int;
7908 /* vshort, vshort, vshort, 4 bit literal. */
7909 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7911 type = v8hi_ftype_v8hi_v8hi_int;
7913 /* vint, vint, vint, 4 bit literal. */
7914 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7916 type = v4si_ftype_v4si_v4si_int;
7918 /* vfloat, vfloat, vfloat, 4 bit literal. */
7919 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7921 type = v4sf_ftype_v4sf_v4sf_int;
7926 def_builtin (d->mask, d->name, type, d->code);
7929 /* Add the simple binary operators. */
7930 d = (struct builtin_description *) bdesc_2arg;
7931 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7933 enum machine_mode mode0, mode1, mode2;
7936 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7939 mode0 = insn_data[d->icode].operand[0].mode;
7940 mode1 = insn_data[d->icode].operand[1].mode;
7941 mode2 = insn_data[d->icode].operand[2].mode;
7943 /* When all three operands are of the same mode. */
7944 if (mode0 == mode1 && mode1 == mode2)
7949 type = v4sf_ftype_v4sf_v4sf;
7952 type = v4si_ftype_v4si_v4si;
7955 type = v16qi_ftype_v16qi_v16qi;
7958 type = v8hi_ftype_v8hi_v8hi;
7961 type = v2si_ftype_v2si_v2si;
7964 type = v2sf_ftype_v2sf_v2sf;
7967 type = int_ftype_int_int;
7974 /* A few other combos we really don't want to do manually. */
7976 /* vint, vfloat, vfloat. */
7977 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7978 type = v4si_ftype_v4sf_v4sf;
7980 /* vshort, vchar, vchar. */
7981 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7982 type = v8hi_ftype_v16qi_v16qi;
7984 /* vint, vshort, vshort. */
7985 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7986 type = v4si_ftype_v8hi_v8hi;
7988 /* vshort, vint, vint. */
7989 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7990 type = v8hi_ftype_v4si_v4si;
7992 /* vchar, vshort, vshort. */
7993 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7994 type = v16qi_ftype_v8hi_v8hi;
7996 /* vint, vchar, vint. */
7997 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7998 type = v4si_ftype_v16qi_v4si;
8000 /* vint, vchar, vchar. */
8001 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8002 type = v4si_ftype_v16qi_v16qi;
8004 /* vint, vshort, vint. */
8005 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8006 type = v4si_ftype_v8hi_v4si;
8008 /* vint, vint, 5 bit literal. */
8009 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8010 type = v4si_ftype_v4si_int;
8012 /* vshort, vshort, 5 bit literal. */
8013 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8014 type = v8hi_ftype_v8hi_int;
8016 /* vchar, vchar, 5 bit literal. */
8017 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8018 type = v16qi_ftype_v16qi_int;
8020 /* vfloat, vint, 5 bit literal. */
8021 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8022 type = v4sf_ftype_v4si_int;
8024 /* vint, vfloat, 5 bit literal. */
8025 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8026 type = v4si_ftype_v4sf_int;
8028 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8029 type = v2si_ftype_int_int;
8031 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8032 type = v2si_ftype_v2si_char;
8034 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8035 type = v2si_ftype_int_char;
8038 else if (mode0 == SImode)
8043 type = int_ftype_v4si_v4si;
8046 type = int_ftype_v4sf_v4sf;
8049 type = int_ftype_v16qi_v16qi;
8052 type = int_ftype_v8hi_v8hi;
8062 def_builtin (d->mask, d->name, type, d->code);
8065 /* Add the simple unary operators. */
8066 d = (struct builtin_description *) bdesc_1arg;
8067 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8069 enum machine_mode mode0, mode1;
8072 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8075 mode0 = insn_data[d->icode].operand[0].mode;
8076 mode1 = insn_data[d->icode].operand[1].mode;
8078 if (mode0 == V4SImode && mode1 == QImode)
8079 type = v4si_ftype_int;
8080 else if (mode0 == V8HImode && mode1 == QImode)
8081 type = v8hi_ftype_int;
8082 else if (mode0 == V16QImode && mode1 == QImode)
8083 type = v16qi_ftype_int;
8084 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8085 type = v4sf_ftype_v4sf;
8086 else if (mode0 == V8HImode && mode1 == V16QImode)
8087 type = v8hi_ftype_v16qi;
8088 else if (mode0 == V4SImode && mode1 == V8HImode)
8089 type = v4si_ftype_v8hi;
8090 else if (mode0 == V2SImode && mode1 == V2SImode)
8091 type = v2si_ftype_v2si;
8092 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8093 type = v2sf_ftype_v2sf;
8094 else if (mode0 == V2SFmode && mode1 == V2SImode)
8095 type = v2sf_ftype_v2si;
8096 else if (mode0 == V2SImode && mode1 == V2SFmode)
8097 type = v2si_ftype_v2sf;
8098 else if (mode0 == V2SImode && mode1 == QImode)
8099 type = v2si_ftype_char;
8103 def_builtin (d->mask, d->name, type, d->code);
8108 rs6000_init_libfuncs (void)
8110 if (!TARGET_HARD_FLOAT)
8113 if (DEFAULT_ABI != ABI_V4)
8115 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8117 /* AIX library routines for float->int conversion. */
8118 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8119 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8120 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8121 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8124 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8125 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8126 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8127 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8128 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8132 /* 32-bit SVR4 quad floating point routines. */
8134 set_optab_libfunc (add_optab, TFmode, "_q_add");
8135 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8136 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8137 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8138 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8139 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8140 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8142 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8143 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8144 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8145 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8146 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8147 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8149 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8150 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8151 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8152 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8153 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8154 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8155 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8160 /* Expand a block clear operation, and return 1 if successful. Return 0
8161 if we should let the compiler generate normal code.
8163 operands[0] is the destination
8164 operands[1] is the length
8165 operands[2] is the alignment */
8168 expand_block_clear (rtx operands[])
8170 rtx orig_dest = operands[0];
8171 rtx bytes_rtx = operands[1];
8172 rtx align_rtx = operands[2];
8173 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8174 HOST_WIDE_INT align;
8175 HOST_WIDE_INT bytes;
8180 /* If this is not a fixed size move, just call memcpy */
8184 /* If this is not a fixed size alignment, abort */
8185 if (GET_CODE (align_rtx) != CONST_INT)
8187 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8189 /* Anything to clear? */
8190 bytes = INTVAL (bytes_rtx);
8194 /* Use the builtin memset after a point, to avoid huge code bloat.
8195 When optimize_size, avoid any significant code bloat; calling
8196 memset is about 4 instructions, so allow for one instruction to
8197 load zero and three to do clearing. */
8198 if (TARGET_ALTIVEC && align >= 128)
8200 else if (TARGET_POWERPC64 && align >= 32)
8205 if (optimize_size && bytes > 3 * clear_step)
8207 if (! optimize_size && bytes > 8 * clear_step)
8210 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8212 enum machine_mode mode = BLKmode;
8215 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8220 else if (bytes >= 8 && TARGET_POWERPC64
8221 /* 64-bit loads and stores require word-aligned
8223 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8228 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8229 { /* move 4 bytes */
8233 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8234 { /* move 2 bytes */
8238 else /* move 1 byte at a time */
8244 dest = adjust_address (orig_dest, mode, offset);
8246 emit_move_insn (dest, CONST0_RTX (mode));
8253 /* Expand a block move operation, and return 1 if successful. Return 0
8254 if we should let the compiler generate normal code.
8256 operands[0] is the destination
8257 operands[1] is the source
8258 operands[2] is the length
8259 operands[3] is the alignment */
8261 #define MAX_MOVE_REG 4
8264 expand_block_move (rtx operands[])
8266 rtx orig_dest = operands[0];
8267 rtx orig_src = operands[1];
8268 rtx bytes_rtx = operands[2];
8269 rtx align_rtx = operands[3];
8270 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8275 rtx stores[MAX_MOVE_REG];
8278 /* If this is not a fixed size move, just call memcpy */
8282 /* If this is not a fixed size alignment, abort */
8283 if (GET_CODE (align_rtx) != CONST_INT)
8285 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8287 /* Anything to move? */
8288 bytes = INTVAL (bytes_rtx);
8292 /* store_one_arg depends on expand_block_move to handle at least the size of
8293 reg_parm_stack_space. */
8294 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8297 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8300 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8301 rtx (*mov) (rtx, rtx);
8303 enum machine_mode mode = BLKmode;
8306 /* Altivec first, since it will be faster than a string move
8307 when it applies, and usually not significantly larger. */
8308 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8312 gen_func.mov = gen_movv4si;
8314 else if (TARGET_STRING
8315 && bytes > 24 /* move up to 32 bytes at a time */
8323 && ! fixed_regs[12])
8325 move_bytes = (bytes > 32) ? 32 : bytes;
8326 gen_func.movmemsi = gen_movmemsi_8reg;
8328 else if (TARGET_STRING
8329 && bytes > 16 /* move up to 24 bytes at a time */
8335 && ! fixed_regs[10])
8337 move_bytes = (bytes > 24) ? 24 : bytes;
8338 gen_func.movmemsi = gen_movmemsi_6reg;
8340 else if (TARGET_STRING
8341 && bytes > 8 /* move up to 16 bytes at a time */
8347 move_bytes = (bytes > 16) ? 16 : bytes;
8348 gen_func.movmemsi = gen_movmemsi_4reg;
8350 else if (bytes >= 8 && TARGET_POWERPC64
8351 /* 64-bit loads and stores require word-aligned
8353 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8357 gen_func.mov = gen_movdi;
8359 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8360 { /* move up to 8 bytes at a time */
8361 move_bytes = (bytes > 8) ? 8 : bytes;
8362 gen_func.movmemsi = gen_movmemsi_2reg;
8364 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8365 { /* move 4 bytes */
8368 gen_func.mov = gen_movsi;
8370 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8371 { /* move 2 bytes */
8374 gen_func.mov = gen_movhi;
8376 else if (TARGET_STRING && bytes > 1)
8377 { /* move up to 4 bytes at a time */
8378 move_bytes = (bytes > 4) ? 4 : bytes;
8379 gen_func.movmemsi = gen_movmemsi_1reg;
8381 else /* move 1 byte at a time */
8385 gen_func.mov = gen_movqi;
8388 src = adjust_address (orig_src, mode, offset);
8389 dest = adjust_address (orig_dest, mode, offset);
8391 if (mode != BLKmode)
8393 rtx tmp_reg = gen_reg_rtx (mode);
8395 emit_insn ((*gen_func.mov) (tmp_reg, src));
8396 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8399 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8402 for (i = 0; i < num_reg; i++)
8403 emit_insn (stores[i]);
8407 if (mode == BLKmode)
8409 /* Move the address into scratch registers. The movmemsi
8410 patterns require zero offset. */
8411 if (!REG_P (XEXP (src, 0)))
8413 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8414 src = replace_equiv_address (src, src_reg);
8416 set_mem_size (src, GEN_INT (move_bytes));
8418 if (!REG_P (XEXP (dest, 0)))
8420 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8421 dest = replace_equiv_address (dest, dest_reg);
8423 set_mem_size (dest, GEN_INT (move_bytes));
8425 emit_insn ((*gen_func.movmemsi) (dest, src,
8426 GEN_INT (move_bytes & 31),
8435 /* Return a string to perform a load_multiple operation.
8436 operands[0] is the vector.
8437 operands[1] is the source address.
8438 operands[2] is the first destination register. */
8441 rs6000_output_load_multiple (rtx operands[3])
8443 /* We have to handle the case where the pseudo used to contain the address
8444 is assigned to one of the output registers. */
8446 int words = XVECLEN (operands[0], 0);
8449 if (XVECLEN (operands[0], 0) == 1)
8450 return "{l|lwz} %2,0(%1)";
8452 for (i = 0; i < words; i++)
8453 if (refers_to_regno_p (REGNO (operands[2]) + i,
8454 REGNO (operands[2]) + i + 1, operands[1], 0))
8458 xop[0] = GEN_INT (4 * (words-1));
8459 xop[1] = operands[1];
8460 xop[2] = operands[2];
8461 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8466 xop[0] = GEN_INT (4 * (words-1));
8467 xop[1] = operands[1];
8468 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8469 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8474 for (j = 0; j < words; j++)
8477 xop[0] = GEN_INT (j * 4);
8478 xop[1] = operands[1];
8479 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8480 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8482 xop[0] = GEN_INT (i * 4);
8483 xop[1] = operands[1];
8484 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8489 return "{lsi|lswi} %2,%1,%N0";
8493 /* A validation routine: say whether CODE, a condition code, and MODE
8494 match. The other alternatives either don't make sense or should
8495 never be generated. */
8498 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8500 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8501 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8502 || GET_MODE_CLASS (mode) != MODE_CC)
8505 /* These don't make sense. */
8506 if ((code == GT || code == LT || code == GE || code == LE)
8507 && mode == CCUNSmode)
8510 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8511 && mode != CCUNSmode)
8514 if (mode != CCFPmode
8515 && (code == ORDERED || code == UNORDERED
8516 || code == UNEQ || code == LTGT
8517 || code == UNGT || code == UNLT
8518 || code == UNGE || code == UNLE))
8521 /* These should never be generated except for
8522 flag_finite_math_only. */
8523 if (mode == CCFPmode
8524 && ! flag_finite_math_only
8525 && (code == LE || code == GE
8526 || code == UNEQ || code == LTGT
8527 || code == UNGT || code == UNLT))
8530 /* These are invalid; the information is not there. */
8531 if (mode == CCEQmode
8532 && code != EQ && code != NE)
8537 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8538 mask required to convert the result of a rotate insn into a shift
8539 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8542 includes_lshift_p (rtx shiftop, rtx andop)
8544 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8546 shift_mask <<= INTVAL (shiftop);
8548 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8551 /* Similar, but for right shift. */
8554 includes_rshift_p (rtx shiftop, rtx andop)
8556 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8558 shift_mask >>= INTVAL (shiftop);
8560 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8563 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8564 to perform a left shift. It must have exactly SHIFTOP least
8565 significant 0's, then one or more 1's, then zero or more 0's. */
8568 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8570 if (GET_CODE (andop) == CONST_INT)
8572 HOST_WIDE_INT c, lsb, shift_mask;
8575 if (c == 0 || c == ~0)
8579 shift_mask <<= INTVAL (shiftop);
8581 /* Find the least significant one bit. */
8584 /* It must coincide with the LSB of the shift mask. */
8585 if (-lsb != shift_mask)
8588 /* Invert to look for the next transition (if any). */
8591 /* Remove the low group of ones (originally low group of zeros). */
8594 /* Again find the lsb, and check we have all 1's above. */
8598 else if (GET_CODE (andop) == CONST_DOUBLE
8599 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8601 HOST_WIDE_INT low, high, lsb;
8602 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8604 low = CONST_DOUBLE_LOW (andop);
8605 if (HOST_BITS_PER_WIDE_INT < 64)
8606 high = CONST_DOUBLE_HIGH (andop);
8608 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8609 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8612 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8614 shift_mask_high = ~0;
8615 if (INTVAL (shiftop) > 32)
8616 shift_mask_high <<= INTVAL (shiftop) - 32;
8620 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8627 return high == -lsb;
8630 shift_mask_low = ~0;
8631 shift_mask_low <<= INTVAL (shiftop);
8635 if (-lsb != shift_mask_low)
8638 if (HOST_BITS_PER_WIDE_INT < 64)
8643 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8646 return high == -lsb;
8650 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8656 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8657 to perform a left shift. It must have SHIFTOP or more least
8658 significant 0's, with the remainder of the word 1's. */
8661 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8663 if (GET_CODE (andop) == CONST_INT)
8665 HOST_WIDE_INT c, lsb, shift_mask;
8668 shift_mask <<= INTVAL (shiftop);
8671 /* Find the least significant one bit. */
8674 /* It must be covered by the shift mask.
8675 This test also rejects c == 0. */
8676 if ((lsb & shift_mask) == 0)
8679 /* Check we have all 1's above the transition, and reject all 1's. */
8680 return c == -lsb && lsb != 1;
8682 else if (GET_CODE (andop) == CONST_DOUBLE
8683 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8685 HOST_WIDE_INT low, lsb, shift_mask_low;
8687 low = CONST_DOUBLE_LOW (andop);
8689 if (HOST_BITS_PER_WIDE_INT < 64)
8691 HOST_WIDE_INT high, shift_mask_high;
8693 high = CONST_DOUBLE_HIGH (andop);
8697 shift_mask_high = ~0;
8698 if (INTVAL (shiftop) > 32)
8699 shift_mask_high <<= INTVAL (shiftop) - 32;
8703 if ((lsb & shift_mask_high) == 0)
8706 return high == -lsb;
8712 shift_mask_low = ~0;
8713 shift_mask_low <<= INTVAL (shiftop);
8717 if ((lsb & shift_mask_low) == 0)
8720 return low == -lsb && lsb != 1;
8726 /* Return 1 if operands will generate a valid arguments to rlwimi
8727 instruction for insert with right shift in 64-bit mode. The mask may
8728 not start on the first bit or stop on the last bit because wrap-around
8729 effects of instruction do not correspond to semantics of RTL insn. */
8732 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8734 if (INTVAL (startop) < 64
8735 && INTVAL (startop) > 32
8736 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8737 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8738 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8739 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8740 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8746 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8747 for lfq and stfq insns iff the registers are hard registers. */
8750 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8752 /* We might have been passed a SUBREG. */
8753 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8756 /* We might have been passed non floating point registers. */
8757 if (!FP_REGNO_P (REGNO (reg1))
8758 || !FP_REGNO_P (REGNO (reg2)))
8761 return (REGNO (reg1) == REGNO (reg2) - 1);
8764 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8765 addr1 and addr2 must be in consecutive memory locations
8766 (addr2 == addr1 + 8). */
8769 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
8775 /* The mems cannot be volatile. */
8776 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8779 addr1 = XEXP (mem1, 0);
8780 addr2 = XEXP (mem2, 0);
8782 /* Extract an offset (if used) from the first addr. */
8783 if (GET_CODE (addr1) == PLUS)
8785 /* If not a REG, return zero. */
8786 if (GET_CODE (XEXP (addr1, 0)) != REG)
8790 reg1 = REGNO (XEXP (addr1, 0));
8791 /* The offset must be constant! */
8792 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8794 offset1 = INTVAL (XEXP (addr1, 1));
8797 else if (GET_CODE (addr1) != REG)
8801 reg1 = REGNO (addr1);
8802 /* This was a simple (mem (reg)) expression. Offset is 0. */
8806 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8807 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8808 register as addr1. */
8809 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8811 if (GET_CODE (addr2) != PLUS)
8814 if (GET_CODE (XEXP (addr2, 0)) != REG
8815 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8818 if (reg1 != REGNO (XEXP (addr2, 0)))
8821 /* The offset for the second addr must be 8 more than the first addr. */
8822 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8825 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8830 /* Return the register class of a scratch register needed to copy IN into
8831 or out of a register in CLASS in MODE. If it can be done directly,
8832 NO_REGS is returned. */
8835 secondary_reload_class (enum reg_class class,
8836 enum machine_mode mode ATTRIBUTE_UNUSED,
8841 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8843 && MACHOPIC_INDIRECT
8847 /* We cannot copy a symbolic operand directly into anything
8848 other than BASE_REGS for TARGET_ELF. So indicate that a
8849 register from BASE_REGS is needed as an intermediate
8852 On Darwin, pic addresses require a load from memory, which
8853 needs a base register. */
8854 if (class != BASE_REGS
8855 && (GET_CODE (in) == SYMBOL_REF
8856 || GET_CODE (in) == HIGH
8857 || GET_CODE (in) == LABEL_REF
8858 || GET_CODE (in) == CONST))
8862 if (GET_CODE (in) == REG)
8865 if (regno >= FIRST_PSEUDO_REGISTER)
8867 regno = true_regnum (in);
8868 if (regno >= FIRST_PSEUDO_REGISTER)
8872 else if (GET_CODE (in) == SUBREG)
8874 regno = true_regnum (in);
8875 if (regno >= FIRST_PSEUDO_REGISTER)
8881 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8883 if (class == GENERAL_REGS || class == BASE_REGS
8884 || (regno >= 0 && INT_REGNO_P (regno)))
8887 /* Constants, memory, and FP registers can go into FP registers. */
8888 if ((regno == -1 || FP_REGNO_P (regno))
8889 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8892 /* Memory, and AltiVec registers can go into AltiVec registers. */
8893 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8894 && class == ALTIVEC_REGS)
8897 /* We can copy among the CR registers. */
8898 if ((class == CR_REGS || class == CR0_REGS)
8899 && regno >= 0 && CR_REGNO_P (regno))
8902 /* Otherwise, we need GENERAL_REGS. */
8903 return GENERAL_REGS;
8906 /* Given a comparison operation, return the bit number in CCR to test. We
8907 know this is a valid comparison.
8909 SCC_P is 1 if this is for an scc. That means that %D will have been
8910 used instead of %C, so the bits will be in different places.
8912 Return -1 if OP isn't a valid comparison for some reason. */
8915 ccr_bit (rtx op, int scc_p)
8917 enum rtx_code code = GET_CODE (op);
8918 enum machine_mode cc_mode;
8923 if (!COMPARISON_P (op))
8928 if (GET_CODE (reg) != REG
8929 || ! CR_REGNO_P (REGNO (reg)))
8932 cc_mode = GET_MODE (reg);
8933 cc_regnum = REGNO (reg);
8934 base_bit = 4 * (cc_regnum - CR0_REGNO);
8936 validate_condition_mode (code, cc_mode);
8938 /* When generating a sCOND operation, only positive conditions are
8940 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8941 && code != GTU && code != LTU)
8947 return scc_p ? base_bit + 3 : base_bit + 2;
8949 return base_bit + 2;
8950 case GT: case GTU: case UNLE:
8951 return base_bit + 1;
8952 case LT: case LTU: case UNGE:
8954 case ORDERED: case UNORDERED:
8955 return base_bit + 3;
8958 /* If scc, we will have done a cror to put the bit in the
8959 unordered position. So test that bit. For integer, this is ! LT
8960 unless this is an scc insn. */
8961 return scc_p ? base_bit + 3 : base_bit;
8964 return scc_p ? base_bit + 3 : base_bit + 1;
8971 /* Return the GOT register. */
8974 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8976 /* The second flow pass currently (June 1999) can't update
8977 regs_ever_live without disturbing other parts of the compiler, so
8978 update it here to make the prolog/epilogue code happy. */
8979 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8980 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8982 current_function_uses_pic_offset_table = 1;
8984 return pic_offset_table_rtx;
8987 /* Function to init struct machine_function.
8988 This will be called, via a pointer variable,
8989 from push_function_context. */
8991 static struct machine_function *
8992 rs6000_init_machine_status (void)
8994 return ggc_alloc_cleared (sizeof (machine_function));
8997 /* These macros test for integers and extract the low-order bits. */
8999 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9000 && GET_MODE (X) == VOIDmode)
9002 #define INT_LOWPART(X) \
9003 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9009 unsigned long val = INT_LOWPART (op);
9011 /* If the high bit is zero, the value is the first 1 bit we find
9013 if ((val & 0x80000000) == 0)
9015 if ((val & 0xffffffff) == 0)
9019 while (((val <<= 1) & 0x80000000) == 0)
9024 /* If the high bit is set and the low bit is not, or the mask is all
9025 1's, the value is zero. */
9026 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9029 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9032 while (((val >>= 1) & 1) != 0)
9042 unsigned long val = INT_LOWPART (op);
9044 /* If the low bit is zero, the value is the first 1 bit we find from
9048 if ((val & 0xffffffff) == 0)
9052 while (((val >>= 1) & 1) == 0)
9058 /* If the low bit is set and the high bit is not, or the mask is all
9059 1's, the value is 31. */
9060 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9063 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9066 while (((val <<= 1) & 0x80000000) != 0)
9072 /* Locate some local-dynamic symbol still in use by this function
9073 so that we can print its name in some tls_ld pattern. */
9076 rs6000_get_some_local_dynamic_name (void)
9080 if (cfun->machine->some_ld_name)
9081 return cfun->machine->some_ld_name;
9083 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9085 && for_each_rtx (&PATTERN (insn),
9086 rs6000_get_some_local_dynamic_name_1, 0))
9087 return cfun->machine->some_ld_name;
9092 /* Helper function for rs6000_get_some_local_dynamic_name. */
9095 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9099 if (GET_CODE (x) == SYMBOL_REF)
9101 const char *str = XSTR (x, 0);
9102 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9104 cfun->machine->some_ld_name = str;
9112 /* Write out a function code label. */
9115 rs6000_output_function_entry (FILE *file, const char *fname)
9117 if (fname[0] != '.')
9119 switch (DEFAULT_ABI)
9128 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9137 RS6000_OUTPUT_BASENAME (file, fname);
9139 assemble_name (file, fname);
9142 /* Print an operand. Recognize special options, documented below. */
9145 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9146 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9148 #define SMALL_DATA_RELOC "sda21"
9149 #define SMALL_DATA_REG 0
9153 print_operand (FILE *file, rtx x, int code)
9157 unsigned HOST_WIDE_INT uval;
9162 /* Write out an instruction after the call which may be replaced
9163 with glue code by the loader. This depends on the AIX version. */
9164 asm_fprintf (file, RS6000_CALL_GLUE);
9167 /* %a is output_address. */
9170 /* If X is a constant integer whose low-order 5 bits are zero,
9171 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9172 in the AIX assembler where "sri" with a zero shift count
9173 writes a trash instruction. */
9174 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9181 /* If constant, low-order 16 bits of constant, unsigned.
9182 Otherwise, write normally. */
9184 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9186 print_operand (file, x, 0);
9190 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9191 for 64-bit mask direction. */
9192 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
9195 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9199 /* X is a CR register. Print the number of the GT bit of the CR. */
9200 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9201 output_operand_lossage ("invalid %%E value");
9203 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9207 /* Like 'J' but get to the EQ bit. */
9208 if (GET_CODE (x) != REG)
9211 /* Bit 1 is EQ bit. */
9212 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9214 /* If we want bit 31, write a shift count of zero, not 32. */
9215 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9219 /* X is a CR register. Print the number of the EQ bit of the CR */
9220 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9221 output_operand_lossage ("invalid %%E value");
9223 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9227 /* X is a CR register. Print the shift count needed to move it
9228 to the high-order four bits. */
9229 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9230 output_operand_lossage ("invalid %%f value");
9232 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9236 /* Similar, but print the count for the rotate in the opposite
9238 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9239 output_operand_lossage ("invalid %%F value");
9241 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9245 /* X is a constant integer. If it is negative, print "m",
9246 otherwise print "z". This is to make an aze or ame insn. */
9247 if (GET_CODE (x) != CONST_INT)
9248 output_operand_lossage ("invalid %%G value");
9249 else if (INTVAL (x) >= 0)
9256 /* If constant, output low-order five bits. Otherwise, write
9259 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9261 print_operand (file, x, 0);
9265 /* If constant, output low-order six bits. Otherwise, write
9268 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9270 print_operand (file, x, 0);
9274 /* Print `i' if this is a constant, else nothing. */
9280 /* Write the bit number in CCR for jump. */
9283 output_operand_lossage ("invalid %%j code");
9285 fprintf (file, "%d", i);
9289 /* Similar, but add one for shift count in rlinm for scc and pass
9290 scc flag to `ccr_bit'. */
9293 output_operand_lossage ("invalid %%J code");
9295 /* If we want bit 31, write a shift count of zero, not 32. */
9296 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9300 /* X must be a constant. Write the 1's complement of the
9303 output_operand_lossage ("invalid %%k value");
9305 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9309 /* X must be a symbolic constant on ELF. Write an
9310 expression suitable for an 'addi' that adds in the low 16
9312 if (GET_CODE (x) != CONST)
9314 print_operand_address (file, x);
9319 if (GET_CODE (XEXP (x, 0)) != PLUS
9320 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9321 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9322 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9323 output_operand_lossage ("invalid %%K value");
9324 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9326 /* For GNU as, there must be a non-alphanumeric character
9327 between 'l' and the number. The '-' is added by
9328 print_operand() already. */
9329 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9331 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9335 /* %l is output_asm_label. */
9338 /* Write second word of DImode or DFmode reference. Works on register
9339 or non-indexed memory only. */
9340 if (GET_CODE (x) == REG)
9341 fputs (reg_names[REGNO (x) + 1], file);
9342 else if (GET_CODE (x) == MEM)
9344 /* Handle possible auto-increment. Since it is pre-increment and
9345 we have already done it, we can just use an offset of word. */
9346 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9347 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9348 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9351 output_address (XEXP (adjust_address_nv (x, SImode,
9355 if (small_data_operand (x, GET_MODE (x)))
9356 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9357 reg_names[SMALL_DATA_REG]);
9362 /* MB value for a mask operand. */
9363 if (! mask_operand (x, SImode))
9364 output_operand_lossage ("invalid %%m value");
9366 fprintf (file, "%d", extract_MB (x));
9370 /* ME value for a mask operand. */
9371 if (! mask_operand (x, SImode))
9372 output_operand_lossage ("invalid %%M value");
9374 fprintf (file, "%d", extract_ME (x));
9377 /* %n outputs the negative of its operand. */
9380 /* Write the number of elements in the vector times 4. */
9381 if (GET_CODE (x) != PARALLEL)
9382 output_operand_lossage ("invalid %%N value");
9384 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9388 /* Similar, but subtract 1 first. */
9389 if (GET_CODE (x) != PARALLEL)
9390 output_operand_lossage ("invalid %%O value");
9392 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9396 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9398 || INT_LOWPART (x) < 0
9399 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9400 output_operand_lossage ("invalid %%p value");
9402 fprintf (file, "%d", i);
9406 /* The operand must be an indirect memory reference. The result
9407 is the register name. */
9408 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9409 || REGNO (XEXP (x, 0)) >= 32)
9410 output_operand_lossage ("invalid %%P value");
9412 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9416 /* This outputs the logical code corresponding to a boolean
9417 expression. The expression may have one or both operands
9418 negated (if one, only the first one). For condition register
9419 logical operations, it will also treat the negated
9420 CR codes as NOTs, but not handle NOTs of them. */
9422 const char *const *t = 0;
9424 enum rtx_code code = GET_CODE (x);
9425 static const char * const tbl[3][3] = {
9426 { "and", "andc", "nor" },
9427 { "or", "orc", "nand" },
9428 { "xor", "eqv", "xor" } };
9432 else if (code == IOR)
9434 else if (code == XOR)
9437 output_operand_lossage ("invalid %%q value");
9439 if (GET_CODE (XEXP (x, 0)) != NOT)
9443 if (GET_CODE (XEXP (x, 1)) == NOT)
9461 /* X is a CR register. Print the mask for `mtcrf'. */
9462 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9463 output_operand_lossage ("invalid %%R value");
9465 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9469 /* Low 5 bits of 32 - value */
9471 output_operand_lossage ("invalid %%s value");
9473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9477 /* PowerPC64 mask position. All 0's is excluded.
9478 CONST_INT 32-bit mask is considered sign-extended so any
9479 transition must occur within the CONST_INT, not on the boundary. */
9480 if (! mask64_operand (x, DImode))
9481 output_operand_lossage ("invalid %%S value");
9483 uval = INT_LOWPART (x);
9485 if (uval & 1) /* Clear Left */
9487 #if HOST_BITS_PER_WIDE_INT > 64
9488 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9492 else /* Clear Right */
9495 #if HOST_BITS_PER_WIDE_INT > 64
9496 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9504 fprintf (file, "%d", i);
9508 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9509 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9512 /* Bit 3 is OV bit. */
9513 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9515 /* If we want bit 31, write a shift count of zero, not 32. */
9516 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9520 /* Print the symbolic name of a branch target register. */
9521 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9522 && REGNO (x) != COUNT_REGISTER_REGNUM))
9523 output_operand_lossage ("invalid %%T value");
9524 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9525 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9527 fputs ("ctr", file);
9531 /* High-order 16 bits of constant for use in unsigned operand. */
9533 output_operand_lossage ("invalid %%u value");
9535 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9536 (INT_LOWPART (x) >> 16) & 0xffff);
9540 /* High-order 16 bits of constant for use in signed operand. */
9542 output_operand_lossage ("invalid %%v value");
9544 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9545 (INT_LOWPART (x) >> 16) & 0xffff);
9549 /* Print `u' if this has an auto-increment or auto-decrement. */
9550 if (GET_CODE (x) == MEM
9551 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9552 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9557 /* Print the trap code for this operand. */
9558 switch (GET_CODE (x))
9561 fputs ("eq", file); /* 4 */
9564 fputs ("ne", file); /* 24 */
9567 fputs ("lt", file); /* 16 */
9570 fputs ("le", file); /* 20 */
9573 fputs ("gt", file); /* 8 */
9576 fputs ("ge", file); /* 12 */
9579 fputs ("llt", file); /* 2 */
9582 fputs ("lle", file); /* 6 */
9585 fputs ("lgt", file); /* 1 */
9588 fputs ("lge", file); /* 5 */
9596 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9599 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9600 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9602 print_operand (file, x, 0);
9606 /* MB value for a PowerPC64 rldic operand. */
9607 val = (GET_CODE (x) == CONST_INT
9608 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9613 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9614 if ((val <<= 1) < 0)
9617 #if HOST_BITS_PER_WIDE_INT == 32
9618 if (GET_CODE (x) == CONST_INT && i >= 0)
9619 i += 32; /* zero-extend high-part was all 0's */
9620 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9622 val = CONST_DOUBLE_LOW (x);
9629 for ( ; i < 64; i++)
9630 if ((val <<= 1) < 0)
9635 fprintf (file, "%d", i + 1);
9639 if (GET_CODE (x) == MEM
9640 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9645 /* Like 'L', for third word of TImode */
9646 if (GET_CODE (x) == REG)
9647 fputs (reg_names[REGNO (x) + 2], file);
9648 else if (GET_CODE (x) == MEM)
9650 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9651 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9652 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9654 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9655 if (small_data_operand (x, GET_MODE (x)))
9656 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9657 reg_names[SMALL_DATA_REG]);
9662 /* X is a SYMBOL_REF. Write out the name preceded by a
9663 period and without any trailing data in brackets. Used for function
9664 names. If we are configured for System V (or the embedded ABI) on
9665 the PowerPC, do not emit the period, since those systems do not use
9666 TOCs and the like. */
9667 if (GET_CODE (x) != SYMBOL_REF)
9670 /* Mark the decl as referenced so that cgraph will output the
9672 if (SYMBOL_REF_DECL (x))
9673 mark_decl_referenced (SYMBOL_REF_DECL (x));
9675 /* For macho, check to see if we need a stub. */
9678 const char *name = XSTR (x, 0);
9680 if (MACHOPIC_INDIRECT
9681 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9682 name = machopic_indirection_name (x, /*stub_p=*/true);
9684 assemble_name (file, name);
9686 else if (!DOT_SYMBOLS)
9687 assemble_name (file, XSTR (x, 0));
9689 rs6000_output_function_entry (file, XSTR (x, 0));
9693 /* Like 'L', for last word of TImode. */
9694 if (GET_CODE (x) == REG)
9695 fputs (reg_names[REGNO (x) + 3], file);
9696 else if (GET_CODE (x) == MEM)
9698 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9699 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9700 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9702 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9703 if (small_data_operand (x, GET_MODE (x)))
9704 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9705 reg_names[SMALL_DATA_REG]);
9709 /* Print AltiVec or SPE memory operand. */
9714 if (GET_CODE (x) != MEM)
9722 if (GET_CODE (tmp) == REG)
9724 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9727 /* Handle [reg+UIMM]. */
9728 else if (GET_CODE (tmp) == PLUS &&
9729 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9733 if (GET_CODE (XEXP (tmp, 0)) != REG)
9736 x = INTVAL (XEXP (tmp, 1));
9737 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9741 /* Fall through. Must be [reg+reg]. */
9744 && GET_CODE (tmp) == AND
9745 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9746 && INTVAL (XEXP (tmp, 1)) == -16)
9747 tmp = XEXP (tmp, 0);
9748 if (GET_CODE (tmp) == REG)
9749 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9750 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9752 if (REGNO (XEXP (tmp, 0)) == 0)
9753 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9754 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9756 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9757 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9765 if (GET_CODE (x) == REG)
9766 fprintf (file, "%s", reg_names[REGNO (x)]);
9767 else if (GET_CODE (x) == MEM)
9769 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9770 know the width from the mode. */
9771 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9772 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9773 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9774 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9775 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9776 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9778 output_address (XEXP (x, 0));
9781 output_addr_const (file, x);
9785 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9789 output_operand_lossage ("invalid %%xn code");
9793 /* Print the address of an operand. */
9796 print_operand_address (FILE *file, rtx x)
9798 if (GET_CODE (x) == REG)
9799 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9800 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9801 || GET_CODE (x) == LABEL_REF)
9803 output_addr_const (file, x);
9804 if (small_data_operand (x, GET_MODE (x)))
9805 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9806 reg_names[SMALL_DATA_REG]);
9807 else if (TARGET_TOC)
9810 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9812 if (REGNO (XEXP (x, 0)) == 0)
9813 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9814 reg_names[ REGNO (XEXP (x, 0)) ]);
9816 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9817 reg_names[ REGNO (XEXP (x, 1)) ]);
9819 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9820 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9821 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9823 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9824 && CONSTANT_P (XEXP (x, 1)))
9826 output_addr_const (file, XEXP (x, 1));
9827 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9831 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9832 && CONSTANT_P (XEXP (x, 1)))
9834 fprintf (file, "lo16(");
9835 output_addr_const (file, XEXP (x, 1));
9836 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9839 else if (legitimate_constant_pool_address_p (x))
9841 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9843 rtx contains_minus = XEXP (x, 1);
9847 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9848 turn it into (sym) for output_addr_const. */
9849 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9850 contains_minus = XEXP (contains_minus, 0);
9852 minus = XEXP (contains_minus, 0);
9853 symref = XEXP (minus, 0);
9854 XEXP (contains_minus, 0) = symref;
9859 name = XSTR (symref, 0);
9860 newname = alloca (strlen (name) + sizeof ("@toc"));
9861 strcpy (newname, name);
9862 strcat (newname, "@toc");
9863 XSTR (symref, 0) = newname;
9865 output_addr_const (file, XEXP (x, 1));
9867 XSTR (symref, 0) = name;
9868 XEXP (contains_minus, 0) = minus;
9871 output_addr_const (file, XEXP (x, 1));
9873 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9879 /* Target hook for assembling integer objects. The PowerPC version has
9880 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9881 is defined. It also needs to handle DI-mode objects on 64-bit
9885 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9887 #ifdef RELOCATABLE_NEEDS_FIXUP
9888 /* Special handling for SI values. */
9889 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
9891 extern int in_toc_section (void);
9892 static int recurse = 0;
9894 /* For -mrelocatable, we mark all addresses that need to be fixed up
9895 in the .fixup section. */
9896 if (TARGET_RELOCATABLE
9897 && !in_toc_section ()
9898 && !in_text_section ()
9899 && !in_unlikely_text_section ()
9901 && GET_CODE (x) != CONST_INT
9902 && GET_CODE (x) != CONST_DOUBLE
9908 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9910 ASM_OUTPUT_LABEL (asm_out_file, buf);
9911 fprintf (asm_out_file, "\t.long\t(");
9912 output_addr_const (asm_out_file, x);
9913 fprintf (asm_out_file, ")@fixup\n");
9914 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9915 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9916 fprintf (asm_out_file, "\t.long\t");
9917 assemble_name (asm_out_file, buf);
9918 fprintf (asm_out_file, "\n\t.previous\n");
9922 /* Remove initial .'s to turn a -mcall-aixdesc function
9923 address into the address of the descriptor, not the function
9925 else if (GET_CODE (x) == SYMBOL_REF
9926 && XSTR (x, 0)[0] == '.'
9927 && DEFAULT_ABI == ABI_AIX)
9929 const char *name = XSTR (x, 0);
9930 while (*name == '.')
9933 fprintf (asm_out_file, "\t.long\t%s\n", name);
9937 #endif /* RELOCATABLE_NEEDS_FIXUP */
9938 return default_assemble_integer (x, size, aligned_p);
9941 #ifdef HAVE_GAS_HIDDEN
9942 /* Emit an assembler directive to set symbol visibility for DECL to
9946 rs6000_assemble_visibility (tree decl, int vis)
9948 /* Functions need to have their entry point symbol visibility set as
9949 well as their descriptor symbol visibility. */
9950 if (DEFAULT_ABI == ABI_AIX
9952 && TREE_CODE (decl) == FUNCTION_DECL)
9954 static const char * const visibility_types[] = {
9955 NULL, "internal", "hidden", "protected"
9958 const char *name, *type;
9960 name = ((* targetm.strip_name_encoding)
9961 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9962 type = visibility_types[vis];
9964 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9965 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9968 default_assemble_visibility (decl, vis);
9973 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9975 /* Reversal of FP compares takes care -- an ordered compare
9976 becomes an unordered compare and vice versa. */
9977 if (mode == CCFPmode
9978 && (!flag_finite_math_only
9979 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9980 || code == UNEQ || code == LTGT))
9981 return reverse_condition_maybe_unordered (code);
9983 return reverse_condition (code);
9986 /* Generate a compare for CODE. Return a brand-new rtx that
9987 represents the result of the compare. */
9990 rs6000_generate_compare (enum rtx_code code)
9992 enum machine_mode comp_mode;
9995 if (rs6000_compare_fp_p)
9996 comp_mode = CCFPmode;
9997 else if (code == GTU || code == LTU
9998 || code == GEU || code == LEU)
9999 comp_mode = CCUNSmode;
10000 else if ((code == EQ || code == NE)
10001 && GET_CODE (rs6000_compare_op0) == SUBREG
10002 && GET_CODE (rs6000_compare_op1) == SUBREG
10003 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10004 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10005 /* These are unsigned values, perhaps there will be a later
10006 ordering compare that can be shared with this one.
10007 Unfortunately we cannot detect the signedness of the operands
10008 for non-subregs. */
10009 comp_mode = CCUNSmode;
10011 comp_mode = CCmode;
10013 /* First, the compare. */
10014 compare_result = gen_reg_rtx (comp_mode);
10016 /* SPE FP compare instructions on the GPRs. Yuck! */
10017 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10018 && rs6000_compare_fp_p)
10020 rtx cmp, or1, or2, or_result, compare_result2;
10021 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10023 if (op_mode == VOIDmode)
10024 op_mode = GET_MODE (rs6000_compare_op1);
10026 /* Note: The E500 comparison instructions set the GT bit (x +
10027 1), on success. This explains the mess. */
10031 case EQ: case UNEQ: case NE: case LTGT:
10032 if (op_mode == SFmode)
10033 cmp = flag_unsafe_math_optimizations
10034 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10035 rs6000_compare_op1)
10036 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10037 rs6000_compare_op1);
10038 else if (op_mode == DFmode)
10039 cmp = flag_unsafe_math_optimizations
10040 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10041 rs6000_compare_op1)
10042 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10043 rs6000_compare_op1);
10046 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10047 if (op_mode == SFmode)
10048 cmp = flag_unsafe_math_optimizations
10049 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10050 rs6000_compare_op1)
10051 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10052 rs6000_compare_op1);
10053 else if (op_mode == DFmode)
10054 cmp = flag_unsafe_math_optimizations
10055 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10056 rs6000_compare_op1)
10057 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10058 rs6000_compare_op1);
10061 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10062 if (op_mode == SFmode)
10063 cmp = flag_unsafe_math_optimizations
10064 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10065 rs6000_compare_op1)
10066 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10067 rs6000_compare_op1);
10068 else if (op_mode == DFmode)
10069 cmp = flag_unsafe_math_optimizations
10070 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10071 rs6000_compare_op1)
10072 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10073 rs6000_compare_op1);
10080 /* Synthesize LE and GE from LT/GT || EQ. */
10081 if (code == LE || code == GE || code == LEU || code == GEU)
10087 case LE: code = LT; break;
10088 case GE: code = GT; break;
10089 case LEU: code = LT; break;
10090 case GEU: code = GT; break;
10094 or1 = gen_reg_rtx (SImode);
10095 or2 = gen_reg_rtx (SImode);
10096 or_result = gen_reg_rtx (CCEQmode);
10097 compare_result2 = gen_reg_rtx (CCFPmode);
10100 if (op_mode == SFmode)
10101 cmp = flag_unsafe_math_optimizations
10102 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10103 rs6000_compare_op1)
10104 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10105 rs6000_compare_op1);
10106 else if (op_mode == DFmode)
10107 cmp = flag_unsafe_math_optimizations
10108 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10109 rs6000_compare_op1)
10110 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10111 rs6000_compare_op1);
10115 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
10116 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
10118 /* OR them together. */
10119 cmp = gen_rtx_SET (VOIDmode, or_result,
10120 gen_rtx_COMPARE (CCEQmode,
10121 gen_rtx_IOR (SImode, or1, or2),
10123 compare_result = or_result;
10128 if (code == NE || code == LTGT)
10138 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10139 CLOBBERs to match cmptf_internal2 pattern. */
10140 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10141 && GET_MODE (rs6000_compare_op0) == TFmode
10142 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10143 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10144 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10146 gen_rtx_SET (VOIDmode,
10148 gen_rtx_COMPARE (comp_mode,
10149 rs6000_compare_op0,
10150 rs6000_compare_op1)),
10151 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10152 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10153 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10154 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10155 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10156 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10157 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10158 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10160 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10161 gen_rtx_COMPARE (comp_mode,
10162 rs6000_compare_op0,
10163 rs6000_compare_op1)));
10166 /* Some kinds of FP comparisons need an OR operation;
10167 under flag_unsafe_math_optimizations we don't bother. */
10168 if (rs6000_compare_fp_p
10169 && ! flag_unsafe_math_optimizations
10170 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10171 && (code == LE || code == GE
10172 || code == UNEQ || code == LTGT
10173 || code == UNGT || code == UNLT))
10175 enum rtx_code or1, or2;
10176 rtx or1_rtx, or2_rtx, compare2_rtx;
10177 rtx or_result = gen_reg_rtx (CCEQmode);
10181 case LE: or1 = LT; or2 = EQ; break;
10182 case GE: or1 = GT; or2 = EQ; break;
10183 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10184 case LTGT: or1 = LT; or2 = GT; break;
10185 case UNGT: or1 = UNORDERED; or2 = GT; break;
10186 case UNLT: or1 = UNORDERED; or2 = LT; break;
10189 validate_condition_mode (or1, comp_mode);
10190 validate_condition_mode (or2, comp_mode);
10191 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10192 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10193 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10194 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10196 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10198 compare_result = or_result;
10202 validate_condition_mode (code, GET_MODE (compare_result));
10204 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10208 /* Emit the RTL for an sCOND pattern. */
10211 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10214 enum machine_mode op_mode;
10215 enum rtx_code cond_code;
10217 condition_rtx = rs6000_generate_compare (code);
10218 cond_code = GET_CODE (condition_rtx);
10220 if (TARGET_E500 && rs6000_compare_fp_p
10221 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10225 PUT_MODE (condition_rtx, SImode);
10226 t = XEXP (condition_rtx, 0);
10228 if (cond_code != NE && cond_code != EQ)
10231 if (cond_code == NE)
10232 emit_insn (gen_e500_flip_eq_bit (t, t));
10234 emit_insn (gen_move_from_CR_eq_bit (result, t));
10238 if (cond_code == NE
10239 || cond_code == GE || cond_code == LE
10240 || cond_code == GEU || cond_code == LEU
10241 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10243 rtx not_result = gen_reg_rtx (CCEQmode);
10244 rtx not_op, rev_cond_rtx;
10245 enum machine_mode cc_mode;
10247 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10249 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10250 SImode, XEXP (condition_rtx, 0), const0_rtx);
10251 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10252 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10253 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10256 op_mode = GET_MODE (rs6000_compare_op0);
10257 if (op_mode == VOIDmode)
10258 op_mode = GET_MODE (rs6000_compare_op1);
10260 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10262 PUT_MODE (condition_rtx, DImode);
10263 convert_move (result, condition_rtx, 0);
10267 PUT_MODE (condition_rtx, SImode);
10268 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10272 /* Emit a branch of kind CODE to location LOC. */
10275 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10277 rtx condition_rtx, loc_ref;
10279 condition_rtx = rs6000_generate_compare (code);
10280 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10281 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10282 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10283 loc_ref, pc_rtx)));
10286 /* Return the string to output a conditional branch to LABEL, which is
10287 the operand number of the label, or -1 if the branch is really a
10288 conditional return.
10290 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10291 condition code register and its mode specifies what kind of
10292 comparison we made.
10294 REVERSED is nonzero if we should reverse the sense of the comparison.
10296 INSN is the insn. */
10299 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10301 static char string[64];
10302 enum rtx_code code = GET_CODE (op);
10303 rtx cc_reg = XEXP (op, 0);
10304 enum machine_mode mode = GET_MODE (cc_reg);
10305 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10306 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10307 int really_reversed = reversed ^ need_longbranch;
10313 validate_condition_mode (code, mode);
10315 /* Work out which way this really branches. We could use
10316 reverse_condition_maybe_unordered here always but this
10317 makes the resulting assembler clearer. */
10318 if (really_reversed)
10320 /* Reversal of FP compares takes care -- an ordered compare
10321 becomes an unordered compare and vice versa. */
10322 if (mode == CCFPmode)
10323 code = reverse_condition_maybe_unordered (code);
10325 code = reverse_condition (code);
10328 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10330 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10333 /* Opposite of GT. */
10335 else if (code == NE)
10343 /* Not all of these are actually distinct opcodes, but
10344 we distinguish them for clarity of the resulting assembler. */
10345 case NE: case LTGT:
10346 ccode = "ne"; break;
10347 case EQ: case UNEQ:
10348 ccode = "eq"; break;
10350 ccode = "ge"; break;
10351 case GT: case GTU: case UNGT:
10352 ccode = "gt"; break;
10354 ccode = "le"; break;
10355 case LT: case LTU: case UNLT:
10356 ccode = "lt"; break;
10357 case UNORDERED: ccode = "un"; break;
10358 case ORDERED: ccode = "nu"; break;
10359 case UNGE: ccode = "nl"; break;
10360 case UNLE: ccode = "ng"; break;
10365 /* Maybe we have a guess as to how likely the branch is.
10366 The old mnemonics don't have a way to specify this information. */
10368 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10369 if (note != NULL_RTX)
10371 /* PROB is the difference from 50%. */
10372 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10374 /* Only hint for highly probable/improbable branches on newer
10375 cpus as static prediction overrides processor dynamic
10376 prediction. For older cpus we may as well always hint, but
10377 assume not taken for branches that are very close to 50% as a
10378 mispredicted taken branch is more expensive than a
10379 mispredicted not-taken branch. */
10380 if (rs6000_always_hint
10381 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10383 if (abs (prob) > REG_BR_PROB_BASE / 20
10384 && ((prob > 0) ^ need_longbranch))
10392 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10394 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10396 /* We need to escape any '%' characters in the reg_names string.
10397 Assume they'd only be the first character.... */
10398 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10400 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10404 /* If the branch distance was too far, we may have to use an
10405 unconditional branch to go the distance. */
10406 if (need_longbranch)
10407 s += sprintf (s, ",$+8\n\tb %s", label);
10409 s += sprintf (s, ",%s", label);
10415 /* Return the string to flip the EQ bit on a CR. */
10417 output_e500_flip_eq_bit (rtx dst, rtx src)
10419 static char string[64];
10422 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10423 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10427 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
10428 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
10430 sprintf (string, "crnot %d,%d", a, b);
10434 /* Return insn index for the vector compare instruction for given CODE,
10435 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10439 get_vec_cmp_insn (enum rtx_code code,
10440 enum machine_mode dest_mode,
10441 enum machine_mode op_mode)
10443 if (!TARGET_ALTIVEC)
10444 return INSN_NOT_AVAILABLE;
10449 if (dest_mode == V16QImode && op_mode == V16QImode)
10450 return UNSPEC_VCMPEQUB;
10451 if (dest_mode == V8HImode && op_mode == V8HImode)
10452 return UNSPEC_VCMPEQUH;
10453 if (dest_mode == V4SImode && op_mode == V4SImode)
10454 return UNSPEC_VCMPEQUW;
10455 if (dest_mode == V4SImode && op_mode == V4SFmode)
10456 return UNSPEC_VCMPEQFP;
10459 if (dest_mode == V4SImode && op_mode == V4SFmode)
10460 return UNSPEC_VCMPGEFP;
10462 if (dest_mode == V16QImode && op_mode == V16QImode)
10463 return UNSPEC_VCMPGTSB;
10464 if (dest_mode == V8HImode && op_mode == V8HImode)
10465 return UNSPEC_VCMPGTSH;
10466 if (dest_mode == V4SImode && op_mode == V4SImode)
10467 return UNSPEC_VCMPGTSW;
10468 if (dest_mode == V4SImode && op_mode == V4SFmode)
10469 return UNSPEC_VCMPGTFP;
10472 if (dest_mode == V16QImode && op_mode == V16QImode)
10473 return UNSPEC_VCMPGTUB;
10474 if (dest_mode == V8HImode && op_mode == V8HImode)
10475 return UNSPEC_VCMPGTUH;
10476 if (dest_mode == V4SImode && op_mode == V4SImode)
10477 return UNSPEC_VCMPGTUW;
10482 return INSN_NOT_AVAILABLE;
10485 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10486 DMODE is expected destination mode. This is a recursive function. */
10489 rs6000_emit_vector_compare (enum rtx_code rcode,
10491 enum machine_mode dmode)
10495 enum machine_mode dest_mode;
10496 enum machine_mode op_mode = GET_MODE (op1);
10498 #ifdef ENABLE_CHECKING
10499 if (!TARGET_ALTIVEC)
10502 if (GET_MODE (op0) != GET_MODE (op1))
10506 /* Floating point vector compare instructions uses destination V4SImode.
10507 Move destination to appropriate mode later. */
10508 if (dmode == V4SFmode)
10509 dest_mode = V4SImode;
10513 mask = gen_reg_rtx (dest_mode);
10514 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10516 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10518 bool swap_operands = false;
10519 bool try_again = false;
10524 swap_operands = true;
10529 swap_operands = true;
10533 /* Treat A != B as ~(A==B). */
10535 enum insn_code nor_code;
10536 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10539 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10540 if (nor_code == CODE_FOR_nothing)
10542 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10544 if (dmode != dest_mode)
10546 rtx temp = gen_reg_rtx (dest_mode);
10547 convert_move (temp, mask, 0);
10557 /* Try GT/GTU/LT/LTU OR EQ */
10560 enum insn_code ior_code;
10561 enum rtx_code new_code;
10565 else if (rcode == GEU)
10567 else if (rcode == LE)
10569 else if (rcode == LEU)
10574 c_rtx = rs6000_emit_vector_compare (new_code,
10575 op0, op1, dest_mode);
10576 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10579 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10580 if (ior_code == CODE_FOR_nothing)
10582 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10583 if (dmode != dest_mode)
10585 rtx temp = gen_reg_rtx (dest_mode);
10586 convert_move (temp, mask, 0);
10598 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10599 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10600 /* You only get two chances. */
10613 emit_insn (gen_rtx_fmt_ee (SET,
10616 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10617 gen_rtvec (2, op0, op1),
10619 if (dmode != dest_mode)
10621 rtx temp = gen_reg_rtx (dest_mode);
10622 convert_move (temp, mask, 0);
10628 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10629 valid insn doesn exist for given mode. */
10632 get_vsel_insn (enum machine_mode mode)
10637 return UNSPEC_VSEL4SI;
10640 return UNSPEC_VSEL4SF;
10643 return UNSPEC_VSEL8HI;
10646 return UNSPEC_VSEL16QI;
10649 return INSN_NOT_AVAILABLE;
10652 return INSN_NOT_AVAILABLE;
10655 /* Emit vector select insn where DEST is destination using
10656 operands OP1, OP2 and MASK. */
10659 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10662 enum machine_mode dest_mode = GET_MODE (dest);
10663 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10665 temp = gen_reg_rtx (dest_mode);
10667 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10668 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10669 gen_rtvec (3, op1, op2, mask),
10672 emit_move_insn (dest, temp);
10676 /* Emit vector conditional expression.
10677 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10678 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10681 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10682 rtx cond, rtx cc_op0, rtx cc_op1)
10684 enum machine_mode dest_mode = GET_MODE (dest);
10685 enum rtx_code rcode = GET_CODE (cond);
10688 if (!TARGET_ALTIVEC)
10691 /* Get the vector mask for the given relational operations. */
10692 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10694 rs6000_emit_vector_select (dest, op1, op2, mask);
10699 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10700 operands of the last comparison is nonzero/true, FALSE_COND if it
10701 is zero/false. Return 0 if the hardware has no such operation. */
10704 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10706 enum rtx_code code = GET_CODE (op);
10707 rtx op0 = rs6000_compare_op0;
10708 rtx op1 = rs6000_compare_op1;
10709 REAL_VALUE_TYPE c1;
10710 enum machine_mode compare_mode = GET_MODE (op0);
10711 enum machine_mode result_mode = GET_MODE (dest);
10713 bool is_against_zero;
10715 /* These modes should always match. */
10716 if (GET_MODE (op1) != compare_mode
10717 /* In the isel case however, we can use a compare immediate, so
10718 op1 may be a small constant. */
10719 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10721 if (GET_MODE (true_cond) != result_mode)
10723 if (GET_MODE (false_cond) != result_mode)
10726 /* First, work out if the hardware can do this at all, or
10727 if it's too slow.... */
10728 if (! rs6000_compare_fp_p)
10731 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10734 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10735 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10738 is_against_zero = op1 == CONST0_RTX (compare_mode);
10740 /* A floating-point subtract might overflow, underflow, or produce
10741 an inexact result, thus changing the floating-point flags, so it
10742 can't be generated if we care about that. It's safe if one side
10743 of the construct is zero, since then no subtract will be
10745 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10746 && flag_trapping_math && ! is_against_zero)
10749 /* Eliminate half of the comparisons by switching operands, this
10750 makes the remaining code simpler. */
10751 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10752 || code == LTGT || code == LT || code == UNLE)
10754 code = reverse_condition_maybe_unordered (code);
10756 true_cond = false_cond;
10760 /* UNEQ and LTGT take four instructions for a comparison with zero,
10761 it'll probably be faster to use a branch here too. */
10762 if (code == UNEQ && HONOR_NANS (compare_mode))
10765 if (GET_CODE (op1) == CONST_DOUBLE)
10766 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10768 /* We're going to try to implement comparisons by performing
10769 a subtract, then comparing against zero. Unfortunately,
10770 Inf - Inf is NaN which is not zero, and so if we don't
10771 know that the operand is finite and the comparison
10772 would treat EQ different to UNORDERED, we can't do it. */
10773 if (HONOR_INFINITIES (compare_mode)
10774 && code != GT && code != UNGE
10775 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10776 /* Constructs of the form (a OP b ? a : b) are safe. */
10777 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10778 || (! rtx_equal_p (op0, true_cond)
10779 && ! rtx_equal_p (op1, true_cond))))
10782 /* At this point we know we can use fsel. */
10784 /* Reduce the comparison to a comparison against zero. */
10785 if (! is_against_zero)
10787 temp = gen_reg_rtx (compare_mode);
10788 emit_insn (gen_rtx_SET (VOIDmode, temp,
10789 gen_rtx_MINUS (compare_mode, op0, op1)));
10791 op1 = CONST0_RTX (compare_mode);
10794 /* If we don't care about NaNs we can reduce some of the comparisons
10795 down to faster ones. */
10796 if (! HONOR_NANS (compare_mode))
10802 true_cond = false_cond;
10815 /* Now, reduce everything down to a GE. */
10822 temp = gen_reg_rtx (compare_mode);
10823 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10828 temp = gen_reg_rtx (compare_mode);
10829 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10834 temp = gen_reg_rtx (compare_mode);
10835 emit_insn (gen_rtx_SET (VOIDmode, temp,
10836 gen_rtx_NEG (compare_mode,
10837 gen_rtx_ABS (compare_mode, op0))));
10842 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10843 temp = gen_reg_rtx (result_mode);
10844 emit_insn (gen_rtx_SET (VOIDmode, temp,
10845 gen_rtx_IF_THEN_ELSE (result_mode,
10846 gen_rtx_GE (VOIDmode,
10848 true_cond, false_cond)));
10849 false_cond = true_cond;
10852 temp = gen_reg_rtx (compare_mode);
10853 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10858 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10859 temp = gen_reg_rtx (result_mode);
10860 emit_insn (gen_rtx_SET (VOIDmode, temp,
10861 gen_rtx_IF_THEN_ELSE (result_mode,
10862 gen_rtx_GE (VOIDmode,
10864 true_cond, false_cond)));
10865 true_cond = false_cond;
10868 temp = gen_reg_rtx (compare_mode);
10869 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10877 emit_insn (gen_rtx_SET (VOIDmode, dest,
10878 gen_rtx_IF_THEN_ELSE (result_mode,
10879 gen_rtx_GE (VOIDmode,
10881 true_cond, false_cond)));
10885 /* Same as above, but for ints (isel). */
10888 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10890 rtx condition_rtx, cr;
10892 /* All isel implementations thus far are 32-bits. */
10893 if (GET_MODE (rs6000_compare_op0) != SImode)
10896 /* We still have to do the compare, because isel doesn't do a
10897 compare, it just looks at the CRx bits set by a previous compare
10899 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10900 cr = XEXP (condition_rtx, 0);
10902 if (GET_MODE (cr) == CCmode)
10903 emit_insn (gen_isel_signed (dest, condition_rtx,
10904 true_cond, false_cond, cr));
10906 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10907 true_cond, false_cond, cr));
10913 output_isel (rtx *operands)
10915 enum rtx_code code;
10917 code = GET_CODE (operands[1]);
10918 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10920 PUT_CODE (operands[1], reverse_condition (code));
10921 return "isel %0,%3,%2,%j1";
10924 return "isel %0,%2,%3,%j1";
10928 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10930 enum machine_mode mode = GET_MODE (op0);
10934 if (code == SMAX || code == SMIN)
10939 if (code == SMAX || code == UMAX)
10940 target = emit_conditional_move (dest, c, op0, op1, mode,
10941 op0, op1, mode, 0);
10943 target = emit_conditional_move (dest, c, op0, op1, mode,
10944 op1, op0, mode, 0);
10945 if (target == NULL_RTX)
10947 if (target != dest)
10948 emit_move_insn (dest, target);
10951 /* Emit instructions to move SRC to DST. Called by splitters for
10952 multi-register moves. It will emit at most one instruction for
10953 each register that is accessed; that is, it won't emit li/lis pairs
10954 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10958 rs6000_split_multireg_move (rtx dst, rtx src)
10960 /* The register number of the first register being moved. */
10962 /* The mode that is to be moved. */
10963 enum machine_mode mode;
10964 /* The mode that the move is being done in, and its size. */
10965 enum machine_mode reg_mode;
10967 /* The number of registers that will be moved. */
10970 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10971 mode = GET_MODE (dst);
10972 nregs = HARD_REGNO_NREGS (reg, mode);
10973 if (FP_REGNO_P (reg))
10975 else if (ALTIVEC_REGNO_P (reg))
10976 reg_mode = V16QImode;
10978 reg_mode = word_mode;
10979 reg_mode_size = GET_MODE_SIZE (reg_mode);
10981 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10984 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10986 /* Move register range backwards, if we might have destructive
10989 for (i = nregs - 1; i >= 0; i--)
10990 emit_insn (gen_rtx_SET (VOIDmode,
10991 simplify_gen_subreg (reg_mode, dst, mode,
10992 i * reg_mode_size),
10993 simplify_gen_subreg (reg_mode, src, mode,
10994 i * reg_mode_size)));
11000 bool used_update = false;
11002 if (MEM_P (src) && INT_REGNO_P (reg))
11006 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11007 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11010 breg = XEXP (XEXP (src, 0), 0);
11011 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11012 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11013 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11014 emit_insn (TARGET_32BIT
11015 ? gen_addsi3 (breg, breg, delta_rtx)
11016 : gen_adddi3 (breg, breg, delta_rtx));
11017 src = gen_rtx_MEM (mode, breg);
11019 else if (! offsettable_memref_p (src))
11021 rtx newsrc, basereg;
11022 basereg = gen_rtx_REG (Pmode, reg);
11023 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11024 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11025 MEM_COPY_ATTRIBUTES (newsrc, src);
11029 breg = XEXP (src, 0);
11030 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11031 breg = XEXP (breg, 0);
11033 /* If the base register we are using to address memory is
11034 also a destination reg, then change that register last. */
11036 && REGNO (breg) >= REGNO (dst)
11037 && REGNO (breg) < REGNO (dst) + nregs)
11038 j = REGNO (breg) - REGNO (dst);
11041 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11045 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11046 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11049 breg = XEXP (XEXP (dst, 0), 0);
11050 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11051 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11052 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11054 /* We have to update the breg before doing the store.
11055 Use store with update, if available. */
11059 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11060 emit_insn (TARGET_32BIT
11061 ? (TARGET_POWERPC64
11062 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11063 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11064 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11065 used_update = true;
11068 emit_insn (TARGET_32BIT
11069 ? gen_addsi3 (breg, breg, delta_rtx)
11070 : gen_adddi3 (breg, breg, delta_rtx));
11071 dst = gen_rtx_MEM (mode, breg);
11073 else if (! offsettable_memref_p (dst))
11077 for (i = 0; i < nregs; i++)
11079 /* Calculate index to next subword. */
11084 /* If compiler already emitted move of first word by
11085 store with update, no need to do anything. */
11086 if (j == 0 && used_update)
11089 emit_insn (gen_rtx_SET (VOIDmode,
11090 simplify_gen_subreg (reg_mode, dst, mode,
11091 j * reg_mode_size),
11092 simplify_gen_subreg (reg_mode, src, mode,
11093 j * reg_mode_size)));
11099 /* This page contains routines that are used to determine what the
11100 function prologue and epilogue code will do and write them out. */
11102 /* Return the first fixed-point register that is required to be
11103 saved. 32 if none. */
11106 first_reg_to_save (void)
11110 /* Find lowest numbered live register. */
11111 for (first_reg = 13; first_reg <= 31; first_reg++)
11112 if (regs_ever_live[first_reg]
11113 && (! call_used_regs[first_reg]
11114 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11115 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11116 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11117 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11122 && current_function_uses_pic_offset_table
11123 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11124 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11130 /* Similar, for FP regs. */
11133 first_fp_reg_to_save (void)
11137 /* Find lowest numbered live register. */
11138 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11139 if (regs_ever_live[first_reg])
11145 /* Similar, for AltiVec regs. */
11148 first_altivec_reg_to_save (void)
11152 /* Stack frame remains as is unless we are in AltiVec ABI. */
11153 if (! TARGET_ALTIVEC_ABI)
11154 return LAST_ALTIVEC_REGNO + 1;
11156 /* Find lowest numbered live register. */
11157 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11158 if (regs_ever_live[i])
11164 /* Return a 32-bit mask of the AltiVec registers we need to set in
11165 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11166 the 32-bit word is 0. */
11168 static unsigned int
11169 compute_vrsave_mask (void)
11171 unsigned int i, mask = 0;
11173 /* First, find out if we use _any_ altivec registers. */
11174 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11175 if (regs_ever_live[i])
11176 mask |= ALTIVEC_REG_BIT (i);
11181 /* Next, remove the argument registers from the set. These must
11182 be in the VRSAVE mask set by the caller, so we don't need to add
11183 them in again. More importantly, the mask we compute here is
11184 used to generate CLOBBERs in the set_vrsave insn, and we do not
11185 wish the argument registers to die. */
11186 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11187 mask &= ~ALTIVEC_REG_BIT (i);
11189 /* Similarly, remove the return value from the set. */
11192 diddle_return_value (is_altivec_return_reg, &yes);
11194 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11200 /* For a very restricted set of circumstances, we can cut down the
11201 size of prologues/epilogues by calling our own save/restore-the-world
11205 compute_save_world_info (rs6000_stack_t *info_ptr)
11207 info_ptr->world_save_p = 1;
11208 info_ptr->world_save_p
11209 = (WORLD_SAVE_P (info_ptr)
11210 && DEFAULT_ABI == ABI_DARWIN
11211 && ! (current_function_calls_setjmp && flag_exceptions)
11212 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11213 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11214 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11215 && info_ptr->cr_save_p);
11217 /* This will not work in conjunction with sibcalls. Make sure there
11218 are none. (This check is expensive, but seldom executed.) */
11219 if (WORLD_SAVE_P (info_ptr))
11222 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11223 if ( GET_CODE (insn) == CALL_INSN
11224 && SIBLING_CALL_P (insn))
11226 info_ptr->world_save_p = 0;
11231 if (WORLD_SAVE_P (info_ptr))
11233 /* Even if we're not touching VRsave, make sure there's room on the
11234 stack for it, if it looks like we're calling SAVE_WORLD, which
11235 will attempt to save it. */
11236 info_ptr->vrsave_size = 4;
11238 /* "Save" the VRsave register too if we're saving the world. */
11239 if (info_ptr->vrsave_mask == 0)
11240 info_ptr->vrsave_mask = compute_vrsave_mask ();
11242 /* Because the Darwin register save/restore routines only handle
11243 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11244 check and abort if there's something worng. */
11245 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
11246 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11254 is_altivec_return_reg (rtx reg, void *xyes)
11256 bool *yes = (bool *) xyes;
11257 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11262 /* Calculate the stack information for the current function. This is
11263 complicated by having two separate calling sequences, the AIX calling
11264 sequence and the V.4 calling sequence.
11266 AIX (and Darwin/Mac OS X) stack frames look like:
11268 SP----> +---------------------------------------+
11269 | back chain to caller | 0 0
11270 +---------------------------------------+
11271 | saved CR | 4 8 (8-11)
11272 +---------------------------------------+
11274 +---------------------------------------+
11275 | reserved for compilers | 12 24
11276 +---------------------------------------+
11277 | reserved for binders | 16 32
11278 +---------------------------------------+
11279 | saved TOC pointer | 20 40
11280 +---------------------------------------+
11281 | Parameter save area (P) | 24 48
11282 +---------------------------------------+
11283 | Alloca space (A) | 24+P etc.
11284 +---------------------------------------+
11285 | Local variable space (L) | 24+P+A
11286 +---------------------------------------+
11287 | Float/int conversion temporary (X) | 24+P+A+L
11288 +---------------------------------------+
11289 | Save area for AltiVec registers (W) | 24+P+A+L+X
11290 +---------------------------------------+
11291 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11292 +---------------------------------------+
11293 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11294 +---------------------------------------+
11295 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11296 +---------------------------------------+
11297 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11298 +---------------------------------------+
11299 old SP->| back chain to caller's caller |
11300 +---------------------------------------+
11302 The required alignment for AIX configurations is two words (i.e., 8
11306 V.4 stack frames look like:
11308 SP----> +---------------------------------------+
11309 | back chain to caller | 0
11310 +---------------------------------------+
11311 | caller's saved LR | 4
11312 +---------------------------------------+
11313 | Parameter save area (P) | 8
11314 +---------------------------------------+
11315 | Alloca space (A) | 8+P
11316 +---------------------------------------+
11317 | Varargs save area (V) | 8+P+A
11318 +---------------------------------------+
11319 | Local variable space (L) | 8+P+A+V
11320 +---------------------------------------+
11321 | Float/int conversion temporary (X) | 8+P+A+V+L
11322 +---------------------------------------+
11323 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11324 +---------------------------------------+
11325 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11326 +---------------------------------------+
11327 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11328 +---------------------------------------+
11329 | SPE: area for 64-bit GP registers |
11330 +---------------------------------------+
11331 | SPE alignment padding |
11332 +---------------------------------------+
11333 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11334 +---------------------------------------+
11335 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11336 +---------------------------------------+
11337 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11338 +---------------------------------------+
11339 old SP->| back chain to caller's caller |
11340 +---------------------------------------+
11342 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11343 given. (But note below and in sysv4.h that we require only 8 and
11344 may round up the size of our stack frame anyways. The historical
11345 reason is early versions of powerpc-linux which didn't properly
11346 align the stack at program startup. A happy side-effect is that
11347 -mno-eabi libraries can be used with -meabi programs.)
11349 The EABI configuration defaults to the V.4 layout. However,
11350 the stack alignment requirements may differ. If -mno-eabi is not
11351 given, the required stack alignment is 8 bytes; if -mno-eabi is
11352 given, the required alignment is 16 bytes. (But see V.4 comment
11355 #ifndef ABI_STACK_BOUNDARY
11356 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11359 static rs6000_stack_t *
11360 rs6000_stack_info (void)
11362 static rs6000_stack_t info, zero_info;
11363 rs6000_stack_t *info_ptr = &info;
11364 int reg_size = TARGET_32BIT ? 4 : 8;
11367 HOST_WIDE_INT non_fixed_size;
11369 /* Zero all fields portably. */
11374 /* Cache value so we don't rescan instruction chain over and over. */
11375 if (cfun->machine->insn_chain_scanned_p == 0)
11376 cfun->machine->insn_chain_scanned_p
11377 = spe_func_has_64bit_regs_p () + 1;
11378 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
11381 /* Select which calling sequence. */
11382 info_ptr->abi = DEFAULT_ABI;
11384 /* Calculate which registers need to be saved & save area size. */
11385 info_ptr->first_gp_reg_save = first_reg_to_save ();
11386 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11387 even if it currently looks like we won't. */
11388 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
11389 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11390 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
11391 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11392 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
11394 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
11396 /* For the SPE, we have an additional upper 32-bits on each GPR.
11397 Ideally we should save the entire 64-bits only when the upper
11398 half is used in SIMD instructions. Since we only record
11399 registers live (not the size they are used in), this proves
11400 difficult because we'd have to traverse the instruction chain at
11401 the right time, taking reload into account. This is a real pain,
11402 so we opt to save the GPRs in 64-bits always if but one register
11403 gets used in 64-bits. Otherwise, all the registers in the frame
11404 get saved in 32-bits.
11406 So... since when we save all GPRs (except the SP) in 64-bits, the
11407 traditional GP save area will be empty. */
11408 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11409 info_ptr->gp_size = 0;
11411 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11412 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11414 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11415 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11416 - info_ptr->first_altivec_reg_save);
11418 /* Does this function call anything? */
11419 info_ptr->calls_p = (! current_function_is_leaf
11420 || cfun->machine->ra_needs_full_frame);
11422 /* Determine if we need to save the link register. */
11423 if (rs6000_ra_ever_killed ()
11424 || (DEFAULT_ABI == ABI_AIX
11425 && current_function_profile
11426 && !TARGET_PROFILE_KERNEL)
11427 #ifdef TARGET_RELOCATABLE
11428 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11430 || (info_ptr->first_fp_reg_save != 64
11431 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
11432 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
11433 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
11434 || (DEFAULT_ABI == ABI_DARWIN
11436 && current_function_uses_pic_offset_table)
11437 || info_ptr->calls_p)
11439 info_ptr->lr_save_p = 1;
11440 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
11443 /* Determine if we need to save the condition code registers. */
11444 if (regs_ever_live[CR2_REGNO]
11445 || regs_ever_live[CR3_REGNO]
11446 || regs_ever_live[CR4_REGNO])
11448 info_ptr->cr_save_p = 1;
11449 if (DEFAULT_ABI == ABI_V4)
11450 info_ptr->cr_size = reg_size;
11453 /* If the current function calls __builtin_eh_return, then we need
11454 to allocate stack space for registers that will hold data for
11455 the exception handler. */
11456 if (current_function_calls_eh_return)
11459 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11462 /* SPE saves EH registers in 64-bits. */
11463 ehrd_size = i * (TARGET_SPE_ABI
11464 && info_ptr->spe_64bit_regs_used != 0
11465 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
11470 /* Determine various sizes. */
11471 info_ptr->reg_size = reg_size;
11472 info_ptr->fixed_size = RS6000_SAVE_AREA;
11473 info_ptr->varargs_size = RS6000_VARARGS_AREA;
11474 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
11475 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
11476 TARGET_ALTIVEC ? 16 : 8);
11478 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11479 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11481 info_ptr->spe_gp_size = 0;
11483 if (TARGET_ALTIVEC_ABI)
11484 info_ptr->vrsave_mask = compute_vrsave_mask ();
11486 info_ptr->vrsave_mask = 0;
11488 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11489 info_ptr->vrsave_size = 4;
11491 info_ptr->vrsave_size = 0;
11493 compute_save_world_info (info_ptr);
11495 /* Calculate the offsets. */
11496 switch (DEFAULT_ABI)
11504 info_ptr->fp_save_offset = - info_ptr->fp_size;
11505 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11507 if (TARGET_ALTIVEC_ABI)
11509 info_ptr->vrsave_save_offset
11510 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11512 /* Align stack so vector save area is on a quadword boundary. */
11513 if (info_ptr->altivec_size != 0)
11514 info_ptr->altivec_padding_size
11515 = 16 - (-info_ptr->vrsave_save_offset % 16);
11517 info_ptr->altivec_padding_size = 0;
11519 info_ptr->altivec_save_offset
11520 = info_ptr->vrsave_save_offset
11521 - info_ptr->altivec_padding_size
11522 - info_ptr->altivec_size;
11524 /* Adjust for AltiVec case. */
11525 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11528 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
11529 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11530 info_ptr->lr_save_offset = 2*reg_size;
11534 info_ptr->fp_save_offset = - info_ptr->fp_size;
11535 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11536 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
11538 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11540 /* Align stack so SPE GPR save area is aligned on a
11541 double-word boundary. */
11542 if (info_ptr->spe_gp_size != 0)
11543 info_ptr->spe_padding_size
11544 = 8 - (-info_ptr->cr_save_offset % 8);
11546 info_ptr->spe_padding_size = 0;
11548 info_ptr->spe_gp_save_offset
11549 = info_ptr->cr_save_offset
11550 - info_ptr->spe_padding_size
11551 - info_ptr->spe_gp_size;
11553 /* Adjust for SPE case. */
11554 info_ptr->toc_save_offset
11555 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11557 else if (TARGET_ALTIVEC_ABI)
11559 info_ptr->vrsave_save_offset
11560 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11562 /* Align stack so vector save area is on a quadword boundary. */
11563 if (info_ptr->altivec_size != 0)
11564 info_ptr->altivec_padding_size
11565 = 16 - (-info_ptr->vrsave_save_offset % 16);
11567 info_ptr->altivec_padding_size = 0;
11569 info_ptr->altivec_save_offset
11570 = info_ptr->vrsave_save_offset
11571 - info_ptr->altivec_padding_size
11572 - info_ptr->altivec_size;
11574 /* Adjust for AltiVec case. */
11575 info_ptr->toc_save_offset
11576 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11579 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
11580 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
11581 info_ptr->lr_save_offset = reg_size;
11585 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
11586 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11587 + info_ptr->gp_size
11588 + info_ptr->altivec_size
11589 + info_ptr->altivec_padding_size
11590 + info_ptr->spe_gp_size
11591 + info_ptr->spe_padding_size
11593 + info_ptr->cr_size
11594 + info_ptr->lr_size
11595 + info_ptr->vrsave_size
11596 + info_ptr->toc_size,
11599 non_fixed_size = (info_ptr->vars_size
11600 + info_ptr->parm_size
11601 + info_ptr->save_size
11602 + info_ptr->varargs_size);
11604 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11605 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11607 /* Determine if we need to allocate any stack frame:
11609 For AIX we need to push the stack if a frame pointer is needed
11610 (because the stack might be dynamically adjusted), if we are
11611 debugging, if we make calls, or if the sum of fp_save, gp_save,
11612 and local variables are more than the space needed to save all
11613 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11614 + 18*8 = 288 (GPR13 reserved).
11616 For V.4 we don't have the stack cushion that AIX uses, but assume
11617 that the debugger can handle stackless frames. */
11619 if (info_ptr->calls_p)
11620 info_ptr->push_p = 1;
11622 else if (DEFAULT_ABI == ABI_V4)
11623 info_ptr->push_p = non_fixed_size != 0;
11625 else if (frame_pointer_needed)
11626 info_ptr->push_p = 1;
11628 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11629 info_ptr->push_p = 1;
11632 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11634 /* Zero offsets if we're not saving those registers. */
11635 if (info_ptr->fp_size == 0)
11636 info_ptr->fp_save_offset = 0;
11638 if (info_ptr->gp_size == 0)
11639 info_ptr->gp_save_offset = 0;
11641 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11642 info_ptr->altivec_save_offset = 0;
11644 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11645 info_ptr->vrsave_save_offset = 0;
11647 if (! TARGET_SPE_ABI
11648 || info_ptr->spe_64bit_regs_used == 0
11649 || info_ptr->spe_gp_size == 0)
11650 info_ptr->spe_gp_save_offset = 0;
11652 if (! info_ptr->lr_save_p)
11653 info_ptr->lr_save_offset = 0;
11655 if (! info_ptr->cr_save_p)
11656 info_ptr->cr_save_offset = 0;
11658 if (! info_ptr->toc_save_p)
11659 info_ptr->toc_save_offset = 0;
11664 /* Return true if the current function uses any GPRs in 64-bit SIMD
11668 spe_func_has_64bit_regs_p (void)
11672 /* Functions that save and restore all the call-saved registers will
11673 need to save/restore the registers in 64-bits. */
11674 if (current_function_calls_eh_return
11675 || current_function_calls_setjmp
11676 || current_function_has_nonlocal_goto)
11679 insns = get_insns ();
11681 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11687 /* FIXME: This should be implemented with attributes...
11689 (set_attr "spe64" "true")....then,
11690 if (get_spe64(insn)) return true;
11692 It's the only reliable way to do the stuff below. */
11694 i = PATTERN (insn);
11695 if (GET_CODE (i) == SET)
11697 enum machine_mode mode = GET_MODE (SET_SRC (i));
11699 if (SPE_VECTOR_MODE (mode))
11701 if (TARGET_E500_DOUBLE && mode == DFmode)
11711 debug_stack_info (rs6000_stack_t *info)
11713 const char *abi_string;
11716 info = rs6000_stack_info ();
11718 fprintf (stderr, "\nStack information for function %s:\n",
11719 ((current_function_decl && DECL_NAME (current_function_decl))
11720 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11725 default: abi_string = "Unknown"; break;
11726 case ABI_NONE: abi_string = "NONE"; break;
11727 case ABI_AIX: abi_string = "AIX"; break;
11728 case ABI_DARWIN: abi_string = "Darwin"; break;
11729 case ABI_V4: abi_string = "V.4"; break;
11732 fprintf (stderr, "\tABI = %5s\n", abi_string);
11734 if (TARGET_ALTIVEC_ABI)
11735 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11737 if (TARGET_SPE_ABI)
11738 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11740 if (info->first_gp_reg_save != 32)
11741 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11743 if (info->first_fp_reg_save != 64)
11744 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
11746 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11747 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11748 info->first_altivec_reg_save);
11750 if (info->lr_save_p)
11751 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
11753 if (info->cr_save_p)
11754 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11756 if (info->toc_save_p)
11757 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11759 if (info->vrsave_mask)
11760 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11763 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11766 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11768 if (info->gp_save_offset)
11769 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11771 if (info->fp_save_offset)
11772 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11774 if (info->altivec_save_offset)
11775 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11776 info->altivec_save_offset);
11778 if (info->spe_gp_save_offset)
11779 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11780 info->spe_gp_save_offset);
11782 if (info->vrsave_save_offset)
11783 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11784 info->vrsave_save_offset);
11786 if (info->lr_save_offset)
11787 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11789 if (info->cr_save_offset)
11790 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11792 if (info->toc_save_offset)
11793 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11795 if (info->varargs_save_offset)
11796 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11798 if (info->total_size)
11799 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11802 if (info->varargs_size)
11803 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11805 if (info->vars_size)
11806 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11809 if (info->parm_size)
11810 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11812 if (info->fixed_size)
11813 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11816 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11818 if (info->spe_gp_size)
11819 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11822 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11824 if (info->altivec_size)
11825 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11827 if (info->vrsave_size)
11828 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11830 if (info->altivec_padding_size)
11831 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11832 info->altivec_padding_size);
11834 if (info->spe_padding_size)
11835 fprintf (stderr, "\tspe_padding_size = %5d\n",
11836 info->spe_padding_size);
11839 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
11842 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11844 if (info->toc_size)
11845 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11847 if (info->save_size)
11848 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11850 if (info->reg_size != 4)
11851 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11853 fprintf (stderr, "\n");
11857 rs6000_return_addr (int count, rtx frame)
11859 /* Currently we don't optimize very well between prolog and body
11860 code and for PIC code the code can be actually quite bad, so
11861 don't try to be too clever here. */
11862 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11864 cfun->machine->ra_needs_full_frame = 1;
11871 plus_constant (copy_to_reg
11872 (gen_rtx_MEM (Pmode,
11873 memory_address (Pmode, frame))),
11874 RETURN_ADDRESS_OFFSET)));
11877 cfun->machine->ra_need_lr = 1;
11878 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11881 /* Say whether a function is a candidate for sibcall handling or not.
11882 We do not allow indirect calls to be optimized into sibling calls.
11883 Also, we can't do it if there are any vector parameters; there's
11884 nowhere to put the VRsave code so it works; note that functions with
11885 vector parameters are required to have a prototype, so the argument
11886 type info must be available here. (The tail recursion case can work
11887 with vector parameters, but there's no way to distinguish here.) */
11889 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11894 if (TARGET_ALTIVEC_VRSAVE)
11896 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11897 type; type = TREE_CHAIN (type))
11899 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11903 if (DEFAULT_ABI == ABI_DARWIN
11904 || (*targetm.binds_local_p) (decl))
11906 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11908 if (!lookup_attribute ("longcall", attr_list)
11909 || lookup_attribute ("shortcall", attr_list))
11917 rs6000_ra_ever_killed (void)
11923 if (current_function_is_thunk)
11926 /* regs_ever_live has LR marked as used if any sibcalls are present,
11927 but this should not force saving and restoring in the
11928 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
11929 clobbers LR, so that is inappropriate. */
11931 /* Also, the prologue can generate a store into LR that
11932 doesn't really count, like this:
11935 bcl to set PIC register
11939 When we're called from the epilogue, we need to avoid counting
11940 this as a store. */
11942 push_topmost_sequence ();
11943 top = get_insns ();
11944 pop_topmost_sequence ();
11945 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11947 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11951 if (FIND_REG_INC_NOTE (insn, reg))
11953 else if (GET_CODE (insn) == CALL_INSN
11954 && !SIBLING_CALL_P (insn))
11956 else if (set_of (reg, insn) != NULL_RTX
11957 && !prologue_epilogue_contains (insn))
11964 /* Add a REG_MAYBE_DEAD note to the insn. */
11966 rs6000_maybe_dead (rtx insn)
11968 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11973 /* Emit instructions needed to load the TOC register.
11974 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11975 a constant pool; or for SVR4 -fpic. */
11978 rs6000_emit_load_toc_table (int fromprolog)
11981 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11983 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11985 rtx temp = (fromprolog
11986 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11987 : gen_reg_rtx (Pmode));
11988 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11990 rs6000_maybe_dead (insn);
11991 insn = emit_move_insn (dest, temp);
11993 rs6000_maybe_dead (insn);
11995 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11998 rtx tempLR = (fromprolog
11999 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12000 : gen_reg_rtx (Pmode));
12001 rtx temp0 = (fromprolog
12002 ? gen_rtx_REG (Pmode, 0)
12003 : gen_reg_rtx (Pmode));
12010 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12011 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12013 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12014 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12016 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12018 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12019 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12026 static int reload_toc_labelno = 0;
12028 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12030 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12031 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12033 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12034 emit_move_insn (dest, tempLR);
12035 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12037 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12039 rs6000_maybe_dead (insn);
12041 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12043 /* This is for AIX code running in non-PIC ELF32. */
12046 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12047 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12049 insn = emit_insn (gen_elf_high (dest, realsym));
12051 rs6000_maybe_dead (insn);
12052 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12054 rs6000_maybe_dead (insn);
12056 else if (DEFAULT_ABI == ABI_AIX)
12059 insn = emit_insn (gen_load_toc_aix_si (dest));
12061 insn = emit_insn (gen_load_toc_aix_di (dest));
12063 rs6000_maybe_dead (insn);
12069 /* Emit instructions to restore the link register after determining where
12070 its value has been stored. */
12073 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12075 rs6000_stack_t *info = rs6000_stack_info ();
12078 operands[0] = source;
12079 operands[1] = scratch;
12081 if (info->lr_save_p)
12083 rtx frame_rtx = stack_pointer_rtx;
12084 HOST_WIDE_INT sp_offset = 0;
12087 if (frame_pointer_needed
12088 || current_function_calls_alloca
12089 || info->total_size > 32767)
12091 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12092 frame_rtx = operands[1];
12094 else if (info->push_p)
12095 sp_offset = info->total_size;
12097 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12098 tmp = gen_rtx_MEM (Pmode, tmp);
12099 emit_move_insn (tmp, operands[0]);
12102 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12105 static GTY(()) int set = -1;
12108 get_TOC_alias_set (void)
12111 set = new_alias_set ();
12115 /* This returns nonzero if the current function uses the TOC. This is
12116 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12117 is generated by the ABI_V4 load_toc_* patterns. */
12124 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12127 rtx pat = PATTERN (insn);
12130 if (GET_CODE (pat) == PARALLEL)
12131 for (i = 0; i < XVECLEN (pat, 0); i++)
12133 rtx sub = XVECEXP (pat, 0, i);
12134 if (GET_CODE (sub) == USE)
12136 sub = XEXP (sub, 0);
12137 if (GET_CODE (sub) == UNSPEC
12138 && XINT (sub, 1) == UNSPEC_TOC)
12148 create_TOC_reference (rtx symbol)
12150 return gen_rtx_PLUS (Pmode,
12151 gen_rtx_REG (Pmode, TOC_REGISTER),
12152 gen_rtx_CONST (Pmode,
12153 gen_rtx_MINUS (Pmode, symbol,
12154 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12157 /* If _Unwind_* has been called from within the same module,
12158 toc register is not guaranteed to be saved to 40(1) on function
12159 entry. Save it there in that case. */
12162 rs6000_aix_emit_builtin_unwind_init (void)
12165 rtx stack_top = gen_reg_rtx (Pmode);
12166 rtx opcode_addr = gen_reg_rtx (Pmode);
12167 rtx opcode = gen_reg_rtx (SImode);
12168 rtx tocompare = gen_reg_rtx (SImode);
12169 rtx no_toc_save_needed = gen_label_rtx ();
12171 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12172 emit_move_insn (stack_top, mem);
12174 mem = gen_rtx_MEM (Pmode,
12175 gen_rtx_PLUS (Pmode, stack_top,
12176 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12177 emit_move_insn (opcode_addr, mem);
12178 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12179 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12180 : 0xE8410028, SImode));
12182 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12183 SImode, NULL_RTX, NULL_RTX,
12184 no_toc_save_needed);
12186 mem = gen_rtx_MEM (Pmode,
12187 gen_rtx_PLUS (Pmode, stack_top,
12188 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12189 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12190 emit_label (no_toc_save_needed);
12193 /* This ties together stack memory (MEM with an alias set of
12194 rs6000_sr_alias_set) and the change to the stack pointer. */
12197 rs6000_emit_stack_tie (void)
12199 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12201 set_mem_alias_set (mem, rs6000_sr_alias_set);
12202 emit_insn (gen_stack_tie (mem));
12205 /* Emit the correct code for allocating stack space, as insns.
12206 If COPY_R12, make sure a copy of the old frame is left in r12.
12207 The generated code may use hard register 0 as a temporary. */
12210 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12213 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12214 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12215 rtx todec = gen_int_mode (-size, Pmode);
12217 if (INTVAL (todec) != -size)
12219 warning("stack frame too large");
12220 emit_insn (gen_trap ());
12224 if (current_function_limit_stack)
12226 if (REG_P (stack_limit_rtx)
12227 && REGNO (stack_limit_rtx) > 1
12228 && REGNO (stack_limit_rtx) <= 31)
12230 emit_insn (TARGET_32BIT
12231 ? gen_addsi3 (tmp_reg,
12234 : gen_adddi3 (tmp_reg,
12238 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12241 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12243 && DEFAULT_ABI == ABI_V4)
12245 rtx toload = gen_rtx_CONST (VOIDmode,
12246 gen_rtx_PLUS (Pmode,
12250 emit_insn (gen_elf_high (tmp_reg, toload));
12251 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12252 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12256 warning ("stack limit expression is not supported");
12259 if (copy_r12 || ! TARGET_UPDATE)
12260 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12266 /* Need a note here so that try_split doesn't get confused. */
12267 if (get_last_insn() == NULL_RTX)
12268 emit_note (NOTE_INSN_DELETED);
12269 insn = emit_move_insn (tmp_reg, todec);
12270 try_split (PATTERN (insn), insn, 0);
12274 insn = emit_insn (TARGET_32BIT
12275 ? gen_movsi_update (stack_reg, stack_reg,
12277 : gen_movdi_di_update (stack_reg, stack_reg,
12278 todec, stack_reg));
12282 insn = emit_insn (TARGET_32BIT
12283 ? gen_addsi3 (stack_reg, stack_reg, todec)
12284 : gen_adddi3 (stack_reg, stack_reg, todec));
12285 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12286 gen_rtx_REG (Pmode, 12));
12289 RTX_FRAME_RELATED_P (insn) = 1;
12291 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12292 gen_rtx_SET (VOIDmode, stack_reg,
12293 gen_rtx_PLUS (Pmode, stack_reg,
12298 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12299 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12300 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12301 deduce these equivalences by itself so it wasn't necessary to hold
12302 its hand so much. */
12305 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
12306 rtx reg2, rtx rreg)
12310 /* copy_rtx will not make unique copies of registers, so we need to
12311 ensure we don't have unwanted sharing here. */
12313 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12316 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12318 real = copy_rtx (PATTERN (insn));
12320 if (reg2 != NULL_RTX)
12321 real = replace_rtx (real, reg2, rreg);
12323 real = replace_rtx (real, reg,
12324 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12325 STACK_POINTER_REGNUM),
12328 /* We expect that 'real' is either a SET or a PARALLEL containing
12329 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12330 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12332 if (GET_CODE (real) == SET)
12336 temp = simplify_rtx (SET_SRC (set));
12338 SET_SRC (set) = temp;
12339 temp = simplify_rtx (SET_DEST (set));
12341 SET_DEST (set) = temp;
12342 if (GET_CODE (SET_DEST (set)) == MEM)
12344 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12346 XEXP (SET_DEST (set), 0) = temp;
12349 else if (GET_CODE (real) == PARALLEL)
12352 for (i = 0; i < XVECLEN (real, 0); i++)
12353 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12355 rtx set = XVECEXP (real, 0, i);
12357 temp = simplify_rtx (SET_SRC (set));
12359 SET_SRC (set) = temp;
12360 temp = simplify_rtx (SET_DEST (set));
12362 SET_DEST (set) = temp;
12363 if (GET_CODE (SET_DEST (set)) == MEM)
12365 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12367 XEXP (SET_DEST (set), 0) = temp;
12369 RTX_FRAME_RELATED_P (set) = 1;
12376 real = spe_synthesize_frame_save (real);
12378 RTX_FRAME_RELATED_P (insn) = 1;
12379 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12384 /* Given an SPE frame note, return a PARALLEL of SETs with the
12385 original note, plus a synthetic register save. */
12388 spe_synthesize_frame_save (rtx real)
12390 rtx synth, offset, reg, real2;
12392 if (GET_CODE (real) != SET
12393 || GET_MODE (SET_SRC (real)) != V2SImode)
12396 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12397 frame related note. The parallel contains a set of the register
12398 being saved, and another set to a synthetic register (n+1200).
12399 This is so we can differentiate between 64-bit and 32-bit saves.
12400 Words cannot describe this nastiness. */
12402 if (GET_CODE (SET_DEST (real)) != MEM
12403 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12404 || GET_CODE (SET_SRC (real)) != REG)
12408 (set (mem (plus (reg x) (const y)))
12411 (set (mem (plus (reg x) (const y+4)))
12415 real2 = copy_rtx (real);
12416 PUT_MODE (SET_DEST (real2), SImode);
12417 reg = SET_SRC (real2);
12418 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12419 synth = copy_rtx (real2);
12421 if (BYTES_BIG_ENDIAN)
12423 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12424 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12427 reg = SET_SRC (synth);
12429 synth = replace_rtx (synth, reg,
12430 gen_rtx_REG (SImode, REGNO (reg) + 1200));
12432 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12433 synth = replace_rtx (synth, offset,
12434 GEN_INT (INTVAL (offset)
12435 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12437 RTX_FRAME_RELATED_P (synth) = 1;
12438 RTX_FRAME_RELATED_P (real2) = 1;
12439 if (BYTES_BIG_ENDIAN)
12440 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12442 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12447 /* Returns an insn that has a vrsave set operation with the
12448 appropriate CLOBBERs. */
12451 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
12454 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
12455 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12458 = gen_rtx_SET (VOIDmode,
12460 gen_rtx_UNSPEC_VOLATILE (SImode,
12461 gen_rtvec (2, reg, vrsave),
12466 /* We need to clobber the registers in the mask so the scheduler
12467 does not move sets to VRSAVE before sets of AltiVec registers.
12469 However, if the function receives nonlocal gotos, reload will set
12470 all call saved registers live. We will end up with:
12472 (set (reg 999) (mem))
12473 (parallel [ (set (reg vrsave) (unspec blah))
12474 (clobber (reg 999))])
12476 The clobber will cause the store into reg 999 to be dead, and
12477 flow will attempt to delete an epilogue insn. In this case, we
12478 need an unspec use/set of the register. */
12480 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12481 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12483 if (!epiloguep || call_used_regs [i])
12484 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12485 gen_rtx_REG (V4SImode, i));
12488 rtx reg = gen_rtx_REG (V4SImode, i);
12491 = gen_rtx_SET (VOIDmode,
12493 gen_rtx_UNSPEC (V4SImode,
12494 gen_rtvec (1, reg), 27));
12498 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12500 for (i = 0; i < nclobs; ++i)
12501 XVECEXP (insn, 0, i) = clobs[i];
12506 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12507 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12510 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
12511 unsigned int regno, int offset, HOST_WIDE_INT total_size)
12513 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12514 rtx replacea, replaceb;
12516 int_rtx = GEN_INT (offset);
12518 /* Some cases that need register indexed addressing. */
12519 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12520 || (TARGET_E500_DOUBLE && mode == DFmode)
12522 && SPE_VECTOR_MODE (mode)
12523 && !SPE_CONST_OFFSET_OK (offset)))
12525 /* Whomever calls us must make sure r11 is available in the
12526 flow path of instructions in the prologue. */
12527 offset_rtx = gen_rtx_REG (Pmode, 11);
12528 emit_move_insn (offset_rtx, int_rtx);
12530 replacea = offset_rtx;
12531 replaceb = int_rtx;
12535 offset_rtx = int_rtx;
12536 replacea = NULL_RTX;
12537 replaceb = NULL_RTX;
12540 reg = gen_rtx_REG (mode, regno);
12541 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12542 mem = gen_rtx_MEM (mode, addr);
12543 set_mem_alias_set (mem, rs6000_sr_alias_set);
12545 insn = emit_move_insn (mem, reg);
12547 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12550 /* Emit an offset memory reference suitable for a frame store, while
12551 converting to a valid addressing mode. */
12554 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12556 rtx int_rtx, offset_rtx;
12558 int_rtx = GEN_INT (offset);
12560 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12561 || (TARGET_E500_DOUBLE && mode == DFmode))
12563 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12564 emit_move_insn (offset_rtx, int_rtx);
12567 offset_rtx = int_rtx;
12569 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12572 #ifndef TARGET_FIX_AND_CONTINUE
12573 #define TARGET_FIX_AND_CONTINUE 0
12576 /* Emit function prologue as insns. */
12579 rs6000_emit_prologue (void)
12581 rs6000_stack_t *info = rs6000_stack_info ();
12582 enum machine_mode reg_mode = Pmode;
12583 int reg_size = TARGET_32BIT ? 4 : 8;
12584 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12585 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12586 rtx frame_reg_rtx = sp_reg_rtx;
12587 rtx cr_save_rtx = NULL_RTX;
12589 int saving_FPRs_inline;
12590 int using_store_multiple;
12591 HOST_WIDE_INT sp_offset = 0;
12593 if (TARGET_FIX_AND_CONTINUE)
12595 /* gdb on darwin arranges to forward a function from the old
12596 address by modifying the first 4 instructions of the function
12597 to branch to the overriding function. This is necessary to
12598 permit function pointers that point to the old function to
12599 actually forward to the new function. */
12600 emit_insn (gen_nop ());
12601 emit_insn (gen_nop ());
12602 emit_insn (gen_nop ());
12603 emit_insn (gen_nop ());
12606 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12608 reg_mode = V2SImode;
12612 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12613 && (!TARGET_SPE_ABI
12614 || info->spe_64bit_regs_used == 0)
12615 && info->first_gp_reg_save < 31);
12616 saving_FPRs_inline = (info->first_fp_reg_save == 64
12617 || FP_SAVE_INLINE (info->first_fp_reg_save)
12618 || current_function_calls_eh_return
12619 || cfun->machine->ra_need_lr);
12621 /* For V.4, update stack before we do any saving and set back pointer. */
12623 && (DEFAULT_ABI == ABI_V4
12624 || current_function_calls_eh_return))
12626 if (info->total_size < 32767)
12627 sp_offset = info->total_size;
12629 frame_reg_rtx = frame_ptr_rtx;
12630 rs6000_emit_allocate_stack (info->total_size,
12631 (frame_reg_rtx != sp_reg_rtx
12632 && (info->cr_save_p
12634 || info->first_fp_reg_save < 64
12635 || info->first_gp_reg_save < 32
12637 if (frame_reg_rtx != sp_reg_rtx)
12638 rs6000_emit_stack_tie ();
12641 /* Handle world saves specially here. */
12642 if (WORLD_SAVE_P (info))
12648 /* save_world expects lr in r0. */
12649 if (info->lr_save_p)
12651 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12652 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12653 RTX_FRAME_RELATED_P (insn) = 1;
12656 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12657 assumptions about the offsets of various bits of the stack
12658 frame. Abort if things aren't what they should be. */
12659 if (info->gp_save_offset != -220
12660 || info->fp_save_offset != -144
12661 || info->lr_save_offset != 8
12662 || info->cr_save_offset != 4
12664 || !info->lr_save_p
12665 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12666 || (info->vrsave_save_offset != -224
12667 || info->altivec_save_offset != (-224 -16 -192)))
12670 treg = gen_rtx_REG (SImode, 11);
12671 emit_move_insn (treg, GEN_INT (-info->total_size));
12673 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12674 in R11. It also clobbers R12, so beware! */
12676 /* Preserve CR2 for save_world prologues */
12678 sz += 32 - info->first_gp_reg_save;
12679 sz += 64 - info->first_fp_reg_save;
12680 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12681 p = rtvec_alloc (sz);
12683 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
12684 gen_rtx_REG (Pmode,
12685 LINK_REGISTER_REGNUM));
12686 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
12687 gen_rtx_SYMBOL_REF (Pmode,
12689 /* We do floats first so that the instruction pattern matches
12691 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12693 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12694 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12695 GEN_INT (info->fp_save_offset
12696 + sp_offset + 8 * i));
12697 rtx mem = gen_rtx_MEM (DFmode, addr);
12698 set_mem_alias_set (mem, rs6000_sr_alias_set);
12700 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12702 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
12704 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12705 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12706 GEN_INT (info->altivec_save_offset
12707 + sp_offset + 16 * i));
12708 rtx mem = gen_rtx_MEM (V4SImode, addr);
12709 set_mem_alias_set (mem, rs6000_sr_alias_set);
12711 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12713 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12715 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12716 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12717 GEN_INT (info->gp_save_offset
12718 + sp_offset + reg_size * i));
12719 rtx mem = gen_rtx_MEM (reg_mode, addr);
12720 set_mem_alias_set (mem, rs6000_sr_alias_set);
12722 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12726 /* CR register traditionally saved as CR2. */
12727 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12728 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12729 GEN_INT (info->cr_save_offset
12731 rtx mem = gen_rtx_MEM (reg_mode, addr);
12732 set_mem_alias_set (mem, rs6000_sr_alias_set);
12734 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12736 /* Prevent any attempt to delete the setting of r0 and treg! */
12737 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12738 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12739 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12741 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12742 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12743 NULL_RTX, NULL_RTX);
12745 if (current_function_calls_eh_return)
12750 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12751 if (regno == INVALID_REGNUM)
12753 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12754 info->ehrd_offset + sp_offset
12755 + reg_size * (int) i,
12761 /* Save AltiVec registers if needed. */
12762 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12766 /* There should be a non inline version of this, for when we
12767 are saving lots of vector registers. */
12768 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12769 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12771 rtx areg, savereg, mem;
12774 offset = info->altivec_save_offset + sp_offset
12775 + 16 * (i - info->first_altivec_reg_save);
12777 savereg = gen_rtx_REG (V4SImode, i);
12779 areg = gen_rtx_REG (Pmode, 0);
12780 emit_move_insn (areg, GEN_INT (offset));
12782 /* AltiVec addressing mode is [reg+reg]. */
12783 mem = gen_rtx_MEM (V4SImode,
12784 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12786 set_mem_alias_set (mem, rs6000_sr_alias_set);
12788 insn = emit_move_insn (mem, savereg);
12790 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12791 areg, GEN_INT (offset));
12795 /* VRSAVE is a bit vector representing which AltiVec registers
12796 are used. The OS uses this to determine which vector
12797 registers to save on a context switch. We need to save
12798 VRSAVE on the stack frame, add whatever AltiVec registers we
12799 used in this function, and do the corresponding magic in the
12802 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12803 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
12805 rtx reg, mem, vrsave;
12808 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12809 as frame_reg_rtx and r11 as the static chain pointer for
12810 nested functions. */
12811 reg = gen_rtx_REG (SImode, 0);
12812 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12814 emit_insn (gen_get_vrsave_internal (reg));
12816 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12819 offset = info->vrsave_save_offset + sp_offset;
12821 = gen_rtx_MEM (SImode,
12822 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12823 set_mem_alias_set (mem, rs6000_sr_alias_set);
12824 insn = emit_move_insn (mem, reg);
12826 /* Include the registers in the mask. */
12827 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12829 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12832 /* If we use the link register, get it into r0. */
12833 if (!WORLD_SAVE_P (info) && info->lr_save_p)
12835 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12836 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12837 RTX_FRAME_RELATED_P (insn) = 1;
12840 /* If we need to save CR, put it into r12. */
12841 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12845 cr_save_rtx = gen_rtx_REG (SImode, 12);
12846 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12847 RTX_FRAME_RELATED_P (insn) = 1;
12848 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12849 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12850 But that's OK. All we have to do is specify that _one_ condition
12851 code register is saved in this stack slot. The thrower's epilogue
12852 will then restore all the call-saved registers.
12853 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12854 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12855 gen_rtx_REG (SImode, CR2_REGNO));
12856 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12861 /* Do any required saving of fpr's. If only one or two to save, do
12862 it ourselves. Otherwise, call function. */
12863 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
12866 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12867 if ((regs_ever_live[info->first_fp_reg_save+i]
12868 && ! call_used_regs[info->first_fp_reg_save+i]))
12869 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12870 info->first_fp_reg_save + i,
12871 info->fp_save_offset + sp_offset + 8 * i,
12874 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
12878 const char *alloc_rname;
12880 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12882 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12883 gen_rtx_REG (Pmode,
12884 LINK_REGISTER_REGNUM));
12885 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12886 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12887 alloc_rname = ggc_strdup (rname);
12888 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12889 gen_rtx_SYMBOL_REF (Pmode,
12891 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12893 rtx addr, reg, mem;
12894 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12895 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12896 GEN_INT (info->fp_save_offset
12897 + sp_offset + 8*i));
12898 mem = gen_rtx_MEM (DFmode, addr);
12899 set_mem_alias_set (mem, rs6000_sr_alias_set);
12901 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12903 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12904 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12905 NULL_RTX, NULL_RTX);
12908 /* Save GPRs. This is done as a PARALLEL if we are using
12909 the store-multiple instructions. */
12910 if (!WORLD_SAVE_P (info) && using_store_multiple)
12914 p = rtvec_alloc (32 - info->first_gp_reg_save);
12915 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12917 rtx addr, reg, mem;
12918 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12919 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12920 GEN_INT (info->gp_save_offset
12923 mem = gen_rtx_MEM (reg_mode, addr);
12924 set_mem_alias_set (mem, rs6000_sr_alias_set);
12926 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12928 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12929 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12930 NULL_RTX, NULL_RTX);
12932 else if (!WORLD_SAVE_P (info))
12935 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12936 if ((regs_ever_live[info->first_gp_reg_save+i]
12937 && (! call_used_regs[info->first_gp_reg_save+i]
12938 || (i+info->first_gp_reg_save
12939 == RS6000_PIC_OFFSET_TABLE_REGNUM
12940 && TARGET_TOC && TARGET_MINIMAL_TOC)))
12941 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12942 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12943 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12945 rtx addr, reg, mem;
12946 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12948 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12950 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12953 if (!SPE_CONST_OFFSET_OK (offset))
12955 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12956 emit_move_insn (b, GEN_INT (offset));
12959 b = GEN_INT (offset);
12961 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12962 mem = gen_rtx_MEM (V2SImode, addr);
12963 set_mem_alias_set (mem, rs6000_sr_alias_set);
12964 insn = emit_move_insn (mem, reg);
12966 if (GET_CODE (b) == CONST_INT)
12967 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12968 NULL_RTX, NULL_RTX);
12970 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12971 b, GEN_INT (offset));
12975 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12976 GEN_INT (info->gp_save_offset
12979 mem = gen_rtx_MEM (reg_mode, addr);
12980 set_mem_alias_set (mem, rs6000_sr_alias_set);
12982 insn = emit_move_insn (mem, reg);
12983 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12984 NULL_RTX, NULL_RTX);
12989 /* ??? There's no need to emit actual instructions here, but it's the
12990 easiest way to get the frame unwind information emitted. */
12991 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
12993 unsigned int i, regno;
12995 /* In AIX ABI we need to pretend we save r2 here. */
12998 rtx addr, reg, mem;
13000 reg = gen_rtx_REG (reg_mode, 2);
13001 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13002 GEN_INT (sp_offset + 5 * reg_size));
13003 mem = gen_rtx_MEM (reg_mode, addr);
13004 set_mem_alias_set (mem, rs6000_sr_alias_set);
13006 insn = emit_move_insn (mem, reg);
13007 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13008 NULL_RTX, NULL_RTX);
13009 PATTERN (insn) = gen_blockage ();
13014 regno = EH_RETURN_DATA_REGNO (i);
13015 if (regno == INVALID_REGNUM)
13018 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13019 info->ehrd_offset + sp_offset
13020 + reg_size * (int) i,
13025 /* Save lr if we used it. */
13026 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13028 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13029 GEN_INT (info->lr_save_offset + sp_offset));
13030 rtx reg = gen_rtx_REG (Pmode, 0);
13031 rtx mem = gen_rtx_MEM (Pmode, addr);
13032 /* This should not be of rs6000_sr_alias_set, because of
13033 __builtin_return_address. */
13035 insn = emit_move_insn (mem, reg);
13036 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13037 NULL_RTX, NULL_RTX);
13040 /* Save CR if we use any that must be preserved. */
13041 if (!WORLD_SAVE_P (info) && info->cr_save_p)
13043 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13044 GEN_INT (info->cr_save_offset + sp_offset));
13045 rtx mem = gen_rtx_MEM (SImode, addr);
13046 /* See the large comment above about why CR2_REGNO is used. */
13047 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13049 set_mem_alias_set (mem, rs6000_sr_alias_set);
13051 /* If r12 was used to hold the original sp, copy cr into r0 now
13053 if (REGNO (frame_reg_rtx) == 12)
13057 cr_save_rtx = gen_rtx_REG (SImode, 0);
13058 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13059 RTX_FRAME_RELATED_P (insn) = 1;
13060 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13061 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13066 insn = emit_move_insn (mem, cr_save_rtx);
13068 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13069 NULL_RTX, NULL_RTX);
13072 /* Update stack and set back pointer unless this is V.4,
13073 for which it was done previously. */
13074 if (!WORLD_SAVE_P (info) && info->push_p
13075 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13076 rs6000_emit_allocate_stack (info->total_size, FALSE);
13078 /* Set frame pointer, if needed. */
13079 if (frame_pointer_needed)
13081 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13083 RTX_FRAME_RELATED_P (insn) = 1;
13086 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13087 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13088 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13089 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13091 /* If emit_load_toc_table will use the link register, we need to save
13092 it. We use R12 for this purpose because emit_load_toc_table
13093 can use register 0. This allows us to use a plain 'blr' to return
13094 from the procedure more often. */
13095 int save_LR_around_toc_setup = (TARGET_ELF
13096 && DEFAULT_ABI != ABI_AIX
13098 && ! info->lr_save_p
13099 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13100 if (save_LR_around_toc_setup)
13102 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13104 insn = emit_move_insn (frame_ptr_rtx, lr);
13105 rs6000_maybe_dead (insn);
13106 RTX_FRAME_RELATED_P (insn) = 1;
13108 rs6000_emit_load_toc_table (TRUE);
13110 insn = emit_move_insn (lr, frame_ptr_rtx);
13111 rs6000_maybe_dead (insn);
13112 RTX_FRAME_RELATED_P (insn) = 1;
13115 rs6000_emit_load_toc_table (TRUE);
13119 if (DEFAULT_ABI == ABI_DARWIN
13120 && flag_pic && current_function_uses_pic_offset_table)
13122 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13123 rtx src = machopic_function_base_sym ();
13125 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13127 insn = emit_move_insn (gen_rtx_REG (Pmode,
13128 RS6000_PIC_OFFSET_TABLE_REGNUM),
13130 rs6000_maybe_dead (insn);
13135 /* Write function prologue. */
13138 rs6000_output_function_prologue (FILE *file,
13139 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13141 rs6000_stack_t *info = rs6000_stack_info ();
13143 if (TARGET_DEBUG_STACK)
13144 debug_stack_info (info);
13146 /* Write .extern for any function we will call to save and restore
13148 if (info->first_fp_reg_save < 64
13149 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13150 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13151 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13152 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13153 RESTORE_FP_SUFFIX);
13155 /* Write .extern for AIX common mode routines, if needed. */
13156 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13158 fputs ("\t.extern __mulh\n", file);
13159 fputs ("\t.extern __mull\n", file);
13160 fputs ("\t.extern __divss\n", file);
13161 fputs ("\t.extern __divus\n", file);
13162 fputs ("\t.extern __quoss\n", file);
13163 fputs ("\t.extern __quous\n", file);
13164 common_mode_defined = 1;
13167 if (! HAVE_prologue)
13171 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13172 the "toplevel" insn chain. */
13173 emit_note (NOTE_INSN_DELETED);
13174 rs6000_emit_prologue ();
13175 emit_note (NOTE_INSN_DELETED);
13177 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13181 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13183 INSN_ADDRESSES_NEW (insn, addr);
13188 if (TARGET_DEBUG_STACK)
13189 debug_rtx_list (get_insns (), 100);
13190 final (get_insns (), file, FALSE, FALSE);
13194 rs6000_pic_labelno++;
13197 /* Emit function epilogue as insns.
13199 At present, dwarf2out_frame_debug_expr doesn't understand
13200 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13201 anywhere in the epilogue. Most of the insns below would in any case
13202 need special notes to explain where r11 is in relation to the stack. */
13205 rs6000_emit_epilogue (int sibcall)
13207 rs6000_stack_t *info;
13208 int restoring_FPRs_inline;
13209 int using_load_multiple;
13210 int using_mfcr_multiple;
13211 int use_backchain_to_restore_sp;
13213 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13214 rtx frame_reg_rtx = sp_reg_rtx;
13215 enum machine_mode reg_mode = Pmode;
13216 int reg_size = TARGET_32BIT ? 4 : 8;
13219 info = rs6000_stack_info ();
13221 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13223 reg_mode = V2SImode;
13227 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13228 && (!TARGET_SPE_ABI
13229 || info->spe_64bit_regs_used == 0)
13230 && info->first_gp_reg_save < 31);
13231 restoring_FPRs_inline = (sibcall
13232 || current_function_calls_eh_return
13233 || info->first_fp_reg_save == 64
13234 || FP_SAVE_INLINE (info->first_fp_reg_save));
13235 use_backchain_to_restore_sp = (frame_pointer_needed
13236 || current_function_calls_alloca
13237 || info->total_size > 32767);
13238 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13239 || rs6000_cpu == PROCESSOR_PPC603
13240 || rs6000_cpu == PROCESSOR_PPC750
13243 if (WORLD_SAVE_P (info))
13247 const char *alloc_rname;
13250 /* eh_rest_world_r10 will return to the location saved in the LR
13251 stack slot (which is not likely to be our caller.)
13252 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13253 rest_world is similar, except any R10 parameter is ignored.
13254 The exception-handling stuff that was here in 2.95 is no
13255 longer necessary. */
13259 + 32 - info->first_gp_reg_save
13260 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13261 + 63 + 1 - info->first_fp_reg_save);
13263 strcpy (rname, ((current_function_calls_eh_return) ?
13264 "*eh_rest_world_r10" : "*rest_world"));
13265 alloc_rname = ggc_strdup (rname);
13268 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13269 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13270 gen_rtx_REG (Pmode,
13271 LINK_REGISTER_REGNUM));
13273 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13274 /* The instruction pattern requires a clobber here;
13275 it is shared with the restVEC helper. */
13277 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
13280 /* CR register traditionally saved as CR2. */
13281 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13282 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13283 GEN_INT (info->cr_save_offset));
13284 rtx mem = gen_rtx_MEM (reg_mode, addr);
13285 set_mem_alias_set (mem, rs6000_sr_alias_set);
13287 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13290 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13292 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13293 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13294 GEN_INT (info->gp_save_offset
13296 rtx mem = gen_rtx_MEM (reg_mode, addr);
13297 set_mem_alias_set (mem, rs6000_sr_alias_set);
13299 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13301 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13303 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13304 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13305 GEN_INT (info->altivec_save_offset
13307 rtx mem = gen_rtx_MEM (V4SImode, addr);
13308 set_mem_alias_set (mem, rs6000_sr_alias_set);
13310 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13312 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
13314 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13315 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13316 GEN_INT (info->fp_save_offset
13318 rtx mem = gen_rtx_MEM (DFmode, addr);
13319 set_mem_alias_set (mem, rs6000_sr_alias_set);
13321 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13324 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
13326 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
13328 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
13330 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
13332 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
13333 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13338 /* If we have a frame pointer, a call to alloca, or a large stack
13339 frame, restore the old stack pointer using the backchain. Otherwise,
13340 we know what size to update it with. */
13341 if (use_backchain_to_restore_sp)
13343 /* Under V.4, don't reset the stack pointer until after we're done
13344 loading the saved registers. */
13345 if (DEFAULT_ABI == ABI_V4)
13346 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
13348 emit_move_insn (frame_reg_rtx,
13349 gen_rtx_MEM (Pmode, sp_reg_rtx));
13352 else if (info->push_p)
13354 if (DEFAULT_ABI == ABI_V4
13355 || current_function_calls_eh_return)
13356 sp_offset = info->total_size;
13359 emit_insn (TARGET_32BIT
13360 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13361 GEN_INT (info->total_size))
13362 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13363 GEN_INT (info->total_size)));
13367 /* Restore AltiVec registers if needed. */
13368 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13372 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13373 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13375 rtx addr, areg, mem;
13377 areg = gen_rtx_REG (Pmode, 0);
13379 (areg, GEN_INT (info->altivec_save_offset
13381 + 16 * (i - info->first_altivec_reg_save)));
13383 /* AltiVec addressing mode is [reg+reg]. */
13384 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13385 mem = gen_rtx_MEM (V4SImode, addr);
13386 set_mem_alias_set (mem, rs6000_sr_alias_set);
13388 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13392 /* Restore VRSAVE if needed. */
13393 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13394 && info->vrsave_mask != 0)
13396 rtx addr, mem, reg;
13398 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13399 GEN_INT (info->vrsave_save_offset + sp_offset));
13400 mem = gen_rtx_MEM (SImode, addr);
13401 set_mem_alias_set (mem, rs6000_sr_alias_set);
13402 reg = gen_rtx_REG (SImode, 12);
13403 emit_move_insn (reg, mem);
13405 emit_insn (generate_set_vrsave (reg, info, 1));
13408 /* Get the old lr if we saved it. */
13409 if (info->lr_save_p)
13411 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13412 info->lr_save_offset + sp_offset);
13414 set_mem_alias_set (mem, rs6000_sr_alias_set);
13416 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
13419 /* Get the old cr if we saved it. */
13420 if (info->cr_save_p)
13422 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13423 GEN_INT (info->cr_save_offset + sp_offset));
13424 rtx mem = gen_rtx_MEM (SImode, addr);
13426 set_mem_alias_set (mem, rs6000_sr_alias_set);
13428 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13431 /* Set LR here to try to overlap restores below. */
13432 if (info->lr_save_p)
13433 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13434 gen_rtx_REG (Pmode, 0));
13436 /* Load exception handler data registers, if needed. */
13437 if (current_function_calls_eh_return)
13439 unsigned int i, regno;
13443 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13444 GEN_INT (sp_offset + 5 * reg_size));
13445 rtx mem = gen_rtx_MEM (reg_mode, addr);
13447 set_mem_alias_set (mem, rs6000_sr_alias_set);
13449 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13456 regno = EH_RETURN_DATA_REGNO (i);
13457 if (regno == INVALID_REGNUM)
13460 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13461 info->ehrd_offset + sp_offset
13462 + reg_size * (int) i);
13463 set_mem_alias_set (mem, rs6000_sr_alias_set);
13465 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13469 /* Restore GPRs. This is done as a PARALLEL if we are using
13470 the load-multiple instructions. */
13471 if (using_load_multiple)
13474 p = rtvec_alloc (32 - info->first_gp_reg_save);
13475 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13477 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13478 GEN_INT (info->gp_save_offset
13481 rtx mem = gen_rtx_MEM (reg_mode, addr);
13483 set_mem_alias_set (mem, rs6000_sr_alias_set);
13486 gen_rtx_SET (VOIDmode,
13487 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13490 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13493 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13494 if ((regs_ever_live[info->first_gp_reg_save+i]
13495 && (! call_used_regs[info->first_gp_reg_save+i]
13496 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13497 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13498 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13499 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13500 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13502 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13503 GEN_INT (info->gp_save_offset
13506 rtx mem = gen_rtx_MEM (reg_mode, addr);
13508 /* Restore 64-bit quantities for SPE. */
13509 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13511 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13514 if (!SPE_CONST_OFFSET_OK (offset))
13516 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13517 emit_move_insn (b, GEN_INT (offset));
13520 b = GEN_INT (offset);
13522 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13523 mem = gen_rtx_MEM (V2SImode, addr);
13526 set_mem_alias_set (mem, rs6000_sr_alias_set);
13528 emit_move_insn (gen_rtx_REG (reg_mode,
13529 info->first_gp_reg_save + i), mem);
13532 /* Restore fpr's if we need to do it without calling a function. */
13533 if (restoring_FPRs_inline)
13534 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13535 if ((regs_ever_live[info->first_fp_reg_save+i]
13536 && ! call_used_regs[info->first_fp_reg_save+i]))
13539 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13540 GEN_INT (info->fp_save_offset
13543 mem = gen_rtx_MEM (DFmode, addr);
13544 set_mem_alias_set (mem, rs6000_sr_alias_set);
13546 emit_move_insn (gen_rtx_REG (DFmode,
13547 info->first_fp_reg_save + i),
13551 /* If we saved cr, restore it here. Just those that were used. */
13552 if (info->cr_save_p)
13554 rtx r12_rtx = gen_rtx_REG (SImode, 12);
13557 if (using_mfcr_multiple)
13559 for (i = 0; i < 8; i++)
13560 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13566 if (using_mfcr_multiple && count > 1)
13571 p = rtvec_alloc (count);
13574 for (i = 0; i < 8; i++)
13575 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13577 rtvec r = rtvec_alloc (2);
13578 RTVEC_ELT (r, 0) = r12_rtx;
13579 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
13580 RTVEC_ELT (p, ndx) =
13581 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
13582 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
13585 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13590 for (i = 0; i < 8; i++)
13591 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13593 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
13599 /* If this is V.4, unwind the stack pointer after all of the loads
13600 have been done. We need to emit a block here so that sched
13601 doesn't decide to move the sp change before the register restores
13602 (which may not have any obvious dependency on the stack). This
13603 doesn't hurt performance, because there is no scheduling that can
13604 be done after this point. */
13605 if (DEFAULT_ABI == ABI_V4
13606 || current_function_calls_eh_return)
13608 if (frame_reg_rtx != sp_reg_rtx)
13609 rs6000_emit_stack_tie ();
13611 if (use_backchain_to_restore_sp)
13613 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
13615 else if (sp_offset != 0)
13617 emit_insn (TARGET_32BIT
13618 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13619 GEN_INT (sp_offset))
13620 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13621 GEN_INT (sp_offset)));
13625 if (current_function_calls_eh_return)
13627 rtx sa = EH_RETURN_STACKADJ_RTX;
13628 emit_insn (TARGET_32BIT
13629 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13630 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13636 if (! restoring_FPRs_inline)
13637 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13639 p = rtvec_alloc (2);
13641 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
13642 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13643 gen_rtx_REG (Pmode,
13644 LINK_REGISTER_REGNUM));
13646 /* If we have to restore more than two FP registers, branch to the
13647 restore function. It will return to our caller. */
13648 if (! restoring_FPRs_inline)
13652 const char *alloc_rname;
13654 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
13655 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
13656 alloc_rname = ggc_strdup (rname);
13657 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13658 gen_rtx_SYMBOL_REF (Pmode,
13661 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13664 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13665 GEN_INT (info->fp_save_offset + 8*i));
13666 mem = gen_rtx_MEM (DFmode, addr);
13667 set_mem_alias_set (mem, rs6000_sr_alias_set);
13669 RTVEC_ELT (p, i+3) =
13670 gen_rtx_SET (VOIDmode,
13671 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13676 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13680 /* Write function epilogue. */
13683 rs6000_output_function_epilogue (FILE *file,
13684 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13686 rs6000_stack_t *info = rs6000_stack_info ();
13688 if (! HAVE_epilogue)
13690 rtx insn = get_last_insn ();
13691 /* If the last insn was a BARRIER, we don't have to write anything except
13692 the trace table. */
13693 if (GET_CODE (insn) == NOTE)
13694 insn = prev_nonnote_insn (insn);
13695 if (insn == 0 || GET_CODE (insn) != BARRIER)
13697 /* This is slightly ugly, but at least we don't have two
13698 copies of the epilogue-emitting code. */
13701 /* A NOTE_INSN_DELETED is supposed to be at the start
13702 and end of the "toplevel" insn chain. */
13703 emit_note (NOTE_INSN_DELETED);
13704 rs6000_emit_epilogue (FALSE);
13705 emit_note (NOTE_INSN_DELETED);
13707 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13711 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13713 INSN_ADDRESSES_NEW (insn, addr);
13718 if (TARGET_DEBUG_STACK)
13719 debug_rtx_list (get_insns (), 100);
13720 final (get_insns (), file, FALSE, FALSE);
13726 macho_branch_islands ();
13727 /* Mach-O doesn't support labels at the end of objects, so if
13728 it looks like we might want one, insert a NOP. */
13730 rtx insn = get_last_insn ();
13733 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13734 insn = PREV_INSN (insn);
13738 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13739 fputs ("\tnop\n", file);
13743 /* Output a traceback table here. See /usr/include/sys/debug.h for info
13746 We don't output a traceback table if -finhibit-size-directive was
13747 used. The documentation for -finhibit-size-directive reads
13748 ``don't output a @code{.size} assembler directive, or anything
13749 else that would cause trouble if the function is split in the
13750 middle, and the two halves are placed at locations far apart in
13751 memory.'' The traceback table has this property, since it
13752 includes the offset from the start of the function to the
13753 traceback table itself.
13755 System V.4 Powerpc's (and the embedded ABI derived from it) use a
13756 different traceback table. */
13757 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13758 && rs6000_traceback != traceback_none)
13760 const char *fname = NULL;
13761 const char *language_string = lang_hooks.name;
13762 int fixed_parms = 0, float_parms = 0, parm_info = 0;
13764 int optional_tbtab;
13766 if (rs6000_traceback == traceback_full)
13767 optional_tbtab = 1;
13768 else if (rs6000_traceback == traceback_part)
13769 optional_tbtab = 0;
13771 optional_tbtab = !optimize_size && !TARGET_ELF;
13773 if (optional_tbtab)
13775 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13776 while (*fname == '.') /* V.4 encodes . in the name */
13779 /* Need label immediately before tbtab, so we can compute
13780 its offset from the function start. */
13781 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13782 ASM_OUTPUT_LABEL (file, fname);
13785 /* The .tbtab pseudo-op can only be used for the first eight
13786 expressions, since it can't handle the possibly variable
13787 length fields that follow. However, if you omit the optional
13788 fields, the assembler outputs zeros for all optional fields
13789 anyways, giving each variable length field is minimum length
13790 (as defined in sys/debug.h). Thus we can not use the .tbtab
13791 pseudo-op at all. */
13793 /* An all-zero word flags the start of the tbtab, for debuggers
13794 that have to find it by searching forward from the entry
13795 point or from the current pc. */
13796 fputs ("\t.long 0\n", file);
13798 /* Tbtab format type. Use format type 0. */
13799 fputs ("\t.byte 0,", file);
13801 /* Language type. Unfortunately, there does not seem to be any
13802 official way to discover the language being compiled, so we
13803 use language_string.
13804 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13805 Java is 13. Objective-C is 14. */
13806 if (! strcmp (language_string, "GNU C"))
13808 else if (! strcmp (language_string, "GNU F77")
13809 || ! strcmp (language_string, "GNU F95"))
13811 else if (! strcmp (language_string, "GNU Pascal"))
13813 else if (! strcmp (language_string, "GNU Ada"))
13815 else if (! strcmp (language_string, "GNU C++"))
13817 else if (! strcmp (language_string, "GNU Java"))
13819 else if (! strcmp (language_string, "GNU Objective-C"))
13823 fprintf (file, "%d,", i);
13825 /* 8 single bit fields: global linkage (not set for C extern linkage,
13826 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13827 from start of procedure stored in tbtab, internal function, function
13828 has controlled storage, function has no toc, function uses fp,
13829 function logs/aborts fp operations. */
13830 /* Assume that fp operations are used if any fp reg must be saved. */
13831 fprintf (file, "%d,",
13832 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
13834 /* 6 bitfields: function is interrupt handler, name present in
13835 proc table, function calls alloca, on condition directives
13836 (controls stack walks, 3 bits), saves condition reg, saves
13838 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13839 set up as a frame pointer, even when there is no alloca call. */
13840 fprintf (file, "%d,",
13841 ((optional_tbtab << 6)
13842 | ((optional_tbtab & frame_pointer_needed) << 5)
13843 | (info->cr_save_p << 1)
13844 | (info->lr_save_p)));
13846 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
13848 fprintf (file, "%d,",
13849 (info->push_p << 7) | (64 - info->first_fp_reg_save));
13851 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13852 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13854 if (optional_tbtab)
13856 /* Compute the parameter info from the function decl argument
13859 int next_parm_info_bit = 31;
13861 for (decl = DECL_ARGUMENTS (current_function_decl);
13862 decl; decl = TREE_CHAIN (decl))
13864 rtx parameter = DECL_INCOMING_RTL (decl);
13865 enum machine_mode mode = GET_MODE (parameter);
13867 if (GET_CODE (parameter) == REG)
13869 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13875 if (mode == SFmode)
13877 else if (mode == DFmode || mode == TFmode)
13882 /* If only one bit will fit, don't or in this entry. */
13883 if (next_parm_info_bit > 0)
13884 parm_info |= (bits << (next_parm_info_bit - 1));
13885 next_parm_info_bit -= 2;
13889 fixed_parms += ((GET_MODE_SIZE (mode)
13890 + (UNITS_PER_WORD - 1))
13892 next_parm_info_bit -= 1;
13898 /* Number of fixed point parameters. */
13899 /* This is actually the number of words of fixed point parameters; thus
13900 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13901 fprintf (file, "%d,", fixed_parms);
13903 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13905 /* This is actually the number of fp registers that hold parameters;
13906 and thus the maximum value is 13. */
13907 /* Set parameters on stack bit if parameters are not in their original
13908 registers, regardless of whether they are on the stack? Xlc
13909 seems to set the bit when not optimizing. */
13910 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13912 if (! optional_tbtab)
13915 /* Optional fields follow. Some are variable length. */
13917 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13918 11 double float. */
13919 /* There is an entry for each parameter in a register, in the order that
13920 they occur in the parameter list. Any intervening arguments on the
13921 stack are ignored. If the list overflows a long (max possible length
13922 34 bits) then completely leave off all elements that don't fit. */
13923 /* Only emit this long if there was at least one parameter. */
13924 if (fixed_parms || float_parms)
13925 fprintf (file, "\t.long %d\n", parm_info);
13927 /* Offset from start of code to tb table. */
13928 fputs ("\t.long ", file);
13929 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13931 RS6000_OUTPUT_BASENAME (file, fname);
13933 assemble_name (file, fname);
13935 rs6000_output_function_entry (file, fname);
13938 /* Interrupt handler mask. */
13939 /* Omit this long, since we never set the interrupt handler bit
13942 /* Number of CTL (controlled storage) anchors. */
13943 /* Omit this long, since the has_ctl bit is never set above. */
13945 /* Displacement into stack of each CTL anchor. */
13946 /* Omit this list of longs, because there are no CTL anchors. */
13948 /* Length of function name. */
13951 fprintf (file, "\t.short %d\n", (int) strlen (fname));
13953 /* Function name. */
13954 assemble_string (fname, strlen (fname));
13956 /* Register for alloca automatic storage; this is always reg 31.
13957 Only emit this if the alloca bit was set above. */
13958 if (frame_pointer_needed)
13959 fputs ("\t.byte 31\n", file);
13961 fputs ("\t.align 2\n", file);
13965 /* A C compound statement that outputs the assembler code for a thunk
13966 function, used to implement C++ virtual function calls with
13967 multiple inheritance. The thunk acts as a wrapper around a virtual
13968 function, adjusting the implicit object parameter before handing
13969 control off to the real function.
13971 First, emit code to add the integer DELTA to the location that
13972 contains the incoming first argument. Assume that this argument
13973 contains a pointer, and is the one used to pass the `this' pointer
13974 in C++. This is the incoming argument *before* the function
13975 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13976 values of all other incoming arguments.
13978 After the addition, emit code to jump to FUNCTION, which is a
13979 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13980 not touch the return address. Hence returning from FUNCTION will
13981 return to whoever called the current `thunk'.
13983 The effect must be as if FUNCTION had been called directly with the
13984 adjusted first argument. This macro is responsible for emitting
13985 all of the code for a thunk function; output_function_prologue()
13986 and output_function_epilogue() are not invoked.
13988 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13989 been extracted from it.) It might possibly be useful on some
13990 targets, but probably not.
13992 If you do not define this macro, the target-independent code in the
13993 C++ frontend will generate a less efficient heavyweight thunk that
13994 calls FUNCTION instead of jumping to it. The generic approach does
13995 not support varargs. */
13998 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13999 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14002 rtx this, insn, funexp;
14004 reload_completed = 1;
14005 epilogue_completed = 1;
14006 no_new_pseudos = 1;
14007 reset_block_changes ();
14009 /* Mark the end of the (empty) prologue. */
14010 emit_note (NOTE_INSN_PROLOGUE_END);
14012 /* Find the "this" pointer. If the function returns a structure,
14013 the structure return pointer is in r3. */
14014 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14015 this = gen_rtx_REG (Pmode, 4);
14017 this = gen_rtx_REG (Pmode, 3);
14019 /* Apply the constant offset, if required. */
14022 rtx delta_rtx = GEN_INT (delta);
14023 emit_insn (TARGET_32BIT
14024 ? gen_addsi3 (this, this, delta_rtx)
14025 : gen_adddi3 (this, this, delta_rtx));
14028 /* Apply the offset from the vtable, if required. */
14031 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14032 rtx tmp = gen_rtx_REG (Pmode, 12);
14034 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14035 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14037 emit_insn (TARGET_32BIT
14038 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14039 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14040 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14044 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14046 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14048 emit_insn (TARGET_32BIT
14049 ? gen_addsi3 (this, this, tmp)
14050 : gen_adddi3 (this, this, tmp));
14053 /* Generate a tail call to the target function. */
14054 if (!TREE_USED (function))
14056 assemble_external (function);
14057 TREE_USED (function) = 1;
14059 funexp = XEXP (DECL_RTL (function), 0);
14060 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14063 if (MACHOPIC_INDIRECT)
14064 funexp = machopic_indirect_call_target (funexp);
14067 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14068 generate sibcall RTL explicitly to avoid constraint abort. */
14069 insn = emit_call_insn (
14070 gen_rtx_PARALLEL (VOIDmode,
14072 gen_rtx_CALL (VOIDmode,
14073 funexp, const0_rtx),
14074 gen_rtx_USE (VOIDmode, const0_rtx),
14075 gen_rtx_USE (VOIDmode,
14076 gen_rtx_REG (SImode,
14077 LINK_REGISTER_REGNUM)),
14078 gen_rtx_RETURN (VOIDmode))));
14079 SIBLING_CALL_P (insn) = 1;
14082 /* Run just enough of rest_of_compilation to get the insns emitted.
14083 There's not really enough bulk here to make other passes such as
14084 instruction scheduling worth while. Note that use_thunk calls
14085 assemble_start_function and assemble_end_function. */
14086 insn = get_insns ();
14087 insn_locators_initialize ();
14088 shorten_branches (insn);
14089 final_start_function (insn, file, 1);
14090 final (insn, file, 1, 0);
14091 final_end_function ();
14093 reload_completed = 0;
14094 epilogue_completed = 0;
14095 no_new_pseudos = 0;
14098 /* A quick summary of the various types of 'constant-pool tables'
14101 Target Flags Name One table per
14102 AIX (none) AIX TOC object file
14103 AIX -mfull-toc AIX TOC object file
14104 AIX -mminimal-toc AIX minimal TOC translation unit
14105 SVR4/EABI (none) SVR4 SDATA object file
14106 SVR4/EABI -fpic SVR4 pic object file
14107 SVR4/EABI -fPIC SVR4 PIC translation unit
14108 SVR4/EABI -mrelocatable EABI TOC function
14109 SVR4/EABI -maix AIX TOC object file
14110 SVR4/EABI -maix -mminimal-toc
14111 AIX minimal TOC translation unit
14113 Name Reg. Set by entries contains:
14114 made by addrs? fp? sum?
14116 AIX TOC 2 crt0 as Y option option
14117 AIX minimal TOC 30 prolog gcc Y Y option
14118 SVR4 SDATA 13 crt0 gcc N Y N
14119 SVR4 pic 30 prolog ld Y not yet N
14120 SVR4 PIC 30 prolog gcc Y option option
14121 EABI TOC 30 prolog gcc Y option option
14125 /* Hash functions for the hash table. */
14128 rs6000_hash_constant (rtx k)
14130 enum rtx_code code = GET_CODE (k);
14131 enum machine_mode mode = GET_MODE (k);
14132 unsigned result = (code << 3) ^ mode;
14133 const char *format;
14136 format = GET_RTX_FORMAT (code);
14137 flen = strlen (format);
14143 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14146 if (mode != VOIDmode)
14147 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14159 for (; fidx < flen; fidx++)
14160 switch (format[fidx])
14165 const char *str = XSTR (k, fidx);
14166 len = strlen (str);
14167 result = result * 613 + len;
14168 for (i = 0; i < len; i++)
14169 result = result * 613 + (unsigned) str[i];
14174 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14178 result = result * 613 + (unsigned) XINT (k, fidx);
14181 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14182 result = result * 613 + (unsigned) XWINT (k, fidx);
14186 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
14187 result = result * 613 + (unsigned) (XWINT (k, fidx)
14201 toc_hash_function (const void *hash_entry)
14203 const struct toc_hash_struct *thc =
14204 (const struct toc_hash_struct *) hash_entry;
14205 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14208 /* Compare H1 and H2 for equivalence. */
14211 toc_hash_eq (const void *h1, const void *h2)
14213 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14214 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14216 if (((const struct toc_hash_struct *) h1)->key_mode
14217 != ((const struct toc_hash_struct *) h2)->key_mode)
14220 return rtx_equal_p (r1, r2);
14223 /* These are the names given by the C++ front-end to vtables, and
14224 vtable-like objects. Ideally, this logic should not be here;
14225 instead, there should be some programmatic way of inquiring as
14226 to whether or not an object is a vtable. */
14228 #define VTABLE_NAME_P(NAME) \
14229 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
14230 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14231 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14232 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14233 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14236 rs6000_output_symbol_ref (FILE *file, rtx x)
14238 /* Currently C++ toc references to vtables can be emitted before it
14239 is decided whether the vtable is public or private. If this is
14240 the case, then the linker will eventually complain that there is
14241 a reference to an unknown section. Thus, for vtables only,
14242 we emit the TOC reference to reference the symbol and not the
14244 const char *name = XSTR (x, 0);
14246 if (VTABLE_NAME_P (name))
14248 RS6000_OUTPUT_BASENAME (file, name);
14251 assemble_name (file, name);
14254 /* Output a TOC entry. We derive the entry name from what is being
14258 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14261 const char *name = buf;
14262 const char *real_name;
14269 /* When the linker won't eliminate them, don't output duplicate
14270 TOC entries (this happens on AIX if there is any kind of TOC,
14271 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14273 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
14275 struct toc_hash_struct *h;
14278 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14279 time because GGC is not initialized at that point. */
14280 if (toc_hash_table == NULL)
14281 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
14282 toc_hash_eq, NULL);
14284 h = ggc_alloc (sizeof (*h));
14286 h->key_mode = mode;
14287 h->labelno = labelno;
14289 found = htab_find_slot (toc_hash_table, h, 1);
14290 if (*found == NULL)
14292 else /* This is indeed a duplicate.
14293 Set this label equal to that label. */
14295 fputs ("\t.set ", file);
14296 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14297 fprintf (file, "%d,", labelno);
14298 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14299 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
14305 /* If we're going to put a double constant in the TOC, make sure it's
14306 aligned properly when strict alignment is on. */
14307 if (GET_CODE (x) == CONST_DOUBLE
14308 && STRICT_ALIGNMENT
14309 && GET_MODE_BITSIZE (mode) >= 64
14310 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14311 ASM_OUTPUT_ALIGN (file, 3);
14314 (*targetm.asm_out.internal_label) (file, "LC", labelno);
14316 /* Handle FP constants specially. Note that if we have a minimal
14317 TOC, things we put here aren't actually in the TOC, so we can allow
14319 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14321 REAL_VALUE_TYPE rv;
14324 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14325 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14329 if (TARGET_MINIMAL_TOC)
14330 fputs (DOUBLE_INT_ASM_OP, file);
14332 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14333 k[0] & 0xffffffff, k[1] & 0xffffffff,
14334 k[2] & 0xffffffff, k[3] & 0xffffffff);
14335 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14336 k[0] & 0xffffffff, k[1] & 0xffffffff,
14337 k[2] & 0xffffffff, k[3] & 0xffffffff);
14342 if (TARGET_MINIMAL_TOC)
14343 fputs ("\t.long ", file);
14345 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14346 k[0] & 0xffffffff, k[1] & 0xffffffff,
14347 k[2] & 0xffffffff, k[3] & 0xffffffff);
14348 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14349 k[0] & 0xffffffff, k[1] & 0xffffffff,
14350 k[2] & 0xffffffff, k[3] & 0xffffffff);
14354 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14356 REAL_VALUE_TYPE rv;
14359 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14360 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
14364 if (TARGET_MINIMAL_TOC)
14365 fputs (DOUBLE_INT_ASM_OP, file);
14367 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14368 k[0] & 0xffffffff, k[1] & 0xffffffff);
14369 fprintf (file, "0x%lx%08lx\n",
14370 k[0] & 0xffffffff, k[1] & 0xffffffff);
14375 if (TARGET_MINIMAL_TOC)
14376 fputs ("\t.long ", file);
14378 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14379 k[0] & 0xffffffff, k[1] & 0xffffffff);
14380 fprintf (file, "0x%lx,0x%lx\n",
14381 k[0] & 0xffffffff, k[1] & 0xffffffff);
14385 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14387 REAL_VALUE_TYPE rv;
14390 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14391 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14395 if (TARGET_MINIMAL_TOC)
14396 fputs (DOUBLE_INT_ASM_OP, file);
14398 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14399 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
14404 if (TARGET_MINIMAL_TOC)
14405 fputs ("\t.long ", file);
14407 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14408 fprintf (file, "0x%lx\n", l & 0xffffffff);
14412 else if (GET_MODE (x) == VOIDmode
14413 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
14415 unsigned HOST_WIDE_INT low;
14416 HOST_WIDE_INT high;
14418 if (GET_CODE (x) == CONST_DOUBLE)
14420 low = CONST_DOUBLE_LOW (x);
14421 high = CONST_DOUBLE_HIGH (x);
14424 #if HOST_BITS_PER_WIDE_INT == 32
14427 high = (low & 0x80000000) ? ~0 : 0;
14431 low = INTVAL (x) & 0xffffffff;
14432 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
14436 /* TOC entries are always Pmode-sized, but since this
14437 is a bigendian machine then if we're putting smaller
14438 integer constants in the TOC we have to pad them.
14439 (This is still a win over putting the constants in
14440 a separate constant pool, because then we'd have
14441 to have both a TOC entry _and_ the actual constant.)
14443 For a 32-bit target, CONST_INT values are loaded and shifted
14444 entirely within `low' and can be stored in one TOC entry. */
14446 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
14447 abort ();/* It would be easy to make this work, but it doesn't now. */
14449 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
14451 #if HOST_BITS_PER_WIDE_INT == 32
14452 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14453 POINTER_SIZE, &low, &high, 0);
14456 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14457 high = (HOST_WIDE_INT) low >> 32;
14464 if (TARGET_MINIMAL_TOC)
14465 fputs (DOUBLE_INT_ASM_OP, file);
14467 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14468 (long) high & 0xffffffff, (long) low & 0xffffffff);
14469 fprintf (file, "0x%lx%08lx\n",
14470 (long) high & 0xffffffff, (long) low & 0xffffffff);
14475 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14477 if (TARGET_MINIMAL_TOC)
14478 fputs ("\t.long ", file);
14480 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14481 (long) high & 0xffffffff, (long) low & 0xffffffff);
14482 fprintf (file, "0x%lx,0x%lx\n",
14483 (long) high & 0xffffffff, (long) low & 0xffffffff);
14487 if (TARGET_MINIMAL_TOC)
14488 fputs ("\t.long ", file);
14490 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14491 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
14497 if (GET_CODE (x) == CONST)
14499 if (GET_CODE (XEXP (x, 0)) != PLUS)
14502 base = XEXP (XEXP (x, 0), 0);
14503 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14506 if (GET_CODE (base) == SYMBOL_REF)
14507 name = XSTR (base, 0);
14508 else if (GET_CODE (base) == LABEL_REF)
14509 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14510 else if (GET_CODE (base) == CODE_LABEL)
14511 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14515 real_name = (*targetm.strip_name_encoding) (name);
14516 if (TARGET_MINIMAL_TOC)
14517 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
14520 fprintf (file, "\t.tc %s", real_name);
14523 fprintf (file, ".N%d", - offset);
14525 fprintf (file, ".P%d", offset);
14527 fputs ("[TC],", file);
14530 /* Currently C++ toc references to vtables can be emitted before it
14531 is decided whether the vtable is public or private. If this is
14532 the case, then the linker will eventually complain that there is
14533 a TOC reference to an unknown section. Thus, for vtables only,
14534 we emit the TOC reference to reference the symbol and not the
14536 if (VTABLE_NAME_P (name))
14538 RS6000_OUTPUT_BASENAME (file, name);
14540 fprintf (file, "%d", offset);
14541 else if (offset > 0)
14542 fprintf (file, "+%d", offset);
14545 output_addr_const (file, x);
14549 /* Output an assembler pseudo-op to write an ASCII string of N characters
14550 starting at P to FILE.
14552 On the RS/6000, we have to do this using the .byte operation and
14553 write out special characters outside the quoted string.
14554 Also, the assembler is broken; very long strings are truncated,
14555 so we must artificially break them up early. */
14558 output_ascii (FILE *file, const char *p, int n)
14561 int i, count_string;
14562 const char *for_string = "\t.byte \"";
14563 const char *for_decimal = "\t.byte ";
14564 const char *to_close = NULL;
14567 for (i = 0; i < n; i++)
14570 if (c >= ' ' && c < 0177)
14573 fputs (for_string, file);
14576 /* Write two quotes to get one. */
14584 for_decimal = "\"\n\t.byte ";
14588 if (count_string >= 512)
14590 fputs (to_close, file);
14592 for_string = "\t.byte \"";
14593 for_decimal = "\t.byte ";
14601 fputs (for_decimal, file);
14602 fprintf (file, "%d", c);
14604 for_string = "\n\t.byte \"";
14605 for_decimal = ", ";
14611 /* Now close the string if we have written one. Then end the line. */
14613 fputs (to_close, file);
14616 /* Generate a unique section name for FILENAME for a section type
14617 represented by SECTION_DESC. Output goes into BUF.
14619 SECTION_DESC can be any string, as long as it is different for each
14620 possible section type.
14622 We name the section in the same manner as xlc. The name begins with an
14623 underscore followed by the filename (after stripping any leading directory
14624 names) with the last period replaced by the string SECTION_DESC. If
14625 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14629 rs6000_gen_section_name (char **buf, const char *filename,
14630 const char *section_desc)
14632 const char *q, *after_last_slash, *last_period = 0;
14636 after_last_slash = filename;
14637 for (q = filename; *q; q++)
14640 after_last_slash = q + 1;
14641 else if (*q == '.')
14645 len = strlen (after_last_slash) + strlen (section_desc) + 2;
14646 *buf = (char *) xmalloc (len);
14651 for (q = after_last_slash; *q; q++)
14653 if (q == last_period)
14655 strcpy (p, section_desc);
14656 p += strlen (section_desc);
14660 else if (ISALNUM (*q))
14664 if (last_period == 0)
14665 strcpy (p, section_desc);
14670 /* Emit profile function. */
14673 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
14675 if (TARGET_PROFILE_KERNEL)
14678 if (DEFAULT_ABI == ABI_AIX)
14680 #ifndef NO_PROFILE_COUNTERS
14681 # define NO_PROFILE_COUNTERS 0
14683 if (NO_PROFILE_COUNTERS)
14684 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14688 const char *label_name;
14691 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14692 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14693 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
14695 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14699 else if (DEFAULT_ABI == ABI_DARWIN)
14701 const char *mcount_name = RS6000_MCOUNT;
14702 int caller_addr_regno = LINK_REGISTER_REGNUM;
14704 /* Be conservative and always set this, at least for now. */
14705 current_function_uses_pic_offset_table = 1;
14708 /* For PIC code, set up a stub and collect the caller's address
14709 from r0, which is where the prologue puts it. */
14710 if (MACHOPIC_INDIRECT
14711 && current_function_uses_pic_offset_table)
14712 caller_addr_regno = 0;
14714 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14716 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14720 /* Write function profiler code. */
14723 output_function_profiler (FILE *file, int labelno)
14728 switch (DEFAULT_ABI)
14737 warning ("no profiling of 64-bit code for this ABI");
14740 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14741 fprintf (file, "\tmflr %s\n", reg_names[0]);
14744 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
14745 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14746 reg_names[0], save_lr, reg_names[1]);
14747 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
14748 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
14749 assemble_name (file, buf);
14750 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
14752 else if (flag_pic > 1)
14754 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14755 reg_names[0], save_lr, reg_names[1]);
14756 /* Now, we need to get the address of the label. */
14757 fputs ("\tbl 1f\n\t.long ", file);
14758 assemble_name (file, buf);
14759 fputs ("-.\n1:", file);
14760 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
14761 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
14762 reg_names[0], reg_names[11]);
14763 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14764 reg_names[0], reg_names[0], reg_names[11]);
14768 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
14769 assemble_name (file, buf);
14770 fputs ("@ha\n", file);
14771 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14772 reg_names[0], save_lr, reg_names[1]);
14773 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
14774 assemble_name (file, buf);
14775 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
14778 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
14779 fprintf (file, "\tbl %s%s\n",
14780 RS6000_MCOUNT, flag_pic ? "@plt" : "");
14785 if (!TARGET_PROFILE_KERNEL)
14787 /* Don't do anything, done in output_profile_hook (). */
14794 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14795 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14797 if (cfun->static_chain_decl != NULL)
14799 asm_fprintf (file, "\tstd %s,24(%s)\n",
14800 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14801 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14802 asm_fprintf (file, "\tld %s,24(%s)\n",
14803 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14806 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14813 /* Power4 load update and store update instructions are cracked into a
14814 load or store and an integer insn which are executed in the same cycle.
14815 Branches have their own dispatch slot which does not count against the
14816 GCC issue rate, but it changes the program flow so there are no other
14817 instructions to issue in this cycle. */
14820 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14821 int verbose ATTRIBUTE_UNUSED,
14822 rtx insn, int more)
14824 if (GET_CODE (PATTERN (insn)) == USE
14825 || GET_CODE (PATTERN (insn)) == CLOBBER)
14828 if (rs6000_sched_groups)
14830 if (is_microcoded_insn (insn))
14832 else if (is_cracked_insn (insn))
14833 return more > 2 ? more - 2 : 0;
14839 /* Adjust the cost of a scheduling dependency. Return the new cost of
14840 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14843 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
14845 if (! recog_memoized (insn))
14848 if (REG_NOTE_KIND (link) != 0)
14851 if (REG_NOTE_KIND (link) == 0)
14853 /* Data dependency; DEP_INSN writes a register that INSN reads
14854 some cycles later. */
14856 /* Separate a load from a narrower, dependent store. */
14857 if (rs6000_sched_groups
14858 && GET_CODE (PATTERN (insn)) == SET
14859 && GET_CODE (PATTERN (dep_insn)) == SET
14860 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14861 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14862 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14863 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14866 switch (get_attr_type (insn))
14869 /* Tell the first scheduling pass about the latency between
14870 a mtctr and bctr (and mtlr and br/blr). The first
14871 scheduling pass will not know about this latency since
14872 the mtctr instruction, which has the latency associated
14873 to it, will be generated by reload. */
14874 return TARGET_POWER ? 5 : 4;
14876 /* Leave some extra cycles between a compare and its
14877 dependent branch, to inhibit expensive mispredicts. */
14878 if ((rs6000_cpu_attr == CPU_PPC603
14879 || rs6000_cpu_attr == CPU_PPC604
14880 || rs6000_cpu_attr == CPU_PPC604E
14881 || rs6000_cpu_attr == CPU_PPC620
14882 || rs6000_cpu_attr == CPU_PPC630
14883 || rs6000_cpu_attr == CPU_PPC750
14884 || rs6000_cpu_attr == CPU_PPC7400
14885 || rs6000_cpu_attr == CPU_PPC7450
14886 || rs6000_cpu_attr == CPU_POWER4
14887 || rs6000_cpu_attr == CPU_POWER5)
14888 && recog_memoized (dep_insn)
14889 && (INSN_CODE (dep_insn) >= 0)
14890 && (get_attr_type (dep_insn) == TYPE_CMP
14891 || get_attr_type (dep_insn) == TYPE_COMPARE
14892 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
14893 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14894 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14895 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14896 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14897 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14902 /* Fall out to return default cost. */
14908 /* The function returns a true if INSN is microcoded.
14909 Return false otherwise. */
14912 is_microcoded_insn (rtx insn)
14914 if (!insn || !INSN_P (insn)
14915 || GET_CODE (PATTERN (insn)) == USE
14916 || GET_CODE (PATTERN (insn)) == CLOBBER)
14919 if (rs6000_sched_groups)
14921 enum attr_type type = get_attr_type (insn);
14922 if (type == TYPE_LOAD_EXT_U
14923 || type == TYPE_LOAD_EXT_UX
14924 || type == TYPE_LOAD_UX
14925 || type == TYPE_STORE_UX
14926 || type == TYPE_MFCR)
14933 /* The function returns a nonzero value if INSN can be scheduled only
14934 as the first insn in a dispatch group ("dispatch-slot restricted").
14935 In this case, the returned value indicates how many dispatch slots
14936 the insn occupies (at the beginning of the group).
14937 Return 0 otherwise. */
14940 is_dispatch_slot_restricted (rtx insn)
14942 enum attr_type type;
14944 if (!rs6000_sched_groups)
14948 || insn == NULL_RTX
14949 || GET_CODE (insn) == NOTE
14950 || GET_CODE (PATTERN (insn)) == USE
14951 || GET_CODE (PATTERN (insn)) == CLOBBER)
14954 type = get_attr_type (insn);
14961 case TYPE_DELAYED_CR:
14962 case TYPE_CR_LOGICAL:
14970 if (rs6000_cpu == PROCESSOR_POWER5
14971 && is_cracked_insn (insn))
14977 /* The function returns true if INSN is cracked into 2 instructions
14978 by the processor (and therefore occupies 2 issue slots). */
14981 is_cracked_insn (rtx insn)
14983 if (!insn || !INSN_P (insn)
14984 || GET_CODE (PATTERN (insn)) == USE
14985 || GET_CODE (PATTERN (insn)) == CLOBBER)
14988 if (rs6000_sched_groups)
14990 enum attr_type type = get_attr_type (insn);
14991 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
14992 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14993 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14994 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14995 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14996 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14997 || type == TYPE_IDIV || type == TYPE_LDIV
14998 || type == TYPE_INSERT_WORD)
15005 /* The function returns true if INSN can be issued only from
15006 the branch slot. */
15009 is_branch_slot_insn (rtx insn)
15011 if (!insn || !INSN_P (insn)
15012 || GET_CODE (PATTERN (insn)) == USE
15013 || GET_CODE (PATTERN (insn)) == CLOBBER)
15016 if (rs6000_sched_groups)
15018 enum attr_type type = get_attr_type (insn);
15019 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15027 /* A C statement (sans semicolon) to update the integer scheduling
15028 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15029 INSN earlier, reduce the priority to execute INSN later. Do not
15030 define this macro if you do not need to adjust the scheduling
15031 priorities of insns. */
15034 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15036 /* On machines (like the 750) which have asymmetric integer units,
15037 where one integer unit can do multiply and divides and the other
15038 can't, reduce the priority of multiply/divide so it is scheduled
15039 before other integer operations. */
15042 if (! INSN_P (insn))
15045 if (GET_CODE (PATTERN (insn)) == USE)
15048 switch (rs6000_cpu_attr) {
15050 switch (get_attr_type (insn))
15057 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15058 priority, priority);
15059 if (priority >= 0 && priority < 0x01000000)
15066 if (is_dispatch_slot_restricted (insn)
15067 && reload_completed
15068 && current_sched_info->sched_max_insns_priority
15069 && rs6000_sched_restricted_insns_priority)
15072 /* Prioritize insns that can be dispatched only in the first
15074 if (rs6000_sched_restricted_insns_priority == 1)
15075 /* Attach highest priority to insn. This means that in
15076 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15077 precede 'priority' (critical path) considerations. */
15078 return current_sched_info->sched_max_insns_priority;
15079 else if (rs6000_sched_restricted_insns_priority == 2)
15080 /* Increase priority of insn by a minimal amount. This means that in
15081 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15082 considerations precede dispatch-slot restriction considerations. */
15083 return (priority + 1);
15089 /* Return how many instructions the machine can issue per cycle. */
15092 rs6000_issue_rate (void)
15094 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15095 if (!reload_completed)
15098 switch (rs6000_cpu_attr) {
15099 case CPU_RIOS1: /* ? */
15101 case CPU_PPC601: /* ? */
15124 /* Return how many instructions to look ahead for better insn
15128 rs6000_use_sched_lookahead (void)
15130 if (rs6000_cpu_attr == CPU_PPC8540)
15135 /* Determine is PAT refers to memory. */
15138 is_mem_ref (rtx pat)
15144 if (GET_CODE (pat) == MEM)
15147 /* Recursively process the pattern. */
15148 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15150 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15153 ret |= is_mem_ref (XEXP (pat, i));
15154 else if (fmt[i] == 'E')
15155 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15156 ret |= is_mem_ref (XVECEXP (pat, i, j));
15162 /* Determine if PAT is a PATTERN of a load insn. */
15165 is_load_insn1 (rtx pat)
15167 if (!pat || pat == NULL_RTX)
15170 if (GET_CODE (pat) == SET)
15171 return is_mem_ref (SET_SRC (pat));
15173 if (GET_CODE (pat) == PARALLEL)
15177 for (i = 0; i < XVECLEN (pat, 0); i++)
15178 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15185 /* Determine if INSN loads from memory. */
15188 is_load_insn (rtx insn)
15190 if (!insn || !INSN_P (insn))
15193 if (GET_CODE (insn) == CALL_INSN)
15196 return is_load_insn1 (PATTERN (insn));
15199 /* Determine if PAT is a PATTERN of a store insn. */
15202 is_store_insn1 (rtx pat)
15204 if (!pat || pat == NULL_RTX)
15207 if (GET_CODE (pat) == SET)
15208 return is_mem_ref (SET_DEST (pat));
15210 if (GET_CODE (pat) == PARALLEL)
15214 for (i = 0; i < XVECLEN (pat, 0); i++)
15215 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15222 /* Determine if INSN stores to memory. */
15225 is_store_insn (rtx insn)
15227 if (!insn || !INSN_P (insn))
15230 return is_store_insn1 (PATTERN (insn));
15233 /* Returns whether the dependence between INSN and NEXT is considered
15234 costly by the given target. */
15237 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15240 /* If the flag is not enbled - no dependence is considered costly;
15241 allow all dependent insns in the same group.
15242 This is the most aggressive option. */
15243 if (rs6000_sched_costly_dep == no_dep_costly)
15246 /* If the flag is set to 1 - a dependence is always considered costly;
15247 do not allow dependent instructions in the same group.
15248 This is the most conservative option. */
15249 if (rs6000_sched_costly_dep == all_deps_costly)
15252 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15253 && is_load_insn (next)
15254 && is_store_insn (insn))
15255 /* Prevent load after store in the same group. */
15258 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
15259 && is_load_insn (next)
15260 && is_store_insn (insn)
15261 && (!link || (int) REG_NOTE_KIND (link) == 0))
15262 /* Prevent load after store in the same group if it is a true
15266 /* The flag is set to X; dependences with latency >= X are considered costly,
15267 and will not be scheduled in the same group. */
15268 if (rs6000_sched_costly_dep <= max_dep_latency
15269 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15275 /* Return the next insn after INSN that is found before TAIL is reached,
15276 skipping any "non-active" insns - insns that will not actually occupy
15277 an issue slot. Return NULL_RTX if such an insn is not found. */
15280 get_next_active_insn (rtx insn, rtx tail)
15284 if (!insn || insn == tail)
15287 next_insn = NEXT_INSN (insn);
15290 && next_insn != tail
15291 && (GET_CODE(next_insn) == NOTE
15292 || GET_CODE (PATTERN (next_insn)) == USE
15293 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15295 next_insn = NEXT_INSN (next_insn);
15298 if (!next_insn || next_insn == tail)
15304 /* Return whether the presence of INSN causes a dispatch group termination
15305 of group WHICH_GROUP.
15307 If WHICH_GROUP == current_group, this function will return true if INSN
15308 causes the termination of the current group (i.e, the dispatch group to
15309 which INSN belongs). This means that INSN will be the last insn in the
15310 group it belongs to.
15312 If WHICH_GROUP == previous_group, this function will return true if INSN
15313 causes the termination of the previous group (i.e, the dispatch group that
15314 precedes the group to which INSN belongs). This means that INSN will be
15315 the first insn in the group it belongs to). */
15318 insn_terminates_group_p (rtx insn, enum group_termination which_group)
15320 enum attr_type type;
15325 type = get_attr_type (insn);
15327 if (is_microcoded_insn (insn))
15330 if (which_group == current_group)
15332 if (is_branch_slot_insn (insn))
15336 else if (which_group == previous_group)
15338 if (is_dispatch_slot_restricted (insn))
15346 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15347 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15350 is_costly_group (rtx *group_insns, rtx next_insn)
15355 int issue_rate = rs6000_issue_rate ();
15357 for (i = 0; i < issue_rate; i++)
15359 rtx insn = group_insns[i];
15362 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
15364 rtx next = XEXP (link, 0);
15365 if (next == next_insn)
15367 cost = insn_cost (insn, link, next_insn);
15368 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15377 /* Utility of the function redefine_groups.
15378 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15379 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15380 to keep it "far" (in a separate group) from GROUP_INSNS, following
15381 one of the following schemes, depending on the value of the flag
15382 -minsert_sched_nops = X:
15383 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15384 in order to force NEXT_INSN into a separate group.
15385 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15386 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15387 insertion (has a group just ended, how many vacant issue slots remain in the
15388 last group, and how many dispatch groups were encountered so far). */
15391 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15392 rtx next_insn, bool *group_end, int can_issue_more,
15397 int issue_rate = rs6000_issue_rate ();
15398 bool end = *group_end;
15401 if (next_insn == NULL_RTX)
15402 return can_issue_more;
15404 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15405 return can_issue_more;
15407 force = is_costly_group (group_insns, next_insn);
15409 return can_issue_more;
15411 if (sched_verbose > 6)
15412 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
15413 *group_count ,can_issue_more);
15415 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15418 can_issue_more = 0;
15420 /* Since only a branch can be issued in the last issue_slot, it is
15421 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15422 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15423 in this case the last nop will start a new group and the branch
15424 will be forced to the new group. */
15425 if (can_issue_more && !is_branch_slot_insn (next_insn))
15428 while (can_issue_more > 0)
15431 emit_insn_before (nop, next_insn);
15439 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15441 int n_nops = rs6000_sched_insert_nops;
15443 /* Nops can't be issued from the branch slot, so the effective
15444 issue_rate for nops is 'issue_rate - 1'. */
15445 if (can_issue_more == 0)
15446 can_issue_more = issue_rate;
15448 if (can_issue_more == 0)
15450 can_issue_more = issue_rate - 1;
15453 for (i = 0; i < issue_rate; i++)
15455 group_insns[i] = 0;
15462 emit_insn_before (nop, next_insn);
15463 if (can_issue_more == issue_rate - 1) /* new group begins */
15466 if (can_issue_more == 0)
15468 can_issue_more = issue_rate - 1;
15471 for (i = 0; i < issue_rate; i++)
15473 group_insns[i] = 0;
15479 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15482 /* Is next_insn going to start a new group? */
15485 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15486 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15487 || (can_issue_more < issue_rate &&
15488 insn_terminates_group_p (next_insn, previous_group)));
15489 if (*group_end && end)
15492 if (sched_verbose > 6)
15493 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15494 *group_count, can_issue_more);
15495 return can_issue_more;
15498 return can_issue_more;
15501 /* This function tries to synch the dispatch groups that the compiler "sees"
15502 with the dispatch groups that the processor dispatcher is expected to
15503 form in practice. It tries to achieve this synchronization by forcing the
15504 estimated processor grouping on the compiler (as opposed to the function
15505 'pad_goups' which tries to force the scheduler's grouping on the processor).
15507 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15508 examines the (estimated) dispatch groups that will be formed by the processor
15509 dispatcher. It marks these group boundaries to reflect the estimated
15510 processor grouping, overriding the grouping that the scheduler had marked.
15511 Depending on the value of the flag '-minsert-sched-nops' this function can
15512 force certain insns into separate groups or force a certain distance between
15513 them by inserting nops, for example, if there exists a "costly dependence"
15516 The function estimates the group boundaries that the processor will form as
15517 folllows: It keeps track of how many vacant issue slots are available after
15518 each insn. A subsequent insn will start a new group if one of the following
15520 - no more vacant issue slots remain in the current dispatch group.
15521 - only the last issue slot, which is the branch slot, is vacant, but the next
15522 insn is not a branch.
15523 - only the last 2 or less issue slots, including the branch slot, are vacant,
15524 which means that a cracked insn (which occupies two issue slots) can't be
15525 issued in this group.
15526 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15527 start a new group. */
15530 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15532 rtx insn, next_insn;
15534 int can_issue_more;
15537 int group_count = 0;
15541 issue_rate = rs6000_issue_rate ();
15542 group_insns = alloca (issue_rate * sizeof (rtx));
15543 for (i = 0; i < issue_rate; i++)
15545 group_insns[i] = 0;
15547 can_issue_more = issue_rate;
15549 insn = get_next_active_insn (prev_head_insn, tail);
15552 while (insn != NULL_RTX)
15554 slot = (issue_rate - can_issue_more);
15555 group_insns[slot] = insn;
15557 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15558 if (insn_terminates_group_p (insn, current_group))
15559 can_issue_more = 0;
15561 next_insn = get_next_active_insn (insn, tail);
15562 if (next_insn == NULL_RTX)
15563 return group_count + 1;
15565 /* Is next_insn going to start a new group? */
15567 = (can_issue_more == 0
15568 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15569 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15570 || (can_issue_more < issue_rate &&
15571 insn_terminates_group_p (next_insn, previous_group)));
15573 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
15574 next_insn, &group_end, can_issue_more,
15580 can_issue_more = 0;
15581 for (i = 0; i < issue_rate; i++)
15583 group_insns[i] = 0;
15587 if (GET_MODE (next_insn) == TImode && can_issue_more)
15588 PUT_MODE(next_insn, VOIDmode);
15589 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
15590 PUT_MODE (next_insn, TImode);
15593 if (can_issue_more == 0)
15594 can_issue_more = issue_rate;
15597 return group_count;
15600 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15601 dispatch group boundaries that the scheduler had marked. Pad with nops
15602 any dispatch groups which have vacant issue slots, in order to force the
15603 scheduler's grouping on the processor dispatcher. The function
15604 returns the number of dispatch groups found. */
15607 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15609 rtx insn, next_insn;
15612 int can_issue_more;
15614 int group_count = 0;
15616 /* Initialize issue_rate. */
15617 issue_rate = rs6000_issue_rate ();
15618 can_issue_more = issue_rate;
15620 insn = get_next_active_insn (prev_head_insn, tail);
15621 next_insn = get_next_active_insn (insn, tail);
15623 while (insn != NULL_RTX)
15626 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15628 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15630 if (next_insn == NULL_RTX)
15635 /* If the scheduler had marked group termination at this location
15636 (between insn and next_indn), and neither insn nor next_insn will
15637 force group termination, pad the group with nops to force group
15640 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15641 && !insn_terminates_group_p (insn, current_group)
15642 && !insn_terminates_group_p (next_insn, previous_group))
15644 if (!is_branch_slot_insn(next_insn))
15647 while (can_issue_more)
15650 emit_insn_before (nop, next_insn);
15655 can_issue_more = issue_rate;
15660 next_insn = get_next_active_insn (insn, tail);
15663 return group_count;
15666 /* The following function is called at the end of scheduling BB.
15667 After reload, it inserts nops at insn group bundling. */
15670 rs6000_sched_finish (FILE *dump, int sched_verbose)
15675 fprintf (dump, "=== Finishing schedule.\n");
15677 if (reload_completed && rs6000_sched_groups)
15679 if (rs6000_sched_insert_nops == sched_finish_none)
15682 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
15683 n_groups = pad_groups (dump, sched_verbose,
15684 current_sched_info->prev_head,
15685 current_sched_info->next_tail);
15687 n_groups = redefine_groups (dump, sched_verbose,
15688 current_sched_info->prev_head,
15689 current_sched_info->next_tail);
15691 if (sched_verbose >= 6)
15693 fprintf (dump, "ngroups = %d\n", n_groups);
15694 print_rtl (dump, current_sched_info->prev_head);
15695 fprintf (dump, "Done finish_sched\n");
15700 /* Length in units of the trampoline for entering a nested function. */
15703 rs6000_trampoline_size (void)
15707 switch (DEFAULT_ABI)
15713 ret = (TARGET_32BIT) ? 12 : 24;
15718 ret = (TARGET_32BIT) ? 40 : 48;
15725 /* Emit RTL insns to initialize the variable parts of a trampoline.
15726 FNADDR is an RTX for the address of the function's pure code.
15727 CXT is an RTX for the static chain value for the function. */
15730 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
15732 enum machine_mode pmode = Pmode;
15733 int regsize = (TARGET_32BIT) ? 4 : 8;
15734 rtx ctx_reg = force_reg (pmode, cxt);
15736 switch (DEFAULT_ABI)
15741 /* Macros to shorten the code expansions below. */
15742 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
15743 #define MEM_PLUS(addr,offset) \
15744 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
15746 /* Under AIX, just build the 3 word function descriptor */
15749 rtx fn_reg = gen_reg_rtx (pmode);
15750 rtx toc_reg = gen_reg_rtx (pmode);
15751 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
15752 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
15753 emit_move_insn (MEM_DEREF (addr), fn_reg);
15754 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15755 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15759 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15762 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
15763 FALSE, VOIDmode, 4,
15765 GEN_INT (rs6000_trampoline_size ()), SImode,
15775 /* Table of valid machine attributes. */
15777 const struct attribute_spec rs6000_attribute_table[] =
15779 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
15780 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
15781 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15782 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15783 #ifdef SUBTARGET_ATTRIBUTE_TABLE
15784 SUBTARGET_ATTRIBUTE_TABLE,
15786 { NULL, 0, 0, false, false, false, NULL }
15789 /* Handle the "altivec" attribute. The attribute may have
15790 arguments as follows:
15792 __attribute__((altivec(vector__)))
15793 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15794 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15796 and may appear more than once (e.g., 'vector bool char') in a
15797 given declaration. */
15800 rs6000_handle_altivec_attribute (tree *node,
15801 tree name ATTRIBUTE_UNUSED,
15803 int flags ATTRIBUTE_UNUSED,
15804 bool *no_add_attrs)
15806 tree type = *node, result = NULL_TREE;
15807 enum machine_mode mode;
15810 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15811 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15812 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
15815 while (POINTER_TYPE_P (type)
15816 || TREE_CODE (type) == FUNCTION_TYPE
15817 || TREE_CODE (type) == METHOD_TYPE
15818 || TREE_CODE (type) == ARRAY_TYPE)
15819 type = TREE_TYPE (type);
15821 mode = TYPE_MODE (type);
15823 /* Check for invalid AltiVec type qualifiers. */
15824 if (type == long_unsigned_type_node || type == long_integer_type_node)
15827 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15828 else if (rs6000_warn_altivec_long)
15829 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15831 else if (type == long_long_unsigned_type_node
15832 || type == long_long_integer_type_node)
15833 error ("use of %<long long%> in AltiVec types is invalid");
15834 else if (type == double_type_node)
15835 error ("use of %<double%> in AltiVec types is invalid");
15836 else if (type == long_double_type_node)
15837 error ("use of %<long double%> in AltiVec types is invalid");
15838 else if (type == boolean_type_node)
15839 error ("use of boolean types in AltiVec types is invalid");
15840 else if (TREE_CODE (type) == COMPLEX_TYPE)
15841 error ("use of %<complex%> in AltiVec types is invalid");
15843 switch (altivec_type)
15846 unsigned_p = TYPE_UNSIGNED (type);
15850 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15853 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15856 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15858 case SFmode: result = V4SF_type_node; break;
15859 /* If the user says 'vector int bool', we may be handed the 'bool'
15860 attribute _before_ the 'vector' attribute, and so select the
15861 proper type in the 'b' case below. */
15862 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15870 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15871 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15872 case QImode: case V16QImode: result = bool_V16QI_type_node;
15879 case V8HImode: result = pixel_V8HI_type_node;
15885 if (result && result != type && TYPE_READONLY (type))
15886 result = build_qualified_type (result, TYPE_QUAL_CONST);
15888 *no_add_attrs = true; /* No need to hang on to the attribute. */
15891 *node = reconstruct_complex_type (*node, result);
15896 /* AltiVec defines four built-in scalar types that serve as vector
15897 elements; we must teach the compiler how to mangle them. */
15899 static const char *
15900 rs6000_mangle_fundamental_type (tree type)
15902 if (type == bool_char_type_node) return "U6__boolc";
15903 if (type == bool_short_type_node) return "U6__bools";
15904 if (type == pixel_type_node) return "u7__pixel";
15905 if (type == bool_int_type_node) return "U6__booli";
15907 /* For all other types, use normal C++ mangling. */
15911 /* Handle a "longcall" or "shortcall" attribute; arguments as in
15912 struct attribute_spec.handler. */
15915 rs6000_handle_longcall_attribute (tree *node, tree name,
15916 tree args ATTRIBUTE_UNUSED,
15917 int flags ATTRIBUTE_UNUSED,
15918 bool *no_add_attrs)
15920 if (TREE_CODE (*node) != FUNCTION_TYPE
15921 && TREE_CODE (*node) != FIELD_DECL
15922 && TREE_CODE (*node) != TYPE_DECL)
15924 warning ("%qs attribute only applies to functions",
15925 IDENTIFIER_POINTER (name));
15926 *no_add_attrs = true;
15932 /* Set longcall attributes on all functions declared when
15933 rs6000_default_long_calls is true. */
15935 rs6000_set_default_type_attributes (tree type)
15937 if (rs6000_default_long_calls
15938 && (TREE_CODE (type) == FUNCTION_TYPE
15939 || TREE_CODE (type) == METHOD_TYPE))
15940 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15942 TYPE_ATTRIBUTES (type));
15945 /* Return a reference suitable for calling a function with the
15946 longcall attribute. */
15949 rs6000_longcall_ref (rtx call_ref)
15951 const char *call_name;
15954 if (GET_CODE (call_ref) != SYMBOL_REF)
15957 /* System V adds '.' to the internal name, so skip them. */
15958 call_name = XSTR (call_ref, 0);
15959 if (*call_name == '.')
15961 while (*call_name == '.')
15964 node = get_identifier (call_name);
15965 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15968 return force_reg (Pmode, call_ref);
15971 #ifdef USING_ELFOS_H
15973 /* A C statement or statements to switch to the appropriate section
15974 for output of RTX in mode MODE. You can assume that RTX is some
15975 kind of constant in RTL. The argument MODE is redundant except in
15976 the case of a `const_int' rtx. Select the section by calling
15977 `text_section' or one of the alternatives for other sections.
15979 Do not define this macro if you put all constants in the read-only
15983 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15984 unsigned HOST_WIDE_INT align)
15986 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15989 default_elf_select_rtx_section (mode, x, align);
15992 /* A C statement or statements to switch to the appropriate
15993 section for output of DECL. DECL is either a `VAR_DECL' node
15994 or a constant of some sort. RELOC indicates whether forming
15995 the initial value of DECL requires link-time relocations. */
15998 rs6000_elf_select_section (tree decl, int reloc,
15999 unsigned HOST_WIDE_INT align)
16001 /* Pretend that we're always building for a shared library when
16002 ABI_AIX, because otherwise we end up with dynamic relocations
16003 in read-only sections. This happens for function pointers,
16004 references to vtables in typeinfo, and probably other cases. */
16005 default_elf_select_section_1 (decl, reloc, align,
16006 flag_pic || DEFAULT_ABI == ABI_AIX);
16009 /* A C statement to build up a unique section name, expressed as a
16010 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16011 RELOC indicates whether the initial value of EXP requires
16012 link-time relocations. If you do not define this macro, GCC will use
16013 the symbol name prefixed by `.' as the section name. Note - this
16014 macro can now be called for uninitialized data items as well as
16015 initialized data and functions. */
16018 rs6000_elf_unique_section (tree decl, int reloc)
16020 /* As above, pretend that we're always building for a shared library
16021 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16022 default_unique_section_1 (decl, reloc,
16023 flag_pic || DEFAULT_ABI == ABI_AIX);
16026 /* For a SYMBOL_REF, set generic flags and then perform some
16027 target-specific processing.
16029 When the AIX ABI is requested on a non-AIX system, replace the
16030 function name with the real name (with a leading .) rather than the
16031 function descriptor name. This saves a lot of overriding code to
16032 read the prefixes. */
16035 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16037 default_encode_section_info (decl, rtl, first);
16040 && TREE_CODE (decl) == FUNCTION_DECL
16042 && DEFAULT_ABI == ABI_AIX)
16044 rtx sym_ref = XEXP (rtl, 0);
16045 size_t len = strlen (XSTR (sym_ref, 0));
16046 char *str = alloca (len + 2);
16048 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16049 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16054 rs6000_elf_in_small_data_p (tree decl)
16056 if (rs6000_sdata == SDATA_NONE)
16059 /* We want to merge strings, so we never consider them small data. */
16060 if (TREE_CODE (decl) == STRING_CST)
16063 /* Functions are never in the small data area. */
16064 if (TREE_CODE (decl) == FUNCTION_DECL)
16067 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16069 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16070 if (strcmp (section, ".sdata") == 0
16071 || strcmp (section, ".sdata2") == 0
16072 || strcmp (section, ".sbss") == 0
16073 || strcmp (section, ".sbss2") == 0
16074 || strcmp (section, ".PPC.EMB.sdata0") == 0
16075 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16080 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16083 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16084 /* If it's not public, and we're not going to reference it there,
16085 there's no need to put it in the small data section. */
16086 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16093 #endif /* USING_ELFOS_H */
16096 /* Return a REG that occurs in ADDR with coefficient 1.
16097 ADDR can be effectively incremented by incrementing REG.
16099 r0 is special and we must not select it as an address
16100 register by this routine since our caller will try to
16101 increment the returned register via an "la" instruction. */
16104 find_addr_reg (rtx addr)
16106 while (GET_CODE (addr) == PLUS)
16108 if (GET_CODE (XEXP (addr, 0)) == REG
16109 && REGNO (XEXP (addr, 0)) != 0)
16110 addr = XEXP (addr, 0);
16111 else if (GET_CODE (XEXP (addr, 1)) == REG
16112 && REGNO (XEXP (addr, 1)) != 0)
16113 addr = XEXP (addr, 1);
16114 else if (CONSTANT_P (XEXP (addr, 0)))
16115 addr = XEXP (addr, 1);
16116 else if (CONSTANT_P (XEXP (addr, 1)))
16117 addr = XEXP (addr, 0);
16121 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16127 rs6000_fatal_bad_address (rtx op)
16129 fatal_insn ("bad address", op);
16134 static tree branch_island_list = 0;
16136 /* Remember to generate a branch island for far calls to the given
16140 add_compiler_branch_island (tree label_name, tree function_name,
16143 tree branch_island = build_tree_list (function_name, label_name);
16144 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16145 TREE_CHAIN (branch_island) = branch_island_list;
16146 branch_island_list = branch_island;
16149 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16150 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16151 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16152 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16154 /* Generate far-jump branch islands for everything on the
16155 branch_island_list. Invoked immediately after the last instruction
16156 of the epilogue has been emitted; the branch-islands must be
16157 appended to, and contiguous with, the function body. Mach-O stubs
16158 are generated in machopic_output_stub(). */
16161 macho_branch_islands (void)
16164 tree branch_island;
16166 for (branch_island = branch_island_list;
16168 branch_island = TREE_CHAIN (branch_island))
16170 const char *label =
16171 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16173 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16174 char name_buf[512];
16175 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16176 if (name[0] == '*' || name[0] == '&')
16177 strcpy (name_buf, name+1);
16181 strcpy (name_buf+1, name);
16183 strcpy (tmp_buf, "\n");
16184 strcat (tmp_buf, label);
16185 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16186 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16187 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16188 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16191 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16192 strcat (tmp_buf, label);
16193 strcat (tmp_buf, "_pic\n");
16194 strcat (tmp_buf, label);
16195 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16197 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16198 strcat (tmp_buf, name_buf);
16199 strcat (tmp_buf, " - ");
16200 strcat (tmp_buf, label);
16201 strcat (tmp_buf, "_pic)\n");
16203 strcat (tmp_buf, "\tmtlr r0\n");
16205 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16206 strcat (tmp_buf, name_buf);
16207 strcat (tmp_buf, " - ");
16208 strcat (tmp_buf, label);
16209 strcat (tmp_buf, "_pic)\n");
16211 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16215 strcat (tmp_buf, ":\nlis r12,hi16(");
16216 strcat (tmp_buf, name_buf);
16217 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16218 strcat (tmp_buf, name_buf);
16219 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16221 output_asm_insn (tmp_buf, 0);
16222 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16223 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16224 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16225 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16228 branch_island_list = 0;
16231 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16232 already there or not. */
16235 no_previous_def (tree function_name)
16237 tree branch_island;
16238 for (branch_island = branch_island_list;
16240 branch_island = TREE_CHAIN (branch_island))
16241 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16246 /* GET_PREV_LABEL gets the label name from the previous definition of
16250 get_prev_label (tree function_name)
16252 tree branch_island;
16253 for (branch_island = branch_island_list;
16255 branch_island = TREE_CHAIN (branch_island))
16256 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16257 return BRANCH_ISLAND_LABEL_NAME (branch_island);
16261 /* INSN is either a function call or a millicode call. It may have an
16262 unconditional jump in its delay slot.
16264 CALL_DEST is the routine we are calling. */
16267 output_call (rtx insn, rtx *operands, int dest_operand_number,
16268 int cookie_operand_number)
16270 static char buf[256];
16271 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16272 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
16275 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
16277 if (no_previous_def (funname))
16279 int line_number = 0;
16280 rtx label_rtx = gen_label_rtx ();
16281 char *label_buf, temp_buf[256];
16282 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16283 CODE_LABEL_NUMBER (label_rtx));
16284 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16285 labelname = get_identifier (label_buf);
16286 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16288 line_number = NOTE_LINE_NUMBER (insn);
16289 add_compiler_branch_island (labelname, funname, line_number);
16292 labelname = get_prev_label (funname);
16294 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16295 instruction will reach 'foo', otherwise link as 'bl L42'".
16296 "L42" should be a 'branch island', that will do a far jump to
16297 'foo'. Branch islands are generated in
16298 macho_branch_islands(). */
16299 sprintf (buf, "jbsr %%z%d,%.246s",
16300 dest_operand_number, IDENTIFIER_POINTER (labelname));
16303 sprintf (buf, "bl %%z%d", dest_operand_number);
16307 /* Generate PIC and indirect symbol stubs. */
16310 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16312 unsigned int length;
16313 char *symbol_name, *lazy_ptr_name;
16314 char *local_label_0;
16315 static int label = 0;
16317 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16318 symb = (*targetm.strip_name_encoding) (symb);
16321 length = strlen (symb);
16322 symbol_name = alloca (length + 32);
16323 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16325 lazy_ptr_name = alloca (length + 32);
16326 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16329 machopic_picsymbol_stub1_section ();
16331 machopic_symbol_stub1_section ();
16335 fprintf (file, "\t.align 5\n");
16337 fprintf (file, "%s:\n", stub);
16338 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16341 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
16342 sprintf (local_label_0, "\"L%011d$spb\"", label);
16344 fprintf (file, "\tmflr r0\n");
16345 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16346 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16347 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16348 lazy_ptr_name, local_label_0);
16349 fprintf (file, "\tmtlr r0\n");
16350 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16351 (TARGET_64BIT ? "ldu" : "lwzu"),
16352 lazy_ptr_name, local_label_0);
16353 fprintf (file, "\tmtctr r12\n");
16354 fprintf (file, "\tbctr\n");
16358 fprintf (file, "\t.align 4\n");
16360 fprintf (file, "%s:\n", stub);
16361 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16363 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
16364 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16365 (TARGET_64BIT ? "ldu" : "lwzu"),
16367 fprintf (file, "\tmtctr r12\n");
16368 fprintf (file, "\tbctr\n");
16371 machopic_lazy_symbol_ptr_section ();
16372 fprintf (file, "%s:\n", lazy_ptr_name);
16373 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16374 fprintf (file, "%sdyld_stub_binding_helper\n",
16375 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
16378 /* Legitimize PIC addresses. If the address is already
16379 position-independent, we return ORIG. Newly generated
16380 position-independent addresses go into a reg. This is REG if non
16381 zero, otherwise we allocate register(s) as necessary. */
16383 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
16386 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
16391 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16392 reg = gen_reg_rtx (Pmode);
16394 if (GET_CODE (orig) == CONST)
16396 if (GET_CODE (XEXP (orig, 0)) == PLUS
16397 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16400 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16402 /* Use a different reg for the intermediate value, as
16403 it will be marked UNCHANGING. */
16404 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16407 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16410 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16416 if (GET_CODE (offset) == CONST_INT)
16418 if (SMALL_INT (offset))
16419 return plus_constant (base, INTVAL (offset));
16420 else if (! reload_in_progress && ! reload_completed)
16421 offset = force_reg (Pmode, offset);
16424 rtx mem = force_const_mem (Pmode, orig);
16425 return machopic_legitimize_pic_address (mem, Pmode, reg);
16428 return gen_rtx_PLUS (Pmode, base, offset);
16431 /* Fall back on generic machopic code. */
16432 return machopic_legitimize_pic_address (orig, mode, reg);
16435 /* This is just a placeholder to make linking work without having to
16436 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16437 ever needed for Darwin (not too likely!) this would have to get a
16438 real definition. */
16445 /* Output a .machine directive for the Darwin assembler, and call
16446 the generic start_file routine. */
16449 rs6000_darwin_file_start (void)
16451 static const struct
16457 { "ppc64", "ppc64", MASK_64BIT },
16458 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16459 { "power4", "ppc970", 0 },
16460 { "G5", "ppc970", 0 },
16461 { "7450", "ppc7450", 0 },
16462 { "7400", "ppc7400", MASK_ALTIVEC },
16463 { "G4", "ppc7400", 0 },
16464 { "750", "ppc750", 0 },
16465 { "740", "ppc750", 0 },
16466 { "G3", "ppc750", 0 },
16467 { "604e", "ppc604e", 0 },
16468 { "604", "ppc604", 0 },
16469 { "603e", "ppc603", 0 },
16470 { "603", "ppc603", 0 },
16471 { "601", "ppc601", 0 },
16472 { NULL, "ppc", 0 } };
16473 const char *cpu_id = "";
16476 rs6000_file_start();
16478 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16479 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16480 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16481 && rs6000_select[i].string[0] != '\0')
16482 cpu_id = rs6000_select[i].string;
16484 /* Look through the mapping array. Pick the first name that either
16485 matches the argument, has a bit set in IF_SET that is also set
16486 in the target flags, or has a NULL name. */
16489 while (mapping[i].arg != NULL
16490 && strcmp (mapping[i].arg, cpu_id) != 0
16491 && (mapping[i].if_set & target_flags) == 0)
16494 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16497 #endif /* TARGET_MACHO */
16500 static unsigned int
16501 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
16503 return default_section_type_flags_1 (decl, name, reloc,
16504 flag_pic || DEFAULT_ABI == ABI_AIX);
16507 /* Record an element in the table of global constructors. SYMBOL is
16508 a SYMBOL_REF of the function to be called; PRIORITY is a number
16509 between 0 and MAX_INIT_PRIORITY.
16511 This differs from default_named_section_asm_out_constructor in
16512 that we have special handling for -mrelocatable. */
16515 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
16517 const char *section = ".ctors";
16520 if (priority != DEFAULT_INIT_PRIORITY)
16522 sprintf (buf, ".ctors.%.5u",
16523 /* Invert the numbering so the linker puts us in the proper
16524 order; constructors are run from right to left, and the
16525 linker sorts in increasing order. */
16526 MAX_INIT_PRIORITY - priority);
16530 named_section_flags (section, SECTION_WRITE);
16531 assemble_align (POINTER_SIZE);
16533 if (TARGET_RELOCATABLE)
16535 fputs ("\t.long (", asm_out_file);
16536 output_addr_const (asm_out_file, symbol);
16537 fputs (")@fixup\n", asm_out_file);
16540 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16544 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
16546 const char *section = ".dtors";
16549 if (priority != DEFAULT_INIT_PRIORITY)
16551 sprintf (buf, ".dtors.%.5u",
16552 /* Invert the numbering so the linker puts us in the proper
16553 order; constructors are run from right to left, and the
16554 linker sorts in increasing order. */
16555 MAX_INIT_PRIORITY - priority);
16559 named_section_flags (section, SECTION_WRITE);
16560 assemble_align (POINTER_SIZE);
16562 if (TARGET_RELOCATABLE)
16564 fputs ("\t.long (", asm_out_file);
16565 output_addr_const (asm_out_file, symbol);
16566 fputs (")@fixup\n", asm_out_file);
16569 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16573 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
16577 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16578 ASM_OUTPUT_LABEL (file, name);
16579 fputs (DOUBLE_INT_ASM_OP, file);
16580 rs6000_output_function_entry (file, name);
16581 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16584 fputs ("\t.size\t", file);
16585 assemble_name (file, name);
16586 fputs (",24\n\t.type\t.", file);
16587 assemble_name (file, name);
16588 fputs (",@function\n", file);
16589 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16591 fputs ("\t.globl\t.", file);
16592 assemble_name (file, name);
16597 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16598 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16599 rs6000_output_function_entry (file, name);
16600 fputs (":\n", file);
16604 if (TARGET_RELOCATABLE
16605 && (get_pool_size () != 0 || current_function_profile)
16610 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16612 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16613 fprintf (file, "\t.long ");
16614 assemble_name (file, buf);
16616 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16617 assemble_name (file, buf);
16621 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16622 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16624 if (DEFAULT_ABI == ABI_AIX)
16626 const char *desc_name, *orig_name;
16628 orig_name = (*targetm.strip_name_encoding) (name);
16629 desc_name = orig_name;
16630 while (*desc_name == '.')
16633 if (TREE_PUBLIC (decl))
16634 fprintf (file, "\t.globl %s\n", desc_name);
16636 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16637 fprintf (file, "%s:\n", desc_name);
16638 fprintf (file, "\t.long %s\n", orig_name);
16639 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16640 if (DEFAULT_ABI == ABI_AIX)
16641 fputs ("\t.long 0\n", file);
16642 fprintf (file, "\t.previous\n");
16644 ASM_OUTPUT_LABEL (file, name);
16650 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
16652 fputs (GLOBAL_ASM_OP, stream);
16653 RS6000_OUTPUT_BASENAME (stream, name);
16654 putc ('\n', stream);
16658 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16659 tree decl ATTRIBUTE_UNUSED)
16662 static const char * const suffix[3] = { "PR", "RO", "RW" };
16664 if (flags & SECTION_CODE)
16666 else if (flags & SECTION_WRITE)
16671 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
16672 (flags & SECTION_CODE) ? "." : "",
16673 name, suffix[smclass], flags & SECTION_ENTSIZE);
16677 rs6000_xcoff_select_section (tree decl, int reloc,
16678 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16680 if (decl_readonly_section_1 (decl, reloc, 1))
16682 if (TREE_PUBLIC (decl))
16683 read_only_data_section ();
16685 read_only_private_data_section ();
16689 if (TREE_PUBLIC (decl))
16692 private_data_section ();
16697 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
16701 /* Use select_section for private and uninitialized data. */
16702 if (!TREE_PUBLIC (decl)
16703 || DECL_COMMON (decl)
16704 || DECL_INITIAL (decl) == NULL_TREE
16705 || DECL_INITIAL (decl) == error_mark_node
16706 || (flag_zero_initialized_in_bss
16707 && initializer_zerop (DECL_INITIAL (decl))))
16710 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16711 name = (*targetm.strip_name_encoding) (name);
16712 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
16715 /* Select section for constant in constant pool.
16717 On RS/6000, all constants are in the private read-only data area.
16718 However, if this is being placed in the TOC it must be output as a
16722 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
16723 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16725 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16728 read_only_private_data_section ();
16731 /* Remove any trailing [DS] or the like from the symbol name. */
16733 static const char *
16734 rs6000_xcoff_strip_name_encoding (const char *name)
16739 len = strlen (name);
16740 if (name[len - 1] == ']')
16741 return ggc_alloc_string (name, len - 4);
16746 /* Section attributes. AIX is always PIC. */
16748 static unsigned int
16749 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
16751 unsigned int align;
16752 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16754 /* Align to at least UNIT size. */
16755 if (flags & SECTION_CODE)
16756 align = MIN_UNITS_PER_WORD;
16758 /* Increase alignment of large objects if not already stricter. */
16759 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16760 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16761 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16763 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
16766 /* Output at beginning of assembler file.
16768 Initialize the section names for the RS/6000 at this point.
16770 Specify filename, including full path, to assembler.
16772 We want to go into the TOC section so at least one .toc will be emitted.
16773 Also, in order to output proper .bs/.es pairs, we need at least one static
16774 [RW] section emitted.
16776 Finally, declare mcount when profiling to make the assembler happy. */
16779 rs6000_xcoff_file_start (void)
16781 rs6000_gen_section_name (&xcoff_bss_section_name,
16782 main_input_filename, ".bss_");
16783 rs6000_gen_section_name (&xcoff_private_data_section_name,
16784 main_input_filename, ".rw_");
16785 rs6000_gen_section_name (&xcoff_read_only_section_name,
16786 main_input_filename, ".ro_");
16788 fputs ("\t.file\t", asm_out_file);
16789 output_quoted_string (asm_out_file, main_input_filename);
16790 fputc ('\n', asm_out_file);
16791 if (write_symbols != NO_DEBUG)
16792 private_data_section ();
16795 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16796 rs6000_file_start ();
16799 /* Output at end of assembler file.
16800 On the RS/6000, referencing data should automatically pull in text. */
16803 rs6000_xcoff_file_end (void)
16806 fputs ("_section_.text:\n", asm_out_file);
16808 fputs (TARGET_32BIT
16809 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16812 #endif /* TARGET_XCOFF */
16815 /* Cross-module name binding. Darwin does not support overriding
16816 functions at dynamic-link time. */
16819 rs6000_binds_local_p (tree decl)
16821 return default_binds_local_p_1 (decl, 0);
16825 /* Compute a (partial) cost for rtx X. Return true if the complete
16826 cost has been computed, and false if subexpressions should be
16827 scanned. In either case, *TOTAL contains the cost result. */
16830 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
16832 enum machine_mode mode = GET_MODE (x);
16836 /* On the RS/6000, if it is valid in the insn, it is free. */
16838 if (((outer_code == SET
16839 || outer_code == PLUS
16840 || outer_code == MINUS)
16841 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16842 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
16843 || (outer_code == AND
16844 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16845 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16846 mode == SImode ? 'L' : 'J'))
16847 || mask_operand (x, VOIDmode)))
16848 || ((outer_code == IOR || outer_code == XOR)
16849 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16850 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16851 mode == SImode ? 'L' : 'J'))))
16852 || outer_code == ASHIFT
16853 || outer_code == ASHIFTRT
16854 || outer_code == LSHIFTRT
16855 || outer_code == ROTATE
16856 || outer_code == ROTATERT
16857 || outer_code == ZERO_EXTRACT
16858 || (outer_code == MULT
16859 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16860 || ((outer_code == DIV || outer_code == UDIV
16861 || outer_code == MOD || outer_code == UMOD)
16862 && exact_log2 (INTVAL (x)) >= 0)
16863 || (outer_code == COMPARE
16864 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16865 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16866 || (outer_code == EQ
16867 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16868 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16869 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16870 mode == SImode ? 'L' : 'J'))))
16871 || (outer_code == GTU
16872 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16873 || (outer_code == LTU
16874 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
16879 else if ((outer_code == PLUS
16880 && reg_or_add_cint64_operand (x, VOIDmode))
16881 || (outer_code == MINUS
16882 && reg_or_sub_cint64_operand (x, VOIDmode))
16883 || ((outer_code == SET
16884 || outer_code == IOR
16885 || outer_code == XOR)
16887 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16889 *total = COSTS_N_INSNS (1);
16896 && ((outer_code == AND
16897 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16898 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
16899 || mask64_operand (x, DImode)))
16900 || ((outer_code == IOR || outer_code == XOR)
16901 && CONST_DOUBLE_HIGH (x) == 0
16902 && (CONST_DOUBLE_LOW (x)
16903 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16908 else if (mode == DImode
16909 && (outer_code == SET
16910 || outer_code == IOR
16911 || outer_code == XOR)
16912 && CONST_DOUBLE_HIGH (x) == 0)
16914 *total = COSTS_N_INSNS (1);
16923 /* When optimizing for size, MEM should be slightly more expensive
16924 than generating address, e.g., (plus (reg) (const)).
16925 L1 cache latency is about two instructions. */
16926 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
16934 if (mode == DFmode)
16936 if (GET_CODE (XEXP (x, 0)) == MULT)
16938 /* FNMA accounted in outer NEG. */
16939 if (outer_code == NEG)
16940 *total = rs6000_cost->dmul - rs6000_cost->fp;
16942 *total = rs6000_cost->dmul;
16945 *total = rs6000_cost->fp;
16947 else if (mode == SFmode)
16949 /* FNMA accounted in outer NEG. */
16950 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16953 *total = rs6000_cost->fp;
16955 else if (GET_CODE (XEXP (x, 0)) == MULT)
16957 /* The rs6000 doesn't have shift-and-add instructions. */
16958 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16959 *total += COSTS_N_INSNS (1);
16962 *total = COSTS_N_INSNS (1);
16966 if (mode == DFmode)
16968 if (GET_CODE (XEXP (x, 0)) == MULT)
16970 /* FNMA accounted in outer NEG. */
16971 if (outer_code == NEG)
16974 *total = rs6000_cost->dmul;
16977 *total = rs6000_cost->fp;
16979 else if (mode == SFmode)
16981 /* FNMA accounted in outer NEG. */
16982 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16985 *total = rs6000_cost->fp;
16987 else if (GET_CODE (XEXP (x, 0)) == MULT)
16989 /* The rs6000 doesn't have shift-and-sub instructions. */
16990 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
16991 *total += COSTS_N_INSNS (1);
16994 *total = COSTS_N_INSNS (1);
16998 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16999 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
17001 if (INTVAL (XEXP (x, 1)) >= -256
17002 && INTVAL (XEXP (x, 1)) <= 255)
17003 *total = rs6000_cost->mulsi_const9;
17005 *total = rs6000_cost->mulsi_const;
17007 /* FMA accounted in outer PLUS/MINUS. */
17008 else if ((mode == DFmode || mode == SFmode)
17009 && (outer_code == PLUS || outer_code == MINUS))
17011 else if (mode == DFmode)
17012 *total = rs6000_cost->dmul;
17013 else if (mode == SFmode)
17014 *total = rs6000_cost->fp;
17015 else if (mode == DImode)
17016 *total = rs6000_cost->muldi;
17018 *total = rs6000_cost->mulsi;
17023 if (FLOAT_MODE_P (mode))
17025 *total = mode == DFmode ? rs6000_cost->ddiv
17026 : rs6000_cost->sdiv;
17033 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17034 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17036 if (code == DIV || code == MOD)
17038 *total = COSTS_N_INSNS (2);
17041 *total = COSTS_N_INSNS (1);
17045 if (GET_MODE (XEXP (x, 1)) == DImode)
17046 *total = rs6000_cost->divdi;
17048 *total = rs6000_cost->divsi;
17050 /* Add in shift and subtract for MOD. */
17051 if (code == MOD || code == UMOD)
17052 *total += COSTS_N_INSNS (2);
17056 *total = COSTS_N_INSNS (4);
17060 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17071 *total = COSTS_N_INSNS (1);
17079 /* Handle mul_highpart. */
17080 if (outer_code == TRUNCATE
17081 && GET_CODE (XEXP (x, 0)) == MULT)
17083 if (mode == DImode)
17084 *total = rs6000_cost->muldi;
17086 *total = rs6000_cost->mulsi;
17089 else if (outer_code == AND)
17092 *total = COSTS_N_INSNS (1);
17097 if (GET_CODE (XEXP (x, 0)) == MEM)
17100 *total = COSTS_N_INSNS (1);
17106 if (!FLOAT_MODE_P (mode))
17108 *total = COSTS_N_INSNS (1);
17114 case UNSIGNED_FLOAT:
17118 case FLOAT_TRUNCATE:
17119 *total = rs6000_cost->fp;
17123 switch (XINT (x, 1))
17126 *total = rs6000_cost->fp;
17138 *total = COSTS_N_INSNS (1);
17141 else if (FLOAT_MODE_P (mode)
17142 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17144 *total = rs6000_cost->fp;
17152 /* Carry bit requires mode == Pmode.
17153 NEG or PLUS already counted so only add one. */
17155 && (outer_code == NEG || outer_code == PLUS))
17157 *total = COSTS_N_INSNS (1);
17160 if (outer_code == SET)
17162 if (XEXP (x, 1) == const0_rtx)
17164 *total = COSTS_N_INSNS (2);
17167 else if (mode == Pmode)
17169 *total = COSTS_N_INSNS (3);
17178 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17180 *total = COSTS_N_INSNS (2);
17184 if (outer_code == COMPARE)
17198 /* A C expression returning the cost of moving data from a register of class
17199 CLASS1 to one of CLASS2. */
17202 rs6000_register_move_cost (enum machine_mode mode,
17203 enum reg_class from, enum reg_class to)
17205 /* Moves from/to GENERAL_REGS. */
17206 if (reg_classes_intersect_p (to, GENERAL_REGS)
17207 || reg_classes_intersect_p (from, GENERAL_REGS))
17209 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17212 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17213 return (rs6000_memory_move_cost (mode, from, 0)
17214 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17216 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17218 else if (from == CR_REGS)
17222 /* A move will cost one instruction per GPR moved. */
17223 return 2 * HARD_REGNO_NREGS (0, mode);
17226 /* Moving between two similar registers is just one instruction. */
17227 else if (reg_classes_intersect_p (to, from))
17228 return mode == TFmode ? 4 : 2;
17230 /* Everything else has to go through GENERAL_REGS. */
17232 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17233 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17236 /* A C expressions returning the cost of moving data of MODE from a register to
17240 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17241 int in ATTRIBUTE_UNUSED)
17243 if (reg_classes_intersect_p (class, GENERAL_REGS))
17244 return 4 * HARD_REGNO_NREGS (0, mode);
17245 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17246 return 4 * HARD_REGNO_NREGS (32, mode);
17247 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17248 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17250 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17253 /* Return an RTX representing where to find the function value of a
17254 function returning MODE. */
17256 rs6000_complex_function_value (enum machine_mode mode)
17258 unsigned int regno;
17260 enum machine_mode inner = GET_MODE_INNER (mode);
17261 unsigned int inner_bytes = GET_MODE_SIZE (inner);
17263 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17264 regno = FP_ARG_RETURN;
17267 regno = GP_ARG_RETURN;
17269 /* 32-bit is OK since it'll go in r3/r4. */
17270 if (TARGET_32BIT && inner_bytes >= 4)
17271 return gen_rtx_REG (mode, regno);
17274 if (inner_bytes >= 8)
17275 return gen_rtx_REG (mode, regno);
17277 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17279 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
17280 GEN_INT (inner_bytes));
17281 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17284 /* Define how to find the value returned by a function.
17285 VALTYPE is the data type of the value (as a tree).
17286 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17287 otherwise, FUNC is 0.
17289 On the SPE, both FPs and vectors are returned in r3.
17291 On RS/6000 an integer value is in r3 and a floating-point value is in
17292 fp1, unless -msoft-float. */
17295 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17297 enum machine_mode mode;
17298 unsigned int regno;
17300 /* Special handling for structs in darwin64. */
17301 if (rs6000_darwin64_abi
17302 && TYPE_MODE (valtype) == BLKmode
17303 && TREE_CODE (valtype) == RECORD_TYPE
17304 && int_size_in_bytes (valtype) > 0)
17306 CUMULATIVE_ARGS valcum;
17310 valcum.fregno = FP_ARG_MIN_REG;
17311 valcum.vregno = ALTIVEC_ARG_MIN_REG;
17312 /* Do a trial code generation as if this were going to be passed as
17313 an argument; if any part goes in memory, we return NULL. */
17314 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
17317 /* Otherwise fall through to standard ABI rules. */
17320 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17322 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17323 return gen_rtx_PARALLEL (DImode,
17325 gen_rtx_EXPR_LIST (VOIDmode,
17326 gen_rtx_REG (SImode, GP_ARG_RETURN),
17328 gen_rtx_EXPR_LIST (VOIDmode,
17329 gen_rtx_REG (SImode,
17330 GP_ARG_RETURN + 1),
17334 if ((INTEGRAL_TYPE_P (valtype)
17335 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17336 || POINTER_TYPE_P (valtype))
17337 mode = TARGET_32BIT ? SImode : DImode;
17339 mode = TYPE_MODE (valtype);
17341 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
17342 regno = FP_ARG_RETURN;
17343 else if (TREE_CODE (valtype) == COMPLEX_TYPE
17344 && targetm.calls.split_complex_arg)
17345 return rs6000_complex_function_value (mode);
17346 else if (TREE_CODE (valtype) == VECTOR_TYPE
17347 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
17348 && ALTIVEC_VECTOR_MODE (mode))
17349 regno = ALTIVEC_ARG_RETURN;
17350 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17351 && (mode == DFmode || mode == DCmode))
17352 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17354 regno = GP_ARG_RETURN;
17356 return gen_rtx_REG (mode, regno);
17359 /* Define how to find the value returned by a library function
17360 assuming the value has mode MODE. */
17362 rs6000_libcall_value (enum machine_mode mode)
17364 unsigned int regno;
17366 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17368 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17369 return gen_rtx_PARALLEL (DImode,
17371 gen_rtx_EXPR_LIST (VOIDmode,
17372 gen_rtx_REG (SImode, GP_ARG_RETURN),
17374 gen_rtx_EXPR_LIST (VOIDmode,
17375 gen_rtx_REG (SImode,
17376 GP_ARG_RETURN + 1),
17380 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17381 && TARGET_HARD_FLOAT && TARGET_FPRS)
17382 regno = FP_ARG_RETURN;
17383 else if (ALTIVEC_VECTOR_MODE (mode)
17384 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
17385 regno = ALTIVEC_ARG_RETURN;
17386 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
17387 return rs6000_complex_function_value (mode);
17388 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17389 && (mode == DFmode || mode == DCmode))
17390 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17392 regno = GP_ARG_RETURN;
17394 return gen_rtx_REG (mode, regno);
17397 /* Define the offset between two registers, FROM to be eliminated and its
17398 replacement TO, at the start of a routine. */
17400 rs6000_initial_elimination_offset (int from, int to)
17402 rs6000_stack_t *info = rs6000_stack_info ();
17403 HOST_WIDE_INT offset;
17405 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17406 offset = info->push_p ? 0 : -info->total_size;
17407 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17408 offset = info->total_size;
17409 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17410 offset = info->push_p ? info->total_size : 0;
17411 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17419 /* Return true if TYPE is of type __ev64_opaque__. */
17422 is_ev64_opaque_type (tree type)
17425 && (type == opaque_V2SI_type_node
17426 || type == opaque_V2SF_type_node
17427 || type == opaque_p_V2SI_type_node));
17431 rs6000_dwarf_register_span (rtx reg)
17436 && (SPE_VECTOR_MODE (GET_MODE (reg))
17437 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17442 regno = REGNO (reg);
17444 /* The duality of the SPE register size wreaks all kinds of havoc.
17445 This is a way of distinguishing r0 in 32-bits from r0 in
17448 gen_rtx_PARALLEL (VOIDmode,
17451 gen_rtx_REG (SImode, regno + 1200),
17452 gen_rtx_REG (SImode, regno))
17454 gen_rtx_REG (SImode, regno),
17455 gen_rtx_REG (SImode, regno + 1200)));
17458 /* Map internal gcc register numbers to DWARF2 register numbers. */
17461 rs6000_dbx_register_number (unsigned int regno)
17463 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17465 if (regno == MQ_REGNO)
17467 if (regno == LINK_REGISTER_REGNUM)
17469 if (regno == COUNT_REGISTER_REGNUM)
17471 if (CR_REGNO_P (regno))
17472 return regno - CR0_REGNO + 86;
17473 if (regno == XER_REGNO)
17475 if (ALTIVEC_REGNO_P (regno))
17476 return regno - FIRST_ALTIVEC_REGNO + 1124;
17477 if (regno == VRSAVE_REGNO)
17479 if (regno == VSCR_REGNO)
17481 if (regno == SPE_ACC_REGNO)
17483 if (regno == SPEFSCR_REGNO)
17485 /* SPE high reg number. We get these values of regno from
17486 rs6000_dwarf_register_span. */
17487 if (regno >= 1200 && regno < 1232)
17493 /* target hook eh_return_filter_mode */
17494 static enum machine_mode
17495 rs6000_eh_return_filter_mode (void)
17497 return TARGET_32BIT ? SImode : word_mode;
17500 /* Target hook for vector_mode_supported_p. */
17502 rs6000_vector_mode_supported_p (enum machine_mode mode)
17505 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17508 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17515 #include "gt-rs6000.h"