1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (and (match_operand 0 "register_operand")
37 (match_test "GET_CODE (op) != REG
38 || ALTIVEC_REGNO_P (REGNO (op))
39 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
41 ;; Return 1 if op is XER register.
42 (define_predicate "xer_operand"
43 (and (match_code "reg")
44 (match_test "XER_REGNO_P (REGNO (op))")))
46 ;; Return 1 if op is a signed 5-bit constant integer.
47 (define_predicate "s5bit_cint_operand"
48 (and (match_code "const_int")
49 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
51 ;; Return 1 if op is a unsigned 5-bit constant integer.
52 (define_predicate "u5bit_cint_operand"
53 (and (match_code "const_int")
54 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
56 ;; Return 1 if op is a signed 8-bit constant integer.
57 ;; Integer multiplication complete more quickly
58 (define_predicate "s8bit_cint_operand"
59 (and (match_code "const_int")
60 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
62 ;; Return 1 if op is a constant integer that can fit in a D field.
63 (define_predicate "short_cint_operand"
64 (and (match_code "const_int")
65 (match_test "satisfies_constraint_I (op)")))
67 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
68 (define_predicate "u_short_cint_operand"
69 (and (match_code "const_int")
70 (match_test "satisfies_constraint_K (op)")))
72 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
73 (define_predicate "non_short_cint_operand"
74 (and (match_code "const_int")
75 (match_test "(unsigned HOST_WIDE_INT)
76 (INTVAL (op) + 0x8000) >= 0x10000")))
78 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
79 (define_predicate "exact_log2_cint_operand"
80 (and (match_code "const_int")
81 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
83 ;; Return 1 if op is a register that is not special.
84 (define_predicate "gpc_reg_operand"
85 (and (match_operand 0 "register_operand")
86 (match_test "(GET_CODE (op) != REG
87 || (REGNO (op) >= ARG_POINTER_REGNUM
88 && !XER_REGNO_P (REGNO (op)))
89 || REGNO (op) < MQ_REGNO)
90 && !((TARGET_E500_DOUBLE || TARGET_SPE)
91 && invalid_e500_subreg (op, mode))")))
93 ;; Return 1 if op is a register that is a condition register field.
94 (define_predicate "cc_reg_operand"
95 (and (match_operand 0 "register_operand")
96 (match_test "GET_CODE (op) != REG
97 || REGNO (op) > LAST_VIRTUAL_REGISTER
98 || CR_REGNO_P (REGNO (op))")))
100 ;; Return 1 if op is a register that is a condition register field not cr0.
101 (define_predicate "cc_reg_not_cr0_operand"
102 (and (match_operand 0 "register_operand")
103 (match_test "GET_CODE (op) != REG
104 || REGNO (op) > LAST_VIRTUAL_REGISTER
105 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
107 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
108 (define_predicate "cc_reg_not_micro_cr0_operand"
109 (and (match_operand 0 "register_operand")
110 (match_test "GET_CODE (op) != REG
111 || REGNO (op) > LAST_VIRTUAL_REGISTER
112 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
113 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
115 ;; Return 1 if op is a constant integer valid for D field
116 ;; or non-special register register.
117 (define_predicate "reg_or_short_operand"
118 (if_then_else (match_code "const_int")
119 (match_operand 0 "short_cint_operand")
120 (match_operand 0 "gpc_reg_operand")))
122 ;; Return 1 if op is a constant integer valid whose negation is valid for
123 ;; D field or non-special register register.
124 ;; Do not allow a constant zero because all patterns that call this
125 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
126 ;; or equal to const, which does not work for zero.
127 (define_predicate "reg_or_neg_short_operand"
128 (if_then_else (match_code "const_int")
129 (match_test "satisfies_constraint_P (op)
130 && INTVAL (op) != 0")
131 (match_operand 0 "gpc_reg_operand")))
133 ;; Return 1 if op is a constant integer valid for DS field
134 ;; or non-special register.
135 (define_predicate "reg_or_aligned_short_operand"
136 (if_then_else (match_code "const_int")
137 (and (match_operand 0 "short_cint_operand")
138 (match_test "!(INTVAL (op) & 3)"))
139 (match_operand 0 "gpc_reg_operand")))
141 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
142 ;; or non-special register.
143 (define_predicate "reg_or_u_short_operand"
144 (if_then_else (match_code "const_int")
145 (match_operand 0 "u_short_cint_operand")
146 (match_operand 0 "gpc_reg_operand")))
148 ;; Return 1 if op is any constant integer
149 ;; or non-special register.
150 (define_predicate "reg_or_cint_operand"
151 (ior (match_code "const_int")
152 (match_operand 0 "gpc_reg_operand")))
154 ;; Return 1 if op is a constant integer valid for addition
155 ;; or non-special register.
156 (define_predicate "reg_or_add_cint_operand"
157 (if_then_else (match_code "const_int")
158 (match_test "(HOST_BITS_PER_WIDE_INT == 32
159 && (mode == SImode || INTVAL (op) < 0x7fff8000))
160 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
161 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
162 (match_operand 0 "gpc_reg_operand")))
164 ;; Return 1 if op is a constant integer valid for subtraction
165 ;; or non-special register.
166 (define_predicate "reg_or_sub_cint_operand"
167 (if_then_else (match_code "const_int")
168 (match_test "(HOST_BITS_PER_WIDE_INT == 32
169 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
170 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
172 ? 0x80000000 : 0x80008000))
173 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
174 (match_operand 0 "gpc_reg_operand")))
176 ;; Return 1 if op is any 32-bit unsigned constant integer
177 ;; or non-special register.
178 (define_predicate "reg_or_logical_cint_operand"
179 (if_then_else (match_code "const_int")
180 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
182 || ((INTVAL (op) & GET_MODE_MASK (mode)
183 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
184 (if_then_else (match_code "const_double")
185 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
187 && CONST_DOUBLE_HIGH (op) == 0")
188 (match_operand 0 "gpc_reg_operand"))))
190 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
191 ;; with no more than one instruction per word.
192 (define_predicate "easy_fp_constant"
193 (match_code "const_double")
198 if (GET_MODE (op) != mode
199 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
202 /* Consider all constants with -msoft-float to be easy. */
203 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
204 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
208 if (DECIMAL_FLOAT_MODE_P (mode))
211 /* If we are using V.4 style PIC, consider all constants to be hard. */
212 if (flag_pic && DEFAULT_ABI == ABI_V4)
215 #ifdef TARGET_RELOCATABLE
216 /* Similarly if we are using -mrelocatable, consider all constants
218 if (TARGET_RELOCATABLE)
225 if (TARGET_E500_DOUBLE)
228 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
229 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
231 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
232 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
233 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
234 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
237 /* Force constants to memory before reload to utilize
238 compress_float_constant.
239 Avoid this when flag_unsafe_math_optimizations is enabled
240 because RDIV division to reciprocal optimization is not able
241 to regenerate the division. */
242 if (TARGET_E500_DOUBLE
243 || (!reload_in_progress && !reload_completed
244 && !flag_unsafe_math_optimizations))
247 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
248 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
250 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
251 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
254 /* The constant 0.f is easy. */
255 if (op == CONST0_RTX (SFmode))
258 /* Force constants to memory before reload to utilize
259 compress_float_constant.
260 Avoid this when flag_unsafe_math_optimizations is enabled
261 because RDIV division to reciprocal optimization is not able
262 to regenerate the division. */
263 if (!reload_in_progress && !reload_completed
264 && !flag_unsafe_math_optimizations)
267 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
268 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
270 return num_insns_constant_wide (k[0]) == 1;
273 return ((TARGET_POWERPC64
274 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
275 || (num_insns_constant (op, DImode) <= 2));
285 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
286 ;; vector register without using memory.
287 (define_predicate "easy_vector_constant"
288 (match_code "const_vector")
290 /* As the paired vectors are actually FPRs it seems that there is
291 no easy way to load a CONST_VECTOR without using memory. */
292 if (TARGET_PAIRED_FLOAT)
295 if (ALTIVEC_VECTOR_MODE (mode))
297 if (zero_constant (op, mode))
299 return easy_altivec_constant (op, mode);
302 if (SPE_VECTOR_MODE (mode))
305 if (zero_constant (op, mode))
307 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
310 /* Limit SPE vectors to 15 bits signed. These we can generate with:
315 I don't know how efficient it would be to allow bigger constants,
316 considering we'll have an extra 'ori' for every 'li'. I doubt 5
317 instructions is better than a 64-bit memory load, but I don't
318 have the e500 timing specs. */
319 if (mode == V2SImode)
321 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
322 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
323 return cst >= -0x7fff && cst <= 0x7fff
324 && cst2 >= -0x7fff && cst2 <= 0x7fff;
331 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
332 (define_predicate "easy_vector_constant_add_self"
333 (and (match_code "const_vector")
334 (and (match_test "TARGET_ALTIVEC")
335 (match_test "easy_altivec_constant (op, mode)")))
337 HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
338 val = ((val & 0xff) ^ 0x80) - 0x80;
339 return EASY_VECTOR_15_ADD_SELF (val);
342 ;; Return 1 if operand is constant zero (scalars and vectors).
343 (define_predicate "zero_constant"
344 (and (match_code "const_int,const_double,const_vector")
345 (match_test "op == CONST0_RTX (mode)")))
347 ;; Return 1 if operand is 0.0.
348 ;; or non-special register register field no cr0
349 (define_predicate "zero_fp_constant"
350 (and (match_code "const_double")
351 (match_test "SCALAR_FLOAT_MODE_P (mode)
352 && op == CONST0_RTX (mode)")))
354 ;; Return 1 if the operand is in volatile memory. Note that during the
355 ;; RTL generation phase, memory_operand does not return TRUE for volatile
356 ;; memory references. So this function allows us to recognize volatile
357 ;; references where it's safe.
358 (define_predicate "volatile_mem_operand"
359 (and (and (match_code "mem")
360 (match_test "MEM_VOLATILE_P (op)"))
361 (if_then_else (match_test "reload_completed")
362 (match_operand 0 "memory_operand")
363 (if_then_else (match_test "reload_in_progress")
364 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
365 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
367 ;; Return 1 if the operand is an offsettable memory operand.
368 (define_predicate "offsettable_mem_operand"
369 (and (match_operand 0 "memory_operand")
370 (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC
371 && GET_CODE (XEXP (op, 0)) != PRE_DEC
372 && GET_CODE (XEXP (op, 0)) != PRE_MODIFY")))
374 ;; Return 1 if the operand is a memory operand with an address divisible by 4
375 (define_predicate "word_offset_memref_operand"
376 (match_operand 0 "memory_operand")
378 /* Address inside MEM. */
381 /* Extract address from auto-inc/dec. */
382 if (GET_CODE (op) == PRE_INC
383 || GET_CODE (op) == PRE_DEC)
385 else if (GET_CODE (op) == PRE_MODIFY)
388 return (GET_CODE (op) != PLUS
389 || ! REG_P (XEXP (op, 0))
390 || GET_CODE (XEXP (op, 1)) != CONST_INT
391 || INTVAL (XEXP (op, 1)) % 4 == 0);
394 ;; Return 1 if the operand is an indexed or indirect memory operand.
395 (define_predicate "indexed_or_indirect_operand"
400 && ALTIVEC_VECTOR_MODE (mode)
401 && GET_CODE (op) == AND
402 && GET_CODE (XEXP (op, 1)) == CONST_INT
403 && INTVAL (XEXP (op, 1)) == -16)
406 return indexed_or_indirect_address (op, mode);
409 ;; Return 1 if the operand is an indexed or indirect address.
410 (define_special_predicate "indexed_or_indirect_address"
411 (and (match_test "REG_P (op)
412 || (GET_CODE (op) == PLUS
413 /* Omit testing REG_P (XEXP (op, 0)). */
414 && REG_P (XEXP (op, 1)))")
415 (match_operand 0 "address_operand")))
417 ;; Used for the destination of the fix_truncdfsi2 expander.
418 ;; If stfiwx will be used, the result goes to memory; otherwise,
419 ;; we're going to emit a store and a load of a subreg, so the dest is a
421 (define_predicate "fix_trunc_dest_operand"
422 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
423 (match_operand 0 "memory_operand")
424 (match_operand 0 "gpc_reg_operand")))
426 ;; Return 1 if the operand is either a non-special register or can be used
427 ;; as the operand of a `mode' add insn.
428 (define_predicate "add_operand"
429 (if_then_else (match_code "const_int")
430 (match_test "satisfies_constraint_I (op)
431 || satisfies_constraint_L (op)")
432 (match_operand 0 "gpc_reg_operand")))
434 ;; Return 1 if OP is a constant but not a valid add_operand.
435 (define_predicate "non_add_cint_operand"
436 (and (match_code "const_int")
437 (match_test "!satisfies_constraint_I (op)
438 && !satisfies_constraint_L (op)")))
440 ;; Return 1 if the operand is a constant that can be used as the operand
442 (define_predicate "logical_const_operand"
443 (match_code "const_int,const_double")
445 HOST_WIDE_INT opl, oph;
447 if (GET_CODE (op) == CONST_INT)
449 opl = INTVAL (op) & GET_MODE_MASK (mode);
451 if (HOST_BITS_PER_WIDE_INT <= 32
452 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
455 else if (GET_CODE (op) == CONST_DOUBLE)
457 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
459 opl = CONST_DOUBLE_LOW (op);
460 oph = CONST_DOUBLE_HIGH (op);
467 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
468 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
471 ;; Return 1 if the operand is a non-special register or a constant that
472 ;; can be used as the operand of an OR or XOR.
473 (define_predicate "logical_operand"
474 (ior (match_operand 0 "gpc_reg_operand")
475 (match_operand 0 "logical_const_operand")))
477 ;; Return 1 if op is a constant that is not a logical operand, but could
478 ;; be split into one.
479 (define_predicate "non_logical_cint_operand"
480 (and (match_code "const_int,const_double")
481 (and (not (match_operand 0 "logical_operand"))
482 (match_operand 0 "reg_or_logical_cint_operand"))))
484 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
485 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
486 ;; transitions). Reject all ones and all zeros, since these should have
487 ;; been optimized away and confuse the making of MB and ME.
488 (define_predicate "mask_operand"
489 (match_code "const_int")
491 HOST_WIDE_INT c, lsb;
495 if (TARGET_POWERPC64)
497 /* Fail if the mask is not 32-bit. */
498 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
501 /* Fail if the mask wraps around because the upper 32-bits of the
502 mask will all be 1s, contrary to GCC's internal view. */
503 if ((c & 0x80000001) == 0x80000001)
507 /* We don't change the number of transitions by inverting,
508 so make sure we start with the LS bit zero. */
512 /* Reject all zeros or all ones. */
516 /* Find the first transition. */
519 /* Invert to look for a second transition. */
522 /* Erase first transition. */
525 /* Find the second transition (if any). */
528 /* Match if all the bits above are 1's (or c is zero). */
532 ;; Return 1 for the PowerPC64 rlwinm corner case.
533 (define_predicate "mask_operand_wrap"
534 (match_code "const_int")
536 HOST_WIDE_INT c, lsb;
540 if ((c & 0x80000001) != 0x80000001)
554 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
555 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
556 ;; transition). Reject all zeros, since zero should have been
557 ;; optimized away and confuses the making of MB and ME.
558 (define_predicate "mask64_operand"
559 (match_code "const_int")
561 HOST_WIDE_INT c, lsb;
565 /* Reject all zeros. */
569 /* We don't change the number of transitions by inverting,
570 so make sure we start with the LS bit zero. */
574 /* Find the first transition. */
577 /* Match if all the bits above are 1's (or c is zero). */
581 ;; Like mask64_operand, but allow up to three transitions. This
582 ;; predicate is used by insn patterns that generate two rldicl or
583 ;; rldicr machine insns.
584 (define_predicate "mask64_2_operand"
585 (match_code "const_int")
587 HOST_WIDE_INT c, lsb;
591 /* Disallow all zeros. */
595 /* We don't change the number of transitions by inverting,
596 so make sure we start with the LS bit zero. */
600 /* Find the first transition. */
603 /* Invert to look for a second transition. */
606 /* Erase first transition. */
609 /* Find the second transition. */
612 /* Invert to look for a third transition. */
615 /* Erase second transition. */
618 /* Find the third transition (if any). */
621 /* Match if all the bits above are 1's (or c is zero). */
625 ;; Like and_operand, but also match constants that can be implemented
626 ;; with two rldicl or rldicr insns.
627 (define_predicate "and64_2_operand"
628 (ior (match_operand 0 "mask64_2_operand")
629 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
630 (match_operand 0 "gpc_reg_operand")
631 (match_operand 0 "logical_operand"))))
633 ;; Return 1 if the operand is either a non-special register or a
634 ;; constant that can be used as the operand of a logical AND.
635 (define_predicate "and_operand"
636 (ior (match_operand 0 "mask_operand")
637 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
638 (match_operand 0 "mask64_operand"))
639 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
640 (match_operand 0 "gpc_reg_operand")
641 (match_operand 0 "logical_operand")))))
643 ;; Return 1 if the operand is either a logical operand or a short cint operand.
644 (define_predicate "scc_eq_operand"
645 (ior (match_operand 0 "logical_operand")
646 (match_operand 0 "short_cint_operand")))
648 ;; Return 1 if the operand is a general non-special register or memory operand.
649 (define_predicate "reg_or_mem_operand"
650 (ior (match_operand 0 "memory_operand")
651 (ior (and (match_code "mem")
652 (match_test "macho_lo_sum_memory_operand (op, mode)"))
653 (ior (match_operand 0 "volatile_mem_operand")
654 (match_operand 0 "gpc_reg_operand")))))
656 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
657 (define_predicate "reg_or_none500mem_operand"
658 (if_then_else (match_code "mem")
659 (and (match_test "!TARGET_E500_DOUBLE")
660 (ior (match_operand 0 "memory_operand")
661 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
662 (match_operand 0 "volatile_mem_operand"))))
663 (match_operand 0 "gpc_reg_operand")))
665 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
666 (define_predicate "zero_reg_mem_operand"
667 (ior (match_operand 0 "zero_fp_constant")
668 (match_operand 0 "reg_or_mem_operand")))
670 ;; Return 1 if the operand is a general register or memory operand without
671 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
673 (define_predicate "lwa_operand"
674 (match_code "reg,subreg,mem")
678 if (reload_completed && GET_CODE (inner) == SUBREG)
679 inner = SUBREG_REG (inner);
681 return gpc_reg_operand (inner, mode)
682 || (memory_operand (inner, mode)
683 && GET_CODE (XEXP (inner, 0)) != PRE_INC
684 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
685 && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
686 || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
687 && (GET_CODE (XEXP (inner, 0)) != PLUS
688 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
689 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
692 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
693 (define_predicate "symbol_ref_operand"
694 (and (match_code "symbol_ref")
695 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
696 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
698 ;; Return 1 if op is an operand that can be loaded via the GOT.
699 ;; or non-special register register field no cr0
700 (define_predicate "got_operand"
701 (match_code "symbol_ref,const,label_ref"))
703 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
704 ;; excluding labels involving addition.
705 (define_predicate "got_no_const_operand"
706 (match_code "symbol_ref,label_ref"))
708 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
709 (define_predicate "rs6000_tls_symbol_ref"
710 (and (match_code "symbol_ref")
711 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
713 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
714 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
715 (define_predicate "call_operand"
716 (if_then_else (match_code "reg")
717 (match_test "REGNO (op) == LR_REGNO
718 || REGNO (op) == CTR_REGNO
719 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
720 (match_code "symbol_ref")))
722 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
724 (define_predicate "current_file_function_operand"
725 (and (match_code "symbol_ref")
726 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
727 && ((SYMBOL_REF_LOCAL_P (op)
728 && (DEFAULT_ABI != ABI_AIX
729 || !SYMBOL_REF_EXTERNAL_P (op)))
730 || (op == XEXP (DECL_RTL (current_function_decl),
733 ;; Return 1 if this operand is a valid input for a move insn.
734 (define_predicate "input_operand"
735 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
736 const_double,const_vector,const_int,plus")
738 /* Memory is always valid. */
739 if (memory_operand (op, mode))
742 /* For floating-point, easy constants are valid. */
743 if (SCALAR_FLOAT_MODE_P (mode)
745 && easy_fp_constant (op, mode))
748 /* Allow any integer constant. */
749 if (GET_MODE_CLASS (mode) == MODE_INT
750 && (GET_CODE (op) == CONST_INT
751 || GET_CODE (op) == CONST_DOUBLE))
754 /* Allow easy vector constants. */
755 if (GET_CODE (op) == CONST_VECTOR
756 && easy_vector_constant (op, mode))
759 /* Do not allow invalid E500 subregs. */
760 if ((TARGET_E500_DOUBLE || TARGET_SPE)
761 && GET_CODE (op) == SUBREG
762 && invalid_e500_subreg (op, mode))
765 /* For floating-point or multi-word mode, the only remaining valid type
767 if (SCALAR_FLOAT_MODE_P (mode)
768 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
769 return register_operand (op, mode);
771 /* The only cases left are integral modes one word or smaller (we
772 do not get called for MODE_CC values). These can be in any
774 if (register_operand (op, mode))
777 /* A SYMBOL_REF referring to the TOC is valid. */
778 if (legitimate_constant_pool_address_p (op))
781 /* A constant pool expression (relative to the TOC) is valid */
782 if (toc_relative_expr_p (op))
785 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
787 if (DEFAULT_ABI == ABI_V4
788 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
789 && small_data_operand (op, Pmode))
795 ;; Return true if OP is an invalid SUBREG operation on the e500.
796 (define_predicate "rs6000_nonimmediate_operand"
797 (match_code "reg,subreg,mem")
799 if ((TARGET_E500_DOUBLE || TARGET_SPE)
800 && GET_CODE (op) == SUBREG
801 && invalid_e500_subreg (op, mode))
804 return nonimmediate_operand (op, mode);
807 ;; Return true if operand is boolean operator.
808 (define_predicate "boolean_operator"
809 (match_code "and,ior,xor"))
811 ;; Return true if operand is OR-form of boolean operator.
812 (define_predicate "boolean_or_operator"
813 (match_code "ior,xor"))
815 ;; Return true if operand is an equality operator.
816 (define_special_predicate "equality_operator"
817 (match_code "eq,ne"))
819 ;; Return true if operand is MIN or MAX operator.
820 (define_predicate "min_max_operator"
821 (match_code "smin,smax,umin,umax"))
823 ;; Return 1 if OP is a comparison operation that is valid for a branch
824 ;; instruction. We check the opcode against the mode of the CC value.
825 ;; validate_condition_mode is an assertion.
826 (define_predicate "branch_comparison_operator"
827 (and (match_operand 0 "comparison_operator")
828 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
829 (match_test "validate_condition_mode (GET_CODE (op),
830 GET_MODE (XEXP (op, 0))),
833 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
834 ;; it must be a positive comparison.
835 (define_predicate "scc_comparison_operator"
836 (and (match_operand 0 "branch_comparison_operator")
837 (match_code "eq,lt,gt,ltu,gtu,unordered")))
839 ;; Return 1 if OP is a comparison operation that is valid for a branch
840 ;; insn, which is true if the corresponding bit in the CC register is set.
841 (define_predicate "branch_positive_comparison_operator"
842 (and (match_operand 0 "branch_comparison_operator")
843 (match_code "eq,lt,gt,ltu,gtu,unordered")))
845 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
846 (define_predicate "trap_comparison_operator"
847 (and (match_operand 0 "comparison_operator")
848 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
850 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
851 (define_predicate "load_multiple_operation"
852 (match_code "parallel")
854 int count = XVECLEN (op, 0);
855 unsigned int dest_regno;
859 /* Perform a quick check so we don't blow up below. */
861 || GET_CODE (XVECEXP (op, 0, 0)) != SET
862 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
863 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
866 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
867 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
869 for (i = 1; i < count; i++)
871 rtx elt = XVECEXP (op, 0, i);
873 if (GET_CODE (elt) != SET
874 || GET_CODE (SET_DEST (elt)) != REG
875 || GET_MODE (SET_DEST (elt)) != SImode
876 || REGNO (SET_DEST (elt)) != dest_regno + i
877 || GET_CODE (SET_SRC (elt)) != MEM
878 || GET_MODE (SET_SRC (elt)) != SImode
879 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
880 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
881 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
882 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
889 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
890 ;; The second vector element is a CLOBBER.
891 (define_predicate "store_multiple_operation"
892 (match_code "parallel")
894 int count = XVECLEN (op, 0) - 1;
895 unsigned int src_regno;
899 /* Perform a quick check so we don't blow up below. */
901 || GET_CODE (XVECEXP (op, 0, 0)) != SET
902 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
903 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
906 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
907 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
909 for (i = 1; i < count; i++)
911 rtx elt = XVECEXP (op, 0, i + 1);
913 if (GET_CODE (elt) != SET
914 || GET_CODE (SET_SRC (elt)) != REG
915 || GET_MODE (SET_SRC (elt)) != SImode
916 || REGNO (SET_SRC (elt)) != src_regno + i
917 || GET_CODE (SET_DEST (elt)) != MEM
918 || GET_MODE (SET_DEST (elt)) != SImode
919 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
920 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
921 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
922 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
929 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
931 (define_predicate "save_world_operation"
932 (match_code "parallel")
937 int count = XVECLEN (op, 0);
943 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
944 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
947 for (i=1; i <= 18; i++)
949 elt = XVECEXP (op, 0, index++);
950 if (GET_CODE (elt) != SET
951 || GET_CODE (SET_DEST (elt)) != MEM
952 || ! memory_operand (SET_DEST (elt), DFmode)
953 || GET_CODE (SET_SRC (elt)) != REG
954 || GET_MODE (SET_SRC (elt)) != DFmode)
958 for (i=1; i <= 12; i++)
960 elt = XVECEXP (op, 0, index++);
961 if (GET_CODE (elt) != SET
962 || GET_CODE (SET_DEST (elt)) != MEM
963 || GET_CODE (SET_SRC (elt)) != REG
964 || GET_MODE (SET_SRC (elt)) != V4SImode)
968 for (i=1; i <= 19; i++)
970 elt = XVECEXP (op, 0, index++);
971 if (GET_CODE (elt) != SET
972 || GET_CODE (SET_DEST (elt)) != MEM
973 || ! memory_operand (SET_DEST (elt), Pmode)
974 || GET_CODE (SET_SRC (elt)) != REG
975 || GET_MODE (SET_SRC (elt)) != Pmode)
979 elt = XVECEXP (op, 0, index++);
980 if (GET_CODE (elt) != SET
981 || GET_CODE (SET_DEST (elt)) != MEM
982 || ! memory_operand (SET_DEST (elt), Pmode)
983 || GET_CODE (SET_SRC (elt)) != REG
984 || REGNO (SET_SRC (elt)) != CR2_REGNO
985 || GET_MODE (SET_SRC (elt)) != Pmode)
988 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
989 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
994 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
996 (define_predicate "restore_world_operation"
997 (match_code "parallel")
1002 int count = XVECLEN (op, 0);
1008 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1009 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1010 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1011 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1014 elt = XVECEXP (op, 0, index++);
1015 if (GET_CODE (elt) != SET
1016 || GET_CODE (SET_SRC (elt)) != MEM
1017 || ! memory_operand (SET_SRC (elt), Pmode)
1018 || GET_CODE (SET_DEST (elt)) != REG
1019 || REGNO (SET_DEST (elt)) != CR2_REGNO
1020 || GET_MODE (SET_DEST (elt)) != Pmode)
1023 for (i=1; i <= 19; i++)
1025 elt = XVECEXP (op, 0, index++);
1026 if (GET_CODE (elt) != SET
1027 || GET_CODE (SET_SRC (elt)) != MEM
1028 || ! memory_operand (SET_SRC (elt), Pmode)
1029 || GET_CODE (SET_DEST (elt)) != REG
1030 || GET_MODE (SET_DEST (elt)) != Pmode)
1034 for (i=1; i <= 12; i++)
1036 elt = XVECEXP (op, 0, index++);
1037 if (GET_CODE (elt) != SET
1038 || GET_CODE (SET_SRC (elt)) != MEM
1039 || GET_CODE (SET_DEST (elt)) != REG
1040 || GET_MODE (SET_DEST (elt)) != V4SImode)
1044 for (i=1; i <= 18; i++)
1046 elt = XVECEXP (op, 0, index++);
1047 if (GET_CODE (elt) != SET
1048 || GET_CODE (SET_SRC (elt)) != MEM
1049 || ! memory_operand (SET_SRC (elt), DFmode)
1050 || GET_CODE (SET_DEST (elt)) != REG
1051 || GET_MODE (SET_DEST (elt)) != DFmode)
1055 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1056 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1057 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1058 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1059 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1064 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1065 (define_predicate "vrsave_operation"
1066 (match_code "parallel")
1068 int count = XVECLEN (op, 0);
1069 unsigned int dest_regno, src_regno;
1073 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1074 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1075 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1076 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1079 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1080 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1082 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1085 for (i = 1; i < count; i++)
1087 rtx elt = XVECEXP (op, 0, i);
1089 if (GET_CODE (elt) != CLOBBER
1090 && GET_CODE (elt) != SET)
1097 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1098 (define_predicate "mfcr_operation"
1099 (match_code "parallel")
1101 int count = XVECLEN (op, 0);
1104 /* Perform a quick check so we don't blow up below. */
1106 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1107 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1108 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1111 for (i = 0; i < count; i++)
1113 rtx exp = XVECEXP (op, 0, i);
1118 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1120 if (GET_CODE (src_reg) != REG
1121 || GET_MODE (src_reg) != CCmode
1122 || ! CR_REGNO_P (REGNO (src_reg)))
1125 if (GET_CODE (exp) != SET
1126 || GET_CODE (SET_DEST (exp)) != REG
1127 || GET_MODE (SET_DEST (exp)) != SImode
1128 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1130 unspec = SET_SRC (exp);
1131 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1133 if (GET_CODE (unspec) != UNSPEC
1134 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1135 || XVECLEN (unspec, 0) != 2
1136 || XVECEXP (unspec, 0, 0) != src_reg
1137 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1138 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1144 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1145 (define_predicate "mtcrf_operation"
1146 (match_code "parallel")
1148 int count = XVECLEN (op, 0);
1152 /* Perform a quick check so we don't blow up below. */
1154 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1155 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1156 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1158 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1160 if (GET_CODE (src_reg) != REG
1161 || GET_MODE (src_reg) != SImode
1162 || ! INT_REGNO_P (REGNO (src_reg)))
1165 for (i = 0; i < count; i++)
1167 rtx exp = XVECEXP (op, 0, i);
1171 if (GET_CODE (exp) != SET
1172 || GET_CODE (SET_DEST (exp)) != REG
1173 || GET_MODE (SET_DEST (exp)) != CCmode
1174 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1176 unspec = SET_SRC (exp);
1177 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1179 if (GET_CODE (unspec) != UNSPEC
1180 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1181 || XVECLEN (unspec, 0) != 2
1182 || XVECEXP (unspec, 0, 0) != src_reg
1183 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1184 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1190 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1191 (define_predicate "lmw_operation"
1192 (match_code "parallel")
1194 int count = XVECLEN (op, 0);
1195 unsigned int dest_regno;
1197 unsigned int base_regno;
1198 HOST_WIDE_INT offset;
1201 /* Perform a quick check so we don't blow up below. */
1203 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1204 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1205 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1208 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1209 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1212 || count != 32 - (int) dest_regno)
1215 if (legitimate_indirect_address_p (src_addr, 0))
1218 base_regno = REGNO (src_addr);
1219 if (base_regno == 0)
1222 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1224 offset = INTVAL (XEXP (src_addr, 1));
1225 base_regno = REGNO (XEXP (src_addr, 0));
1230 for (i = 0; i < count; i++)
1232 rtx elt = XVECEXP (op, 0, i);
1235 HOST_WIDE_INT newoffset;
1237 if (GET_CODE (elt) != SET
1238 || GET_CODE (SET_DEST (elt)) != REG
1239 || GET_MODE (SET_DEST (elt)) != SImode
1240 || REGNO (SET_DEST (elt)) != dest_regno + i
1241 || GET_CODE (SET_SRC (elt)) != MEM
1242 || GET_MODE (SET_SRC (elt)) != SImode)
1244 newaddr = XEXP (SET_SRC (elt), 0);
1245 if (legitimate_indirect_address_p (newaddr, 0))
1250 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1252 addr_reg = XEXP (newaddr, 0);
1253 newoffset = INTVAL (XEXP (newaddr, 1));
1257 if (REGNO (addr_reg) != base_regno
1258 || newoffset != offset + 4 * i)
1265 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1266 (define_predicate "stmw_operation"
1267 (match_code "parallel")
1269 int count = XVECLEN (op, 0);
1270 unsigned int src_regno;
1272 unsigned int base_regno;
1273 HOST_WIDE_INT offset;
1276 /* Perform a quick check so we don't blow up below. */
1278 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1279 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1280 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1283 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1284 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1287 || count != 32 - (int) src_regno)
1290 if (legitimate_indirect_address_p (dest_addr, 0))
1293 base_regno = REGNO (dest_addr);
1294 if (base_regno == 0)
1297 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1299 offset = INTVAL (XEXP (dest_addr, 1));
1300 base_regno = REGNO (XEXP (dest_addr, 0));
1305 for (i = 0; i < count; i++)
1307 rtx elt = XVECEXP (op, 0, i);
1310 HOST_WIDE_INT newoffset;
1312 if (GET_CODE (elt) != SET
1313 || GET_CODE (SET_SRC (elt)) != REG
1314 || GET_MODE (SET_SRC (elt)) != SImode
1315 || REGNO (SET_SRC (elt)) != src_regno + i
1316 || GET_CODE (SET_DEST (elt)) != MEM
1317 || GET_MODE (SET_DEST (elt)) != SImode)
1319 newaddr = XEXP (SET_DEST (elt), 0);
1320 if (legitimate_indirect_address_p (newaddr, 0))
1325 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1327 addr_reg = XEXP (newaddr, 0);
1328 newoffset = INTVAL (XEXP (newaddr, 1));
1332 if (REGNO (addr_reg) != base_regno
1333 || newoffset != offset + 4 * i)