gcc/config/rs6000/power6.md

   1 ;; Scheduling description for IBM POWER6 processor.
   2 ;;   Copyright (C) 2006, 2007 Free Software Foundation, Inc.
   3 ;;   Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Sources:
  22
  23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
  24 ;; (2 engines per chip).  The chip can issue up to 5 internal ops
  25 ;; per cycle.
  26
  27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
  28
  29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
  30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
  31 (define_cpu_unit "bpu_power6" "power6bu")
  32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
  33
  34 (define_reservation "LS2_power6"
  35                     "lsu1_power6+lsu2_power6")
  36
  37 (define_reservation "FPU_power6"
  38                     "fpu1_power6|fpu2_power6")
  39
  40 (define_reservation "BRU_power6"
  41                     "bpu_power6")
  42
  43 (define_reservation "LSU_power6"
  44                     "lsu1_power6|lsu2_power6")
  45
  46 (define_reservation "LSF_power6"
  47                     "(lsu1_power6+fpu1_power6)\
  48                     |(lsu1_power6+fpu2_power6)\
  49                     |(lsu2_power6+fpu1_power6)\
  50                     |(lsu2_power6+fpu2_power6)")
  51
  52 (define_reservation "LX2_power6"
  53                     "(iu1_power6+iu2_power6+lsu1_power6)\
  54                     |(iu1_power6+iu2_power6+lsu2_power6)")
  55
  56 (define_reservation "FX2_power6"
  57                     "iu1_power6+iu2_power6")
  58
  59 (define_reservation "X2F_power6"
  60                     "(iu1_power6+iu2_power6+fpu1_power6)\
  61                     |(iu1_power6+iu2_power6+fpu2_power6)")
  62
  63 (define_reservation "BX2_power6"
  64                     "iu1_power6+iu2_power6+bpu_power6")
  65
  66 (define_reservation "LSX_power6"
  67                     "(iu1_power6+lsu1_power6)\
  68                     |(iu1_power6+lsu2_power6)\
  69                     |(iu2_power6+lsu1_power6)\
  70                     |(iu2_power6+lsu2_power6)")
  71
  72 (define_reservation "FXU_power6"
  73                     "iu1_power6|iu2_power6")
  74
  75 (define_reservation "XLF_power6"
  76                     "(iu1_power6+lsu1_power6+fpu1_power6)\
  77                     |(iu1_power6+lsu1_power6+fpu2_power6)\
  78                     |(iu1_power6+lsu2_power6+fpu1_power6)\
  79                     |(iu1_power6+lsu2_power6+fpu2_power6)\
  80                     |(iu2_power6+lsu1_power6+fpu1_power6)\
  81                     |(iu2_power6+lsu1_power6+fpu2_power6)\
  82                     |(iu2_power6+lsu2_power6+fpu1_power6)\
  83                     |(iu2_power6+lsu2_power6+fpu2_power6)")
  84
  85 (define_reservation "BRX_power6"
  86                     "(bpu_power6+iu1_power6)\
  87                     |(bpu_power6+iu2_power6)")
  88
  89 ; Load/store
  90
  91 ; The default for a value written by a fixed point load
  92 ; that is read/written by a subsequent fixed point op.
  93 (define_insn_reservation "power6-load" 2 ; fx
  94   (and (eq_attr "type" "load")
  95        (eq_attr "cpu" "power6"))
  96   "LSU_power6")
  97
  98 ; define the bypass for the case where the value written
  99 ; by a fixed point load is used as the source value on
 100 ; a store.
 101 (define_bypass 1 "power6-load,\
 102                   power6-load-update,\
 103                   power6-load-update-indexed"
 104                  "power6-store,\
 105                   power6-store-update,\
 106                   power6-store-update-indexed,\
 107                   power6-fpstore,\
 108                   power6-fpstore-update"
 109   "store_data_bypass_p")
 110
 111 (define_insn_reservation "power6-load-ext" 4 ; fx
 112   (and (eq_attr "type" "load_ext")
 113        (eq_attr "cpu" "power6"))
 114   "LSU_power6")
 115
 116 ; define the bypass for the case where the value written
 117 ; by a fixed point load ext is used as the source value on
 118 ; a store.
 119 (define_bypass 1 "power6-load-ext,\
 120                   power6-load-ext-update,\
 121                   power6-load-ext-update-indexed"
 122                  "power6-store,\
 123                   power6-store-update,\
 124                   power6-store-update-indexed,\
 125                   power6-fpstore,\
 126                   power6-fpstore-update"
 127   "store_data_bypass_p")
 128
 129 (define_insn_reservation "power6-load-update" 2 ; fx
 130   (and (eq_attr "type" "load_u")
 131        (eq_attr "cpu" "power6"))
 132   "LSX_power6")
 133
 134 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
 135   (and (eq_attr "type" "load_ux")
 136        (eq_attr "cpu" "power6"))
 137   "LSX_power6")
 138
 139 (define_insn_reservation "power6-load-ext-update" 4 ; fx
 140   (and (eq_attr "type" "load_ext_u")
 141        (eq_attr "cpu" "power6"))
 142   "LSX_power6")
 143
 144 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
 145   (and (eq_attr "type" "load_ext_ux")
 146        (eq_attr "cpu" "power6"))
 147   "LSX_power6")
 148
 149 (define_insn_reservation "power6-fpload" 1
 150   (and (eq_attr "type" "fpload")
 151        (eq_attr "cpu" "power6"))
 152   "LSU_power6")
 153
 154 (define_insn_reservation "power6-fpload-update" 1
 155   (and (eq_attr "type" "fpload_u,fpload_ux")
 156        (eq_attr "cpu" "power6"))
 157   "LSX_power6")
 158
 159 (define_insn_reservation "power6-store" 14
 160   (and (eq_attr "type" "store")
 161        (eq_attr "cpu" "power6"))
 162   "LSU_power6")
 163
 164 (define_insn_reservation "power6-store-update" 14
 165   (and (eq_attr "type" "store_u")
 166        (eq_attr "cpu" "power6"))
 167   "LSX_power6")
 168
 169 (define_insn_reservation "power6-store-update-indexed" 14
 170   (and (eq_attr "type" "store_ux")
 171        (eq_attr "cpu" "power6"))
 172   "LX2_power6")
 173
 174 (define_insn_reservation "power6-fpstore" 14
 175   (and (eq_attr "type" "fpstore")
 176        (eq_attr "cpu" "power6"))
 177   "LSF_power6")
 178
 179 (define_insn_reservation "power6-fpstore-update" 14
 180   (and (eq_attr "type" "fpstore_u,fpstore_ux")
 181        (eq_attr "cpu" "power6"))
 182   "XLF_power6")
 183
 184 (define_insn_reservation "power6-larx" 3
 185   (and (eq_attr "type" "load_l")
 186        (eq_attr "cpu" "power6"))
 187   "LS2_power6")
 188
 189 (define_insn_reservation "power6-stcx" 10 ; best case
 190   (and (eq_attr "type" "store_c")
 191        (eq_attr "cpu" "power6"))
 192   "LSX_power6")
 193
 194 (define_insn_reservation "power6-sync" 11 ; N/A
 195   (and (eq_attr "type" "sync")
 196        (eq_attr "cpu" "power6"))
 197   "LSU_power6")
 198
 199 (define_insn_reservation "power6-integer" 1
 200   (and (eq_attr "type" "integer")
 201        (eq_attr "cpu" "power6"))
 202   "FXU_power6")
 203
 204 (define_insn_reservation "power6-exts" 1
 205   (and (eq_attr "type" "exts")
 206        (eq_attr "cpu" "power6"))
 207   "FXU_power6")
 208
 209 (define_insn_reservation "power6-shift" 1
 210   (and (eq_attr "type" "shift")
 211        (eq_attr "cpu" "power6"))
 212   "FXU_power6")
 213
 214 (define_insn_reservation "power6-insert" 1
 215   (and (eq_attr "type" "insert_word")
 216        (eq_attr "cpu" "power6"))
 217   "FX2_power6")
 218
 219 (define_insn_reservation "power6-insert-dword" 1
 220   (and (eq_attr "type" "insert_dword")
 221        (eq_attr "cpu" "power6"))
 222   "FX2_power6")
 223
 224 ; define the bypass for the case where the value written
 225 ; by a fixed point op is used as the source value on a
 226 ; store.
 227 (define_bypass 1 "power6-integer,\
 228                   power6-exts,\
 229                   power6-shift,\
 230                   power6-insert,\
 231                   power6-insert-dword"
 232                  "power6-store,\
 233                   power6-store-update,\
 234                   power6-store-update-indexed,\
 235                   power6-fpstore,\
 236                   power6-fpstore-update"
 237   "store_data_bypass_p")
 238
 239 (define_insn_reservation "power6-cntlz" 2
 240   (and (eq_attr "type" "cntlz")
 241        (eq_attr "cpu" "power6"))
 242   "FXU_power6")
 243
 244 (define_bypass 1 "power6-cntlz"
 245                  "power6-store,\
 246                   power6-store-update,\
 247                   power6-store-update-indexed,\
 248                   power6-fpstore,\
 249                   power6-fpstore-update"
 250   "store_data_bypass_p")
 251
 252 (define_insn_reservation "power6-var-rotate" 4
 253   (and (eq_attr "type" "var_shift_rotate")
 254        (eq_attr "cpu" "power6"))
 255   "FXU_power6")
 256
 257 (define_insn_reservation "power6-trap" 1 ; N/A
 258   (and (eq_attr "type" "trap")
 259        (eq_attr "cpu" "power6"))
 260   "BRX_power6")
 261
 262 (define_insn_reservation "power6-two" 1
 263   (and (eq_attr "type" "two")
 264        (eq_attr "cpu" "power6"))
 265   "(iu1_power6,iu1_power6)\
 266   |(iu1_power6+iu2_power6,nothing)\
 267   |(iu1_power6,iu2_power6)\
 268   |(iu2_power6,iu1_power6)\
 269   |(iu2_power6,iu2_power6)")
 270
 271 (define_insn_reservation "power6-three" 1
 272   (and (eq_attr "type" "three")
 273        (eq_attr "cpu" "power6"))
 274   "(iu1_power6,iu1_power6,iu1_power6)\
 275   |(iu1_power6,iu1_power6,iu2_power6)\
 276   |(iu1_power6,iu2_power6,iu1_power6)\
 277   |(iu1_power6,iu2_power6,iu2_power6)\
 278   |(iu2_power6,iu1_power6,iu1_power6)\
 279   |(iu2_power6,iu1_power6,iu2_power6)\
 280   |(iu2_power6,iu2_power6,iu1_power6)\
 281   |(iu2_power6,iu2_power6,iu2_power6)\
 282   |(iu1_power6+iu2_power6,iu1_power6)\
 283   |(iu1_power6+iu2_power6,iu2_power6)\
 284   |(iu1_power6,iu1_power6+iu2_power6)\
 285   |(iu2_power6,iu1_power6+iu2_power6)")
 286
 287 (define_insn_reservation "power6-cmp" 1
 288   (and (eq_attr "type" "cmp")
 289        (eq_attr "cpu" "power6"))
 290   "FXU_power6")
 291
 292 (define_insn_reservation "power6-compare" 1
 293   (and (eq_attr "type" "compare")
 294        (eq_attr "cpu" "power6"))
 295   "FXU_power6")
 296
 297 (define_insn_reservation "power6-fast-compare" 1
 298   (and (eq_attr "type" "fast_compare")
 299        (eq_attr "cpu" "power6"))
 300   "FXU_power6")
 301
 302 ; define the bypass for the case where the value written
 303 ; by a fixed point rec form op is used as the source value
 304 ; on a store.
 305 (define_bypass 1 "power6-compare,\
 306                   power6-fast-compare"
 307                  "power6-store,\
 308                   power6-store-update,\
 309                   power6-store-update-indexed,\
 310                   power6-fpstore,\
 311                   power6-fpstore-update"
 312   "store_data_bypass_p")
 313
 314 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
 315   (and (eq_attr "type" "delayed_compare")
 316        (eq_attr "cpu" "power6"))
 317   "FXU_power6")
 318
 319 (define_insn_reservation "power6-var-delayed-compare" 4
 320   (and (eq_attr "type" "var_delayed_compare")
 321        (eq_attr "cpu" "power6"))
 322   "FXU_power6")
 323
 324 (define_insn_reservation "power6-lmul-cmp" 16
 325   (and (eq_attr "type" "lmul_compare")
 326        (eq_attr "cpu" "power6"))
 327   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 328   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 329
 330 (define_insn_reservation "power6-imul-cmp" 16
 331   (and (eq_attr "type" "imul_compare")
 332        (eq_attr "cpu" "power6"))
 333   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 334   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 335
 336 (define_insn_reservation "power6-lmul" 16
 337   (and (eq_attr "type" "lmul")
 338        (eq_attr "cpu" "power6"))
 339   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 340   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 341
 342 (define_insn_reservation "power6-imul" 16
 343   (and (eq_attr "type" "imul")
 344        (eq_attr "cpu" "power6"))
 345   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 346   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 347
 348 (define_insn_reservation "power6-imul3" 16
 349   (and (eq_attr "type" "imul2,imul3")
 350        (eq_attr "cpu" "power6"))
 351   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 352   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 353
 354 (define_bypass 9 "power6-imul,\
 355                   power6-lmul,\
 356                   power6-imul-cmp,\
 357                   power6-lmul-cmp,\
 358                   power6-imul3"
 359                  "power6-store,\
 360                   power6-store-update,\
 361                   power6-store-update-indexed,\
 362                   power6-fpstore,\
 363                   power6-fpstore-update"
 364   "store_data_bypass_p")
 365
 366 (define_insn_reservation "power6-idiv" 44
 367   (and (eq_attr "type" "idiv")
 368        (eq_attr "cpu" "power6"))
 369   "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
 370   |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
 371
 372 ; The latency for this bypass is yet to be defined
 373 ;(define_bypass ? "power6-idiv"
 374 ;                 "power6-store,\
 375 ;                  power6-store-update,\
 376 ;                  power6-store-update-indexed,\
 377 ;                  power6-fpstore,\
 378 ;                  power6-fpstore-update"
 379 ;  "store_data_bypass_p")
 380
 381 (define_insn_reservation "power6-ldiv" 56
 382   (and (eq_attr "type" "ldiv")
 383        (eq_attr "cpu" "power6"))
 384   "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
 385   |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
 386
 387 ; The latency for this bypass is yet to be defined
 388 ;(define_bypass ? "power6-ldiv"
 389 ;                 "power6-store,\
 390 ;                  power6-store-update,\
 391 ;                  power6-store-update-indexed,\
 392 ;                  power6-fpstore,\
 393 ;                  power6-fpstore-update"
 394 ;  "store_data_bypass_p")
 395
 396 (define_insn_reservation "power6-mtjmpr" 2
 397   (and (eq_attr "type" "mtjmpr,mfjmpr")
 398        (eq_attr "cpu" "power6"))
 399   "BX2_power6")
 400
 401 (define_bypass 5 "power6-mtjmpr" "power6-branch")
 402
 403 (define_insn_reservation "power6-branch" 2
 404   (and (eq_attr "type" "jmpreg,branch")
 405        (eq_attr "cpu" "power6"))
 406   "BRU_power6")
 407
 408 (define_bypass 5 "power6-branch" "power6-mtjmpr")
 409
 410 (define_insn_reservation "power6-crlogical" 3
 411   (and (eq_attr "type" "cr_logical")
 412        (eq_attr "cpu" "power6"))
 413   "BRU_power6")
 414
 415 (define_bypass 3 "power6-crlogical" "power6-branch")
 416
 417 (define_insn_reservation "power6-delayedcr" 3
 418   (and (eq_attr "type" "delayed_cr")
 419        (eq_attr "cpu" "power6"))
 420   "BRU_power6")
 421
 422 (define_insn_reservation "power6-mfcr" 6 ; N/A
 423   (and (eq_attr "type" "mfcr")
 424        (eq_attr "cpu" "power6"))
 425   "BX2_power6")
 426
 427 ; mfcrf (1 field)
 428 (define_insn_reservation "power6-mfcrf" 3 ; N/A
 429   (and (eq_attr "type" "mfcrf")
 430        (eq_attr "cpu" "power6"))
 431   "BX2_power6") ;
 432
 433 ; mtcrf (1 field)
 434 (define_insn_reservation "power6-mtcr" 4 ; N/A
 435   (and (eq_attr "type" "mtcr")
 436        (eq_attr "cpu" "power6"))
 437   "BX2_power6")
 438
 439 (define_bypass 9 "power6-mtcr" "power6-branch")
 440
 441 (define_insn_reservation "power6-fp" 6
 442   (and (eq_attr "type" "fp,dmul")
 443        (eq_attr "cpu" "power6"))
 444   "FPU_power6")
 445
 446 ; Any fp instruction that updates a CR has a latency
 447 ; of 6 to a dependent branch
 448 (define_bypass 6 "power6-fp" "power6-branch")
 449
 450 (define_bypass 1 "power6-fp"
 451                  "power6-fpstore,power6-fpstore-update"
 452   "store_data_bypass_p")
 453
 454 (define_insn_reservation "power6-fpcompare" 8
 455   (and (eq_attr "type" "fpcompare")
 456        (eq_attr "cpu" "power6"))
 457   "FPU_power6")
 458
 459 (define_bypass 12 "power6-fpcompare"
 460                   "power6-branch,power6-crlogical")
 461
 462 (define_insn_reservation "power6-sdiv" 26
 463   (and (eq_attr "type" "sdiv")
 464        (eq_attr "cpu" "power6"))
 465   "FPU_power6")
 466
 467 (define_insn_reservation "power6-ddiv" 32
 468   (and (eq_attr "type" "ddiv")
 469        (eq_attr "cpu" "power6"))
 470   "FPU_power6")
 471
 472 (define_insn_reservation "power6-sqrt" 30
 473   (and (eq_attr "type" "ssqrt")
 474        (eq_attr "cpu" "power6"))
 475   "FPU_power6")
 476
 477 (define_insn_reservation "power6-dsqrt" 42
 478   (and (eq_attr "type" "dsqrt")
 479        (eq_attr "cpu" "power6"))
 480   "FPU_power6")
 481
 482 (define_insn_reservation "power6-isync" 2 ; N/A
 483   (and (eq_attr "type" "isync")
 484        (eq_attr "cpu" "power6"))
 485   "FXU_power6")
 486
 487 (define_insn_reservation "power6-vecload" 1
 488   (and (eq_attr "type" "vecload")
 489        (eq_attr "cpu" "power6"))
 490   "LSU_power6")
 491
 492 (define_insn_reservation "power6-vecstore" 1
 493   (and (eq_attr "type" "vecstore")
 494        (eq_attr "cpu" "power6"))
 495   "LSF_power6")
 496
 497 (define_insn_reservation "power6-vecsimple" 3
 498   (and (eq_attr "type" "vecsimple")
 499        (eq_attr "cpu" "power6"))
 500   "FPU_power6")
 501
 502 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
 503                                      power6-vecperm")
 504
 505 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
 506
 507 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
 508
 509 (define_insn_reservation "power6-veccmp" 1
 510   (and (eq_attr "type" "veccmp")
 511        (eq_attr "cpu" "power6"))
 512   "FPU_power6")
 513
 514 (define_bypass 10 "power6-veccmp" "power6-branch")
 515
 516 (define_insn_reservation "power6-vecfloat" 7
 517   (and (eq_attr "type" "vecfloat")
 518        (eq_attr "cpu" "power6"))
 519   "FPU_power6")
 520
 521 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
 522
 523 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
 524                                      power6-vecperm")
 525
 526 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
 527
 528 (define_insn_reservation "power6-veccomplex" 7
 529   (and (eq_attr "type" "vecsimple")
 530        (eq_attr "cpu" "power6"))
 531   "FPU_power6")
 532
 533 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
 534                                        power6-vecfloat" )
 535
 536 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
 537
 538 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
 539
 540 (define_insn_reservation "power6-vecperm" 4
 541   (and (eq_attr "type" "vecperm")
 542        (eq_attr "cpu" "power6"))
 543   "FPU_power6")
 544
 545 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
 546                                    power6-vecfloat" )
 547
 548 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
 549
 550 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
 551
 552 (define_insn_reservation "power6-mftgpr" 8
 553   (and (eq_attr "type" "mftgpr")
 554        (eq_attr "cpu" "power6"))
 555   "X2F_power6")
 556
 557 (define_insn_reservation "power6-mffgpr" 14
 558   (and (eq_attr "type" "mffgpr")
 559        (eq_attr "cpu" "power6"))
 560   "LX2_power6")
 561
 562 (define_bypass 4 "power6-mftgpr" "power6-imul,\
 563                                   power6-lmul,\
 564                                   power6-imul-cmp,\
 565                                   power6-lmul-cmp,\
 566                                   power6-imul3,\
 567                                   power6-idiv,\
 568                                   power6-ldiv" )