gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 2, or (at your
   9 ;; option) any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to the
  18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  19 ;; MA 02111-1307, USA.
  20
  21 ;; Sources: IBM Red Book and White Paper on POWER4
  22
  23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  24 ;; Instructions that update more than one register get broken into two
  25 ;; (split) or more internal ops.  The chip can issue up to 5
  26 ;; internal ops per cycle.
  27
  28 (define_automaton "power4iu,power4fpu,power4vec,power4misc")
  29
  30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
  32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  36                  "power4misc")
  37
  38 (define_reservation "lsq_power4"
  39                     "(du1_power4,lsu1_power4)\
  40                     |(du2_power4,lsu2_power4)\
  41                     |(du3_power4,nothing,lsu2_power4)\
  42                     |(du4_power4,nothing,lsu1_power4)")
  43
  44 (define_reservation "lsuq_power4"
  45                     "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
  46                     |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
  47                     |(du3_power4+du4_power4,lsu2_power4+iu1_power4)")
  48 ;                   |(du2_power4+du3_power4,nothing,lsu2_power4,iu2_power4)
  49
  50 (define_reservation "iq_power4"
  51                     "(du1_power4,iu1_power4)\
  52                     |(du2_power4,iu2_power4)\
  53                     |(du3_power4,nothing,iu2_power4)\
  54                     |(du4_power4,nothing,iu1_power4)")
  55
  56 (define_reservation "fpq_power4"
  57                     "(du1_power4,fpu1_power4)\
  58                     |(du2_power4,fpu2_power4)\
  59                     |(du3_power4,nothing,fpu2_power4)\
  60                     |(du4_power4,nothing,fpu1_power4)")
  61
  62 (define_reservation "vq_power4"
  63                     "(du1_power4,vec_power4)\
  64                     |(du2_power4,vec_power4)\
  65                     |(du3_power4,nothing,vec_power4)\
  66                     |(du4_power4,nothing,vec_power4)")
  67
  68 (define_reservation "vpq_power4"
  69                     "(du1_power4,vecperm_power4)\
  70                     |(du2_power4,vecperm_power4)\
  71                     |(du3_power4,nothing,vecperm_power4)\
  72                     |(du4_power4,nothing,vecperm_power4)")
  73
  74
  75 ; Dispatch slots are allocated in order conforming to program order.
  76 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  77 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  78 (absence_set "du3_power4" "du4_power4,du5_power4")
  79 (absence_set "du4_power4" "du5_power4")
  80
  81
  82 ; Load/store
  83 (define_insn_reservation "power4-load" 4 ; 3
  84   (and (eq_attr "type" "load")
  85        (eq_attr "cpu" "power4"))
  86   "lsq_power4")
  87
  88 (define_insn_reservation "power4-load-ext" 5
  89   (and (eq_attr "type" "load_ext")
  90        (eq_attr "cpu" "power4"))
  91   "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
  92   |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
  93   |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")
  94
  95 (define_insn_reservation "power4-load-ext-update" 5
  96   (and (eq_attr "type" "load_ext_u")
  97        (eq_attr "cpu" "power4"))
  98   "du1_power4+du2_power4+du3_power4+du4_power4,\
  99    lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
 100
 101 (define_insn_reservation "power4-load-ext-update-indexed" 5
 102   (and (eq_attr "type" "load_ext_ux")
 103        (eq_attr "cpu" "power4"))
 104   "du1_power4+du2_power4+du3_power4+du4_power4,\
 105    iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
 106
 107 (define_insn_reservation "power4-load-update-indexed" 3
 108   (and (eq_attr "type" "load_ux")
 109        (eq_attr "cpu" "power4"))
 110   "du1_power4+du2_power4+du3_power4+du4_power4,\
 111    iu1_power4,lsu2_power4+iu2_power4")
 112
 113 (define_insn_reservation "power4-load-update" 4 ; 3
 114   (and (eq_attr "type" "load_u")
 115        (eq_attr "cpu" "power4"))
 116   "lsuq_power4")
 117
 118 (define_insn_reservation "power4-fpload" 6 ; 5
 119   (and (eq_attr "type" "fpload")
 120        (eq_attr "cpu" "power4"))
 121   "lsq_power4")
 122
 123 (define_insn_reservation "power4-fpload-update" 6 ; 5
 124   (and (eq_attr "type" "fpload_u,fpload_ux")
 125        (eq_attr "cpu" "power4"))
 126   "lsuq_power4")
 127
 128 (define_insn_reservation "power4-vecload" 6 ; 5
 129   (and (eq_attr "type" "vecload")
 130        (eq_attr "cpu" "power4"))
 131   "lsq_power4")
 132
 133 (define_insn_reservation "power4-store" 1
 134   (and (eq_attr "type" "store")
 135        (eq_attr "cpu" "power4"))
 136   "(du1_power4,lsu1_power4,iu1_power4)\
 137   |(du2_power4,lsu2_power4,iu2_power4)\
 138   |(du3_power4,lsu2_power4,nothing,iu2_power4)\
 139   |(du4_power4,lsu1_power4,nothing,iu1_power4)")
 140
 141 (define_insn_reservation "power4-store-update" 1
 142   (and (eq_attr "type" "store_u")
 143        (eq_attr "cpu" "power4"))
 144   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
 145   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
 146   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
 147   |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
 148
 149 (define_insn_reservation "power4-store-update-indexed" 1
 150   (and (eq_attr "type" "store_ux")
 151        (eq_attr "cpu" "power4"))
 152    "du1_power4+du2_power4+du3_power4+du4_power4,\
 153     iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
 154
 155 (define_insn_reservation "power4-fpstore" 1
 156   (and (eq_attr "type" "fpstore")
 157        (eq_attr "cpu" "power4"))
 158   "(du1_power4,lsu1_power4,fpu1_power4)\
 159   |(du2_power4,lsu2_power4,fpu2_power4)\
 160   |(du3_power4,lsu2_power4,nothing,fpu2_power4)\
 161   |(du4_power4,lsu1_power4,nothing,fpu1_power4)")
 162
 163 (define_insn_reservation "power4-fpstore-update" 1
 164   (and (eq_attr "type" "fpstore_u,fpstore_ux")
 165        (eq_attr "cpu" "power4"))
 166   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
 167   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
 168   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
 169 ;  |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)")
 170
 171 (define_insn_reservation "power4-vecstore" 1
 172   (and (eq_attr "type" "vecstore")
 173        (eq_attr "cpu" "power4"))
 174   "(du1_power4,lsu1_power4,vec_power4)\
 175   |(du2_power4,lsu2_power4,vec_power4)\
 176   |(du3_power4,lsu2_power4,nothing,vec_power4)\
 177   |(du4_power4,lsu1_power4,nothing,vec_power4)")
 178
 179
 180 ; Integer latency is 2 cycles
 181 (define_insn_reservation "power4-integer" 2
 182   (and (eq_attr "type" "integer")
 183        (eq_attr "cpu" "power4"))
 184   "iq_power4")
 185
 186 (define_insn_reservation "power4-insert" 4
 187   (and (eq_attr "type" "insert_word")
 188        (eq_attr "cpu" "power4"))
 189   "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
 190   |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
 191   |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)")
 192
 193 (define_insn_reservation "power4-cmp" 3
 194   (and (eq_attr "type" "cmp,fast_compare")
 195        (eq_attr "cpu" "power4"))
 196   "iq_power4")
 197
 198 (define_insn_reservation "power4-compare" 2
 199   (and (eq_attr "type" "compare,delayed_compare")
 200        (eq_attr "cpu" "power4"))
 201   "(du1_power4+du2_power4,iu1_power4,iu2_power4)\
 202   |(du2_power4+du3_power4,iu2_power4,iu2_power4)\
 203   |(du3_power4+du4_power4,nothing,iu2_power4,iu1_power4)")
 204
 205 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 206
 207 (define_insn_reservation "power4-lmul-cmp" 7
 208   (and (eq_attr "type" "lmul_compare")
 209        (eq_attr "cpu" "power4"))
 210   "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
 211   |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
 212   |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
 213 ;  |(du3_power4+du4_power4,nothing,iu2_power4*6,iu1_power4)")
 214
 215 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 216
 217 (define_insn_reservation "power4-imul-cmp" 5
 218   (and (eq_attr "type" "imul_compare")
 219        (eq_attr "cpu" "power4"))
 220   "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
 221   |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
 222   |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
 223 ;  |(du3_power4+du4_power4,nothing,iu2_power4*4,iu1_power4)")
 224
 225 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 226
 227 (define_insn_reservation "power4-lmul" 7
 228   (and (eq_attr "type" "lmul")
 229        (eq_attr "cpu" "power4"))
 230   "(du1_power4,iu1_power4*6)\
 231   |(du2_power4,iu2_power4*6)\
 232   |(du3_power4,iu2_power4*6)\
 233   |(du4_power4,iu2_power4*6)")
 234 ;  |(du3_power4,nothing,iu2_power4*6)\
 235 ;  |(du4_power4,nothing,iu2_power4*6)")
 236
 237 (define_insn_reservation "power4-imul" 5
 238   (and (eq_attr "type" "imul")
 239        (eq_attr "cpu" "power4"))
 240   "(du1_power4,iu1_power4*4)\
 241   |(du2_power4,iu2_power4*4)\
 242   |(du3_power4,iu2_power4*4)\
 243   |(du4_power4,iu1_power4*4)")
 244 ;  |(du3_power4,nothing,iu2_power4*4)\
 245 ;  |(du4_power4,nothing,iu1_power4*4)")
 246
 247 (define_insn_reservation "power4-imul3" 4
 248   (and (eq_attr "type" "imul2,imul3")
 249        (eq_attr "cpu" "power4"))
 250   "(du1_power4,iu1_power4*3)\
 251   |(du2_power4,iu2_power4*3)\
 252   |(du3_power4,iu2_power4*3)\
 253   |(du4_power4,iu1_power4*3)")
 254 ;  |(du3_power4,nothing,iu2_power4*3)\
 255 ;  |(du4_power4,nothing,iu1_power4*3)")
 256
 257
 258 ; SPR move only executes in first IU.
 259 ; Integer division only executes in second IU.
 260 (define_insn_reservation "power4-idiv" 36
 261   (and (eq_attr "type" "idiv")
 262        (eq_attr "cpu" "power4"))
 263   "du1_power4+du2_power4,iu2_power4*35")
 264
 265 (define_insn_reservation "power4-ldiv" 68
 266   (and (eq_attr "type" "ldiv")
 267        (eq_attr "cpu" "power4"))
 268   "du1_power4+du2_power4,iu2_power4*67")
 269
 270
 271 (define_insn_reservation "power4-mtjmpr" 3
 272   (and (eq_attr "type" "mtjmpr,mfjmpr")
 273        (eq_attr "cpu" "power4"))
 274   "du1_power4,bpu_power4")
 275
 276
 277 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 278 ; grabbing previous dispatch slots once this is assigned.
 279 (define_insn_reservation "power4-branch" 2
 280   (and (eq_attr "type" "jmpreg,branch")
 281        (eq_attr "cpu" "power4"))
 282   "(du5_power4\
 283    |du4_power4+du5_power4\
 284    |du3_power4+du4_power4+du5_power4\
 285    |du2_power4+du3_power4+du4_power4+du5_power4\
 286    |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
 287
 288
 289 ; Condition Register logical ops are split if non-destructive (RT != RB)
 290 (define_insn_reservation "power4-crlogical" 2
 291   (and (eq_attr "type" "cr_logical")
 292        (eq_attr "cpu" "power4"))
 293   "du1_power4,cru_power4")
 294
 295 (define_insn_reservation "power4-delayedcr" 4
 296   (and (eq_attr "type" "delayed_cr")
 297        (eq_attr "cpu" "power4"))
 298   "du1_power4+du2_power4,cru_power4,cru_power4")
 299
 300 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 301 (define_insn_reservation "power4-mfcr" 6
 302   (and (eq_attr "type" "mfcr")
 303        (eq_attr "cpu" "power4"))
 304   "du1_power4+du2_power4+du3_power4+du4_power4,\
 305    du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
 306    cru_power4,cru_power4,cru_power4")
 307
 308 ; mfcrf (1 field)
 309 (define_insn_reservation "power4-mfcrf" 3
 310   (and (eq_attr "type" "mfcrf")
 311        (eq_attr "cpu" "power4"))
 312   "du1_power4,cru_power4")
 313
 314 ; mtcrf (1 field)
 315 (define_insn_reservation "power4-mtcr" 4
 316   (and (eq_attr "type" "mtcr")
 317        (eq_attr "cpu" "power4"))
 318   "du1_power4,iu1_power4")
 319
 320 ; Basic FP latency is 6 cycles
 321 (define_insn_reservation "power4-fp" 6
 322   (and (eq_attr "type" "fp,dmul")
 323        (eq_attr "cpu" "power4"))
 324   "fpq_power4")
 325
 326 (define_insn_reservation "power4-fpcompare" 5
 327   (and (eq_attr "type" "fpcompare")
 328        (eq_attr "cpu" "power4"))
 329   "fpq_power4")
 330
 331 (define_insn_reservation "power4-sdiv" 33
 332   (and (eq_attr "type" "sdiv,ddiv")
 333        (eq_attr "cpu" "power4"))
 334   "(du1_power4,fpu1_power4*28)\
 335   |(du2_power4,fpu2_power4*28)\
 336   |(du3_power4,fpu2_power4*28)\
 337   |(du4_power4,fpu1_power4*28)")
 338 ;  |(du3_power4,nothing,fpu2_power4*28)\
 339 ;  |(du4_power4,nothing,fpu1_power4*28)")
 340
 341 (define_insn_reservation "power4-sqrt" 40
 342   (and (eq_attr "type" "ssqrt,dsqrt")
 343        (eq_attr "cpu" "power4"))
 344   "(du1_power4,fpu1_power4*35)\
 345   |(du2_power4,fpu2_power4*35)\
 346   |(du3_power4,fpu2_power4*35)\
 347   |(du4_power4,fpu2_power4*35)")
 348 ;  |(du3_power4,nothing,fpu2_power4*35)\
 349 ;  |(du4_power4,nothing,fpu2_power4*35)")
 350
 351
 352 ; VMX
 353 (define_insn_reservation "power4-vecsimple" 2
 354   (and (eq_attr "type" "vecsimple")
 355        (eq_attr "cpu" "power4"))
 356   "vq_power4")
 357
 358 (define_insn_reservation "power4-veccomplex" 5
 359   (and (eq_attr "type" "veccomplex")
 360        (eq_attr "cpu" "power4"))
 361   "vq_power4")
 362
 363 ; vecfp compare
 364 (define_insn_reservation "power4-veccmp" 8
 365   (and (eq_attr "type" "veccmp")
 366        (eq_attr "cpu" "power4"))
 367   "vq_power4")
 368
 369 (define_insn_reservation "power4-vecfloat" 8
 370   (and (eq_attr "type" "vecfloat")
 371        (eq_attr "cpu" "power4"))
 372   "vq_power4")
 373
 374 (define_insn_reservation "power4-vecperm" 2
 375   (and (eq_attr "type" "vecperm")
 376        (eq_attr "cpu" "power4"))
 377   "vpq_power4")
 378
 379 (define_bypass 4 "power4-vecload" "power4-vecperm")
 380
 381 (define_bypass 3 "power4-vecsimple" "power4-vecperm")
 382 (define_bypass 6 "power4-veccomplex" "power4-vecperm")
 383 (define_bypass 3 "power4-vecperm"
 384                  "power4-vecsimple,power4-veccomplex,power4-vecfloat")
 385 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
 386
 387 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
 388                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 389
 390 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
 391 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
 392 (define_bypass 10 "power4-vecfloat" "power4-vecstore")