1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;; Sources: IBM Red Book and White Paper on POWER4
23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
24 ;; Instructions that update more than one register get broken into two
25 ;; (split) or more internal ops. The chip can issue up to 5
26 ;; internal ops per cycle.
28 (define_automaton "power4iu,power4lsu,power4fpu,power4misc,power4vec,power4disp")
30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4lsu")
32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
38 (define_reservation "q1_power4" "du1_power4|du4_power4")
39 (define_reservation "q2_power4" "du2_power4|du3_power4")
41 (define_reservation "lsq_power4" "((du1_power4|du4_power4),lsu1_power4)\
42 |((du2_power4|du3_power4),lsu2_power4)")
44 (define_reservation "lsuq_power4"
45 "((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
46 |((du2_power4+du3_power4),lsu2_power4+iu2_power4)\
47 |((du3_power4+du4_power4),lsu2_power4+iu1_power4)")
48 ;;; |((du2_power4+du3_power4),lsu2_power4,iu2_power4)
50 (define_reservation "lsuxq_power4"
51 "(du1_power4+du2_power4+du3_power4+du4_power4),\
52 iu1_power4,(lsu2_power4+iu2_power4)")
54 (define_reservation "iq_power4" "((du1_power4|du4_power4),iu1_power4)\
55 |((du2_power4|du3_power4),iu2_power4)")
57 (define_reservation "fpq_power4" "((du1_power4|du4_power4),fpu1_power4)\
58 |((du2_power4|du3_power4),fpu2_power4)")
60 (define_reservation "vq_power4"
61 "(du1_power4|du2_power4|du3_power4|du4_power4),vec_power4")
62 (define_reservation "vpq_power4"
63 "(du1_power4|du2_power4|du3_power4|du4_power4),\
67 ; Dispatch slots are allocated in order conforming to program order.
68 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
69 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
70 (absence_set "du3_power4" "du4_power4,du5_power4")
71 (absence_set "du4_power4" "du5_power4")
75 (define_insn_reservation "power4-load" 3
76 (and (eq_attr "type" "load")
77 (eq_attr "cpu" "power4"))
80 (define_insn_reservation "power4-load-ext" 5
81 (and (eq_attr "type" "load_ext")
82 (eq_attr "cpu" "power4"))
83 "((du1_power4+du2_power4),lsu1_power4,nothing,nothing,iu2_power4)\
84 |((du2_power4+du3_power4),lsu2_power4,nothing,nothing,iu2_power4)\
85 |((du3_power4+du4_power4),lsu2_power4,nothing,nothing,iu1_power4)")
87 (define_insn_reservation "power4-load-ext-update" 5
88 (and (eq_attr "type" "load_ext_u")
89 (eq_attr "cpu" "power4"))
90 "(du1_power4+du2_power4+du3_power4+du4_power4),\
91 (lsu1_power4+iu2_power4),nothing,nothing,iu2_power4")
93 (define_insn_reservation "power4-load-ext-update-indexed" 5
94 (and (eq_attr "type" "load_ext_ux")
95 (eq_attr "cpu" "power4"))
96 "(du1_power4+du2_power4+du3_power4+du4_power4),\
97 iu1_power4,(lsu2_power4+iu1_power4),nothing,nothing,iu2_power4")
99 (define_insn_reservation "power4-load-update-indexed" 3
100 (and (eq_attr "type" "load_ux")
101 (eq_attr "cpu" "power4"))
104 (define_insn_reservation "power4-load-update" 3
105 (and (eq_attr "type" "load_u")
106 (eq_attr "cpu" "power4"))
109 (define_insn_reservation "power4-fpload" 5
110 (and (eq_attr "type" "fpload")
111 (eq_attr "cpu" "power4"))
114 (define_insn_reservation "power4-fpload-update" 5
115 (and (eq_attr "type" "fpload_u")
116 (eq_attr "cpu" "power4"))
119 (define_insn_reservation "power4-fpload-update-indexed" 5
120 (and (eq_attr "type" "fpload_ux")
121 (eq_attr "cpu" "power4"))
124 (define_insn_reservation "power4-vecload" 5
125 (and (eq_attr "type" "vecload")
126 (eq_attr "cpu" "power4"))
129 (define_insn_reservation "power4-store" 1
130 (and (eq_attr "type" "store")
131 (eq_attr "cpu" "power4"))
132 "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\
133 |((du2_power4|du3_power4),lsu2_power4,iu1_power4)")
135 (define_insn_reservation "power4-store-update" 1
136 (and (eq_attr "type" "store_u")
137 (eq_attr "cpu" "power4"))
140 (define_insn_reservation "power4-store-update-indexed" 1
141 (and (eq_attr "type" "store_ux")
142 (eq_attr "cpu" "power4"))
145 (define_insn_reservation "power4-fpstore" 1
146 (and (eq_attr "type" "fpstore")
147 (eq_attr "cpu" "power4"))
148 "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\
149 |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)")
151 (define_insn_reservation "power4-fpstore-update" 1
152 (and (eq_attr "type" "fpstore_u")
153 (eq_attr "cpu" "power4"))
154 "((du1_power4+du2_power4),(fpu1_power4+iu2_power4),lsu1_power4)\
155 |((du2_power4+du3_power4),(fpu2_power4+iu2_power4),lsu2_power4)\
156 |((du3_power4+du4_power4),(fpu2_power4+iu1_power4),lsu2_power4)")
157 ;;;((du2_power4+du3_power4),fpu2_power4,(iu2_power4+lsu2_power4))
159 (define_insn_reservation "power4-fpstore-update-indexed" 1
160 (and (eq_attr "type" "fpstore_ux")
161 (eq_attr "cpu" "power4"))
162 "(du1_power4+du2_power4+du3_power4+du4_power4),
163 iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)")
165 (define_insn_reservation "power4-vecstore" 1
166 (and (eq_attr "type" "vecstore")
167 (eq_attr "cpu" "power4"))
168 "((du1_power4|du4_power4),lsu1_power4,vec_power4)\
169 |((du2_power4|du3_power4),lsu2_power4,vec_power4)")
172 ; Integer latency is 2 cycles
173 (define_insn_reservation "power4-integer" 2
174 (and (eq_attr "type" "integer")
175 (eq_attr "cpu" "power4"))
178 (define_insn_reservation "power4-cmp" 3
179 (and (eq_attr "type" "cmp,fast_compare")
180 (eq_attr "cpu" "power4"))
183 (define_insn_reservation "power4-compare" 4
184 (and (eq_attr "type" "compare,delayed_compare")
185 (eq_attr "cpu" "power4"))
186 "((du1_power4+du2_power4),iu1_power4,iu2_power4)\
187 |((du2_power4+du3_power4),iu2_power4,iu2_power4)\
188 |((du3_power4+du4_power4),iu2_power4,iu1_power4)")
190 (define_bypass 2 "power4-compare" "power4-integer")
192 (define_insn_reservation "power4-imul" 7
193 (and (eq_attr "type" "imul,lmul")
194 (eq_attr "cpu" "power4"))
195 "(q1_power4,iu1_power4*6)|(q2_power4,iu2_power4*6)")
197 (define_insn_reservation "power4-imul2" 5
198 (and (eq_attr "type" "imul2")
199 (eq_attr "cpu" "power4"))
200 "(q1_power4,iu1_power4*4)|(q2_power4,iu2_power4*4)")
202 (define_insn_reservation "power4-imul3" 4
203 (and (eq_attr "type" "imul3")
204 (eq_attr "cpu" "power4"))
205 "(q1_power4,iu1_power4*3)|(q2_power4,iu2_power4*3)")
207 ; SPR move only executes in first IU.
208 ; Integer division only executes in second IU.
209 (define_insn_reservation "power4-idiv" 36
210 (and (eq_attr "type" "idiv")
211 (eq_attr "cpu" "power4"))
212 "(du1_power4+du2_power4),iu2_power4*35")
214 (define_insn_reservation "power4-ldiv" 68
215 (and (eq_attr "type" "ldiv")
216 (eq_attr "cpu" "power4"))
217 "(du1_power4+du2_power4),iu2_power4*67")
220 (define_insn_reservation "power4-mtjmpr" 3
221 (and (eq_attr "type" "mtjmpr")
222 (eq_attr "cpu" "power4"))
223 "du1_power4,bpu_power4")
226 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
227 ; grabbing previous dispatch slots once this is assigned.
228 (define_insn_reservation "power4-branch" 2
229 (and (eq_attr "type" "jmpreg,branch")
230 (eq_attr "cpu" "power4"))
231 "du5_power4,bpu_power4")
234 ; Condition Register logical ops are split if non-destructive (RT != RB)
235 (define_insn_reservation "power4-crlogical" 2
236 (and (eq_attr "type" "cr_logical")
237 (eq_attr "cpu" "power4"))
238 "du1_power4,cru_power4")
240 (define_insn_reservation "power4-delayedcr" 4
241 (and (eq_attr "type" "delayed_cr")
242 (eq_attr "cpu" "power4"))
243 "(du1_power4+du2_power4),cru_power4,cru_power4")
245 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
246 (define_insn_reservation "power4-mfcr" 6
247 (and (eq_attr "type" "mfcr")
248 (eq_attr "cpu" "power4"))
249 "(du1_power4+du2_power4+du3_power4+du4_power4),\
250 (du1_power4+du2_power4+du3_power4+du4_power4+cru_power4),\
251 cru_power4,cru_power4,cru_power4")
254 (define_insn_reservation "power4-mtcr" 4
255 (and (eq_attr "type" "mtcr")
256 (eq_attr "cpu" "power4"))
257 "du1_power4,iu1_power4")
259 ; Basic FP latency is 6 cycles
260 (define_insn_reservation "power4-fp" 6
261 (and (eq_attr "type" "fp,dmul")
262 (eq_attr "cpu" "power4"))
265 (define_insn_reservation "power4-fpcompare" 5
266 (and (eq_attr "type" "fpcompare")
267 (eq_attr "cpu" "power4"))
270 (define_insn_reservation "power4-sdiv" 33
271 (and (eq_attr "type" "sdiv,ddiv")
272 (eq_attr "cpu" "power4"))
273 "(q1_power4,fpu1_power4*28)|(q2_power4,fpu2_power4*28)")
275 (define_insn_reservation "power4-sqrt" 40
276 (and (eq_attr "type" "ssqrt,dsqrt")
277 (eq_attr "cpu" "power4"))
278 "(q1_power4,fpu1_power4*35)|(q2_power4,fpu2_power4*35)")
282 (define_insn_reservation "power4-vecsimple" 2
283 (and (eq_attr "type" "vecsimple")
284 (eq_attr "cpu" "power4"))
287 (define_insn_reservation "power4-veccomplex" 2
288 (and (eq_attr "type" "veccomplex")
289 (eq_attr "cpu" "power4"))
293 (define_insn_reservation "power4-veccmp" 8
294 (and (eq_attr "type" "veccmp")
295 (eq_attr "cpu" "power4"))
298 (define_insn_reservation "power4-vecfloat" 8
299 (and (eq_attr "type" "vecfloat")
300 (eq_attr "cpu" "power4"))
303 (define_insn_reservation "power4-vecperm" 2
304 (and (eq_attr "type" "vecperm")
305 (eq_attr "cpu" "power4"))
308 (define_bypass 4 "power4-vecload" "power4-vecperm")
310 (define_bypass 3 "power4-vecsimple,power4-veccomplex" "power4-vecperm")
311 (define_bypass 3 "power4-vecperm"
312 "power4-vecsimple,power4-veccomplex,power4-vecfloat")
313 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
315 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
316 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
318 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
319 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
320 (define_bypass 10 "power4-vecfloat" "power4-vecstore")