gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GNU CC.
   5 ;;
   6 ;; GNU CC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GNU CC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GNU CC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21 ;; Sources: IBM Red Book and White Paper on POWER4
  22
  23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  24 ;; Instructions that update more than one register get broken into two
  25 ;; (split) or more internal ops.  The chip can issue up to 5
  26 ;; internal ops per cycle.
  27
  28 (define_automaton "power4iu,power4lsu,power4fpu,power4misc,power4vec,power4disp")
  29
  30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4lsu")
  32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  36                  "power4disp")
  37
  38 (define_reservation "lsq_power4"
  39                     "(du1_power4,lsu1_power4)\
  40                     |(du2_power4,lsu2_power4)\
  41                     |(du3_power4,nothing,lsu2_power4)\
  42                     |(du4_power4,nothing,lsu1_power4)")
  43
  44 (define_reservation "lsuq_power4"
  45                     "((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
  46                     |((du2_power4+du3_power4),lsu2_power4+iu2_power4)\
  47                     |((du3_power4+du4_power4),lsu2_power4+iu1_power4)")
  48 ;                   |((du2_power4+du3_power4),nothing,lsu2_power4,iu2_power4)
  49
  50 (define_reservation "iq_power4"
  51                     "(du1_power4,iu1_power4)\
  52                     |(du2_power4,iu2_power4)\
  53                     |(du3_power4,nothing,iu2_power4)\
  54                     |(du4_power4,nothing,iu1_power4)")
  55
  56 (define_reservation "fpq_power4"
  57                     "(du1_power4,fpu1_power4)\
  58                     |(du2_power4,fpu2_power4)\
  59                     |(du3_power4,nothing,fpu2_power4)\
  60                     |(du4_power4,nothing,fpu1_power4)")
  61
  62 (define_reservation "vq_power4"
  63                     "(du1_power4,vec_power4)\
  64                     |(du2_power4,vec_power4)\
  65                     |(du3_power4,nothing,vec_power4)\
  66                     |(du4_power4,nothing,vec_power4)")
  67
  68 (define_reservation "vpq_power4"
  69                     "(du1_power4,vecperm_power4)\
  70                     |(du2_power4,vecperm_power4)\
  71                     |(du3_power4,nothing,vecperm_power4)\
  72                     |(du4_power4,nothing,vecperm_power4)")
  73
  74
  75 ; Dispatch slots are allocated in order conforming to program order.
  76 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  77 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  78 (absence_set "du3_power4" "du4_power4,du5_power4")
  79 (absence_set "du4_power4" "du5_power4")
  80
  81
  82 ; Load/store
  83 (define_insn_reservation "power4-load" 4 ; 3
  84   (and (eq_attr "type" "load")
  85        (eq_attr "cpu" "power4"))
  86   "lsq_power4")
  87
  88 (define_insn_reservation "power4-load-ext" 5
  89   (and (eq_attr "type" "load_ext")
  90        (eq_attr "cpu" "power4"))
  91   "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
  92   |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
  93   |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")
  94
  95 (define_insn_reservation "power4-load-ext-update" 5
  96   (and (eq_attr "type" "load_ext_u")
  97        (eq_attr "cpu" "power4"))
  98   "(du1_power4+du2_power4+du3_power4+du4_power4),\
  99    (lsu1_power4+iu2_power4),nothing,nothing,iu2_power4")
 100
 101 (define_insn_reservation "power4-load-ext-update-indexed" 5
 102   (and (eq_attr "type" "load_ext_ux")
 103        (eq_attr "cpu" "power4"))
 104   "(du1_power4+du2_power4+du3_power4+du4_power4),\
 105    iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
 106
 107 (define_insn_reservation "power4-load-update-indexed" 4 ; 3
 108   (and (eq_attr "type" "load_ux")
 109        (eq_attr "cpu" "power4"))
 110    "du1_power4+du2_power4+du3_power4+du4_power4,\
 111    iu1_power4,lsu2_power4+iu2_power4")
 112
 113 (define_insn_reservation "power4-load-update" 4 ; 3
 114   (and (eq_attr "type" "load_u")
 115        (eq_attr "cpu" "power4"))
 116   "lsuq_power4")
 117
 118 (define_insn_reservation "power4-fpload" 6 ; 5
 119   (and (eq_attr "type" "fpload")
 120        (eq_attr "cpu" "power4"))
 121   "lsq_power4")
 122
 123 (define_insn_reservation "power4-fpload-update" 6 ; 5
 124   (and (eq_attr "type" "fpload_u,fpload_ux")
 125        (eq_attr "cpu" "power4"))
 126   "lsuq_power4")
 127
 128 (define_insn_reservation "power4-vecload" 6 ; 5
 129   (and (eq_attr "type" "vecload")
 130        (eq_attr "cpu" "power4"))
 131   "lsq_power4")
 132
 133 (define_insn_reservation "power4-store" 1
 134   (and (eq_attr "type" "store")
 135        (eq_attr "cpu" "power4"))
 136   "(du1_power4,lsu1_power4,iu1_power4)\
 137   |(du2_power4,lsu2_power4,iu2_power4)\
 138   |(du3_power4,lsu2_power4,nothing,iu2_power4)\
 139   |(du4_power4,lsu1_power4,nothing,iu1_power4)")
 140
 141 (define_insn_reservation "power4-store-update" 1
 142   (and (eq_attr "type" "store_u")
 143        (eq_attr "cpu" "power4"))
 144   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
 145   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
 146   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
 147   |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
 148
 149 (define_insn_reservation "power4-store-update-indexed" 1
 150   (and (eq_attr "type" "store_ux")
 151        (eq_attr "cpu" "power4"))
 152    "du1_power4+du2_power4+du3_power4+du4_power4,\
 153     iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
 154
 155 (define_insn_reservation "power4-fpstore" 1
 156   (and (eq_attr "type" "fpstore")
 157        (eq_attr "cpu" "power4"))
 158   "(du1_power4,lsu1_power4,fpu1_power4)\
 159   |(du2_power4,lsu2_power4,fpu2_power4)\
 160   |(du3_power4,lsu2_power4,nothing,fpu2_power4)\
 161   |(du4_power4,lsu1_power4,nothing,fpu1_power4)")
 162
 163 (define_insn_reservation "power4-fpstore-update" 1
 164   (and (eq_attr "type" "fpstore_u,fpstore_ux")
 165        (eq_attr "cpu" "power4"))
 166   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
 167   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
 168   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
 169 ;  |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)")
 170
 171 (define_insn_reservation "power4-vecstore" 1
 172   (and (eq_attr "type" "vecstore")
 173        (eq_attr "cpu" "power4"))
 174   "(du1_power4,lsu1_power4,vec_power4)\
 175   |(du2_power4,lsu2_power4,vec_power4)\
 176   |(du3_power4,lsu2_power4,nothing,vec_power4)\
 177   |(du4_power4,lsu1_power4,nothing,vec_power4)")
 178
 179
 180 ; Integer latency is 2 cycles
 181 (define_insn_reservation "power4-integer" 2
 182   (and (eq_attr "type" "integer")
 183        (eq_attr "cpu" "power4"))
 184   "iq_power4")
 185
 186 (define_insn_reservation "power4-cmp" 3
 187   (and (eq_attr "type" "cmp,fast_compare")
 188        (eq_attr "cpu" "power4"))
 189   "iq_power4")
 190
 191 (define_insn_reservation "power4-compare" 2
 192   (and (eq_attr "type" "compare,delayed_compare")
 193        (eq_attr "cpu" "power4"))
 194   "(du1_power4+du2_power4,iu1_power4,iu2_power4)\
 195   |(du2_power4+du3_power4,iu2_power4,iu2_power4)\
 196   |(du3_power4+du4_power4,nothing,iu2_power4,iu1_power4)")
 197
 198 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 199
 200 (define_insn_reservation "power4-lmul-cmp" 8 ; 7
 201   (and (eq_attr "type" "lmul_compare")
 202        (eq_attr "cpu" "power4"))
 203   "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
 204   |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
 205   |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
 206 ;  |(du3_power4+du4_power4,nothing,iu2_power4*6,iu1_power4)")
 207
 208 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 209
 210 (define_insn_reservation "power4-imul-cmp" 6 ; 5
 211   (and (eq_attr "type" "imul_compare")
 212        (eq_attr "cpu" "power4"))
 213   "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
 214   |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
 215   |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
 216 ;  |(du3_power4+du4_power4,nothing,iu2_power4*4,iu1_power4)")
 217
 218 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 219
 220 (define_insn_reservation "power4-lmul" 8 ; 7
 221   (and (eq_attr "type" "lmul")
 222        (eq_attr "cpu" "power4"))
 223   "(du1_power4,iu1_power4*6)\
 224   |(du2_power4,iu2_power4*6)\
 225   |(du3_power4,iu2_power4*6)\
 226   |(du4_power4,iu2_power4*6)")
 227 ;  |(du3_power4,nothing,iu2_power4*6)\
 228 ;  |(du4_power4,nothing,iu2_power4*6)")
 229
 230 (define_insn_reservation "power4-imul" 6 ; 5
 231   (and (eq_attr "type" "imul")
 232        (eq_attr "cpu" "power4"))
 233   "(du1_power4,iu1_power4*4)\
 234   |(du2_power4,iu2_power4*4)\
 235   |(du3_power4,iu2_power4*4)\
 236   |(du4_power4,iu1_power4*4)")
 237 ;  |(du3_power4,nothing,iu2_power4*4)\
 238 ;  |(du4_power4,nothing,iu1_power4*4)")
 239
 240 (define_insn_reservation "power4-imul3" 5 ; 4
 241   (and (eq_attr "type" "imul2,imul3")
 242        (eq_attr "cpu" "power4"))
 243   "(du1_power4,iu1_power4*3)\
 244   |(du2_power4,iu2_power4*3)\
 245   |(du3_power4,iu2_power4*3)\
 246   |(du4_power4,iu1_power4*3)")
 247 ;  |(du3_power4,nothing,iu2_power4*3)\
 248 ;  |(du4_power4,nothing,iu1_power4*3)")
 249
 250
 251 ; SPR move only executes in first IU.
 252 ; Integer division only executes in second IU.
 253 (define_insn_reservation "power4-idiv" 36
 254   (and (eq_attr "type" "idiv")
 255        (eq_attr "cpu" "power4"))
 256   "(du1_power4+du2_power4),iu2_power4*35")
 257
 258 (define_insn_reservation "power4-ldiv" 68
 259   (and (eq_attr "type" "ldiv")
 260        (eq_attr "cpu" "power4"))
 261   "(du1_power4+du2_power4),iu2_power4*67")
 262
 263
 264 (define_insn_reservation "power4-mtjmpr" 3
 265   (and (eq_attr "type" "mtjmpr")
 266        (eq_attr "cpu" "power4"))
 267   "du1_power4,bpu_power4")
 268
 269
 270 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 271 ; grabbing previous dispatch slots once this is assigned.
 272 (define_insn_reservation "power4-branch" 2
 273   (and (eq_attr "type" "jmpreg,branch")
 274        (eq_attr "cpu" "power4"))
 275   "(du5_power4\
 276    |du4_power4+du5_power4\
 277    |du3_power4+du4_power4+du5_power4\
 278    |du2_power4+du3_power4+du4_power4+du5_power4\
 279    |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
 280
 281
 282 ; Condition Register logical ops are split if non-destructive (RT != RB)
 283 (define_insn_reservation "power4-crlogical" 2
 284   (and (eq_attr "type" "cr_logical")
 285        (eq_attr "cpu" "power4"))
 286   "du1_power4,cru_power4")
 287
 288 (define_insn_reservation "power4-delayedcr" 4
 289   (and (eq_attr "type" "delayed_cr")
 290        (eq_attr "cpu" "power4"))
 291   "(du1_power4+du2_power4),cru_power4,cru_power4")
 292
 293 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 294 (define_insn_reservation "power4-mfcr" 6
 295   (and (eq_attr "type" "mfcr")
 296        (eq_attr "cpu" "power4"))
 297   "(du1_power4+du2_power4+du3_power4+du4_power4),\
 298    (du1_power4+du2_power4+du3_power4+du4_power4+cru_power4),\
 299     cru_power4,cru_power4,cru_power4")
 300
 301 ; mtcrf (1 field)
 302 (define_insn_reservation "power4-mtcr" 4
 303   (and (eq_attr "type" "mtcr")
 304        (eq_attr "cpu" "power4"))
 305   "du1_power4,iu1_power4")
 306
 307 ; Basic FP latency is 6 cycles
 308 (define_insn_reservation "power4-fp" 7 ; 6
 309   (and (eq_attr "type" "fp,dmul")
 310        (eq_attr "cpu" "power4"))
 311   "fpq_power4")
 312
 313 (define_insn_reservation "power4-fpcompare" 5
 314   (and (eq_attr "type" "fpcompare")
 315        (eq_attr "cpu" "power4"))
 316   "fpq_power4")
 317
 318 (define_insn_reservation "power4-sdiv" 33
 319   (and (eq_attr "type" "sdiv,ddiv")
 320        (eq_attr "cpu" "power4"))
 321   "(du1_power4,fpu1_power4*28)\
 322   |(du2_power4,fpu2_power4*28)\
 323   |(du3_power4,fpu2_power4*28)\
 324   |(du4_power4,fpu1_power4*28)")
 325 ;  |(du3_power4,nothing,fpu2_power4*28)\
 326 ;  |(du4_power4,nothing,fpu1_power4*28)")
 327
 328 (define_insn_reservation "power4-sqrt" 40
 329   (and (eq_attr "type" "ssqrt,dsqrt")
 330        (eq_attr "cpu" "power4"))
 331   "(du1_power4,fpu1_power4*35)\
 332   |(du2_power4,fpu2_power4*35)\
 333   |(du3_power4,fpu2_power4*35)\
 334   |(du4_power4,fpu2_power4*35)")
 335 ;  |(du3_power4,nothing,fpu2_power4*35)\
 336 ;  |(du4_power4,nothing,fpu2_power4*35)")
 337
 338
 339 ; VMX
 340 (define_insn_reservation "power4-vecsimple" 2
 341   (and (eq_attr "type" "vecsimple")
 342        (eq_attr "cpu" "power4"))
 343   "vq_power4")
 344
 345 (define_insn_reservation "power4-veccomplex" 2
 346   (and (eq_attr "type" "veccomplex")
 347        (eq_attr "cpu" "power4"))
 348   "vq_power4")
 349
 350 ; vecfp compare
 351 (define_insn_reservation "power4-veccmp" 8
 352   (and (eq_attr "type" "veccmp")
 353        (eq_attr "cpu" "power4"))
 354   "vq_power4")
 355
 356 (define_insn_reservation "power4-vecfloat" 8
 357   (and (eq_attr "type" "vecfloat")
 358        (eq_attr "cpu" "power4"))
 359   "vq_power4")
 360
 361 (define_insn_reservation "power4-vecperm" 2
 362   (and (eq_attr "type" "vecperm")
 363        (eq_attr "cpu" "power4"))
 364   "vpq_power4")
 365
 366 (define_bypass 4 "power4-vecload" "power4-vecperm")
 367
 368 (define_bypass 3 "power4-vecsimple,power4-veccomplex" "power4-vecperm")
 369 (define_bypass 3 "power4-vecperm"
 370                  "power4-vecsimple,power4-veccomplex,power4-vecfloat")
 371 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
 372
 373 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
 374                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 375
 376 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
 377 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
 378 (define_bypass 10 "power4-vecfloat" "power4-vecstore")