1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
2 Copyright (C) 2004, 2005 Free Software Foundation, Inc.
3 Contributed by Apple Computer Inc.
5 This file is part of GCC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 (define_insn "adddi3_high"
23 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
24 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
25 (high:DI (match_operand 2 "" ""))))]
26 "TARGET_MACHO && TARGET_64BIT"
27 "{cau|addis} %0,%1,ha16(%2)"
28 [(set_attr "length" "4")])
30 (define_insn "movdf_low_si"
31 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
32 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
33 (match_operand 2 "" ""))))]
34 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
37 switch (which_alternative)
40 return \"lfd %0,lo16(%2)(%1)\";
44 operands2[0] = operands[0];
45 operands2[1] = operands[1];
46 operands2[2] = operands[2];
47 if (TARGET_POWERPC64 && TARGET_32BIT)
48 /* Note, old assemblers didn't support relocation here. */
49 return \"ld %0,lo16(%2)(%1)\";
52 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
53 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
55 if (MACHO_DYNAMIC_NO_PIC_P)
56 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
58 /* We cannot rely on ha16(low half)==ha16(high half), alas,
59 although in practice it almost always is. */
60 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
62 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
69 [(set_attr "type" "load")
70 (set_attr "length" "4,12")])
73 (define_insn "movdf_low_di"
74 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
75 (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
76 (match_operand 2 "" ""))))]
77 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
80 switch (which_alternative)
83 return \"lfd %0,lo16(%2)(%1)\";
85 return \"ld %0,lo16(%2)(%1)\";
90 [(set_attr "type" "load")
91 (set_attr "length" "4,4")])
93 (define_insn "movdf_low_st_si"
94 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
95 (match_operand 2 "" "")))
96 (match_operand:DF 0 "gpc_reg_operand" "f"))]
97 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
98 "stfd %0,lo16(%2)(%1)"
99 [(set_attr "type" "store")
100 (set_attr "length" "4")])
102 (define_insn "movdf_low_st_di"
103 [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
104 (match_operand 2 "" "")))
105 (match_operand:DF 0 "gpc_reg_operand" "f"))]
106 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
107 "stfd %0,lo16(%2)(%1)"
108 [(set_attr "type" "store")
109 (set_attr "length" "4")])
111 (define_insn "movsf_low_si"
112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
113 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
114 (match_operand 2 "" ""))))]
115 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
118 {l|lwz} %0,lo16(%2)(%1)"
119 [(set_attr "type" "load")
120 (set_attr "length" "4")])
122 (define_insn "movsf_low_di"
123 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
124 (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
125 (match_operand 2 "" ""))))]
126 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
129 {l|lwz} %0,lo16(%2)(%1)"
130 [(set_attr "type" "load")
131 (set_attr "length" "4")])
133 (define_insn "movsf_low_st_si"
134 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
135 (match_operand 2 "" "")))
136 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
137 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
140 {st|stw} %0,lo16(%2)(%1)"
141 [(set_attr "type" "store")
142 (set_attr "length" "4")])
144 (define_insn "movsf_low_st_di"
145 [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
146 (match_operand 2 "" "")))
147 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
148 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
151 {st|stw} %0,lo16(%2)(%1)"
152 [(set_attr "type" "store")
153 (set_attr "length" "4")])
155 ;; 64-bit MachO load/store support
156 (define_insn "movdi_low"
157 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
158 (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
159 (match_operand 2 "" ""))))]
160 "TARGET_MACHO && TARGET_64BIT"
161 "{l|ld} %0,lo16(%2)(%1)"
162 [(set_attr "type" "load")
163 (set_attr "length" "4")])
165 (define_insn "movsi_low_st"
166 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
167 (match_operand 2 "" "")))
168 (match_operand:SI 0 "gpc_reg_operand" "r"))]
169 "TARGET_MACHO && ! TARGET_64BIT"
170 "{st|stw} %0,lo16(%2)(%1)"
171 [(set_attr "type" "store")
172 (set_attr "length" "4")])
174 (define_insn "movdi_low_st"
175 [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
176 (match_operand 2 "" "")))
177 (match_operand:DI 0 "gpc_reg_operand" "r"))]
178 "TARGET_MACHO && TARGET_64BIT"
179 "{st|std} %0,lo16(%2)(%1)"
180 [(set_attr "type" "store")
181 (set_attr "length" "4")])
183 ;; Mach-O PIC trickery.
184 (define_expand "macho_high"
185 [(set (match_operand 0 "" "")
186 (high (match_operand 1 "" "")))]
190 emit_insn (gen_macho_high_di (operands[0], operands[1]));
192 emit_insn (gen_macho_high_si (operands[0], operands[1]));
197 (define_insn "macho_high_si"
198 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
199 (high:SI (match_operand 1 "" "")))]
200 "TARGET_MACHO && ! TARGET_64BIT"
201 "{liu|lis} %0,ha16(%1)")
204 (define_insn "macho_high_di"
205 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
206 (high:DI (match_operand 1 "" "")))]
207 "TARGET_MACHO && TARGET_64BIT"
208 "{liu|lis} %0,ha16(%1)")
210 (define_expand "macho_low"
211 [(set (match_operand 0 "" "")
212 (lo_sum (match_operand 1 "" "")
213 (match_operand 2 "" "")))]
217 emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
219 emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
224 (define_insn "macho_low_si"
225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
226 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
227 (match_operand 2 "" "")))]
228 "TARGET_MACHO && ! TARGET_64BIT"
230 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
231 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
233 (define_insn "macho_low_di"
234 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
235 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
236 (match_operand 2 "" "")))]
237 "TARGET_MACHO && TARGET_64BIT"
239 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
240 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
243 [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
244 (match_operand:DI 1 "short_cint_operand" "")))
245 (match_operand:V4SI 2 "register_operand" ""))
246 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
247 "TARGET_MACHO && TARGET_64BIT"
248 [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
249 (set (mem:V4SI (match_dup 3))
253 (define_expand "load_macho_picbase"
254 [(set (match_operand 0 "" "")
255 (unspec [(match_operand 1 "" "")]
257 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
260 emit_insn (gen_load_macho_picbase_si (operands[0], operands[1]));
262 emit_insn (gen_load_macho_picbase_di (operands[0], operands[1]));
267 (define_insn "load_macho_picbase_si"
268 [(set (match_operand:SI 0 "register_operand" "=l")
269 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
271 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
273 [(set_attr "type" "branch")
274 (set_attr "length" "4")])
276 (define_insn "load_macho_picbase_di"
277 [(set (match_operand:DI 0 "register_operand" "=l")
278 (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] UNSPEC_LD_MPIC))]
279 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
281 [(set_attr "type" "branch")
282 (set_attr "length" "4")])
284 (define_expand "macho_correct_pic"
285 [(set (match_operand 0 "" "")
286 (plus (match_operand 1 "" "")
287 (unspec [(match_operand 2 "" "")
288 (match_operand 3 "" "")]
289 UNSPEC_MPIC_CORRECT)))]
290 "DEFAULT_ABI == ABI_DARWIN"
293 emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
296 emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
302 (define_insn "macho_correct_pic_si"
303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
304 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
305 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
306 (match_operand:SI 3 "immediate_operand" "s")]
307 UNSPEC_MPIC_CORRECT)))]
308 "DEFAULT_ABI == ABI_DARWIN"
309 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
310 [(set_attr "length" "8")])
312 (define_insn "macho_correct_pic_di"
313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
314 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
315 (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
316 (match_operand:DI 3 "immediate_operand" "s")]
318 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
319 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
320 [(set_attr "length" "8")])
322 (define_insn "*call_indirect_nonlocal_darwin64"
323 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
324 (match_operand 1 "" "g,g,g,g"))
325 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
326 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
327 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
331 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
332 (set_attr "length" "4,4,8,8")])
334 (define_insn "*call_nonlocal_darwin64"
335 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
336 (match_operand 1 "" "g,g"))
337 (use (match_operand:SI 2 "immediate_operand" "O,n"))
338 (clobber (match_scratch:SI 3 "=l,l"))]
339 "(DEFAULT_ABI == ABI_DARWIN)
340 && (INTVAL (operands[2]) & CALL_LONG) == 0"
343 return output_call(insn, operands, 0, 2);
348 [(set_attr "type" "branch,branch")
349 (set_attr "length" "4,8")])
351 (define_insn "*call_value_indirect_nonlocal_darwin64"
352 [(set (match_operand 0 "" "")
353 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
354 (match_operand 2 "" "g,g,g,g")))
355 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
356 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
357 "DEFAULT_ABI == ABI_DARWIN"
361 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
362 (set_attr "length" "4,4,8,8")])
364 (define_insn "*call_value_nonlocal_darwin64"
365 [(set (match_operand 0 "" "")
366 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
367 (match_operand 2 "" "g,g")))
368 (use (match_operand:SI 3 "immediate_operand" "O,n"))
369 (clobber (match_scratch:SI 4 "=l,l"))]
370 "(DEFAULT_ABI == ABI_DARWIN)
371 && (INTVAL (operands[3]) & CALL_LONG) == 0"
374 return output_call(insn, operands, 1, 3);
379 [(set_attr "type" "branch,branch")
380 (set_attr "length" "4,8")])
382 (define_insn "*sibcall_nonlocal_darwin64"
383 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
384 (match_operand 1 "" ""))
385 (use (match_operand 2 "immediate_operand" "O,n"))
386 (use (match_operand:SI 3 "register_operand" "l,l"))
388 "(DEFAULT_ABI == ABI_DARWIN)
389 && (INTVAL (operands[2]) & CALL_LONG) == 0"
393 [(set_attr "type" "branch,branch")
394 (set_attr "length" "4,8")])
396 (define_insn "*sibcall_value_nonlocal_darwin64"
397 [(set (match_operand 0 "" "")
398 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
399 (match_operand 2 "" "")))
400 (use (match_operand:SI 3 "immediate_operand" "O,n"))
401 (use (match_operand:SI 4 "register_operand" "l,l"))
403 "(DEFAULT_ABI == ABI_DARWIN)
404 && (INTVAL (operands[3]) & CALL_LONG) == 0"
409 [(set_attr "type" "branch,branch")
410 (set_attr "length" "4,8")])
413 (define_insn "*sibcall_symbolic_64"
414 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
415 (match_operand 1 "" ""))
416 (use (match_operand 2 "" ""))
417 (use (match_operand:SI 3 "register_operand" "l,l"))
419 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
422 switch (which_alternative)
424 case 0: return \"b %z0\";
425 case 1: return \"b%T0\";
426 default: gcc_unreachable ();
429 [(set_attr "type" "branch")
430 (set_attr "length" "4")])
432 (define_insn "*sibcall_value_symbolic_64"
433 [(set (match_operand 0 "" "")
434 (call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
435 (match_operand 2 "" "")))
436 (use (match_operand:SI 3 "" ""))
437 (use (match_operand:SI 4 "register_operand" "l,l"))
439 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
442 switch (which_alternative)
444 case 0: return \"b %z1\";
445 case 1: return \"b%T1\";
446 default: gcc_unreachable ();
449 [(set_attr "type" "branch")
450 (set_attr "length" "4")])