gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VSPLTISW     141)
  24    (UNSPEC_VSPLTISH     140)
  25    (UNSPEC_VSPLTISB     139)
  26    ])
  27
  28 ;; Generic LVX load instruction.
  29 (define_insn "altivec_lvx_4si"
  30   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  31         (match_operand:V4SI 1 "memory_operand" "m"))]
  32   "TARGET_ALTIVEC"
  33   "lvx %0,%y1"
  34   [(set_attr "type" "vecload")])
  35
  36 (define_insn "altivec_lvx_8hi"
  37   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  38         (match_operand:V8HI 1 "memory_operand" "m"))]
  39   "TARGET_ALTIVEC"
  40   "lvx %0,%y1"
  41   [(set_attr "type" "vecload")])
  42
  43 (define_insn "altivec_lvx_16qi"
  44   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  45         (match_operand:V16QI 1 "memory_operand" "m"))]
  46   "TARGET_ALTIVEC"
  47   "lvx %0,%y1"
  48   [(set_attr "type" "vecload")])
  49
  50 (define_insn "altivec_lvx_4sf"
  51   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  52         (match_operand:V4SF 1 "memory_operand" "m"))]
  53   "TARGET_ALTIVEC"
  54   "lvx %0,%y1"
  55   [(set_attr "type" "vecload")])
  56
  57 ;; Generic STVX store instruction.
  58 (define_insn "altivec_stvx_4si"
  59   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  60         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  61   "TARGET_ALTIVEC"
  62   "stvx %1,%y0"
  63   [(set_attr "type" "vecstore")])
  64
  65 (define_insn "altivec_stvx_8hi"
  66   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  67         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  68   "TARGET_ALTIVEC"
  69   "stvx %1,%y0"
  70   [(set_attr "type" "vecstore")])
  71
  72 (define_insn "altivec_stvx_16qi"
  73   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  74         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 (define_insn "altivec_stvx_4sf"
  80   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  81         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  82   "TARGET_ALTIVEC"
  83   "stvx %1,%y0"
  84   [(set_attr "type" "vecstore")])
  85
  86 ;; Vector move instructions.
  87 (define_expand "movv4si"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  89         (match_operand:V4SI 1 "any_operand" ""))]
  90   "TARGET_ALTIVEC"
  91   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  92
  93 (define_insn "*movv4si_internal"
  94   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  95         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
  96   "TARGET_ALTIVEC"
  97   "*
  98 {
  99   switch (which_alternative)
 100     {
 101     case 0: return \"stvx %1,%y0\";
 102     case 1: return \"lvx %0,%y1\";
 103     case 2: return \"vor %0,%1,%1\";
 104     case 3: return \"#\";
 105     case 4: return \"#\";
 106     case 5: return \"#\";
 107     case 6: return output_vec_const_move (operands);
 108     default: abort();
 109     }
 110 }"
 111   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 112
 113 (define_split
 114   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 115         (match_operand:V4SI 1 "input_operand" ""))]
 116   "TARGET_ALTIVEC && reload_completed && TARGET_POWERPC64
 117    && altivec_in_gprs_p (operands[0], operands[1])"
 118   [(set (match_dup 2) (match_dup 4))
 119    (set (match_dup 3) (match_dup 5))]
 120 "{
 121      rs6000_split_altivec_in_gprs (operands);
 122 }")
 123
 124 (define_split
 125   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 126         (match_operand:V4SI 1 "input_operand" ""))]
 127   "TARGET_ALTIVEC && reload_completed && !TARGET_POWERPC64
 128    && altivec_in_gprs_p (operands[0], operands[1])"
 129   [(set (match_dup 2) (match_dup 6))
 130    (set (match_dup 3) (match_dup 7))
 131    (set (match_dup 4) (match_dup 8))
 132    (set (match_dup 5) (match_dup 9))]
 133 "{
 134      rs6000_split_altivec_in_gprs (operands);
 135 }")
 136
 137 (define_split
 138   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 139         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 140   "TARGET_ALTIVEC && reload_completed"
 141   [(set (match_dup 0)
 142         (unspec:V4SI [(match_dup 3)] UNSPEC_VSPLTISW))
 143    (set (match_dup 0)
 144         (plus:V4SI (match_dup 0)
 145                    (match_dup 0)))]
 146   "
 147 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 148
 149 (define_expand "movv8hi"
 150   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 151         (match_operand:V8HI 1 "any_operand" ""))]
 152   "TARGET_ALTIVEC"
 153   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 154
 155 (define_insn "*movv8hi_internal1"
 156   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 157         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
 158   "TARGET_ALTIVEC"
 159   "*
 160 {
 161    switch (which_alternative)
 162      {
 163      case 0: return \"stvx %1,%y0\";
 164      case 1: return \"lvx %0,%y1\";
 165      case 2: return \"vor %0,%1,%1\";
 166      case 3: return \"#\";
 167      case 4: return \"#\";
 168      case 5: return \"#\";
 169      case 6: return output_vec_const_move (operands);
 170      default: abort ();
 171      }
 172 }"
 173   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 174
 175 (define_split
 176   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 177         (match_operand:V8HI 1 "input_operand" ""))]
 178   "TARGET_ALTIVEC && reload_completed && TARGET_POWERPC64
 179    && altivec_in_gprs_p (operands[0], operands[1])"
 180   [(set (match_dup 2) (match_dup 4))
 181    (set (match_dup 3) (match_dup 5))]
 182 "{
 183      rs6000_split_altivec_in_gprs (operands);
 184 }")
 185
 186 (define_split
 187   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 188         (match_operand:V8HI 1 "input_operand" ""))]
 189   "TARGET_ALTIVEC && reload_completed && !TARGET_POWERPC64
 190    && altivec_in_gprs_p (operands[0], operands[1])"
 191   [(set (match_dup 2) (match_dup 6))
 192    (set (match_dup 3) (match_dup 7))
 193    (set (match_dup 4) (match_dup 8))
 194    (set (match_dup 5) (match_dup 9))]
 195 "{
 196      rs6000_split_altivec_in_gprs (operands);
 197 }")
 198
 199 (define_split
 200   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 201         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 202   "TARGET_ALTIVEC && reload_completed"
 203   [(set (match_dup 0)
 204         (unspec:V8HI [(match_dup 3)] UNSPEC_VSPLTISH))
 205    (set (match_dup 0)
 206         (plus:V8HI (match_dup 0)
 207                    (match_dup 0)))]
 208   "
 209 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 210
 211 (define_expand "movv16qi"
 212   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 213         (match_operand:V16QI 1 "any_operand" ""))]
 214   "TARGET_ALTIVEC"
 215   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 216
 217 (define_insn "*movv16qi_internal1"
 218   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 219         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
 220   "TARGET_ALTIVEC"
 221   "*
 222 {
 223   switch (which_alternative)
 224     {
 225     case 0: return \"stvx %1,%y0\";
 226     case 1: return \"lvx %0,%y1\";
 227     case 2: return \"vor %0,%1,%1\";
 228     case 3: return \"#\";
 229     case 4: return \"#\";
 230     case 5: return \"#\";
 231     case 6: return output_vec_const_move (operands);
 232     default: abort ();
 233     }
 234 }"
 235   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 236
 237 (define_split
 238   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 239         (match_operand:V16QI 1 "input_operand" ""))]
 240   "TARGET_ALTIVEC && reload_completed && TARGET_POWERPC64
 241    && altivec_in_gprs_p (operands[0], operands[1])"
 242   [(set (match_dup 2) (match_dup 4))
 243    (set (match_dup 3) (match_dup 5))]
 244 "{
 245      rs6000_split_altivec_in_gprs (operands);
 246 }")
 247
 248 (define_split
 249   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 250         (match_operand:V16QI 1 "input_operand" ""))]
 251   "TARGET_ALTIVEC && reload_completed && !TARGET_POWERPC64
 252    && altivec_in_gprs_p (operands[0], operands[1])"
 253   [(set (match_dup 2) (match_dup 6))
 254    (set (match_dup 3) (match_dup 7))
 255    (set (match_dup 4) (match_dup 8))
 256    (set (match_dup 5) (match_dup 9))]
 257 "{
 258      rs6000_split_altivec_in_gprs (operands);
 259 }")
 260
 261 (define_split
 262   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 263         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 264   "TARGET_ALTIVEC && reload_completed"
 265   [(set (match_dup 0)
 266         (unspec:V16QI [(match_dup 3)] UNSPEC_VSPLTISB))
 267    (set (match_dup 0)
 268         (plus:V16QI (match_dup 0)
 269                    (match_dup 0)))]
 270   "
 271 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 272
 273 (define_expand "movv4sf"
 274   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 275         (match_operand:V4SF 1 "any_operand" ""))]
 276   "TARGET_ALTIVEC"
 277   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 278
 279 (define_insn "*movv4sf_internal1"
 280   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 281         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
 282   "TARGET_ALTIVEC"
 283   "*
 284 {
 285   switch (which_alternative)
 286     {
 287     case 0: return \"stvx %1,%y0\";
 288     case 1: return \"lvx %0,%y1\";
 289     case 2: return \"vor %0,%1,%1\";
 290     case 3: return \"#\";
 291     case 4: return \"#\";
 292     case 5: return \"#\";
 293     case 6: return output_vec_const_move (operands);
 294     default: abort ();
 295     }
 296 }"
 297   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 298
 299 (define_split
 300   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 301         (match_operand:V4SF 1 "input_operand" ""))]
 302   "TARGET_ALTIVEC && reload_completed && TARGET_POWERPC64
 303    && altivec_in_gprs_p (operands[0], operands[1])"
 304   [(set (match_dup 2) (match_dup 4))
 305    (set (match_dup 3) (match_dup 5))]
 306 "{
 307      rs6000_split_altivec_in_gprs (operands);
 308 }")
 309
 310 (define_split
 311   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 312         (match_operand:V4SF 1 "input_operand" ""))]
 313   "TARGET_ALTIVEC && reload_completed && !TARGET_POWERPC64
 314    && altivec_in_gprs_p (operands[0], operands[1])"
 315   [(set (match_dup 2) (match_dup 6))
 316    (set (match_dup 3) (match_dup 7))
 317    (set (match_dup 4) (match_dup 8))
 318    (set (match_dup 5) (match_dup 9))]
 319 "{
 320      rs6000_split_altivec_in_gprs (operands);
 321 }")
 322
 323 (define_insn "get_vrsave_internal"
 324   [(set (match_operand:SI 0 "register_operand" "=r")
 325         (unspec:SI [(reg:SI 109)] 214))]
 326   "TARGET_ALTIVEC"
 327   "*
 328 {
 329   if (TARGET_MACHO)
 330      return \"mfspr %0,256\";
 331   else
 332      return \"mfvrsave %0\";
 333 }"
 334   [(set_attr "type" "*")])
 335
 336 (define_insn "*set_vrsave_internal"
 337   [(match_parallel 0 "vrsave_operation"
 338      [(set (reg:SI 109)
 339            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 340                                 (reg:SI 109)] 30))])]
 341   "TARGET_ALTIVEC"
 342   "*
 343 {
 344   if (TARGET_MACHO)
 345     return \"mtspr 256,%1\";
 346   else
 347     return \"mtvrsave %1\";
 348 }"
 349   [(set_attr "type" "*")])
 350
 351 ;; Simple binary operations.
 352
 353 (define_insn "addv16qi3"
 354   [(set (match_operand:V16QI 0 "register_operand" "=v")
 355         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 356                     (match_operand:V16QI 2 "register_operand" "v")))]
 357   "TARGET_ALTIVEC"
 358   "vaddubm %0,%1,%2"
 359   [(set_attr "type" "vecsimple")])
 360
 361 (define_insn "addv8hi3"
 362   [(set (match_operand:V8HI 0 "register_operand" "=v")
 363         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 364                    (match_operand:V8HI 2 "register_operand" "v")))]
 365   "TARGET_ALTIVEC"
 366   "vadduhm %0,%1,%2"
 367   [(set_attr "type" "vecsimple")])
 368
 369 (define_insn "addv4si3"
 370   [(set (match_operand:V4SI 0 "register_operand" "=v")
 371         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 372                    (match_operand:V4SI 2 "register_operand" "v")))]
 373   "TARGET_ALTIVEC"
 374   "vadduwm %0,%1,%2"
 375   [(set_attr "type" "vecsimple")])
 376
 377 (define_insn "addv4sf3"
 378   [(set (match_operand:V4SF 0 "register_operand" "=v")
 379         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 380                    (match_operand:V4SF 2 "register_operand" "v")))]
 381   "TARGET_ALTIVEC"
 382   "vaddfp %0,%1,%2"
 383   [(set_attr "type" "vecfloat")])
 384
 385 (define_insn "altivec_vaddcuw"
 386   [(set (match_operand:V4SI 0 "register_operand" "=v")
 387         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 388                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 389   "TARGET_ALTIVEC"
 390   "vaddcuw %0,%1,%2"
 391   [(set_attr "type" "vecsimple")])
 392
 393 (define_insn "altivec_vaddubs"
 394   [(set (match_operand:V16QI 0 "register_operand" "=v")
 395         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 396                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 397    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 398   "TARGET_ALTIVEC"
 399   "vaddubs %0,%1,%2"
 400   [(set_attr "type" "vecsimple")])
 401
 402 (define_insn "altivec_vaddsbs"
 403   [(set (match_operand:V16QI 0 "register_operand" "=v")
 404         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 405                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 406    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 407   "TARGET_ALTIVEC"
 408   "vaddsbs %0,%1,%2"
 409   [(set_attr "type" "vecsimple")])
 410
 411 (define_insn "altivec_vadduhs"
 412   [(set (match_operand:V8HI 0 "register_operand" "=v")
 413         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 414                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 415    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 416   "TARGET_ALTIVEC"
 417   "vadduhs %0,%1,%2"
 418   [(set_attr "type" "vecsimple")])
 419
 420 (define_insn "altivec_vaddshs"
 421   [(set (match_operand:V8HI 0 "register_operand" "=v")
 422         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 423                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 424    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 425   "TARGET_ALTIVEC"
 426   "vaddshs %0,%1,%2"
 427   [(set_attr "type" "vecsimple")])
 428
 429 (define_insn "altivec_vadduws"
 430   [(set (match_operand:V4SI 0 "register_operand" "=v")
 431         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 432                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 433    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 434   "TARGET_ALTIVEC"
 435   "vadduws %0,%1,%2"
 436   [(set_attr "type" "vecsimple")])
 437
 438 (define_insn "altivec_vaddsws"
 439   [(set (match_operand:V4SI 0 "register_operand" "=v")
 440         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 441                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 442    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 443   "TARGET_ALTIVEC"
 444   "vaddsws %0,%1,%2"
 445   [(set_attr "type" "vecsimple")])
 446
 447 (define_insn "andv4si3"
 448   [(set (match_operand:V4SI 0 "register_operand" "=v")
 449         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 450                   (match_operand:V4SI 2 "register_operand" "v")))]
 451   "TARGET_ALTIVEC"
 452   "vand %0,%1,%2"
 453   [(set_attr "type" "vecsimple")])
 454
 455 (define_insn "altivec_vandc"
 456   [(set (match_operand:V4SI 0 "register_operand" "=v")
 457         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 458                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 459   "TARGET_ALTIVEC"
 460   "vandc %0,%1,%2"
 461   [(set_attr "type" "vecsimple")])
 462
 463 (define_insn "altivec_vavgub"
 464   [(set (match_operand:V16QI 0 "register_operand" "=v")
 465         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 466                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 467   "TARGET_ALTIVEC"
 468   "vavgub %0,%1,%2"
 469   [(set_attr "type" "vecsimple")])
 470
 471 (define_insn "altivec_vavgsb"
 472   [(set (match_operand:V16QI 0 "register_operand" "=v")
 473         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 474                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 475   "TARGET_ALTIVEC"
 476   "vavgsb %0,%1,%2"
 477   [(set_attr "type" "vecsimple")])
 478
 479 (define_insn "altivec_vavguh"
 480   [(set (match_operand:V8HI 0 "register_operand" "=v")
 481         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 482                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 483   "TARGET_ALTIVEC"
 484   "vavguh %0,%1,%2"
 485   [(set_attr "type" "vecsimple")])
 486
 487 (define_insn "altivec_vavgsh"
 488   [(set (match_operand:V8HI 0 "register_operand" "=v")
 489         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 490                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 491   "TARGET_ALTIVEC"
 492   "vavgsh %0,%1,%2"
 493   [(set_attr "type" "vecsimple")])
 494
 495 (define_insn "altivec_vavguw"
 496   [(set (match_operand:V4SI 0 "register_operand" "=v")
 497         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 498                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 499   "TARGET_ALTIVEC"
 500   "vavguw %0,%1,%2"
 501   [(set_attr "type" "vecsimple")])
 502
 503 (define_insn "altivec_vavgsw"
 504   [(set (match_operand:V4SI 0 "register_operand" "=v")
 505         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 506                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 507   "TARGET_ALTIVEC"
 508   "vavgsw %0,%1,%2"
 509   [(set_attr "type" "vecsimple")])
 510
 511 (define_insn "altivec_vcmpbfp"
 512   [(set (match_operand:V4SI 0 "register_operand" "=v")
 513         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 514                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 515   "TARGET_ALTIVEC"
 516   "vcmpbfp %0,%1,%2"
 517   [(set_attr "type" "veccmp")])
 518
 519 (define_insn "altivec_vcmpequb"
 520   [(set (match_operand:V16QI 0 "register_operand" "=v")
 521         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 522                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 523   "TARGET_ALTIVEC"
 524   "vcmpequb %0,%1,%2"
 525   [(set_attr "type" "vecsimple")])
 526
 527 (define_insn "altivec_vcmpequh"
 528   [(set (match_operand:V8HI 0 "register_operand" "=v")
 529         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 530                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 531   "TARGET_ALTIVEC"
 532   "vcmpequh %0,%1,%2"
 533   [(set_attr "type" "vecsimple")])
 534
 535 (define_insn "altivec_vcmpequw"
 536   [(set (match_operand:V4SI 0 "register_operand" "=v")
 537         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 538                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 539   "TARGET_ALTIVEC"
 540   "vcmpequw %0,%1,%2"
 541   [(set_attr "type" "vecsimple")])
 542
 543 (define_insn "altivec_vcmpeqfp"
 544   [(set (match_operand:V4SI 0 "register_operand" "=v")
 545         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 546                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 547   "TARGET_ALTIVEC"
 548   "vcmpeqfp %0,%1,%2"
 549   [(set_attr "type" "veccmp")])
 550
 551 (define_insn "altivec_vcmpgefp"
 552   [(set (match_operand:V4SI 0 "register_operand" "=v")
 553         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 554                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 555   "TARGET_ALTIVEC"
 556   "vcmpgefp %0,%1,%2"
 557   [(set_attr "type" "veccmp")])
 558
 559 (define_insn "altivec_vcmpgtub"
 560   [(set (match_operand:V16QI 0 "register_operand" "=v")
 561         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 562                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 563   "TARGET_ALTIVEC"
 564   "vcmpgtub %0,%1,%2"
 565   [(set_attr "type" "vecsimple")])
 566
 567 (define_insn "altivec_vcmpgtsb"
 568   [(set (match_operand:V16QI 0 "register_operand" "=v")
 569         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 570                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 571   "TARGET_ALTIVEC"
 572   "vcmpgtsb %0,%1,%2"
 573   [(set_attr "type" "vecsimple")])
 574
 575 (define_insn "altivec_vcmpgtuh"
 576   [(set (match_operand:V8HI 0 "register_operand" "=v")
 577         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 578                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 579   "TARGET_ALTIVEC"
 580   "vcmpgtuh %0,%1,%2"
 581   [(set_attr "type" "vecsimple")])
 582
 583 (define_insn "altivec_vcmpgtsh"
 584   [(set (match_operand:V8HI 0 "register_operand" "=v")
 585         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 586                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 587   "TARGET_ALTIVEC"
 588   "vcmpgtsh %0,%1,%2"
 589   [(set_attr "type" "vecsimple")])
 590
 591 (define_insn "altivec_vcmpgtuw"
 592   [(set (match_operand:V4SI 0 "register_operand" "=v")
 593         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 594                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 595   "TARGET_ALTIVEC"
 596   "vcmpgtuw %0,%1,%2"
 597   [(set_attr "type" "vecsimple")])
 598
 599 (define_insn "altivec_vcmpgtsw"
 600   [(set (match_operand:V4SI 0 "register_operand" "=v")
 601         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 602                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 603   "TARGET_ALTIVEC"
 604   "vcmpgtsw %0,%1,%2"
 605   [(set_attr "type" "vecsimple")])
 606
 607 (define_insn "altivec_vcmpgtfp"
 608   [(set (match_operand:V4SI 0 "register_operand" "=v")
 609         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 610                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 611   "TARGET_ALTIVEC"
 612   "vcmpgtfp %0,%1,%2"
 613   [(set_attr "type" "veccmp")])
 614
 615 ;; Fused multiply add
 616 (define_insn "altivec_vmaddfp"
 617   [(set (match_operand:V4SF 0 "register_operand" "=v")
 618         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 619                               (match_operand:V4SF 2 "register_operand" "v"))
 620                    (match_operand:V4SF 3 "register_operand" "v")))]
 621   "TARGET_ALTIVEC"
 622   "vmaddfp %0,%1,%2,%3"
 623   [(set_attr "type" "vecfloat")])
 624
 625 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 626
 627 (define_expand "mulv4sf3"
 628   [(use (match_operand:V4SF 0 "register_operand" ""))
 629    (use (match_operand:V4SF 1 "register_operand" ""))
 630    (use (match_operand:V4SF 2 "register_operand" ""))]
 631   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 632   "
 633 {
 634   rtx neg0;
 635
 636   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 637   neg0 = gen_reg_rtx (V4SFmode);
 638   emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
 639   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 640
 641   /* Use the multiply-add.  */
 642   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 643                                   neg0));
 644   DONE;
 645 }")
 646
 647 ;; Fused multiply subtract
 648 (define_insn "altivec_vnmsubfp"
 649   [(set (match_operand:V4SF 0 "register_operand" "=v")
 650         (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 651                                (match_operand:V4SF 2 "register_operand" "v"))
 652                     (match_operand:V4SF 3 "register_operand" "v")))]
 653   "TARGET_ALTIVEC"
 654   "vnmsubfp %0,%1,%2,%3"
 655   [(set_attr "type" "vecfloat")])
 656
 657
 658 (define_insn "altivec_vmsumubm"
 659   [(set (match_operand:V4SI 0 "register_operand" "=v")
 660         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 661                       (match_operand:V16QI 2 "register_operand" "v")
 662                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 663   "TARGET_ALTIVEC"
 664   "vmsumubm %0,%1,%2,%3"
 665   [(set_attr "type" "veccomplex")])
 666
 667 (define_insn "altivec_vmsummbm"
 668   [(set (match_operand:V4SI 0 "register_operand" "=v")
 669         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 670                       (match_operand:V16QI 2 "register_operand" "v")
 671                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 672   "TARGET_ALTIVEC"
 673   "vmsumubm %0,%1,%2,%3"
 674   [(set_attr "type" "veccomplex")])
 675
 676 (define_insn "altivec_vmsumuhm"
 677   [(set (match_operand:V4SI 0 "register_operand" "=v")
 678         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 679                       (match_operand:V8HI 2 "register_operand" "v")
 680                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 681   "TARGET_ALTIVEC"
 682   "vmsumuhm %0,%1,%2,%3"
 683   [(set_attr "type" "veccomplex")])
 684
 685 (define_insn "altivec_vmsumshm"
 686   [(set (match_operand:V4SI 0 "register_operand" "=v")
 687         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 688                       (match_operand:V8HI 2 "register_operand" "v")
 689                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 690   "TARGET_ALTIVEC"
 691   "vmsumshm %0,%1,%2,%3"
 692   [(set_attr "type" "veccomplex")])
 693
 694 (define_insn "altivec_vmsumuhs"
 695   [(set (match_operand:V4SI 0 "register_operand" "=v")
 696         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 697                       (match_operand:V8HI 2 "register_operand" "v")
 698                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 699    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 700   "TARGET_ALTIVEC"
 701   "vmsumuhs %0,%1,%2,%3"
 702   [(set_attr "type" "veccomplex")])
 703
 704 (define_insn "altivec_vmsumshs"
 705   [(set (match_operand:V4SI 0 "register_operand" "=v")
 706         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 707                       (match_operand:V8HI 2 "register_operand" "v")
 708                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 709    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 710   "TARGET_ALTIVEC"
 711   "vmsumshs %0,%1,%2,%3"
 712   [(set_attr "type" "veccomplex")])
 713
 714 (define_insn "umaxv16qi3"
 715   [(set (match_operand:V16QI 0 "register_operand" "=v")
 716         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 717                     (match_operand:V16QI 2 "register_operand" "v")))]
 718   "TARGET_ALTIVEC"
 719   "vmaxub %0,%1,%2"
 720   [(set_attr "type" "vecsimple")])
 721
 722 (define_insn "smaxv16qi3"
 723   [(set (match_operand:V16QI 0 "register_operand" "=v")
 724         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 725                     (match_operand:V16QI 2 "register_operand" "v")))]
 726   "TARGET_ALTIVEC"
 727   "vmaxsb %0,%1,%2"
 728   [(set_attr "type" "vecsimple")])
 729
 730 (define_insn "umaxv8hi3"
 731   [(set (match_operand:V8HI 0 "register_operand" "=v")
 732         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 733                    (match_operand:V8HI 2 "register_operand" "v")))]
 734   "TARGET_ALTIVEC"
 735   "vmaxuh %0,%1,%2"
 736   [(set_attr "type" "vecsimple")])
 737
 738 (define_insn "smaxv8hi3"
 739   [(set (match_operand:V8HI 0 "register_operand" "=v")
 740         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 741                    (match_operand:V8HI 2 "register_operand" "v")))]
 742   "TARGET_ALTIVEC"
 743   "vmaxsh %0,%1,%2"
 744   [(set_attr "type" "vecsimple")])
 745
 746 (define_insn "umaxv4si3"
 747   [(set (match_operand:V4SI 0 "register_operand" "=v")
 748         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 749                    (match_operand:V4SI 2 "register_operand" "v")))]
 750   "TARGET_ALTIVEC"
 751   "vmaxuw %0,%1,%2"
 752   [(set_attr "type" "vecsimple")])
 753
 754 (define_insn "smaxv4si3"
 755   [(set (match_operand:V4SI 0 "register_operand" "=v")
 756         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 757                    (match_operand:V4SI 2 "register_operand" "v")))]
 758   "TARGET_ALTIVEC"
 759   "vmaxsw %0,%1,%2"
 760   [(set_attr "type" "vecsimple")])
 761
 762 (define_insn "smaxv4sf3"
 763   [(set (match_operand:V4SF 0 "register_operand" "=v")
 764         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 765                    (match_operand:V4SF 2 "register_operand" "v")))]
 766   "TARGET_ALTIVEC"
 767   "vmaxfp %0,%1,%2"
 768   [(set_attr "type" "veccmp")])
 769
 770 (define_insn "altivec_vmhaddshs"
 771   [(set (match_operand:V8HI 0 "register_operand" "=v")
 772         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 773                       (match_operand:V8HI 2 "register_operand" "v")
 774                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 775    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 776   "TARGET_ALTIVEC"
 777   "vmhaddshs %0,%1,%2,%3"
 778   [(set_attr "type" "veccomplex")])
 779 (define_insn "altivec_vmhraddshs"
 780   [(set (match_operand:V8HI 0 "register_operand" "=v")
 781         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 782                       (match_operand:V8HI 2 "register_operand" "v")
 783                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 784    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 785   "TARGET_ALTIVEC"
 786   "vmhraddshs %0,%1,%2,%3"
 787   [(set_attr "type" "veccomplex")])
 788 (define_insn "altivec_vmladduhm"
 789   [(set (match_operand:V8HI 0 "register_operand" "=v")
 790         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 791                       (match_operand:V8HI 2 "register_operand" "v")
 792                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 793   "TARGET_ALTIVEC"
 794   "vmladduhm %0,%1,%2,%3"
 795   [(set_attr "type" "veccomplex")])
 796
 797 (define_insn "altivec_vmrghb"
 798   [(set (match_operand:V16QI 0 "register_operand" "=v")
 799         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 800                                            (parallel [(const_int 8)
 801                                                       (const_int 9)
 802                                                       (const_int 10)
 803                                                       (const_int 11)
 804                                                       (const_int 12)
 805                                                       (const_int 13)
 806                                                       (const_int 14)
 807                                                       (const_int 15)
 808                                                       (const_int 0)
 809                                                       (const_int 1)
 810                                                       (const_int 2)
 811                                                       (const_int 3)
 812                                                       (const_int 4)
 813                                                       (const_int 5)
 814                                                       (const_int 6)
 815                                                       (const_int 7)]))
 816                       (match_operand:V16QI 2 "register_operand" "v")
 817                       (const_int 255)))]
 818   "TARGET_ALTIVEC"
 819   "vmrghb %0,%1,%2"
 820   [(set_attr "type" "vecperm")])
 821
 822 (define_insn "altivec_vmrghh"
 823   [(set (match_operand:V8HI 0 "register_operand" "=v")
 824         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 825                                            (parallel [(const_int 4)
 826                                                       (const_int 5)
 827                                                       (const_int 6)
 828                                                       (const_int 7)
 829                                                       (const_int 0)
 830                                                       (const_int 1)
 831                                                       (const_int 2)
 832                                                       (const_int 3)]))
 833                       (match_operand:V8HI 2 "register_operand" "v")
 834                       (const_int 15)))]
 835   "TARGET_ALTIVEC"
 836   "vmrghh %0,%1,%2"
 837   [(set_attr "type" "vecperm")])
 838
 839 (define_insn "altivec_vmrghw"
 840   [(set (match_operand:V4SI 0 "register_operand" "=v")
 841         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 842                                          (parallel [(const_int 2)
 843                                                     (const_int 3)
 844                                                     (const_int 0)
 845                                                     (const_int 1)]))
 846                       (match_operand:V4SI 2 "register_operand" "v")
 847                       (const_int 12)))]
 848   "TARGET_ALTIVEC"
 849   "vmrghw %0,%1,%2"
 850   [(set_attr "type" "vecperm")])
 851
 852 (define_insn "altivec_vmrglb"
 853   [(set (match_operand:V16QI 0 "register_operand" "=v")
 854         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 855                                            (parallel [(const_int 0)
 856                                                       (const_int 1)
 857                                                       (const_int 2)
 858                                                       (const_int 3)
 859                                                       (const_int 4)
 860                                                       (const_int 5)
 861                                                       (const_int 6)
 862                                                       (const_int 7)
 863                                                       (const_int 8)
 864                                                       (const_int 9)
 865                                                       (const_int 10)
 866                                                       (const_int 11)
 867                                                       (const_int 12)
 868                                                       (const_int 13)
 869                                                       (const_int 14)
 870                                                       (const_int 15)]))
 871                       (match_operand:V16QI 1 "register_operand" "v")
 872                       (const_int 255)))]
 873   "TARGET_ALTIVEC"
 874   "vmrglb %0,%1,%2"
 875   [(set_attr "type" "vecperm")])
 876
 877 (define_insn "altivec_vmrglh"
 878   [(set (match_operand:V8HI 0 "register_operand" "=v")
 879         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 880                                            (parallel [(const_int 0)
 881                                                       (const_int 1)
 882                                                       (const_int 2)
 883                                                       (const_int 3)
 884                                                       (const_int 4)
 885                                                       (const_int 5)
 886                                                       (const_int 6)
 887                                                       (const_int 7)]))
 888                       (match_operand:V8HI 1 "register_operand" "v")
 889                       (const_int 15)))]
 890   "TARGET_ALTIVEC"
 891   "vmrglh %0,%1,%2"
 892   [(set_attr "type" "vecperm")])
 893
 894 (define_insn "altivec_vmrglw"
 895   [(set (match_operand:V4SI 0 "register_operand" "=v")
 896         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 897                                          (parallel [(const_int 0)
 898                                                     (const_int 1)
 899                                                     (const_int 2)
 900                                                     (const_int 3)]))
 901                       (match_operand:V4SI 1 "register_operand" "v")
 902                       (const_int 12)))]
 903   "TARGET_ALTIVEC"
 904   "vmrglw %0,%1,%2"
 905   [(set_attr "type" "vecperm")])
 906
 907 (define_insn "uminv16qi3"
 908   [(set (match_operand:V16QI 0 "register_operand" "=v")
 909         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 910                     (match_operand:V16QI 2 "register_operand" "v")))]
 911   "TARGET_ALTIVEC"
 912   "vminub %0,%1,%2"
 913   [(set_attr "type" "vecsimple")])
 914
 915 (define_insn "sminv16qi3"
 916   [(set (match_operand:V16QI 0 "register_operand" "=v")
 917         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 918                     (match_operand:V16QI 2 "register_operand" "v")))]
 919   "TARGET_ALTIVEC"
 920   "vminsb %0,%1,%2"
 921   [(set_attr "type" "vecsimple")])
 922
 923 (define_insn "uminv8hi3"
 924   [(set (match_operand:V8HI 0 "register_operand" "=v")
 925         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 926                    (match_operand:V8HI 2 "register_operand" "v")))]
 927   "TARGET_ALTIVEC"
 928   "vminuh %0,%1,%2"
 929   [(set_attr "type" "vecsimple")])
 930
 931 (define_insn "sminv8hi3"
 932   [(set (match_operand:V8HI 0 "register_operand" "=v")
 933         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 934                    (match_operand:V8HI 2 "register_operand" "v")))]
 935   "TARGET_ALTIVEC"
 936   "vminsh %0,%1,%2"
 937   [(set_attr "type" "vecsimple")])
 938
 939 (define_insn "uminv4si3"
 940   [(set (match_operand:V4SI 0 "register_operand" "=v")
 941         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 942                    (match_operand:V4SI 2 "register_operand" "v")))]
 943   "TARGET_ALTIVEC"
 944   "vminuw %0,%1,%2"
 945   [(set_attr "type" "vecsimple")])
 946
 947 (define_insn "sminv4si3"
 948   [(set (match_operand:V4SI 0 "register_operand" "=v")
 949         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 950                    (match_operand:V4SI 2 "register_operand" "v")))]
 951   "TARGET_ALTIVEC"
 952   "vminsw %0,%1,%2"
 953   [(set_attr "type" "vecsimple")])
 954
 955 (define_insn "sminv4sf3"
 956   [(set (match_operand:V4SF 0 "register_operand" "=v")
 957         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 958                    (match_operand:V4SF 2 "register_operand" "v")))]
 959   "TARGET_ALTIVEC"
 960   "vminfp %0,%1,%2"
 961   [(set_attr "type" "veccmp")])
 962
 963 (define_insn "altivec_vmuleub"
 964   [(set (match_operand:V8HI 0 "register_operand" "=v")
 965         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 966                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 967   "TARGET_ALTIVEC"
 968   "vmuleub %0,%1,%2"
 969   [(set_attr "type" "veccomplex")])
 970
 971 (define_insn "altivec_vmulesb"
 972   [(set (match_operand:V8HI 0 "register_operand" "=v")
 973         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 974                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 975   "TARGET_ALTIVEC"
 976   "vmulesb %0,%1,%2"
 977   [(set_attr "type" "veccomplex")])
 978
 979 (define_insn "altivec_vmuleuh"
 980   [(set (match_operand:V4SI 0 "register_operand" "=v")
 981         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 982                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 983   "TARGET_ALTIVEC"
 984   "vmuleuh %0,%1,%2"
 985   [(set_attr "type" "veccomplex")])
 986
 987 (define_insn "altivec_vmulesh"
 988   [(set (match_operand:V4SI 0 "register_operand" "=v")
 989         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 990                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 991   "TARGET_ALTIVEC"
 992   "vmulesh %0,%1,%2"
 993   [(set_attr "type" "veccomplex")])
 994
 995 (define_insn "altivec_vmuloub"
 996   [(set (match_operand:V8HI 0 "register_operand" "=v")
 997         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 998                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 999   "TARGET_ALTIVEC"
1000   "vmuloub %0,%1,%2"
1001   [(set_attr "type" "veccomplex")])
1002
1003 (define_insn "altivec_vmulosb"
1004   [(set (match_operand:V8HI 0 "register_operand" "=v")
1005         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1006                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
1007   "TARGET_ALTIVEC"
1008   "vmulosb %0,%1,%2"
1009   [(set_attr "type" "veccomplex")])
1010
1011 (define_insn "altivec_vmulouh"
1012   [(set (match_operand:V4SI 0 "register_operand" "=v")
1013         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1014                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
1015   "TARGET_ALTIVEC"
1016   "vmulouh %0,%1,%2"
1017   [(set_attr "type" "veccomplex")])
1018
1019 (define_insn "altivec_vmulosh"
1020   [(set (match_operand:V4SI 0 "register_operand" "=v")
1021         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1022                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
1023   "TARGET_ALTIVEC"
1024   "vmulosh %0,%1,%2"
1025   [(set_attr "type" "veccomplex")])
1026
1027 (define_insn "altivec_vnor"
1028   [(set (match_operand:V4SI 0 "register_operand" "=v")
1029         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
1030                             (match_operand:V4SI 2 "register_operand" "v"))))]
1031   "TARGET_ALTIVEC"
1032   "vnor %0,%1,%2"
1033   [(set_attr "type" "vecsimple")])
1034
1035 (define_insn "iorv4si3"
1036   [(set (match_operand:V4SI 0 "register_operand" "=v")
1037         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
1038                   (match_operand:V4SI 2 "register_operand" "v")))]
1039   "TARGET_ALTIVEC"
1040   "vor %0,%1,%2"
1041   [(set_attr "type" "vecsimple")])
1042
1043 (define_insn "altivec_vpkuhum"
1044   [(set (match_operand:V16QI 0 "register_operand" "=v")
1045         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1046                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
1047   "TARGET_ALTIVEC"
1048   "vpkuhum %0,%1,%2"
1049   [(set_attr "type" "vecperm")])
1050
1051 (define_insn "altivec_vpkuwum"
1052   [(set (match_operand:V8HI 0 "register_operand" "=v")
1053         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1054                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
1055   "TARGET_ALTIVEC"
1056   "vpkuwum %0,%1,%2"
1057   [(set_attr "type" "vecperm")])
1058
1059 (define_insn "altivec_vpkpx"
1060   [(set (match_operand:V8HI 0 "register_operand" "=v")
1061         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1062                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
1063   "TARGET_ALTIVEC"
1064   "vpkpx %0,%1,%2"
1065   [(set_attr "type" "vecperm")])
1066
1067 (define_insn "altivec_vpkuhss"
1068   [(set (match_operand:V16QI 0 "register_operand" "=v")
1069         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1070                        (match_operand:V8HI 2 "register_operand" "v")] 96))
1071    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1072   "TARGET_ALTIVEC"
1073   "vpkuhss %0,%1,%2"
1074   [(set_attr "type" "vecperm")])
1075
1076 (define_insn "altivec_vpkshss"
1077   [(set (match_operand:V16QI 0 "register_operand" "=v")
1078         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1079                        (match_operand:V8HI 2 "register_operand" "v")] 97))
1080    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1081   "TARGET_ALTIVEC"
1082   "vpkshss %0,%1,%2"
1083   [(set_attr "type" "vecperm")])
1084
1085 (define_insn "altivec_vpkuwss"
1086   [(set (match_operand:V8HI 0 "register_operand" "=v")
1087         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1088                       (match_operand:V4SI 2 "register_operand" "v")] 98))
1089    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1090   "TARGET_ALTIVEC"
1091   "vpkuwss %0,%1,%2"
1092   [(set_attr "type" "vecperm")])
1093
1094 (define_insn "altivec_vpkswss"
1095   [(set (match_operand:V8HI 0 "register_operand" "=v")
1096         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1097                       (match_operand:V4SI 2 "register_operand" "v")] 99))
1098    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1099   "TARGET_ALTIVEC"
1100   "vpkswss %0,%1,%2"
1101   [(set_attr "type" "vecperm")])
1102
1103 (define_insn "altivec_vpkuhus"
1104   [(set (match_operand:V16QI 0 "register_operand" "=v")
1105         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1106                        (match_operand:V8HI 2 "register_operand" "v")] 100))
1107    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1108   "TARGET_ALTIVEC"
1109   "vpkuhus %0,%1,%2"
1110   [(set_attr "type" "vecperm")])
1111
1112 (define_insn "altivec_vpkshus"
1113   [(set (match_operand:V16QI 0 "register_operand" "=v")
1114         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1115                        (match_operand:V8HI 2 "register_operand" "v")] 101))
1116    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1117   "TARGET_ALTIVEC"
1118   "vpkshus %0,%1,%2"
1119   [(set_attr "type" "vecperm")])
1120
1121 (define_insn "altivec_vpkuwus"
1122   [(set (match_operand:V8HI 0 "register_operand" "=v")
1123         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1124                       (match_operand:V4SI 2 "register_operand" "v")] 102))
1125    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1126   "TARGET_ALTIVEC"
1127   "vpkuwus %0,%1,%2"
1128   [(set_attr "type" "vecperm")])
1129
1130 (define_insn "altivec_vpkswus"
1131   [(set (match_operand:V8HI 0 "register_operand" "=v")
1132         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1133                       (match_operand:V4SI 2 "register_operand" "v")] 103))
1134    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1135   "TARGET_ALTIVEC"
1136   "vpkswus %0,%1,%2"
1137   [(set_attr "type" "vecperm")])
1138
1139 (define_insn "altivec_vrlb"
1140   [(set (match_operand:V16QI 0 "register_operand" "=v")
1141         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1142                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1143   "TARGET_ALTIVEC"
1144   "vrlb %0,%1,%2"
1145   [(set_attr "type" "vecsimple")])
1146
1147 (define_insn "altivec_vrlh"
1148   [(set (match_operand:V8HI 0 "register_operand" "=v")
1149         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1150                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1151   "TARGET_ALTIVEC"
1152   "vrlh %0,%1,%2"
1153   [(set_attr "type" "vecsimple")])
1154
1155 (define_insn "altivec_vrlw"
1156   [(set (match_operand:V4SI 0 "register_operand" "=v")
1157         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1158                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1159   "TARGET_ALTIVEC"
1160   "vrlw %0,%1,%2"
1161   [(set_attr "type" "vecsimple")])
1162
1163 (define_insn "altivec_vslb"
1164   [(set (match_operand:V16QI 0 "register_operand" "=v")
1165         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1166                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1167   "TARGET_ALTIVEC"
1168   "vslb %0,%1,%2"
1169   [(set_attr "type" "vecsimple")])
1170
1171 (define_insn "altivec_vslh"
1172   [(set (match_operand:V8HI 0 "register_operand" "=v")
1173         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1174                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1175   "TARGET_ALTIVEC"
1176   "vslh %0,%1,%2"
1177   [(set_attr "type" "vecsimple")])
1178
1179 (define_insn "altivec_vslw"
1180   [(set (match_operand:V4SI 0 "register_operand" "=v")
1181         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1182                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1183   "TARGET_ALTIVEC"
1184   "vslw %0,%1,%2"
1185   [(set_attr "type" "vecsimple")])
1186
1187 (define_insn "altivec_vslw_v4sf"
1188   [(set (match_operand:V4SF 0 "register_operand" "=v")
1189         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1190                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
1191   "TARGET_ALTIVEC"
1192   "vslw %0,%1,%2"
1193   [(set_attr "type" "vecsimple")])
1194
1195 (define_insn "altivec_vsl"
1196   [(set (match_operand:V4SI 0 "register_operand" "=v")
1197         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1198                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1199   "TARGET_ALTIVEC"
1200   "vsl %0,%1,%2"
1201   [(set_attr "type" "vecperm")])
1202
1203 (define_insn "altivec_vslo"
1204   [(set (match_operand:V4SI 0 "register_operand" "=v")
1205         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1206                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1207   "TARGET_ALTIVEC"
1208   "vslo %0,%1,%2"
1209   [(set_attr "type" "vecperm")])
1210
1211 (define_insn "altivec_vsrb"
1212   [(set (match_operand:V16QI 0 "register_operand" "=v")
1213         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1214                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1215   "TARGET_ALTIVEC"
1216   "vsrb %0,%1,%2"
1217   [(set_attr "type" "vecsimple")])
1218
1219 (define_insn "altivec_vsrh"
1220   [(set (match_operand:V8HI 0 "register_operand" "=v")
1221         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1222                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1223   "TARGET_ALTIVEC"
1224   "vsrh %0,%1,%2"
1225   [(set_attr "type" "vecsimple")])
1226
1227 (define_insn "altivec_vsrw"
1228   [(set (match_operand:V4SI 0 "register_operand" "=v")
1229         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1230                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1231   "TARGET_ALTIVEC"
1232   "vsrw %0,%1,%2"
1233   [(set_attr "type" "vecsimple")])
1234
1235 (define_insn "altivec_vsrab"
1236   [(set (match_operand:V16QI 0 "register_operand" "=v")
1237         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1238                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1239   "TARGET_ALTIVEC"
1240   "vsrab %0,%1,%2"
1241   [(set_attr "type" "vecsimple")])
1242
1243 (define_insn "altivec_vsrah"
1244   [(set (match_operand:V8HI 0 "register_operand" "=v")
1245         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1246                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1247   "TARGET_ALTIVEC"
1248   "vsrah %0,%1,%2"
1249   [(set_attr "type" "vecsimple")])
1250
1251 (define_insn "altivec_vsraw"
1252   [(set (match_operand:V4SI 0 "register_operand" "=v")
1253         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1254                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1255   "TARGET_ALTIVEC"
1256   "vsraw %0,%1,%2"
1257   [(set_attr "type" "vecsimple")])
1258
1259 (define_insn "altivec_vsr"
1260   [(set (match_operand:V4SI 0 "register_operand" "=v")
1261         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1262                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1263   "TARGET_ALTIVEC"
1264   "vsr %0,%1,%2"
1265   [(set_attr "type" "vecperm")])
1266
1267 (define_insn "altivec_vsro"
1268   [(set (match_operand:V4SI 0 "register_operand" "=v")
1269         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1270                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1271   "TARGET_ALTIVEC"
1272   "vsro %0,%1,%2"
1273   [(set_attr "type" "vecperm")])
1274
1275 (define_insn "subv16qi3"
1276   [(set (match_operand:V16QI 0 "register_operand" "=v")
1277         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1278                      (match_operand:V16QI 2 "register_operand" "v")))]
1279   "TARGET_ALTIVEC"
1280   "vsububm %0,%1,%2"
1281   [(set_attr "type" "vecsimple")])
1282
1283 (define_insn "subv8hi3"
1284   [(set (match_operand:V8HI 0 "register_operand" "=v")
1285         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1286                     (match_operand:V8HI 2 "register_operand" "v")))]
1287   "TARGET_ALTIVEC"
1288   "vsubuhm %0,%1,%2"
1289   [(set_attr "type" "vecsimple")])
1290
1291 (define_insn "subv4si3"
1292   [(set (match_operand:V4SI 0 "register_operand" "=v")
1293         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1294                     (match_operand:V4SI 2 "register_operand" "v")))]
1295   "TARGET_ALTIVEC"
1296   "vsubuwm %0,%1,%2"
1297   [(set_attr "type" "vecsimple")])
1298
1299 (define_insn "subv4sf3"
1300   [(set (match_operand:V4SF 0 "register_operand" "=v")
1301         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1302                     (match_operand:V4SF 2 "register_operand" "v")))]
1303   "TARGET_ALTIVEC"
1304   "vsubfp %0,%1,%2"
1305   [(set_attr "type" "vecfloat")])
1306
1307 (define_insn "altivec_vsubcuw"
1308   [(set (match_operand:V4SI 0 "register_operand" "=v")
1309         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1310                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1311   "TARGET_ALTIVEC"
1312   "vsubcuw %0,%1,%2"
1313   [(set_attr "type" "vecsimple")])
1314
1315 (define_insn "altivec_vsububs"
1316   [(set (match_operand:V16QI 0 "register_operand" "=v")
1317         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1318                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1319    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1320   "TARGET_ALTIVEC"
1321   "vsububs %0,%1,%2"
1322   [(set_attr "type" "vecsimple")])
1323
1324 (define_insn "altivec_vsubsbs"
1325   [(set (match_operand:V16QI 0 "register_operand" "=v")
1326         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1327                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1328    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1329   "TARGET_ALTIVEC"
1330   "vsubsbs %0,%1,%2"
1331   [(set_attr "type" "vecsimple")])
1332
1333 (define_insn "altivec_vsubuhs"
1334   [(set (match_operand:V8HI 0 "register_operand" "=v")
1335         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1336                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1337    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1338   "TARGET_ALTIVEC"
1339   "vsubuhs %0,%1,%2"
1340   [(set_attr "type" "vecsimple")])
1341
1342 (define_insn "altivec_vsubshs"
1343   [(set (match_operand:V8HI 0 "register_operand" "=v")
1344         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1345                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1346    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1347   "TARGET_ALTIVEC"
1348   "vsubshs %0,%1,%2"
1349   [(set_attr "type" "vecsimple")])
1350
1351 (define_insn "altivec_vsubuws"
1352   [(set (match_operand:V4SI 0 "register_operand" "=v")
1353         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1354                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1355    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1356   "TARGET_ALTIVEC"
1357   "vsubuws %0,%1,%2"
1358   [(set_attr "type" "vecsimple")])
1359
1360 (define_insn "altivec_vsubsws"
1361   [(set (match_operand:V4SI 0 "register_operand" "=v")
1362         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1363                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1364    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1365   "TARGET_ALTIVEC"
1366   "vsubsws %0,%1,%2"
1367   [(set_attr "type" "vecsimple")])
1368
1369 (define_insn "altivec_vsum4ubs"
1370   [(set (match_operand:V4SI 0 "register_operand" "=v")
1371         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1372                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1373    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1374   "TARGET_ALTIVEC"
1375   "vsum4ubs %0,%1,%2"
1376   [(set_attr "type" "veccomplex")])
1377
1378 (define_insn "altivec_vsum4sbs"
1379   [(set (match_operand:V4SI 0 "register_operand" "=v")
1380         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1381                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1382    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1383   "TARGET_ALTIVEC"
1384   "vsum4sbs %0,%1,%2"
1385   [(set_attr "type" "veccomplex")])
1386
1387 (define_insn "altivec_vsum4shs"
1388   [(set (match_operand:V4SI 0 "register_operand" "=v")
1389         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1390                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1391    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1392   "TARGET_ALTIVEC"
1393   "vsum4shs %0,%1,%2"
1394   [(set_attr "type" "veccomplex")])
1395
1396 (define_insn "altivec_vsum2sws"
1397   [(set (match_operand:V4SI 0 "register_operand" "=v")
1398         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1399                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1400    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1401   "TARGET_ALTIVEC"
1402   "vsum2sws %0,%1,%2"
1403   [(set_attr "type" "veccomplex")])
1404
1405 (define_insn "altivec_vsumsws"
1406   [(set (match_operand:V4SI 0 "register_operand" "=v")
1407         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1408                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1409    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1410   "TARGET_ALTIVEC"
1411   "vsumsws %0,%1,%2"
1412   [(set_attr "type" "veccomplex")])
1413
1414 ;; Vector xor's
1415 (define_insn "xorv4si3"
1416   [(set (match_operand:V4SI 0 "register_operand" "=v")
1417         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1418                   (match_operand:V4SI 2 "register_operand" "v")))]
1419   "TARGET_ALTIVEC"
1420   "vxor %0,%1,%2"
1421   [(set_attr "type" "vecsimple")])
1422
1423 (define_insn "xorv8hi3"
1424   [(set (match_operand:V8HI 0 "register_operand" "=v")
1425         (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1426                   (match_operand:V8HI 2 "register_operand" "v")))]
1427   "TARGET_ALTIVEC"
1428   "vxor %0,%1,%2"
1429   [(set_attr "type" "vecsimple")])
1430
1431 (define_insn "xorv16qi3"
1432   [(set (match_operand:V16QI 0 "register_operand" "=v")
1433         (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1434                    (match_operand:V16QI 2 "register_operand" "v")))]
1435   "TARGET_ALTIVEC"
1436   "vxor %0,%1,%2"
1437   [(set_attr "type" "vecsimple")])
1438
1439 (define_insn "altivec_vspltb"
1440   [(set (match_operand:V16QI 0 "register_operand" "=v")
1441         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1442                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1443   "TARGET_ALTIVEC"
1444   "vspltb %0,%1,%2"
1445   [(set_attr "type" "vecperm")])
1446 ;; End of vector xor's
1447
1448 (define_insn "altivec_vsplth"
1449   [(set (match_operand:V8HI 0 "register_operand" "=v")
1450         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1451                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1452   "TARGET_ALTIVEC"
1453   "vsplth %0,%1,%2"
1454   [(set_attr "type" "vecperm")])
1455
1456 (define_insn "altivec_vspltw"
1457   [(set (match_operand:V4SI 0 "register_operand" "=v")
1458         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1459                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1460   "TARGET_ALTIVEC"
1461   "vspltw %0,%1,%2"
1462   [(set_attr "type" "vecperm")])
1463
1464 (define_insn "altivec_vspltisb"
1465   [(set (match_operand:V16QI 0 "register_operand" "=v")
1466         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1467                       UNSPEC_VSPLTISB))]
1468   "TARGET_ALTIVEC"
1469   "vspltisb %0,%1"
1470   [(set_attr "type" "vecperm")])
1471
1472 (define_insn "altivec_vspltish"
1473   [(set (match_operand:V8HI 0 "register_operand" "=v")
1474         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1475                      UNSPEC_VSPLTISH))]
1476   "TARGET_ALTIVEC"
1477   "vspltish %0,%1"
1478   [(set_attr "type" "vecperm")])
1479
1480 (define_insn "altivec_vspltisw"
1481   [(set (match_operand:V4SI 0 "register_operand" "=v")
1482         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1483                      UNSPEC_VSPLTISW))]
1484   "TARGET_ALTIVEC"
1485   "vspltisw %0,%1"
1486   [(set_attr "type" "vecperm")])
1487
1488 (define_insn "altivec_vspltisw_v4sf"
1489   [(set (match_operand:V4SF 0 "register_operand" "=v")
1490         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1491   "TARGET_ALTIVEC"
1492   "vspltisw %0,%1"
1493   [(set_attr "type" "vecperm")])
1494
1495 (define_insn "ftruncv4sf2"
1496   [(set (match_operand:V4SF 0 "register_operand" "=v")
1497         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1498   "TARGET_ALTIVEC"
1499   "vrfiz %0,%1"
1500   [(set_attr "type" "vecfloat")])
1501
1502 (define_insn "altivec_vperm_4si"
1503   [(set (match_operand:V4SI 0 "register_operand" "=v")
1504         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1505                       (match_operand:V4SI 2 "register_operand" "v")
1506                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1507   "TARGET_ALTIVEC"
1508   "vperm %0,%1,%2,%3"
1509   [(set_attr "type" "vecperm")])
1510
1511 (define_insn "altivec_vperm_4sf"
1512   [(set (match_operand:V4SF 0 "register_operand" "=v")
1513         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1514                       (match_operand:V4SF 2 "register_operand" "v")
1515                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1516   "TARGET_ALTIVEC"
1517   "vperm %0,%1,%2,%3"
1518   [(set_attr "type" "vecperm")])
1519
1520 (define_insn "altivec_vperm_8hi"
1521   [(set (match_operand:V8HI 0 "register_operand" "=v")
1522         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1523                       (match_operand:V8HI 2 "register_operand" "v")
1524                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1525   "TARGET_ALTIVEC"
1526   "vperm %0,%1,%2,%3"
1527   [(set_attr "type" "vecperm")])
1528
1529 (define_insn "altivec_vperm_16qi"
1530   [(set (match_operand:V16QI 0 "register_operand" "=v")
1531         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1532                        (match_operand:V16QI 2 "register_operand" "v")
1533                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1534   "TARGET_ALTIVEC"
1535   "vperm %0,%1,%2,%3"
1536   [(set_attr "type" "vecperm")])
1537
1538 (define_insn "altivec_vrfip"
1539   [(set (match_operand:V4SF 0 "register_operand" "=v")
1540         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1541   "TARGET_ALTIVEC"
1542   "vrfip %0,%1"
1543   [(set_attr "type" "vecfloat")])
1544
1545 (define_insn "altivec_vrfin"
1546   [(set (match_operand:V4SF 0 "register_operand" "=v")
1547         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1548   "TARGET_ALTIVEC"
1549   "vrfin %0,%1"
1550   [(set_attr "type" "vecfloat")])
1551
1552 (define_insn "altivec_vrfim"
1553   [(set (match_operand:V4SF 0 "register_operand" "=v")
1554         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1555   "TARGET_ALTIVEC"
1556   "vrfim %0,%1"
1557   [(set_attr "type" "vecfloat")])
1558
1559 (define_insn "altivec_vcfux"
1560   [(set (match_operand:V4SF 0 "register_operand" "=v")
1561         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1562                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1563   "TARGET_ALTIVEC"
1564   "vcfux %0,%1,%2"
1565   [(set_attr "type" "vecfloat")])
1566
1567 (define_insn "altivec_vcfsx"
1568   [(set (match_operand:V4SF 0 "register_operand" "=v")
1569         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1570                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1571   "TARGET_ALTIVEC"
1572   "vcfsx %0,%1,%2"
1573   [(set_attr "type" "vecfloat")])
1574
1575 (define_insn "altivec_vctuxs"
1576   [(set (match_operand:V4SI 0 "register_operand" "=v")
1577         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1578                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1579    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1580   "TARGET_ALTIVEC"
1581   "vctuxs %0,%1,%2"
1582   [(set_attr "type" "vecfloat")])
1583
1584 (define_insn "altivec_vctsxs"
1585   [(set (match_operand:V4SI 0 "register_operand" "=v")
1586         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1587                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1588    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1589   "TARGET_ALTIVEC"
1590   "vctsxs %0,%1,%2"
1591   [(set_attr "type" "vecfloat")])
1592
1593 (define_insn "altivec_vlogefp"
1594   [(set (match_operand:V4SF 0 "register_operand" "=v")
1595         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1596   "TARGET_ALTIVEC"
1597   "vlogefp %0,%1"
1598   [(set_attr "type" "vecfloat")])
1599
1600 (define_insn "altivec_vexptefp"
1601   [(set (match_operand:V4SF 0 "register_operand" "=v")
1602         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1603   "TARGET_ALTIVEC"
1604   "vexptefp %0,%1"
1605   [(set_attr "type" "vecfloat")])
1606
1607 (define_insn "altivec_vrsqrtefp"
1608   [(set (match_operand:V4SF 0 "register_operand" "=v")
1609         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1610   "TARGET_ALTIVEC"
1611   "vrsqrtefp %0,%1"
1612   [(set_attr "type" "vecfloat")])
1613
1614 (define_insn "altivec_vrefp"
1615   [(set (match_operand:V4SF 0 "register_operand" "=v")
1616         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1617   "TARGET_ALTIVEC"
1618   "vrefp %0,%1"
1619   [(set_attr "type" "vecfloat")])
1620
1621 (define_insn "altivec_vsel_4si"
1622   [(set (match_operand:V4SI 0 "register_operand" "=v")
1623         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1624                       (match_operand:V4SI 2 "register_operand" "v")
1625                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1626   "TARGET_ALTIVEC"
1627   "vsel %0,%1,%2,%3"
1628   [(set_attr "type" "vecperm")])
1629
1630 (define_insn "altivec_vsel_4sf"
1631   [(set (match_operand:V4SF 0 "register_operand" "=v")
1632         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1633                       (match_operand:V4SF 2 "register_operand" "v")
1634                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1635   "TARGET_ALTIVEC"
1636   "vsel %0,%1,%2,%3"
1637   [(set_attr "type" "vecperm")])
1638
1639 (define_insn "altivec_vsel_8hi"
1640   [(set (match_operand:V8HI 0 "register_operand" "=v")
1641         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1642                       (match_operand:V8HI 2 "register_operand" "v")
1643                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1644   "TARGET_ALTIVEC"
1645   "vsel %0,%1,%2,%3"
1646   [(set_attr "type" "vecperm")])
1647
1648 (define_insn "altivec_vsel_16qi"
1649   [(set (match_operand:V16QI 0 "register_operand" "=v")
1650         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1651                        (match_operand:V16QI 2 "register_operand" "v")
1652                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1653   "TARGET_ALTIVEC"
1654   "vsel %0,%1,%2,%3"
1655   [(set_attr "type" "vecperm")])
1656
1657 (define_insn "altivec_vsldoi_4si"
1658   [(set (match_operand:V4SI 0 "register_operand" "=v")
1659         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1660                       (match_operand:V4SI 2 "register_operand" "v")
1661                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1662   "TARGET_ALTIVEC"
1663   "vsldoi %0,%1,%2,%3"
1664   [(set_attr "type" "vecperm")])
1665
1666 (define_insn "altivec_vsldoi_4sf"
1667   [(set (match_operand:V4SF 0 "register_operand" "=v")
1668         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1669                       (match_operand:V4SF 2 "register_operand" "v")
1670                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1671   "TARGET_ALTIVEC"
1672   "vsldoi %0,%1,%2,%3"
1673   [(set_attr "type" "vecperm")])
1674
1675 (define_insn "altivec_vsldoi_8hi"
1676   [(set (match_operand:V8HI 0 "register_operand" "=v")
1677         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1678                       (match_operand:V8HI 2 "register_operand" "v")
1679                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1680   "TARGET_ALTIVEC"
1681   "vsldoi %0,%1,%2,%3"
1682   [(set_attr "type" "vecperm")])
1683
1684 (define_insn "altivec_vsldoi_16qi"
1685   [(set (match_operand:V16QI 0 "register_operand" "=v")
1686         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1687                        (match_operand:V16QI 2 "register_operand" "v")
1688                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1689   "TARGET_ALTIVEC"
1690   "vsldoi %0,%1,%2,%3"
1691   [(set_attr "type" "vecperm")])
1692
1693 (define_insn "altivec_vupkhsb"
1694   [(set (match_operand:V8HI 0 "register_operand" "=v")
1695         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1696   "TARGET_ALTIVEC"
1697   "vupkhsb %0,%1"
1698   [(set_attr "type" "vecperm")])
1699
1700 (define_insn "altivec_vupkhpx"
1701   [(set (match_operand:V4SI 0 "register_operand" "=v")
1702         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1703   "TARGET_ALTIVEC"
1704   "vupkhpx %0,%1"
1705   [(set_attr "type" "vecperm")])
1706
1707 (define_insn "altivec_vupkhsh"
1708   [(set (match_operand:V4SI 0 "register_operand" "=v")
1709         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1710   "TARGET_ALTIVEC"
1711   "vupkhsh %0,%1"
1712   [(set_attr "type" "vecperm")])
1713
1714 (define_insn "altivec_vupklsb"
1715   [(set (match_operand:V8HI 0 "register_operand" "=v")
1716         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1717   "TARGET_ALTIVEC"
1718   "vupklsb %0,%1"
1719   [(set_attr "type" "vecperm")])
1720
1721 (define_insn "altivec_vupklpx"
1722   [(set (match_operand:V4SI 0 "register_operand" "=v")
1723         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1724   "TARGET_ALTIVEC"
1725   "vupklpx %0,%1"
1726   [(set_attr "type" "vecperm")])
1727
1728 (define_insn "altivec_vupklsh"
1729   [(set (match_operand:V4SI 0 "register_operand" "=v")
1730         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1731   "TARGET_ALTIVEC"
1732   "vupklsh %0,%1"
1733   [(set_attr "type" "vecperm")])
1734
1735 ;; AltiVec predicates.
1736
1737 (define_expand "cr6_test_for_zero"
1738   [(set (match_operand:SI 0 "register_operand" "=r")
1739         (eq:SI (reg:CC 74)
1740                (const_int 0)))]
1741   "TARGET_ALTIVEC"
1742   "")
1743
1744 (define_expand "cr6_test_for_zero_reverse"
1745   [(set (match_operand:SI 0 "register_operand" "=r")
1746         (eq:SI (reg:CC 74)
1747                (const_int 0)))
1748    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1749   "TARGET_ALTIVEC"
1750   "")
1751
1752 (define_expand "cr6_test_for_lt"
1753   [(set (match_operand:SI 0 "register_operand" "=r")
1754         (lt:SI (reg:CC 74)
1755                (const_int 0)))]
1756   "TARGET_ALTIVEC"
1757   "")
1758
1759 (define_expand "cr6_test_for_lt_reverse"
1760   [(set (match_operand:SI 0 "register_operand" "=r")
1761         (lt:SI (reg:CC 74)
1762                (const_int 0)))
1763    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1764   "TARGET_ALTIVEC"
1765   "")
1766
1767 ;; We can get away with generating the opcode on the fly (%3 below)
1768 ;; because all the predicates have the same scheduling parameters.
1769
1770 (define_insn "altivec_predicate_v4si"
1771   [(set (reg:CC 74)
1772         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1773                     (match_operand:V4SI 2 "register_operand" "v")
1774                     (match_operand 3 "any_operand" "")] 173))
1775    (clobber (match_scratch:V4SI 0 "=v"))]
1776   "TARGET_ALTIVEC"
1777   "%3 %0,%1,%2"
1778 [(set_attr "type" "veccmp")])
1779
1780 (define_insn "altivec_predicate_v4sf"
1781   [(set (reg:CC 74)
1782         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1783                     (match_operand:V4SF 2 "register_operand" "v")
1784                     (match_operand 3 "any_operand" "")] 174))
1785    (clobber (match_scratch:V4SF 0 "=v"))]
1786   "TARGET_ALTIVEC"
1787   "%3 %0,%1,%2"
1788 [(set_attr "type" "veccmp")])
1789
1790 (define_insn "altivec_predicate_v8hi"
1791   [(set (reg:CC 74)
1792         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1793                     (match_operand:V8HI 2 "register_operand" "v")
1794                     (match_operand 3 "any_operand" "")] 175))
1795    (clobber (match_scratch:V8HI 0 "=v"))]
1796   "TARGET_ALTIVEC"
1797   "%3 %0,%1,%2"
1798 [(set_attr "type" "veccmp")])
1799
1800 (define_insn "altivec_predicate_v16qi"
1801   [(set (reg:CC 74)
1802         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1803                     (match_operand:V16QI 2 "register_operand" "v")
1804                     (match_operand 3 "any_operand" "")] 175))
1805    (clobber (match_scratch:V16QI 0 "=v"))]
1806   "TARGET_ALTIVEC"
1807   "%3 %0,%1,%2"
1808 [(set_attr "type" "veccmp")])
1809
1810 (define_insn "altivec_mtvscr"
1811   [(set (reg:SI 110)
1812         (unspec_volatile:SI
1813          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1814   "TARGET_ALTIVEC"
1815   "mtvscr %0"
1816   [(set_attr "type" "vecsimple")])
1817
1818 (define_insn "altivec_mfvscr"
1819   [(set (match_operand:V8HI 0 "register_operand" "=v")
1820         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1821   "TARGET_ALTIVEC"
1822   "mfvscr %0"
1823   [(set_attr "type" "vecsimple")])
1824
1825 (define_insn "altivec_dssall"
1826   [(unspec [(const_int 0)] 188)]
1827   "TARGET_ALTIVEC"
1828   "dssall"
1829   [(set_attr "type" "vecsimple")])
1830
1831 (define_insn "altivec_dss"
1832   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1833   "TARGET_ALTIVEC"
1834   "dss %0"
1835   [(set_attr "type" "vecsimple")])
1836
1837 (define_insn "altivec_dst"
1838   [(unspec [(match_operand:SI 0 "register_operand" "b")
1839             (match_operand:SI 1 "register_operand" "r")
1840             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1841   "TARGET_ALTIVEC"
1842   "dst %0,%1,%2"
1843   [(set_attr "type" "vecsimple")])
1844
1845 (define_insn "altivec_dstt"
1846   [(unspec [(match_operand:SI 0 "register_operand" "b")
1847             (match_operand:SI 1 "register_operand" "r")
1848             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1849   "TARGET_ALTIVEC"
1850   "dstt %0,%1,%2"
1851   [(set_attr "type" "vecsimple")])
1852
1853 (define_insn "altivec_dstst"
1854   [(unspec [(match_operand:SI 0 "register_operand" "b")
1855             (match_operand:SI 1 "register_operand" "r")
1856             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1857   "TARGET_ALTIVEC"
1858   "dstst %0,%1,%2"
1859   [(set_attr "type" "vecsimple")])
1860
1861 (define_insn "altivec_dststt"
1862   [(unspec [(match_operand:SI 0 "register_operand" "b")
1863             (match_operand:SI 1 "register_operand" "r")
1864             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1865   "TARGET_ALTIVEC"
1866   "dststt %0,%1,%2"
1867   [(set_attr "type" "vecsimple")])
1868
1869 (define_insn "altivec_lvsl"
1870   [(set (match_operand:V16QI 0 "register_operand" "=v")
1871         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1872                        (match_operand:SI 2 "register_operand" "r")] 194))]
1873   "TARGET_ALTIVEC"
1874   "lvsl %0,%1,%2"
1875   [(set_attr "type" "vecload")])
1876
1877 (define_insn "altivec_lvsr"
1878   [(set (match_operand:V16QI 0 "register_operand" "=v")
1879         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1880                        (match_operand:SI 2 "register_operand" "r")] 195))]
1881   "TARGET_ALTIVEC"
1882   "lvsr %0,%1,%2"
1883   [(set_attr "type" "vecload")])
1884
1885 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1886 ;; identical rtl but different instructions-- and gcc gets confused.
1887
1888 (define_insn "altivec_lvebx"
1889   [(parallel
1890     [(set (match_operand:V16QI 0 "register_operand" "=v")
1891           (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b")
1892                               (match_operand:SI 2 "register_operand" "r"))))
1893      (unspec [(const_int 0)] 196)])]
1894   "TARGET_ALTIVEC"
1895   "lvebx %0,%1,%2"
1896   [(set_attr "type" "vecload")])
1897
1898 (define_insn "altivec_lvehx"
1899   [(parallel
1900     [(set (match_operand:V8HI 0 "register_operand" "=v")
1901           (mem:V8HI
1902            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1903                             (match_operand:SI 2 "register_operand" "r"))
1904                    (const_int -2))))
1905      (unspec [(const_int 0)] 197)])]
1906   "TARGET_ALTIVEC"
1907   "lvehx %0,%1,%2"
1908   [(set_attr "type" "vecload")])
1909
1910 (define_insn "altivec_lvewx"
1911   [(parallel
1912     [(set (match_operand:V4SI 0 "register_operand" "=v")
1913           (mem:V4SI
1914            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1915                             (match_operand:SI 2 "register_operand" "r"))
1916                    (const_int -4))))
1917      (unspec [(const_int 0)] 198)])]
1918   "TARGET_ALTIVEC"
1919   "lvewx %0,%1,%2"
1920   [(set_attr "type" "vecload")])
1921
1922 (define_insn "altivec_lvxl"
1923   [(parallel
1924     [(set (match_operand:V4SI 0 "register_operand" "=v")
1925           (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1926                              (match_operand:SI 2 "register_operand" "r"))))
1927      (unspec [(const_int 0)] 213)])]
1928   "TARGET_ALTIVEC"
1929   "lvxl %0,%1,%2"
1930   [(set_attr "type" "vecload")])
1931
1932 (define_insn "altivec_lvx"
1933   [(set (match_operand:V4SI 0 "register_operand" "=v")
1934         (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1935                            (match_operand:SI 2 "register_operand" "r"))))]
1936   "TARGET_ALTIVEC"
1937   "lvx %0,%1,%2"
1938   [(set_attr "type" "vecload")])
1939
1940 (define_insn "altivec_stvx"
1941   [(parallel
1942     [(set (mem:V4SI
1943            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1944                             (match_operand:SI 1 "register_operand" "r"))
1945                    (const_int -16)))
1946           (match_operand:V4SI 2 "register_operand" "v"))
1947      (unspec [(const_int 0)] 201)])]
1948   "TARGET_ALTIVEC"
1949   "stvx %2,%0,%1"
1950   [(set_attr "type" "vecstore")])
1951
1952 (define_insn "altivec_stvxl"
1953   [(parallel
1954     [(set (mem:V4SI
1955            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1956                             (match_operand:SI 1 "register_operand" "r"))
1957                    (const_int -16)))
1958           (match_operand:V4SI 2 "register_operand" "v"))
1959      (unspec [(const_int 0)] 202)])]
1960   "TARGET_ALTIVEC"
1961   "stvxl %2,%0,%1"
1962   [(set_attr "type" "vecstore")])
1963
1964 (define_insn "altivec_stvebx"
1965   [(parallel
1966     [(set (mem:V16QI
1967            (plus:SI (match_operand:SI 0 "register_operand" "b")
1968                     (match_operand:SI 1 "register_operand" "r")))
1969           (match_operand:V16QI 2 "register_operand" "v"))
1970      (unspec [(const_int 0)] 203)])]
1971   "TARGET_ALTIVEC"
1972   "stvebx %2,%0,%1"
1973   [(set_attr "type" "vecstore")])
1974
1975 (define_insn "altivec_stvehx"
1976   [(parallel
1977     [(set (mem:V8HI
1978            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1979                             (match_operand:SI 1 "register_operand" "r"))
1980                    (const_int -2)))
1981           (match_operand:V8HI 2 "register_operand" "v"))
1982      (unspec [(const_int 0)] 204)])]
1983   "TARGET_ALTIVEC"
1984   "stvehx %2,%0,%1"
1985   [(set_attr "type" "vecstore")])
1986
1987 (define_insn "altivec_stvewx"
1988   [(parallel
1989     [(set (mem:V4SI
1990            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1991                             (match_operand:SI 1 "register_operand" "r"))
1992                    (const_int -4)))
1993           (match_operand:V4SI 2 "register_operand" "v"))
1994      (unspec [(const_int 0)] 205)])]
1995   "TARGET_ALTIVEC"
1996   "stvewx %2,%0,%1"
1997   [(set_attr "type" "vecstore")])
1998
1999 (define_insn "absv16qi2"
2000   [(set (match_operand:V16QI 0 "register_operand" "=v")
2001         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
2002    (clobber (match_scratch:V16QI 2 "=&v"))
2003    (clobber (match_scratch:V16QI 3 "=&v"))]
2004   "TARGET_ALTIVEC"
2005   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
2006   [(set_attr "type" "vecsimple")
2007    (set_attr "length" "12")])
2008
2009 (define_insn "absv8hi2"
2010   [(set (match_operand:V8HI 0 "register_operand" "=v")
2011         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
2012    (clobber (match_scratch:V8HI 2 "=&v"))
2013    (clobber (match_scratch:V8HI 3 "=&v"))]
2014   "TARGET_ALTIVEC"
2015   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
2016   [(set_attr "type" "vecsimple")
2017    (set_attr "length" "12")])
2018
2019 (define_insn "absv4si2"
2020   [(set (match_operand:V4SI 0 "register_operand" "=v")
2021         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
2022    (clobber (match_scratch:V4SI 2 "=&v"))
2023    (clobber (match_scratch:V4SI 3 "=&v"))]
2024   "TARGET_ALTIVEC"
2025   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
2026   [(set_attr "type" "vecsimple")
2027    (set_attr "length" "12")])
2028
2029 (define_insn "absv4sf2"
2030   [(set (match_operand:V4SF 0 "register_operand" "=v")
2031         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
2032    (clobber (match_scratch:V4SF 2 "=&v"))
2033    (clobber (match_scratch:V4SF 3 "=&v"))]
2034   "TARGET_ALTIVEC"
2035   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
2036   [(set_attr "type" "vecsimple")
2037    (set_attr "length" "12")])
2038
2039 (define_insn "altivec_abss_v16qi"
2040   [(set (match_operand:V16QI 0 "register_operand" "=v")
2041         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
2042    (clobber (match_scratch:V16QI 2 "=&v"))
2043    (clobber (match_scratch:V16QI 3 "=&v"))]
2044   "TARGET_ALTIVEC"
2045   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
2046   [(set_attr "type" "vecsimple")
2047    (set_attr "length" "12")])
2048
2049 (define_insn "altivec_abss_v8hi"
2050   [(set (match_operand:V8HI 0 "register_operand" "=v")
2051         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
2052    (clobber (match_scratch:V8HI 2 "=&v"))
2053    (clobber (match_scratch:V8HI 3 "=&v"))]
2054   "TARGET_ALTIVEC"
2055   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
2056   [(set_attr "type" "vecsimple")
2057    (set_attr "length" "12")])
2058
2059 (define_insn "altivec_abss_v4si"
2060   [(set (match_operand:V4SI 0 "register_operand" "=v")
2061         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
2062    (clobber (match_scratch:V4SI 2 "=&v"))
2063    (clobber (match_scratch:V4SI 3 "=&v"))]
2064   "TARGET_ALTIVEC"
2065   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
2066   [(set_attr "type" "vecsimple")
2067    (set_attr "length" "12")])