gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VSPLTISW     141)
  24    (UNSPEC_VSPLTISH     140)
  25    (UNSPEC_VSPLTISB     139)
  26    ])
  27
  28 ;; Generic LVX load instruction.
  29 (define_insn "altivec_lvx_4si"
  30   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  31         (match_operand:V4SI 1 "memory_operand" "m"))]
  32   "TARGET_ALTIVEC"
  33   "lvx %0,%y1"
  34   [(set_attr "type" "vecload")])
  35
  36 (define_insn "altivec_lvx_8hi"
  37   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  38         (match_operand:V8HI 1 "memory_operand" "m"))]
  39   "TARGET_ALTIVEC"
  40   "lvx %0,%y1"
  41   [(set_attr "type" "vecload")])
  42
  43 (define_insn "altivec_lvx_16qi"
  44   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  45         (match_operand:V16QI 1 "memory_operand" "m"))]
  46   "TARGET_ALTIVEC"
  47   "lvx %0,%y1"
  48   [(set_attr "type" "vecload")])
  49
  50 (define_insn "altivec_lvx_4sf"
  51   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  52         (match_operand:V4SF 1 "memory_operand" "m"))]
  53   "TARGET_ALTIVEC"
  54   "lvx %0,%y1"
  55   [(set_attr "type" "vecload")])
  56
  57 ;; Generic STVX store instruction.
  58 (define_insn "altivec_stvx_4si"
  59   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  60         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  61   "TARGET_ALTIVEC"
  62   "stvx %1,%y0"
  63   [(set_attr "type" "vecstore")])
  64
  65 (define_insn "altivec_stvx_8hi"
  66   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  67         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  68   "TARGET_ALTIVEC"
  69   "stvx %1,%y0"
  70   [(set_attr "type" "vecstore")])
  71
  72 (define_insn "altivec_stvx_16qi"
  73   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  74         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 (define_insn "altivec_stvx_4sf"
  80   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  81         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  82   "TARGET_ALTIVEC"
  83   "stvx %1,%y0"
  84   [(set_attr "type" "vecstore")])
  85
  86 ;; Vector move instructions.
  87 (define_expand "movv4si"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  89         (match_operand:V4SI 1 "any_operand" ""))]
  90   "TARGET_ALTIVEC"
  91   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  92
  93 (define_insn "*movv4si_internal"
  94   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  95         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
  96   "TARGET_ALTIVEC
  97    && (altivec_register_operand (operands[0], V4SImode)
  98        || altivec_register_operand (operands[1], V4SImode))"
  99   "*
 100 {
 101   switch (which_alternative)
 102     {
 103     case 0: return \"stvx %1,%y0\";
 104     case 1: return \"lvx %0,%y1\";
 105     case 2: return \"vor %0,%1,%1\";
 106     case 3: return \"#\";
 107     case 4: return \"#\";
 108     case 5: return \"#\";
 109     case 6: return output_vec_const_move (operands);
 110     default: abort();
 111     }
 112 }"
 113   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 114
 115 (define_split
 116   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 117         (match_operand:V4SI 1 "input_operand" ""))]
 118   "TARGET_ALTIVEC && reload_completed
 119    && gpr_or_gpr_p (operands[0], operands[1])"
 120   [(pc)]
 121 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 122
 123 (define_split
 124   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 125         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 126   "TARGET_ALTIVEC && reload_completed"
 127   [(set (match_dup 0)
 128         (unspec:V4SI [(match_dup 3)] UNSPEC_VSPLTISW))
 129    (set (match_dup 0)
 130         (plus:V4SI (match_dup 0)
 131                    (match_dup 0)))]
 132   "
 133 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 134
 135 (define_expand "movv8hi"
 136   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 137         (match_operand:V8HI 1 "any_operand" ""))]
 138   "TARGET_ALTIVEC"
 139   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 140
 141 (define_insn "*movv8hi_internal1"
 142   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 143         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
 144   "TARGET_ALTIVEC
 145    && (altivec_register_operand (operands[0], V8HImode)
 146        || altivec_register_operand (operands[1], V8HImode))"
 147   "*
 148 {
 149    switch (which_alternative)
 150      {
 151      case 0: return \"stvx %1,%y0\";
 152      case 1: return \"lvx %0,%y1\";
 153      case 2: return \"vor %0,%1,%1\";
 154      case 3: return \"#\";
 155      case 4: return \"#\";
 156      case 5: return \"#\";
 157      case 6: return output_vec_const_move (operands);
 158      default: abort ();
 159      }
 160 }"
 161   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 162
 163 (define_split
 164   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 165         (match_operand:V8HI 1 "input_operand" ""))]
 166   "TARGET_ALTIVEC && reload_completed
 167    && gpr_or_gpr_p (operands[0], operands[1])"
 168   [(pc)]
 169 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 170
 171 (define_split
 172   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 173         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 174   "TARGET_ALTIVEC && reload_completed"
 175   [(set (match_dup 0)
 176         (unspec:V8HI [(match_dup 3)] UNSPEC_VSPLTISH))
 177    (set (match_dup 0)
 178         (plus:V8HI (match_dup 0)
 179                    (match_dup 0)))]
 180   "
 181 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 182
 183 (define_expand "movv16qi"
 184   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 185         (match_operand:V16QI 1 "any_operand" ""))]
 186   "TARGET_ALTIVEC"
 187   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 188
 189 (define_insn "*movv16qi_internal1"
 190   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 191         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
 192   "TARGET_ALTIVEC
 193    && (altivec_register_operand (operands[0], V16QImode)
 194        || altivec_register_operand (operands[1], V16QImode))"
 195   "*
 196 {
 197   switch (which_alternative)
 198     {
 199     case 0: return \"stvx %1,%y0\";
 200     case 1: return \"lvx %0,%y1\";
 201     case 2: return \"vor %0,%1,%1\";
 202     case 3: return \"#\";
 203     case 4: return \"#\";
 204     case 5: return \"#\";
 205     case 6: return output_vec_const_move (operands);
 206     default: abort ();
 207     }
 208 }"
 209   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 210
 211 (define_split
 212   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 213         (match_operand:V16QI 1 "input_operand" ""))]
 214   "TARGET_ALTIVEC && reload_completed
 215    && gpr_or_gpr_p (operands[0], operands[1])"
 216   [(pc)]
 217 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 218
 219 (define_split
 220   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 221         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 222   "TARGET_ALTIVEC && reload_completed"
 223   [(set (match_dup 0)
 224         (unspec:V16QI [(match_dup 3)] UNSPEC_VSPLTISB))
 225    (set (match_dup 0)
 226         (plus:V16QI (match_dup 0)
 227                    (match_dup 0)))]
 228   "
 229 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
 230
 231 (define_expand "movv4sf"
 232   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 233         (match_operand:V4SF 1 "any_operand" ""))]
 234   "TARGET_ALTIVEC"
 235   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 236
 237 (define_insn "*movv4sf_internal1"
 238   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 239         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
 240   "TARGET_ALTIVEC
 241    && (altivec_register_operand (operands[0], V4SFmode)
 242        || altivec_register_operand (operands[1], V4SFmode))"
 243   "*
 244 {
 245   switch (which_alternative)
 246     {
 247     case 0: return \"stvx %1,%y0\";
 248     case 1: return \"lvx %0,%y1\";
 249     case 2: return \"vor %0,%1,%1\";
 250     case 3: return \"#\";
 251     case 4: return \"#\";
 252     case 5: return \"#\";
 253     case 6: return output_vec_const_move (operands);
 254     default: abort ();
 255     }
 256 }"
 257   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 258
 259 (define_split
 260   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 261         (match_operand:V4SF 1 "input_operand" ""))]
 262   "TARGET_ALTIVEC && reload_completed
 263    && gpr_or_gpr_p (operands[0], operands[1])"
 264   [(pc)]
 265 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 266
 267 (define_insn "get_vrsave_internal"
 268   [(set (match_operand:SI 0 "register_operand" "=r")
 269         (unspec:SI [(reg:SI 109)] 214))]
 270   "TARGET_ALTIVEC"
 271   "*
 272 {
 273   if (TARGET_MACHO)
 274      return \"mfspr %0,256\";
 275   else
 276      return \"mfvrsave %0\";
 277 }"
 278   [(set_attr "type" "*")])
 279
 280 (define_insn "*set_vrsave_internal"
 281   [(match_parallel 0 "vrsave_operation"
 282      [(set (reg:SI 109)
 283            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 284                                 (reg:SI 109)] 30))])]
 285   "TARGET_ALTIVEC"
 286   "*
 287 {
 288   if (TARGET_MACHO)
 289     return \"mtspr 256,%1\";
 290   else
 291     return \"mtvrsave %1\";
 292 }"
 293   [(set_attr "type" "*")])
 294
 295 ;; Simple binary operations.
 296
 297 (define_insn "addv16qi3"
 298   [(set (match_operand:V16QI 0 "register_operand" "=v")
 299         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 300                     (match_operand:V16QI 2 "register_operand" "v")))]
 301   "TARGET_ALTIVEC"
 302   "vaddubm %0,%1,%2"
 303   [(set_attr "type" "vecsimple")])
 304
 305 (define_insn "addv8hi3"
 306   [(set (match_operand:V8HI 0 "register_operand" "=v")
 307         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 308                    (match_operand:V8HI 2 "register_operand" "v")))]
 309   "TARGET_ALTIVEC"
 310   "vadduhm %0,%1,%2"
 311   [(set_attr "type" "vecsimple")])
 312
 313 (define_insn "addv4si3"
 314   [(set (match_operand:V4SI 0 "register_operand" "=v")
 315         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 316                    (match_operand:V4SI 2 "register_operand" "v")))]
 317   "TARGET_ALTIVEC"
 318   "vadduwm %0,%1,%2"
 319   [(set_attr "type" "vecsimple")])
 320
 321 (define_insn "addv4sf3"
 322   [(set (match_operand:V4SF 0 "register_operand" "=v")
 323         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 324                    (match_operand:V4SF 2 "register_operand" "v")))]
 325   "TARGET_ALTIVEC"
 326   "vaddfp %0,%1,%2"
 327   [(set_attr "type" "vecfloat")])
 328
 329 (define_insn "altivec_vaddcuw"
 330   [(set (match_operand:V4SI 0 "register_operand" "=v")
 331         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 332                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 333   "TARGET_ALTIVEC"
 334   "vaddcuw %0,%1,%2"
 335   [(set_attr "type" "vecsimple")])
 336
 337 (define_insn "altivec_vaddubs"
 338   [(set (match_operand:V16QI 0 "register_operand" "=v")
 339         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 340                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 341    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 342   "TARGET_ALTIVEC"
 343   "vaddubs %0,%1,%2"
 344   [(set_attr "type" "vecsimple")])
 345
 346 (define_insn "altivec_vaddsbs"
 347   [(set (match_operand:V16QI 0 "register_operand" "=v")
 348         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 349                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 350    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 351   "TARGET_ALTIVEC"
 352   "vaddsbs %0,%1,%2"
 353   [(set_attr "type" "vecsimple")])
 354
 355 (define_insn "altivec_vadduhs"
 356   [(set (match_operand:V8HI 0 "register_operand" "=v")
 357         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 358                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 359    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 360   "TARGET_ALTIVEC"
 361   "vadduhs %0,%1,%2"
 362   [(set_attr "type" "vecsimple")])
 363
 364 (define_insn "altivec_vaddshs"
 365   [(set (match_operand:V8HI 0 "register_operand" "=v")
 366         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 367                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 368    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 369   "TARGET_ALTIVEC"
 370   "vaddshs %0,%1,%2"
 371   [(set_attr "type" "vecsimple")])
 372
 373 (define_insn "altivec_vadduws"
 374   [(set (match_operand:V4SI 0 "register_operand" "=v")
 375         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 376                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 377    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 378   "TARGET_ALTIVEC"
 379   "vadduws %0,%1,%2"
 380   [(set_attr "type" "vecsimple")])
 381
 382 (define_insn "altivec_vaddsws"
 383   [(set (match_operand:V4SI 0 "register_operand" "=v")
 384         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 385                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 386    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 387   "TARGET_ALTIVEC"
 388   "vaddsws %0,%1,%2"
 389   [(set_attr "type" "vecsimple")])
 390
 391 (define_insn "andv4si3"
 392   [(set (match_operand:V4SI 0 "register_operand" "=v")
 393         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 394                   (match_operand:V4SI 2 "register_operand" "v")))]
 395   "TARGET_ALTIVEC"
 396   "vand %0,%1,%2"
 397   [(set_attr "type" "vecsimple")])
 398
 399 (define_insn "altivec_vandc"
 400   [(set (match_operand:V4SI 0 "register_operand" "=v")
 401         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 402                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 403   "TARGET_ALTIVEC"
 404   "vandc %0,%1,%2"
 405   [(set_attr "type" "vecsimple")])
 406
 407 (define_insn "altivec_vavgub"
 408   [(set (match_operand:V16QI 0 "register_operand" "=v")
 409         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 410                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 411   "TARGET_ALTIVEC"
 412   "vavgub %0,%1,%2"
 413   [(set_attr "type" "vecsimple")])
 414
 415 (define_insn "altivec_vavgsb"
 416   [(set (match_operand:V16QI 0 "register_operand" "=v")
 417         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 418                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 419   "TARGET_ALTIVEC"
 420   "vavgsb %0,%1,%2"
 421   [(set_attr "type" "vecsimple")])
 422
 423 (define_insn "altivec_vavguh"
 424   [(set (match_operand:V8HI 0 "register_operand" "=v")
 425         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 426                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 427   "TARGET_ALTIVEC"
 428   "vavguh %0,%1,%2"
 429   [(set_attr "type" "vecsimple")])
 430
 431 (define_insn "altivec_vavgsh"
 432   [(set (match_operand:V8HI 0 "register_operand" "=v")
 433         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 434                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 435   "TARGET_ALTIVEC"
 436   "vavgsh %0,%1,%2"
 437   [(set_attr "type" "vecsimple")])
 438
 439 (define_insn "altivec_vavguw"
 440   [(set (match_operand:V4SI 0 "register_operand" "=v")
 441         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 442                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 443   "TARGET_ALTIVEC"
 444   "vavguw %0,%1,%2"
 445   [(set_attr "type" "vecsimple")])
 446
 447 (define_insn "altivec_vavgsw"
 448   [(set (match_operand:V4SI 0 "register_operand" "=v")
 449         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 450                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 451   "TARGET_ALTIVEC"
 452   "vavgsw %0,%1,%2"
 453   [(set_attr "type" "vecsimple")])
 454
 455 (define_insn "altivec_vcmpbfp"
 456   [(set (match_operand:V4SI 0 "register_operand" "=v")
 457         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 458                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 459   "TARGET_ALTIVEC"
 460   "vcmpbfp %0,%1,%2"
 461   [(set_attr "type" "veccmp")])
 462
 463 (define_insn "altivec_vcmpequb"
 464   [(set (match_operand:V16QI 0 "register_operand" "=v")
 465         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 466                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 467   "TARGET_ALTIVEC"
 468   "vcmpequb %0,%1,%2"
 469   [(set_attr "type" "vecsimple")])
 470
 471 (define_insn "altivec_vcmpequh"
 472   [(set (match_operand:V8HI 0 "register_operand" "=v")
 473         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 474                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 475   "TARGET_ALTIVEC"
 476   "vcmpequh %0,%1,%2"
 477   [(set_attr "type" "vecsimple")])
 478
 479 (define_insn "altivec_vcmpequw"
 480   [(set (match_operand:V4SI 0 "register_operand" "=v")
 481         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 482                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 483   "TARGET_ALTIVEC"
 484   "vcmpequw %0,%1,%2"
 485   [(set_attr "type" "vecsimple")])
 486
 487 (define_insn "altivec_vcmpeqfp"
 488   [(set (match_operand:V4SI 0 "register_operand" "=v")
 489         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 490                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 491   "TARGET_ALTIVEC"
 492   "vcmpeqfp %0,%1,%2"
 493   [(set_attr "type" "veccmp")])
 494
 495 (define_insn "altivec_vcmpgefp"
 496   [(set (match_operand:V4SI 0 "register_operand" "=v")
 497         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 498                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 499   "TARGET_ALTIVEC"
 500   "vcmpgefp %0,%1,%2"
 501   [(set_attr "type" "veccmp")])
 502
 503 (define_insn "altivec_vcmpgtub"
 504   [(set (match_operand:V16QI 0 "register_operand" "=v")
 505         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 506                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 507   "TARGET_ALTIVEC"
 508   "vcmpgtub %0,%1,%2"
 509   [(set_attr "type" "vecsimple")])
 510
 511 (define_insn "altivec_vcmpgtsb"
 512   [(set (match_operand:V16QI 0 "register_operand" "=v")
 513         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 514                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 515   "TARGET_ALTIVEC"
 516   "vcmpgtsb %0,%1,%2"
 517   [(set_attr "type" "vecsimple")])
 518
 519 (define_insn "altivec_vcmpgtuh"
 520   [(set (match_operand:V8HI 0 "register_operand" "=v")
 521         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 522                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 523   "TARGET_ALTIVEC"
 524   "vcmpgtuh %0,%1,%2"
 525   [(set_attr "type" "vecsimple")])
 526
 527 (define_insn "altivec_vcmpgtsh"
 528   [(set (match_operand:V8HI 0 "register_operand" "=v")
 529         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 530                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 531   "TARGET_ALTIVEC"
 532   "vcmpgtsh %0,%1,%2"
 533   [(set_attr "type" "vecsimple")])
 534
 535 (define_insn "altivec_vcmpgtuw"
 536   [(set (match_operand:V4SI 0 "register_operand" "=v")
 537         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 538                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 539   "TARGET_ALTIVEC"
 540   "vcmpgtuw %0,%1,%2"
 541   [(set_attr "type" "vecsimple")])
 542
 543 (define_insn "altivec_vcmpgtsw"
 544   [(set (match_operand:V4SI 0 "register_operand" "=v")
 545         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 546                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 547   "TARGET_ALTIVEC"
 548   "vcmpgtsw %0,%1,%2"
 549   [(set_attr "type" "vecsimple")])
 550
 551 (define_insn "altivec_vcmpgtfp"
 552   [(set (match_operand:V4SI 0 "register_operand" "=v")
 553         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 554                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 555   "TARGET_ALTIVEC"
 556   "vcmpgtfp %0,%1,%2"
 557   [(set_attr "type" "veccmp")])
 558
 559 ;; Fused multiply add
 560 (define_insn "altivec_vmaddfp"
 561   [(set (match_operand:V4SF 0 "register_operand" "=v")
 562         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 563                               (match_operand:V4SF 2 "register_operand" "v"))
 564                    (match_operand:V4SF 3 "register_operand" "v")))]
 565   "TARGET_ALTIVEC"
 566   "vmaddfp %0,%1,%2,%3"
 567   [(set_attr "type" "vecfloat")])
 568
 569 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 570
 571 (define_expand "mulv4sf3"
 572   [(use (match_operand:V4SF 0 "register_operand" ""))
 573    (use (match_operand:V4SF 1 "register_operand" ""))
 574    (use (match_operand:V4SF 2 "register_operand" ""))]
 575   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 576   "
 577 {
 578   rtx neg0;
 579
 580   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 581   neg0 = gen_reg_rtx (V4SFmode);
 582   emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
 583   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 584
 585   /* Use the multiply-add.  */
 586   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 587                                   neg0));
 588   DONE;
 589 }")
 590
 591 ;; Fused multiply subtract
 592 (define_insn "altivec_vnmsubfp"
 593   [(set (match_operand:V4SF 0 "register_operand" "=v")
 594         (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 595                                (match_operand:V4SF 2 "register_operand" "v"))
 596                     (match_operand:V4SF 3 "register_operand" "v")))]
 597   "TARGET_ALTIVEC"
 598   "vnmsubfp %0,%1,%2,%3"
 599   [(set_attr "type" "vecfloat")])
 600
 601
 602 (define_insn "altivec_vmsumubm"
 603   [(set (match_operand:V4SI 0 "register_operand" "=v")
 604         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 605                       (match_operand:V16QI 2 "register_operand" "v")
 606                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 607   "TARGET_ALTIVEC"
 608   "vmsumubm %0,%1,%2,%3"
 609   [(set_attr "type" "veccomplex")])
 610
 611 (define_insn "altivec_vmsummbm"
 612   [(set (match_operand:V4SI 0 "register_operand" "=v")
 613         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 614                       (match_operand:V16QI 2 "register_operand" "v")
 615                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 616   "TARGET_ALTIVEC"
 617   "vmsummbm %0,%1,%2,%3"
 618   [(set_attr "type" "veccomplex")])
 619
 620 (define_insn "altivec_vmsumuhm"
 621   [(set (match_operand:V4SI 0 "register_operand" "=v")
 622         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 623                       (match_operand:V8HI 2 "register_operand" "v")
 624                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 625   "TARGET_ALTIVEC"
 626   "vmsumuhm %0,%1,%2,%3"
 627   [(set_attr "type" "veccomplex")])
 628
 629 (define_insn "altivec_vmsumshm"
 630   [(set (match_operand:V4SI 0 "register_operand" "=v")
 631         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 632                       (match_operand:V8HI 2 "register_operand" "v")
 633                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 634   "TARGET_ALTIVEC"
 635   "vmsumshm %0,%1,%2,%3"
 636   [(set_attr "type" "veccomplex")])
 637
 638 (define_insn "altivec_vmsumuhs"
 639   [(set (match_operand:V4SI 0 "register_operand" "=v")
 640         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 641                       (match_operand:V8HI 2 "register_operand" "v")
 642                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 643    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 644   "TARGET_ALTIVEC"
 645   "vmsumuhs %0,%1,%2,%3"
 646   [(set_attr "type" "veccomplex")])
 647
 648 (define_insn "altivec_vmsumshs"
 649   [(set (match_operand:V4SI 0 "register_operand" "=v")
 650         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 651                       (match_operand:V8HI 2 "register_operand" "v")
 652                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 653    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 654   "TARGET_ALTIVEC"
 655   "vmsumshs %0,%1,%2,%3"
 656   [(set_attr "type" "veccomplex")])
 657
 658 (define_insn "umaxv16qi3"
 659   [(set (match_operand:V16QI 0 "register_operand" "=v")
 660         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 661                     (match_operand:V16QI 2 "register_operand" "v")))]
 662   "TARGET_ALTIVEC"
 663   "vmaxub %0,%1,%2"
 664   [(set_attr "type" "vecsimple")])
 665
 666 (define_insn "smaxv16qi3"
 667   [(set (match_operand:V16QI 0 "register_operand" "=v")
 668         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 669                     (match_operand:V16QI 2 "register_operand" "v")))]
 670   "TARGET_ALTIVEC"
 671   "vmaxsb %0,%1,%2"
 672   [(set_attr "type" "vecsimple")])
 673
 674 (define_insn "umaxv8hi3"
 675   [(set (match_operand:V8HI 0 "register_operand" "=v")
 676         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 677                    (match_operand:V8HI 2 "register_operand" "v")))]
 678   "TARGET_ALTIVEC"
 679   "vmaxuh %0,%1,%2"
 680   [(set_attr "type" "vecsimple")])
 681
 682 (define_insn "smaxv8hi3"
 683   [(set (match_operand:V8HI 0 "register_operand" "=v")
 684         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 685                    (match_operand:V8HI 2 "register_operand" "v")))]
 686   "TARGET_ALTIVEC"
 687   "vmaxsh %0,%1,%2"
 688   [(set_attr "type" "vecsimple")])
 689
 690 (define_insn "umaxv4si3"
 691   [(set (match_operand:V4SI 0 "register_operand" "=v")
 692         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 693                    (match_operand:V4SI 2 "register_operand" "v")))]
 694   "TARGET_ALTIVEC"
 695   "vmaxuw %0,%1,%2"
 696   [(set_attr "type" "vecsimple")])
 697
 698 (define_insn "smaxv4si3"
 699   [(set (match_operand:V4SI 0 "register_operand" "=v")
 700         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 701                    (match_operand:V4SI 2 "register_operand" "v")))]
 702   "TARGET_ALTIVEC"
 703   "vmaxsw %0,%1,%2"
 704   [(set_attr "type" "vecsimple")])
 705
 706 (define_insn "smaxv4sf3"
 707   [(set (match_operand:V4SF 0 "register_operand" "=v")
 708         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 709                    (match_operand:V4SF 2 "register_operand" "v")))]
 710   "TARGET_ALTIVEC"
 711   "vmaxfp %0,%1,%2"
 712   [(set_attr "type" "veccmp")])
 713
 714 (define_insn "altivec_vmhaddshs"
 715   [(set (match_operand:V8HI 0 "register_operand" "=v")
 716         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 717                       (match_operand:V8HI 2 "register_operand" "v")
 718                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 719    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 720   "TARGET_ALTIVEC"
 721   "vmhaddshs %0,%1,%2,%3"
 722   [(set_attr "type" "veccomplex")])
 723 (define_insn "altivec_vmhraddshs"
 724   [(set (match_operand:V8HI 0 "register_operand" "=v")
 725         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 726                       (match_operand:V8HI 2 "register_operand" "v")
 727                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 728    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 729   "TARGET_ALTIVEC"
 730   "vmhraddshs %0,%1,%2,%3"
 731   [(set_attr "type" "veccomplex")])
 732 (define_insn "altivec_vmladduhm"
 733   [(set (match_operand:V8HI 0 "register_operand" "=v")
 734         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 735                       (match_operand:V8HI 2 "register_operand" "v")
 736                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 737   "TARGET_ALTIVEC"
 738   "vmladduhm %0,%1,%2,%3"
 739   [(set_attr "type" "veccomplex")])
 740
 741 (define_insn "altivec_vmrghb"
 742   [(set (match_operand:V16QI 0 "register_operand" "=v")
 743         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 744                                            (parallel [(const_int 8)
 745                                                       (const_int 9)
 746                                                       (const_int 10)
 747                                                       (const_int 11)
 748                                                       (const_int 12)
 749                                                       (const_int 13)
 750                                                       (const_int 14)
 751                                                       (const_int 15)
 752                                                       (const_int 0)
 753                                                       (const_int 1)
 754                                                       (const_int 2)
 755                                                       (const_int 3)
 756                                                       (const_int 4)
 757                                                       (const_int 5)
 758                                                       (const_int 6)
 759                                                       (const_int 7)]))
 760                       (match_operand:V16QI 2 "register_operand" "v")
 761                       (const_int 255)))]
 762   "TARGET_ALTIVEC"
 763   "vmrghb %0,%1,%2"
 764   [(set_attr "type" "vecperm")])
 765
 766 (define_insn "altivec_vmrghh"
 767   [(set (match_operand:V8HI 0 "register_operand" "=v")
 768         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 769                                            (parallel [(const_int 4)
 770                                                       (const_int 5)
 771                                                       (const_int 6)
 772                                                       (const_int 7)
 773                                                       (const_int 0)
 774                                                       (const_int 1)
 775                                                       (const_int 2)
 776                                                       (const_int 3)]))
 777                       (match_operand:V8HI 2 "register_operand" "v")
 778                       (const_int 15)))]
 779   "TARGET_ALTIVEC"
 780   "vmrghh %0,%1,%2"
 781   [(set_attr "type" "vecperm")])
 782
 783 (define_insn "altivec_vmrghw"
 784   [(set (match_operand:V4SI 0 "register_operand" "=v")
 785         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 786                                          (parallel [(const_int 2)
 787                                                     (const_int 3)
 788                                                     (const_int 0)
 789                                                     (const_int 1)]))
 790                       (match_operand:V4SI 2 "register_operand" "v")
 791                       (const_int 12)))]
 792   "TARGET_ALTIVEC"
 793   "vmrghw %0,%1,%2"
 794   [(set_attr "type" "vecperm")])
 795
 796 (define_insn "altivec_vmrglb"
 797   [(set (match_operand:V16QI 0 "register_operand" "=v")
 798         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 799                                            (parallel [(const_int 0)
 800                                                       (const_int 1)
 801                                                       (const_int 2)
 802                                                       (const_int 3)
 803                                                       (const_int 4)
 804                                                       (const_int 5)
 805                                                       (const_int 6)
 806                                                       (const_int 7)
 807                                                       (const_int 8)
 808                                                       (const_int 9)
 809                                                       (const_int 10)
 810                                                       (const_int 11)
 811                                                       (const_int 12)
 812                                                       (const_int 13)
 813                                                       (const_int 14)
 814                                                       (const_int 15)]))
 815                       (match_operand:V16QI 1 "register_operand" "v")
 816                       (const_int 255)))]
 817   "TARGET_ALTIVEC"
 818   "vmrglb %0,%1,%2"
 819   [(set_attr "type" "vecperm")])
 820
 821 (define_insn "altivec_vmrglh"
 822   [(set (match_operand:V8HI 0 "register_operand" "=v")
 823         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 824                                            (parallel [(const_int 0)
 825                                                       (const_int 1)
 826                                                       (const_int 2)
 827                                                       (const_int 3)
 828                                                       (const_int 4)
 829                                                       (const_int 5)
 830                                                       (const_int 6)
 831                                                       (const_int 7)]))
 832                       (match_operand:V8HI 1 "register_operand" "v")
 833                       (const_int 15)))]
 834   "TARGET_ALTIVEC"
 835   "vmrglh %0,%1,%2"
 836   [(set_attr "type" "vecperm")])
 837
 838 (define_insn "altivec_vmrglw"
 839   [(set (match_operand:V4SI 0 "register_operand" "=v")
 840         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 841                                          (parallel [(const_int 0)
 842                                                     (const_int 1)
 843                                                     (const_int 2)
 844                                                     (const_int 3)]))
 845                       (match_operand:V4SI 1 "register_operand" "v")
 846                       (const_int 12)))]
 847   "TARGET_ALTIVEC"
 848   "vmrglw %0,%1,%2"
 849   [(set_attr "type" "vecperm")])
 850
 851 (define_insn "uminv16qi3"
 852   [(set (match_operand:V16QI 0 "register_operand" "=v")
 853         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 854                     (match_operand:V16QI 2 "register_operand" "v")))]
 855   "TARGET_ALTIVEC"
 856   "vminub %0,%1,%2"
 857   [(set_attr "type" "vecsimple")])
 858
 859 (define_insn "sminv16qi3"
 860   [(set (match_operand:V16QI 0 "register_operand" "=v")
 861         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 862                     (match_operand:V16QI 2 "register_operand" "v")))]
 863   "TARGET_ALTIVEC"
 864   "vminsb %0,%1,%2"
 865   [(set_attr "type" "vecsimple")])
 866
 867 (define_insn "uminv8hi3"
 868   [(set (match_operand:V8HI 0 "register_operand" "=v")
 869         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 870                    (match_operand:V8HI 2 "register_operand" "v")))]
 871   "TARGET_ALTIVEC"
 872   "vminuh %0,%1,%2"
 873   [(set_attr "type" "vecsimple")])
 874
 875 (define_insn "sminv8hi3"
 876   [(set (match_operand:V8HI 0 "register_operand" "=v")
 877         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 878                    (match_operand:V8HI 2 "register_operand" "v")))]
 879   "TARGET_ALTIVEC"
 880   "vminsh %0,%1,%2"
 881   [(set_attr "type" "vecsimple")])
 882
 883 (define_insn "uminv4si3"
 884   [(set (match_operand:V4SI 0 "register_operand" "=v")
 885         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 886                    (match_operand:V4SI 2 "register_operand" "v")))]
 887   "TARGET_ALTIVEC"
 888   "vminuw %0,%1,%2"
 889   [(set_attr "type" "vecsimple")])
 890
 891 (define_insn "sminv4si3"
 892   [(set (match_operand:V4SI 0 "register_operand" "=v")
 893         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 894                    (match_operand:V4SI 2 "register_operand" "v")))]
 895   "TARGET_ALTIVEC"
 896   "vminsw %0,%1,%2"
 897   [(set_attr "type" "vecsimple")])
 898
 899 (define_insn "sminv4sf3"
 900   [(set (match_operand:V4SF 0 "register_operand" "=v")
 901         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 902                    (match_operand:V4SF 2 "register_operand" "v")))]
 903   "TARGET_ALTIVEC"
 904   "vminfp %0,%1,%2"
 905   [(set_attr "type" "veccmp")])
 906
 907 (define_insn "altivec_vmuleub"
 908   [(set (match_operand:V8HI 0 "register_operand" "=v")
 909         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 910                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 911   "TARGET_ALTIVEC"
 912   "vmuleub %0,%1,%2"
 913   [(set_attr "type" "veccomplex")])
 914
 915 (define_insn "altivec_vmulesb"
 916   [(set (match_operand:V8HI 0 "register_operand" "=v")
 917         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 918                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 919   "TARGET_ALTIVEC"
 920   "vmulesb %0,%1,%2"
 921   [(set_attr "type" "veccomplex")])
 922
 923 (define_insn "altivec_vmuleuh"
 924   [(set (match_operand:V4SI 0 "register_operand" "=v")
 925         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 926                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 927   "TARGET_ALTIVEC"
 928   "vmuleuh %0,%1,%2"
 929   [(set_attr "type" "veccomplex")])
 930
 931 (define_insn "altivec_vmulesh"
 932   [(set (match_operand:V4SI 0 "register_operand" "=v")
 933         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 934                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 935   "TARGET_ALTIVEC"
 936   "vmulesh %0,%1,%2"
 937   [(set_attr "type" "veccomplex")])
 938
 939 (define_insn "altivec_vmuloub"
 940   [(set (match_operand:V8HI 0 "register_operand" "=v")
 941         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 942                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 943   "TARGET_ALTIVEC"
 944   "vmuloub %0,%1,%2"
 945   [(set_attr "type" "veccomplex")])
 946
 947 (define_insn "altivec_vmulosb"
 948   [(set (match_operand:V8HI 0 "register_operand" "=v")
 949         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 950                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 951   "TARGET_ALTIVEC"
 952   "vmulosb %0,%1,%2"
 953   [(set_attr "type" "veccomplex")])
 954
 955 (define_insn "altivec_vmulouh"
 956   [(set (match_operand:V4SI 0 "register_operand" "=v")
 957         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 958                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 959   "TARGET_ALTIVEC"
 960   "vmulouh %0,%1,%2"
 961   [(set_attr "type" "veccomplex")])
 962
 963 (define_insn "altivec_vmulosh"
 964   [(set (match_operand:V4SI 0 "register_operand" "=v")
 965         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 966                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 967   "TARGET_ALTIVEC"
 968   "vmulosh %0,%1,%2"
 969   [(set_attr "type" "veccomplex")])
 970
 971 (define_insn "altivec_vnor"
 972   [(set (match_operand:V4SI 0 "register_operand" "=v")
 973         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 974                             (match_operand:V4SI 2 "register_operand" "v"))))]
 975   "TARGET_ALTIVEC"
 976   "vnor %0,%1,%2"
 977   [(set_attr "type" "vecsimple")])
 978
 979 (define_insn "iorv4si3"
 980   [(set (match_operand:V4SI 0 "register_operand" "=v")
 981         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 982                   (match_operand:V4SI 2 "register_operand" "v")))]
 983   "TARGET_ALTIVEC"
 984   "vor %0,%1,%2"
 985   [(set_attr "type" "vecsimple")])
 986
 987 (define_insn "altivec_vpkuhum"
 988   [(set (match_operand:V16QI 0 "register_operand" "=v")
 989         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 990                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 991   "TARGET_ALTIVEC"
 992   "vpkuhum %0,%1,%2"
 993   [(set_attr "type" "vecperm")])
 994
 995 (define_insn "altivec_vpkuwum"
 996   [(set (match_operand:V8HI 0 "register_operand" "=v")
 997         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 998                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 999   "TARGET_ALTIVEC"
1000   "vpkuwum %0,%1,%2"
1001   [(set_attr "type" "vecperm")])
1002
1003 (define_insn "altivec_vpkpx"
1004   [(set (match_operand:V8HI 0 "register_operand" "=v")
1005         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1006                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
1007   "TARGET_ALTIVEC"
1008   "vpkpx %0,%1,%2"
1009   [(set_attr "type" "vecperm")])
1010
1011 (define_insn "altivec_vpkuhss"
1012   [(set (match_operand:V16QI 0 "register_operand" "=v")
1013         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1014                        (match_operand:V8HI 2 "register_operand" "v")] 96))
1015    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1016   "TARGET_ALTIVEC"
1017   "vpkuhss %0,%1,%2"
1018   [(set_attr "type" "vecperm")])
1019
1020 (define_insn "altivec_vpkshss"
1021   [(set (match_operand:V16QI 0 "register_operand" "=v")
1022         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1023                        (match_operand:V8HI 2 "register_operand" "v")] 97))
1024    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1025   "TARGET_ALTIVEC"
1026   "vpkshss %0,%1,%2"
1027   [(set_attr "type" "vecperm")])
1028
1029 (define_insn "altivec_vpkuwss"
1030   [(set (match_operand:V8HI 0 "register_operand" "=v")
1031         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1032                       (match_operand:V4SI 2 "register_operand" "v")] 98))
1033    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1034   "TARGET_ALTIVEC"
1035   "vpkuwss %0,%1,%2"
1036   [(set_attr "type" "vecperm")])
1037
1038 (define_insn "altivec_vpkswss"
1039   [(set (match_operand:V8HI 0 "register_operand" "=v")
1040         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1041                       (match_operand:V4SI 2 "register_operand" "v")] 99))
1042    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1043   "TARGET_ALTIVEC"
1044   "vpkswss %0,%1,%2"
1045   [(set_attr "type" "vecperm")])
1046
1047 (define_insn "altivec_vpkuhus"
1048   [(set (match_operand:V16QI 0 "register_operand" "=v")
1049         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1050                        (match_operand:V8HI 2 "register_operand" "v")] 100))
1051    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1052   "TARGET_ALTIVEC"
1053   "vpkuhus %0,%1,%2"
1054   [(set_attr "type" "vecperm")])
1055
1056 (define_insn "altivec_vpkshus"
1057   [(set (match_operand:V16QI 0 "register_operand" "=v")
1058         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1059                        (match_operand:V8HI 2 "register_operand" "v")] 101))
1060    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1061   "TARGET_ALTIVEC"
1062   "vpkshus %0,%1,%2"
1063   [(set_attr "type" "vecperm")])
1064
1065 (define_insn "altivec_vpkuwus"
1066   [(set (match_operand:V8HI 0 "register_operand" "=v")
1067         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1068                       (match_operand:V4SI 2 "register_operand" "v")] 102))
1069    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1070   "TARGET_ALTIVEC"
1071   "vpkuwus %0,%1,%2"
1072   [(set_attr "type" "vecperm")])
1073
1074 (define_insn "altivec_vpkswus"
1075   [(set (match_operand:V8HI 0 "register_operand" "=v")
1076         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1077                       (match_operand:V4SI 2 "register_operand" "v")] 103))
1078    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1079   "TARGET_ALTIVEC"
1080   "vpkswus %0,%1,%2"
1081   [(set_attr "type" "vecperm")])
1082
1083 (define_insn "altivec_vrlb"
1084   [(set (match_operand:V16QI 0 "register_operand" "=v")
1085         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1086                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1087   "TARGET_ALTIVEC"
1088   "vrlb %0,%1,%2"
1089   [(set_attr "type" "vecsimple")])
1090
1091 (define_insn "altivec_vrlh"
1092   [(set (match_operand:V8HI 0 "register_operand" "=v")
1093         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1094                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1095   "TARGET_ALTIVEC"
1096   "vrlh %0,%1,%2"
1097   [(set_attr "type" "vecsimple")])
1098
1099 (define_insn "altivec_vrlw"
1100   [(set (match_operand:V4SI 0 "register_operand" "=v")
1101         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1102                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1103   "TARGET_ALTIVEC"
1104   "vrlw %0,%1,%2"
1105   [(set_attr "type" "vecsimple")])
1106
1107 (define_insn "altivec_vslb"
1108   [(set (match_operand:V16QI 0 "register_operand" "=v")
1109         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1110                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1111   "TARGET_ALTIVEC"
1112   "vslb %0,%1,%2"
1113   [(set_attr "type" "vecsimple")])
1114
1115 (define_insn "altivec_vslh"
1116   [(set (match_operand:V8HI 0 "register_operand" "=v")
1117         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1118                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1119   "TARGET_ALTIVEC"
1120   "vslh %0,%1,%2"
1121   [(set_attr "type" "vecsimple")])
1122
1123 (define_insn "altivec_vslw"
1124   [(set (match_operand:V4SI 0 "register_operand" "=v")
1125         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1126                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1127   "TARGET_ALTIVEC"
1128   "vslw %0,%1,%2"
1129   [(set_attr "type" "vecsimple")])
1130
1131 (define_insn "altivec_vslw_v4sf"
1132   [(set (match_operand:V4SF 0 "register_operand" "=v")
1133         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1134                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
1135   "TARGET_ALTIVEC"
1136   "vslw %0,%1,%2"
1137   [(set_attr "type" "vecsimple")])
1138
1139 (define_insn "altivec_vsl"
1140   [(set (match_operand:V4SI 0 "register_operand" "=v")
1141         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1142                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1143   "TARGET_ALTIVEC"
1144   "vsl %0,%1,%2"
1145   [(set_attr "type" "vecperm")])
1146
1147 (define_insn "altivec_vslo"
1148   [(set (match_operand:V4SI 0 "register_operand" "=v")
1149         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1150                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1151   "TARGET_ALTIVEC"
1152   "vslo %0,%1,%2"
1153   [(set_attr "type" "vecperm")])
1154
1155 (define_insn "altivec_vsrb"
1156   [(set (match_operand:V16QI 0 "register_operand" "=v")
1157         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1158                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1159   "TARGET_ALTIVEC"
1160   "vsrb %0,%1,%2"
1161   [(set_attr "type" "vecsimple")])
1162
1163 (define_insn "altivec_vsrh"
1164   [(set (match_operand:V8HI 0 "register_operand" "=v")
1165         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1166                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1167   "TARGET_ALTIVEC"
1168   "vsrh %0,%1,%2"
1169   [(set_attr "type" "vecsimple")])
1170
1171 (define_insn "altivec_vsrw"
1172   [(set (match_operand:V4SI 0 "register_operand" "=v")
1173         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1174                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1175   "TARGET_ALTIVEC"
1176   "vsrw %0,%1,%2"
1177   [(set_attr "type" "vecsimple")])
1178
1179 (define_insn "altivec_vsrab"
1180   [(set (match_operand:V16QI 0 "register_operand" "=v")
1181         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1182                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1183   "TARGET_ALTIVEC"
1184   "vsrab %0,%1,%2"
1185   [(set_attr "type" "vecsimple")])
1186
1187 (define_insn "altivec_vsrah"
1188   [(set (match_operand:V8HI 0 "register_operand" "=v")
1189         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1190                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1191   "TARGET_ALTIVEC"
1192   "vsrah %0,%1,%2"
1193   [(set_attr "type" "vecsimple")])
1194
1195 (define_insn "altivec_vsraw"
1196   [(set (match_operand:V4SI 0 "register_operand" "=v")
1197         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1198                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1199   "TARGET_ALTIVEC"
1200   "vsraw %0,%1,%2"
1201   [(set_attr "type" "vecsimple")])
1202
1203 (define_insn "altivec_vsr"
1204   [(set (match_operand:V4SI 0 "register_operand" "=v")
1205         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1206                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1207   "TARGET_ALTIVEC"
1208   "vsr %0,%1,%2"
1209   [(set_attr "type" "vecperm")])
1210
1211 (define_insn "altivec_vsro"
1212   [(set (match_operand:V4SI 0 "register_operand" "=v")
1213         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1214                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1215   "TARGET_ALTIVEC"
1216   "vsro %0,%1,%2"
1217   [(set_attr "type" "vecperm")])
1218
1219 (define_insn "subv16qi3"
1220   [(set (match_operand:V16QI 0 "register_operand" "=v")
1221         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1222                      (match_operand:V16QI 2 "register_operand" "v")))]
1223   "TARGET_ALTIVEC"
1224   "vsububm %0,%1,%2"
1225   [(set_attr "type" "vecsimple")])
1226
1227 (define_insn "subv8hi3"
1228   [(set (match_operand:V8HI 0 "register_operand" "=v")
1229         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1230                     (match_operand:V8HI 2 "register_operand" "v")))]
1231   "TARGET_ALTIVEC"
1232   "vsubuhm %0,%1,%2"
1233   [(set_attr "type" "vecsimple")])
1234
1235 (define_insn "subv4si3"
1236   [(set (match_operand:V4SI 0 "register_operand" "=v")
1237         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1238                     (match_operand:V4SI 2 "register_operand" "v")))]
1239   "TARGET_ALTIVEC"
1240   "vsubuwm %0,%1,%2"
1241   [(set_attr "type" "vecsimple")])
1242
1243 (define_insn "subv4sf3"
1244   [(set (match_operand:V4SF 0 "register_operand" "=v")
1245         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1246                     (match_operand:V4SF 2 "register_operand" "v")))]
1247   "TARGET_ALTIVEC"
1248   "vsubfp %0,%1,%2"
1249   [(set_attr "type" "vecfloat")])
1250
1251 (define_insn "altivec_vsubcuw"
1252   [(set (match_operand:V4SI 0 "register_operand" "=v")
1253         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1254                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1255   "TARGET_ALTIVEC"
1256   "vsubcuw %0,%1,%2"
1257   [(set_attr "type" "vecsimple")])
1258
1259 (define_insn "altivec_vsububs"
1260   [(set (match_operand:V16QI 0 "register_operand" "=v")
1261         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1262                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1263    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1264   "TARGET_ALTIVEC"
1265   "vsububs %0,%1,%2"
1266   [(set_attr "type" "vecsimple")])
1267
1268 (define_insn "altivec_vsubsbs"
1269   [(set (match_operand:V16QI 0 "register_operand" "=v")
1270         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1271                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1272    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1273   "TARGET_ALTIVEC"
1274   "vsubsbs %0,%1,%2"
1275   [(set_attr "type" "vecsimple")])
1276
1277 (define_insn "altivec_vsubuhs"
1278   [(set (match_operand:V8HI 0 "register_operand" "=v")
1279         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1280                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1281    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1282   "TARGET_ALTIVEC"
1283   "vsubuhs %0,%1,%2"
1284   [(set_attr "type" "vecsimple")])
1285
1286 (define_insn "altivec_vsubshs"
1287   [(set (match_operand:V8HI 0 "register_operand" "=v")
1288         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1289                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1290    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1291   "TARGET_ALTIVEC"
1292   "vsubshs %0,%1,%2"
1293   [(set_attr "type" "vecsimple")])
1294
1295 (define_insn "altivec_vsubuws"
1296   [(set (match_operand:V4SI 0 "register_operand" "=v")
1297         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1298                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1299    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1300   "TARGET_ALTIVEC"
1301   "vsubuws %0,%1,%2"
1302   [(set_attr "type" "vecsimple")])
1303
1304 (define_insn "altivec_vsubsws"
1305   [(set (match_operand:V4SI 0 "register_operand" "=v")
1306         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1307                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1308    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1309   "TARGET_ALTIVEC"
1310   "vsubsws %0,%1,%2"
1311   [(set_attr "type" "vecsimple")])
1312
1313 (define_insn "altivec_vsum4ubs"
1314   [(set (match_operand:V4SI 0 "register_operand" "=v")
1315         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1316                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1317    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1318   "TARGET_ALTIVEC"
1319   "vsum4ubs %0,%1,%2"
1320   [(set_attr "type" "veccomplex")])
1321
1322 (define_insn "altivec_vsum4sbs"
1323   [(set (match_operand:V4SI 0 "register_operand" "=v")
1324         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1325                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1326    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1327   "TARGET_ALTIVEC"
1328   "vsum4sbs %0,%1,%2"
1329   [(set_attr "type" "veccomplex")])
1330
1331 (define_insn "altivec_vsum4shs"
1332   [(set (match_operand:V4SI 0 "register_operand" "=v")
1333         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1334                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1335    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1336   "TARGET_ALTIVEC"
1337   "vsum4shs %0,%1,%2"
1338   [(set_attr "type" "veccomplex")])
1339
1340 (define_insn "altivec_vsum2sws"
1341   [(set (match_operand:V4SI 0 "register_operand" "=v")
1342         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1343                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1344    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1345   "TARGET_ALTIVEC"
1346   "vsum2sws %0,%1,%2"
1347   [(set_attr "type" "veccomplex")])
1348
1349 (define_insn "altivec_vsumsws"
1350   [(set (match_operand:V4SI 0 "register_operand" "=v")
1351         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1352                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1353    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1354   "TARGET_ALTIVEC"
1355   "vsumsws %0,%1,%2"
1356   [(set_attr "type" "veccomplex")])
1357
1358 ;; Vector xor's
1359 (define_insn "xorv4si3"
1360   [(set (match_operand:V4SI 0 "register_operand" "=v")
1361         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1362                   (match_operand:V4SI 2 "register_operand" "v")))]
1363   "TARGET_ALTIVEC"
1364   "vxor %0,%1,%2"
1365   [(set_attr "type" "vecsimple")])
1366
1367 (define_insn "xorv8hi3"
1368   [(set (match_operand:V8HI 0 "register_operand" "=v")
1369         (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1370                   (match_operand:V8HI 2 "register_operand" "v")))]
1371   "TARGET_ALTIVEC"
1372   "vxor %0,%1,%2"
1373   [(set_attr "type" "vecsimple")])
1374
1375 (define_insn "xorv16qi3"
1376   [(set (match_operand:V16QI 0 "register_operand" "=v")
1377         (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1378                    (match_operand:V16QI 2 "register_operand" "v")))]
1379   "TARGET_ALTIVEC"
1380   "vxor %0,%1,%2"
1381   [(set_attr "type" "vecsimple")])
1382
1383 (define_insn "altivec_vspltb"
1384   [(set (match_operand:V16QI 0 "register_operand" "=v")
1385         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1386                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1387   "TARGET_ALTIVEC"
1388   "vspltb %0,%1,%2"
1389   [(set_attr "type" "vecperm")])
1390 ;; End of vector xor's
1391
1392 (define_insn "altivec_vsplth"
1393   [(set (match_operand:V8HI 0 "register_operand" "=v")
1394         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1395                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1396   "TARGET_ALTIVEC"
1397   "vsplth %0,%1,%2"
1398   [(set_attr "type" "vecperm")])
1399
1400 (define_insn "altivec_vspltw"
1401   [(set (match_operand:V4SI 0 "register_operand" "=v")
1402         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1403                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1404   "TARGET_ALTIVEC"
1405   "vspltw %0,%1,%2"
1406   [(set_attr "type" "vecperm")])
1407
1408 (define_insn "altivec_vspltisb"
1409   [(set (match_operand:V16QI 0 "register_operand" "=v")
1410         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1411                       UNSPEC_VSPLTISB))]
1412   "TARGET_ALTIVEC"
1413   "vspltisb %0,%1"
1414   [(set_attr "type" "vecperm")])
1415
1416 (define_insn "altivec_vspltish"
1417   [(set (match_operand:V8HI 0 "register_operand" "=v")
1418         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1419                      UNSPEC_VSPLTISH))]
1420   "TARGET_ALTIVEC"
1421   "vspltish %0,%1"
1422   [(set_attr "type" "vecperm")])
1423
1424 (define_insn "altivec_vspltisw"
1425   [(set (match_operand:V4SI 0 "register_operand" "=v")
1426         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1427                      UNSPEC_VSPLTISW))]
1428   "TARGET_ALTIVEC"
1429   "vspltisw %0,%1"
1430   [(set_attr "type" "vecperm")])
1431
1432 (define_insn "altivec_vspltisw_v4sf"
1433   [(set (match_operand:V4SF 0 "register_operand" "=v")
1434         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1435   "TARGET_ALTIVEC"
1436   "vspltisw %0,%1"
1437   [(set_attr "type" "vecperm")])
1438
1439 (define_insn "ftruncv4sf2"
1440   [(set (match_operand:V4SF 0 "register_operand" "=v")
1441         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1442   "TARGET_ALTIVEC"
1443   "vrfiz %0,%1"
1444   [(set_attr "type" "vecfloat")])
1445
1446 (define_insn "altivec_vperm_4si"
1447   [(set (match_operand:V4SI 0 "register_operand" "=v")
1448         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1449                       (match_operand:V4SI 2 "register_operand" "v")
1450                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1451   "TARGET_ALTIVEC"
1452   "vperm %0,%1,%2,%3"
1453   [(set_attr "type" "vecperm")])
1454
1455 (define_insn "altivec_vperm_4sf"
1456   [(set (match_operand:V4SF 0 "register_operand" "=v")
1457         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1458                       (match_operand:V4SF 2 "register_operand" "v")
1459                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1460   "TARGET_ALTIVEC"
1461   "vperm %0,%1,%2,%3"
1462   [(set_attr "type" "vecperm")])
1463
1464 (define_insn "altivec_vperm_8hi"
1465   [(set (match_operand:V8HI 0 "register_operand" "=v")
1466         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1467                       (match_operand:V8HI 2 "register_operand" "v")
1468                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1469   "TARGET_ALTIVEC"
1470   "vperm %0,%1,%2,%3"
1471   [(set_attr "type" "vecperm")])
1472
1473 (define_insn "altivec_vperm_16qi"
1474   [(set (match_operand:V16QI 0 "register_operand" "=v")
1475         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1476                        (match_operand:V16QI 2 "register_operand" "v")
1477                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1478   "TARGET_ALTIVEC"
1479   "vperm %0,%1,%2,%3"
1480   [(set_attr "type" "vecperm")])
1481
1482 (define_insn "altivec_vrfip"
1483   [(set (match_operand:V4SF 0 "register_operand" "=v")
1484         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1485   "TARGET_ALTIVEC"
1486   "vrfip %0,%1"
1487   [(set_attr "type" "vecfloat")])
1488
1489 (define_insn "altivec_vrfin"
1490   [(set (match_operand:V4SF 0 "register_operand" "=v")
1491         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1492   "TARGET_ALTIVEC"
1493   "vrfin %0,%1"
1494   [(set_attr "type" "vecfloat")])
1495
1496 (define_insn "altivec_vrfim"
1497   [(set (match_operand:V4SF 0 "register_operand" "=v")
1498         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1499   "TARGET_ALTIVEC"
1500   "vrfim %0,%1"
1501   [(set_attr "type" "vecfloat")])
1502
1503 (define_insn "altivec_vcfux"
1504   [(set (match_operand:V4SF 0 "register_operand" "=v")
1505         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1506                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1507   "TARGET_ALTIVEC"
1508   "vcfux %0,%1,%2"
1509   [(set_attr "type" "vecfloat")])
1510
1511 (define_insn "altivec_vcfsx"
1512   [(set (match_operand:V4SF 0 "register_operand" "=v")
1513         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1514                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1515   "TARGET_ALTIVEC"
1516   "vcfsx %0,%1,%2"
1517   [(set_attr "type" "vecfloat")])
1518
1519 (define_insn "altivec_vctuxs"
1520   [(set (match_operand:V4SI 0 "register_operand" "=v")
1521         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1522                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1523    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1524   "TARGET_ALTIVEC"
1525   "vctuxs %0,%1,%2"
1526   [(set_attr "type" "vecfloat")])
1527
1528 (define_insn "altivec_vctsxs"
1529   [(set (match_operand:V4SI 0 "register_operand" "=v")
1530         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1531                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1532    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1533   "TARGET_ALTIVEC"
1534   "vctsxs %0,%1,%2"
1535   [(set_attr "type" "vecfloat")])
1536
1537 (define_insn "altivec_vlogefp"
1538   [(set (match_operand:V4SF 0 "register_operand" "=v")
1539         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1540   "TARGET_ALTIVEC"
1541   "vlogefp %0,%1"
1542   [(set_attr "type" "vecfloat")])
1543
1544 (define_insn "altivec_vexptefp"
1545   [(set (match_operand:V4SF 0 "register_operand" "=v")
1546         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1547   "TARGET_ALTIVEC"
1548   "vexptefp %0,%1"
1549   [(set_attr "type" "vecfloat")])
1550
1551 (define_insn "altivec_vrsqrtefp"
1552   [(set (match_operand:V4SF 0 "register_operand" "=v")
1553         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1554   "TARGET_ALTIVEC"
1555   "vrsqrtefp %0,%1"
1556   [(set_attr "type" "vecfloat")])
1557
1558 (define_insn "altivec_vrefp"
1559   [(set (match_operand:V4SF 0 "register_operand" "=v")
1560         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1561   "TARGET_ALTIVEC"
1562   "vrefp %0,%1"
1563   [(set_attr "type" "vecfloat")])
1564
1565 (define_insn "altivec_vsel_4si"
1566   [(set (match_operand:V4SI 0 "register_operand" "=v")
1567         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1568                       (match_operand:V4SI 2 "register_operand" "v")
1569                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1570   "TARGET_ALTIVEC"
1571   "vsel %0,%1,%2,%3"
1572   [(set_attr "type" "vecperm")])
1573
1574 (define_insn "altivec_vsel_4sf"
1575   [(set (match_operand:V4SF 0 "register_operand" "=v")
1576         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1577                       (match_operand:V4SF 2 "register_operand" "v")
1578                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1579   "TARGET_ALTIVEC"
1580   "vsel %0,%1,%2,%3"
1581   [(set_attr "type" "vecperm")])
1582
1583 (define_insn "altivec_vsel_8hi"
1584   [(set (match_operand:V8HI 0 "register_operand" "=v")
1585         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1586                       (match_operand:V8HI 2 "register_operand" "v")
1587                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1588   "TARGET_ALTIVEC"
1589   "vsel %0,%1,%2,%3"
1590   [(set_attr "type" "vecperm")])
1591
1592 (define_insn "altivec_vsel_16qi"
1593   [(set (match_operand:V16QI 0 "register_operand" "=v")
1594         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1595                        (match_operand:V16QI 2 "register_operand" "v")
1596                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1597   "TARGET_ALTIVEC"
1598   "vsel %0,%1,%2,%3"
1599   [(set_attr "type" "vecperm")])
1600
1601 (define_insn "altivec_vsldoi_4si"
1602   [(set (match_operand:V4SI 0 "register_operand" "=v")
1603         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1604                       (match_operand:V4SI 2 "register_operand" "v")
1605                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1606   "TARGET_ALTIVEC"
1607   "vsldoi %0,%1,%2,%3"
1608   [(set_attr "type" "vecperm")])
1609
1610 (define_insn "altivec_vsldoi_4sf"
1611   [(set (match_operand:V4SF 0 "register_operand" "=v")
1612         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1613                       (match_operand:V4SF 2 "register_operand" "v")
1614                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1615   "TARGET_ALTIVEC"
1616   "vsldoi %0,%1,%2,%3"
1617   [(set_attr "type" "vecperm")])
1618
1619 (define_insn "altivec_vsldoi_8hi"
1620   [(set (match_operand:V8HI 0 "register_operand" "=v")
1621         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1622                       (match_operand:V8HI 2 "register_operand" "v")
1623                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1624   "TARGET_ALTIVEC"
1625   "vsldoi %0,%1,%2,%3"
1626   [(set_attr "type" "vecperm")])
1627
1628 (define_insn "altivec_vsldoi_16qi"
1629   [(set (match_operand:V16QI 0 "register_operand" "=v")
1630         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1631                        (match_operand:V16QI 2 "register_operand" "v")
1632                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1633   "TARGET_ALTIVEC"
1634   "vsldoi %0,%1,%2,%3"
1635   [(set_attr "type" "vecperm")])
1636
1637 (define_insn "altivec_vupkhsb"
1638   [(set (match_operand:V8HI 0 "register_operand" "=v")
1639         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1640   "TARGET_ALTIVEC"
1641   "vupkhsb %0,%1"
1642   [(set_attr "type" "vecperm")])
1643
1644 (define_insn "altivec_vupkhpx"
1645   [(set (match_operand:V4SI 0 "register_operand" "=v")
1646         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1647   "TARGET_ALTIVEC"
1648   "vupkhpx %0,%1"
1649   [(set_attr "type" "vecperm")])
1650
1651 (define_insn "altivec_vupkhsh"
1652   [(set (match_operand:V4SI 0 "register_operand" "=v")
1653         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1654   "TARGET_ALTIVEC"
1655   "vupkhsh %0,%1"
1656   [(set_attr "type" "vecperm")])
1657
1658 (define_insn "altivec_vupklsb"
1659   [(set (match_operand:V8HI 0 "register_operand" "=v")
1660         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1661   "TARGET_ALTIVEC"
1662   "vupklsb %0,%1"
1663   [(set_attr "type" "vecperm")])
1664
1665 (define_insn "altivec_vupklpx"
1666   [(set (match_operand:V4SI 0 "register_operand" "=v")
1667         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1668   "TARGET_ALTIVEC"
1669   "vupklpx %0,%1"
1670   [(set_attr "type" "vecperm")])
1671
1672 (define_insn "altivec_vupklsh"
1673   [(set (match_operand:V4SI 0 "register_operand" "=v")
1674         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1675   "TARGET_ALTIVEC"
1676   "vupklsh %0,%1"
1677   [(set_attr "type" "vecperm")])
1678
1679 ;; AltiVec predicates.
1680
1681 (define_expand "cr6_test_for_zero"
1682   [(set (match_operand:SI 0 "register_operand" "=r")
1683         (eq:SI (reg:CC 74)
1684                (const_int 0)))]
1685   "TARGET_ALTIVEC"
1686   "")
1687
1688 (define_expand "cr6_test_for_zero_reverse"
1689   [(set (match_operand:SI 0 "register_operand" "=r")
1690         (eq:SI (reg:CC 74)
1691                (const_int 0)))
1692    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1693   "TARGET_ALTIVEC"
1694   "")
1695
1696 (define_expand "cr6_test_for_lt"
1697   [(set (match_operand:SI 0 "register_operand" "=r")
1698         (lt:SI (reg:CC 74)
1699                (const_int 0)))]
1700   "TARGET_ALTIVEC"
1701   "")
1702
1703 (define_expand "cr6_test_for_lt_reverse"
1704   [(set (match_operand:SI 0 "register_operand" "=r")
1705         (lt:SI (reg:CC 74)
1706                (const_int 0)))
1707    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1708   "TARGET_ALTIVEC"
1709   "")
1710
1711 ;; We can get away with generating the opcode on the fly (%3 below)
1712 ;; because all the predicates have the same scheduling parameters.
1713
1714 (define_insn "altivec_predicate_v4si"
1715   [(set (reg:CC 74)
1716         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1717                     (match_operand:V4SI 2 "register_operand" "v")
1718                     (match_operand 3 "any_operand" "")] 173))
1719    (clobber (match_scratch:V4SI 0 "=v"))]
1720   "TARGET_ALTIVEC"
1721   "%3 %0,%1,%2"
1722 [(set_attr "type" "veccmp")])
1723
1724 (define_insn "altivec_predicate_v4sf"
1725   [(set (reg:CC 74)
1726         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1727                     (match_operand:V4SF 2 "register_operand" "v")
1728                     (match_operand 3 "any_operand" "")] 174))
1729    (clobber (match_scratch:V4SF 0 "=v"))]
1730   "TARGET_ALTIVEC"
1731   "%3 %0,%1,%2"
1732 [(set_attr "type" "veccmp")])
1733
1734 (define_insn "altivec_predicate_v8hi"
1735   [(set (reg:CC 74)
1736         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1737                     (match_operand:V8HI 2 "register_operand" "v")
1738                     (match_operand 3 "any_operand" "")] 175))
1739    (clobber (match_scratch:V8HI 0 "=v"))]
1740   "TARGET_ALTIVEC"
1741   "%3 %0,%1,%2"
1742 [(set_attr "type" "veccmp")])
1743
1744 (define_insn "altivec_predicate_v16qi"
1745   [(set (reg:CC 74)
1746         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1747                     (match_operand:V16QI 2 "register_operand" "v")
1748                     (match_operand 3 "any_operand" "")] 175))
1749    (clobber (match_scratch:V16QI 0 "=v"))]
1750   "TARGET_ALTIVEC"
1751   "%3 %0,%1,%2"
1752 [(set_attr "type" "veccmp")])
1753
1754 (define_insn "altivec_mtvscr"
1755   [(set (reg:SI 110)
1756         (unspec_volatile:SI
1757          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1758   "TARGET_ALTIVEC"
1759   "mtvscr %0"
1760   [(set_attr "type" "vecsimple")])
1761
1762 (define_insn "altivec_mfvscr"
1763   [(set (match_operand:V8HI 0 "register_operand" "=v")
1764         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1765   "TARGET_ALTIVEC"
1766   "mfvscr %0"
1767   [(set_attr "type" "vecsimple")])
1768
1769 (define_insn "altivec_dssall"
1770   [(unspec [(const_int 0)] 188)]
1771   "TARGET_ALTIVEC"
1772   "dssall"
1773   [(set_attr "type" "vecsimple")])
1774
1775 (define_insn "altivec_dss"
1776   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1777   "TARGET_ALTIVEC"
1778   "dss %0"
1779   [(set_attr "type" "vecsimple")])
1780
1781 (define_insn "altivec_dst"
1782   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1783             (match_operand:SI 1 "register_operand" "r")
1784             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1785   "TARGET_ALTIVEC"
1786   "dst %P0,%1,%2"
1787   [(set_attr "type" "vecsimple")])
1788
1789 (define_insn "altivec_dstt"
1790   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1791             (match_operand:SI 1 "register_operand" "r")
1792             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1793   "TARGET_ALTIVEC"
1794   "dstt %P0,%1,%2"
1795   [(set_attr "type" "vecsimple")])
1796
1797 (define_insn "altivec_dstst"
1798   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1799             (match_operand:SI 1 "register_operand" "r")
1800             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1801   "TARGET_ALTIVEC"
1802   "dstst %P0,%1,%2"
1803   [(set_attr "type" "vecsimple")])
1804
1805 (define_insn "altivec_dststt"
1806   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1807             (match_operand:SI 1 "register_operand" "r")
1808             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1809   "TARGET_ALTIVEC"
1810   "dststt %P0,%1,%2"
1811   [(set_attr "type" "vecsimple")])
1812
1813 (define_insn "altivec_lvsl"
1814   [(set (match_operand:V16QI 0 "register_operand" "=v")
1815         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1816   "TARGET_ALTIVEC"
1817   "lvsl %0,%y1"
1818   [(set_attr "type" "vecload")])
1819
1820 (define_insn "altivec_lvsr"
1821   [(set (match_operand:V16QI 0 "register_operand" "=v")
1822         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1823   "TARGET_ALTIVEC"
1824   "lvsr %0,%y1"
1825   [(set_attr "type" "vecload")])
1826
1827 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1828 ;; identical rtl but different instructions-- and gcc gets confused.
1829
1830 (define_insn "altivec_lvebx"
1831   [(parallel
1832     [(set (match_operand:V16QI 0 "register_operand" "=v")
1833           (match_operand:V16QI 1 "memory_operand" "m"))
1834      (unspec [(const_int 0)] 196)])]
1835   "TARGET_ALTIVEC"
1836   "lvebx %0,%y1"
1837   [(set_attr "type" "vecload")])
1838
1839 (define_insn "altivec_lvehx"
1840   [(parallel
1841     [(set (match_operand:V8HI 0 "register_operand" "=v")
1842           (match_operand:V8HI 1 "memory_operand" "m"))
1843      (unspec [(const_int 0)] 197)])]
1844   "TARGET_ALTIVEC"
1845   "lvehx %0,%y1"
1846   [(set_attr "type" "vecload")])
1847
1848 (define_insn "altivec_lvewx"
1849   [(parallel
1850     [(set (match_operand:V4SI 0 "register_operand" "=v")
1851           (match_operand:V4SI 1 "memory_operand" "m"))
1852      (unspec [(const_int 0)] 198)])]
1853   "TARGET_ALTIVEC"
1854   "lvewx %0,%y1"
1855   [(set_attr "type" "vecload")])
1856
1857 (define_insn "altivec_lvxl"
1858   [(parallel
1859     [(set (match_operand:V4SI 0 "register_operand" "=v")
1860           (match_operand:V4SI 1 "memory_operand" "m"))
1861      (unspec [(const_int 0)] 213)])]
1862   "TARGET_ALTIVEC"
1863   "lvxl %0,%y1"
1864   [(set_attr "type" "vecload")])
1865
1866 (define_insn "altivec_lvx"
1867   [(set (match_operand:V4SI 0 "register_operand" "=v")
1868         (match_operand:V4SI 1 "memory_operand" "m"))]
1869   "TARGET_ALTIVEC"
1870   "lvx %0,%y1"
1871   [(set_attr "type" "vecload")])
1872
1873 (define_insn "altivec_stvx"
1874   [(parallel
1875     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1876           (match_operand:V4SI 1 "register_operand" "v"))
1877      (unspec [(const_int 0)] 201)])]
1878   "TARGET_ALTIVEC"
1879   "stvx %1,%y0"
1880   [(set_attr "type" "vecstore")])
1881
1882 (define_insn "altivec_stvxl"
1883   [(parallel
1884     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1885           (match_operand:V4SI 1 "register_operand" "v"))
1886      (unspec [(const_int 0)] 202)])]
1887   "TARGET_ALTIVEC"
1888   "stvxl %1,%y0"
1889   [(set_attr "type" "vecstore")])
1890
1891 (define_insn "altivec_stvebx"
1892   [(parallel
1893     [(set (match_operand:V16QI 0 "memory_operand" "=m")
1894           (match_operand:V16QI 1 "register_operand" "v"))
1895      (unspec [(const_int 0)] 203)])]
1896   "TARGET_ALTIVEC"
1897   "stvebx %1,%y0"
1898   [(set_attr "type" "vecstore")])
1899
1900 (define_insn "altivec_stvehx"
1901   [(parallel
1902     [(set (match_operand:V8HI 0 "memory_operand" "=m")
1903           (match_operand:V8HI 1 "register_operand" "v"))
1904      (unspec [(const_int 0)] 204)])]
1905   "TARGET_ALTIVEC"
1906   "stvehx %1,%y0"
1907   [(set_attr "type" "vecstore")])
1908
1909 (define_insn "altivec_stvewx"
1910   [(parallel
1911     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1912           (match_operand:V4SI 1 "register_operand" "v"))
1913      (unspec [(const_int 0)] 205)])]
1914   "TARGET_ALTIVEC"
1915   "stvewx %1,%y0"
1916   [(set_attr "type" "vecstore")])
1917
1918 (define_insn "absv16qi2"
1919   [(set (match_operand:V16QI 0 "register_operand" "=v")
1920         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1921    (clobber (match_scratch:V16QI 2 "=&v"))
1922    (clobber (match_scratch:V16QI 3 "=&v"))]
1923   "TARGET_ALTIVEC"
1924   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1925   [(set_attr "type" "vecsimple")
1926    (set_attr "length" "12")])
1927
1928 (define_insn "absv8hi2"
1929   [(set (match_operand:V8HI 0 "register_operand" "=v")
1930         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1931    (clobber (match_scratch:V8HI 2 "=&v"))
1932    (clobber (match_scratch:V8HI 3 "=&v"))]
1933   "TARGET_ALTIVEC"
1934   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1935   [(set_attr "type" "vecsimple")
1936    (set_attr "length" "12")])
1937
1938 (define_insn "absv4si2"
1939   [(set (match_operand:V4SI 0 "register_operand" "=v")
1940         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1941    (clobber (match_scratch:V4SI 2 "=&v"))
1942    (clobber (match_scratch:V4SI 3 "=&v"))]
1943   "TARGET_ALTIVEC"
1944   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1945   [(set_attr "type" "vecsimple")
1946    (set_attr "length" "12")])
1947
1948 (define_insn "absv4sf2"
1949   [(set (match_operand:V4SF 0 "register_operand" "=v")
1950         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1951    (clobber (match_scratch:V4SF 2 "=&v"))
1952    (clobber (match_scratch:V4SF 3 "=&v"))]
1953   "TARGET_ALTIVEC"
1954   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1955   [(set_attr "type" "vecsimple")
1956    (set_attr "length" "12")])
1957
1958 (define_insn "altivec_abss_v16qi"
1959   [(set (match_operand:V16QI 0 "register_operand" "=v")
1960         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1961    (clobber (match_scratch:V16QI 2 "=&v"))
1962    (clobber (match_scratch:V16QI 3 "=&v"))]
1963   "TARGET_ALTIVEC"
1964   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1965   [(set_attr "type" "vecsimple")
1966    (set_attr "length" "12")])
1967
1968 (define_insn "altivec_abss_v8hi"
1969   [(set (match_operand:V8HI 0 "register_operand" "=v")
1970         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1971    (clobber (match_scratch:V8HI 2 "=&v"))
1972    (clobber (match_scratch:V8HI 3 "=&v"))]
1973   "TARGET_ALTIVEC"
1974   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1975   [(set_attr "type" "vecsimple")
1976    (set_attr "length" "12")])
1977
1978 (define_insn "altivec_abss_v4si"
1979   [(set (match_operand:V4SI 0 "register_operand" "=v")
1980         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1981    (clobber (match_scratch:V4SI 2 "=&v"))
1982    (clobber (match_scratch:V4SI 3 "=&v"))]
1983   "TARGET_ALTIVEC"
1984   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1985   [(set_attr "type" "vecsimple")
1986    (set_attr "length" "12")])