2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
20 ;; MA 02111-1307, USA.
43 (UNSPEC_VCOND_V4SI 301)
44 (UNSPEC_VCOND_V4SF 302)
45 (UNSPEC_VCOND_V8HI 303)
46 (UNSPEC_VCOND_V16QI 304)
47 (UNSPEC_VCONDU_V4SI 305)
48 (UNSPEC_VCONDU_V8HI 306)
49 (UNSPEC_VCONDU_V16QI 307)
53 (define_mode_macro VI [V4SI V8HI V16QI])
55 (define_mode_macro VIshort [V8HI V16QI])
57 (define_mode_macro VF [V4SF])
58 ;; Vec modes, pity mode macros are not composable
59 (define_mode_macro V [V4SI V8HI V16QI V4SF])
61 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
63 ;; Generic LVX load instruction.
64 (define_insn "altivec_lvx_<mode>"
65 [(set (match_operand:V 0 "altivec_register_operand" "=v")
66 (match_operand:V 1 "memory_operand" "m"))]
69 [(set_attr "type" "vecload")])
71 ;; Generic STVX store instruction.
72 (define_insn "altivec_stvx_<mode>"
73 [(set (match_operand:V 0 "memory_operand" "=m")
74 (match_operand:V 1 "altivec_register_operand" "v"))]
77 [(set_attr "type" "vecstore")])
79 ;; Vector move instructions.
80 (define_expand "mov<mode>"
81 [(set (match_operand:V 0 "nonimmediate_operand" "")
82 (match_operand:V 1 "any_operand" ""))]
85 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
89 (define_insn "*mov<mode>_internal"
90 [(set (match_operand:V 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
91 (match_operand:V 1 "input_operand" "v,m,v,r,o,r,W"))]
93 && (register_operand (operands[0], <MODE>mode)
94 || register_operand (operands[1], <MODE>mode))"
96 switch (which_alternative)
98 case 0: return "stvx %1,%y0";
99 case 1: return "lvx %0,%y1";
100 case 2: return "vor %0,%1,%1";
104 case 6: return output_vec_const_move (operands);
105 default: gcc_unreachable ();
108 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
111 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
112 (match_operand:V4SI 1 "input_operand" ""))]
113 "TARGET_ALTIVEC && reload_completed
114 && gpr_or_gpr_p (operands[0], operands[1])"
117 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
121 [(set (match_operand:V4SI 0 "altivec_register_operand" "")
122 (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
123 "TARGET_ALTIVEC && reload_completed"
124 [(set (match_dup 0) (match_dup 3))
126 (plus:V4SI (match_dup 0)
129 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
133 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
134 (match_operand:V8HI 1 "input_operand" ""))]
135 "TARGET_ALTIVEC && reload_completed
136 && gpr_or_gpr_p (operands[0], operands[1])"
138 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
141 [(set (match_operand:V8HI 0 "altivec_register_operand" "")
142 (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
143 "TARGET_ALTIVEC && reload_completed"
144 [(set (match_dup 0) (match_dup 3))
146 (plus:V8HI (match_dup 0)
149 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
153 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
154 (match_operand:V16QI 1 "input_operand" ""))]
155 "TARGET_ALTIVEC && reload_completed
156 && gpr_or_gpr_p (operands[0], operands[1])"
158 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
161 [(set (match_operand:V16QI 0 "altivec_register_operand" "")
162 (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
163 "TARGET_ALTIVEC && reload_completed"
164 [(set (match_dup 0) (match_dup 3))
166 (plus:V16QI (match_dup 0)
169 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
173 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
174 (match_operand:V4SF 1 "input_operand" ""))]
175 "TARGET_ALTIVEC && reload_completed
176 && gpr_or_gpr_p (operands[0], operands[1])"
179 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
182 (define_insn "get_vrsave_internal"
183 [(set (match_operand:SI 0 "register_operand" "=r")
184 (unspec:SI [(reg:SI 109)] 214))]
188 return "mfspr %0,256";
190 return "mfvrsave %0";
192 [(set_attr "type" "*")])
194 (define_insn "*set_vrsave_internal"
195 [(match_parallel 0 "vrsave_operation"
197 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
198 (reg:SI 109)] 30))])]
202 return "mtspr 256,%1";
204 return "mtvrsave %1";
206 [(set_attr "type" "*")])
208 (define_insn "*save_world"
209 [(match_parallel 0 "save_world_operation"
210 [(clobber (match_operand:SI 1 "register_operand" "=l"))
211 (use (match_operand:SI 2 "call_operand" "s"))])]
212 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
214 [(set_attr "type" "branch")
215 (set_attr "length" "4")])
217 (define_insn "*restore_world"
218 [(match_parallel 0 "restore_world_operation"
220 (use (match_operand:SI 1 "register_operand" "l"))
221 (use (match_operand:SI 2 "call_operand" "s"))
222 (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
223 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
226 ;; Simple binary operations.
229 (define_insn "add<mode>3"
230 [(set (match_operand:VI 0 "register_operand" "=v")
231 (plus:VI (match_operand:VI 1 "register_operand" "v")
232 (match_operand:VI 2 "register_operand" "v")))]
234 "vaddu<VI_char>m %0,%1,%2"
235 [(set_attr "type" "vecsimple")])
237 (define_insn "addv4sf3"
238 [(set (match_operand:V4SF 0 "register_operand" "=v")
239 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
240 (match_operand:V4SF 2 "register_operand" "v")))]
243 [(set_attr "type" "vecfloat")])
245 (define_insn "altivec_vaddcuw"
246 [(set (match_operand:V4SI 0 "register_operand" "=v")
247 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
248 (match_operand:V4SI 2 "register_operand" "v")] 35))]
251 [(set_attr "type" "vecsimple")])
253 (define_insn "altivec_vaddu<VI_char>s"
254 [(set (match_operand:VI 0 "register_operand" "=v")
255 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
256 (match_operand:VI 2 "register_operand" "v")] 36))
257 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
259 "vaddu<VI_char>s %0,%1,%2"
260 [(set_attr "type" "vecsimple")])
262 (define_insn "altivec_vadds<VI_char>s"
263 [(set (match_operand:VI 0 "register_operand" "=v")
264 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
265 (match_operand:VI 2 "register_operand" "v")] 37))
266 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
268 "vadds<VI_char>s %0,%1,%2"
269 [(set_attr "type" "vecsimple")])
272 (define_insn "sub<mode>3"
273 [(set (match_operand:VI 0 "register_operand" "=v")
274 (minus:VI (match_operand:VI 1 "register_operand" "v")
275 (match_operand:VI 2 "register_operand" "v")))]
277 "vsubu<VI_char>m %0,%1,%2"
278 [(set_attr "type" "vecsimple")])
280 (define_insn "subv4sf3"
281 [(set (match_operand:V4SF 0 "register_operand" "=v")
282 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
283 (match_operand:V4SF 2 "register_operand" "v")))]
286 [(set_attr "type" "vecfloat")])
288 (define_insn "altivec_vsubcuw"
289 [(set (match_operand:V4SI 0 "register_operand" "=v")
290 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
291 (match_operand:V4SI 2 "register_operand" "v")] 124))]
294 [(set_attr "type" "vecsimple")])
296 (define_insn "altivec_vsubu<VI_char>s"
297 [(set (match_operand:VI 0 "register_operand" "=v")
298 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
299 (match_operand:VI 2 "register_operand" "v")] 125))
300 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
302 "vsubu<VI_char>s %0,%1,%2"
303 [(set_attr "type" "vecsimple")])
305 (define_insn "altivec_vsubs<VI_char>s"
306 [(set (match_operand:VI 0 "register_operand" "=v")
307 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
308 (match_operand:VI 2 "register_operand" "v")] UNSPEC_SUBS))
309 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
311 "vsubs<VI_char>s %0,%1,%2"
312 [(set_attr "type" "vecsimple")])
315 (define_insn "altivec_vavgu<VI_char>"
316 [(set (match_operand:VI 0 "register_operand" "=v")
317 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
318 (match_operand:VI 2 "register_operand" "v")] 44))]
320 "vavgu<VI_char> %0,%1,%2"
321 [(set_attr "type" "vecsimple")])
323 (define_insn "altivec_vavgs<VI_char>"
324 [(set (match_operand:VI 0 "register_operand" "=v")
325 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
326 (match_operand:VI 2 "register_operand" "v")] 45))]
328 "vavgs<VI_char> %0,%1,%2"
329 [(set_attr "type" "vecsimple")])
331 (define_insn "altivec_vcmpbfp"
332 [(set (match_operand:V4SI 0 "register_operand" "=v")
333 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
334 (match_operand:V4SF 2 "register_operand" "v")]
338 [(set_attr "type" "veccmp")])
340 (define_insn "altivec_vcmpequb"
341 [(set (match_operand:V16QI 0 "register_operand" "=v")
342 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
343 (match_operand:V16QI 2 "register_operand" "v")]
347 [(set_attr "type" "vecsimple")])
349 (define_insn "altivec_vcmpequh"
350 [(set (match_operand:V8HI 0 "register_operand" "=v")
351 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
352 (match_operand:V8HI 2 "register_operand" "v")]
356 [(set_attr "type" "vecsimple")])
358 (define_insn "altivec_vcmpequw"
359 [(set (match_operand:V4SI 0 "register_operand" "=v")
360 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
361 (match_operand:V4SI 2 "register_operand" "v")]
365 [(set_attr "type" "vecsimple")])
367 (define_insn "altivec_vcmpeqfp"
368 [(set (match_operand:V4SI 0 "register_operand" "=v")
369 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
370 (match_operand:V4SF 2 "register_operand" "v")]
374 [(set_attr "type" "veccmp")])
376 (define_insn "altivec_vcmpgefp"
377 [(set (match_operand:V4SI 0 "register_operand" "=v")
378 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
379 (match_operand:V4SF 2 "register_operand" "v")]
383 [(set_attr "type" "veccmp")])
385 (define_insn "altivec_vcmpgtub"
386 [(set (match_operand:V16QI 0 "register_operand" "=v")
387 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
388 (match_operand:V16QI 2 "register_operand" "v")]
392 [(set_attr "type" "vecsimple")])
394 (define_insn "altivec_vcmpgtsb"
395 [(set (match_operand:V16QI 0 "register_operand" "=v")
396 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
397 (match_operand:V16QI 2 "register_operand" "v")]
401 [(set_attr "type" "vecsimple")])
403 (define_insn "altivec_vcmpgtuh"
404 [(set (match_operand:V8HI 0 "register_operand" "=v")
405 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
406 (match_operand:V8HI 2 "register_operand" "v")]
410 [(set_attr "type" "vecsimple")])
412 (define_insn "altivec_vcmpgtsh"
413 [(set (match_operand:V8HI 0 "register_operand" "=v")
414 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
415 (match_operand:V8HI 2 "register_operand" "v")]
419 [(set_attr "type" "vecsimple")])
421 (define_insn "altivec_vcmpgtuw"
422 [(set (match_operand:V4SI 0 "register_operand" "=v")
423 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
424 (match_operand:V4SI 2 "register_operand" "v")]
428 [(set_attr "type" "vecsimple")])
430 (define_insn "altivec_vcmpgtsw"
431 [(set (match_operand:V4SI 0 "register_operand" "=v")
432 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
433 (match_operand:V4SI 2 "register_operand" "v")]
437 [(set_attr "type" "vecsimple")])
439 (define_insn "altivec_vcmpgtfp"
440 [(set (match_operand:V4SI 0 "register_operand" "=v")
441 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
442 (match_operand:V4SF 2 "register_operand" "v")]
446 [(set_attr "type" "veccmp")])
448 ;; Fused multiply add
449 (define_insn "altivec_vmaddfp"
450 [(set (match_operand:V4SF 0 "register_operand" "=v")
451 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
452 (match_operand:V4SF 2 "register_operand" "v"))
453 (match_operand:V4SF 3 "register_operand" "v")))]
455 "vmaddfp %0,%1,%2,%3"
456 [(set_attr "type" "vecfloat")])
458 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
460 (define_expand "mulv4sf3"
461 [(use (match_operand:V4SF 0 "register_operand" ""))
462 (use (match_operand:V4SF 1 "register_operand" ""))
463 (use (match_operand:V4SF 2 "register_operand" ""))]
464 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
469 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
470 neg0 = gen_reg_rtx (V4SFmode);
471 emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
472 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
474 /* Use the multiply-add. */
475 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
480 ;; 32 bit integer multiplication
481 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
482 ;; A_low = Operand_0 & 0xFFFF
483 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
484 ;; B_low = Operand_1 & 0xFFFF
485 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
487 ;; (define_insn "mulv4si3"
488 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
489 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
490 ;; (match_operand:V4SI 2 "register_operand" "v")))]
491 (define_expand "mulv4si3"
492 [(use (match_operand:V4SI 0 "register_operand" ""))
493 (use (match_operand:V4SI 1 "register_operand" ""))
494 (use (match_operand:V4SI 2 "register_operand" ""))]
507 zero = gen_reg_rtx (V4SImode);
508 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
510 sixteen = gen_reg_rtx (V4SImode);
511 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
513 swap = gen_reg_rtx (V4SImode);
514 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
516 one = gen_reg_rtx (V8HImode);
517 convert_move (one, operands[1], 0);
519 two = gen_reg_rtx (V8HImode);
520 convert_move (two, operands[2], 0);
522 small_swap = gen_reg_rtx (V8HImode);
523 convert_move (small_swap, swap, 0);
525 low_product = gen_reg_rtx (V4SImode);
526 emit_insn (gen_altivec_vmulouh (low_product, one, two));
528 high_product = gen_reg_rtx (V4SImode);
529 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
531 emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
533 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
539 ;; Fused multiply subtract
540 (define_insn "altivec_vnmsubfp"
541 [(set (match_operand:V4SF 0 "register_operand" "=v")
542 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
543 (match_operand:V4SF 2 "register_operand" "v"))
544 (match_operand:V4SF 3 "register_operand" "v"))))]
546 "vnmsubfp %0,%1,%2,%3"
547 [(set_attr "type" "vecfloat")])
549 (define_insn "altivec_vmsumu<VI_char>m"
550 [(set (match_operand:V4SI 0 "register_operand" "=v")
551 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
552 (match_operand:VIshort 2 "register_operand" "v")
553 (match_operand:V4SI 3 "register_operand" "v")] 65))]
555 "vmsumu<VI_char>m %0,%1,%2,%3"
556 [(set_attr "type" "veccomplex")])
558 (define_insn "altivec_vmsumm<VI_char>m"
559 [(set (match_operand:V4SI 0 "register_operand" "=v")
560 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
561 (match_operand:VIshort 2 "register_operand" "v")
562 (match_operand:V4SI 3 "register_operand" "v")] 66))]
564 "vmsumm<VI_char>m %0,%1,%2,%3"
565 [(set_attr "type" "veccomplex")])
567 (define_insn "altivec_vmsumshm"
568 [(set (match_operand:V4SI 0 "register_operand" "=v")
569 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
570 (match_operand:V8HI 2 "register_operand" "v")
571 (match_operand:V4SI 3 "register_operand" "v")] 68))]
573 "vmsumshm %0,%1,%2,%3"
574 [(set_attr "type" "veccomplex")])
576 (define_insn "altivec_vmsumuhs"
577 [(set (match_operand:V4SI 0 "register_operand" "=v")
578 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
579 (match_operand:V8HI 2 "register_operand" "v")
580 (match_operand:V4SI 3 "register_operand" "v")] 69))
581 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
583 "vmsumuhs %0,%1,%2,%3"
584 [(set_attr "type" "veccomplex")])
586 (define_insn "altivec_vmsumshs"
587 [(set (match_operand:V4SI 0 "register_operand" "=v")
588 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
589 (match_operand:V8HI 2 "register_operand" "v")
590 (match_operand:V4SI 3 "register_operand" "v")] 70))
591 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
593 "vmsumshs %0,%1,%2,%3"
594 [(set_attr "type" "veccomplex")])
598 (define_insn "umax<mode>3"
599 [(set (match_operand:VI 0 "register_operand" "=v")
600 (umax:VI (match_operand:VI 1 "register_operand" "v")
601 (match_operand:VI 2 "register_operand" "v")))]
603 "vmaxu<VI_char> %0,%1,%2"
604 [(set_attr "type" "vecsimple")])
606 (define_insn "smax<mode>3"
607 [(set (match_operand:VI 0 "register_operand" "=v")
608 (smax:VI (match_operand:VI 1 "register_operand" "v")
609 (match_operand:VI 2 "register_operand" "v")))]
611 "vmaxs<VI_char> %0,%1,%2"
612 [(set_attr "type" "vecsimple")])
614 (define_insn "smaxv4sf3"
615 [(set (match_operand:V4SF 0 "register_operand" "=v")
616 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
617 (match_operand:V4SF 2 "register_operand" "v")))]
620 [(set_attr "type" "veccmp")])
622 (define_insn "umin<mode>3"
623 [(set (match_operand:VI 0 "register_operand" "=v")
624 (umin:VI (match_operand:VI 1 "register_operand" "v")
625 (match_operand:VI 2 "register_operand" "v")))]
627 "vminu<VI_char> %0,%1,%2"
628 [(set_attr "type" "vecsimple")])
630 (define_insn "smin<mode>3"
631 [(set (match_operand:VI 0 "register_operand" "=v")
632 (smin:VI (match_operand:VI 1 "register_operand" "v")
633 (match_operand:VI 2 "register_operand" "v")))]
635 "vmins<VI_char> %0,%1,%2"
636 [(set_attr "type" "vecsimple")])
638 (define_insn "sminv4sf3"
639 [(set (match_operand:V4SF 0 "register_operand" "=v")
640 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
641 (match_operand:V4SF 2 "register_operand" "v")))]
644 [(set_attr "type" "veccmp")])
646 (define_insn "altivec_vmhaddshs"
647 [(set (match_operand:V8HI 0 "register_operand" "=v")
648 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
649 (match_operand:V8HI 2 "register_operand" "v")
650 (match_operand:V8HI 3 "register_operand" "v")] 71))
651 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
653 "vmhaddshs %0,%1,%2,%3"
654 [(set_attr "type" "veccomplex")])
655 (define_insn "altivec_vmhraddshs"
656 [(set (match_operand:V8HI 0 "register_operand" "=v")
657 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
658 (match_operand:V8HI 2 "register_operand" "v")
659 (match_operand:V8HI 3 "register_operand" "v")] 72))
660 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
662 "vmhraddshs %0,%1,%2,%3"
663 [(set_attr "type" "veccomplex")])
664 (define_insn "altivec_vmladduhm"
665 [(set (match_operand:V8HI 0 "register_operand" "=v")
666 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
667 (match_operand:V8HI 2 "register_operand" "v")
668 (match_operand:V8HI 3 "register_operand" "v")] 73))]
670 "vmladduhm %0,%1,%2,%3"
671 [(set_attr "type" "veccomplex")])
673 (define_insn "altivec_vmrghb"
674 [(set (match_operand:V16QI 0 "register_operand" "=v")
675 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
676 (parallel [(const_int 0)
692 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
693 (parallel [(const_int 8)
712 [(set_attr "type" "vecperm")])
714 (define_insn "altivec_vmrghh"
715 [(set (match_operand:V8HI 0 "register_operand" "=v")
716 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
717 (parallel [(const_int 0)
725 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
726 (parallel [(const_int 4)
737 [(set_attr "type" "vecperm")])
739 (define_insn "altivec_vmrghw"
740 [(set (match_operand:V4SI 0 "register_operand" "=v")
741 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
742 (parallel [(const_int 0)
746 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
747 (parallel [(const_int 2)
754 [(set_attr "type" "vecperm")])
756 (define_insn "altivec_vmrglb"
757 [(set (match_operand:V16QI 0 "register_operand" "=v")
758 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
759 (parallel [(const_int 8)
775 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
776 (parallel [(const_int 0)
795 [(set_attr "type" "vecperm")])
797 (define_insn "altivec_vmrglh"
798 [(set (match_operand:V8HI 0 "register_operand" "=v")
799 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
800 (parallel [(const_int 4)
808 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
809 (parallel [(const_int 0)
820 [(set_attr "type" "vecperm")])
822 (define_insn "altivec_vmrglw"
823 [(set (match_operand:V4SI 0 "register_operand" "=v")
824 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
825 (parallel [(const_int 2)
829 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
830 (parallel [(const_int 0)
837 [(set_attr "type" "vecperm")])
839 (define_insn "altivec_vmuleub"
840 [(set (match_operand:V8HI 0 "register_operand" "=v")
841 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
842 (match_operand:V16QI 2 "register_operand" "v")] 83))]
845 [(set_attr "type" "veccomplex")])
847 (define_insn "altivec_vmulesb"
848 [(set (match_operand:V8HI 0 "register_operand" "=v")
849 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
850 (match_operand:V16QI 2 "register_operand" "v")] 84))]
853 [(set_attr "type" "veccomplex")])
855 (define_insn "altivec_vmuleuh"
856 [(set (match_operand:V4SI 0 "register_operand" "=v")
857 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
858 (match_operand:V8HI 2 "register_operand" "v")] 85))]
861 [(set_attr "type" "veccomplex")])
863 (define_insn "altivec_vmulesh"
864 [(set (match_operand:V4SI 0 "register_operand" "=v")
865 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
866 (match_operand:V8HI 2 "register_operand" "v")] 86))]
869 [(set_attr "type" "veccomplex")])
871 (define_insn "altivec_vmuloub"
872 [(set (match_operand:V8HI 0 "register_operand" "=v")
873 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
874 (match_operand:V16QI 2 "register_operand" "v")] 87))]
877 [(set_attr "type" "veccomplex")])
879 (define_insn "altivec_vmulosb"
880 [(set (match_operand:V8HI 0 "register_operand" "=v")
881 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
882 (match_operand:V16QI 2 "register_operand" "v")] 88))]
885 [(set_attr "type" "veccomplex")])
887 (define_insn "altivec_vmulouh"
888 [(set (match_operand:V4SI 0 "register_operand" "=v")
889 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
890 (match_operand:V8HI 2 "register_operand" "v")] 89))]
893 [(set_attr "type" "veccomplex")])
895 (define_insn "altivec_vmulosh"
896 [(set (match_operand:V4SI 0 "register_operand" "=v")
897 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
898 (match_operand:V8HI 2 "register_operand" "v")] 90))]
901 [(set_attr "type" "veccomplex")])
906 (define_insn "and<mode>3"
907 [(set (match_operand:VI 0 "register_operand" "=v")
908 (and:VI (match_operand:VI 1 "register_operand" "v")
909 (match_operand:VI 2 "register_operand" "v")))]
912 [(set_attr "type" "vecsimple")])
914 (define_insn "ior<mode>3"
915 [(set (match_operand:VI 0 "register_operand" "=v")
916 (ior:VI (match_operand:VI 1 "register_operand" "v")
917 (match_operand:VI 2 "register_operand" "v")))]
920 [(set_attr "type" "vecsimple")])
922 (define_insn "xor<mode>3"
923 [(set (match_operand:VI 0 "register_operand" "=v")
924 (xor:VI (match_operand:VI 1 "register_operand" "v")
925 (match_operand:VI 2 "register_operand" "v")))]
928 [(set_attr "type" "vecsimple")])
930 (define_insn "one_cmpl<mode>2"
931 [(set (match_operand:VI 0 "register_operand" "=v")
932 (not:VI (match_operand:VI 1 "register_operand" "v")))]
935 [(set_attr "type" "vecsimple")])
937 (define_insn "altivec_nor<mode>3"
938 [(set (match_operand:VI 0 "register_operand" "=v")
939 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
940 (match_operand:VI 2 "register_operand" "v"))))]
943 [(set_attr "type" "vecsimple")])
945 (define_insn "andc<mode>3"
946 [(set (match_operand:VI 0 "register_operand" "=v")
947 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
948 (match_operand:VI 1 "register_operand" "v")))]
951 [(set_attr "type" "vecsimple")])
953 (define_insn "*andc3_v4sf"
954 [(set (match_operand:V4SF 0 "register_operand" "=v")
955 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
956 (match_operand:V4SF 1 "register_operand" "v")))]
959 [(set_attr "type" "vecsimple")])
961 (define_insn "altivec_vpkuhum"
962 [(set (match_operand:V16QI 0 "register_operand" "=v")
963 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
964 (match_operand:V8HI 2 "register_operand" "v")] 93))]
967 [(set_attr "type" "vecperm")])
969 (define_insn "altivec_vpkuwum"
970 [(set (match_operand:V8HI 0 "register_operand" "=v")
971 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
972 (match_operand:V4SI 2 "register_operand" "v")] 94))]
975 [(set_attr "type" "vecperm")])
977 (define_insn "altivec_vpkpx"
978 [(set (match_operand:V8HI 0 "register_operand" "=v")
979 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
980 (match_operand:V4SI 2 "register_operand" "v")] 95))]
983 [(set_attr "type" "vecperm")])
985 (define_insn "altivec_vpkuhss"
986 [(set (match_operand:V16QI 0 "register_operand" "=v")
987 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
988 (match_operand:V8HI 2 "register_operand" "v")] 96))
989 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
992 [(set_attr "type" "vecperm")])
994 (define_insn "altivec_vpkshss"
995 [(set (match_operand:V16QI 0 "register_operand" "=v")
996 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
997 (match_operand:V8HI 2 "register_operand" "v")] 97))
998 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1001 [(set_attr "type" "vecperm")])
1003 (define_insn "altivec_vpkuwss"
1004 [(set (match_operand:V8HI 0 "register_operand" "=v")
1005 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1006 (match_operand:V4SI 2 "register_operand" "v")] 98))
1007 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1010 [(set_attr "type" "vecperm")])
1012 (define_insn "altivec_vpkswss"
1013 [(set (match_operand:V8HI 0 "register_operand" "=v")
1014 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1015 (match_operand:V4SI 2 "register_operand" "v")] 99))
1016 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1019 [(set_attr "type" "vecperm")])
1021 (define_insn "altivec_vpkuhus"
1022 [(set (match_operand:V16QI 0 "register_operand" "=v")
1023 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1024 (match_operand:V8HI 2 "register_operand" "v")] 100))
1025 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1028 [(set_attr "type" "vecperm")])
1030 (define_insn "altivec_vpkshus"
1031 [(set (match_operand:V16QI 0 "register_operand" "=v")
1032 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1033 (match_operand:V8HI 2 "register_operand" "v")] 101))
1034 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1037 [(set_attr "type" "vecperm")])
1039 (define_insn "altivec_vpkuwus"
1040 [(set (match_operand:V8HI 0 "register_operand" "=v")
1041 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1042 (match_operand:V4SI 2 "register_operand" "v")] 102))
1043 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1046 [(set_attr "type" "vecperm")])
1048 (define_insn "altivec_vpkswus"
1049 [(set (match_operand:V8HI 0 "register_operand" "=v")
1050 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1051 (match_operand:V4SI 2 "register_operand" "v")] 103))
1052 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1055 [(set_attr "type" "vecperm")])
1057 (define_insn "altivec_vrl<VI_char>"
1058 [(set (match_operand:VI 0 "register_operand" "=v")
1059 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1060 (match_operand:VI 2 "register_operand" "v")] 104))]
1062 "vrl<VI_char> %0,%1,%2"
1063 [(set_attr "type" "vecsimple")])
1065 (define_insn "altivec_vsl<VI_char>"
1066 [(set (match_operand:VI 0 "register_operand" "=v")
1067 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1068 (match_operand:VI 2 "register_operand" "v")] 107))]
1070 "vsl<VI_char> %0,%1,%2"
1071 [(set_attr "type" "vecsimple")])
1073 (define_insn "altivec_vslw_v4sf"
1074 [(set (match_operand:V4SF 0 "register_operand" "=v")
1075 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1076 (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VSLW))]
1079 [(set_attr "type" "vecsimple")])
1081 (define_insn "altivec_vsl"
1082 [(set (match_operand:V4SI 0 "register_operand" "=v")
1083 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1084 (match_operand:V4SI 2 "register_operand" "v")] 110))]
1087 [(set_attr "type" "vecperm")])
1089 (define_insn "altivec_vslo"
1090 [(set (match_operand:V4SI 0 "register_operand" "=v")
1091 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1092 (match_operand:V4SI 2 "register_operand" "v")] 111))]
1095 [(set_attr "type" "vecperm")])
1097 (define_insn "lshr<mode>3"
1098 [(set (match_operand:VI 0 "register_operand" "=v")
1099 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1100 (match_operand:VI 2 "register_operand" "v") ))]
1102 "vsr<VI_char> %0,%1,%2"
1103 [(set_attr "type" "vecsimple")])
1105 (define_insn "ashr<mode>3"
1106 [(set (match_operand:VI 0 "register_operand" "=v")
1107 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1108 (match_operand:VI 2 "register_operand" "v") ))]
1110 "vsra<VI_char> %0,%1,%2"
1111 [(set_attr "type" "vecsimple")])
1113 (define_insn "altivec_vsr"
1114 [(set (match_operand:V4SI 0 "register_operand" "=v")
1115 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1116 (match_operand:V4SI 2 "register_operand" "v")] 118))]
1119 [(set_attr "type" "vecperm")])
1121 (define_insn "altivec_vsro"
1122 [(set (match_operand:V4SI 0 "register_operand" "=v")
1123 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1124 (match_operand:V4SI 2 "register_operand" "v")] 119))]
1127 [(set_attr "type" "vecperm")])
1129 (define_insn "altivec_vsum4ubs"
1130 [(set (match_operand:V4SI 0 "register_operand" "=v")
1131 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1132 (match_operand:V4SI 2 "register_operand" "v")] 131))
1133 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1136 [(set_attr "type" "veccomplex")])
1138 (define_insn "altivec_vsum4s<VI_char>s"
1139 [(set (match_operand:V4SI 0 "register_operand" "=v")
1140 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1141 (match_operand:V4SI 2 "register_operand" "v")] 132))
1142 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1144 "vsum4s<VI_char>s %0,%1,%2"
1145 [(set_attr "type" "veccomplex")])
1147 (define_insn "altivec_vsum2sws"
1148 [(set (match_operand:V4SI 0 "register_operand" "=v")
1149 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1150 (match_operand:V4SI 2 "register_operand" "v")] 134))
1151 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1154 [(set_attr "type" "veccomplex")])
1156 (define_insn "altivec_vsumsws"
1157 [(set (match_operand:V4SI 0 "register_operand" "=v")
1158 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1159 (match_operand:V4SI 2 "register_operand" "v")] 135))
1160 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1163 [(set_attr "type" "veccomplex")])
1165 (define_insn "altivec_vspltb"
1166 [(set (match_operand:V16QI 0 "register_operand" "=v")
1167 (vec_duplicate:V16QI
1168 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1170 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1173 [(set_attr "type" "vecperm")])
1175 (define_insn "altivec_vsplth"
1176 [(set (match_operand:V8HI 0 "register_operand" "=v")
1178 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1180 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1183 [(set_attr "type" "vecperm")])
1185 (define_insn "altivec_vspltw"
1186 [(set (match_operand:V4SI 0 "register_operand" "=v")
1188 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1190 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1193 [(set_attr "type" "vecperm")])
1195 (define_insn "altivec_vspltis<VI_char>"
1196 [(set (match_operand:VI 0 "register_operand" "=v")
1198 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1200 "vspltis<VI_char> %0,%1"
1201 [(set_attr "type" "vecperm")])
1203 (define_insn "altivec_vspltisw_v4sf"
1204 [(set (match_operand:V4SF 0 "register_operand" "=v")
1206 (float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))]
1209 [(set_attr "type" "vecperm")])
1211 (define_insn "ftruncv4sf2"
1212 [(set (match_operand:V4SF 0 "register_operand" "=v")
1213 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1216 [(set_attr "type" "vecfloat")])
1218 (define_insn "altivec_vperm_v4sf"
1219 [(set (match_operand:V4SF 0 "register_operand" "=v")
1220 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1221 (match_operand:V4SF 2 "register_operand" "v")
1222 (match_operand:V16QI 3 "register_operand" "v")] 145))]
1225 [(set_attr "type" "vecperm")])
1227 (define_insn "altivec_vperm_<mode>"
1228 [(set (match_operand:VI 0 "register_operand" "=v")
1229 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1230 (match_operand:VI 2 "register_operand" "v")
1231 (match_operand:V16QI 3 "register_operand" "v")] 144))]
1234 [(set_attr "type" "vecperm")])
1236 (define_insn "altivec_vrfip"
1237 [(set (match_operand:V4SF 0 "register_operand" "=v")
1238 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1241 [(set_attr "type" "vecfloat")])
1243 (define_insn "altivec_vrfin"
1244 [(set (match_operand:V4SF 0 "register_operand" "=v")
1245 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1248 [(set_attr "type" "vecfloat")])
1250 (define_insn "altivec_vrfim"
1251 [(set (match_operand:V4SF 0 "register_operand" "=v")
1252 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1255 [(set_attr "type" "vecfloat")])
1257 (define_insn "altivec_vcfux"
1258 [(set (match_operand:V4SF 0 "register_operand" "=v")
1259 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1260 (match_operand:QI 2 "immediate_operand" "i")] 151))]
1263 [(set_attr "type" "vecfloat")])
1265 (define_insn "altivec_vcfsx"
1266 [(set (match_operand:V4SF 0 "register_operand" "=v")
1267 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1268 (match_operand:QI 2 "immediate_operand" "i")] 152))]
1271 [(set_attr "type" "vecfloat")])
1273 (define_insn "altivec_vctuxs"
1274 [(set (match_operand:V4SI 0 "register_operand" "=v")
1275 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1276 (match_operand:QI 2 "immediate_operand" "i")] 153))
1277 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1280 [(set_attr "type" "vecfloat")])
1282 (define_insn "altivec_vctsxs"
1283 [(set (match_operand:V4SI 0 "register_operand" "=v")
1284 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1285 (match_operand:QI 2 "immediate_operand" "i")] 154))
1286 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1289 [(set_attr "type" "vecfloat")])
1291 (define_insn "altivec_vlogefp"
1292 [(set (match_operand:V4SF 0 "register_operand" "=v")
1293 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1296 [(set_attr "type" "vecfloat")])
1298 (define_insn "altivec_vexptefp"
1299 [(set (match_operand:V4SF 0 "register_operand" "=v")
1300 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1303 [(set_attr "type" "vecfloat")])
1305 (define_insn "altivec_vrsqrtefp"
1306 [(set (match_operand:V4SF 0 "register_operand" "=v")
1307 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1310 [(set_attr "type" "vecfloat")])
1312 (define_insn "altivec_vrefp"
1313 [(set (match_operand:V4SF 0 "register_operand" "=v")
1314 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1317 [(set_attr "type" "vecfloat")])
1319 (define_expand "vcondv4si"
1320 [(set (match_operand:V4SI 0 "register_operand" "=v")
1321 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1322 (match_operand:V4SI 2 "register_operand" "v")
1323 (match_operand:V4SI 3 "comparison_operator" "")
1324 (match_operand:V4SI 4 "register_operand" "v")
1325 (match_operand:V4SI 5 "register_operand" "v")
1326 ] UNSPEC_VCOND_V4SI))]
1330 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1331 operands[3], operands[4], operands[5]))
1338 (define_expand "vconduv4si"
1339 [(set (match_operand:V4SI 0 "register_operand" "=v")
1340 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1341 (match_operand:V4SI 2 "register_operand" "v")
1342 (match_operand:V4SI 3 "comparison_operator" "")
1343 (match_operand:V4SI 4 "register_operand" "v")
1344 (match_operand:V4SI 5 "register_operand" "v")
1345 ] UNSPEC_VCONDU_V4SI))]
1349 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1350 operands[3], operands[4], operands[5]))
1357 (define_expand "vcondv4sf"
1358 [(set (match_operand:V4SF 0 "register_operand" "=v")
1359 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1360 (match_operand:V4SF 2 "register_operand" "v")
1361 (match_operand:V4SF 3 "comparison_operator" "")
1362 (match_operand:V4SF 4 "register_operand" "v")
1363 (match_operand:V4SF 5 "register_operand" "v")
1364 ] UNSPEC_VCOND_V4SF))]
1368 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1369 operands[3], operands[4], operands[5]))
1376 (define_expand "vcondv8hi"
1377 [(set (match_operand:V4SF 0 "register_operand" "=v")
1378 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1379 (match_operand:V8HI 2 "register_operand" "v")
1380 (match_operand:V8HI 3 "comparison_operator" "")
1381 (match_operand:V8HI 4 "register_operand" "v")
1382 (match_operand:V8HI 5 "register_operand" "v")
1383 ] UNSPEC_VCOND_V8HI))]
1387 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1388 operands[3], operands[4], operands[5]))
1395 (define_expand "vconduv8hi"
1396 [(set (match_operand:V4SF 0 "register_operand" "=v")
1397 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1398 (match_operand:V8HI 2 "register_operand" "v")
1399 (match_operand:V8HI 3 "comparison_operator" "")
1400 (match_operand:V8HI 4 "register_operand" "v")
1401 (match_operand:V8HI 5 "register_operand" "v")
1402 ] UNSPEC_VCONDU_V8HI))]
1406 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1407 operands[3], operands[4], operands[5]))
1414 (define_expand "vcondv16qi"
1415 [(set (match_operand:V4SF 0 "register_operand" "=v")
1416 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1417 (match_operand:V16QI 2 "register_operand" "v")
1418 (match_operand:V16QI 3 "comparison_operator" "")
1419 (match_operand:V16QI 4 "register_operand" "v")
1420 (match_operand:V16QI 5 "register_operand" "v")
1421 ] UNSPEC_VCOND_V16QI))]
1425 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1426 operands[3], operands[4], operands[5]))
1433 (define_expand "vconduv16qi"
1434 [(set (match_operand:V4SF 0 "register_operand" "=v")
1435 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1436 (match_operand:V16QI 2 "register_operand" "v")
1437 (match_operand:V16QI 3 "comparison_operator" "")
1438 (match_operand:V16QI 4 "register_operand" "v")
1439 (match_operand:V16QI 5 "register_operand" "v")
1440 ] UNSPEC_VCONDU_V16QI))]
1444 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1445 operands[3], operands[4], operands[5]))
1453 (define_insn "altivec_vsel_v4si"
1454 [(set (match_operand:V4SI 0 "register_operand" "=v")
1455 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1456 (match_operand:V4SI 2 "register_operand" "v")
1457 (match_operand:V4SI 3 "register_operand" "v")]
1461 [(set_attr "type" "vecperm")])
1463 (define_insn "altivec_vsel_v4sf"
1464 [(set (match_operand:V4SF 0 "register_operand" "=v")
1465 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1466 (match_operand:V4SF 2 "register_operand" "v")
1467 (match_operand:V4SI 3 "register_operand" "v")]
1471 [(set_attr "type" "vecperm")])
1473 (define_insn "altivec_vsel_v8hi"
1474 [(set (match_operand:V8HI 0 "register_operand" "=v")
1475 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1476 (match_operand:V8HI 2 "register_operand" "v")
1477 (match_operand:V8HI 3 "register_operand" "v")]
1481 [(set_attr "type" "vecperm")])
1483 (define_insn "altivec_vsel_v16qi"
1484 [(set (match_operand:V16QI 0 "register_operand" "=v")
1485 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1486 (match_operand:V16QI 2 "register_operand" "v")
1487 (match_operand:V16QI 3 "register_operand" "v")]
1491 [(set_attr "type" "vecperm")])
1493 (define_insn "altivec_vsldoi_v4si"
1494 [(set (match_operand:V4SI 0 "register_operand" "=v")
1495 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1496 (match_operand:V4SI 2 "register_operand" "v")
1497 (match_operand:QI 3 "immediate_operand" "i")] 163))]
1499 "vsldoi %0,%1,%2,%3"
1500 [(set_attr "type" "vecperm")])
1502 (define_insn "altivec_vsldoi_v4sf"
1503 [(set (match_operand:V4SF 0 "register_operand" "=v")
1504 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1505 (match_operand:V4SF 2 "register_operand" "v")
1506 (match_operand:QI 3 "immediate_operand" "i")] 164))]
1508 "vsldoi %0,%1,%2,%3"
1509 [(set_attr "type" "vecperm")])
1511 (define_insn "altivec_vsldoi_v8hi"
1512 [(set (match_operand:V8HI 0 "register_operand" "=v")
1513 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1514 (match_operand:V8HI 2 "register_operand" "v")
1515 (match_operand:QI 3 "immediate_operand" "i")] 165))]
1517 "vsldoi %0,%1,%2,%3"
1518 [(set_attr "type" "vecperm")])
1520 (define_insn "altivec_vsldoi_v16qi"
1521 [(set (match_operand:V16QI 0 "register_operand" "=v")
1522 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1523 (match_operand:V16QI 2 "register_operand" "v")
1524 (match_operand:QI 3 "immediate_operand" "i")] 166))]
1526 "vsldoi %0,%1,%2,%3"
1527 [(set_attr "type" "vecperm")])
1529 (define_insn "altivec_vupkhsb"
1530 [(set (match_operand:V8HI 0 "register_operand" "=v")
1531 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1534 [(set_attr "type" "vecperm")])
1536 (define_insn "altivec_vupkhpx"
1537 [(set (match_operand:V4SI 0 "register_operand" "=v")
1538 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1541 [(set_attr "type" "vecperm")])
1543 (define_insn "altivec_vupkhsh"
1544 [(set (match_operand:V4SI 0 "register_operand" "=v")
1545 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1548 [(set_attr "type" "vecperm")])
1550 (define_insn "altivec_vupklsb"
1551 [(set (match_operand:V8HI 0 "register_operand" "=v")
1552 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1555 [(set_attr "type" "vecperm")])
1557 (define_insn "altivec_vupklpx"
1558 [(set (match_operand:V4SI 0 "register_operand" "=v")
1559 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1562 [(set_attr "type" "vecperm")])
1564 (define_insn "altivec_vupklsh"
1565 [(set (match_operand:V4SI 0 "register_operand" "=v")
1566 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1569 [(set_attr "type" "vecperm")])
1571 ;; AltiVec predicates.
1573 (define_expand "cr6_test_for_zero"
1574 [(set (match_operand:SI 0 "register_operand" "=r")
1580 (define_expand "cr6_test_for_zero_reverse"
1581 [(set (match_operand:SI 0 "register_operand" "=r")
1584 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1588 (define_expand "cr6_test_for_lt"
1589 [(set (match_operand:SI 0 "register_operand" "=r")
1595 (define_expand "cr6_test_for_lt_reverse"
1596 [(set (match_operand:SI 0 "register_operand" "=r")
1599 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1603 ;; We can get away with generating the opcode on the fly (%3 below)
1604 ;; because all the predicates have the same scheduling parameters.
1606 (define_insn "altivec_predicate_v4sf"
1608 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1609 (match_operand:V4SF 2 "register_operand" "v")
1610 (match_operand 3 "any_operand" "")] 174))
1611 (clobber (match_scratch:V4SF 0 "=v"))]
1614 [(set_attr "type" "veccmp")])
1616 (define_insn "altivec_predicate_<mode>"
1618 (unspec:CC [(match_operand:VI 1 "register_operand" "v")
1619 (match_operand:VI 2 "register_operand" "v")
1620 (match_operand 3 "any_operand" "")] 173))
1621 (clobber (match_scratch:VI 0 "=v"))]
1624 [(set_attr "type" "veccmp")])
1626 (define_insn "altivec_mtvscr"
1629 [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1632 [(set_attr "type" "vecsimple")])
1634 (define_insn "altivec_mfvscr"
1635 [(set (match_operand:V8HI 0 "register_operand" "=v")
1636 (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1639 [(set_attr "type" "vecsimple")])
1641 (define_insn "altivec_dssall"
1642 [(unspec_volatile [(const_int 0)] 188)]
1645 [(set_attr "type" "vecsimple")])
1647 (define_insn "altivec_dss"
1648 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1651 [(set_attr "type" "vecsimple")])
1653 (define_insn "altivec_dst"
1654 [(unspec [(match_operand 0 "register_operand" "b")
1655 (match_operand:SI 1 "register_operand" "r")
1656 (match_operand:QI 2 "immediate_operand" "i")] 190)]
1657 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1659 [(set_attr "type" "vecsimple")])
1661 (define_insn "altivec_dstt"
1662 [(unspec [(match_operand 0 "register_operand" "b")
1663 (match_operand:SI 1 "register_operand" "r")
1664 (match_operand:QI 2 "immediate_operand" "i")] 191)]
1665 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1667 [(set_attr "type" "vecsimple")])
1669 (define_insn "altivec_dstst"
1670 [(unspec [(match_operand 0 "register_operand" "b")
1671 (match_operand:SI 1 "register_operand" "r")
1672 (match_operand:QI 2 "immediate_operand" "i")] 192)]
1673 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1675 [(set_attr "type" "vecsimple")])
1677 (define_insn "altivec_dststt"
1678 [(unspec [(match_operand 0 "register_operand" "b")
1679 (match_operand:SI 1 "register_operand" "r")
1680 (match_operand:QI 2 "immediate_operand" "i")] 193)]
1681 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1683 [(set_attr "type" "vecsimple")])
1685 (define_insn "altivec_lvsl"
1686 [(set (match_operand:V16QI 0 "register_operand" "=v")
1687 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1690 [(set_attr "type" "vecload")])
1692 (define_insn "altivec_lvsr"
1693 [(set (match_operand:V16QI 0 "register_operand" "=v")
1694 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1697 [(set_attr "type" "vecload")])
1699 (define_expand "build_vector_mask_for_load"
1700 [(set (match_operand:V16QI 0 "register_operand" "=v")
1701 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1708 gcc_assert (GET_CODE (operands[1]) == MEM);
1710 addr = XEXP (operands[1], 0);
1711 temp = gen_reg_rtx (GET_MODE (addr));
1712 emit_insn (gen_rtx_SET (VOIDmode, temp,
1713 gen_rtx_NEG (GET_MODE (addr), addr)));
1714 emit_insn (gen_altivec_lvsr (operands[0],
1715 gen_rtx_MEM (GET_MODE (operands[1]), temp)));
1719 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1720 ;; identical rtl but different instructions-- and gcc gets confused.
1722 (define_insn "altivec_lve<VI_char>x"
1724 [(set (match_operand:VI 0 "register_operand" "=v")
1725 (match_operand:VI 1 "memory_operand" "m"))
1726 (unspec [(const_int 0)] 196)])]
1728 "lve<VI_char>x %0,%y1"
1729 [(set_attr "type" "vecload")])
1731 (define_insn "altivec_lvxl"
1733 [(set (match_operand:V4SI 0 "register_operand" "=v")
1734 (match_operand:V4SI 1 "memory_operand" "m"))
1735 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1738 [(set_attr "type" "vecload")])
1740 (define_insn "altivec_lvx"
1741 [(set (match_operand:V4SI 0 "register_operand" "=v")
1742 (match_operand:V4SI 1 "memory_operand" "m"))]
1745 [(set_attr "type" "vecload")])
1747 (define_insn "altivec_stvx"
1749 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1750 (match_operand:V4SI 1 "register_operand" "v"))
1751 (unspec [(const_int 0)] 201)])]
1754 [(set_attr "type" "vecstore")])
1756 (define_insn "altivec_stvxl"
1758 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1759 (match_operand:V4SI 1 "register_operand" "v"))
1760 (unspec [(const_int 0)] 202)])]
1763 [(set_attr "type" "vecstore")])
1765 (define_insn "altivec_stve<VI_char>x"
1767 [(set (match_operand:VI 0 "memory_operand" "=m")
1768 (match_operand:VI 1 "register_operand" "v"))
1769 (unspec [(const_int 0)] 203)])]
1771 "stve<VI_char>x %1,%y0"
1772 [(set_attr "type" "vecstore")])
1775 ;; vspltis? SCRATCH0,0
1776 ;; vsubu?m SCRATCH2,SCRATCH1,%1
1777 ;; vmaxs? %0,%1,SCRATCH2"
1778 (define_expand "abs<mode>2"
1779 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1781 (minus:VI (match_dup 2)
1782 (match_operand:VI 1 "register_operand" "v")))
1783 (set (match_operand:VI 0 "register_operand" "=v")
1784 (smax:VI (match_dup 1) (match_dup 3)))]
1787 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1788 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1792 ;; vspltisw SCRATCH1,-1
1793 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
1794 ;; vandc %0,%1,SCRATCH2
1795 (define_expand "absv4sf2"
1797 (vec_duplicate:V4SF (float:SF (const_int -1))))
1799 (unspec:V4SF [(match_dup 2) (match_dup 2)] UNSPEC_VSLW))
1800 (set (match_operand:V4SF 0 "register_operand" "=v")
1801 (and:V4SF (not:V4SF (match_dup 3))
1802 (match_operand:V4SF 1 "register_operand" "v")))]
1805 operands[2] = gen_reg_rtx (V4SFmode);
1806 operands[3] = gen_reg_rtx (V4SFmode);
1810 ;; vspltis? SCRATCH0,0
1811 ;; vsubs?s SCRATCH2,SCRATCH1,%1
1812 ;; vmaxs? %0,%1,SCRATCH2"
1813 (define_expand "altivec_abss_<mode>"
1814 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1815 (parallel [(set (match_dup 3)
1816 (unspec:VI [(match_dup 2)
1817 (match_operand:VI 1 "register_operand" "v")]
1819 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
1820 (set (match_operand:VI 0 "register_operand" "=v")
1821 (smax:VI (match_dup 1) (match_dup 3)))]
1824 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1825 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1828 ;; Vector shift left in bits. Currently supported ony for shift
1829 ;; amounts that can be expressed as byte shifts (divisible by 8).
1830 ;; General shift amounts can be supported using vslo + vsl. We're
1831 ;; not expecting to see these yet (the vectorizer currently
1832 ;; generates only shifts divisible by byte_size).
1833 (define_expand "vec_shl_<mode>"
1834 [(set (match_operand:V 0 "register_operand" "=v")
1835 (unspec:V [(match_operand:V 1 "register_operand" "v")
1836 (match_operand:QI 2 "reg_or_short_operand" "")] 219 ))]
1840 rtx bitshift = operands[2];
1841 rtx byteshift = gen_reg_rtx (QImode);
1842 HOST_WIDE_INT bitshift_val;
1843 HOST_WIDE_INT byteshift_val;
1845 if (! CONSTANT_P (bitshift))
1847 bitshift_val = INTVAL (bitshift);
1848 if (bitshift_val & 0x7)
1850 byteshift_val = bitshift_val >> 3;
1851 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
1852 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
1857 ;; Vector shift left in bits. Currently supported ony for shift
1858 ;; amounts that can be expressed as byte shifts (divisible by 8).
1859 ;; General shift amounts can be supported using vsro + vsr. We're
1860 ;; not expecting to see these yet (the vectorizer currently
1861 ;; generates only shifts divisible by byte_size).
1862 (define_expand "vec_shr_<mode>"
1863 [(set (match_operand:V 0 "register_operand" "=v")
1864 (unspec:V [(match_operand:V 1 "register_operand" "v")
1865 (match_operand:QI 2 "reg_or_short_operand" "")] 219 ))]
1869 rtx bitshift = operands[2];
1870 rtx byteshift = gen_reg_rtx (QImode);
1871 HOST_WIDE_INT bitshift_val;
1872 HOST_WIDE_INT byteshift_val;
1874 if (! CONSTANT_P (bitshift))
1876 bitshift_val = INTVAL (bitshift);
1877 if (bitshift_val & 0x7)
1879 byteshift_val = 16 - (bitshift_val >> 3);
1880 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
1881 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
1886 (define_insn "altivec_vsumsws_nomode"
1887 [(set (match_operand 0 "register_operand" "=v")
1888 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1889 (match_operand:V4SI 2 "register_operand" "v")] 135))
1890 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1893 [(set_attr "type" "veccomplex")])
1895 (define_expand "reduc_splus_<mode>"
1896 [(set (match_operand:VIshort 0 "register_operand" "=v")
1897 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")] 217))]
1901 rtx vzero = gen_reg_rtx (V4SImode);
1902 rtx vtmp1 = gen_reg_rtx (V4SImode);
1904 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1905 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
1906 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1910 (define_expand "reduc_uplus_v16qi"
1911 [(set (match_operand:V16QI 0 "register_operand" "=v")
1912 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 217))]
1916 rtx vzero = gen_reg_rtx (V4SImode);
1917 rtx vtmp1 = gen_reg_rtx (V4SImode);
1919 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1920 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
1921 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1925 (define_insn "vec_realign_load_v4sf"
1926 [(set (match_operand:V4SF 0 "register_operand" "=v")
1927 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1928 (match_operand:V4SF 2 "register_operand" "v")
1929 (match_operand:V16QI 3 "register_operand" "v")] 216))]
1932 [(set_attr "type" "vecperm")])
1934 (define_insn "vec_realign_load_<mode>"
1935 [(set (match_operand:VI 0 "register_operand" "=v")
1936 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1937 (match_operand:VI 2 "register_operand" "v")
1938 (match_operand:V16QI 3 "register_operand" "v")] 215))]
1941 [(set_attr "type" "vecperm")])