2 ;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
20 ;; MA 02111-1307, USA.
23 [(UNSPEC_VSPLTISW 141)
28 ;; Generic LVX load instruction.
29 (define_insn "altivec_lvx_4si"
30 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
31 (match_operand:V4SI 1 "memory_operand" "m"))]
34 [(set_attr "type" "vecload")])
36 (define_insn "altivec_lvx_8hi"
37 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
38 (match_operand:V8HI 1 "memory_operand" "m"))]
41 [(set_attr "type" "vecload")])
43 (define_insn "altivec_lvx_16qi"
44 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
45 (match_operand:V16QI 1 "memory_operand" "m"))]
48 [(set_attr "type" "vecload")])
50 (define_insn "altivec_lvx_4sf"
51 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
52 (match_operand:V4SF 1 "memory_operand" "m"))]
55 [(set_attr "type" "vecload")])
57 ;; Generic STVX store instruction.
58 (define_insn "altivec_stvx_4si"
59 [(set (match_operand:V4SI 0 "memory_operand" "=m")
60 (match_operand:V4SI 1 "altivec_register_operand" "v"))]
63 [(set_attr "type" "vecstore")])
65 (define_insn "altivec_stvx_8hi"
66 [(set (match_operand:V8HI 0 "memory_operand" "=m")
67 (match_operand:V8HI 1 "altivec_register_operand" "v"))]
70 [(set_attr "type" "vecstore")])
72 (define_insn "altivec_stvx_16qi"
73 [(set (match_operand:V16QI 0 "memory_operand" "=m")
74 (match_operand:V16QI 1 "altivec_register_operand" "v"))]
77 [(set_attr "type" "vecstore")])
79 (define_insn "altivec_stvx_4sf"
80 [(set (match_operand:V4SF 0 "memory_operand" "=m")
81 (match_operand:V4SF 1 "altivec_register_operand" "v"))]
84 [(set_attr "type" "vecstore")])
86 ;; Vector move instructions.
87 (define_expand "movv4si"
88 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
89 (match_operand:V4SI 1 "any_operand" ""))]
91 "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
93 (define_insn "*movv4si_internal"
94 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
95 (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
99 switch (which_alternative)
101 case 0: return \"stvx %1,%y0\";
102 case 1: return \"lvx %0,%y1\";
103 case 2: return \"vor %0,%1,%1\";
104 case 3: return \"#\";
105 case 4: return \"#\";
106 case 5: return \"#\";
107 case 6: return output_vec_const_move (operands);
111 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
114 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
115 (match_operand:V4SI 1 "input_operand" ""))]
116 "TARGET_ALTIVEC && reload_completed
117 && gpr_or_gpr_p (operands[0], operands[1])"
119 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
122 [(set (match_operand:V4SI 0 "altivec_register_operand" "")
123 (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
124 "TARGET_ALTIVEC && reload_completed"
126 (unspec:V4SI [(match_dup 3)] UNSPEC_VSPLTISW))
128 (plus:V4SI (match_dup 0)
131 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
133 (define_expand "movv8hi"
134 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
135 (match_operand:V8HI 1 "any_operand" ""))]
137 "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
139 (define_insn "*movv8hi_internal1"
140 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
141 (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
145 switch (which_alternative)
147 case 0: return \"stvx %1,%y0\";
148 case 1: return \"lvx %0,%y1\";
149 case 2: return \"vor %0,%1,%1\";
150 case 3: return \"#\";
151 case 4: return \"#\";
152 case 5: return \"#\";
153 case 6: return output_vec_const_move (operands);
157 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
160 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
161 (match_operand:V8HI 1 "input_operand" ""))]
162 "TARGET_ALTIVEC && reload_completed
163 && gpr_or_gpr_p (operands[0], operands[1])"
165 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
168 [(set (match_operand:V8HI 0 "altivec_register_operand" "")
169 (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
170 "TARGET_ALTIVEC && reload_completed"
172 (unspec:V8HI [(match_dup 3)] UNSPEC_VSPLTISH))
174 (plus:V8HI (match_dup 0)
177 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
179 (define_expand "movv16qi"
180 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
181 (match_operand:V16QI 1 "any_operand" ""))]
183 "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
185 (define_insn "*movv16qi_internal1"
186 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
187 (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
191 switch (which_alternative)
193 case 0: return \"stvx %1,%y0\";
194 case 1: return \"lvx %0,%y1\";
195 case 2: return \"vor %0,%1,%1\";
196 case 3: return \"#\";
197 case 4: return \"#\";
198 case 5: return \"#\";
199 case 6: return output_vec_const_move (operands);
203 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
206 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
207 (match_operand:V16QI 1 "input_operand" ""))]
208 "TARGET_ALTIVEC && reload_completed
209 && gpr_or_gpr_p (operands[0], operands[1])"
211 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
214 [(set (match_operand:V16QI 0 "altivec_register_operand" "")
215 (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
216 "TARGET_ALTIVEC && reload_completed"
218 (unspec:V16QI [(match_dup 3)] UNSPEC_VSPLTISB))
220 (plus:V16QI (match_dup 0)
223 { operands[3] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)) >> 1); }")
225 (define_expand "movv4sf"
226 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
227 (match_operand:V4SF 1 "any_operand" ""))]
229 "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
231 (define_insn "*movv4sf_internal1"
232 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
233 (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
237 switch (which_alternative)
239 case 0: return \"stvx %1,%y0\";
240 case 1: return \"lvx %0,%y1\";
241 case 2: return \"vor %0,%1,%1\";
242 case 3: return \"#\";
243 case 4: return \"#\";
244 case 5: return \"#\";
245 case 6: return output_vec_const_move (operands);
249 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
252 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
253 (match_operand:V4SF 1 "input_operand" ""))]
254 "TARGET_ALTIVEC && reload_completed
255 && gpr_or_gpr_p (operands[0], operands[1])"
257 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
259 (define_insn "get_vrsave_internal"
260 [(set (match_operand:SI 0 "register_operand" "=r")
261 (unspec:SI [(reg:SI 109)] 214))]
266 return \"mfspr %0,256\";
268 return \"mfvrsave %0\";
270 [(set_attr "type" "*")])
272 (define_insn "*set_vrsave_internal"
273 [(match_parallel 0 "vrsave_operation"
275 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
276 (reg:SI 109)] 30))])]
281 return \"mtspr 256,%1\";
283 return \"mtvrsave %1\";
285 [(set_attr "type" "*")])
287 ;; Simple binary operations.
289 (define_insn "addv16qi3"
290 [(set (match_operand:V16QI 0 "register_operand" "=v")
291 (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
292 (match_operand:V16QI 2 "register_operand" "v")))]
295 [(set_attr "type" "vecsimple")])
297 (define_insn "addv8hi3"
298 [(set (match_operand:V8HI 0 "register_operand" "=v")
299 (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
300 (match_operand:V8HI 2 "register_operand" "v")))]
303 [(set_attr "type" "vecsimple")])
305 (define_insn "addv4si3"
306 [(set (match_operand:V4SI 0 "register_operand" "=v")
307 (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
308 (match_operand:V4SI 2 "register_operand" "v")))]
311 [(set_attr "type" "vecsimple")])
313 (define_insn "addv4sf3"
314 [(set (match_operand:V4SF 0 "register_operand" "=v")
315 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
316 (match_operand:V4SF 2 "register_operand" "v")))]
319 [(set_attr "type" "vecfloat")])
321 (define_insn "altivec_vaddcuw"
322 [(set (match_operand:V4SI 0 "register_operand" "=v")
323 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
324 (match_operand:V4SI 2 "register_operand" "v")] 35))]
327 [(set_attr "type" "vecsimple")])
329 (define_insn "altivec_vaddubs"
330 [(set (match_operand:V16QI 0 "register_operand" "=v")
331 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
332 (match_operand:V16QI 2 "register_operand" "v")] 36))
333 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
336 [(set_attr "type" "vecsimple")])
338 (define_insn "altivec_vaddsbs"
339 [(set (match_operand:V16QI 0 "register_operand" "=v")
340 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
341 (match_operand:V16QI 2 "register_operand" "v")] 37))
342 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
345 [(set_attr "type" "vecsimple")])
347 (define_insn "altivec_vadduhs"
348 [(set (match_operand:V8HI 0 "register_operand" "=v")
349 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
350 (match_operand:V8HI 2 "register_operand" "v")] 38))
351 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
354 [(set_attr "type" "vecsimple")])
356 (define_insn "altivec_vaddshs"
357 [(set (match_operand:V8HI 0 "register_operand" "=v")
358 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
359 (match_operand:V8HI 2 "register_operand" "v")] 39))
360 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
363 [(set_attr "type" "vecsimple")])
365 (define_insn "altivec_vadduws"
366 [(set (match_operand:V4SI 0 "register_operand" "=v")
367 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
368 (match_operand:V4SI 2 "register_operand" "v")] 40))
369 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
372 [(set_attr "type" "vecsimple")])
374 (define_insn "altivec_vaddsws"
375 [(set (match_operand:V4SI 0 "register_operand" "=v")
376 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
377 (match_operand:V4SI 2 "register_operand" "v")] 41))
378 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
381 [(set_attr "type" "vecsimple")])
383 (define_insn "andv4si3"
384 [(set (match_operand:V4SI 0 "register_operand" "=v")
385 (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
386 (match_operand:V4SI 2 "register_operand" "v")))]
389 [(set_attr "type" "vecsimple")])
391 (define_insn "altivec_vandc"
392 [(set (match_operand:V4SI 0 "register_operand" "=v")
393 (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
394 (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
397 [(set_attr "type" "vecsimple")])
399 (define_insn "altivec_vavgub"
400 [(set (match_operand:V16QI 0 "register_operand" "=v")
401 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
402 (match_operand:V16QI 2 "register_operand" "v")] 44))]
405 [(set_attr "type" "vecsimple")])
407 (define_insn "altivec_vavgsb"
408 [(set (match_operand:V16QI 0 "register_operand" "=v")
409 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
410 (match_operand:V16QI 2 "register_operand" "v")] 45))]
413 [(set_attr "type" "vecsimple")])
415 (define_insn "altivec_vavguh"
416 [(set (match_operand:V8HI 0 "register_operand" "=v")
417 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
418 (match_operand:V8HI 2 "register_operand" "v")] 46))]
421 [(set_attr "type" "vecsimple")])
423 (define_insn "altivec_vavgsh"
424 [(set (match_operand:V8HI 0 "register_operand" "=v")
425 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
426 (match_operand:V8HI 2 "register_operand" "v")] 47))]
429 [(set_attr "type" "vecsimple")])
431 (define_insn "altivec_vavguw"
432 [(set (match_operand:V4SI 0 "register_operand" "=v")
433 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
434 (match_operand:V4SI 2 "register_operand" "v")] 48))]
437 [(set_attr "type" "vecsimple")])
439 (define_insn "altivec_vavgsw"
440 [(set (match_operand:V4SI 0 "register_operand" "=v")
441 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
442 (match_operand:V4SI 2 "register_operand" "v")] 49))]
445 [(set_attr "type" "vecsimple")])
447 (define_insn "altivec_vcmpbfp"
448 [(set (match_operand:V4SI 0 "register_operand" "=v")
449 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
450 (match_operand:V4SF 2 "register_operand" "v")] 50))]
453 [(set_attr "type" "veccmp")])
455 (define_insn "altivec_vcmpequb"
456 [(set (match_operand:V16QI 0 "register_operand" "=v")
457 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
458 (match_operand:V16QI 2 "register_operand" "v")] 51))]
461 [(set_attr "type" "vecsimple")])
463 (define_insn "altivec_vcmpequh"
464 [(set (match_operand:V8HI 0 "register_operand" "=v")
465 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
466 (match_operand:V8HI 2 "register_operand" "v")] 52))]
469 [(set_attr "type" "vecsimple")])
471 (define_insn "altivec_vcmpequw"
472 [(set (match_operand:V4SI 0 "register_operand" "=v")
473 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
474 (match_operand:V4SI 2 "register_operand" "v")] 53))]
477 [(set_attr "type" "vecsimple")])
479 (define_insn "altivec_vcmpeqfp"
480 [(set (match_operand:V4SI 0 "register_operand" "=v")
481 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
482 (match_operand:V4SF 2 "register_operand" "v")] 54))]
485 [(set_attr "type" "veccmp")])
487 (define_insn "altivec_vcmpgefp"
488 [(set (match_operand:V4SI 0 "register_operand" "=v")
489 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
490 (match_operand:V4SF 2 "register_operand" "v")] 55))]
493 [(set_attr "type" "veccmp")])
495 (define_insn "altivec_vcmpgtub"
496 [(set (match_operand:V16QI 0 "register_operand" "=v")
497 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
498 (match_operand:V16QI 2 "register_operand" "v")] 56))]
501 [(set_attr "type" "vecsimple")])
503 (define_insn "altivec_vcmpgtsb"
504 [(set (match_operand:V16QI 0 "register_operand" "=v")
505 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
506 (match_operand:V16QI 2 "register_operand" "v")] 57))]
509 [(set_attr "type" "vecsimple")])
511 (define_insn "altivec_vcmpgtuh"
512 [(set (match_operand:V8HI 0 "register_operand" "=v")
513 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
514 (match_operand:V8HI 2 "register_operand" "v")] 58))]
517 [(set_attr "type" "vecsimple")])
519 (define_insn "altivec_vcmpgtsh"
520 [(set (match_operand:V8HI 0 "register_operand" "=v")
521 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
522 (match_operand:V8HI 2 "register_operand" "v")] 59))]
525 [(set_attr "type" "vecsimple")])
527 (define_insn "altivec_vcmpgtuw"
528 [(set (match_operand:V4SI 0 "register_operand" "=v")
529 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
530 (match_operand:V4SI 2 "register_operand" "v")] 60))]
533 [(set_attr "type" "vecsimple")])
535 (define_insn "altivec_vcmpgtsw"
536 [(set (match_operand:V4SI 0 "register_operand" "=v")
537 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
538 (match_operand:V4SI 2 "register_operand" "v")] 61))]
541 [(set_attr "type" "vecsimple")])
543 (define_insn "altivec_vcmpgtfp"
544 [(set (match_operand:V4SI 0 "register_operand" "=v")
545 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
546 (match_operand:V4SF 2 "register_operand" "v")] 62))]
549 [(set_attr "type" "veccmp")])
551 ;; Fused multiply add
552 (define_insn "altivec_vmaddfp"
553 [(set (match_operand:V4SF 0 "register_operand" "=v")
554 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
555 (match_operand:V4SF 2 "register_operand" "v"))
556 (match_operand:V4SF 3 "register_operand" "v")))]
558 "vmaddfp %0,%1,%2,%3"
559 [(set_attr "type" "vecfloat")])
561 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
563 (define_expand "mulv4sf3"
564 [(use (match_operand:V4SF 0 "register_operand" ""))
565 (use (match_operand:V4SF 1 "register_operand" ""))
566 (use (match_operand:V4SF 2 "register_operand" ""))]
567 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
572 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
573 neg0 = gen_reg_rtx (V4SFmode);
574 emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
575 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
577 /* Use the multiply-add. */
578 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
583 ;; Fused multiply subtract
584 (define_insn "altivec_vnmsubfp"
585 [(set (match_operand:V4SF 0 "register_operand" "=v")
586 (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
587 (match_operand:V4SF 2 "register_operand" "v"))
588 (match_operand:V4SF 3 "register_operand" "v")))]
590 "vnmsubfp %0,%1,%2,%3"
591 [(set_attr "type" "vecfloat")])
594 (define_insn "altivec_vmsumubm"
595 [(set (match_operand:V4SI 0 "register_operand" "=v")
596 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
597 (match_operand:V16QI 2 "register_operand" "v")
598 (match_operand:V4SI 3 "register_operand" "v")] 65))]
600 "vmsumubm %0,%1,%2,%3"
601 [(set_attr "type" "veccomplex")])
603 (define_insn "altivec_vmsummbm"
604 [(set (match_operand:V4SI 0 "register_operand" "=v")
605 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
606 (match_operand:V16QI 2 "register_operand" "v")
607 (match_operand:V4SI 3 "register_operand" "v")] 66))]
609 "vmsummbm %0,%1,%2,%3"
610 [(set_attr "type" "veccomplex")])
612 (define_insn "altivec_vmsumuhm"
613 [(set (match_operand:V4SI 0 "register_operand" "=v")
614 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
615 (match_operand:V8HI 2 "register_operand" "v")
616 (match_operand:V4SI 3 "register_operand" "v")] 67))]
618 "vmsumuhm %0,%1,%2,%3"
619 [(set_attr "type" "veccomplex")])
621 (define_insn "altivec_vmsumshm"
622 [(set (match_operand:V4SI 0 "register_operand" "=v")
623 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
624 (match_operand:V8HI 2 "register_operand" "v")
625 (match_operand:V4SI 3 "register_operand" "v")] 68))]
627 "vmsumshm %0,%1,%2,%3"
628 [(set_attr "type" "veccomplex")])
630 (define_insn "altivec_vmsumuhs"
631 [(set (match_operand:V4SI 0 "register_operand" "=v")
632 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
633 (match_operand:V8HI 2 "register_operand" "v")
634 (match_operand:V4SI 3 "register_operand" "v")] 69))
635 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
637 "vmsumuhs %0,%1,%2,%3"
638 [(set_attr "type" "veccomplex")])
640 (define_insn "altivec_vmsumshs"
641 [(set (match_operand:V4SI 0 "register_operand" "=v")
642 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
643 (match_operand:V8HI 2 "register_operand" "v")
644 (match_operand:V4SI 3 "register_operand" "v")] 70))
645 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
647 "vmsumshs %0,%1,%2,%3"
648 [(set_attr "type" "veccomplex")])
650 (define_insn "umaxv16qi3"
651 [(set (match_operand:V16QI 0 "register_operand" "=v")
652 (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
653 (match_operand:V16QI 2 "register_operand" "v")))]
656 [(set_attr "type" "vecsimple")])
658 (define_insn "smaxv16qi3"
659 [(set (match_operand:V16QI 0 "register_operand" "=v")
660 (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
661 (match_operand:V16QI 2 "register_operand" "v")))]
664 [(set_attr "type" "vecsimple")])
666 (define_insn "umaxv8hi3"
667 [(set (match_operand:V8HI 0 "register_operand" "=v")
668 (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
669 (match_operand:V8HI 2 "register_operand" "v")))]
672 [(set_attr "type" "vecsimple")])
674 (define_insn "smaxv8hi3"
675 [(set (match_operand:V8HI 0 "register_operand" "=v")
676 (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
677 (match_operand:V8HI 2 "register_operand" "v")))]
680 [(set_attr "type" "vecsimple")])
682 (define_insn "umaxv4si3"
683 [(set (match_operand:V4SI 0 "register_operand" "=v")
684 (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
685 (match_operand:V4SI 2 "register_operand" "v")))]
688 [(set_attr "type" "vecsimple")])
690 (define_insn "smaxv4si3"
691 [(set (match_operand:V4SI 0 "register_operand" "=v")
692 (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
693 (match_operand:V4SI 2 "register_operand" "v")))]
696 [(set_attr "type" "vecsimple")])
698 (define_insn "smaxv4sf3"
699 [(set (match_operand:V4SF 0 "register_operand" "=v")
700 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
701 (match_operand:V4SF 2 "register_operand" "v")))]
704 [(set_attr "type" "veccmp")])
706 (define_insn "altivec_vmhaddshs"
707 [(set (match_operand:V8HI 0 "register_operand" "=v")
708 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
709 (match_operand:V8HI 2 "register_operand" "v")
710 (match_operand:V8HI 3 "register_operand" "v")] 71))
711 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
713 "vmhaddshs %0,%1,%2,%3"
714 [(set_attr "type" "veccomplex")])
715 (define_insn "altivec_vmhraddshs"
716 [(set (match_operand:V8HI 0 "register_operand" "=v")
717 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
718 (match_operand:V8HI 2 "register_operand" "v")
719 (match_operand:V8HI 3 "register_operand" "v")] 72))
720 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
722 "vmhraddshs %0,%1,%2,%3"
723 [(set_attr "type" "veccomplex")])
724 (define_insn "altivec_vmladduhm"
725 [(set (match_operand:V8HI 0 "register_operand" "=v")
726 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
727 (match_operand:V8HI 2 "register_operand" "v")
728 (match_operand:V8HI 3 "register_operand" "v")] 73))]
730 "vmladduhm %0,%1,%2,%3"
731 [(set_attr "type" "veccomplex")])
733 (define_insn "altivec_vmrghb"
734 [(set (match_operand:V16QI 0 "register_operand" "=v")
735 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
736 (parallel [(const_int 8)
752 (match_operand:V16QI 2 "register_operand" "v")
756 [(set_attr "type" "vecperm")])
758 (define_insn "altivec_vmrghh"
759 [(set (match_operand:V8HI 0 "register_operand" "=v")
760 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
761 (parallel [(const_int 4)
769 (match_operand:V8HI 2 "register_operand" "v")
773 [(set_attr "type" "vecperm")])
775 (define_insn "altivec_vmrghw"
776 [(set (match_operand:V4SI 0 "register_operand" "=v")
777 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
778 (parallel [(const_int 2)
782 (match_operand:V4SI 2 "register_operand" "v")
786 [(set_attr "type" "vecperm")])
788 (define_insn "altivec_vmrglb"
789 [(set (match_operand:V16QI 0 "register_operand" "=v")
790 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
791 (parallel [(const_int 0)
807 (match_operand:V16QI 1 "register_operand" "v")
811 [(set_attr "type" "vecperm")])
813 (define_insn "altivec_vmrglh"
814 [(set (match_operand:V8HI 0 "register_operand" "=v")
815 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
816 (parallel [(const_int 0)
824 (match_operand:V8HI 1 "register_operand" "v")
828 [(set_attr "type" "vecperm")])
830 (define_insn "altivec_vmrglw"
831 [(set (match_operand:V4SI 0 "register_operand" "=v")
832 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
833 (parallel [(const_int 0)
837 (match_operand:V4SI 1 "register_operand" "v")
841 [(set_attr "type" "vecperm")])
843 (define_insn "uminv16qi3"
844 [(set (match_operand:V16QI 0 "register_operand" "=v")
845 (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
846 (match_operand:V16QI 2 "register_operand" "v")))]
849 [(set_attr "type" "vecsimple")])
851 (define_insn "sminv16qi3"
852 [(set (match_operand:V16QI 0 "register_operand" "=v")
853 (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
854 (match_operand:V16QI 2 "register_operand" "v")))]
857 [(set_attr "type" "vecsimple")])
859 (define_insn "uminv8hi3"
860 [(set (match_operand:V8HI 0 "register_operand" "=v")
861 (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
862 (match_operand:V8HI 2 "register_operand" "v")))]
865 [(set_attr "type" "vecsimple")])
867 (define_insn "sminv8hi3"
868 [(set (match_operand:V8HI 0 "register_operand" "=v")
869 (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
870 (match_operand:V8HI 2 "register_operand" "v")))]
873 [(set_attr "type" "vecsimple")])
875 (define_insn "uminv4si3"
876 [(set (match_operand:V4SI 0 "register_operand" "=v")
877 (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
878 (match_operand:V4SI 2 "register_operand" "v")))]
881 [(set_attr "type" "vecsimple")])
883 (define_insn "sminv4si3"
884 [(set (match_operand:V4SI 0 "register_operand" "=v")
885 (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
886 (match_operand:V4SI 2 "register_operand" "v")))]
889 [(set_attr "type" "vecsimple")])
891 (define_insn "sminv4sf3"
892 [(set (match_operand:V4SF 0 "register_operand" "=v")
893 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
894 (match_operand:V4SF 2 "register_operand" "v")))]
897 [(set_attr "type" "veccmp")])
899 (define_insn "altivec_vmuleub"
900 [(set (match_operand:V8HI 0 "register_operand" "=v")
901 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
902 (match_operand:V16QI 2 "register_operand" "v")] 83))]
905 [(set_attr "type" "veccomplex")])
907 (define_insn "altivec_vmulesb"
908 [(set (match_operand:V8HI 0 "register_operand" "=v")
909 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
910 (match_operand:V16QI 2 "register_operand" "v")] 84))]
913 [(set_attr "type" "veccomplex")])
915 (define_insn "altivec_vmuleuh"
916 [(set (match_operand:V4SI 0 "register_operand" "=v")
917 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
918 (match_operand:V8HI 2 "register_operand" "v")] 85))]
921 [(set_attr "type" "veccomplex")])
923 (define_insn "altivec_vmulesh"
924 [(set (match_operand:V4SI 0 "register_operand" "=v")
925 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
926 (match_operand:V8HI 2 "register_operand" "v")] 86))]
929 [(set_attr "type" "veccomplex")])
931 (define_insn "altivec_vmuloub"
932 [(set (match_operand:V8HI 0 "register_operand" "=v")
933 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
934 (match_operand:V16QI 2 "register_operand" "v")] 87))]
937 [(set_attr "type" "veccomplex")])
939 (define_insn "altivec_vmulosb"
940 [(set (match_operand:V8HI 0 "register_operand" "=v")
941 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
942 (match_operand:V16QI 2 "register_operand" "v")] 88))]
945 [(set_attr "type" "veccomplex")])
947 (define_insn "altivec_vmulouh"
948 [(set (match_operand:V4SI 0 "register_operand" "=v")
949 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
950 (match_operand:V8HI 2 "register_operand" "v")] 89))]
953 [(set_attr "type" "veccomplex")])
955 (define_insn "altivec_vmulosh"
956 [(set (match_operand:V4SI 0 "register_operand" "=v")
957 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
958 (match_operand:V8HI 2 "register_operand" "v")] 90))]
961 [(set_attr "type" "veccomplex")])
963 (define_insn "altivec_vnor"
964 [(set (match_operand:V4SI 0 "register_operand" "=v")
965 (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
966 (match_operand:V4SI 2 "register_operand" "v"))))]
969 [(set_attr "type" "vecsimple")])
971 (define_insn "iorv4si3"
972 [(set (match_operand:V4SI 0 "register_operand" "=v")
973 (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
974 (match_operand:V4SI 2 "register_operand" "v")))]
977 [(set_attr "type" "vecsimple")])
979 (define_insn "altivec_vpkuhum"
980 [(set (match_operand:V16QI 0 "register_operand" "=v")
981 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
982 (match_operand:V8HI 2 "register_operand" "v")] 93))]
985 [(set_attr "type" "vecperm")])
987 (define_insn "altivec_vpkuwum"
988 [(set (match_operand:V8HI 0 "register_operand" "=v")
989 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
990 (match_operand:V4SI 2 "register_operand" "v")] 94))]
993 [(set_attr "type" "vecperm")])
995 (define_insn "altivec_vpkpx"
996 [(set (match_operand:V8HI 0 "register_operand" "=v")
997 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
998 (match_operand:V4SI 2 "register_operand" "v")] 95))]
1001 [(set_attr "type" "vecperm")])
1003 (define_insn "altivec_vpkuhss"
1004 [(set (match_operand:V16QI 0 "register_operand" "=v")
1005 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1006 (match_operand:V8HI 2 "register_operand" "v")] 96))
1007 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1010 [(set_attr "type" "vecperm")])
1012 (define_insn "altivec_vpkshss"
1013 [(set (match_operand:V16QI 0 "register_operand" "=v")
1014 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1015 (match_operand:V8HI 2 "register_operand" "v")] 97))
1016 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1019 [(set_attr "type" "vecperm")])
1021 (define_insn "altivec_vpkuwss"
1022 [(set (match_operand:V8HI 0 "register_operand" "=v")
1023 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1024 (match_operand:V4SI 2 "register_operand" "v")] 98))
1025 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1028 [(set_attr "type" "vecperm")])
1030 (define_insn "altivec_vpkswss"
1031 [(set (match_operand:V8HI 0 "register_operand" "=v")
1032 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1033 (match_operand:V4SI 2 "register_operand" "v")] 99))
1034 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1037 [(set_attr "type" "vecperm")])
1039 (define_insn "altivec_vpkuhus"
1040 [(set (match_operand:V16QI 0 "register_operand" "=v")
1041 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1042 (match_operand:V8HI 2 "register_operand" "v")] 100))
1043 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1046 [(set_attr "type" "vecperm")])
1048 (define_insn "altivec_vpkshus"
1049 [(set (match_operand:V16QI 0 "register_operand" "=v")
1050 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1051 (match_operand:V8HI 2 "register_operand" "v")] 101))
1052 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1055 [(set_attr "type" "vecperm")])
1057 (define_insn "altivec_vpkuwus"
1058 [(set (match_operand:V8HI 0 "register_operand" "=v")
1059 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1060 (match_operand:V4SI 2 "register_operand" "v")] 102))
1061 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1064 [(set_attr "type" "vecperm")])
1066 (define_insn "altivec_vpkswus"
1067 [(set (match_operand:V8HI 0 "register_operand" "=v")
1068 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1069 (match_operand:V4SI 2 "register_operand" "v")] 103))
1070 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1073 [(set_attr "type" "vecperm")])
1075 (define_insn "altivec_vrlb"
1076 [(set (match_operand:V16QI 0 "register_operand" "=v")
1077 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1078 (match_operand:V16QI 2 "register_operand" "v")] 104))]
1081 [(set_attr "type" "vecsimple")])
1083 (define_insn "altivec_vrlh"
1084 [(set (match_operand:V8HI 0 "register_operand" "=v")
1085 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1086 (match_operand:V8HI 2 "register_operand" "v")] 105))]
1089 [(set_attr "type" "vecsimple")])
1091 (define_insn "altivec_vrlw"
1092 [(set (match_operand:V4SI 0 "register_operand" "=v")
1093 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1094 (match_operand:V4SI 2 "register_operand" "v")] 106))]
1097 [(set_attr "type" "vecsimple")])
1099 (define_insn "altivec_vslb"
1100 [(set (match_operand:V16QI 0 "register_operand" "=v")
1101 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1102 (match_operand:V16QI 2 "register_operand" "v")] 107))]
1105 [(set_attr "type" "vecsimple")])
1107 (define_insn "altivec_vslh"
1108 [(set (match_operand:V8HI 0 "register_operand" "=v")
1109 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1110 (match_operand:V8HI 2 "register_operand" "v")] 108))]
1113 [(set_attr "type" "vecsimple")])
1115 (define_insn "altivec_vslw"
1116 [(set (match_operand:V4SI 0 "register_operand" "=v")
1117 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1118 (match_operand:V4SI 2 "register_operand" "v")] 109))]
1121 [(set_attr "type" "vecsimple")])
1123 (define_insn "altivec_vslw_v4sf"
1124 [(set (match_operand:V4SF 0 "register_operand" "=v")
1125 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1126 (match_operand:V4SF 2 "register_operand" "v")] 109))]
1129 [(set_attr "type" "vecsimple")])
1131 (define_insn "altivec_vsl"
1132 [(set (match_operand:V4SI 0 "register_operand" "=v")
1133 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1134 (match_operand:V4SI 2 "register_operand" "v")] 110))]
1137 [(set_attr "type" "vecperm")])
1139 (define_insn "altivec_vslo"
1140 [(set (match_operand:V4SI 0 "register_operand" "=v")
1141 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1142 (match_operand:V4SI 2 "register_operand" "v")] 111))]
1145 [(set_attr "type" "vecperm")])
1147 (define_insn "altivec_vsrb"
1148 [(set (match_operand:V16QI 0 "register_operand" "=v")
1149 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1150 (match_operand:V16QI 2 "register_operand" "v")] 112))]
1153 [(set_attr "type" "vecsimple")])
1155 (define_insn "altivec_vsrh"
1156 [(set (match_operand:V8HI 0 "register_operand" "=v")
1157 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1158 (match_operand:V8HI 2 "register_operand" "v")] 113))]
1161 [(set_attr "type" "vecsimple")])
1163 (define_insn "altivec_vsrw"
1164 [(set (match_operand:V4SI 0 "register_operand" "=v")
1165 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1166 (match_operand:V4SI 2 "register_operand" "v")] 114))]
1169 [(set_attr "type" "vecsimple")])
1171 (define_insn "altivec_vsrab"
1172 [(set (match_operand:V16QI 0 "register_operand" "=v")
1173 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1174 (match_operand:V16QI 2 "register_operand" "v")] 115))]
1177 [(set_attr "type" "vecsimple")])
1179 (define_insn "altivec_vsrah"
1180 [(set (match_operand:V8HI 0 "register_operand" "=v")
1181 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1182 (match_operand:V8HI 2 "register_operand" "v")] 116))]
1185 [(set_attr "type" "vecsimple")])
1187 (define_insn "altivec_vsraw"
1188 [(set (match_operand:V4SI 0 "register_operand" "=v")
1189 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1190 (match_operand:V4SI 2 "register_operand" "v")] 117))]
1193 [(set_attr "type" "vecsimple")])
1195 (define_insn "altivec_vsr"
1196 [(set (match_operand:V4SI 0 "register_operand" "=v")
1197 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1198 (match_operand:V4SI 2 "register_operand" "v")] 118))]
1201 [(set_attr "type" "vecperm")])
1203 (define_insn "altivec_vsro"
1204 [(set (match_operand:V4SI 0 "register_operand" "=v")
1205 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1206 (match_operand:V4SI 2 "register_operand" "v")] 119))]
1209 [(set_attr "type" "vecperm")])
1211 (define_insn "subv16qi3"
1212 [(set (match_operand:V16QI 0 "register_operand" "=v")
1213 (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1214 (match_operand:V16QI 2 "register_operand" "v")))]
1217 [(set_attr "type" "vecsimple")])
1219 (define_insn "subv8hi3"
1220 [(set (match_operand:V8HI 0 "register_operand" "=v")
1221 (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1222 (match_operand:V8HI 2 "register_operand" "v")))]
1225 [(set_attr "type" "vecsimple")])
1227 (define_insn "subv4si3"
1228 [(set (match_operand:V4SI 0 "register_operand" "=v")
1229 (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1230 (match_operand:V4SI 2 "register_operand" "v")))]
1233 [(set_attr "type" "vecsimple")])
1235 (define_insn "subv4sf3"
1236 [(set (match_operand:V4SF 0 "register_operand" "=v")
1237 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1238 (match_operand:V4SF 2 "register_operand" "v")))]
1241 [(set_attr "type" "vecfloat")])
1243 (define_insn "altivec_vsubcuw"
1244 [(set (match_operand:V4SI 0 "register_operand" "=v")
1245 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1246 (match_operand:V4SI 2 "register_operand" "v")] 124))]
1249 [(set_attr "type" "vecsimple")])
1251 (define_insn "altivec_vsububs"
1252 [(set (match_operand:V16QI 0 "register_operand" "=v")
1253 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1254 (match_operand:V16QI 2 "register_operand" "v")] 125))
1255 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1258 [(set_attr "type" "vecsimple")])
1260 (define_insn "altivec_vsubsbs"
1261 [(set (match_operand:V16QI 0 "register_operand" "=v")
1262 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1263 (match_operand:V16QI 2 "register_operand" "v")] 126))
1264 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1267 [(set_attr "type" "vecsimple")])
1269 (define_insn "altivec_vsubuhs"
1270 [(set (match_operand:V8HI 0 "register_operand" "=v")
1271 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1272 (match_operand:V8HI 2 "register_operand" "v")] 127))
1273 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1276 [(set_attr "type" "vecsimple")])
1278 (define_insn "altivec_vsubshs"
1279 [(set (match_operand:V8HI 0 "register_operand" "=v")
1280 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1281 (match_operand:V8HI 2 "register_operand" "v")] 128))
1282 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1285 [(set_attr "type" "vecsimple")])
1287 (define_insn "altivec_vsubuws"
1288 [(set (match_operand:V4SI 0 "register_operand" "=v")
1289 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1290 (match_operand:V4SI 2 "register_operand" "v")] 129))
1291 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1294 [(set_attr "type" "vecsimple")])
1296 (define_insn "altivec_vsubsws"
1297 [(set (match_operand:V4SI 0 "register_operand" "=v")
1298 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1299 (match_operand:V4SI 2 "register_operand" "v")] 130))
1300 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1303 [(set_attr "type" "vecsimple")])
1305 (define_insn "altivec_vsum4ubs"
1306 [(set (match_operand:V4SI 0 "register_operand" "=v")
1307 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1308 (match_operand:V4SI 2 "register_operand" "v")] 131))
1309 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1312 [(set_attr "type" "veccomplex")])
1314 (define_insn "altivec_vsum4sbs"
1315 [(set (match_operand:V4SI 0 "register_operand" "=v")
1316 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1317 (match_operand:V4SI 2 "register_operand" "v")] 132))
1318 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1321 [(set_attr "type" "veccomplex")])
1323 (define_insn "altivec_vsum4shs"
1324 [(set (match_operand:V4SI 0 "register_operand" "=v")
1325 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1326 (match_operand:V4SI 2 "register_operand" "v")] 133))
1327 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1330 [(set_attr "type" "veccomplex")])
1332 (define_insn "altivec_vsum2sws"
1333 [(set (match_operand:V4SI 0 "register_operand" "=v")
1334 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1335 (match_operand:V4SI 2 "register_operand" "v")] 134))
1336 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1339 [(set_attr "type" "veccomplex")])
1341 (define_insn "altivec_vsumsws"
1342 [(set (match_operand:V4SI 0 "register_operand" "=v")
1343 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1344 (match_operand:V4SI 2 "register_operand" "v")] 135))
1345 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1348 [(set_attr "type" "veccomplex")])
1351 (define_insn "xorv4si3"
1352 [(set (match_operand:V4SI 0 "register_operand" "=v")
1353 (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1354 (match_operand:V4SI 2 "register_operand" "v")))]
1357 [(set_attr "type" "vecsimple")])
1359 (define_insn "xorv8hi3"
1360 [(set (match_operand:V8HI 0 "register_operand" "=v")
1361 (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1362 (match_operand:V8HI 2 "register_operand" "v")))]
1365 [(set_attr "type" "vecsimple")])
1367 (define_insn "xorv16qi3"
1368 [(set (match_operand:V16QI 0 "register_operand" "=v")
1369 (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1370 (match_operand:V16QI 2 "register_operand" "v")))]
1373 [(set_attr "type" "vecsimple")])
1375 (define_insn "altivec_vspltb"
1376 [(set (match_operand:V16QI 0 "register_operand" "=v")
1377 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1378 (match_operand:QI 2 "immediate_operand" "i")] 136))]
1381 [(set_attr "type" "vecperm")])
1382 ;; End of vector xor's
1384 (define_insn "altivec_vsplth"
1385 [(set (match_operand:V8HI 0 "register_operand" "=v")
1386 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1387 (match_operand:QI 2 "immediate_operand" "i")] 137))]
1390 [(set_attr "type" "vecperm")])
1392 (define_insn "altivec_vspltw"
1393 [(set (match_operand:V4SI 0 "register_operand" "=v")
1394 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1395 (match_operand:QI 2 "immediate_operand" "i")] 138))]
1398 [(set_attr "type" "vecperm")])
1400 (define_insn "altivec_vspltisb"
1401 [(set (match_operand:V16QI 0 "register_operand" "=v")
1402 (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1406 [(set_attr "type" "vecperm")])
1408 (define_insn "altivec_vspltish"
1409 [(set (match_operand:V8HI 0 "register_operand" "=v")
1410 (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1414 [(set_attr "type" "vecperm")])
1416 (define_insn "altivec_vspltisw"
1417 [(set (match_operand:V4SI 0 "register_operand" "=v")
1418 (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1422 [(set_attr "type" "vecperm")])
1424 (define_insn "altivec_vspltisw_v4sf"
1425 [(set (match_operand:V4SF 0 "register_operand" "=v")
1426 (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1429 [(set_attr "type" "vecperm")])
1431 (define_insn "ftruncv4sf2"
1432 [(set (match_operand:V4SF 0 "register_operand" "=v")
1433 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1436 [(set_attr "type" "vecfloat")])
1438 (define_insn "altivec_vperm_4si"
1439 [(set (match_operand:V4SI 0 "register_operand" "=v")
1440 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1441 (match_operand:V4SI 2 "register_operand" "v")
1442 (match_operand:V16QI 3 "register_operand" "v")] 144))]
1445 [(set_attr "type" "vecperm")])
1447 (define_insn "altivec_vperm_4sf"
1448 [(set (match_operand:V4SF 0 "register_operand" "=v")
1449 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1450 (match_operand:V4SF 2 "register_operand" "v")
1451 (match_operand:V16QI 3 "register_operand" "v")] 145))]
1454 [(set_attr "type" "vecperm")])
1456 (define_insn "altivec_vperm_8hi"
1457 [(set (match_operand:V8HI 0 "register_operand" "=v")
1458 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1459 (match_operand:V8HI 2 "register_operand" "v")
1460 (match_operand:V16QI 3 "register_operand" "v")] 146))]
1463 [(set_attr "type" "vecperm")])
1465 (define_insn "altivec_vperm_16qi"
1466 [(set (match_operand:V16QI 0 "register_operand" "=v")
1467 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1468 (match_operand:V16QI 2 "register_operand" "v")
1469 (match_operand:V16QI 3 "register_operand" "v")] 147))]
1472 [(set_attr "type" "vecperm")])
1474 (define_insn "altivec_vrfip"
1475 [(set (match_operand:V4SF 0 "register_operand" "=v")
1476 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1479 [(set_attr "type" "vecfloat")])
1481 (define_insn "altivec_vrfin"
1482 [(set (match_operand:V4SF 0 "register_operand" "=v")
1483 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1486 [(set_attr "type" "vecfloat")])
1488 (define_insn "altivec_vrfim"
1489 [(set (match_operand:V4SF 0 "register_operand" "=v")
1490 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1493 [(set_attr "type" "vecfloat")])
1495 (define_insn "altivec_vcfux"
1496 [(set (match_operand:V4SF 0 "register_operand" "=v")
1497 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1498 (match_operand:QI 2 "immediate_operand" "i")] 151))]
1501 [(set_attr "type" "vecfloat")])
1503 (define_insn "altivec_vcfsx"
1504 [(set (match_operand:V4SF 0 "register_operand" "=v")
1505 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1506 (match_operand:QI 2 "immediate_operand" "i")] 152))]
1509 [(set_attr "type" "vecfloat")])
1511 (define_insn "altivec_vctuxs"
1512 [(set (match_operand:V4SI 0 "register_operand" "=v")
1513 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1514 (match_operand:QI 2 "immediate_operand" "i")] 153))
1515 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1518 [(set_attr "type" "vecfloat")])
1520 (define_insn "altivec_vctsxs"
1521 [(set (match_operand:V4SI 0 "register_operand" "=v")
1522 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1523 (match_operand:QI 2 "immediate_operand" "i")] 154))
1524 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1527 [(set_attr "type" "vecfloat")])
1529 (define_insn "altivec_vlogefp"
1530 [(set (match_operand:V4SF 0 "register_operand" "=v")
1531 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1534 [(set_attr "type" "vecfloat")])
1536 (define_insn "altivec_vexptefp"
1537 [(set (match_operand:V4SF 0 "register_operand" "=v")
1538 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1541 [(set_attr "type" "vecfloat")])
1543 (define_insn "altivec_vrsqrtefp"
1544 [(set (match_operand:V4SF 0 "register_operand" "=v")
1545 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1548 [(set_attr "type" "vecfloat")])
1550 (define_insn "altivec_vrefp"
1551 [(set (match_operand:V4SF 0 "register_operand" "=v")
1552 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1555 [(set_attr "type" "vecfloat")])
1557 (define_insn "altivec_vsel_4si"
1558 [(set (match_operand:V4SI 0 "register_operand" "=v")
1559 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1560 (match_operand:V4SI 2 "register_operand" "v")
1561 (match_operand:V4SI 3 "register_operand" "v")] 159))]
1564 [(set_attr "type" "vecperm")])
1566 (define_insn "altivec_vsel_4sf"
1567 [(set (match_operand:V4SF 0 "register_operand" "=v")
1568 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1569 (match_operand:V4SF 2 "register_operand" "v")
1570 (match_operand:V4SI 3 "register_operand" "v")] 160))]
1573 [(set_attr "type" "vecperm")])
1575 (define_insn "altivec_vsel_8hi"
1576 [(set (match_operand:V8HI 0 "register_operand" "=v")
1577 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1578 (match_operand:V8HI 2 "register_operand" "v")
1579 (match_operand:V8HI 3 "register_operand" "v")] 161))]
1582 [(set_attr "type" "vecperm")])
1584 (define_insn "altivec_vsel_16qi"
1585 [(set (match_operand:V16QI 0 "register_operand" "=v")
1586 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1587 (match_operand:V16QI 2 "register_operand" "v")
1588 (match_operand:V16QI 3 "register_operand" "v")] 162))]
1591 [(set_attr "type" "vecperm")])
1593 (define_insn "altivec_vsldoi_4si"
1594 [(set (match_operand:V4SI 0 "register_operand" "=v")
1595 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1596 (match_operand:V4SI 2 "register_operand" "v")
1597 (match_operand:QI 3 "immediate_operand" "i")] 163))]
1599 "vsldoi %0,%1,%2,%3"
1600 [(set_attr "type" "vecperm")])
1602 (define_insn "altivec_vsldoi_4sf"
1603 [(set (match_operand:V4SF 0 "register_operand" "=v")
1604 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1605 (match_operand:V4SF 2 "register_operand" "v")
1606 (match_operand:QI 3 "immediate_operand" "i")] 164))]
1608 "vsldoi %0,%1,%2,%3"
1609 [(set_attr "type" "vecperm")])
1611 (define_insn "altivec_vsldoi_8hi"
1612 [(set (match_operand:V8HI 0 "register_operand" "=v")
1613 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1614 (match_operand:V8HI 2 "register_operand" "v")
1615 (match_operand:QI 3 "immediate_operand" "i")] 165))]
1617 "vsldoi %0,%1,%2,%3"
1618 [(set_attr "type" "vecperm")])
1620 (define_insn "altivec_vsldoi_16qi"
1621 [(set (match_operand:V16QI 0 "register_operand" "=v")
1622 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1623 (match_operand:V16QI 2 "register_operand" "v")
1624 (match_operand:QI 3 "immediate_operand" "i")] 166))]
1626 "vsldoi %0,%1,%2,%3"
1627 [(set_attr "type" "vecperm")])
1629 (define_insn "altivec_vupkhsb"
1630 [(set (match_operand:V8HI 0 "register_operand" "=v")
1631 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1634 [(set_attr "type" "vecperm")])
1636 (define_insn "altivec_vupkhpx"
1637 [(set (match_operand:V4SI 0 "register_operand" "=v")
1638 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1641 [(set_attr "type" "vecperm")])
1643 (define_insn "altivec_vupkhsh"
1644 [(set (match_operand:V4SI 0 "register_operand" "=v")
1645 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1648 [(set_attr "type" "vecperm")])
1650 (define_insn "altivec_vupklsb"
1651 [(set (match_operand:V8HI 0 "register_operand" "=v")
1652 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1655 [(set_attr "type" "vecperm")])
1657 (define_insn "altivec_vupklpx"
1658 [(set (match_operand:V4SI 0 "register_operand" "=v")
1659 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1662 [(set_attr "type" "vecperm")])
1664 (define_insn "altivec_vupklsh"
1665 [(set (match_operand:V4SI 0 "register_operand" "=v")
1666 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1669 [(set_attr "type" "vecperm")])
1671 ;; AltiVec predicates.
1673 (define_expand "cr6_test_for_zero"
1674 [(set (match_operand:SI 0 "register_operand" "=r")
1680 (define_expand "cr6_test_for_zero_reverse"
1681 [(set (match_operand:SI 0 "register_operand" "=r")
1684 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1688 (define_expand "cr6_test_for_lt"
1689 [(set (match_operand:SI 0 "register_operand" "=r")
1695 (define_expand "cr6_test_for_lt_reverse"
1696 [(set (match_operand:SI 0 "register_operand" "=r")
1699 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1703 ;; We can get away with generating the opcode on the fly (%3 below)
1704 ;; because all the predicates have the same scheduling parameters.
1706 (define_insn "altivec_predicate_v4si"
1708 (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1709 (match_operand:V4SI 2 "register_operand" "v")
1710 (match_operand 3 "any_operand" "")] 173))
1711 (clobber (match_scratch:V4SI 0 "=v"))]
1714 [(set_attr "type" "veccmp")])
1716 (define_insn "altivec_predicate_v4sf"
1718 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1719 (match_operand:V4SF 2 "register_operand" "v")
1720 (match_operand 3 "any_operand" "")] 174))
1721 (clobber (match_scratch:V4SF 0 "=v"))]
1724 [(set_attr "type" "veccmp")])
1726 (define_insn "altivec_predicate_v8hi"
1728 (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1729 (match_operand:V8HI 2 "register_operand" "v")
1730 (match_operand 3 "any_operand" "")] 175))
1731 (clobber (match_scratch:V8HI 0 "=v"))]
1734 [(set_attr "type" "veccmp")])
1736 (define_insn "altivec_predicate_v16qi"
1738 (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1739 (match_operand:V16QI 2 "register_operand" "v")
1740 (match_operand 3 "any_operand" "")] 175))
1741 (clobber (match_scratch:V16QI 0 "=v"))]
1744 [(set_attr "type" "veccmp")])
1746 (define_insn "altivec_mtvscr"
1749 [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1752 [(set_attr "type" "vecsimple")])
1754 (define_insn "altivec_mfvscr"
1755 [(set (match_operand:V8HI 0 "register_operand" "=v")
1756 (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1759 [(set_attr "type" "vecsimple")])
1761 (define_insn "altivec_dssall"
1762 [(unspec [(const_int 0)] 188)]
1765 [(set_attr "type" "vecsimple")])
1767 (define_insn "altivec_dss"
1768 [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1771 [(set_attr "type" "vecsimple")])
1773 (define_insn "altivec_dst"
1774 [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1775 (match_operand:SI 1 "register_operand" "r")
1776 (match_operand:QI 2 "immediate_operand" "i")] 190)]
1779 [(set_attr "type" "vecsimple")])
1781 (define_insn "altivec_dstt"
1782 [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1783 (match_operand:SI 1 "register_operand" "r")
1784 (match_operand:QI 2 "immediate_operand" "i")] 191)]
1787 [(set_attr "type" "vecsimple")])
1789 (define_insn "altivec_dstst"
1790 [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1791 (match_operand:SI 1 "register_operand" "r")
1792 (match_operand:QI 2 "immediate_operand" "i")] 192)]
1795 [(set_attr "type" "vecsimple")])
1797 (define_insn "altivec_dststt"
1798 [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1799 (match_operand:SI 1 "register_operand" "r")
1800 (match_operand:QI 2 "immediate_operand" "i")] 193)]
1803 [(set_attr "type" "vecsimple")])
1805 (define_insn "altivec_lvsl"
1806 [(set (match_operand:V16QI 0 "register_operand" "=v")
1807 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1810 [(set_attr "type" "vecload")])
1812 (define_insn "altivec_lvsr"
1813 [(set (match_operand:V16QI 0 "register_operand" "=v")
1814 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1817 [(set_attr "type" "vecload")])
1819 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1820 ;; identical rtl but different instructions-- and gcc gets confused.
1822 (define_insn "altivec_lvebx"
1824 [(set (match_operand:V16QI 0 "register_operand" "=v")
1825 (match_operand:V16QI 1 "memory_operand" "m"))
1826 (unspec [(const_int 0)] 196)])]
1829 [(set_attr "type" "vecload")])
1831 (define_insn "altivec_lvehx"
1833 [(set (match_operand:V8HI 0 "register_operand" "=v")
1834 (match_operand:V8HI 1 "memory_operand" "m"))
1835 (unspec [(const_int 0)] 197)])]
1838 [(set_attr "type" "vecload")])
1840 (define_insn "altivec_lvewx"
1842 [(set (match_operand:V4SI 0 "register_operand" "=v")
1843 (match_operand:V4SI 1 "memory_operand" "m"))
1844 (unspec [(const_int 0)] 198)])]
1847 [(set_attr "type" "vecload")])
1849 (define_insn "altivec_lvxl"
1851 [(set (match_operand:V4SI 0 "register_operand" "=v")
1852 (match_operand:V4SI 1 "memory_operand" "m"))
1853 (unspec [(const_int 0)] 213)])]
1856 [(set_attr "type" "vecload")])
1858 (define_insn "altivec_lvx"
1859 [(set (match_operand:V4SI 0 "register_operand" "=v")
1860 (match_operand:V4SI 1 "memory_operand" "m"))]
1863 [(set_attr "type" "vecload")])
1865 (define_insn "altivec_stvx"
1867 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1868 (match_operand:V4SI 1 "register_operand" "v"))
1869 (unspec [(const_int 0)] 201)])]
1872 [(set_attr "type" "vecstore")])
1874 (define_insn "altivec_stvxl"
1876 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1877 (match_operand:V4SI 1 "register_operand" "v"))
1878 (unspec [(const_int 0)] 202)])]
1881 [(set_attr "type" "vecstore")])
1883 (define_insn "altivec_stvebx"
1885 [(set (match_operand:V16QI 0 "memory_operand" "=m")
1886 (match_operand:V16QI 1 "register_operand" "v"))
1887 (unspec [(const_int 0)] 203)])]
1890 [(set_attr "type" "vecstore")])
1892 (define_insn "altivec_stvehx"
1894 [(set (match_operand:V8HI 0 "memory_operand" "=m")
1895 (match_operand:V8HI 1 "register_operand" "v"))
1896 (unspec [(const_int 0)] 204)])]
1899 [(set_attr "type" "vecstore")])
1901 (define_insn "altivec_stvewx"
1903 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1904 (match_operand:V4SI 1 "register_operand" "v"))
1905 (unspec [(const_int 0)] 205)])]
1908 [(set_attr "type" "vecstore")])
1910 (define_insn "absv16qi2"
1911 [(set (match_operand:V16QI 0 "register_operand" "=v")
1912 (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1913 (clobber (match_scratch:V16QI 2 "=&v"))
1914 (clobber (match_scratch:V16QI 3 "=&v"))]
1916 "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1917 [(set_attr "type" "vecsimple")
1918 (set_attr "length" "12")])
1920 (define_insn "absv8hi2"
1921 [(set (match_operand:V8HI 0 "register_operand" "=v")
1922 (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1923 (clobber (match_scratch:V8HI 2 "=&v"))
1924 (clobber (match_scratch:V8HI 3 "=&v"))]
1926 "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1927 [(set_attr "type" "vecsimple")
1928 (set_attr "length" "12")])
1930 (define_insn "absv4si2"
1931 [(set (match_operand:V4SI 0 "register_operand" "=v")
1932 (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1933 (clobber (match_scratch:V4SI 2 "=&v"))
1934 (clobber (match_scratch:V4SI 3 "=&v"))]
1936 "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1937 [(set_attr "type" "vecsimple")
1938 (set_attr "length" "12")])
1940 (define_insn "absv4sf2"
1941 [(set (match_operand:V4SF 0 "register_operand" "=v")
1942 (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1943 (clobber (match_scratch:V4SF 2 "=&v"))
1944 (clobber (match_scratch:V4SF 3 "=&v"))]
1946 "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1947 [(set_attr "type" "vecsimple")
1948 (set_attr "length" "12")])
1950 (define_insn "altivec_abss_v16qi"
1951 [(set (match_operand:V16QI 0 "register_operand" "=v")
1952 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1953 (clobber (match_scratch:V16QI 2 "=&v"))
1954 (clobber (match_scratch:V16QI 3 "=&v"))]
1956 "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1957 [(set_attr "type" "vecsimple")
1958 (set_attr "length" "12")])
1960 (define_insn "altivec_abss_v8hi"
1961 [(set (match_operand:V8HI 0 "register_operand" "=v")
1962 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1963 (clobber (match_scratch:V8HI 2 "=&v"))
1964 (clobber (match_scratch:V8HI 3 "=&v"))]
1966 "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1967 [(set_attr "type" "vecsimple")
1968 (set_attr "length" "12")])
1970 (define_insn "altivec_abss_v4si"
1971 [(set (match_operand:V4SI 0 "register_operand" "=v")
1972 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1973 (clobber (match_scratch:V4SI 2 "=&v"))
1974 (clobber (match_scratch:V4SI 3 "=&v"))]
1976 "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1977 [(set_attr "type" "vecsimple")
1978 (set_attr "length" "12")])