gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 ;; Generic LVX load instruction.
  23 (define_insn "altivec_lvx_4si"
  24   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  25         (match_operand:V4SI 1 "memory_operand" "m"))]
  26   "TARGET_ALTIVEC"
  27   "lvx %0,%y1"
  28   [(set_attr "type" "vecload")])
  29
  30 (define_insn "altivec_lvx_8hi"
  31   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  32         (match_operand:V8HI 1 "memory_operand" "m"))]
  33   "TARGET_ALTIVEC"
  34   "lvx %0,%y1"
  35   [(set_attr "type" "vecload")])
  36
  37 (define_insn "altivec_lvx_16qi"
  38   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  39         (match_operand:V16QI 1 "memory_operand" "m"))]
  40   "TARGET_ALTIVEC"
  41   "lvx %0,%y1"
  42   [(set_attr "type" "vecload")])
  43
  44 (define_insn "altivec_lvx_4sf"
  45   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  46         (match_operand:V4SF 1 "memory_operand" "m"))]
  47   "TARGET_ALTIVEC"
  48   "lvx %0,%y1"
  49   [(set_attr "type" "vecload")])
  50
  51 ;; Generic STVX store instruction.
  52 (define_insn "altivec_stvx_4si"
  53   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  54         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  55   "TARGET_ALTIVEC"
  56   "stvx %1,%y0"
  57   [(set_attr "type" "vecstore")])
  58
  59 (define_insn "altivec_stvx_8hi"
  60   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  61         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  62   "TARGET_ALTIVEC"
  63   "stvx %1,%y0"
  64   [(set_attr "type" "vecstore")])
  65
  66 (define_insn "altivec_stvx_16qi"
  67   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  68         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  69   "TARGET_ALTIVEC"
  70   "stvx %1,%y0"
  71   [(set_attr "type" "vecstore")])
  72
  73 (define_insn "altivec_stvx_4sf"
  74   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  75         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  76   "TARGET_ALTIVEC"
  77   "stvx %1,%y0"
  78   [(set_attr "type" "vecstore")])
  79
  80 ;; Vector move instructions.
  81 (define_expand "movv4si"
  82   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  83         (match_operand:V4SI 1 "any_operand" ""))]
  84   "TARGET_ALTIVEC"
  85   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  86
  87 (define_insn "*movv4si_internal"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
  89         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))]
  90   "TARGET_ALTIVEC"
  91   "@
  92    stvx %1,%y0
  93    lvx %0,%y1
  94    vor %0,%1,%1
  95    stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
  96    lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
  97    mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
  98   [(set_attr "type" "altivec")
  99    (set_attr "length" "*,*,*,16,16,16")])
 100
 101 (define_expand "movv8hi"
 102   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 103         (match_operand:V8HI 1 "any_operand" ""))]
 104   "TARGET_ALTIVEC"
 105   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 106
 107 (define_insn "*movv8hi_internal1"
 108   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
 109         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))]
 110   "TARGET_ALTIVEC"
 111   "@
 112    stvx %1,%y0
 113    lvx %0,%y1
 114    vor %0,%1,%1
 115    stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
 116    lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
 117    mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
 118   [(set_attr "type" "altivec")
 119    (set_attr "length" "*,*,*,16,16,16")])
 120
 121 (define_expand "movv16qi"
 122   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 123         (match_operand:V16QI 1 "any_operand" ""))]
 124   "TARGET_ALTIVEC"
 125   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 126
 127 (define_insn "*movv16qi_internal1"
 128   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
 129         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))]
 130   "TARGET_ALTIVEC"
 131   "@
 132    stvx %1,%y0
 133    lvx %0,%y1
 134    vor %0,%1,%1
 135   stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
 136   lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
 137   mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
 138   [(set_attr "type" "altivec")
 139    (set_attr "length" "*,*,*,16,16,16")])
 140
 141 (define_expand "movv4sf"
 142   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 143         (match_operand:V4SF 1 "any_operand" ""))]
 144   "TARGET_ALTIVEC"
 145   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 146
 147 (define_insn "*movv4sf_internal1"
 148   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r")
 149         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))]
 150   "TARGET_ALTIVEC"
 151   "@
 152    stvx %1,%y0
 153    lvx %0,%y1
 154    vor %0,%1,%1
 155    stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
 156    lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
 157    mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
 158   [(set_attr "type" "altivec")
 159    (set_attr "length" "*,*,*,16,16,16")])
 160
 161 (define_insn "get_vrsave_internal"
 162   [(set (match_operand:SI 0 "register_operand" "=r")
 163         (unspec:SI [(reg:SI 109)] 214))]
 164   "TARGET_ALTIVEC"
 165   "*
 166 {
 167   if (TARGET_MACHO)
 168      return \"mfspr %0,256\";
 169   else
 170      return \"mfvrsave %0\";
 171 }"
 172   [(set_attr "type" "altivec")])
 173
 174 (define_insn "*set_vrsave_internal"
 175   [(match_parallel 0 "vrsave_operation"
 176      [(set (reg:SI 109)
 177            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 178                                 (reg:SI 109)] 30))])]
 179   "TARGET_ALTIVEC"
 180   "*
 181 {
 182   if (TARGET_MACHO)
 183     return \"mtspr 256,%1\";
 184   else
 185     return \"mtvrsave %1\";
 186 }"
 187   [(set_attr "type" "altivec")])
 188
 189 ;; Vector clears
 190 (define_insn "*movv4si_const0"
 191   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
 192         (match_operand:V4SI 1 "zero_constant" ""))]
 193   "TARGET_ALTIVEC"
 194   "vxor %0,%0,%0"
 195   [(set_attr "type" "vecsimple")])
 196
 197 (define_insn "*movv4sf_const0"
 198   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
 199         (match_operand:V4SF 1 "zero_constant" ""))]
 200
 201   "TARGET_ALTIVEC"
 202   "vxor %0,%0,%0"
 203   [(set_attr "type" "vecsimple")])
 204
 205 (define_insn "*movv8hi_const0"
 206   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
 207         (match_operand:V8HI 1 "zero_constant" ""))]
 208   "TARGET_ALTIVEC"
 209   "vxor %0,%0,%0"
 210   [(set_attr "type" "vecsimple")])
 211
 212 (define_insn "*movv16qi_const0"
 213   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
 214         (match_operand:V16QI 1 "zero_constant" ""))]
 215   "TARGET_ALTIVEC"
 216   "vxor %0,%0,%0"
 217   [(set_attr "type" "vecsimple")])
 218
 219 ;; Simple binary operations.
 220
 221 (define_insn "addv16qi3"
 222   [(set (match_operand:V16QI 0 "register_operand" "=v")
 223         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 224                     (match_operand:V16QI 2 "register_operand" "v")))]
 225   "TARGET_ALTIVEC"
 226   "vaddubm %0,%1,%2"
 227   [(set_attr "type" "vecsimple")])
 228
 229 (define_insn "addv8hi3"
 230   [(set (match_operand:V8HI 0 "register_operand" "=v")
 231         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 232                    (match_operand:V8HI 2 "register_operand" "v")))]
 233   "TARGET_ALTIVEC"
 234   "vadduhm %0,%1,%2"
 235   [(set_attr "type" "vecsimple")])
 236
 237 (define_insn "addv4si3"
 238   [(set (match_operand:V4SI 0 "register_operand" "=v")
 239         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 240                    (match_operand:V4SI 2 "register_operand" "v")))]
 241   "TARGET_ALTIVEC"
 242   "vadduwm %0,%1,%2"
 243   [(set_attr "type" "vecsimple")])
 244
 245 (define_insn "addv4sf3"
 246   [(set (match_operand:V4SF 0 "register_operand" "=v")
 247         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 248                    (match_operand:V4SF 2 "register_operand" "v")))]
 249   "TARGET_ALTIVEC"
 250   "vaddfp %0,%1,%2"
 251   [(set_attr "type" "vecfloat")])
 252
 253 (define_insn "altivec_vaddcuw"
 254   [(set (match_operand:V4SI 0 "register_operand" "=v")
 255         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 256                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 257   "TARGET_ALTIVEC"
 258   "vaddcuw %0,%1,%2"
 259   [(set_attr "type" "vecsimple")])
 260
 261 (define_insn "altivec_vaddubs"
 262   [(set (match_operand:V16QI 0 "register_operand" "=v")
 263         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 264                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 265    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 266   "TARGET_ALTIVEC"
 267   "vaddubs %0,%1,%2"
 268   [(set_attr "type" "vecsimple")])
 269
 270 (define_insn "altivec_vaddsbs"
 271   [(set (match_operand:V16QI 0 "register_operand" "=v")
 272         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 273                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 274    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 275   "TARGET_ALTIVEC"
 276   "vaddsbs %0,%1,%2"
 277   [(set_attr "type" "vecsimple")])
 278
 279 (define_insn "altivec_vadduhs"
 280   [(set (match_operand:V8HI 0 "register_operand" "=v")
 281         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 282                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 283    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 284   "TARGET_ALTIVEC"
 285   "vadduhs %0,%1,%2"
 286   [(set_attr "type" "vecsimple")])
 287
 288 (define_insn "altivec_vaddshs"
 289   [(set (match_operand:V8HI 0 "register_operand" "=v")
 290         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 291                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 292    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 293   "TARGET_ALTIVEC"
 294   "vaddshs %0,%1,%2"
 295   [(set_attr "type" "vecsimple")])
 296
 297 (define_insn "altivec_vadduws"
 298   [(set (match_operand:V4SI 0 "register_operand" "=v")
 299         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 300                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 301    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 302   "TARGET_ALTIVEC"
 303   "vadduws %0,%1,%2"
 304   [(set_attr "type" "vecsimple")])
 305
 306 (define_insn "altivec_vaddsws"
 307   [(set (match_operand:V4SI 0 "register_operand" "=v")
 308         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 309                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 310    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 311   "TARGET_ALTIVEC"
 312   "vaddsws %0,%1,%2"
 313   [(set_attr "type" "vecsimple")])
 314
 315 (define_insn "andv4si3"
 316   [(set (match_operand:V4SI 0 "register_operand" "=v")
 317         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 318                   (match_operand:V4SI 2 "register_operand" "v")))]
 319   "TARGET_ALTIVEC"
 320   "vand %0,%1,%2"
 321   [(set_attr "type" "vecsimple")])
 322
 323 (define_insn "altivec_vandc"
 324   [(set (match_operand:V4SI 0 "register_operand" "=v")
 325         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 326                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 327   "TARGET_ALTIVEC"
 328   "vandc %0,%1,%2"
 329   [(set_attr "type" "vecsimple")])
 330
 331 (define_insn "altivec_vavgub"
 332   [(set (match_operand:V16QI 0 "register_operand" "=v")
 333         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 334                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 335   "TARGET_ALTIVEC"
 336   "vavgub %0,%1,%2"
 337   [(set_attr "type" "vecsimple")])
 338
 339 (define_insn "altivec_vavgsb"
 340   [(set (match_operand:V16QI 0 "register_operand" "=v")
 341         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 342                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 343   "TARGET_ALTIVEC"
 344   "vavgsb %0,%1,%2"
 345   [(set_attr "type" "vecsimple")])
 346
 347 (define_insn "altivec_vavguh"
 348   [(set (match_operand:V8HI 0 "register_operand" "=v")
 349         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 350                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 351   "TARGET_ALTIVEC"
 352   "vavguh %0,%1,%2"
 353   [(set_attr "type" "vecsimple")])
 354
 355 (define_insn "altivec_vavgsh"
 356   [(set (match_operand:V8HI 0 "register_operand" "=v")
 357         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 358                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 359   "TARGET_ALTIVEC"
 360   "vavgsh %0,%1,%2"
 361   [(set_attr "type" "vecsimple")])
 362
 363 (define_insn "altivec_vavguw"
 364   [(set (match_operand:V4SI 0 "register_operand" "=v")
 365         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 366                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 367   "TARGET_ALTIVEC"
 368   "vavguw %0,%1,%2"
 369   [(set_attr "type" "vecsimple")])
 370
 371 (define_insn "altivec_vavgsw"
 372   [(set (match_operand:V4SI 0 "register_operand" "=v")
 373         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 374                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 375   "TARGET_ALTIVEC"
 376   "vavgsw %0,%1,%2"
 377   [(set_attr "type" "vecsimple")])
 378
 379 (define_insn "altivec_vcmpbfp"
 380   [(set (match_operand:V4SI 0 "register_operand" "=v")
 381         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 382                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 383   "TARGET_ALTIVEC"
 384   "vcmpbfp %0,%1,%2"
 385   [(set_attr "type" "veccmp")])
 386
 387 (define_insn "altivec_vcmpequb"
 388   [(set (match_operand:V16QI 0 "register_operand" "=v")
 389         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 390                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 391   "TARGET_ALTIVEC"
 392   "vcmpequb %0,%1,%2"
 393   [(set_attr "type" "vecsimple")])
 394
 395 (define_insn "altivec_vcmpequh"
 396   [(set (match_operand:V8HI 0 "register_operand" "=v")
 397         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 398                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 399   "TARGET_ALTIVEC"
 400   "vcmpequh %0,%1,%2"
 401   [(set_attr "type" "vecsimple")])
 402
 403 (define_insn "altivec_vcmpequw"
 404   [(set (match_operand:V4SI 0 "register_operand" "=v")
 405         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 406                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 407   "TARGET_ALTIVEC"
 408   "vcmpequw %0,%1,%2"
 409   [(set_attr "type" "vecsimple")])
 410
 411 (define_insn "altivec_vcmpeqfp"
 412   [(set (match_operand:V4SI 0 "register_operand" "=v")
 413         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 414                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 415   "TARGET_ALTIVEC"
 416   "vcmpeqfp %0,%1,%2"
 417   [(set_attr "type" "veccmp")])
 418
 419 (define_insn "altivec_vcmpgefp"
 420   [(set (match_operand:V4SI 0 "register_operand" "=v")
 421         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 422                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 423   "TARGET_ALTIVEC"
 424   "vcmpgefp %0,%1,%2"
 425   [(set_attr "type" "veccmp")])
 426
 427 (define_insn "altivec_vcmpgtub"
 428   [(set (match_operand:V16QI 0 "register_operand" "=v")
 429         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 430                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 431   "TARGET_ALTIVEC"
 432   "vcmpgtub %0,%1,%2"
 433   [(set_attr "type" "vecsimple")])
 434
 435 (define_insn "altivec_vcmpgtsb"
 436   [(set (match_operand:V16QI 0 "register_operand" "=v")
 437         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 438                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 439   "TARGET_ALTIVEC"
 440   "vcmpgtsb %0,%1,%2"
 441   [(set_attr "type" "vecsimple")])
 442
 443 (define_insn "altivec_vcmpgtuh"
 444   [(set (match_operand:V8HI 0 "register_operand" "=v")
 445         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 446                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 447   "TARGET_ALTIVEC"
 448   "vcmpgtuh %0,%1,%2"
 449   [(set_attr "type" "vecsimple")])
 450
 451 (define_insn "altivec_vcmpgtsh"
 452   [(set (match_operand:V8HI 0 "register_operand" "=v")
 453         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 454                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 455   "TARGET_ALTIVEC"
 456   "vcmpgtsh %0,%1,%2"
 457   [(set_attr "type" "vecsimple")])
 458
 459 (define_insn "altivec_vcmpgtuw"
 460   [(set (match_operand:V4SI 0 "register_operand" "=v")
 461         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 462                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 463   "TARGET_ALTIVEC"
 464   "vcmpgtuw %0,%1,%2"
 465   [(set_attr "type" "vecsimple")])
 466
 467 (define_insn "altivec_vcmpgtsw"
 468   [(set (match_operand:V4SI 0 "register_operand" "=v")
 469         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 470                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 471   "TARGET_ALTIVEC"
 472   "vcmpgtsw %0,%1,%2"
 473   [(set_attr "type" "vecsimple")])
 474
 475 (define_insn "altivec_vcmpgtfp"
 476   [(set (match_operand:V4SI 0 "register_operand" "=v")
 477         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 478                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 479   "TARGET_ALTIVEC"
 480   "vcmpgtfp %0,%1,%2"
 481   [(set_attr "type" "veccmp")])
 482
 483 ;; Fused multiply add
 484 (define_insn "altivec_vmaddfp"
 485   [(set (match_operand:V4SF 0 "register_operand" "=v")
 486         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 487                               (match_operand:V4SF 2 "register_operand" "v"))
 488                    (match_operand:V4SF 3 "register_operand" "v")))]
 489   "TARGET_ALTIVEC"
 490   "vmaddfp %0,%1,%2,%3"
 491   [(set_attr "type" "vecfloat")])
 492
 493 ;; The unspec here is a vec splat of 0. We do multiply as a fused
 494 ;; multiply-add with an add of a 0 vector.
 495
 496 (define_expand "mulv4sf3"
 497   [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142))
 498    (set (match_operand:V4SF 0 "register_operand" "=v")
 499         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 500                               (match_operand:V4SF 2 "register_operand" "v"))
 501                    (match_dup 3)))]
 502   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 503   "
 504 { operands[3] = gen_reg_rtx (V4SFmode); }")
 505
 506 ;; Fused multiply subtract
 507 (define_insn "altivec_vnmsubfp"
 508   [(set (match_operand:V4SF 0 "register_operand" "=v")
 509         (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 510                                (match_operand:V4SF 2 "register_operand" "v"))
 511                     (match_operand:V4SF 3 "register_operand" "v")))]
 512   "TARGET_ALTIVEC"
 513   "vnmsubfp %0,%1,%2,%3"
 514   [(set_attr "type" "vecfloat")])
 515
 516
 517 (define_insn "altivec_vmsumubm"
 518   [(set (match_operand:V4SI 0 "register_operand" "=v")
 519         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 520                       (match_operand:V16QI 2 "register_operand" "v")
 521                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 522   "TARGET_ALTIVEC"
 523   "vmsumubm %0, %1, %2, %3"
 524   [(set_attr "type" "veccomplex")])
 525
 526 (define_insn "altivec_vmsummbm"
 527   [(set (match_operand:V4SI 0 "register_operand" "=v")
 528         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 529                       (match_operand:V16QI 2 "register_operand" "v")
 530                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 531   "TARGET_ALTIVEC"
 532   "vmsumubm %0, %1, %2, %3"
 533   [(set_attr "type" "veccomplex")])
 534
 535 (define_insn "altivec_vmsumuhm"
 536   [(set (match_operand:V4SI 0 "register_operand" "=v")
 537         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 538                       (match_operand:V8HI 2 "register_operand" "v")
 539                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 540   "TARGET_ALTIVEC"
 541   "vmsumuhm %0, %1, %2, %3"
 542   [(set_attr "type" "veccomplex")])
 543
 544 (define_insn "altivec_vmsumshm"
 545   [(set (match_operand:V4SI 0 "register_operand" "=v")
 546         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 547                       (match_operand:V8HI 2 "register_operand" "v")
 548                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 549   "TARGET_ALTIVEC"
 550   "vmsumshm %0, %1, %2, %3"
 551   [(set_attr "type" "veccomplex")])
 552
 553 (define_insn "altivec_vmsumuhs"
 554   [(set (match_operand:V4SI 0 "register_operand" "=v")
 555         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 556                       (match_operand:V8HI 2 "register_operand" "v")
 557                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 558    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 559   "TARGET_ALTIVEC"
 560   "vmsumuhs %0, %1, %2, %3"
 561   [(set_attr "type" "veccomplex")])
 562
 563 (define_insn "altivec_vmsumshs"
 564   [(set (match_operand:V4SI 0 "register_operand" "=v")
 565         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 566                       (match_operand:V8HI 2 "register_operand" "v")
 567                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 568    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 569   "TARGET_ALTIVEC"
 570   "vmsumshs %0, %1, %2, %3"
 571   [(set_attr "type" "veccomplex")])
 572
 573 (define_insn "umaxv16qi3"
 574   [(set (match_operand:V16QI 0 "register_operand" "=v")
 575         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 576                     (match_operand:V16QI 2 "register_operand" "v")))]
 577   "TARGET_ALTIVEC"
 578   "vmaxub %0,%1,%2"
 579   [(set_attr "type" "vecsimple")])
 580
 581 (define_insn "smaxv16qi3"
 582   [(set (match_operand:V16QI 0 "register_operand" "=v")
 583         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 584                     (match_operand:V16QI 2 "register_operand" "v")))]
 585   "TARGET_ALTIVEC"
 586   "vmaxsb %0,%1,%2"
 587   [(set_attr "type" "vecsimple")])
 588
 589 (define_insn "umaxv8hi3"
 590   [(set (match_operand:V8HI 0 "register_operand" "=v")
 591         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 592                    (match_operand:V8HI 2 "register_operand" "v")))]
 593   "TARGET_ALTIVEC"
 594   "vmaxuh %0,%1,%2"
 595   [(set_attr "type" "vecsimple")])
 596
 597 (define_insn "smaxv8hi3"
 598   [(set (match_operand:V8HI 0 "register_operand" "=v")
 599         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 600                    (match_operand:V8HI 2 "register_operand" "v")))]
 601   "TARGET_ALTIVEC"
 602   "vmaxsh %0,%1,%2"
 603   [(set_attr "type" "vecsimple")])
 604
 605 (define_insn "umaxv4si3"
 606   [(set (match_operand:V4SI 0 "register_operand" "=v")
 607         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 608                    (match_operand:V4SI 2 "register_operand" "v")))]
 609   "TARGET_ALTIVEC"
 610   "vmaxuw %0,%1,%2"
 611   [(set_attr "type" "vecsimple")])
 612
 613 (define_insn "smaxv4si3"
 614   [(set (match_operand:V4SI 0 "register_operand" "=v")
 615         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 616                    (match_operand:V4SI 2 "register_operand" "v")))]
 617   "TARGET_ALTIVEC"
 618   "vmaxsw %0,%1,%2"
 619   [(set_attr "type" "vecsimple")])
 620
 621 (define_insn "smaxv4sf3"
 622   [(set (match_operand:V4SF 0 "register_operand" "=v")
 623         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 624                    (match_operand:V4SF 2 "register_operand" "v")))]
 625   "TARGET_ALTIVEC"
 626   "vmaxfp %0,%1,%2"
 627   [(set_attr "type" "veccmp")])
 628
 629 (define_insn "altivec_vmhaddshs"
 630   [(set (match_operand:V8HI 0 "register_operand" "=v")
 631         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 632                       (match_operand:V8HI 2 "register_operand" "v")
 633                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 634    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 635   "TARGET_ALTIVEC"
 636   "vmhaddshs %0, %1, %2, %3"
 637   [(set_attr "type" "veccomplex")])
 638 (define_insn "altivec_vmhraddshs"
 639   [(set (match_operand:V8HI 0 "register_operand" "=v")
 640         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 641                       (match_operand:V8HI 2 "register_operand" "v")
 642                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 643    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 644   "TARGET_ALTIVEC"
 645   "vmhraddshs %0, %1, %2, %3"
 646   [(set_attr "type" "veccomplex")])
 647 (define_insn "altivec_vmladduhm"
 648   [(set (match_operand:V8HI 0 "register_operand" "=v")
 649         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 650                       (match_operand:V8HI 2 "register_operand" "v")
 651                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 652   "TARGET_ALTIVEC"
 653   "vmladduhm %0, %1, %2, %3"
 654   [(set_attr "type" "veccomplex")])
 655
 656 (define_insn "altivec_vmrghb"
 657   [(set (match_operand:V16QI 0 "register_operand" "=v")
 658         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 659                                            (parallel [(const_int 8)
 660                                                       (const_int 9)
 661                                                       (const_int 10)
 662                                                       (const_int 11)
 663                                                       (const_int 12)
 664                                                       (const_int 13)
 665                                                       (const_int 14)
 666                                                       (const_int 15)
 667                                                       (const_int 0)
 668                                                       (const_int 1)
 669                                                       (const_int 2)
 670                                                       (const_int 3)
 671                                                       (const_int 4)
 672                                                       (const_int 5)
 673                                                       (const_int 6)
 674                                                       (const_int 7)]))
 675                       (match_operand:V16QI 2 "register_operand" "v")
 676                       (const_int 255)))]
 677   "TARGET_ALTIVEC"
 678   "vmrghb %0,%1,%2"
 679   [(set_attr "type" "vecperm")])
 680
 681 (define_insn "altivec_vmrghh"
 682   [(set (match_operand:V8HI 0 "register_operand" "=v")
 683         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 684                                            (parallel [(const_int 4)
 685                                                       (const_int 5)
 686                                                       (const_int 6)
 687                                                       (const_int 7)
 688                                                       (const_int 0)
 689                                                       (const_int 1)
 690                                                       (const_int 2)
 691                                                       (const_int 3)]))
 692                       (match_operand:V8HI 2 "register_operand" "v")
 693                       (const_int 15)))]
 694   "TARGET_ALTIVEC"
 695   "vmrghh %0,%1,%2"
 696   [(set_attr "type" "vecperm")])
 697
 698 (define_insn "altivec_vmrghw"
 699   [(set (match_operand:V4SI 0 "register_operand" "=v")
 700         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 701                                          (parallel [(const_int 2)
 702                                                     (const_int 3)
 703                                                     (const_int 0)
 704                                                     (const_int 1)]))
 705                       (match_operand:V4SI 2 "register_operand" "v")
 706                       (const_int 12)))]
 707   "TARGET_ALTIVEC"
 708   "vmrghw %0,%1,%2"
 709   [(set_attr "type" "vecperm")])
 710
 711 (define_insn "altivec_vmrglb"
 712   [(set (match_operand:V16QI 0 "register_operand" "=v")
 713         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 714                                            (parallel [(const_int 0)
 715                                                       (const_int 1)
 716                                                       (const_int 2)
 717                                                       (const_int 3)
 718                                                       (const_int 4)
 719                                                       (const_int 5)
 720                                                       (const_int 6)
 721                                                       (const_int 7)
 722                                                       (const_int 8)
 723                                                       (const_int 9)
 724                                                       (const_int 10)
 725                                                       (const_int 11)
 726                                                       (const_int 12)
 727                                                       (const_int 13)
 728                                                       (const_int 14)
 729                                                       (const_int 15)]))
 730                       (match_operand:V16QI 1 "register_operand" "v")
 731                       (const_int 255)))]
 732   "TARGET_ALTIVEC"
 733   "vmrglb %0,%1,%2"
 734   [(set_attr "type" "vecperm")])
 735
 736 (define_insn "altivec_vmrglh"
 737   [(set (match_operand:V8HI 0 "register_operand" "=v")
 738         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 739                                            (parallel [(const_int 0)
 740                                                       (const_int 1)
 741                                                       (const_int 2)
 742                                                       (const_int 3)
 743                                                       (const_int 4)
 744                                                       (const_int 5)
 745                                                       (const_int 6)
 746                                                       (const_int 7)]))
 747                       (match_operand:V8HI 1 "register_operand" "v")
 748                       (const_int 15)))]
 749   "TARGET_ALTIVEC"
 750   "vmrglh %0,%1,%2"
 751   [(set_attr "type" "vecperm")])
 752
 753 (define_insn "altivec_vmrglw"
 754   [(set (match_operand:V4SI 0 "register_operand" "=v")
 755         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 756                                          (parallel [(const_int 0)
 757                                                     (const_int 1)
 758                                                     (const_int 2)
 759                                                     (const_int 3)]))
 760                       (match_operand:V4SI 1 "register_operand" "v")
 761                       (const_int 12)))]
 762   "TARGET_ALTIVEC"
 763   "vmrglw %0,%1,%2"
 764   [(set_attr "type" "vecperm")])
 765
 766 (define_insn "uminv16qi3"
 767   [(set (match_operand:V16QI 0 "register_operand" "=v")
 768         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 769                     (match_operand:V16QI 2 "register_operand" "v")))]
 770   "TARGET_ALTIVEC"
 771   "vminub %0,%1,%2"
 772   [(set_attr "type" "vecsimple")])
 773
 774 (define_insn "sminv16qi3"
 775   [(set (match_operand:V16QI 0 "register_operand" "=v")
 776         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 777                     (match_operand:V16QI 2 "register_operand" "v")))]
 778   "TARGET_ALTIVEC"
 779   "vminsb %0,%1,%2"
 780   [(set_attr "type" "vecsimple")])
 781
 782 (define_insn "uminv8hi3"
 783   [(set (match_operand:V8HI 0 "register_operand" "=v")
 784         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 785                    (match_operand:V8HI 2 "register_operand" "v")))]
 786   "TARGET_ALTIVEC"
 787   "vminuh %0,%1,%2"
 788   [(set_attr "type" "vecsimple")])
 789
 790 (define_insn "sminv8hi3"
 791   [(set (match_operand:V8HI 0 "register_operand" "=v")
 792         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 793                    (match_operand:V8HI 2 "register_operand" "v")))]
 794   "TARGET_ALTIVEC"
 795   "vminsh %0,%1,%2"
 796   [(set_attr "type" "vecsimple")])
 797
 798 (define_insn "uminv4si3"
 799   [(set (match_operand:V4SI 0 "register_operand" "=v")
 800         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 801                    (match_operand:V4SI 2 "register_operand" "v")))]
 802   "TARGET_ALTIVEC"
 803   "vminuw %0,%1,%2"
 804   [(set_attr "type" "vecsimple")])
 805
 806 (define_insn "sminv4si3"
 807   [(set (match_operand:V4SI 0 "register_operand" "=v")
 808         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 809                    (match_operand:V4SI 2 "register_operand" "v")))]
 810   "TARGET_ALTIVEC"
 811   "vminsw %0,%1,%2"
 812   [(set_attr "type" "vecsimple")])
 813
 814 (define_insn "sminv4sf3"
 815   [(set (match_operand:V4SF 0 "register_operand" "=v")
 816         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 817                    (match_operand:V4SF 2 "register_operand" "v")))]
 818   "TARGET_ALTIVEC"
 819   "vminfp %0,%1,%2"
 820   [(set_attr "type" "veccmp")])
 821
 822 (define_insn "altivec_vmuleub"
 823   [(set (match_operand:V8HI 0 "register_operand" "=v")
 824         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 825                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 826   "TARGET_ALTIVEC"
 827   "vmuleub %0,%1,%2"
 828   [(set_attr "type" "veccomplex")])
 829
 830 (define_insn "altivec_vmulesb"
 831   [(set (match_operand:V8HI 0 "register_operand" "=v")
 832         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 833                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 834   "TARGET_ALTIVEC"
 835   "vmulesb %0,%1,%2"
 836   [(set_attr "type" "veccomplex")])
 837
 838 (define_insn "altivec_vmuleuh"
 839   [(set (match_operand:V4SI 0 "register_operand" "=v")
 840         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 841                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 842   "TARGET_ALTIVEC"
 843   "vmuleuh %0,%1,%2"
 844   [(set_attr "type" "veccomplex")])
 845
 846 (define_insn "altivec_vmulesh"
 847   [(set (match_operand:V4SI 0 "register_operand" "=v")
 848         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 849                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 850   "TARGET_ALTIVEC"
 851   "vmulesh %0,%1,%2"
 852   [(set_attr "type" "veccomplex")])
 853
 854 (define_insn "altivec_vmuloub"
 855   [(set (match_operand:V8HI 0 "register_operand" "=v")
 856         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 857                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 858   "TARGET_ALTIVEC"
 859   "vmuloub %0,%1,%2"
 860   [(set_attr "type" "veccomplex")])
 861
 862 (define_insn "altivec_vmulosb"
 863   [(set (match_operand:V8HI 0 "register_operand" "=v")
 864         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 865                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 866   "TARGET_ALTIVEC"
 867   "vmulosb %0,%1,%2"
 868   [(set_attr "type" "veccomplex")])
 869
 870 (define_insn "altivec_vmulouh"
 871   [(set (match_operand:V4SI 0 "register_operand" "=v")
 872         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 873                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 874   "TARGET_ALTIVEC"
 875   "vmulouh %0,%1,%2"
 876   [(set_attr "type" "veccomplex")])
 877
 878 (define_insn "altivec_vmulosh"
 879   [(set (match_operand:V4SI 0 "register_operand" "=v")
 880         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 881                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 882   "TARGET_ALTIVEC"
 883   "vmulosh %0,%1,%2"
 884   [(set_attr "type" "veccomplex")])
 885
 886 (define_insn "altivec_vnor"
 887   [(set (match_operand:V4SI 0 "register_operand" "=v")
 888         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 889                             (match_operand:V4SI 2 "register_operand" "v"))))]
 890   "TARGET_ALTIVEC"
 891   "vnor %0,%1,%2"
 892   [(set_attr "type" "vecsimple")])
 893
 894 (define_insn "iorv4si3"
 895   [(set (match_operand:V4SI 0 "register_operand" "=v")
 896         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 897                   (match_operand:V4SI 2 "register_operand" "v")))]
 898   "TARGET_ALTIVEC"
 899   "vor %0,%1,%2"
 900   [(set_attr "type" "vecsimple")])
 901
 902 (define_insn "altivec_vpkuhum"
 903   [(set (match_operand:V16QI 0 "register_operand" "=v")
 904         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 905                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 906   "TARGET_ALTIVEC"
 907   "vpkuhum %0,%1,%2"
 908   [(set_attr "type" "vecperm")])
 909
 910 (define_insn "altivec_vpkuwum"
 911   [(set (match_operand:V8HI 0 "register_operand" "=v")
 912         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 913                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
 914   "TARGET_ALTIVEC"
 915   "vpkuwum %0,%1,%2"
 916   [(set_attr "type" "vecperm")])
 917
 918 (define_insn "altivec_vpkpx"
 919   [(set (match_operand:V8HI 0 "register_operand" "=v")
 920         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 921                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
 922   "TARGET_ALTIVEC"
 923   "vpkpx %0,%1,%2"
 924   [(set_attr "type" "vecperm")])
 925
 926 (define_insn "altivec_vpkuhss"
 927   [(set (match_operand:V16QI 0 "register_operand" "=v")
 928         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 929                        (match_operand:V8HI 2 "register_operand" "v")] 96))
 930    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 931   "TARGET_ALTIVEC"
 932   "vpkuhss %0,%1,%2"
 933   [(set_attr "type" "vecperm")])
 934
 935 (define_insn "altivec_vpkshss"
 936   [(set (match_operand:V16QI 0 "register_operand" "=v")
 937         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 938                        (match_operand:V8HI 2 "register_operand" "v")] 97))
 939    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 940   "TARGET_ALTIVEC"
 941   "vpkshss %0,%1,%2"
 942   [(set_attr "type" "vecperm")])
 943
 944 (define_insn "altivec_vpkuwss"
 945   [(set (match_operand:V8HI 0 "register_operand" "=v")
 946         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 947                       (match_operand:V4SI 2 "register_operand" "v")] 98))
 948    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 949   "TARGET_ALTIVEC"
 950   "vpkuwss %0,%1,%2"
 951   [(set_attr "type" "vecperm")])
 952
 953 (define_insn "altivec_vpkswss"
 954   [(set (match_operand:V8HI 0 "register_operand" "=v")
 955         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 956                       (match_operand:V4SI 2 "register_operand" "v")] 99))
 957    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 958   "TARGET_ALTIVEC"
 959   "vpkswss %0,%1,%2"
 960   [(set_attr "type" "vecperm")])
 961
 962 (define_insn "altivec_vpkuhus"
 963   [(set (match_operand:V16QI 0 "register_operand" "=v")
 964         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 965                        (match_operand:V8HI 2 "register_operand" "v")] 100))
 966    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 967   "TARGET_ALTIVEC"
 968   "vpkuhus %0,%1,%2"
 969   [(set_attr "type" "vecperm")])
 970
 971 (define_insn "altivec_vpkshus"
 972   [(set (match_operand:V16QI 0 "register_operand" "=v")
 973         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 974                        (match_operand:V8HI 2 "register_operand" "v")] 101))
 975    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 976   "TARGET_ALTIVEC"
 977   "vpkshus %0,%1,%2"
 978   [(set_attr "type" "vecperm")])
 979
 980 (define_insn "altivec_vpkuwus"
 981   [(set (match_operand:V8HI 0 "register_operand" "=v")
 982         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 983                       (match_operand:V4SI 2 "register_operand" "v")] 102))
 984    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 985   "TARGET_ALTIVEC"
 986   "vpkuwus %0,%1,%2"
 987   [(set_attr "type" "vecperm")])
 988
 989 (define_insn "altivec_vpkswus"
 990   [(set (match_operand:V8HI 0 "register_operand" "=v")
 991         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
 992                       (match_operand:V4SI 2 "register_operand" "v")] 103))
 993    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 994   "TARGET_ALTIVEC"
 995   "vpkswus %0,%1,%2"
 996   [(set_attr "type" "vecperm")])
 997
 998 (define_insn "altivec_vrlb"
 999   [(set (match_operand:V16QI 0 "register_operand" "=v")
1000         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1001                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1002   "TARGET_ALTIVEC"
1003   "vrlb %0,%1,%2"
1004   [(set_attr "type" "vecsimple")])
1005
1006 (define_insn "altivec_vrlh"
1007   [(set (match_operand:V8HI 0 "register_operand" "=v")
1008         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1009                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1010   "TARGET_ALTIVEC"
1011   "vrlh %0,%1,%2"
1012   [(set_attr "type" "vecsimple")])
1013
1014 (define_insn "altivec_vrlw"
1015   [(set (match_operand:V4SI 0 "register_operand" "=v")
1016         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1017                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1018   "TARGET_ALTIVEC"
1019   "vrlw %0,%1,%2"
1020   [(set_attr "type" "vecsimple")])
1021
1022 (define_insn "altivec_vslb"
1023   [(set (match_operand:V16QI 0 "register_operand" "=v")
1024         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1025                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1026   "TARGET_ALTIVEC"
1027   "vslb %0,%1,%2"
1028   [(set_attr "type" "vecsimple")])
1029
1030 (define_insn "altivec_vslh"
1031   [(set (match_operand:V8HI 0 "register_operand" "=v")
1032         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1033                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1034   "TARGET_ALTIVEC"
1035   "vslh %0,%1,%2"
1036   [(set_attr "type" "vecsimple")])
1037
1038 (define_insn "altivec_vslw"
1039   [(set (match_operand:V4SI 0 "register_operand" "=v")
1040         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1041                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1042   "TARGET_ALTIVEC"
1043   "vslw %0,%1,%2"
1044   [(set_attr "type" "vecsimple")])
1045
1046 (define_insn "altivec_vsl"
1047   [(set (match_operand:V4SI 0 "register_operand" "=v")
1048         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1049                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1050   "TARGET_ALTIVEC"
1051   "vsl %0,%1,%2"
1052   [(set_attr "type" "vecperm")])
1053
1054 (define_insn "altivec_vslo"
1055   [(set (match_operand:V4SI 0 "register_operand" "=v")
1056         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1057                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1058   "TARGET_ALTIVEC"
1059   "vslo %0,%1,%2"
1060   [(set_attr "type" "vecperm")])
1061
1062 (define_insn "altivec_vsrb"
1063   [(set (match_operand:V16QI 0 "register_operand" "=v")
1064         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1065                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1066   "TARGET_ALTIVEC"
1067   "vsrb %0,%1,%2"
1068   [(set_attr "type" "vecsimple")])
1069
1070 (define_insn "altivec_vsrh"
1071   [(set (match_operand:V8HI 0 "register_operand" "=v")
1072         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1073                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1074   "TARGET_ALTIVEC"
1075   "vsrh %0,%1,%2"
1076   [(set_attr "type" "vecsimple")])
1077
1078 (define_insn "altivec_vsrw"
1079   [(set (match_operand:V4SI 0 "register_operand" "=v")
1080         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1081                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1082   "TARGET_ALTIVEC"
1083   "vsrw %0,%1,%2"
1084   [(set_attr "type" "vecsimple")])
1085
1086 (define_insn "altivec_vsrab"
1087   [(set (match_operand:V16QI 0 "register_operand" "=v")
1088         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1089                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1090   "TARGET_ALTIVEC"
1091   "vsrab %0,%1,%2"
1092   [(set_attr "type" "vecsimple")])
1093
1094 (define_insn "altivec_vsrah"
1095   [(set (match_operand:V8HI 0 "register_operand" "=v")
1096         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1097                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1098   "TARGET_ALTIVEC"
1099   "vsrah %0,%1,%2"
1100   [(set_attr "type" "vecsimple")])
1101
1102 (define_insn "altivec_vsraw"
1103   [(set (match_operand:V4SI 0 "register_operand" "=v")
1104         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1105                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1106   "TARGET_ALTIVEC"
1107   "vsraw %0,%1,%2"
1108   [(set_attr "type" "vecsimple")])
1109
1110 (define_insn "altivec_vsr"
1111   [(set (match_operand:V4SI 0 "register_operand" "=v")
1112         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1113                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1114   "TARGET_ALTIVEC"
1115   "vsr %0,%1,%2"
1116   [(set_attr "type" "vecperm")])
1117
1118 (define_insn "altivec_vsro"
1119   [(set (match_operand:V4SI 0 "register_operand" "=v")
1120         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1121                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1122   "TARGET_ALTIVEC"
1123   "vsro %0,%1,%2"
1124   [(set_attr "type" "vecperm")])
1125
1126 (define_insn "subv16qi3"
1127   [(set (match_operand:V16QI 0 "register_operand" "=v")
1128         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1129                      (match_operand:V16QI 2 "register_operand" "v")))]
1130   "TARGET_ALTIVEC"
1131   "vsububm %0,%1,%2"
1132   [(set_attr "type" "vecsimple")])
1133
1134 (define_insn "subv8hi3"
1135   [(set (match_operand:V8HI 0 "register_operand" "=v")
1136         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1137                     (match_operand:V8HI 2 "register_operand" "v")))]
1138   "TARGET_ALTIVEC"
1139   "vsubuhm %0,%1,%2"
1140   [(set_attr "type" "vecsimple")])
1141
1142 (define_insn "subv4si3"
1143   [(set (match_operand:V4SI 0 "register_operand" "=v")
1144         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1145                     (match_operand:V4SI 2 "register_operand" "v")))]
1146   "TARGET_ALTIVEC"
1147   "vsubuwm %0,%1,%2"
1148   [(set_attr "type" "vecsimple")])
1149
1150 (define_insn "subv4sf3"
1151   [(set (match_operand:V4SF 0 "register_operand" "=v")
1152         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1153                     (match_operand:V4SF 2 "register_operand" "v")))]
1154   "TARGET_ALTIVEC"
1155   "vsubfp %0,%1,%2"
1156   [(set_attr "type" "vecfloat")])
1157
1158 (define_insn "altivec_vsubcuw"
1159   [(set (match_operand:V4SI 0 "register_operand" "=v")
1160         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1161                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1162   "TARGET_ALTIVEC"
1163   "vsubcuw %0,%1,%2"
1164   [(set_attr "type" "vecsimple")])
1165
1166 (define_insn "altivec_vsububs"
1167   [(set (match_operand:V16QI 0 "register_operand" "=v")
1168         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1169                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1170    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1171   "TARGET_ALTIVEC"
1172   "vsububs %0,%1,%2"
1173   [(set_attr "type" "vecsimple")])
1174
1175 (define_insn "altivec_vsubsbs"
1176   [(set (match_operand:V16QI 0 "register_operand" "=v")
1177         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1178                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1179    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1180   "TARGET_ALTIVEC"
1181   "vsubsbs %0,%1,%2"
1182   [(set_attr "type" "vecsimple")])
1183
1184 (define_insn "altivec_vsubuhs"
1185   [(set (match_operand:V8HI 0 "register_operand" "=v")
1186         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1187                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1188    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1189   "TARGET_ALTIVEC"
1190   "vsubuhs %0,%1,%2"
1191   [(set_attr "type" "vecsimple")])
1192
1193 (define_insn "altivec_vsubshs"
1194   [(set (match_operand:V8HI 0 "register_operand" "=v")
1195         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1196                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1197    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1198   "TARGET_ALTIVEC"
1199   "vsubshs %0,%1,%2"
1200   [(set_attr "type" "vecsimple")])
1201
1202 (define_insn "altivec_vsubuws"
1203   [(set (match_operand:V4SI 0 "register_operand" "=v")
1204         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1205                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1206    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1207   "TARGET_ALTIVEC"
1208   "vsubuws %0,%1,%2"
1209   [(set_attr "type" "vecsimple")])
1210
1211 (define_insn "altivec_vsubsws"
1212   [(set (match_operand:V4SI 0 "register_operand" "=v")
1213         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1214                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1215    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1216   "TARGET_ALTIVEC"
1217   "vsubsws %0,%1,%2"
1218   [(set_attr "type" "vecsimple")])
1219
1220 (define_insn "altivec_vsum4ubs"
1221   [(set (match_operand:V4SI 0 "register_operand" "=v")
1222         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1223                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1224    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1225   "TARGET_ALTIVEC"
1226   "vsum4ubs %0,%1,%2"
1227   [(set_attr "type" "veccomplex")])
1228
1229 (define_insn "altivec_vsum4sbs"
1230   [(set (match_operand:V4SI 0 "register_operand" "=v")
1231         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1232                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1233    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1234   "TARGET_ALTIVEC"
1235   "vsum4sbs %0,%1,%2"
1236   [(set_attr "type" "veccomplex")])
1237
1238 (define_insn "altivec_vsum4shs"
1239   [(set (match_operand:V4SI 0 "register_operand" "=v")
1240         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1241                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1242    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1243   "TARGET_ALTIVEC"
1244   "vsum4shs %0,%1,%2"
1245   [(set_attr "type" "veccomplex")])
1246
1247 (define_insn "altivec_vsum2sws"
1248   [(set (match_operand:V4SI 0 "register_operand" "=v")
1249         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1250                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1251    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1252   "TARGET_ALTIVEC"
1253   "vsum2sws %0,%1,%2"
1254   [(set_attr "type" "veccomplex")])
1255
1256 (define_insn "altivec_vsumsws"
1257   [(set (match_operand:V4SI 0 "register_operand" "=v")
1258         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1259                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1260    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1261   "TARGET_ALTIVEC"
1262   "vsumsws %0,%1,%2"
1263   [(set_attr "type" "veccomplex")])
1264
1265 (define_insn "xorv4si3"
1266   [(set (match_operand:V4SI 0 "register_operand" "=v")
1267         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1268                   (match_operand:V4SI 2 "register_operand" "v")))]
1269   "TARGET_ALTIVEC"
1270   "vxor %0,%1,%2"
1271   [(set_attr "type" "vecsimple")])
1272
1273 (define_insn "altivec_vspltb"
1274   [(set (match_operand:V16QI 0 "register_operand" "=v")
1275         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1276                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1277   "TARGET_ALTIVEC"
1278   "vspltb %0,%1,%2"
1279   [(set_attr "type" "vecperm")])
1280
1281 (define_insn "altivec_vsplth"
1282   [(set (match_operand:V8HI 0 "register_operand" "=v")
1283         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1284                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1285   "TARGET_ALTIVEC"
1286   "vsplth %0,%1,%2"
1287   [(set_attr "type" "vecperm")])
1288
1289 (define_insn "altivec_vspltw"
1290   [(set (match_operand:V4SI 0 "register_operand" "=v")
1291         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1292                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1293   "TARGET_ALTIVEC"
1294   "vspltw %0,%1,%2"
1295   [(set_attr "type" "vecperm")])
1296
1297 (define_insn "altivec_vspltisb"
1298   [(set (match_operand:V16QI 0 "register_operand" "=v")
1299         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))]
1300   "TARGET_ALTIVEC"
1301   "vspltisb %0, %1"
1302   [(set_attr "type" "vecsimple")])
1303
1304
1305 (define_insn "altivec_vspltish"
1306   [(set (match_operand:V8HI 0 "register_operand" "=v")
1307         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))]
1308   "TARGET_ALTIVEC"
1309   "vspltish %0, %1"
1310   [(set_attr "type" "vecsimple")])
1311
1312 (define_insn "altivec_vspltisw"
1313   [(set (match_operand:V4SI 0 "register_operand" "=v")
1314         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))]
1315   "TARGET_ALTIVEC"
1316   "vspltisw %0, %1"
1317   [(set_attr "type" "vecsimple")])
1318
1319 (define_insn ""
1320   [(set (match_operand:V4SF 0 "register_operand" "=v")
1321         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1322   "TARGET_ALTIVEC"
1323   "vspltisw %0, %1"
1324   [(set_attr "type" "vecsimple")])
1325
1326 (define_insn "ftruncv4sf2"
1327   [(set (match_operand:V4SF 0 "register_operand" "=v")
1328         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1329   "TARGET_ALTIVEC"
1330   "vrfiz %0, %1"
1331   [(set_attr "type" "vecfloat")])
1332
1333 (define_insn "altivec_vperm_4si"
1334   [(set (match_operand:V4SI 0 "register_operand" "=v")
1335         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1336                       (match_operand:V4SI 2 "register_operand" "v")
1337                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1338   "TARGET_ALTIVEC"
1339   "vperm %0,%1,%2,%3"
1340   [(set_attr "type" "vecperm")])
1341
1342 (define_insn "altivec_vperm_4sf"
1343   [(set (match_operand:V4SF 0 "register_operand" "=v")
1344         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1345                       (match_operand:V4SF 2 "register_operand" "v")
1346                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1347   "TARGET_ALTIVEC"
1348   "vperm %0,%1,%2,%3"
1349   [(set_attr "type" "vecperm")])
1350
1351 (define_insn "altivec_vperm_8hi"
1352   [(set (match_operand:V8HI 0 "register_operand" "=v")
1353         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1354                       (match_operand:V8HI 2 "register_operand" "v")
1355                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1356   "TARGET_ALTIVEC"
1357   "vperm %0,%1,%2,%3"
1358   [(set_attr "type" "vecperm")])
1359
1360 (define_insn "altivec_vperm_16qi"
1361   [(set (match_operand:V16QI 0 "register_operand" "=v")
1362         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1363                        (match_operand:V16QI 2 "register_operand" "v")
1364                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1365   "TARGET_ALTIVEC"
1366   "vperm %0,%1,%2,%3"
1367   [(set_attr "type" "vecperm")])
1368
1369 (define_insn "altivec_vrfip"
1370   [(set (match_operand:V4SF 0 "register_operand" "=v")
1371         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1372   "TARGET_ALTIVEC"
1373   "vrfip %0, %1"
1374   [(set_attr "type" "vecfloat")])
1375
1376 (define_insn "altivec_vrfin"
1377   [(set (match_operand:V4SF 0 "register_operand" "=v")
1378         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1379   "TARGET_ALTIVEC"
1380   "vrfin %0, %1"
1381   [(set_attr "type" "vecfloat")])
1382
1383 (define_insn "altivec_vrfim"
1384   [(set (match_operand:V4SF 0 "register_operand" "=v")
1385         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1386   "TARGET_ALTIVEC"
1387   "vrfim %0, %1"
1388   [(set_attr "type" "vecfloat")])
1389
1390 (define_insn "altivec_vcfux"
1391   [(set (match_operand:V4SF 0 "register_operand" "=v")
1392         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1393                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1394   "TARGET_ALTIVEC"
1395   "vcfux %0, %1, %2"
1396   [(set_attr "type" "vecfloat")])
1397
1398 (define_insn "altivec_vcfsx"
1399   [(set (match_operand:V4SF 0 "register_operand" "=v")
1400         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1401                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1402   "TARGET_ALTIVEC"
1403   "vcfsx %0, %1, %2"
1404   [(set_attr "type" "vecfloat")])
1405
1406 (define_insn "altivec_vctuxs"
1407   [(set (match_operand:V4SI 0 "register_operand" "=v")
1408         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1409                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1410    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1411   "TARGET_ALTIVEC"
1412   "vctuxs %0, %1, %2"
1413   [(set_attr "type" "vecfloat")])
1414
1415 (define_insn "altivec_vctsxs"
1416   [(set (match_operand:V4SI 0 "register_operand" "=v")
1417         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1418                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1419    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1420   "TARGET_ALTIVEC"
1421   "vctsxs %0, %1, %2"
1422   [(set_attr "type" "vecfloat")])
1423
1424 (define_insn "altivec_vlogefp"
1425   [(set (match_operand:V4SF 0 "register_operand" "=v")
1426         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1427   "TARGET_ALTIVEC"
1428   "vlogefp %0, %1"
1429   [(set_attr "type" "vecfloat")])
1430
1431 (define_insn "altivec_vexptefp"
1432   [(set (match_operand:V4SF 0 "register_operand" "=v")
1433         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1434   "TARGET_ALTIVEC"
1435   "vexptefp %0, %1"
1436   [(set_attr "type" "vecfloat")])
1437
1438 (define_insn "altivec_vrsqrtefp"
1439   [(set (match_operand:V4SF 0 "register_operand" "=v")
1440         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1441   "TARGET_ALTIVEC"
1442   "vrsqrtefp %0, %1"
1443   [(set_attr "type" "vecfloat")])
1444
1445 (define_insn "altivec_vrefp"
1446   [(set (match_operand:V4SF 0 "register_operand" "=v")
1447         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1448   "TARGET_ALTIVEC"
1449   "vrefp %0, %1"
1450   [(set_attr "type" "vecfloat")])
1451
1452 (define_insn "altivec_vsel_4si"
1453   [(set (match_operand:V4SI 0 "register_operand" "=v")
1454         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1455                       (match_operand:V4SI 2 "register_operand" "v")
1456                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1457   "TARGET_ALTIVEC"
1458   "vsel %0,%1,%2,%3"
1459   [(set_attr "type" "vecperm")])
1460
1461 (define_insn "altivec_vsel_4sf"
1462   [(set (match_operand:V4SF 0 "register_operand" "=v")
1463         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1464                       (match_operand:V4SF 2 "register_operand" "v")
1465                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1466   "TARGET_ALTIVEC"
1467   "vsel %0,%1,%2,%3"
1468   [(set_attr "type" "vecperm")])
1469
1470 (define_insn "altivec_vsel_8hi"
1471   [(set (match_operand:V8HI 0 "register_operand" "=v")
1472         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1473                       (match_operand:V8HI 2 "register_operand" "v")
1474                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1475   "TARGET_ALTIVEC"
1476   "vsel %0,%1,%2,%3"
1477   [(set_attr "type" "vecperm")])
1478
1479 (define_insn "altivec_vsel_16qi"
1480   [(set (match_operand:V16QI 0 "register_operand" "=v")
1481         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1482                        (match_operand:V16QI 2 "register_operand" "v")
1483                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1484   "TARGET_ALTIVEC"
1485   "vsel %0,%1,%2,%3"
1486   [(set_attr "type" "vecperm")])
1487
1488 (define_insn "altivec_vsldoi_4si"
1489   [(set (match_operand:V4SI 0 "register_operand" "=v")
1490         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1491                       (match_operand:V4SI 2 "register_operand" "v")
1492                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1493   "TARGET_ALTIVEC"
1494   "vsldoi %0, %1, %2, %3"
1495   [(set_attr "type" "vecperm")])
1496
1497 (define_insn "altivec_vsldoi_4sf"
1498   [(set (match_operand:V4SF 0 "register_operand" "=v")
1499         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1500                       (match_operand:V4SF 2 "register_operand" "v")
1501                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1502   "TARGET_ALTIVEC"
1503   "vsldoi %0, %1, %2, %3"
1504   [(set_attr "type" "vecperm")])
1505
1506 (define_insn "altivec_vsldoi_8hi"
1507   [(set (match_operand:V8HI 0 "register_operand" "=v")
1508         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1509                       (match_operand:V8HI 2 "register_operand" "v")
1510                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1511   "TARGET_ALTIVEC"
1512   "vsldoi %0, %1, %2, %3"
1513   [(set_attr "type" "vecperm")])
1514
1515 (define_insn "altivec_vsldoi_16qi"
1516   [(set (match_operand:V16QI 0 "register_operand" "=v")
1517         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1518                        (match_operand:V16QI 2 "register_operand" "v")
1519                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1520   "TARGET_ALTIVEC"
1521   "vsldoi %0, %1, %2, %3"
1522   [(set_attr "type" "vecperm")])
1523
1524 (define_insn "altivec_vupkhsb"
1525   [(set (match_operand:V8HI 0 "register_operand" "=v")
1526         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1527   "TARGET_ALTIVEC"
1528   "vupkhsb %0, %1"
1529   [(set_attr "type" "vecperm")])
1530
1531 (define_insn "altivec_vupkhpx"
1532   [(set (match_operand:V4SI 0 "register_operand" "=v")
1533         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1534   "TARGET_ALTIVEC"
1535   "vupkhpx %0, %1"
1536   [(set_attr "type" "vecperm")])
1537
1538 (define_insn "altivec_vupkhsh"
1539   [(set (match_operand:V4SI 0 "register_operand" "=v")
1540         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1541   "TARGET_ALTIVEC"
1542   "vupkhsh %0, %1"
1543   [(set_attr "type" "vecperm")])
1544
1545 (define_insn "altivec_vupklsb"
1546   [(set (match_operand:V8HI 0 "register_operand" "=v")
1547         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1548   "TARGET_ALTIVEC"
1549   "vupklsb %0, %1"
1550   [(set_attr "type" "vecperm")])
1551
1552 (define_insn "altivec_vupklpx"
1553   [(set (match_operand:V4SI 0 "register_operand" "=v")
1554         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1555   "TARGET_ALTIVEC"
1556   "vupklpx %0, %1"
1557   [(set_attr "type" "vecperm")])
1558
1559 (define_insn "altivec_vupklsh"
1560   [(set (match_operand:V4SI 0 "register_operand" "=v")
1561         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1562   "TARGET_ALTIVEC"
1563   "vupklsh %0, %1"
1564   [(set_attr "type" "vecperm")])
1565
1566 ;; AltiVec predicates.
1567
1568 (define_expand "cr6_test_for_zero"
1569   [(set (match_operand:SI 0 "register_operand" "=r")
1570         (eq:SI (reg:CC 74)
1571                (const_int 0)))]
1572   "TARGET_ALTIVEC"
1573   "")
1574
1575 (define_expand "cr6_test_for_zero_reverse"
1576   [(set (match_operand:SI 0 "register_operand" "=r")
1577         (eq:SI (reg:CC 74)
1578                (const_int 0)))
1579    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1580   "TARGET_ALTIVEC"
1581   "")
1582
1583 (define_expand "cr6_test_for_lt"
1584   [(set (match_operand:SI 0 "register_operand" "=r")
1585         (lt:SI (reg:CC 74)
1586                (const_int 0)))]
1587   "TARGET_ALTIVEC"
1588   "")
1589
1590 (define_expand "cr6_test_for_lt_reverse"
1591   [(set (match_operand:SI 0 "register_operand" "=r")
1592         (lt:SI (reg:CC 74)
1593                (const_int 0)))
1594    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1595   "TARGET_ALTIVEC"
1596   "")
1597
1598 ;; We can get away with generating the opcode on the fly (%3 below)
1599 ;; because all the predicates have the same scheduling parameters.
1600
1601 (define_insn "altivec_predicate_v4si"
1602   [(set (reg:CC 74)
1603         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1604                     (match_operand:V4SI 2 "register_operand" "v")
1605                     (match_operand 3 "any_operand" "")] 173))
1606    (clobber (match_scratch:V4SI 0 "=v"))]
1607   "TARGET_ALTIVEC"
1608   "%3 %0,%1,%2"
1609 [(set_attr "type" "veccmp")])
1610
1611 (define_insn "altivec_predicate_v4sf"
1612   [(set (reg:CC 74)
1613         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1614                     (match_operand:V4SF 2 "register_operand" "v")
1615                     (match_operand 3 "any_operand" "")] 174))
1616    (clobber (match_scratch:V4SF 0 "=v"))]
1617   "TARGET_ALTIVEC"
1618   "%3 %0,%1,%2"
1619 [(set_attr "type" "veccmp")])
1620
1621 (define_insn "altivec_predicate_v8hi"
1622   [(set (reg:CC 74)
1623         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1624                     (match_operand:V8HI 2 "register_operand" "v")
1625                     (match_operand 3 "any_operand" "")] 175))
1626    (clobber (match_scratch:V8HI 0 "=v"))]
1627   "TARGET_ALTIVEC"
1628   "%3 %0,%1,%2"
1629 [(set_attr "type" "veccmp")])
1630
1631 (define_insn "altivec_predicate_v16qi"
1632   [(set (reg:CC 74)
1633         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1634                     (match_operand:V16QI 2 "register_operand" "v")
1635                     (match_operand 3 "any_operand" "")] 175))
1636    (clobber (match_scratch:V16QI 0 "=v"))]
1637   "TARGET_ALTIVEC"
1638   "%3 %0,%1,%2"
1639 [(set_attr "type" "veccmp")])
1640
1641 (define_insn "altivec_mtvscr"
1642   [(set (reg:SI 110)
1643         (unspec_volatile:SI
1644          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1645   "TARGET_ALTIVEC"
1646   "mtvscr %0"
1647   [(set_attr "type" "vecsimple")])
1648
1649 (define_insn "altivec_mfvscr"
1650   [(set (match_operand:V8HI 0 "register_operand" "=v")
1651         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1652   "TARGET_ALTIVEC"
1653   "mfvscr %0"
1654   [(set_attr "type" "vecsimple")])
1655
1656 (define_insn "altivec_dssall"
1657   [(unspec [(const_int 0)] 188)]
1658   "TARGET_ALTIVEC"
1659   "dssall"
1660   [(set_attr "type" "vecsimple")])
1661
1662 (define_insn "altivec_dss"
1663   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1664   "TARGET_ALTIVEC"
1665   "dss %0"
1666   [(set_attr "type" "vecsimple")])
1667
1668 (define_insn "altivec_dst"
1669   [(unspec [(match_operand:SI 0 "register_operand" "b")
1670             (match_operand:SI 1 "register_operand" "r")
1671             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1672   "TARGET_ALTIVEC"
1673   "dst %0,%1,%2"
1674   [(set_attr "type" "vecsimple")])
1675
1676 (define_insn "altivec_dstt"
1677   [(unspec [(match_operand:SI 0 "register_operand" "b")
1678             (match_operand:SI 1 "register_operand" "r")
1679             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1680   "TARGET_ALTIVEC"
1681   "dstt %0,%1,%2"
1682   [(set_attr "type" "vecsimple")])
1683
1684 (define_insn "altivec_dstst"
1685   [(unspec [(match_operand:SI 0 "register_operand" "b")
1686             (match_operand:SI 1 "register_operand" "r")
1687             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1688   "TARGET_ALTIVEC"
1689   "dstst %0,%1,%2"
1690   [(set_attr "type" "vecsimple")])
1691
1692 (define_insn "altivec_dststt"
1693   [(unspec [(match_operand:SI 0 "register_operand" "b")
1694             (match_operand:SI 1 "register_operand" "r")
1695             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1696   "TARGET_ALTIVEC"
1697   "dststt %0,%1,%2"
1698   [(set_attr "type" "vecsimple")])
1699
1700 (define_insn "altivec_lvsl"
1701   [(set (match_operand:V16QI 0 "register_operand" "=v")
1702         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1703                        (match_operand:SI 2 "register_operand" "r")] 194))]
1704   "TARGET_ALTIVEC"
1705   "lvsl %0,%1,%2"
1706   [(set_attr "type" "vecload")])
1707
1708 (define_insn "altivec_lvsr"
1709   [(set (match_operand:V16QI 0 "register_operand" "=v")
1710         (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
1711                        (match_operand:SI 2 "register_operand" "r")] 195))]
1712   "TARGET_ALTIVEC"
1713   "lvsr %0,%1,%2"
1714   [(set_attr "type" "vecload")])
1715
1716 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1717 ;; identical rtl but different instructions-- and gcc gets confused.
1718
1719 (define_insn "altivec_lvebx"
1720   [(parallel
1721     [(set (match_operand:V16QI 0 "register_operand" "=v")
1722           (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b")
1723                               (match_operand:SI 2 "register_operand" "r"))))
1724      (unspec [(const_int 0)] 196)])]
1725   "TARGET_ALTIVEC"
1726   "lvebx %0,%1,%2"
1727   [(set_attr "type" "vecload")])
1728
1729 (define_insn "altivec_lvehx"
1730   [(parallel
1731     [(set (match_operand:V8HI 0 "register_operand" "=v")
1732           (mem:V8HI
1733            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1734                             (match_operand:SI 2 "register_operand" "r"))
1735                    (const_int -2))))
1736      (unspec [(const_int 0)] 197)])]
1737   "TARGET_ALTIVEC"
1738   "lvehx %0,%1,%2"
1739   [(set_attr "type" "vecload")])
1740
1741 (define_insn "altivec_lvewx"
1742   [(parallel
1743     [(set (match_operand:V4SI 0 "register_operand" "=v")
1744           (mem:V4SI
1745            (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1746                             (match_operand:SI 2 "register_operand" "r"))
1747                    (const_int -4))))
1748      (unspec [(const_int 0)] 198)])]
1749   "TARGET_ALTIVEC"
1750   "lvewx %0,%1,%2"
1751   [(set_attr "type" "vecload")])
1752
1753 (define_insn "altivec_lvxl"
1754   [(parallel
1755     [(set (match_operand:V4SI 0 "register_operand" "=v")
1756           (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1757                              (match_operand:SI 2 "register_operand" "r"))))
1758      (unspec [(const_int 0)] 213)])]
1759   "TARGET_ALTIVEC"
1760   "lvxl %0,%1,%2"
1761   [(set_attr "type" "vecload")])
1762
1763 (define_insn "altivec_lvx"
1764   [(set (match_operand:V4SI 0 "register_operand" "=v")
1765         (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
1766                            (match_operand:SI 2 "register_operand" "r"))))]
1767   "TARGET_ALTIVEC"
1768   "lvx %0,%1,%2"
1769   [(set_attr "type" "vecload")])
1770
1771 (define_insn "altivec_stvx"
1772   [(parallel
1773     [(set (mem:V4SI
1774            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1775                             (match_operand:SI 1 "register_operand" "r"))
1776                    (const_int -16)))
1777           (match_operand:V4SI 2 "register_operand" "v"))
1778      (unspec [(const_int 0)] 201)])]
1779   "TARGET_ALTIVEC"
1780   "stvx %2,%0,%1"
1781   [(set_attr "type" "vecstore")])
1782
1783 (define_insn "altivec_stvxl"
1784   [(parallel
1785     [(set (mem:V4SI
1786            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1787                             (match_operand:SI 1 "register_operand" "r"))
1788                    (const_int -16)))
1789           (match_operand:V4SI 2 "register_operand" "v"))
1790      (unspec [(const_int 0)] 202)])]
1791   "TARGET_ALTIVEC"
1792   "stvxl %2,%0,%1"
1793   [(set_attr "type" "vecstore")])
1794
1795 (define_insn "altivec_stvebx"
1796   [(parallel
1797     [(set (mem:V16QI
1798            (plus:SI (match_operand:SI 0 "register_operand" "b")
1799                     (match_operand:SI 1 "register_operand" "r")))
1800           (match_operand:V16QI 2 "register_operand" "v"))
1801      (unspec [(const_int 0)] 203)])]
1802   "TARGET_ALTIVEC"
1803   "stvebx %2,%0,%1"
1804   [(set_attr "type" "vecstore")])
1805
1806 (define_insn "altivec_stvehx"
1807   [(parallel
1808     [(set (mem:V8HI
1809            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1810                             (match_operand:SI 1 "register_operand" "r"))
1811                    (const_int -2)))
1812           (match_operand:V8HI 2 "register_operand" "v"))
1813      (unspec [(const_int 0)] 204)])]
1814   "TARGET_ALTIVEC"
1815   "stvehx %2,%0,%1"
1816   [(set_attr "type" "vecstore")])
1817
1818 (define_insn "altivec_stvewx"
1819   [(parallel
1820     [(set (mem:V4SI
1821            (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
1822                             (match_operand:SI 1 "register_operand" "r"))
1823                    (const_int -4)))
1824           (match_operand:V4SI 2 "register_operand" "v"))
1825      (unspec [(const_int 0)] 205)])]
1826   "TARGET_ALTIVEC"
1827   "stvewx %2,%0,%1"
1828   [(set_attr "type" "vecstore")])
1829
1830 (define_insn "absv16qi2"
1831   [(set (match_operand:V16QI 0 "register_operand" "=v")
1832         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1833    (clobber (match_scratch:V16QI 2 "=v"))
1834    (clobber (match_scratch:V16QI 3 "=v"))]
1835   "TARGET_ALTIVEC"
1836   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1837   [(set_attr "type" "altivec")
1838    (set_attr "length" "12")])
1839
1840 (define_insn "absv8hi2"
1841   [(set (match_operand:V8HI 0 "register_operand" "=v")
1842         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1843    (clobber (match_scratch:V8HI 2 "=v"))
1844    (clobber (match_scratch:V8HI 3 "=v"))]
1845   "TARGET_ALTIVEC"
1846   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1847   [(set_attr "type" "altivec")
1848    (set_attr "length" "12")])
1849
1850 (define_insn "absv4si2"
1851   [(set (match_operand:V4SI 0 "register_operand" "=v")
1852         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1853    (clobber (match_scratch:V4SI 2 "=v"))
1854    (clobber (match_scratch:V4SI 3 "=v"))]
1855   "TARGET_ALTIVEC"
1856   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1857   [(set_attr "type" "altivec")
1858    (set_attr "length" "12")])
1859
1860 (define_insn "absv4sf2"
1861   [(set (match_operand:V4SF 0 "register_operand" "=v")
1862         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1863    (clobber (match_scratch:V4SF 2 "=v"))
1864    (clobber (match_scratch:V4SF 3 "=v"))]
1865   "TARGET_ALTIVEC"
1866   "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1867   [(set_attr "type" "altivec")
1868    (set_attr "length" "12")])
1869
1870 (define_insn "altivec_abss_v16qi"
1871   [(set (match_operand:V16QI 0 "register_operand" "=v")
1872         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1873    (clobber (match_scratch:V16QI 2 "=v"))
1874    (clobber (match_scratch:V16QI 3 "=v"))]
1875   "TARGET_ALTIVEC"
1876   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1877   [(set_attr "type" "altivec")
1878    (set_attr "length" "12")])
1879
1880 (define_insn "altivec_abss_v8hi"
1881   [(set (match_operand:V8HI 0 "register_operand" "=v")
1882         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1883    (clobber (match_scratch:V8HI 2 "=v"))
1884    (clobber (match_scratch:V8HI 3 "=v"))]
1885   "TARGET_ALTIVEC"
1886   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1887   [(set_attr "type" "altivec")
1888    (set_attr "length" "12")])
1889
1890 (define_insn "altivec_abss_v4si"
1891   [(set (match_operand:V4SI 0 "register_operand" "=v")
1892         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1893    (clobber (match_scratch:V4SI 2 "=v"))
1894    (clobber (match_scratch:V4SI 3 "=v"))]
1895   "TARGET_ALTIVEC"
1896   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1897   [(set_attr "type" "altivec")
1898    (set_attr "length" "12")])