gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20 ;; MA 02110-1301, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VCMPBFP       50)
  24    (UNSPEC_VCMPEQUB      51)
  25    (UNSPEC_VCMPEQUH      52)
  26    (UNSPEC_VCMPEQUW      53)
  27    (UNSPEC_VCMPEQFP      54)
  28    (UNSPEC_VCMPGEFP      55)
  29    (UNSPEC_VCMPGTUB      56)
  30    (UNSPEC_VCMPGTSB      57)
  31    (UNSPEC_VCMPGTUH      58)
  32    (UNSPEC_VCMPGTSH      59)
  33    (UNSPEC_VCMPGTUW      60)
  34    (UNSPEC_VCMPGTSW      61)
  35    (UNSPEC_VCMPGTFP      62)
  36    (UNSPEC_VMSUMU        65)
  37    (UNSPEC_VMSUMM        66)
  38    (UNSPEC_VMSUMSHM      68)
  39    (UNSPEC_VMSUMUHS      69)
  40    (UNSPEC_VMSUMSHS      70)
  41    (UNSPEC_VMHADDSHS     71)
  42    (UNSPEC_VMHRADDSHS    72)
  43    (UNSPEC_VMLADDUHM     73)
  44    (UNSPEC_VADDCUW       75)
  45    (UNSPEC_VADDU         76)
  46    (UNSPEC_VADDS         77)
  47    (UNSPEC_VAVGU         80)
  48    (UNSPEC_VAVGS         81)
  49    (UNSPEC_VMULEUB       83)
  50    (UNSPEC_VMULESB       84)
  51    (UNSPEC_VMULEUH       85)
  52    (UNSPEC_VMULESH       86)
  53    (UNSPEC_VMULOUB       87)
  54    (UNSPEC_VMULOSB       88)
  55    (UNSPEC_VMULOUH       89)
  56    (UNSPEC_VMULOSH       90)
  57    (UNSPEC_VPKUHUM       93)
  58    (UNSPEC_VPKUWUM       94)
  59    (UNSPEC_VPKPX         95)
  60    (UNSPEC_VPKSHSS       97)
  61    (UNSPEC_VPKSWSS       99)
  62    (UNSPEC_VPKUHUS      100)
  63    (UNSPEC_VPKSHUS      101)
  64    (UNSPEC_VPKUWUS      102)
  65    (UNSPEC_VPKSWUS      103)
  66    (UNSPEC_VRL          104)
  67    (UNSPEC_VSL          107)
  68    (UNSPEC_VSLW         109)
  69    (UNSPEC_VSLV4SI      110)
  70    (UNSPEC_VSLO         111)
  71    (UNSPEC_VSR          118)
  72    (UNSPEC_VSRO         119)
  73    (UNSPEC_VSUBCUW      124)
  74    (UNSPEC_VSUBU        125)
  75    (UNSPEC_VSUBS        126)
  76    (UNSPEC_VSUM4UBS     131)
  77    (UNSPEC_VSUM4S       132)
  78    (UNSPEC_VSUM2SWS     134)
  79    (UNSPEC_VSUMSWS      135)
  80    (UNSPEC_VPERM        144)
  81    (UNSPEC_VRFIP        148)
  82    (UNSPEC_VRFIN        149)
  83    (UNSPEC_VRFIM        150)
  84    (UNSPEC_VCFUX        151)
  85    (UNSPEC_VCFSX        152)
  86    (UNSPEC_VCTUXS       153)
  87    (UNSPEC_VCTSXS       154)
  88    (UNSPEC_VLOGEFP      155)
  89    (UNSPEC_VEXPTEFP     156)
  90    (UNSPEC_VRSQRTEFP    157)
  91    (UNSPEC_VREFP        158)
  92    (UNSPEC_VSEL4SI      159)
  93    (UNSPEC_VSEL4SF      160)
  94    (UNSPEC_VSEL8HI      161)
  95    (UNSPEC_VSEL16QI     162)
  96    (UNSPEC_VLSDOI       163)
  97    (UNSPEC_VUPKHSB      167)
  98    (UNSPEC_VUPKHPX      168)
  99    (UNSPEC_VUPKHSH      169)
 100    (UNSPEC_VUPKLSB      170)
 101    (UNSPEC_VUPKLPX      171)
 102    (UNSPEC_VUPKLSH      172)
 103    (UNSPEC_PREDICATE    173)
 104    (UNSPEC_DST          190)
 105    (UNSPEC_DSTT         191)
 106    (UNSPEC_DSTST        192)
 107    (UNSPEC_DSTSTT       193)
 108    (UNSPEC_LVSL         194)
 109    (UNSPEC_LVSR         195)
 110    (UNSPEC_LVE          196)
 111    (UNSPEC_STVX         201)
 112    (UNSPEC_STVXL        202)
 113    (UNSPEC_STVE         203)
 114    (UNSPEC_SET_VSCR     213)
 115    (UNSPEC_GET_VRSAVE   214)
 116    (UNSPEC_REALIGN_LOAD 215)
 117    (UNSPEC_REDUC_PLUS   217)
 118    (UNSPEC_VECSH        219)
 119    (UNSPEC_VCOND_V4SI   301)
 120    (UNSPEC_VCOND_V4SF   302)
 121    (UNSPEC_VCOND_V8HI   303)
 122    (UNSPEC_VCOND_V16QI  304)
 123    (UNSPEC_VCONDU_V4SI  305)
 124    (UNSPEC_VCONDU_V8HI  306)
 125    (UNSPEC_VCONDU_V16QI 307)
 126    ])
 127
 128 (define_constants
 129   [(UNSPECV_SET_VRSAVE   30)
 130    (UNSPECV_MTVSCR      186)
 131    (UNSPECV_MFVSCR      187)
 132    (UNSPECV_DSSALL      188)
 133    (UNSPECV_DSS         189)
 134   ])
 135
 136 ;; Vec int modes
 137 (define_mode_macro VI [V4SI V8HI V16QI])
 138 ;; Short vec in modes
 139 (define_mode_macro VIshort [V8HI V16QI])
 140 ;; Vec float modes
 141 (define_mode_macro VF [V4SF])
 142 ;; Vec modes, pity mode macros are not composable
 143 (define_mode_macro V [V4SI V8HI V16QI V4SF])
 144
 145 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
 146
 147 ;; Generic LVX load instruction.
 148 (define_insn "altivec_lvx_<mode>"
 149   [(set (match_operand:V 0 "altivec_register_operand" "=v")
 150         (match_operand:V 1 "memory_operand" "Z"))]
 151   "TARGET_ALTIVEC"
 152   "lvx %0,%y1"
 153   [(set_attr "type" "vecload")])
 154
 155 ;; Generic STVX store instruction.
 156 (define_insn "altivec_stvx_<mode>"
 157   [(set (match_operand:V 0 "memory_operand" "=Z")
 158         (match_operand:V 1 "altivec_register_operand" "v"))]
 159   "TARGET_ALTIVEC"
 160   "stvx %1,%y0"
 161   [(set_attr "type" "vecstore")])
 162
 163 ;; Vector move instructions.
 164 (define_expand "mov<mode>"
 165   [(set (match_operand:V 0 "nonimmediate_operand" "")
 166         (match_operand:V 1 "any_operand" ""))]
 167   "TARGET_ALTIVEC"
 168 {
 169   rs6000_emit_move (operands[0], operands[1], <MODE>mode);
 170   DONE;
 171 })
 172
 173 (define_insn "*mov<mode>_internal"
 174   [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
 175         (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
 176   "TARGET_ALTIVEC
 177    && (register_operand (operands[0], <MODE>mode)
 178        || register_operand (operands[1], <MODE>mode))"
 179 {
 180   switch (which_alternative)
 181     {
 182     case 0: return "stvx %1,%y0";
 183     case 1: return "lvx %0,%y1";
 184     case 2: return "vor %0,%1,%1";
 185     case 3: return "#";
 186     case 4: return "#";
 187     case 5: return "#";
 188     case 6: return output_vec_const_move (operands);
 189     default: gcc_unreachable ();
 190     }
 191 }
 192   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 193
 194 (define_split
 195   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 196         (match_operand:V4SI 1 "input_operand" ""))]
 197   "TARGET_ALTIVEC && reload_completed
 198    && gpr_or_gpr_p (operands[0], operands[1])"
 199   [(pc)]
 200 {
 201   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 202 })
 203
 204 (define_split
 205   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 206         (match_operand:V8HI 1 "input_operand" ""))]
 207   "TARGET_ALTIVEC && reload_completed
 208    && gpr_or_gpr_p (operands[0], operands[1])"
 209   [(pc)]
 210 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 211
 212 (define_split
 213   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 214         (match_operand:V16QI 1 "input_operand" ""))]
 215   "TARGET_ALTIVEC && reload_completed
 216    && gpr_or_gpr_p (operands[0], operands[1])"
 217   [(pc)]
 218 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 219
 220 (define_split
 221   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 222         (match_operand:V4SF 1 "input_operand" ""))]
 223   "TARGET_ALTIVEC && reload_completed
 224    && gpr_or_gpr_p (operands[0], operands[1])"
 225   [(pc)]
 226 {
 227   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 228 })
 229
 230 (define_split
 231   [(set (match_operand:VI 0 "altivec_register_operand" "")
 232         (match_operand:VI 1 "easy_vector_constant_add_self" ""))]
 233   "TARGET_ALTIVEC && reload_completed"
 234   [(set (match_dup 0) (match_dup 3))
 235    (set (match_dup 0) (plus:VI (match_dup 0)
 236                                (match_dup 0)))]
 237 {
 238   rtx dup = gen_easy_altivec_constant (operands[1]);
 239   rtx const_vec;
 240
 241   /* Divide the operand of the resulting VEC_DUPLICATE, and use
 242      simplify_rtx to make a CONST_VECTOR.  */
 243   XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
 244                                                    XEXP (dup, 0), const1_rtx);
 245   const_vec = simplify_rtx (dup);
 246
 247   if (GET_MODE (const_vec) == <MODE>mode)
 248     operands[3] = const_vec;
 249   else
 250     operands[3] = gen_lowpart (<MODE>mode, const_vec);
 251 })
 252
 253 (define_insn "get_vrsave_internal"
 254   [(set (match_operand:SI 0 "register_operand" "=r")
 255         (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
 256   "TARGET_ALTIVEC"
 257 {
 258   if (TARGET_MACHO)
 259      return "mfspr %0,256";
 260   else
 261      return "mfvrsave %0";
 262 }
 263   [(set_attr "type" "*")])
 264
 265 (define_insn "*set_vrsave_internal"
 266   [(match_parallel 0 "vrsave_operation"
 267      [(set (reg:SI 109)
 268            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 269                                 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
 270   "TARGET_ALTIVEC"
 271 {
 272   if (TARGET_MACHO)
 273     return "mtspr 256,%1";
 274   else
 275     return "mtvrsave %1";
 276 }
 277   [(set_attr "type" "*")])
 278
 279 (define_insn "*save_world"
 280  [(match_parallel 0 "save_world_operation"
 281                   [(clobber (match_operand:SI 1 "register_operand" "=l"))
 282                    (use (match_operand:SI 2 "call_operand" "s"))])]
 283  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 284  "bl %z2"
 285   [(set_attr "type" "branch")
 286    (set_attr "length" "4")])
 287
 288 (define_insn "*restore_world"
 289  [(match_parallel 0 "restore_world_operation"
 290                   [(return)
 291                    (use (match_operand:SI 1 "register_operand" "l"))
 292                    (use (match_operand:SI 2 "call_operand" "s"))
 293                    (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
 294  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 295  "b %z2")
 296
 297 ;; Simple binary operations.
 298
 299 ;; add
 300 (define_insn "add<mode>3"
 301   [(set (match_operand:VI 0 "register_operand" "=v")
 302         (plus:VI (match_operand:VI 1 "register_operand" "v")
 303                  (match_operand:VI 2 "register_operand" "v")))]
 304   "TARGET_ALTIVEC"
 305   "vaddu<VI_char>m %0,%1,%2"
 306   [(set_attr "type" "vecsimple")])
 307
 308 (define_insn "addv4sf3"
 309   [(set (match_operand:V4SF 0 "register_operand" "=v")
 310         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 311                    (match_operand:V4SF 2 "register_operand" "v")))]
 312   "TARGET_ALTIVEC"
 313   "vaddfp %0,%1,%2"
 314   [(set_attr "type" "vecfloat")])
 315
 316 (define_insn "altivec_vaddcuw"
 317   [(set (match_operand:V4SI 0 "register_operand" "=v")
 318         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 319                       (match_operand:V4SI 2 "register_operand" "v")]
 320                      UNSPEC_VADDCUW))]
 321   "TARGET_ALTIVEC"
 322   "vaddcuw %0,%1,%2"
 323   [(set_attr "type" "vecsimple")])
 324
 325 (define_insn "altivec_vaddu<VI_char>s"
 326   [(set (match_operand:VI 0 "register_operand" "=v")
 327         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 328                     (match_operand:VI 2 "register_operand" "v")]
 329                    UNSPEC_VADDU))
 330    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 331   "TARGET_ALTIVEC"
 332   "vaddu<VI_char>s %0,%1,%2"
 333   [(set_attr "type" "vecsimple")])
 334
 335 (define_insn "altivec_vadds<VI_char>s"
 336   [(set (match_operand:VI 0 "register_operand" "=v")
 337         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 338                     (match_operand:VI 2 "register_operand" "v")]
 339                    UNSPEC_VADDS))
 340    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 341   "TARGET_ALTIVEC"
 342   "vadds<VI_char>s %0,%1,%2"
 343   [(set_attr "type" "vecsimple")])
 344
 345 ;; sub
 346 (define_insn "sub<mode>3"
 347   [(set (match_operand:VI 0 "register_operand" "=v")
 348         (minus:VI (match_operand:VI 1 "register_operand" "v")
 349                   (match_operand:VI 2 "register_operand" "v")))]
 350   "TARGET_ALTIVEC"
 351   "vsubu<VI_char>m %0,%1,%2"
 352   [(set_attr "type" "vecsimple")])
 353
 354 (define_insn "subv4sf3"
 355   [(set (match_operand:V4SF 0 "register_operand" "=v")
 356         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 357                     (match_operand:V4SF 2 "register_operand" "v")))]
 358   "TARGET_ALTIVEC"
 359   "vsubfp %0,%1,%2"
 360   [(set_attr "type" "vecfloat")])
 361
 362 (define_insn "altivec_vsubcuw"
 363   [(set (match_operand:V4SI 0 "register_operand" "=v")
 364         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 365                       (match_operand:V4SI 2 "register_operand" "v")]
 366                      UNSPEC_VSUBCUW))]
 367   "TARGET_ALTIVEC"
 368   "vsubcuw %0,%1,%2"
 369   [(set_attr "type" "vecsimple")])
 370
 371 (define_insn "altivec_vsubu<VI_char>s"
 372   [(set (match_operand:VI 0 "register_operand" "=v")
 373         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 374                     (match_operand:VI 2 "register_operand" "v")]
 375                    UNSPEC_VSUBU))
 376    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 377   "TARGET_ALTIVEC"
 378   "vsubu<VI_char>s %0,%1,%2"
 379   [(set_attr "type" "vecsimple")])
 380
 381 (define_insn "altivec_vsubs<VI_char>s"
 382   [(set (match_operand:VI 0 "register_operand" "=v")
 383         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 384                     (match_operand:VI 2 "register_operand" "v")]
 385                    UNSPEC_VSUBS))
 386    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 387   "TARGET_ALTIVEC"
 388   "vsubs<VI_char>s %0,%1,%2"
 389   [(set_attr "type" "vecsimple")])
 390
 391 ;;
 392 (define_insn "altivec_vavgu<VI_char>"
 393   [(set (match_operand:VI 0 "register_operand" "=v")
 394         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 395                     (match_operand:VI 2 "register_operand" "v")]
 396                    UNSPEC_VAVGU))]
 397   "TARGET_ALTIVEC"
 398   "vavgu<VI_char> %0,%1,%2"
 399   [(set_attr "type" "vecsimple")])
 400
 401 (define_insn "altivec_vavgs<VI_char>"
 402   [(set (match_operand:VI 0 "register_operand" "=v")
 403         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 404                     (match_operand:VI 2 "register_operand" "v")]
 405                    UNSPEC_VAVGS))]
 406   "TARGET_ALTIVEC"
 407   "vavgs<VI_char> %0,%1,%2"
 408   [(set_attr "type" "vecsimple")])
 409
 410 (define_insn "altivec_vcmpbfp"
 411   [(set (match_operand:V4SI 0 "register_operand" "=v")
 412         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 413                       (match_operand:V4SF 2 "register_operand" "v")]
 414                       UNSPEC_VCMPBFP))]
 415   "TARGET_ALTIVEC"
 416   "vcmpbfp %0,%1,%2"
 417   [(set_attr "type" "veccmp")])
 418
 419 (define_insn "altivec_vcmpequb"
 420   [(set (match_operand:V16QI 0 "register_operand" "=v")
 421         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 422                        (match_operand:V16QI 2 "register_operand" "v")]
 423                        UNSPEC_VCMPEQUB))]
 424   "TARGET_ALTIVEC"
 425   "vcmpequb %0,%1,%2"
 426   [(set_attr "type" "vecsimple")])
 427
 428 (define_insn "altivec_vcmpequh"
 429   [(set (match_operand:V8HI 0 "register_operand" "=v")
 430         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 431                       (match_operand:V8HI 2 "register_operand" "v")]
 432                       UNSPEC_VCMPEQUH))]
 433   "TARGET_ALTIVEC"
 434   "vcmpequh %0,%1,%2"
 435   [(set_attr "type" "vecsimple")])
 436
 437 (define_insn "altivec_vcmpequw"
 438   [(set (match_operand:V4SI 0 "register_operand" "=v")
 439         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 440                       (match_operand:V4SI 2 "register_operand" "v")]
 441                       UNSPEC_VCMPEQUW))]
 442   "TARGET_ALTIVEC"
 443   "vcmpequw %0,%1,%2"
 444   [(set_attr "type" "vecsimple")])
 445
 446 (define_insn "altivec_vcmpeqfp"
 447   [(set (match_operand:V4SI 0 "register_operand" "=v")
 448         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 449                       (match_operand:V4SF 2 "register_operand" "v")]
 450                       UNSPEC_VCMPEQFP))]
 451   "TARGET_ALTIVEC"
 452   "vcmpeqfp %0,%1,%2"
 453   [(set_attr "type" "veccmp")])
 454
 455 (define_insn "altivec_vcmpgefp"
 456   [(set (match_operand:V4SI 0 "register_operand" "=v")
 457         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 458                       (match_operand:V4SF 2 "register_operand" "v")]
 459                      UNSPEC_VCMPGEFP))]
 460   "TARGET_ALTIVEC"
 461   "vcmpgefp %0,%1,%2"
 462   [(set_attr "type" "veccmp")])
 463
 464 (define_insn "altivec_vcmpgtub"
 465   [(set (match_operand:V16QI 0 "register_operand" "=v")
 466         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 467                        (match_operand:V16QI 2 "register_operand" "v")]
 468                       UNSPEC_VCMPGTUB))]
 469   "TARGET_ALTIVEC"
 470   "vcmpgtub %0,%1,%2"
 471   [(set_attr "type" "vecsimple")])
 472
 473 (define_insn "altivec_vcmpgtsb"
 474   [(set (match_operand:V16QI 0 "register_operand" "=v")
 475         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 476                        (match_operand:V16QI 2 "register_operand" "v")]
 477                       UNSPEC_VCMPGTSB))]
 478   "TARGET_ALTIVEC"
 479   "vcmpgtsb %0,%1,%2"
 480   [(set_attr "type" "vecsimple")])
 481
 482 (define_insn "altivec_vcmpgtuh"
 483   [(set (match_operand:V8HI 0 "register_operand" "=v")
 484         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 485                       (match_operand:V8HI 2 "register_operand" "v")]
 486                      UNSPEC_VCMPGTUH))]
 487   "TARGET_ALTIVEC"
 488   "vcmpgtuh %0,%1,%2"
 489   [(set_attr "type" "vecsimple")])
 490
 491 (define_insn "altivec_vcmpgtsh"
 492   [(set (match_operand:V8HI 0 "register_operand" "=v")
 493         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 494                       (match_operand:V8HI 2 "register_operand" "v")]
 495                      UNSPEC_VCMPGTSH))]
 496   "TARGET_ALTIVEC"
 497   "vcmpgtsh %0,%1,%2"
 498   [(set_attr "type" "vecsimple")])
 499
 500 (define_insn "altivec_vcmpgtuw"
 501   [(set (match_operand:V4SI 0 "register_operand" "=v")
 502         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 503                       (match_operand:V4SI 2 "register_operand" "v")]
 504                      UNSPEC_VCMPGTUW))]
 505   "TARGET_ALTIVEC"
 506   "vcmpgtuw %0,%1,%2"
 507   [(set_attr "type" "vecsimple")])
 508
 509 (define_insn "altivec_vcmpgtsw"
 510   [(set (match_operand:V4SI 0 "register_operand" "=v")
 511         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 512                       (match_operand:V4SI 2 "register_operand" "v")]
 513                      UNSPEC_VCMPGTSW))]
 514   "TARGET_ALTIVEC"
 515   "vcmpgtsw %0,%1,%2"
 516   [(set_attr "type" "vecsimple")])
 517
 518 (define_insn "altivec_vcmpgtfp"
 519   [(set (match_operand:V4SI 0 "register_operand" "=v")
 520         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 521                       (match_operand:V4SF 2 "register_operand" "v")]
 522                      UNSPEC_VCMPGTFP))]
 523   "TARGET_ALTIVEC"
 524   "vcmpgtfp %0,%1,%2"
 525   [(set_attr "type" "veccmp")])
 526
 527 ;; Fused multiply add
 528 (define_insn "altivec_vmaddfp"
 529   [(set (match_operand:V4SF 0 "register_operand" "=v")
 530         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 531                               (match_operand:V4SF 2 "register_operand" "v"))
 532                    (match_operand:V4SF 3 "register_operand" "v")))]
 533   "TARGET_ALTIVEC"
 534   "vmaddfp %0,%1,%2,%3"
 535   [(set_attr "type" "vecfloat")])
 536
 537 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 538
 539 (define_expand "mulv4sf3"
 540   [(use (match_operand:V4SF 0 "register_operand" ""))
 541    (use (match_operand:V4SF 1 "register_operand" ""))
 542    (use (match_operand:V4SF 2 "register_operand" ""))]
 543   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 544   "
 545 {
 546   rtx neg0;
 547
 548   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 549   neg0 = gen_reg_rtx (V4SFmode);
 550   emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
 551   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 552
 553   /* Use the multiply-add.  */
 554   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 555                                   neg0));
 556   DONE;
 557 }")
 558
 559 ;; 32 bit integer multiplication
 560 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
 561 ;; A_low = Operand_0 & 0xFFFF
 562 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
 563 ;; B_low = Operand_1 & 0xFFFF
 564 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
 565
 566 ;; (define_insn "mulv4si3"
 567 ;;   [(set (match_operand:V4SI 0 "register_operand" "=v")
 568 ;;         (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
 569 ;;                    (match_operand:V4SI 2 "register_operand" "v")))]
 570 (define_expand "mulv4si3"
 571   [(use (match_operand:V4SI 0 "register_operand" ""))
 572    (use (match_operand:V4SI 1 "register_operand" ""))
 573    (use (match_operand:V4SI 2 "register_operand" ""))]
 574    "TARGET_ALTIVEC"
 575    "
 576  {
 577    rtx zero;
 578    rtx swap;
 579    rtx small_swap;
 580    rtx sixteen;
 581    rtx one;
 582    rtx two;
 583    rtx low_product;
 584    rtx high_product;
 585
 586    zero = gen_reg_rtx (V4SImode);
 587    emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
 588
 589    sixteen = gen_reg_rtx (V4SImode);
 590    emit_insn (gen_altivec_vspltisw (sixteen,  gen_rtx_CONST_INT (V4SImode, -16)));
 591
 592    swap = gen_reg_rtx (V4SImode);
 593    emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
 594
 595    one = gen_reg_rtx (V8HImode);
 596    convert_move (one, operands[1], 0);
 597
 598    two = gen_reg_rtx (V8HImode);
 599    convert_move (two, operands[2], 0);
 600
 601    small_swap = gen_reg_rtx (V8HImode);
 602    convert_move (small_swap, swap, 0);
 603
 604    low_product = gen_reg_rtx (V4SImode);
 605    emit_insn (gen_altivec_vmulouh (low_product, one, two));
 606
 607    high_product = gen_reg_rtx (V4SImode);
 608    emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
 609
 610    emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
 611
 612    emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
 613
 614    DONE;
 615  }")
 616
 617
 618 ;; Fused multiply subtract
 619 (define_insn "altivec_vnmsubfp"
 620   [(set (match_operand:V4SF 0 "register_operand" "=v")
 621         (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 622                                (match_operand:V4SF 2 "register_operand" "v"))
 623                     (match_operand:V4SF 3 "register_operand" "v"))))]
 624   "TARGET_ALTIVEC"
 625   "vnmsubfp %0,%1,%2,%3"
 626   [(set_attr "type" "vecfloat")])
 627
 628 (define_insn "altivec_vmsumu<VI_char>m"
 629   [(set (match_operand:V4SI 0 "register_operand" "=v")
 630         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 631                       (match_operand:VIshort 2 "register_operand" "v")
 632                       (match_operand:V4SI 3 "register_operand" "v")]
 633                      UNSPEC_VMSUMU))]
 634   "TARGET_ALTIVEC"
 635   "vmsumu<VI_char>m %0,%1,%2,%3"
 636   [(set_attr "type" "veccomplex")])
 637
 638 (define_insn "altivec_vmsumm<VI_char>m"
 639   [(set (match_operand:V4SI 0 "register_operand" "=v")
 640         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 641                       (match_operand:VIshort 2 "register_operand" "v")
 642                       (match_operand:V4SI 3 "register_operand" "v")]
 643                      UNSPEC_VMSUMM))]
 644   "TARGET_ALTIVEC"
 645   "vmsumm<VI_char>m %0,%1,%2,%3"
 646   [(set_attr "type" "veccomplex")])
 647
 648 (define_insn "altivec_vmsumshm"
 649   [(set (match_operand:V4SI 0 "register_operand" "=v")
 650         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 651                       (match_operand:V8HI 2 "register_operand" "v")
 652                       (match_operand:V4SI 3 "register_operand" "v")]
 653                      UNSPEC_VMSUMSHM))]
 654   "TARGET_ALTIVEC"
 655   "vmsumshm %0,%1,%2,%3"
 656   [(set_attr "type" "veccomplex")])
 657
 658 (define_insn "altivec_vmsumuhs"
 659   [(set (match_operand:V4SI 0 "register_operand" "=v")
 660         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 661                       (match_operand:V8HI 2 "register_operand" "v")
 662                       (match_operand:V4SI 3 "register_operand" "v")]
 663                      UNSPEC_VMSUMUHS))
 664    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 665   "TARGET_ALTIVEC"
 666   "vmsumuhs %0,%1,%2,%3"
 667   [(set_attr "type" "veccomplex")])
 668
 669 (define_insn "altivec_vmsumshs"
 670   [(set (match_operand:V4SI 0 "register_operand" "=v")
 671         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 672                       (match_operand:V8HI 2 "register_operand" "v")
 673                       (match_operand:V4SI 3 "register_operand" "v")]
 674                      UNSPEC_VMSUMSHS))
 675    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 676   "TARGET_ALTIVEC"
 677   "vmsumshs %0,%1,%2,%3"
 678   [(set_attr "type" "veccomplex")])
 679
 680 ;; max
 681
 682 (define_insn "umax<mode>3"
 683   [(set (match_operand:VI 0 "register_operand" "=v")
 684         (umax:VI (match_operand:VI 1 "register_operand" "v")
 685                  (match_operand:VI 2 "register_operand" "v")))]
 686   "TARGET_ALTIVEC"
 687   "vmaxu<VI_char> %0,%1,%2"
 688   [(set_attr "type" "vecsimple")])
 689
 690 (define_insn "smax<mode>3"
 691   [(set (match_operand:VI 0 "register_operand" "=v")
 692         (smax:VI (match_operand:VI 1 "register_operand" "v")
 693                  (match_operand:VI 2 "register_operand" "v")))]
 694   "TARGET_ALTIVEC"
 695   "vmaxs<VI_char> %0,%1,%2"
 696   [(set_attr "type" "vecsimple")])
 697
 698 (define_insn "smaxv4sf3"
 699   [(set (match_operand:V4SF 0 "register_operand" "=v")
 700         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 701                    (match_operand:V4SF 2 "register_operand" "v")))]
 702   "TARGET_ALTIVEC"
 703   "vmaxfp %0,%1,%2"
 704   [(set_attr "type" "veccmp")])
 705
 706 (define_insn "umin<mode>3"
 707   [(set (match_operand:VI 0 "register_operand" "=v")
 708         (umin:VI (match_operand:VI 1 "register_operand" "v")
 709                  (match_operand:VI 2 "register_operand" "v")))]
 710   "TARGET_ALTIVEC"
 711   "vminu<VI_char> %0,%1,%2"
 712   [(set_attr "type" "vecsimple")])
 713
 714 (define_insn "smin<mode>3"
 715   [(set (match_operand:VI 0 "register_operand" "=v")
 716         (smin:VI (match_operand:VI 1 "register_operand" "v")
 717                  (match_operand:VI 2 "register_operand" "v")))]
 718   "TARGET_ALTIVEC"
 719   "vmins<VI_char> %0,%1,%2"
 720   [(set_attr "type" "vecsimple")])
 721
 722 (define_insn "sminv4sf3"
 723   [(set (match_operand:V4SF 0 "register_operand" "=v")
 724         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 725                    (match_operand:V4SF 2 "register_operand" "v")))]
 726   "TARGET_ALTIVEC"
 727   "vminfp %0,%1,%2"
 728   [(set_attr "type" "veccmp")])
 729
 730 (define_insn "altivec_vmhaddshs"
 731   [(set (match_operand:V8HI 0 "register_operand" "=v")
 732         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 733                       (match_operand:V8HI 2 "register_operand" "v")
 734                       (match_operand:V8HI 3 "register_operand" "v")]
 735                      UNSPEC_VMHADDSHS))
 736    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 737   "TARGET_ALTIVEC"
 738   "vmhaddshs %0,%1,%2,%3"
 739   [(set_attr "type" "veccomplex")])
 740
 741 (define_insn "altivec_vmhraddshs"
 742   [(set (match_operand:V8HI 0 "register_operand" "=v")
 743         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 744                       (match_operand:V8HI 2 "register_operand" "v")
 745                       (match_operand:V8HI 3 "register_operand" "v")]
 746                      UNSPEC_VMHRADDSHS))
 747    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 748   "TARGET_ALTIVEC"
 749   "vmhraddshs %0,%1,%2,%3"
 750   [(set_attr "type" "veccomplex")])
 751
 752 (define_insn "altivec_vmladduhm"
 753   [(set (match_operand:V8HI 0 "register_operand" "=v")
 754         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 755                       (match_operand:V8HI 2 "register_operand" "v")
 756                       (match_operand:V8HI 3 "register_operand" "v")]
 757                      UNSPEC_VMLADDUHM))]
 758   "TARGET_ALTIVEC"
 759   "vmladduhm %0,%1,%2,%3"
 760   [(set_attr "type" "veccomplex")])
 761
 762 (define_insn "altivec_vmrghb"
 763   [(set (match_operand:V16QI 0 "register_operand" "=v")
 764         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 765                                            (parallel [(const_int 0)
 766                                                       (const_int 8)
 767                                                       (const_int 1)
 768                                                       (const_int 9)
 769                                                       (const_int 2)
 770                                                       (const_int 10)
 771                                                       (const_int 3)
 772                                                       (const_int 11)
 773                                                       (const_int 4)
 774                                                       (const_int 12)
 775                                                       (const_int 5)
 776                                                       (const_int 13)
 777                                                       (const_int 6)
 778                                                       (const_int 14)
 779                                                       (const_int 7)
 780                                                       (const_int 15)]))
 781                         (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 782                                            (parallel [(const_int 8)
 783                                                       (const_int 0)
 784                                                       (const_int 9)
 785                                                       (const_int 1)
 786                                                       (const_int 10)
 787                                                       (const_int 2)
 788                                                       (const_int 11)
 789                                                       (const_int 3)
 790                                                       (const_int 12)
 791                                                       (const_int 4)
 792                                                       (const_int 13)
 793                                                       (const_int 5)
 794                                                       (const_int 14)
 795                                                       (const_int 6)
 796                                                       (const_int 15)
 797                                                       (const_int 7)]))
 798                       (const_int 21845)))]
 799   "TARGET_ALTIVEC"
 800   "vmrghb %0,%1,%2"
 801   [(set_attr "type" "vecperm")])
 802
 803 (define_insn "altivec_vmrghh"
 804   [(set (match_operand:V8HI 0 "register_operand" "=v")
 805         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 806                                            (parallel [(const_int 0)
 807                                                       (const_int 4)
 808                                                       (const_int 1)
 809                                                       (const_int 5)
 810                                                       (const_int 2)
 811                                                       (const_int 6)
 812                                                       (const_int 3)
 813                                                       (const_int 7)]))
 814                         (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 815                                            (parallel [(const_int 4)
 816                                                       (const_int 0)
 817                                                       (const_int 5)
 818                                                       (const_int 1)
 819                                                       (const_int 6)
 820                                                       (const_int 2)
 821                                                       (const_int 7)
 822                                                       (const_int 3)]))
 823                       (const_int 85)))]
 824   "TARGET_ALTIVEC"
 825   "vmrghh %0,%1,%2"
 826   [(set_attr "type" "vecperm")])
 827
 828 (define_insn "altivec_vmrghw"
 829   [(set (match_operand:V4SI 0 "register_operand" "=v")
 830         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 831                                          (parallel [(const_int 0)
 832                                                     (const_int 2)
 833                                                     (const_int 1)
 834                                                     (const_int 3)]))
 835                         (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 836                                          (parallel [(const_int 2)
 837                                                     (const_int 0)
 838                                                     (const_int 3)
 839                                                     (const_int 1)]))
 840                       (const_int 5)))]
 841   "TARGET_ALTIVEC"
 842   "vmrghw %0,%1,%2"
 843   [(set_attr "type" "vecperm")])
 844
 845 (define_insn "altivec_vmrglb"
 846   [(set (match_operand:V16QI 0 "register_operand" "=v")
 847         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 848                                            (parallel [(const_int 8)
 849                                                       (const_int 0)
 850                                                       (const_int 9)
 851                                                       (const_int 1)
 852                                                       (const_int 10)
 853                                                       (const_int 2)
 854                                                       (const_int 11)
 855                                                       (const_int 3)
 856                                                       (const_int 12)
 857                                                       (const_int 4)
 858                                                       (const_int 13)
 859                                                       (const_int 5)
 860                                                       (const_int 14)
 861                                                       (const_int 6)
 862                                                       (const_int 15)
 863                                                       (const_int 7)]))
 864                       (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 865                                            (parallel [(const_int 0)
 866                                                       (const_int 8)
 867                                                       (const_int 1)
 868                                                       (const_int 9)
 869                                                       (const_int 2)
 870                                                       (const_int 10)
 871                                                       (const_int 3)
 872                                                       (const_int 11)
 873                                                       (const_int 4)
 874                                                       (const_int 12)
 875                                                       (const_int 5)
 876                                                       (const_int 13)
 877                                                       (const_int 6)
 878                                                       (const_int 14)
 879                                                       (const_int 7)
 880                                                       (const_int 15)]))
 881                       (const_int 21845)))]
 882   "TARGET_ALTIVEC"
 883   "vmrglb %0,%1,%2"
 884   [(set_attr "type" "vecperm")])
 885
 886 (define_insn "altivec_vmrglh"
 887   [(set (match_operand:V8HI 0 "register_operand" "=v")
 888         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 889                                            (parallel [(const_int 4)
 890                                                       (const_int 0)
 891                                                       (const_int 5)
 892                                                       (const_int 1)
 893                                                       (const_int 6)
 894                                                       (const_int 2)
 895                                                       (const_int 7)
 896                                                       (const_int 3)]))
 897                         (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 898                                            (parallel [(const_int 0)
 899                                                       (const_int 4)
 900                                                       (const_int 1)
 901                                                       (const_int 5)
 902                                                       (const_int 2)
 903                                                       (const_int 6)
 904                                                       (const_int 3)
 905                                                       (const_int 7)]))
 906                       (const_int 85)))]
 907   "TARGET_ALTIVEC"
 908   "vmrglh %0,%1,%2"
 909   [(set_attr "type" "vecperm")])
 910
 911 (define_insn "altivec_vmrglw"
 912   [(set (match_operand:V4SI 0 "register_operand" "=v")
 913         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 914                                          (parallel [(const_int 2)
 915                                                     (const_int 0)
 916                                                     (const_int 3)
 917                                                     (const_int 1)]))
 918                         (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 919                                          (parallel [(const_int 0)
 920                                                     (const_int 2)
 921                                                     (const_int 1)
 922                                                     (const_int 3)]))
 923                       (const_int 5)))]
 924   "TARGET_ALTIVEC"
 925   "vmrglw %0,%1,%2"
 926   [(set_attr "type" "vecperm")])
 927
 928 (define_insn "altivec_vmuleub"
 929   [(set (match_operand:V8HI 0 "register_operand" "=v")
 930         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 931                       (match_operand:V16QI 2 "register_operand" "v")]
 932                      UNSPEC_VMULEUB))]
 933   "TARGET_ALTIVEC"
 934   "vmuleub %0,%1,%2"
 935   [(set_attr "type" "veccomplex")])
 936
 937 (define_insn "altivec_vmulesb"
 938   [(set (match_operand:V8HI 0 "register_operand" "=v")
 939         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 940                       (match_operand:V16QI 2 "register_operand" "v")]
 941                      UNSPEC_VMULESB))]
 942   "TARGET_ALTIVEC"
 943   "vmulesb %0,%1,%2"
 944   [(set_attr "type" "veccomplex")])
 945
 946 (define_insn "altivec_vmuleuh"
 947   [(set (match_operand:V4SI 0 "register_operand" "=v")
 948         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 949                       (match_operand:V8HI 2 "register_operand" "v")]
 950                      UNSPEC_VMULEUH))]
 951   "TARGET_ALTIVEC"
 952   "vmuleuh %0,%1,%2"
 953   [(set_attr "type" "veccomplex")])
 954
 955 (define_insn "altivec_vmulesh"
 956   [(set (match_operand:V4SI 0 "register_operand" "=v")
 957         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 958                       (match_operand:V8HI 2 "register_operand" "v")]
 959                      UNSPEC_VMULESH))]
 960   "TARGET_ALTIVEC"
 961   "vmulesh %0,%1,%2"
 962   [(set_attr "type" "veccomplex")])
 963
 964 (define_insn "altivec_vmuloub"
 965   [(set (match_operand:V8HI 0 "register_operand" "=v")
 966         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 967                       (match_operand:V16QI 2 "register_operand" "v")]
 968                      UNSPEC_VMULOUB))]
 969   "TARGET_ALTIVEC"
 970   "vmuloub %0,%1,%2"
 971   [(set_attr "type" "veccomplex")])
 972
 973 (define_insn "altivec_vmulosb"
 974   [(set (match_operand:V8HI 0 "register_operand" "=v")
 975         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 976                       (match_operand:V16QI 2 "register_operand" "v")]
 977                      UNSPEC_VMULOSB))]
 978   "TARGET_ALTIVEC"
 979   "vmulosb %0,%1,%2"
 980   [(set_attr "type" "veccomplex")])
 981
 982 (define_insn "altivec_vmulouh"
 983   [(set (match_operand:V4SI 0 "register_operand" "=v")
 984         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 985                       (match_operand:V8HI 2 "register_operand" "v")]
 986                      UNSPEC_VMULOUH))]
 987   "TARGET_ALTIVEC"
 988   "vmulouh %0,%1,%2"
 989   [(set_attr "type" "veccomplex")])
 990
 991 (define_insn "altivec_vmulosh"
 992   [(set (match_operand:V4SI 0 "register_operand" "=v")
 993         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 994                       (match_operand:V8HI 2 "register_operand" "v")]
 995                      UNSPEC_VMULOSH))]
 996   "TARGET_ALTIVEC"
 997   "vmulosh %0,%1,%2"
 998   [(set_attr "type" "veccomplex")])
 999
1000
1001 ;; logical ops
1002
1003 (define_insn "and<mode>3"
1004   [(set (match_operand:VI 0 "register_operand" "=v")
1005         (and:VI (match_operand:VI 1 "register_operand" "v")
1006                 (match_operand:VI 2 "register_operand" "v")))]
1007   "TARGET_ALTIVEC"
1008   "vand %0,%1,%2"
1009   [(set_attr "type" "vecsimple")])
1010
1011 (define_insn "ior<mode>3"
1012   [(set (match_operand:VI 0 "register_operand" "=v")
1013         (ior:VI (match_operand:VI 1 "register_operand" "v")
1014                 (match_operand:VI 2 "register_operand" "v")))]
1015   "TARGET_ALTIVEC"
1016   "vor %0,%1,%2"
1017   [(set_attr "type" "vecsimple")])
1018
1019 (define_insn "xor<mode>3"
1020   [(set (match_operand:VI 0 "register_operand" "=v")
1021         (xor:VI (match_operand:VI 1 "register_operand" "v")
1022                 (match_operand:VI 2 "register_operand" "v")))]
1023   "TARGET_ALTIVEC"
1024   "vxor %0,%1,%2"
1025   [(set_attr "type" "vecsimple")])
1026
1027 (define_insn "xorv4sf3"
1028   [(set (match_operand:V4SF 0 "register_operand" "=v")
1029         (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1030                   (match_operand:V4SF 2 "register_operand" "v")))]
1031   "TARGET_ALTIVEC"
1032   "vxor %0,%1,%2"
1033   [(set_attr "type" "vecsimple")])
1034
1035 (define_insn "one_cmpl<mode>2"
1036   [(set (match_operand:VI 0 "register_operand" "=v")
1037         (not:VI (match_operand:VI 1 "register_operand" "v")))]
1038   "TARGET_ALTIVEC"
1039   "vnor %0,%1,%1"
1040   [(set_attr "type" "vecsimple")])
1041
1042 (define_insn "altivec_nor<mode>3"
1043   [(set (match_operand:VI 0 "register_operand" "=v")
1044         (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1045                         (match_operand:VI 2 "register_operand" "v"))))]
1046   "TARGET_ALTIVEC"
1047   "vnor %0,%1,%2"
1048   [(set_attr "type" "vecsimple")])
1049
1050 (define_insn "andc<mode>3"
1051   [(set (match_operand:VI 0 "register_operand" "=v")
1052         (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1053                 (match_operand:VI 1 "register_operand" "v")))]
1054   "TARGET_ALTIVEC"
1055   "vandc %0,%1,%2"
1056   [(set_attr "type" "vecsimple")])
1057
1058 (define_insn "*andc3_v4sf"
1059   [(set (match_operand:V4SF 0 "register_operand" "=v")
1060         (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1061                   (match_operand:V4SF 1 "register_operand" "v")))]
1062   "TARGET_ALTIVEC"
1063   "vandc %0,%1,%2"
1064   [(set_attr "type" "vecsimple")])
1065
1066 (define_insn "altivec_vpkuhum"
1067   [(set (match_operand:V16QI 0 "register_operand" "=v")
1068         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1069                        (match_operand:V8HI 2 "register_operand" "v")]
1070                       UNSPEC_VPKUHUM))]
1071   "TARGET_ALTIVEC"
1072   "vpkuhum %0,%1,%2"
1073   [(set_attr "type" "vecperm")])
1074
1075 (define_insn "altivec_vpkuwum"
1076   [(set (match_operand:V8HI 0 "register_operand" "=v")
1077         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1078                       (match_operand:V4SI 2 "register_operand" "v")]
1079                      UNSPEC_VPKUWUM))]
1080   "TARGET_ALTIVEC"
1081   "vpkuwum %0,%1,%2"
1082   [(set_attr "type" "vecperm")])
1083
1084 (define_insn "altivec_vpkpx"
1085   [(set (match_operand:V8HI 0 "register_operand" "=v")
1086         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1087                       (match_operand:V4SI 2 "register_operand" "v")]
1088                      UNSPEC_VPKPX))]
1089   "TARGET_ALTIVEC"
1090   "vpkpx %0,%1,%2"
1091   [(set_attr "type" "vecperm")])
1092
1093 (define_insn "altivec_vpkshss"
1094   [(set (match_operand:V16QI 0 "register_operand" "=v")
1095         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1096                        (match_operand:V8HI 2 "register_operand" "v")]
1097                       UNSPEC_VPKSHSS))
1098    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1099   "TARGET_ALTIVEC"
1100   "vpkshss %0,%1,%2"
1101   [(set_attr "type" "vecperm")])
1102
1103 (define_insn "altivec_vpkswss"
1104   [(set (match_operand:V8HI 0 "register_operand" "=v")
1105         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1106                       (match_operand:V4SI 2 "register_operand" "v")]
1107                      UNSPEC_VPKSWSS))
1108    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1109   "TARGET_ALTIVEC"
1110   "vpkswss %0,%1,%2"
1111   [(set_attr "type" "vecperm")])
1112
1113 (define_insn "altivec_vpkuhus"
1114   [(set (match_operand:V16QI 0 "register_operand" "=v")
1115         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1116                        (match_operand:V8HI 2 "register_operand" "v")]
1117                       UNSPEC_VPKUHUS))
1118    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1119   "TARGET_ALTIVEC"
1120   "vpkuhus %0,%1,%2"
1121   [(set_attr "type" "vecperm")])
1122
1123 (define_insn "altivec_vpkshus"
1124   [(set (match_operand:V16QI 0 "register_operand" "=v")
1125         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1126                        (match_operand:V8HI 2 "register_operand" "v")]
1127                       UNSPEC_VPKSHUS))
1128    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1129   "TARGET_ALTIVEC"
1130   "vpkshus %0,%1,%2"
1131   [(set_attr "type" "vecperm")])
1132
1133 (define_insn "altivec_vpkuwus"
1134   [(set (match_operand:V8HI 0 "register_operand" "=v")
1135         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1136                       (match_operand:V4SI 2 "register_operand" "v")]
1137                      UNSPEC_VPKUWUS))
1138    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1139   "TARGET_ALTIVEC"
1140   "vpkuwus %0,%1,%2"
1141   [(set_attr "type" "vecperm")])
1142
1143 (define_insn "altivec_vpkswus"
1144   [(set (match_operand:V8HI 0 "register_operand" "=v")
1145         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1146                       (match_operand:V4SI 2 "register_operand" "v")]
1147                      UNSPEC_VPKSWUS))
1148    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1149   "TARGET_ALTIVEC"
1150   "vpkswus %0,%1,%2"
1151   [(set_attr "type" "vecperm")])
1152
1153 (define_insn "altivec_vrl<VI_char>"
1154   [(set (match_operand:VI 0 "register_operand" "=v")
1155         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1156                     (match_operand:VI 2 "register_operand" "v")]
1157                    UNSPEC_VRL))]
1158   "TARGET_ALTIVEC"
1159   "vrl<VI_char> %0,%1,%2"
1160   [(set_attr "type" "vecsimple")])
1161
1162 (define_insn "altivec_vsl<VI_char>"
1163   [(set (match_operand:VI 0 "register_operand" "=v")
1164         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1165                     (match_operand:VI 2 "register_operand" "v")]
1166                    UNSPEC_VSL))]
1167   "TARGET_ALTIVEC"
1168   "vsl<VI_char> %0,%1,%2"
1169   [(set_attr "type" "vecsimple")])
1170
1171 (define_insn "altivec_vslw_v4sf"
1172   [(set (match_operand:V4SF 0 "register_operand" "=v")
1173         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1174                       (match_operand:V4SF 2 "register_operand" "v")]
1175                      UNSPEC_VSLW))]
1176   "TARGET_ALTIVEC"
1177   "vslw %0,%1,%2"
1178   [(set_attr "type" "vecsimple")])
1179
1180 (define_insn "altivec_vsl"
1181   [(set (match_operand:V4SI 0 "register_operand" "=v")
1182         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1183                       (match_operand:V4SI 2 "register_operand" "v")]
1184                      UNSPEC_VSLV4SI))]
1185   "TARGET_ALTIVEC"
1186   "vsl %0,%1,%2"
1187   [(set_attr "type" "vecperm")])
1188
1189 (define_insn "altivec_vslo"
1190   [(set (match_operand:V4SI 0 "register_operand" "=v")
1191         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1192                       (match_operand:V4SI 2 "register_operand" "v")]
1193                      UNSPEC_VSLO))]
1194   "TARGET_ALTIVEC"
1195   "vslo %0,%1,%2"
1196   [(set_attr "type" "vecperm")])
1197
1198 (define_insn "lshr<mode>3"
1199   [(set (match_operand:VI 0 "register_operand" "=v")
1200         (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1201                     (match_operand:VI 2 "register_operand" "v") ))]
1202   "TARGET_ALTIVEC"
1203   "vsr<VI_char> %0,%1,%2"
1204   [(set_attr "type" "vecsimple")])
1205
1206 (define_insn "ashr<mode>3"
1207   [(set (match_operand:VI 0 "register_operand" "=v")
1208         (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1209                     (match_operand:VI 2 "register_operand" "v") ))]
1210   "TARGET_ALTIVEC"
1211   "vsra<VI_char> %0,%1,%2"
1212   [(set_attr "type" "vecsimple")])
1213
1214 (define_insn "altivec_vsr"
1215   [(set (match_operand:V4SI 0 "register_operand" "=v")
1216         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1217                       (match_operand:V4SI 2 "register_operand" "v")]
1218                      UNSPEC_VSR))]
1219   "TARGET_ALTIVEC"
1220   "vsr %0,%1,%2"
1221   [(set_attr "type" "vecperm")])
1222
1223 (define_insn "altivec_vsro"
1224   [(set (match_operand:V4SI 0 "register_operand" "=v")
1225         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1226                       (match_operand:V4SI 2 "register_operand" "v")]
1227                      UNSPEC_VSRO))]
1228   "TARGET_ALTIVEC"
1229   "vsro %0,%1,%2"
1230   [(set_attr "type" "vecperm")])
1231
1232 (define_insn "altivec_vsum4ubs"
1233   [(set (match_operand:V4SI 0 "register_operand" "=v")
1234         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1235                       (match_operand:V4SI 2 "register_operand" "v")]
1236                      UNSPEC_VSUM4UBS))
1237    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1238   "TARGET_ALTIVEC"
1239   "vsum4ubs %0,%1,%2"
1240   [(set_attr "type" "veccomplex")])
1241
1242 (define_insn "altivec_vsum4s<VI_char>s"
1243   [(set (match_operand:V4SI 0 "register_operand" "=v")
1244         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1245                       (match_operand:V4SI 2 "register_operand" "v")]
1246                      UNSPEC_VSUM4S))
1247    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1248   "TARGET_ALTIVEC"
1249   "vsum4s<VI_char>s %0,%1,%2"
1250   [(set_attr "type" "veccomplex")])
1251
1252 (define_insn "altivec_vsum2sws"
1253   [(set (match_operand:V4SI 0 "register_operand" "=v")
1254         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1255                       (match_operand:V4SI 2 "register_operand" "v")]
1256                      UNSPEC_VSUM2SWS))
1257    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1258   "TARGET_ALTIVEC"
1259   "vsum2sws %0,%1,%2"
1260   [(set_attr "type" "veccomplex")])
1261
1262 (define_insn "altivec_vsumsws"
1263   [(set (match_operand:V4SI 0 "register_operand" "=v")
1264         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1265                       (match_operand:V4SI 2 "register_operand" "v")]
1266                      UNSPEC_VSUMSWS))
1267    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1268   "TARGET_ALTIVEC"
1269   "vsumsws %0,%1,%2"
1270   [(set_attr "type" "veccomplex")])
1271
1272 (define_insn "altivec_vspltb"
1273   [(set (match_operand:V16QI 0 "register_operand" "=v")
1274         (vec_duplicate:V16QI
1275          (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1276                         (parallel
1277                          [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1278   "TARGET_ALTIVEC"
1279   "vspltb %0,%1,%2"
1280   [(set_attr "type" "vecperm")])
1281
1282 (define_insn "altivec_vsplth"
1283   [(set (match_operand:V8HI 0 "register_operand" "=v")
1284         (vec_duplicate:V8HI
1285          (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1286                         (parallel
1287                          [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1288   "TARGET_ALTIVEC"
1289   "vsplth %0,%1,%2"
1290   [(set_attr "type" "vecperm")])
1291
1292 (define_insn "altivec_vspltw"
1293   [(set (match_operand:V4SI 0 "register_operand" "=v")
1294         (vec_duplicate:V4SI
1295          (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1296                         (parallel
1297                          [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1298   "TARGET_ALTIVEC"
1299   "vspltw %0,%1,%2"
1300   [(set_attr "type" "vecperm")])
1301
1302 (define_insn "*altivec_vspltsf"
1303   [(set (match_operand:V4SF 0 "register_operand" "=v")
1304         (vec_duplicate:V4SF
1305          (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1306                         (parallel
1307                          [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1308   "TARGET_ALTIVEC"
1309   "vspltw %0,%1,%2"
1310   [(set_attr "type" "vecperm")])
1311
1312 (define_insn "altivec_vspltis<VI_char>"
1313   [(set (match_operand:VI 0 "register_operand" "=v")
1314         (vec_duplicate:VI
1315          (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1316   "TARGET_ALTIVEC"
1317   "vspltis<VI_char> %0,%1"
1318   [(set_attr "type" "vecperm")])
1319
1320 (define_insn "altivec_vspltisw_v4sf"
1321   [(set (match_operand:V4SF 0 "register_operand" "=v")
1322         (vec_duplicate:V4SF
1323          (float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))]
1324   "TARGET_ALTIVEC"
1325   "vspltisw %0,%1"
1326   [(set_attr "type" "vecperm")])
1327
1328 (define_insn "ftruncv4sf2"
1329   [(set (match_operand:V4SF 0 "register_operand" "=v")
1330         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1331   "TARGET_ALTIVEC"
1332   "vrfiz %0,%1"
1333   [(set_attr "type" "vecfloat")])
1334
1335 (define_insn "altivec_vperm_<mode>"
1336   [(set (match_operand:V 0 "register_operand" "=v")
1337         (unspec:V [(match_operand:V 1 "register_operand" "v")
1338                    (match_operand:V 2 "register_operand" "v")
1339                    (match_operand:V16QI 3 "register_operand" "v")]
1340                   UNSPEC_VPERM))]
1341   "TARGET_ALTIVEC"
1342   "vperm %0,%1,%2,%3"
1343   [(set_attr "type" "vecperm")])
1344
1345 (define_insn "altivec_vrfip"
1346   [(set (match_operand:V4SF 0 "register_operand" "=v")
1347         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1348                      UNSPEC_VRFIP))]
1349   "TARGET_ALTIVEC"
1350   "vrfip %0,%1"
1351   [(set_attr "type" "vecfloat")])
1352
1353 (define_insn "altivec_vrfin"
1354   [(set (match_operand:V4SF 0 "register_operand" "=v")
1355         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1356                      UNSPEC_VRFIN))]
1357   "TARGET_ALTIVEC"
1358   "vrfin %0,%1"
1359   [(set_attr "type" "vecfloat")])
1360
1361 (define_insn "altivec_vrfim"
1362   [(set (match_operand:V4SF 0 "register_operand" "=v")
1363         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1364                      UNSPEC_VRFIM))]
1365   "TARGET_ALTIVEC"
1366   "vrfim %0,%1"
1367   [(set_attr "type" "vecfloat")])
1368
1369 (define_insn "altivec_vcfux"
1370   [(set (match_operand:V4SF 0 "register_operand" "=v")
1371         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1372                       (match_operand:QI 2 "immediate_operand" "i")]
1373                      UNSPEC_VCFUX))]
1374   "TARGET_ALTIVEC"
1375   "vcfux %0,%1,%2"
1376   [(set_attr "type" "vecfloat")])
1377
1378 (define_insn "altivec_vcfsx"
1379   [(set (match_operand:V4SF 0 "register_operand" "=v")
1380         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1381                       (match_operand:QI 2 "immediate_operand" "i")]
1382                      UNSPEC_VCFSX))]
1383   "TARGET_ALTIVEC"
1384   "vcfsx %0,%1,%2"
1385   [(set_attr "type" "vecfloat")])
1386
1387 (define_insn "altivec_vctuxs"
1388   [(set (match_operand:V4SI 0 "register_operand" "=v")
1389         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1390                       (match_operand:QI 2 "immediate_operand" "i")]
1391                      UNSPEC_VCTUXS))
1392    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1393   "TARGET_ALTIVEC"
1394   "vctuxs %0,%1,%2"
1395   [(set_attr "type" "vecfloat")])
1396
1397 (define_insn "altivec_vctsxs"
1398   [(set (match_operand:V4SI 0 "register_operand" "=v")
1399         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1400                       (match_operand:QI 2 "immediate_operand" "i")]
1401                      UNSPEC_VCTSXS))
1402    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1403   "TARGET_ALTIVEC"
1404   "vctsxs %0,%1,%2"
1405   [(set_attr "type" "vecfloat")])
1406
1407 (define_insn "altivec_vlogefp"
1408   [(set (match_operand:V4SF 0 "register_operand" "=v")
1409         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1410                      UNSPEC_VLOGEFP))]
1411   "TARGET_ALTIVEC"
1412   "vlogefp %0,%1"
1413   [(set_attr "type" "vecfloat")])
1414
1415 (define_insn "altivec_vexptefp"
1416   [(set (match_operand:V4SF 0 "register_operand" "=v")
1417         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1418                      UNSPEC_VEXPTEFP))]
1419   "TARGET_ALTIVEC"
1420   "vexptefp %0,%1"
1421   [(set_attr "type" "vecfloat")])
1422
1423 (define_insn "altivec_vrsqrtefp"
1424   [(set (match_operand:V4SF 0 "register_operand" "=v")
1425         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1426                      UNSPEC_VRSQRTEFP))]
1427   "TARGET_ALTIVEC"
1428   "vrsqrtefp %0,%1"
1429   [(set_attr "type" "vecfloat")])
1430
1431 (define_insn "altivec_vrefp"
1432   [(set (match_operand:V4SF 0 "register_operand" "=v")
1433         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1434                      UNSPEC_VREFP))]
1435   "TARGET_ALTIVEC"
1436   "vrefp %0,%1"
1437   [(set_attr "type" "vecfloat")])
1438
1439 (define_expand "vcondv4si"
1440         [(set (match_operand:V4SI 0 "register_operand" "=v")
1441               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1442                (match_operand:V4SI 2 "register_operand" "v")
1443                (match_operand:V4SI 3 "comparison_operator" "")
1444                (match_operand:V4SI 4 "register_operand" "v")
1445                (match_operand:V4SI 5 "register_operand" "v")
1446                ] UNSPEC_VCOND_V4SI))]
1447         "TARGET_ALTIVEC"
1448         "
1449 {
1450         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1451                                           operands[3], operands[4], operands[5]))
1452         DONE;
1453         else
1454         FAIL;
1455 }
1456         ")
1457
1458 (define_expand "vconduv4si"
1459         [(set (match_operand:V4SI 0 "register_operand" "=v")
1460               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1461                (match_operand:V4SI 2 "register_operand" "v")
1462                (match_operand:V4SI 3 "comparison_operator" "")
1463                (match_operand:V4SI 4 "register_operand" "v")
1464                (match_operand:V4SI 5 "register_operand" "v")
1465                ] UNSPEC_VCONDU_V4SI))]
1466         "TARGET_ALTIVEC"
1467         "
1468 {
1469         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1470                                           operands[3], operands[4], operands[5]))
1471         DONE;
1472         else
1473         FAIL;
1474 }
1475         ")
1476
1477 (define_expand "vcondv4sf"
1478         [(set (match_operand:V4SF 0 "register_operand" "=v")
1479               (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1480                (match_operand:V4SF 2 "register_operand" "v")
1481                (match_operand:V4SF 3 "comparison_operator" "")
1482                (match_operand:V4SF 4 "register_operand" "v")
1483                (match_operand:V4SF 5 "register_operand" "v")
1484                ] UNSPEC_VCOND_V4SF))]
1485         "TARGET_ALTIVEC"
1486         "
1487 {
1488         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1489                                           operands[3], operands[4], operands[5]))
1490         DONE;
1491         else
1492         FAIL;
1493 }
1494         ")
1495
1496 (define_expand "vcondv8hi"
1497         [(set (match_operand:V4SF 0 "register_operand" "=v")
1498               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1499                (match_operand:V8HI 2 "register_operand" "v")
1500                (match_operand:V8HI 3 "comparison_operator" "")
1501                (match_operand:V8HI 4 "register_operand" "v")
1502                (match_operand:V8HI 5 "register_operand" "v")
1503                ] UNSPEC_VCOND_V8HI))]
1504         "TARGET_ALTIVEC"
1505         "
1506 {
1507         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1508                                           operands[3], operands[4], operands[5]))
1509         DONE;
1510         else
1511         FAIL;
1512 }
1513         ")
1514
1515 (define_expand "vconduv8hi"
1516         [(set (match_operand:V4SF 0 "register_operand" "=v")
1517               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1518                (match_operand:V8HI 2 "register_operand" "v")
1519                (match_operand:V8HI 3 "comparison_operator" "")
1520                (match_operand:V8HI 4 "register_operand" "v")
1521                (match_operand:V8HI 5 "register_operand" "v")
1522                ] UNSPEC_VCONDU_V8HI))]
1523         "TARGET_ALTIVEC"
1524         "
1525 {
1526         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1527                                           operands[3], operands[4], operands[5]))
1528         DONE;
1529         else
1530         FAIL;
1531 }
1532         ")
1533
1534 (define_expand "vcondv16qi"
1535         [(set (match_operand:V4SF 0 "register_operand" "=v")
1536               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1537                (match_operand:V16QI 2 "register_operand" "v")
1538                (match_operand:V16QI 3 "comparison_operator" "")
1539                (match_operand:V16QI 4 "register_operand" "v")
1540                (match_operand:V16QI 5 "register_operand" "v")
1541                ] UNSPEC_VCOND_V16QI))]
1542         "TARGET_ALTIVEC"
1543         "
1544 {
1545         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1546                                           operands[3], operands[4], operands[5]))
1547         DONE;
1548         else
1549         FAIL;
1550 }
1551         ")
1552
1553 (define_expand "vconduv16qi"
1554         [(set (match_operand:V4SF 0 "register_operand" "=v")
1555               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1556                (match_operand:V16QI 2 "register_operand" "v")
1557                (match_operand:V16QI 3 "comparison_operator" "")
1558                (match_operand:V16QI 4 "register_operand" "v")
1559                (match_operand:V16QI 5 "register_operand" "v")
1560                ] UNSPEC_VCONDU_V16QI))]
1561         "TARGET_ALTIVEC"
1562         "
1563 {
1564         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1565                                           operands[3], operands[4], operands[5]))
1566         DONE;
1567         else
1568         FAIL;
1569 }
1570         ")
1571
1572
1573 (define_insn "altivec_vsel_v4si"
1574   [(set (match_operand:V4SI 0 "register_operand" "=v")
1575         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1576                       (match_operand:V4SI 2 "register_operand" "v")
1577                       (match_operand:V4SI 3 "register_operand" "v")]
1578                      UNSPEC_VSEL4SI))]
1579   "TARGET_ALTIVEC"
1580   "vsel %0,%1,%2,%3"
1581   [(set_attr "type" "vecperm")])
1582
1583 (define_insn "altivec_vsel_v4sf"
1584   [(set (match_operand:V4SF 0 "register_operand" "=v")
1585         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1586                       (match_operand:V4SF 2 "register_operand" "v")
1587                       (match_operand:V4SI 3 "register_operand" "v")]
1588                       UNSPEC_VSEL4SF))]
1589   "TARGET_ALTIVEC"
1590   "vsel %0,%1,%2,%3"
1591   [(set_attr "type" "vecperm")])
1592
1593 (define_insn "altivec_vsel_v8hi"
1594   [(set (match_operand:V8HI 0 "register_operand" "=v")
1595         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1596                       (match_operand:V8HI 2 "register_operand" "v")
1597                       (match_operand:V8HI 3 "register_operand" "v")]
1598                      UNSPEC_VSEL8HI))]
1599   "TARGET_ALTIVEC"
1600   "vsel %0,%1,%2,%3"
1601   [(set_attr "type" "vecperm")])
1602
1603 (define_insn "altivec_vsel_v16qi"
1604   [(set (match_operand:V16QI 0 "register_operand" "=v")
1605         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1606                        (match_operand:V16QI 2 "register_operand" "v")
1607                        (match_operand:V16QI 3 "register_operand" "v")]
1608                       UNSPEC_VSEL16QI))]
1609   "TARGET_ALTIVEC"
1610   "vsel %0,%1,%2,%3"
1611   [(set_attr "type" "vecperm")])
1612
1613 (define_insn "altivec_vsldoi_<mode>"
1614   [(set (match_operand:V 0 "register_operand" "=v")
1615         (unspec:V [(match_operand:V 1 "register_operand" "v")
1616                    (match_operand:V 2 "register_operand" "v")
1617                    (match_operand:QI 3 "immediate_operand" "i")]
1618                   UNSPEC_VLSDOI))]
1619   "TARGET_ALTIVEC"
1620   "vsldoi %0,%1,%2,%3"
1621   [(set_attr "type" "vecperm")])
1622
1623 (define_insn "altivec_vupkhsb"
1624   [(set (match_operand:V8HI 0 "register_operand" "=v")
1625         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1626                      UNSPEC_VUPKHSB))]
1627   "TARGET_ALTIVEC"
1628   "vupkhsb %0,%1"
1629   [(set_attr "type" "vecperm")])
1630
1631 (define_insn "altivec_vupkhpx"
1632   [(set (match_operand:V4SI 0 "register_operand" "=v")
1633         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1634                      UNSPEC_VUPKHPX))]
1635   "TARGET_ALTIVEC"
1636   "vupkhpx %0,%1"
1637   [(set_attr "type" "vecperm")])
1638
1639 (define_insn "altivec_vupkhsh"
1640   [(set (match_operand:V4SI 0 "register_operand" "=v")
1641         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1642                      UNSPEC_VUPKHSH))]
1643   "TARGET_ALTIVEC"
1644   "vupkhsh %0,%1"
1645   [(set_attr "type" "vecperm")])
1646
1647 (define_insn "altivec_vupklsb"
1648   [(set (match_operand:V8HI 0 "register_operand" "=v")
1649         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1650                      UNSPEC_VUPKLSB))]
1651   "TARGET_ALTIVEC"
1652   "vupklsb %0,%1"
1653   [(set_attr "type" "vecperm")])
1654
1655 (define_insn "altivec_vupklpx"
1656   [(set (match_operand:V4SI 0 "register_operand" "=v")
1657         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1658                      UNSPEC_VUPKLPX))]
1659   "TARGET_ALTIVEC"
1660   "vupklpx %0,%1"
1661   [(set_attr "type" "vecperm")])
1662
1663 (define_insn "altivec_vupklsh"
1664   [(set (match_operand:V4SI 0 "register_operand" "=v")
1665         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1666                      UNSPEC_VUPKLSH))]
1667   "TARGET_ALTIVEC"
1668   "vupklsh %0,%1"
1669   [(set_attr "type" "vecperm")])
1670
1671 ;; AltiVec predicates.
1672
1673 (define_expand "cr6_test_for_zero"
1674   [(set (match_operand:SI 0 "register_operand" "=r")
1675         (eq:SI (reg:CC 74)
1676                (const_int 0)))]
1677   "TARGET_ALTIVEC"
1678   "")
1679
1680 (define_expand "cr6_test_for_zero_reverse"
1681   [(set (match_operand:SI 0 "register_operand" "=r")
1682         (eq:SI (reg:CC 74)
1683                (const_int 0)))
1684    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1685   "TARGET_ALTIVEC"
1686   "")
1687
1688 (define_expand "cr6_test_for_lt"
1689   [(set (match_operand:SI 0 "register_operand" "=r")
1690         (lt:SI (reg:CC 74)
1691                (const_int 0)))]
1692   "TARGET_ALTIVEC"
1693   "")
1694
1695 (define_expand "cr6_test_for_lt_reverse"
1696   [(set (match_operand:SI 0 "register_operand" "=r")
1697         (lt:SI (reg:CC 74)
1698                (const_int 0)))
1699    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1700   "TARGET_ALTIVEC"
1701   "")
1702
1703 ;; We can get away with generating the opcode on the fly (%3 below)
1704 ;; because all the predicates have the same scheduling parameters.
1705
1706 (define_insn "altivec_predicate_<mode>"
1707   [(set (reg:CC 74)
1708         (unspec:CC [(match_operand:V 1 "register_operand" "v")
1709                     (match_operand:V 2 "register_operand" "v")
1710                     (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1711    (clobber (match_scratch:V 0 "=v"))]
1712   "TARGET_ALTIVEC"
1713   "%3 %0,%1,%2"
1714 [(set_attr "type" "veccmp")])
1715
1716 (define_insn "altivec_mtvscr"
1717   [(set (reg:SI 110)
1718         (unspec_volatile:SI
1719          [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1720   "TARGET_ALTIVEC"
1721   "mtvscr %0"
1722   [(set_attr "type" "vecsimple")])
1723
1724 (define_insn "altivec_mfvscr"
1725   [(set (match_operand:V8HI 0 "register_operand" "=v")
1726         (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1727   "TARGET_ALTIVEC"
1728   "mfvscr %0"
1729   [(set_attr "type" "vecsimple")])
1730
1731 (define_insn "altivec_dssall"
1732   [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1733   "TARGET_ALTIVEC"
1734   "dssall"
1735   [(set_attr "type" "vecsimple")])
1736
1737 (define_insn "altivec_dss"
1738   [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1739                     UNSPECV_DSS)]
1740   "TARGET_ALTIVEC"
1741   "dss %0"
1742   [(set_attr "type" "vecsimple")])
1743
1744 (define_insn "altivec_dst"
1745   [(unspec [(match_operand 0 "register_operand" "b")
1746             (match_operand:SI 1 "register_operand" "r")
1747             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1748   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1749   "dst %0,%1,%2"
1750   [(set_attr "type" "vecsimple")])
1751
1752 (define_insn "altivec_dstt"
1753   [(unspec [(match_operand 0 "register_operand" "b")
1754             (match_operand:SI 1 "register_operand" "r")
1755             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1756   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1757   "dstt %0,%1,%2"
1758   [(set_attr "type" "vecsimple")])
1759
1760 (define_insn "altivec_dstst"
1761   [(unspec [(match_operand 0 "register_operand" "b")
1762             (match_operand:SI 1 "register_operand" "r")
1763             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1764   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1765   "dstst %0,%1,%2"
1766   [(set_attr "type" "vecsimple")])
1767
1768 (define_insn "altivec_dststt"
1769   [(unspec [(match_operand 0 "register_operand" "b")
1770             (match_operand:SI 1 "register_operand" "r")
1771             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1772   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1773   "dststt %0,%1,%2"
1774   [(set_attr "type" "vecsimple")])
1775
1776 (define_insn "altivec_lvsl"
1777   [(set (match_operand:V16QI 0 "register_operand" "=v")
1778         (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1779   "TARGET_ALTIVEC"
1780   "lvsl %0,%y1"
1781   [(set_attr "type" "vecload")])
1782
1783 (define_insn "altivec_lvsr"
1784   [(set (match_operand:V16QI 0 "register_operand" "=v")
1785         (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1786   "TARGET_ALTIVEC"
1787   "lvsr %0,%y1"
1788   [(set_attr "type" "vecload")])
1789
1790 (define_expand "build_vector_mask_for_load"
1791   [(set (match_operand:V16QI 0 "register_operand" "")
1792         (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1793   "TARGET_ALTIVEC"
1794   "
1795 {
1796   rtx addr;
1797   rtx temp;
1798
1799   gcc_assert (GET_CODE (operands[1]) == MEM);
1800
1801   addr = XEXP (operands[1], 0);
1802   temp = gen_reg_rtx (GET_MODE (addr));
1803   emit_insn (gen_rtx_SET (VOIDmode, temp,
1804                           gen_rtx_NEG (GET_MODE (addr), addr)));
1805   emit_insn (gen_altivec_lvsr (operands[0],
1806                                replace_equiv_address (operands[1], temp)));
1807   DONE;
1808 }")
1809
1810 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1811 ;; identical rtl but different instructions-- and gcc gets confused.
1812
1813 (define_insn "altivec_lve<VI_char>x"
1814   [(parallel
1815     [(set (match_operand:VI 0 "register_operand" "=v")
1816           (match_operand:VI 1 "memory_operand" "Z"))
1817      (unspec [(const_int 0)] UNSPEC_LVE)])]
1818   "TARGET_ALTIVEC"
1819   "lve<VI_char>x %0,%y1"
1820   [(set_attr "type" "vecload")])
1821
1822 (define_insn "*altivec_lvesfx"
1823   [(parallel
1824     [(set (match_operand:V4SF 0 "register_operand" "=v")
1825           (match_operand:V4SF 1 "memory_operand" "Z"))
1826      (unspec [(const_int 0)] UNSPEC_LVE)])]
1827   "TARGET_ALTIVEC"
1828   "lvewx %0,%y1"
1829   [(set_attr "type" "vecload")])
1830
1831 (define_insn "altivec_lvxl"
1832   [(parallel
1833     [(set (match_operand:V4SI 0 "register_operand" "=v")
1834           (match_operand:V4SI 1 "memory_operand" "Z"))
1835      (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1836   "TARGET_ALTIVEC"
1837   "lvxl %0,%y1"
1838   [(set_attr "type" "vecload")])
1839
1840 (define_insn "altivec_lvx"
1841   [(set (match_operand:V4SI 0 "register_operand" "=v")
1842         (match_operand:V4SI 1 "memory_operand" "Z"))]
1843   "TARGET_ALTIVEC"
1844   "lvx %0,%y1"
1845   [(set_attr "type" "vecload")])
1846
1847 (define_insn "altivec_stvx"
1848   [(parallel
1849     [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1850           (match_operand:V4SI 1 "register_operand" "v"))
1851      (unspec [(const_int 0)] UNSPEC_STVX)])]
1852   "TARGET_ALTIVEC"
1853   "stvx %1,%y0"
1854   [(set_attr "type" "vecstore")])
1855
1856 (define_insn "altivec_stvxl"
1857   [(parallel
1858     [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1859           (match_operand:V4SI 1 "register_operand" "v"))
1860      (unspec [(const_int 0)] UNSPEC_STVXL)])]
1861   "TARGET_ALTIVEC"
1862   "stvxl %1,%y0"
1863   [(set_attr "type" "vecstore")])
1864
1865 (define_insn "altivec_stve<VI_char>x"
1866   [(parallel
1867     [(set (match_operand:VI 0 "memory_operand" "=Z")
1868           (match_operand:VI 1 "register_operand" "v"))
1869      (unspec [(const_int 0)] UNSPEC_STVE)])]
1870   "TARGET_ALTIVEC"
1871   "stve<VI_char>x %1,%y0"
1872   [(set_attr "type" "vecstore")])
1873
1874 (define_insn "*altivec_stvesfx"
1875   [(parallel
1876     [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1877           (match_operand:V4SF 1 "register_operand" "v"))
1878      (unspec [(const_int 0)] UNSPEC_STVE)])]
1879   "TARGET_ALTIVEC"
1880   "stvewx %1,%y0"
1881   [(set_attr "type" "vecstore")])
1882
1883 (define_expand "vec_init<mode>"
1884   [(match_operand:V 0 "register_operand" "")
1885    (match_operand 1 "" "")]
1886   "TARGET_ALTIVEC"
1887 {
1888   rs6000_expand_vector_init (operands[0], operands[1]);
1889   DONE;
1890 })
1891
1892 (define_expand "vec_setv4si"
1893   [(match_operand:V4SI 0 "register_operand" "")
1894    (match_operand:SI 1 "register_operand" "")
1895    (match_operand 2 "const_int_operand" "")]
1896   "TARGET_ALTIVEC"
1897 {
1898   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1899   DONE;
1900 })
1901
1902 (define_expand "vec_setv8hi"
1903   [(match_operand:V8HI 0 "register_operand" "")
1904    (match_operand:HI 1 "register_operand" "")
1905    (match_operand 2 "const_int_operand" "")]
1906   "TARGET_ALTIVEC"
1907 {
1908   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1909   DONE;
1910 })
1911
1912 (define_expand "vec_setv16qi"
1913   [(match_operand:V16QI 0 "register_operand" "")
1914    (match_operand:QI 1 "register_operand" "")
1915    (match_operand 2 "const_int_operand" "")]
1916   "TARGET_ALTIVEC"
1917 {
1918   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1919   DONE;
1920 })
1921
1922 (define_expand "vec_setv4sf"
1923   [(match_operand:V4SF 0 "register_operand" "")
1924    (match_operand:SF 1 "register_operand" "")
1925    (match_operand 2 "const_int_operand" "")]
1926   "TARGET_ALTIVEC"
1927 {
1928   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1929   DONE;
1930 })
1931
1932 (define_expand "vec_extractv4si"
1933   [(match_operand:SI 0 "register_operand" "")
1934    (match_operand:V4SI 1 "register_operand" "")
1935    (match_operand 2 "const_int_operand" "")]
1936   "TARGET_ALTIVEC"
1937 {
1938   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1939   DONE;
1940 })
1941
1942 (define_expand "vec_extractv8hi"
1943   [(match_operand:HI 0 "register_operand" "")
1944    (match_operand:V8HI 1 "register_operand" "")
1945    (match_operand 2 "const_int_operand" "")]
1946   "TARGET_ALTIVEC"
1947 {
1948   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1949   DONE;
1950 })
1951
1952 (define_expand "vec_extractv16qi"
1953   [(match_operand:QI 0 "register_operand" "")
1954    (match_operand:V16QI 1 "register_operand" "")
1955    (match_operand 2 "const_int_operand" "")]
1956   "TARGET_ALTIVEC"
1957 {
1958   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1959   DONE;
1960 })
1961
1962 (define_expand "vec_extractv4sf"
1963   [(match_operand:SF 0 "register_operand" "")
1964    (match_operand:V4SF 1 "register_operand" "")
1965    (match_operand 2 "const_int_operand" "")]
1966   "TARGET_ALTIVEC"
1967 {
1968   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1969   DONE;
1970 })
1971
1972 ;; Generate
1973 ;;    vspltis? SCRATCH0,0
1974 ;;    vsubu?m SCRATCH2,SCRATCH1,%1
1975 ;;    vmaxs? %0,%1,SCRATCH2"
1976 (define_expand "abs<mode>2"
1977   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1978    (set (match_dup 3)
1979         (minus:VI (match_dup 2)
1980                   (match_operand:VI 1 "register_operand" "v")))
1981    (set (match_operand:VI 0 "register_operand" "=v")
1982         (smax:VI (match_dup 1) (match_dup 3)))]
1983   "TARGET_ALTIVEC"
1984 {
1985   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1986   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1987 })
1988
1989 ;; Generate
1990 ;;    vspltisw SCRATCH1,-1
1991 ;;    vslw SCRATCH2,SCRATCH1,SCRATCH1
1992 ;;    vandc %0,%1,SCRATCH2
1993 (define_expand "absv4sf2"
1994   [(set (match_dup 2)
1995         (vec_duplicate:V4SF (float:SF (const_int -1))))
1996    (set (match_dup 3)
1997         (unspec:V4SF [(match_dup 2) (match_dup 2)] UNSPEC_VSLW))
1998    (set (match_operand:V4SF 0 "register_operand" "=v")
1999         (and:V4SF (not:V4SF (match_dup 3))
2000                   (match_operand:V4SF 1 "register_operand" "v")))]
2001   "TARGET_ALTIVEC"
2002 {
2003   operands[2] = gen_reg_rtx (V4SFmode);
2004   operands[3] = gen_reg_rtx (V4SFmode);
2005 })
2006
2007 ;; Generate
2008 ;;    vspltis? SCRATCH0,0
2009 ;;    vsubs?s SCRATCH2,SCRATCH1,%1
2010 ;;    vmaxs? %0,%1,SCRATCH2"
2011 (define_expand "altivec_abss_<mode>"
2012   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2013    (parallel [(set (match_dup 3)
2014                    (unspec:VI [(match_dup 2)
2015                                (match_operand:VI 1 "register_operand" "v")]
2016                               UNSPEC_VSUBS))
2017               (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2018    (set (match_operand:VI 0 "register_operand" "=v")
2019         (smax:VI (match_dup 1) (match_dup 3)))]
2020   "TARGET_ALTIVEC"
2021 {
2022   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2023   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2024 })
2025
2026 ;; Vector shift left in bits. Currently supported ony for shift
2027 ;; amounts that can be expressed as byte shifts (divisible by 8).
2028 ;; General shift amounts can be supported using vslo + vsl. We're
2029 ;; not expecting to see these yet (the vectorizer currently
2030 ;; generates only shifts divisible by byte_size).
2031 (define_expand "vec_shl_<mode>"
2032   [(set (match_operand:V 0 "register_operand" "=v")
2033         (unspec:V [(match_operand:V 1 "register_operand" "v")
2034                    (match_operand:QI 2 "reg_or_short_operand" "")]
2035                   UNSPEC_VECSH))]
2036   "TARGET_ALTIVEC"
2037   "
2038 {
2039   rtx bitshift = operands[2];
2040   rtx byteshift = gen_reg_rtx (QImode);
2041   HOST_WIDE_INT bitshift_val;
2042   HOST_WIDE_INT byteshift_val;
2043
2044   if (! CONSTANT_P (bitshift))
2045     FAIL;
2046   bitshift_val = INTVAL (bitshift);
2047   if (bitshift_val & 0x7)
2048     FAIL;
2049   byteshift_val = bitshift_val >> 3;
2050   byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2051   emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2052                                         byteshift));
2053   DONE;
2054 }")
2055
2056 ;; Vector shift left in bits. Currently supported ony for shift
2057 ;; amounts that can be expressed as byte shifts (divisible by 8).
2058 ;; General shift amounts can be supported using vsro + vsr. We're
2059 ;; not expecting to see these yet (the vectorizer currently
2060 ;; generates only shifts divisible by byte_size).
2061 (define_expand "vec_shr_<mode>"
2062   [(set (match_operand:V 0 "register_operand" "=v")
2063         (unspec:V [(match_operand:V 1 "register_operand" "v")
2064                    (match_operand:QI 2 "reg_or_short_operand" "")]
2065                   UNSPEC_VECSH))]
2066   "TARGET_ALTIVEC"
2067   "
2068 {
2069   rtx bitshift = operands[2];
2070   rtx byteshift = gen_reg_rtx (QImode);
2071   HOST_WIDE_INT bitshift_val;
2072   HOST_WIDE_INT byteshift_val;
2073
2074   if (! CONSTANT_P (bitshift))
2075     FAIL;
2076   bitshift_val = INTVAL (bitshift);
2077   if (bitshift_val & 0x7)
2078     FAIL;
2079   byteshift_val = 16 - (bitshift_val >> 3);
2080   byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2081   emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2082                                         byteshift));
2083   DONE;
2084 }")
2085
2086 (define_insn "altivec_vsumsws_nomode"
2087   [(set (match_operand 0 "register_operand" "=v")
2088         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2089                       (match_operand:V4SI 2 "register_operand" "v")]
2090                      UNSPEC_VSUMSWS))
2091    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2092   "TARGET_ALTIVEC"
2093   "vsumsws %0,%1,%2"
2094   [(set_attr "type" "veccomplex")])
2095
2096 (define_expand "reduc_splus_<mode>"
2097   [(set (match_operand:VIshort 0 "register_operand" "=v")
2098         (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2099                         UNSPEC_REDUC_PLUS))]
2100   "TARGET_ALTIVEC"
2101   "
2102 {
2103   rtx vzero = gen_reg_rtx (V4SImode);
2104   rtx vtmp1 = gen_reg_rtx (V4SImode);
2105
2106   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2107   emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2108   emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2109   DONE;
2110 }")
2111
2112 (define_expand "reduc_uplus_v16qi"
2113   [(set (match_operand:V16QI 0 "register_operand" "=v")
2114         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2115                       UNSPEC_REDUC_PLUS))]
2116   "TARGET_ALTIVEC"
2117   "
2118 {
2119   rtx vzero = gen_reg_rtx (V4SImode);
2120   rtx vtmp1 = gen_reg_rtx (V4SImode);
2121
2122   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2123   emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2124   emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2125   DONE;
2126 }")
2127
2128 (define_insn "vec_realign_load_<mode>"
2129   [(set (match_operand:V 0 "register_operand" "=v")
2130         (unspec:V [(match_operand:V 1 "register_operand" "v")
2131                    (match_operand:V 2 "register_operand" "v")
2132                    (match_operand:V16QI 3 "register_operand" "v")]
2133                   UNSPEC_REALIGN_LOAD))]
2134   "TARGET_ALTIVEC"
2135   "vperm %0,%1,%2,%3"
2136   [(set_attr "type" "vecperm")])
2137
2138 (define_expand "neg<mode>2"
2139   [(use (match_operand:VI 0 "register_operand" ""))
2140    (use (match_operand:VI 1 "register_operand" ""))]
2141   "TARGET_ALTIVEC"
2142   "
2143 {
2144   rtx vzero;
2145
2146   vzero = gen_reg_rtx (GET_MODE (operands[0]));
2147   emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2148   emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2149
2150   DONE;
2151 }")
2152
2153 (define_expand "negv4sf2"
2154   [(use (match_operand:V4SF 0 "register_operand" ""))
2155    (use (match_operand:V4SF 1 "register_operand" ""))]
2156   "TARGET_ALTIVEC"
2157   "
2158 {
2159   rtx neg0;
2160
2161   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
2162   neg0 = gen_reg_rtx (V4SFmode);
2163   emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
2164   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
2165
2166   /* XOR */
2167   emit_insn (gen_xorv4sf3 (operands[0], neg0, operands[1]));
2168
2169   DONE;
2170 }")