1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001,2008 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
54 #include "picochip-protos.h"
56 #include "insn-attr.h" /* For DFA state_t. */
57 #include "insn-config.h" /* Required by recog.h */
58 #include "insn-codes.h" /* For CODE_FOR_? */
59 #include "optabs.h" /* For GEN_FCN */
60 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
61 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
62 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
63 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
66 /* Target AE ISA information. */
67 enum picochip_dfa_type picochip_schedule_type;
69 bool picochip_has_mul_unit = false;
70 bool picochip_has_mac_unit = false;
72 /* targetm hook function prototypes. */
74 void picochip_asm_file_start (void);
75 void picochip_asm_file_end (void);
77 void picochip_init_libfuncs (void);
78 void picochip_reorg (void);
80 int picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum,
81 enum machine_mode mode,
82 tree type, bool named);
84 int picochip_sched_lookahead (void);
85 int picochip_sched_issue_rate (void);
86 int picochip_sched_adjust_cost (rtx insn, rtx link,
87 rtx dep_insn, int cost);
88 int picochip_sched_reorder (FILE * file, int verbose, rtx * ready,
89 int *n_readyp, int clock);
91 void picochip_init_builtins (void);
92 rtx picochip_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
94 bool picochip_rtx_costs (rtx x, int code, int outer_code, int* total);
95 bool picochip_return_in_memory(const_tree type,
96 const_tree fntype ATTRIBUTE_UNUSED);
98 rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
99 rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
100 bool outgoing ATTRIBUTE_UNUSED);
102 picochip_secondary_reload (bool in_p,
103 rtx x ATTRIBUTE_UNUSED,
104 enum reg_class cla ATTRIBUTE_UNUSED,
105 enum machine_mode mode,
106 secondary_reload_info *sri);
108 picochip_asm_named_section (const char *name,
109 unsigned int flags ATTRIBUTE_UNUSED,
110 tree decl ATTRIBUTE_UNUSED);
112 /* Lookup table mapping a register number to the earliest containing
113 class. Used by REGNO_REG_CLASS. */
114 const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER] =
116 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
117 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
118 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
119 GR_REGS, FRAME_REGS, PTR_REGS, CONST_REGS,
120 ACC_REGS, CC_REGS, GR_REGS, GR_REGS
123 /* picoChip register names. */
124 const char *picochip_regnames[] = REGISTER_NAMES;
126 /* Define the maximum number of registers which may be used to pass
127 * parameters to functions. */
128 #define MAX_CALL_PARAMETER_REGS 6
131 /* Target scheduling information. */
133 /* Determine whether we run our final scheduling pass or not. We always
134 avoid the normal second scheduling pass. */
135 int picochip_flag_schedule_insns2;
137 /* Check if variable tracking needs to be run. */
138 int picochip_flag_var_tracking;
140 /* This flag indicates whether the next instruction to be output is a
141 VLIW continuation instruction. It is used to communicate between
142 final_prescan_insn and asm_output_opcode. */
143 static int picochip_vliw_continuation = 0;
145 /* This variable is used to communicate the current instruction
146 between final_prescan_insn and functions such as asm_output_opcode,
147 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
148 current instruction. */
149 static rtx picochip_current_prescan_insn;
151 static bool picochip_is_delay_slot_pending = 0;
153 /* When final_prescan_insn is called, it computes information about
154 the current VLIW packet, and stores it in this structure. When
155 instructions are output, this state is used to make sure that the
156 instructions are output in the correct way (e.g., which ALU to use,
157 whether a macro branch was ever previously a real branch, etc.). */
160 int contains_pico_alu_insn;
161 int contains_non_cc_alu_insn;
162 int num_alu_insns_so_far;
164 /* Record how many instructions are contained in the packet. */
165 int num_insns_in_packet;
167 /* There was a case for this to be more than 1 */
168 int num_cfi_labels_deferred;
169 char cfi_label_name[2][256]; /* Used to record the name of a CFI label
170 emitted inside a VLIW packet. */
171 char lm_label_name[256]; /* Used to record the name of an LM label. */
174 struct vliw_state picochip_current_vliw_state;
176 /* Save/restore recog_data. */
177 static int picochip_saved_which_alternative;
178 static struct recog_data picochip_saved_recog_data;
180 /* Determine which ALU to use for the instruction in
181 picochip_current_prescan_insn. */
182 static char picochip_get_vliw_alu_id (void);
184 /* Initialize the GCC target structure. */
186 #undef TARGET_ASM_FUNCTION_PROLOGUE
187 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
189 #undef TARGET_ASM_FUNCTION_EPILOGUE
190 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
192 #undef TARGET_ASM_INTERNAL_LABEL
193 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
195 #undef TARGET_ASM_GLOBALIZE_LABEL
196 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
198 #undef TARGET_ASM_BYTE_OP
199 #define TARGET_ASM_BYTE_OP ".initByte "
200 #undef TARGET_ASM_ALIGNED_HI_OP
201 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
202 #undef TARGET_ASM_UNALIGNED_HI_OP
203 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
204 #undef TARGET_ASM_ALIGNED_SI_OP
205 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
206 #undef TARGET_ASM_UNALIGNED_SI_OP
207 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
209 #undef TARGET_INIT_BUILTINS
210 #define TARGET_INIT_BUILTINS picochip_init_builtins
212 #undef TARGET_EXPAND_BUILTIN
213 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
215 #undef TARGET_RTX_COSTS
216 #define TARGET_RTX_COSTS picochip_rtx_costs
218 #undef TARGET_SCHED_ISSUE_RATE
219 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
221 #undef TARGET_SCHED_REORDER
222 #define TARGET_SCHED_REORDER picochip_sched_reorder
224 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
225 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
226 picochip_sched_lookahead
228 #undef TARGET_SCHED_ADJUST_COST
229 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
231 #undef TARGET_ASM_NAMED_SECTION
232 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
234 #undef TARGET_HAVE_NAMED_SECTIONS
235 #define TARGET_HAVE_NAMED_SECTIONS 1
237 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
238 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
240 #undef TARGET_INIT_LIBFUNCS
241 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
243 #undef TARGET_ASM_FILE_START
244 #define TARGET_ASM_FILE_START picochip_asm_file_start
246 #undef TARGET_ASM_FILE_END
247 #define TARGET_ASM_FILE_END picochip_asm_file_end
249 #undef TARGET_MACHINE_DEPENDENT_REORG
250 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
252 #undef TARGET_ARG_PARTIAL_BYTES
253 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
255 #undef TARGET_PROMOTE_FUNCTION_ARGS
256 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
257 #undef TARGET_PROMOTE_FUNCTION_RETURN
258 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
259 #undef TARGET_PROMOTE_PROTOTYPES
260 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
262 /* Target support for Anchored Addresses optimization */
263 #undef TARGET_MIN_ANCHOR_OFFSET
264 #define TARGET_MIN_ANCHOR_OFFSET 0
265 #undef TARGET_MAX_ANCHOR_OFFSET
266 #define TARGET_MAX_ANCHOR_OFFSET 7
267 #undef TARGET_ASM_OUTPUT_ANCHOR
268 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
270 #undef TARGET_FUNCTION_VALUE
271 #define TARGET_FUNCTION_VALUE picochip_function_value
273 #undef TARGET_LIBGCC_CMP_RETURN_MODE
274 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
277 /* Loading and storing QImode values to and from memory
278 usually requires a scratch register. */
279 #undef TARGET_SECONDARY_RELOAD
280 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
281 #undef DONT_USE_BUILTIN_SETJMP
282 #define DONT_USE_BUILTIN_SETJMP 1
284 /* How Large Values are Returned */
286 #undef TARGET_RETURN_IN_MEMORY
287 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
289 struct gcc_target targetm = TARGET_INITIALIZER;
292 /* Only return a value in memory if it is greater than 4 bytes.
293 int_size_in_bytes returns -1 for variable size objects, which go in
294 memory always. The cast to unsigned makes -1 > 8. */
297 picochip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
299 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 4);
302 /* Allow certain command options to be overriden. */
304 picochip_override_options (void)
307 /* Turn off the elimination of unused types. The elaborator
308 generates various interesting types to represent constants,
309 generics, and so on, and it is useful to retain this information
310 in the debug output. The increased size of the debug information
311 is not really an issue for us. */
312 flag_eliminate_unused_debug_types = 0;
314 /* Even if the user specifies a -fno-omit-frame-pointer on the
315 command line, we still want to go ahead and omit frame pointer
316 usages, since we dont really have a frame pointer register.
317 So, all accesses to FP need to be converted to accesses off
319 flag_omit_frame_pointer = 1;
321 /* Turning on anchored addresses by default. This is an optimization
322 that could decrease the code size by placing anchors in data and
323 accessing offsets from the anchor for file local data variables.
324 This isnt the default at O2 as yet. */
325 flag_section_anchors = 1;
327 /* CFI asm labels are not supported by the picochip assembler yet */
328 flag_dwarf2_cfi_asm = 0;
330 /* Turn off the second scheduling pass, and move it to
331 picochip_reorg, to avoid having the second jump optimisation
332 trash the instruction modes (e.g., instructions are changed to
333 TImode to mark the beginning of cycles). Two types of DFA
334 scheduling are possible: space and speed. In both cases,
335 instructions are reordered to avoid stalls (e.g., memory loads
336 stall for one cycle). Speed scheduling will also enable VLIW
337 instruction packing. VLIW instructions use more code space, so
338 VLIW scheduling is disabled when scheduling for size. */
339 picochip_flag_schedule_insns2 = flag_schedule_insns_after_reload;
340 flag_schedule_insns_after_reload = 0;
341 if (picochip_flag_schedule_insns2)
345 picochip_schedule_type = DFA_TYPE_SPACE;
348 picochip_schedule_type = DFA_TYPE_SPEED;
349 flag_delayed_branch = 0;
354 picochip_schedule_type = DFA_TYPE_NONE;
356 /* Ensure that the debug level is always at least -g2. The flow
357 analyser works at its best if it always has debug
358 information. DWARF is non-intrusive, so it makes no difference to
359 code quality if debug is always enabled. */
360 if (debug_info_level < DINFO_LEVEL_NORMAL)
362 debug_info_level = DINFO_LEVEL_NORMAL;
363 write_symbols = DWARF2_DEBUG;
366 /* Options of the form -mae=mac, and so on will be substituted by
367 the compiler driver for the appropriate byte access and multiply
368 unit ISA options. Any unrecognised AE types will end up being
369 passed to the compiler, which should reject them as invalid. */
370 if (picochip_ae_type_string != NULL)
371 error ("invalid AE type specified (%s)\n", picochip_ae_type_string);
373 /* Override any specific capabilities of the instruction set. These
374 take precedence over any capabilities inferred from the AE type,
375 regardless of where the options appear on the command line. */
376 if (picochip_mul_type_string == NULL)
378 /* Default to MEM-type multiply, for historical compatibility. */
379 picochip_has_mac_unit = false;
380 picochip_has_mul_unit = true;
384 picochip_has_mac_unit = false;
385 picochip_has_mul_unit = false;
387 if (strcmp (picochip_mul_type_string, "mul") == 0)
388 picochip_has_mul_unit = true;
389 else if (strcmp (picochip_mul_type_string, "mac") == 0)
390 picochip_has_mac_unit = true;
391 else if (strcmp (picochip_mul_type_string, "none") == 0)
392 { /* Do nothing. Unit types already set to false. */ }
394 error ("Invalid mul type specified (%s) - expected mac, mul or none",
395 picochip_mul_type_string);
401 /* Initialise the library functions to handle arithmetic on some of
404 picochip_init_libfuncs (void)
407 set_optab_libfunc (ashr_optab, DImode, "__ashrdi3");
408 set_optab_libfunc (ashl_optab, DImode, "__ashldi3");
409 set_optab_libfunc (lshr_optab, DImode, "__lshrdi3");
411 /* 64-bit signed multiplication. */
412 set_optab_libfunc (smul_optab, DImode, "__muldi3");
414 /* Signed division */
415 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
416 set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
419 set_optab_libfunc (smod_optab, HImode, "__modhi3");
420 set_optab_libfunc (smod_optab, DImode, "__moddi3");
422 /* 32-bit count leading Zeros*/
423 set_optab_libfunc (clz_optab, SImode, "_clzsi2");
425 /* 64-bit comparison */
426 set_optab_libfunc (ucmp_optab, DImode, "__ucmpdi2");
427 set_optab_libfunc (cmp_optab, DImode, "__cmpdi2");
429 /* 64-bit addition and subtraction*/
430 set_optab_libfunc (add_optab, DImode, "_adddi3");
431 set_optab_libfunc (sub_optab, DImode, "_subdi3");
434 /* Return the register class for letter C. */
436 picochip_reg_class_from_letter (unsigned c)
454 pico_leaf_reg_alloc_order[] = LEAF_REG_ALLOC_ORDER;
456 pico_nonleaf_reg_alloc_order[] = REG_ALLOC_ORDER;
459 picochip_order_regs_for_local_alloc (void)
461 /* We change the order for leaf functions alone. We put r12 at
462 the end since using it will prevent us to combine stw/ldws to
463 stl/ldl and it gives no benefit. In non-leaf functions, we
464 would anyway saveup/restore r12, so it makes sense to use it.*/
466 if (leaf_function_p())
468 memcpy ((char *)reg_alloc_order, (const char *) pico_leaf_reg_alloc_order,
469 FIRST_PSEUDO_REGISTER * sizeof (int));
473 memcpy ((char *)reg_alloc_order, (const char *) pico_nonleaf_reg_alloc_order,
474 FIRST_PSEUDO_REGISTER * sizeof (int));
478 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
480 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value, unsigned c)
485 case 'I': /* 4 bits signed. */
486 return value + 8 < 16;
487 case 'J': /* 4 bits unsigned. */
489 case 'K': /* 8 bits signed. */
490 return value + 128 < 256;
491 case 'M': /* 4-bit magnitude. */
492 return abs (value) < 16;
493 case 'N': /* 10 bits signed. */
494 return value + 512 > 1024;
495 case 'O': /* 16 bits signed. */
496 return value + 32768 < 65536;
497 default: /* Unknown letter. */
502 /* Stack utility functions. */
504 picochip_return_addr_rtx(int count, rtx frameaddr ATTRIBUTE_UNUSED)
507 return gen_rtx_REG (Pmode, LINK_REGNUM);
513 /* Emit a set of parallel register expressions used to store
514 blockmode values to pass to functions. */
516 picochip_emit_register_parallel (int size_in_units, int offset)
520 rtx vector[MAX_CALL_PARAMETER_REGS];
524 /* Compute the base register, and number of required registers. */
525 base_reg = offset / 2;
526 num_regs = size_in_units / 2;
527 if (size_in_units % 2 == 1)
530 /* Emit a register for each part of the block mode value to be
531 passed in a register. */
532 for (i = 0; i < num_regs; i++)
533 vector[i] = gen_rtx_EXPR_LIST (VOIDmode,
534 gen_rtx_REG (HImode, base_reg + i),
536 result = gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (num_regs, vector));
542 /* Emit an instruction to allocate a suitable amount of space on the
543 stack, by decrementing the stack pointer. */
545 picochip_emit_stack_allocate (int adjustment)
548 rtx stack_pointer_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
550 /* Use an addition of a negative value. */
551 insn = emit_insn (gen_addhi3 (stack_pointer_reg, stack_pointer_reg,
552 GEN_INT (-adjustment)));
554 /* Make the instruction frame related. Also add an expression note,
555 so that the correct Dwarf information is generated (see documention
556 for RTX_FRAME_RELATED_P for more details). */
557 RTX_FRAME_RELATED_P (insn) = 1;
559 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
560 gen_rtx_SET (VOIDmode, stack_pointer_reg,
561 gen_rtx_PLUS (Pmode, stack_pointer_reg,
562 GEN_INT (-adjustment))),
567 /* Emit an instruction to save a register of the given mode. The
568 offset at which to save the register is given relative to the stack
571 picochip_emit_save_register (rtx reg, int offset)
573 rtx stack_pointer, address, mem, insn;
575 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
577 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
579 mem = gen_rtx_MEM (GET_MODE (reg), address);
581 insn = emit_move_insn (mem, reg);
582 RTX_FRAME_RELATED_P (insn) = 1;
584 /* For modes other than HImode, create a note explaining that
585 multiple registers have been saved. This allows the correct DWARF
586 call frame information to be generated. */
587 switch (GET_MODE (reg))
590 /* The RTL is sufficient to explain HImode register saves. */
594 /* SImode must be broken down into parallel HImode register saves. */
602 gen_rtx_PLUS (Pmode, stack_pointer,
604 gen_rtx_REG (HImode, REGNO (reg)));
605 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 0)) = 1;
608 gen_rtx_SET (HImode, gen_rtx_MEM (HImode,
613 gen_rtx_REG (HImode, REGNO (reg) + 1));
614 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 1)) = 1;
617 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
618 gen_rtx_PARALLEL (VOIDmode, p),
626 ("unexpected mode %s encountered in picochip_emit_save_register\n",
627 GET_MODE_NAME (GET_MODE (reg)));
632 /* Emit an instruction to restore a register of the given mode. The
633 offset from which to restore the register is given relative to the
636 picochip_emit_restore_register (rtx reg, int offset)
638 rtx stack_pointer, address, mem, insn;
640 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
642 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
644 mem = gen_rtx_MEM (GET_MODE (reg), address);
646 insn = emit_move_insn (reg, mem);
650 /* Check that the given byte offset is aligned to the given number of
653 picochip_is_aligned (int byte_offset, int bit_alignment)
655 int byte_alignment = bit_alignment / BITS_PER_UNIT;
656 return (byte_offset % byte_alignment) == 0;
659 /*****************************************************************************
662 * The following section contains code which controls how the stack is
665 * The stack is laid out as follows (high addresses first):
668 * Pretend arguments (ARG PTR)
672 * Outgoing arguments (SP)
674 * The (constant) offsets of the different areas must be calculated
675 * relative to the stack area immediately below, and aligned
676 * appropriately. For example, the frame offset is computed by
677 * determining the offset of the special register area, adding the
678 * size of the special register area, and then aligning the resulting
679 * offset correctly. In turn, the special register offset is computed
680 * from the general register offset, and so on. This enables the
681 * different offsets to change size and alignment, without requiring
682 * the code for other offset calculations to be rewritten.
684 * The argument pointer, and the frame pointer are eliminated wherever
685 * possible, by replacing them with a constant offset from the stack
686 * pointer. In the rare cases where constant offsets from the stack
687 * pointer cannot be computed, another register will be allocated to
688 * serve as the argument pointer, or the frame pointer.
690 * The save registers are stored at small offsets from the caller, to
691 * enable the more efficient SP-based ISA instructions to be used.
693 ****************************************************************************/
695 /* Compute the size of an argument in units. */
697 picochip_compute_arg_size (tree type, enum machine_mode mode)
699 int type_size_in_units = 0;
702 type_size_in_units = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
704 type_size_in_units = GET_MODE_SIZE (mode);
706 return type_size_in_units;
710 /* Determine where the next outgoing arg should be placed. */
712 picochip_function_arg (CUMULATIVE_ARGS cum, int mode, tree type,
713 int named ATTRIBUTE_UNUSED)
716 int type_align_in_units = 0;
717 int type_size_in_units;
719 int offset_overflow = 0;
721 /* VOIDmode is passed when computing the second argument to a `call'
722 pattern. This can be ignored. */
723 if (mode == VOIDmode)
726 /* Compute the alignment and size of the parameter. */
727 type_align_in_units =
728 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
729 type_size_in_units = picochip_compute_arg_size (type, mode);
731 /* Compute the correct offset (i.e., ensure that the offset meets
732 the alignment requirements). */
733 offset_overflow = cum % type_align_in_units;
734 if (offset_overflow == 0)
737 new_offset = (cum - offset_overflow) + type_align_in_units;
741 printf ("Function arg:\n");
742 printf (" Type valid: %s\n", (type ? "yes" : "no"));
743 printf (" Cumulative Value: %d\n", cum);
744 printf (" Mode: %s\n", GET_MODE_NAME (mode));
745 printf (" Type size: %i units\n", type_size_in_units);
746 printf (" Alignment: %i units\n", type_align_in_units);
747 printf (" New offset: %i\n", new_offset);
751 /* If the new offset is outside the register space, return. */
752 if (new_offset >= MAX_CALL_PARAMETER_REGS * 2)
755 /* If the end of the argument is outside the register space, then
756 the argument must overlap the register space. Return the first
757 available register. */
758 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
759 return gen_rtx_REG (HImode, new_offset / 2);
761 /* Create a register of the required mode to hold the parameter. */
762 reg = new_offset / 2;
777 return gen_rtx_REG ((enum machine_mode) mode, reg);
781 /* Empty blockmode values can be passed as arguments (e.g.,
782 * empty structs). These require no registers
783 * whatsoever. Non-empty blockmode values are passed in a set
784 * of parallel registers. */
785 if (type_size_in_units == 0)
788 return picochip_emit_register_parallel (type_size_in_units, new_offset);
793 (0, "Defaulting to stack for %s register creation\n",
794 GET_MODE_NAME (mode));
802 /* Determine where the next incoming function argument will
803 appear. Normally, this works in exactly the same way as
804 picochip_function_arg, except when the function in question is a
805 varadic function. In this case, the incoming arguments all appear
806 to be passed on the stack (actually, some of the arguments are
807 passed in registers, which are then pushed onto the stack by the
808 function prologue). */
810 picochip_incoming_function_arg (CUMULATIVE_ARGS cum, int mode,
811 tree type, int named)
817 return picochip_function_arg (cum, mode, type, named);
821 /* Gives the alignment boundary, in bits, of an argument with the
824 picochip_get_function_arg_boundary (enum machine_mode mode)
829 align = STACK_BOUNDARY;
831 align = GET_MODE_ALIGNMENT (mode);
833 if (align < PARM_BOUNDARY)
834 align = PARM_BOUNDARY;
840 /* Compute partial registers. */
842 picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum, enum machine_mode mode,
843 tree type, bool named ATTRIBUTE_UNUSED)
845 int type_align_in_units = 0;
846 int type_size_in_units;
848 int offset_overflow = 0;
850 unsigned cum = *((unsigned *) p_cum);
852 /* VOIDmode is passed when computing the second argument to a `call'
853 pattern. This can be ignored. */
854 if (mode == VOIDmode)
857 /* Compute the alignment and size of the parameter. */
858 type_align_in_units =
859 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
860 type_size_in_units = picochip_compute_arg_size (type, mode);
862 /* Compute the correct offset (i.e., ensure that the offset meets
863 the alignment requirements). */
864 offset_overflow = cum % type_align_in_units;
865 if (offset_overflow == 0)
868 new_offset = (cum - offset_overflow) + type_align_in_units;
872 printf ("Partial function arg nregs:\n");
873 printf (" Type valid: %s\n", (type ? "yes" : "no"));
874 printf (" Cumulative Value: %d\n", cum);
875 printf (" Mode: %s\n", GET_MODE_NAME (mode));
876 printf (" Type size: %i units\n", type_size_in_units);
877 printf (" Alignment: %i units\n", type_align_in_units);
878 printf (" New offset: %i\n", new_offset);
882 /* If the new offset is outside the register space, return. */
883 if (new_offset >= (MAX_CALL_PARAMETER_REGS * 2))
886 /* If the end of the argument is outside the register space, then
887 the argument must overlap the register space. Return the number
888 of bytes which are passed in registers. */
889 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
890 return ((MAX_CALL_PARAMETER_REGS * 2) - new_offset);
896 /* Advance the cumulative args counter, returning the new counter. */
898 picochip_arg_advance (const CUMULATIVE_ARGS cum, int mode,
899 tree type, int named ATTRIBUTE_UNUSED)
901 int type_align_in_units = 0;
902 int type_size_in_units;
904 int offset_overflow = 0;
906 /* VOIDmode is passed when computing the second argument to a `call'
907 pattern. This can be ignored. */
908 if (mode == VOIDmode)
911 /* Compute the alignment and size of the parameter. */
912 type_align_in_units =
913 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
914 type_size_in_units = picochip_compute_arg_size (type, mode);
916 /* Compute the correct offset (i.e., ensure that the offset meets
917 the alignment requirements). */
918 offset_overflow = cum % type_align_in_units;
919 if (offset_overflow == 0)
922 new_offset = (cum - offset_overflow) + type_align_in_units;
924 /* Advance past the last argument. */
925 new_offset += type_size_in_units;
931 /* Determine whether a register needs saving/restoring. It does if it
932 is live in a function, and isn't a call-used register. */
934 picochip_reg_needs_saving (int reg_num)
936 return df_regs_ever_live_p(reg_num) && !call_used_regs[reg_num];
939 /* Compute and return offset of the main frame. */
941 picochip_frame_byte_offset (void)
943 gcc_assert(picochip_is_aligned
944 (crtl->outgoing_args_size, BITS_PER_WORD));
946 return crtl->outgoing_args_size;
949 /* Return the size of the main frame. */
951 picochip_frame_size_in_bytes (void)
953 int frame_size = get_frame_size();
954 int stack_align = STACK_BOUNDARY/BITS_PER_UNIT;
955 if (!picochip_is_aligned (frame_size, STACK_BOUNDARY))
956 frame_size = frame_size + (stack_align - frame_size%stack_align);
957 gcc_assert(picochip_is_aligned (frame_size, STACK_BOUNDARY));
961 /* Compute and return the size (in bytes) of the register save/restore
962 area for the current function. This only includes the general
963 purpose registers - the special purpose stack pointer and link
964 registers are not included in this area. */
966 picochip_save_area_size_in_bytes (void)
968 int num_regs_to_save = 0;
971 /* Read through all the registers, determining which need to be saved. */
972 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
974 if (picochip_reg_needs_saving (i))
975 num_regs_to_save += 1;
978 return num_regs_to_save * UNITS_PER_WORD;
982 /* Compute and return offset of the save area base. */
984 picochip_save_area_byte_offset (void)
986 int base_offset = (picochip_frame_byte_offset () +
987 picochip_frame_size_in_bytes ());
989 gcc_assert(picochip_is_aligned (base_offset, BITS_PER_WORD));
995 /* Compute and return offset of the special register save area. This
996 area can be found immediately above the normal save area. It must
997 be aligned, to allow the registers to be saved and restored as a
1000 picochip_special_save_area_byte_offset (void)
1002 int byte_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
1003 int offset = (picochip_save_area_byte_offset () +
1004 picochip_save_area_size_in_bytes ());
1006 if ((offset % byte_alignment) != 0)
1007 offset = ((offset / byte_alignment) + 1) * byte_alignment;
1013 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1015 picochip_can_eliminate_link_sp_save (void)
1017 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1018 changing during optimizations phases. So, this function returns different
1019 values when called from initial_elimination_offset and then again when it
1020 is called from prologue/epilogue generation. This means that argument
1021 accesses become wrong. This wouldnt happen only if we were not using the
1022 stack at all. The following conditions ensures that.*/
1024 return (current_function_is_leaf &&
1025 !df_regs_ever_live_p(LINK_REGNUM) &&
1026 !df_regs_ever_live_p(STACK_POINTER_REGNUM) &&
1027 (picochip_special_save_area_byte_offset() == 0) &&
1028 (crtl->args.size == 0) &&
1029 (crtl->args.pretend_args_size == 0));
1032 /* Compute the size of the special reg save area (SP and LNK). If the
1033 SP/LNK registers don't need to be saved, this area can shrink to
1036 picochip_special_save_area_size_in_bytes (void)
1040 if (picochip_can_eliminate_link_sp_save ())
1043 return 2 * UNITS_PER_WORD;
1046 /* Return the number of pretend arguments. If this function is
1047 varadic, all the incoming arguments are effectively passed on the
1048 stack. If this function has real pretend arguments (caused by a
1049 value being passed partially on the stack and partially in
1050 registers), then return the number of registers used. */
1052 picochip_pretend_arg_area_size (void)
1055 if (crtl->args.pretend_args_size != 0)
1057 gcc_assert(crtl->args.pretend_args_size % 4 == 0);
1059 return crtl->args.pretend_args_size;
1061 else if (cfun->stdarg)
1068 /* Compute and return the offset of the pretend arguments. The pretend
1069 arguments are contiguous with the incoming arguments, and must be
1070 correctly aligned. */
1072 picochip_pretend_arg_area_byte_offset (void)
1074 int base_offset = 0;
1076 base_offset = (picochip_special_save_area_byte_offset () +
1077 picochip_special_save_area_size_in_bytes ());
1079 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1080 gcc_assert(picochip_is_aligned
1081 (base_offset + picochip_pretend_arg_area_size (), STACK_BOUNDARY));
1087 /* Compute and return the offset of the incoming arguments. If a
1088 static chain is in use, this will be passed just before the other
1089 arguments. This means that the pretend argument mechanism, used in
1090 variadic functions, doesn't work properly. Thus, static chains work
1091 on their own, as do variadic functions, but not the combination of
1092 the two. This isn't really a problem. */
1094 picochip_arg_area_byte_offset (void)
1096 int base_offset = (picochip_pretend_arg_area_byte_offset () +
1097 picochip_pretend_arg_area_size ());
1099 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1100 the alignment on a 32-bit boundary must be maintained. */
1101 if (cfun->static_chain_decl != NULL)
1103 gcc_assert (!cfun->stdarg);
1107 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1114 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED, int mode)
1117 /* Special case - only one register needed. */
1118 if (GET_MODE_CLASS (mode) == MODE_CC)
1121 /* We actually do not allocate acc0 ever. But, it seems like we need to
1122 make it look like a allocatable register for the dataflow checks to work
1123 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1128 /* General case - compute how much space in terms of units. */
1129 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1134 picochip_class_max_nregs (int class, int mode)
1136 int size = ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1138 if (class == ACC_REGS)
1141 if (GET_MODE_CLASS (mode) == MODE_CC)
1148 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1149 argument pointer) by replacing it with a constant offset from the
1150 main stack register. */
1152 initial_elimination_offset (int from, int to)
1154 int offset_from_sp = 0;
1156 if (FRAME_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1157 offset_from_sp = picochip_frame_byte_offset ();
1158 else if (ARG_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1159 offset_from_sp = picochip_pretend_arg_area_byte_offset ();
1163 return offset_from_sp;
1167 /* Compute and return the size of the incoming argument area. */
1169 picochip_arg_area_size_in_bytes (void)
1171 return crtl->args.size;
1174 /* Determine whether the given register is valid. When the strict mode
1175 is used, only hard registers are valid, otherwise any register is
1178 picochip_legitimate_address_register (rtx x, unsigned strict)
1181 /* Sanity check - non-registers shouldn't make it here, but... */
1182 if (REG != GET_CODE (x))
1186 return REGNO (x) < FIRST_NONHARD_REGISTER;
1192 /* Determine whether the given constant is in the range required for
1193 the given base register. */
1195 picochip_const_ok_for_base (enum machine_mode mode, int regno, int offset,
1198 HOST_WIDE_INT corrected_offset;
1200 if (GET_MODE_SIZE (mode) != 0)
1202 if (GET_MODE_SIZE(mode) <= 4)
1204 /* We can allow incorrect offsets if strict is 0. If strict is 1,
1205 we are in reload and these memory accesses need to be changed. */
1206 if (offset % GET_MODE_SIZE (mode) != 0 && strict == 1)
1208 corrected_offset = offset / GET_MODE_SIZE (mode);
1212 /* We can allow incorrect offsets if strict is 0. If strict is 1,
1213 we are in reload and these memory accesses need to be changed. */
1214 if (offset % 4 != 0 && strict == 1)
1216 corrected_offset = offset / 4;
1221 /* Default to the byte offset as supplied. */
1222 corrected_offset = offset;
1225 /* The offset from the base register can be different depending upon
1226 the base register. The stack/frame/argument pointer offsets can
1227 all be greater than a simple register-based offset. Note that the
1228 frame/argument pointer registers are actually eliminations of the
1229 stack pointer, so a value which is valid for an offset to, for
1230 example, the frame pointer, might be invalid for the stack
1231 pointer once the elimination has occurred. However, there is no
1232 need to handle this special case here, as the stack offset is
1233 always checked after elimination anyway, and the generated code
1234 seems to have identical performance. */
1235 if (regno == STACK_POINTER_REGNUM ||
1236 regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1237 return picochip_const_ok_for_letter_p (corrected_offset, 'K');
1239 return picochip_const_ok_for_letter_p (corrected_offset, 'J');
1243 /* Determine whether a given rtx is a legitimate address for machine_mode
1244 MODE. STRICT is non-zero if we're being strict - any pseudo that
1245 is not a hard register must be a memory reference. */
1247 picochip_legitimate_address_p (int mode, rtx x, unsigned strict)
1251 switch (GET_CODE (x))
1254 valid = picochip_legitimate_address_register (x, strict);
1259 rtx base = XEXP (x, 0);
1260 rtx offset = XEXP (x, 1);
1262 valid = (REG == GET_CODE (base) &&
1263 REGNO_OK_FOR_BASE_P (REGNO(base)) &&
1264 picochip_legitimate_address_register (base, strict) &&
1265 CONST_INT == GET_CODE (offset) &&
1266 picochip_const_ok_for_base (mode, REGNO (base),
1267 INTVAL (offset),strict));
1272 /* The user can select whether a symbol can be used as a memory
1273 address. Typically, this will decrease execution time (no
1274 register load is required first), but will increase code size
1275 (because the symbol will be used several times, rather than
1276 loaded once into a register.*/
1277 valid = TARGET_SYMBOL_AS_ADDRESS;
1282 /* A constant memory address must be a (plus (symbol_ref)
1283 (const_int)), and is only allowed when the symbols are
1284 permitted addresses. */
1285 rtx inner = XEXP (x, 0);
1287 valid = (TARGET_SYMBOL_AS_ADDRESS &&
1288 PLUS == GET_CODE (inner) &&
1289 SYMBOL_REF == GET_CODE (XEXP (inner, 0)) &&
1290 CONST_INT == GET_CODE (XEXP (inner, 1)));
1304 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1306 picochip_symbol_offset (rtx operand)
1309 return (PLUS == GET_CODE (operand) &&
1310 SYMBOL_REF == GET_CODE (XEXP (operand, 0)) &&
1311 CONST_INT == GET_CODE (XEXP (operand, 1)));
1315 /* Assembly output. */
1317 /* The format here should match the format used in the output of
1318 symbol_ref's elsewhere in this file. */
1320 picochip_output_label (FILE * stream, const char name[])
1322 int is_cfi_label = (strncmp (name, "picoMark_LCFI", 13) == 0);
1324 /* If VLIW scheduling is in use, any Call Frame Information labels
1325 generated inside a packet must have their output deferred until
1326 the end of the packet. */
1327 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1328 is_cfi_label && picochip_vliw_continuation)
1330 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1332 internal_error ("LCFI labels have already been deferred.");
1334 strcpy (picochip_current_vliw_state.cfi_label_name[
1335 picochip_current_vliw_state.num_cfi_labels_deferred], name);
1336 picochip_current_vliw_state.num_cfi_labels_deferred++;
1340 assemble_name (stream, name);
1342 if (strncmp (name, "picoMark_", 9) == 0)
1343 fprintf (stream, "=\n");
1345 fprintf (stream, ":\n");
1351 /* The format here should match the format used in the output of
1352 symbol_ref's elsewhere in this file. */
1354 picochip_output_labelref (FILE * stream, const char name[])
1356 fprintf (stream, "_%s", name);
1360 picochip_weaken_label (FILE * stream, const char name[])
1362 fprintf (stream, ".weak ");
1363 assemble_name (stream, name);
1364 fprintf (stream, "\n");
1367 /* Return true if the given label (or label prefix) denotes a marker
1368 label which should be emitted in the form LABEL= */
1370 picochip_is_marker_prefix (const char *prefix)
1372 return (strcmp (prefix, "L") != 0 && strcmp (prefix, "LC") != 0
1373 && strcmp (prefix, "LP") != 0);
1377 picochip_output_internal_label (FILE * stream, const char *prefix,
1381 /* Emit different types of label, based upon their prefix. They
1382 are handled differently to allow the assembler to ensure that
1383 branch target labels are properly aligned, while other labels
1384 will only serve as code markers, not branch targets. Aligning
1385 labels unnecessarily can result in much code wastage. */
1386 if (picochip_is_marker_prefix (prefix))
1388 /* Special label marker. If it appears in the middle of a VLIW
1389 packet, defer it until the end of the packet. There has
1390 never been a need to handle more than one lm label at a time. */
1391 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1392 (strcmp (prefix, "LM")) == 0 && picochip_vliw_continuation)
1394 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1395 internal_error ("LM label has already been deferred.");
1397 sprintf (picochip_current_vliw_state.lm_label_name,
1398 "picoMark_%s%ld", prefix, num);
1403 fprintf (stream, "_picoMark_%s%ld=\n", prefix, num);
1410 fprintf (stream, "_%s%ld:\n", prefix, num);
1416 picochip_generate_internal_label (char *str, const char *prefix, long num)
1418 /* Two types of internal label can be generated: branch target
1419 labels and code marker labels. Branch target labels must always
1420 be aligned (since code will execute at these
1421 points). Differentiate between the two by prepending markers with
1422 a unique prefix, which can later be used in output_label to
1423 figure out which label syntax to use. */
1424 if (picochip_is_marker_prefix (prefix))
1425 sprintf (str, "picoMark_%s%ld", prefix, num);
1427 sprintf (str, "%s%ld", prefix, num);
1432 picochip_asm_output_anchor (rtx symbol)
1434 fprintf (asm_out_file, ".offsetData _%s, ",XSTR (symbol, 0));
1435 fprintf (asm_out_file, "+ " HOST_WIDE_INT_PRINT_DEC"\n",SYMBOL_REF_BLOCK_OFFSET(symbol));
1439 picochip_output_aligned_common (FILE * stream, const char *name,
1440 unsigned size, unsigned alignment)
1443 fprintf (stream, ".commonData ");
1444 assemble_name (stream, name);
1445 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1446 picochip_output_global (stream, name);
1451 picochip_output_aligned_local (FILE * stream, const char *name,
1452 unsigned size, unsigned alignment)
1455 fprintf (stream, ".commonData ");
1456 assemble_name (stream, name);
1457 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1462 picochip_output_global (FILE * stream, const char *name)
1464 fprintf (stream, ".global ");
1465 assemble_name (stream, name);
1466 fprintf (stream, "\n");
1469 /* Output an assembly language string. Output as a sequence of decimal
1470 numbers, followed by the literal string to make it obvious what the
1471 numbers represent. */
1473 picochip_output_ascii (FILE * file, const char *str, int length)
1477 fprintf (file, ".ascii ");
1479 for (i = 0; i < length; ++i)
1481 fprintf (file, "16#%hhx# ", (char) (str[i]));
1484 fprintf (file, " ; ");
1486 for (i = 0; i < length; ++i)
1493 fprintf (file, "\\n");
1496 fprintf (file, "\\t");
1499 fprintf (file, "\\0");
1502 fprintf (file, "%c", c);
1507 fprintf (file, "\n");
1511 /* Output the beginning of an ASM file. */
1513 picochip_asm_file_start (void)
1515 default_file_start ();
1517 fprintf (asm_out_file, "// picoChip ASM file\n");
1518 fprintf (asm_out_file, "//.file \"%s\"\n", main_input_filename);
1520 fprintf (asm_out_file, "// Has byte access: %s\n",
1521 (TARGET_HAS_BYTE_ACCESS ? "Yes" : "No"));
1523 if (TARGET_HAS_MUL_UNIT)
1524 fprintf (asm_out_file, "// Has multiply: Yes (Multiply unit)\n");
1525 else if (TARGET_HAS_MAC_UNIT)
1526 fprintf (asm_out_file, "// Has multiply: Yes (Mac unit)\n");
1528 fprintf (asm_out_file, "// Has multiply: No\n");
1530 /* Variable tracking should be run after all optimizations which change order
1531 of insns. It also needs a valid CFG. This can't be done in
1532 picochip_override_options, because flag_var_tracking is finalized after
1534 picochip_flag_var_tracking = flag_var_tracking;
1535 flag_var_tracking = 0;
1538 /* Output the end of an ASM file. */
1540 picochip_asm_file_end (void)
1542 /* Include a segment end to make it easy for PERL scripts to grab
1543 segments. This is now done by assembler*/
1545 fprintf (asm_out_file, "// End of picoChip ASM file\n");
1549 /* Output frame debug information to the given stream. */
1551 picochip_output_frame_debug (FILE * file)
1555 if (current_function_is_leaf)
1556 fprintf (file, "\t\t// Leaf function\n");
1558 fprintf (file, "\t\t// Non-leaf function\n");
1560 if (picochip_can_eliminate_link_sp_save ())
1561 fprintf (file, "\t\t// Link/fp save/restore can be eliminated\n");
1563 if (cfun->static_chain_decl != NULL)
1564 fprintf (file, "\t\t// Static chain in use\n");
1566 fprintf (file, "\t\t// Incoming argument size: %d bytes\n",
1567 picochip_arg_area_size_in_bytes ());
1568 fprintf (file, "\t\t// Incoming arg offset: %d\n",
1569 picochip_arg_area_byte_offset ());
1570 fprintf (file, "\t\t// Pretend arg size: %d\n",
1571 picochip_pretend_arg_area_size ());
1572 fprintf (file, "\t\t// Pretend arg offset (ARGP): %d\n",
1573 picochip_pretend_arg_area_byte_offset ());
1574 fprintf (file, "\t\t// Special reg area size: %d bytes\n",
1575 picochip_special_save_area_size_in_bytes ());
1576 fprintf (file, "\t\t// Special reg area offset: %d\n",
1577 picochip_special_save_area_byte_offset ());
1579 /* Output which registers are saved. */
1580 fprintf (file, "\t\t// Saved regs: ");
1581 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1583 if (picochip_reg_needs_saving (i))
1584 fprintf (file, "%s ", picochip_regnames[i]);
1586 fprintf (file, "\t\t\n");
1588 fprintf (file, "\t\t// Save area size: %d bytes\n",
1589 picochip_save_area_size_in_bytes ());
1590 fprintf (file, "\t\t// Save area offset: %d\n",
1591 picochip_save_area_byte_offset ());
1593 fprintf (file, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1594 fprintf (file, "\t\t// Frame offset (FP): %d\n",
1595 picochip_frame_byte_offset ());
1597 fprintf (file, "\t\t// Outgoing argument area size: %d bytes\n",
1598 crtl->outgoing_args_size);
1602 /* Output picoChip function prologue. This contains human-readable
1603 information about the function. */
1605 picochip_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1607 /* Get the function's name, as described by its RTL. This may be
1608 different from the DECL_NAME name used in the source file. The
1609 real declaration name must be used, to ensure that the prologue
1610 emits the right information for the linker. */
1613 x = DECL_RTL (current_function_decl);
1614 gcc_assert (MEM_P (x));
1616 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1617 fnname = XSTR (x, 0);
1619 /* Note that the name of the function is given in the &_%s
1620 form. This matches the name of the function as used in labels,
1621 and function calls, and enables processCallGraph to match
1622 function calls to the name of the function, as defined here. */
1623 fprintf (file, "// picoChip Function Prologue : &_%s = %d bytes\n",
1624 fnname, picochip_arg_area_byte_offset ());
1626 picochip_output_frame_debug (file);
1627 fprintf (file, "\n");
1631 /* Output picoChip function epilogue. */
1633 picochip_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1638 x = DECL_RTL (current_function_decl);
1639 gcc_assert (MEM_P (x));
1641 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1642 fnname = XSTR (x, 0);
1643 fprintf (file, "\n// picoChip Function Epilogue : %s\n\n",
1647 /* Manipulate the asm output. Some machines only execute the code when
1648 there is actually a chance of needing it (e.g., FRV doesn't execute
1649 it if the scheduling pass wasn't used). We always execute it,
1650 simple to ensure that it is exercised more often, and bugs are more
1653 This function's prime reason for existence is to insert the VLIW
1654 separators where appropriate. The separators must be inserted
1655 before any comments which appear at the end of the file.
1659 picochip_asm_output_opcode (FILE * f, const char *ptr)
1663 /* Flag to specify when a VLIW continuation has been inserted onto
1664 the line. Continuations are either inserted before any comments,
1665 or before the end of the line is reached. The flag ensures that
1666 we don't insert continuations twice (i.e., at the comment and the
1668 int continuation_inserted = 0;
1670 /* If the instruction uses multiple lines (i.e., a new line
1671 character appears in the opcode), then ensure that no attempt is
1672 made to pack it into a VLIW. */
1673 if (strchr (ptr, '\n') != NULL && picochip_vliw_continuation)
1675 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1679 /* If a delay slot is pending, output the directive to the assembler
1680 before the instruction. */
1681 if (picochip_is_delay_slot_pending)
1683 picochip_is_delay_slot_pending = 0;
1687 /* Keep going for entire opcode. All substitution performed ourselves. */
1692 /* Determine whether a VLIW continuation must be inserted before
1693 any comments, or the end of the opcode. A flag is set to show
1694 that we have inserted a continuation on this line, so that we
1695 don't try to insert another continuation when the end of the
1696 opcode is reached. The only other case for a continuation
1697 might have been a newline, but these aren't allowed in
1698 conjunction with VLIW continuations (see above code). */
1699 if (picochip_vliw_continuation &&
1700 !continuation_inserted &&
1701 ((c == '/' && (*ptr == '/')) || *ptr == '\0'))
1704 continuation_inserted = 1;
1707 /* Detect an explicit VLIW separator. */
1708 if (c == '%' && (*ptr == '|'))
1713 /* Detect the need for an ALU id operand. */
1714 else if (c == '%' && (*ptr == '#'))
1716 fputc (picochip_get_vliw_alu_id (), f);
1719 printf ("Generated ALU char at %s for insn %d\n", ptr,
1720 INSN_UID (picochip_current_prescan_insn));
1722 /* Skip past unwanted # */
1725 /* Detect the need for branch delay slot. */
1726 else if (c == '%' && (*ptr == '>'))
1728 /* Only emit delay slots (NOP's, or otherwise) when delay
1729 * slot scheduling has actually been enabled, otherwise VLIW
1730 * scheduling and delay slot scheduling output combine to
1731 * produce nasty effects. */
1732 if (flag_delayed_branch)
1734 if (dbr_sequence_length () == 0)
1735 fputs ("\n=->\tNOP", f);
1737 picochip_is_delay_slot_pending = 1;
1740 /* Skip past unwanted > */
1743 /* Detect any %digit specifiers. */
1744 else if (c == '%' && (*ptr >= '0' && *ptr <= '9'))
1747 picochip_print_operand (f, recog_data.operand[c], 0);
1748 while ((c = *ptr) >= '0' && c <= '9')
1751 /* Detect any %letterdigit specifiers. */
1752 else if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
1753 || (*ptr >= 'A' && *ptr <= 'Z')))
1755 int letter = *ptr++;
1762 output_asm_label (recog_data.operand[c]);
1766 output_address (recog_data.operand[c]);
1770 picochip_print_operand (f, recog_data.operand[c], letter);
1773 while ((c = *ptr) >= '0' && c <= '9')
1778 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
1784 /* Reached the end of the packet. If any labels were deferred
1785 during output, emit them now. */
1786 if (!picochip_vliw_continuation)
1788 if (picochip_current_vliw_state.num_cfi_labels_deferred != 0)
1791 assemble_name (f, picochip_current_vliw_state.cfi_label_name[0]);
1793 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1796 assemble_name (f, picochip_current_vliw_state.cfi_label_name[1]);
1801 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1804 assemble_name (f, picochip_current_vliw_state.lm_label_name);
1809 /* Output an end-of-packet marker if requested. */
1810 if (!picochip_vliw_continuation &&
1811 TARGET_DEBUG && picochip_schedule_type == DFA_TYPE_SPEED)
1812 fprintf (f, "\n\t//-------------- End of VLIW packet -----------------");
1817 /* Function RTL expansion. */
1819 /* Expand the prologue into RTL. */
1821 picochip_expand_prologue (void)
1823 int stack_adjustment = 0;
1824 int special_save_offset = 0;
1825 int general_save_offset = 0;
1826 int reg_save_offset = 0;
1829 stack_adjustment = picochip_arg_area_byte_offset ();
1830 general_save_offset =
1831 -(stack_adjustment - picochip_save_area_byte_offset ());
1832 special_save_offset =
1833 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1835 /* Save the link registers. We could try to save just one register
1836 here. This would reduce the amount of stack space required.
1837 There hasnt been a good reason to do that so far. */
1838 if (!picochip_can_eliminate_link_sp_save ())
1839 picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
1840 special_save_offset);
1842 /* Save callee-save registers. */
1843 reg_save_offset = 0;
1844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1846 if (picochip_reg_needs_saving (i))
1849 /* If this register is an even numbered register, and the
1850 next register also needs to be saved, use a SImode save,
1851 which does both in one instruction. Note that a special
1852 check is performed to ensure that the double word aligned
1853 store is valid (e.g., it is possible that r6, r8, r9 need
1854 to be saved, in which case once r6 has been saved, the
1855 stored offset is no longer aligned, and an STL/LDL
1856 instruction becomes invalid). Alternately, we could store all
1857 aligned registers first and then save the single one(s). */
1859 picochip_reg_needs_saving (i + 1) &&
1860 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1862 picochip_emit_save_register (gen_rtx_REG (SImode, i),
1863 general_save_offset +
1865 reg_save_offset += 2 * UNITS_PER_WORD;
1870 picochip_emit_save_register (gen_rtx_REG (HImode, i),
1871 general_save_offset +
1873 reg_save_offset += UNITS_PER_WORD;
1879 /* Emit a stack adjustment where required. */
1880 if (stack_adjustment != 0)
1881 picochip_emit_stack_allocate (stack_adjustment);
1883 /* If this function uses varadic arguments, write any unnamed
1884 registers to the stack. */
1887 int stdarg_offset = picochip_pretend_arg_area_byte_offset ();
1889 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
1890 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
1892 picochip_emit_save_register (gen_rtx_REG (SImode, 0), stdarg_offset);
1893 picochip_emit_save_register (gen_rtx_REG (SImode, 2),
1895 picochip_emit_save_register (gen_rtx_REG (SImode, 4),
1902 /* Expand the epilogue into RTL. */
1904 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED)
1906 int stack_adjustment = 0;
1907 int special_save_offset = 0;
1908 int general_save_offset = 0;
1909 int reg_save_offset = 0;
1911 int use_link_fp_restore_stack_adjust = 0; /* Default to using an explicit
1914 stack_adjustment = picochip_arg_area_byte_offset ();
1915 general_save_offset =
1916 -(stack_adjustment - picochip_save_area_byte_offset ());
1917 special_save_offset =
1918 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1920 /* Emit a stack adjustment where required. */
1921 if (stack_adjustment != 0)
1923 /* If the link/fp is already being restored, and the offset to
1924 their save location is small enough, don't bother adjusting
1925 the stack explicitly. */
1926 if (picochip_special_save_area_byte_offset () < 512 &&
1927 !picochip_can_eliminate_link_sp_save ())
1928 use_link_fp_restore_stack_adjust = 1;
1930 /* Explicitly restore the stack. */
1931 picochip_emit_stack_allocate (-stack_adjustment);
1934 /* Restore the Link/FP registers. Only save the link register? */
1935 if (!picochip_can_eliminate_link_sp_save ())
1937 if (use_link_fp_restore_stack_adjust)
1938 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1939 picochip_special_save_area_byte_offset
1942 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1943 special_save_offset);
1946 /* Restore callee-save registers. */
1947 reg_save_offset = 0;
1948 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1950 if (picochip_reg_needs_saving (i))
1953 /* If this register is an even numbered register, and the
1954 next register also needs to be saved, use a SImode save,
1955 which does both in one instruction. Note that a special
1956 check is performed to ensure that the double word aligned
1957 store is valid (e.g., it is possible that r6, r8, r9 need
1958 to be saved, in which case once r6 has been saved, the
1959 stored offset is no longer aligned, and an STL/LDL
1960 instruction becomes invalid). We could store all aligned
1961 registers first, and then save the single one(s). */
1963 picochip_reg_needs_saving (i + 1) &&
1964 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1966 picochip_emit_restore_register (gen_rtx_REG (SImode, i),
1967 general_save_offset +
1969 reg_save_offset += 2 * UNITS_PER_WORD;
1974 picochip_emit_restore_register (gen_rtx_REG (HImode, i),
1975 general_save_offset +
1977 reg_save_offset += UNITS_PER_WORD;
1983 /* Emit a return instruction, which matches a (parallel
1984 [(return) (use r12)]) */
1987 p = rtvec_alloc (2);
1989 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
1990 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
1991 gen_rtx_REG (Pmode, LINK_REGNUM));
1992 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
1997 /* Assembly instruction output. */
1999 /* Test whether the given branch instruction is short, or long. Short
2000 * branches are equivalent to real branches, and may be DFA
2001 * scheduled. Long branches expand to a macro which is handled by the
2002 * elaborator, and cannot be scheduled. Occasionally, the branch
2003 * shortening pass, which is run after DFA scheduling, will change the
2004 * code layout and cause the short branch to be reverted into a long
2005 * branch. Instead of having to fix this up by emitting new assembly,
2006 * the short branch is emitted anyway. There is plenty of slack in the
2007 * calculation of long and short branches (10-bit offset, but only
2008 * 9-bits used in computation), so there is enough slack for this to
2011 picochip_is_short_branch (rtx insn)
2013 int isRealShortBranch = (get_attr_length(insn) == SHORT_BRANCH_LENGTH);
2015 return (isRealShortBranch ||
2016 (!isRealShortBranch &&
2017 picochip_current_vliw_state.num_insns_in_packet > 1));
2020 /* Output a compare-and-branch instruction (matching the cbranch
2023 picochip_output_cbranch (rtx operands[])
2026 if (HImode != GET_MODE (operands[1]) ||
2027 (HImode != GET_MODE (operands[2]) &&
2028 GET_CODE (operands[2]) != CONST_INT))
2030 internal_error ("%s: At least one operand can't be handled",
2034 /* Use the type of comparison to output the appropriate condition
2036 switch (GET_CODE (operands[0]))
2039 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2042 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2045 /* Reverse the operand order to be GE */
2046 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2049 /* Reverse operand order of GEU. */
2050 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2053 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2056 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2059 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2062 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2065 /* Reversed operand version of LT. */
2066 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2069 /* Reverse an LTU. */
2070 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2077 /* Output a compare-and-branch instruction (matching the cbranch
2078 pattern). This function is current unused since the cbranch
2079 split is disabled. The function is kept around so we can use
2080 it when we understand how to do cbranch split safely. */
2082 picochip_output_compare (rtx operands[])
2085 if (HImode != GET_MODE (operands[1]) ||
2086 (HImode != GET_MODE (operands[2]) &&
2087 GET_CODE (operands[2]) != CONST_INT))
2089 internal_error ("%s: At least one operand can't be handled",
2093 /* Use the type of comparison to output the appropriate condition
2095 int code = GET_CODE (operands[0]);
2099 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2102 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2105 /* Reverse the operand order to be GE */
2106 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2109 /* Reverse operand order of GEU. */
2110 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2113 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2116 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2119 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2122 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2125 /* Reversed operand version of LT. */
2126 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2129 /* Reverse an LTU. */
2130 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2137 /* Output the branch insn part of a compare-and-branch split. */
2139 picochip_output_branch (rtx operands[], rtx insn)
2142 int code = GET_CODE(operands[2]);
2143 if (picochip_is_short_branch (insn))
2145 /* Short branches can be output directly using the
2146 appropriate instruction. */
2150 return ("BNE %l0 %>");
2152 return ("BEQ %l0 %>");
2154 return ("BGE %l0 %>");
2156 return ("BHS %l0 %>");
2158 return ("BGE %l0 %>");
2160 return ("BHS %l0 %>");
2162 return ("BLT %l0 %>");
2164 return ("BLO %l0 %>");
2166 return ("BLT %l0 %>");
2168 return ("BLO %l0 %>");
2170 internal_error ("Unknown short branch in %s (type %d)\n",
2171 __FUNCTION__, (int) INTVAL (operands[1]));
2172 return "UNKNOWN_BRANCH";
2177 /* Long branches result in the emission of a special
2178 instruction, which the assembler expands into a suitable long
2181 /* Use the type of comparison to output the appropriate condition
2186 return ("JMPNE %l0 %>");
2188 return ("JMPEQ %l0 %>");
2190 return ("JMPGE %l0 %>");
2192 return ("JMPHS %l0 %>");
2194 return ("JMPGE %l0 %>");
2196 return ("JMPHS %l0 %>");
2198 return ("JMPLT %l0 %>");
2200 return ("JMPLO %l0 %>");
2202 return ("JMPLT %l0 %>");
2204 return ("JMPLO %l0 %>");
2207 internal_error ("Unknown long branch in %s (type %d)\n",
2208 __FUNCTION__, (int) INTVAL (operands[1]));
2209 return "UNKNOWN_BRANCH";
2215 /* Output a jump instruction. */
2217 picochip_output_jump (rtx insn)
2219 if (picochip_is_short_branch (insn))
2222 return "JMPRA %l0%>";
2226 picochip_output_put_array (int alternative, rtx operands[])
2228 /* Local output buffer. */
2231 int portArraySize = INTVAL(operands[1]);
2232 int portBaseIndex = INTVAL(operands[2]);
2234 if (alternative == 0)
2236 sprintf (buf, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2237 portArraySize, portBaseIndex);
2238 output_asm_insn (buf, operands);
2240 else if (alternative == 1)
2242 /* Constant port id. Emit a real instruction. */
2243 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2244 if (portIndex < portBaseIndex ||
2245 portIndex >= (portBaseIndex + portArraySize))
2247 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2248 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2250 sprintf(buf, "PUT R[0:1],%d", portIndex);
2251 output_asm_insn (buf, operands);
2256 /* Both alternatives output the insn directly. */
2260 const char *picochip_output_get_array (int alternative, rtx operands[])
2262 /* Local output buffer. */
2265 int portArraySize = INTVAL(operands[1]);
2266 int portBaseIndex = INTVAL(operands[2]);
2268 if (alternative == 0)
2270 sprintf (buf, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2271 portArraySize, portBaseIndex);
2272 output_asm_insn (buf, operands);
2274 else if (alternative == 1)
2276 /* Constant port id. Emit a real instruction. */
2277 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2278 if (portIndex < portBaseIndex ||
2279 portIndex >= (portBaseIndex + portArraySize))
2281 error ("GET uses port array index %d, which is out of range [%d..%d)",
2282 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2284 sprintf(buf, "GET %d,R[0:1]", portIndex);
2285 output_asm_insn (buf, operands);
2290 /* Both alternatives output the insn directly. */
2294 const char *picochip_output_testport_array (int alternative, rtx operands[])
2296 /* Local output buffer. */
2299 int portArraySize = INTVAL(operands[2]);
2300 int portBaseIndex = INTVAL(operands[3]);
2302 if (alternative == 0)
2304 sprintf (buf, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2305 portArraySize, portBaseIndex);
2306 output_asm_insn (buf, operands);
2308 else if (alternative == 1)
2310 /* Constant port id. Emit a real instruction. */
2311 int portIndex = INTVAL(operands[1]) + portBaseIndex;
2312 if (portIndex < portBaseIndex ||
2313 portIndex >= (portBaseIndex + portArraySize))
2315 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2316 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2318 sprintf(buf, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex);
2319 output_asm_insn (buf, operands);
2324 /* Both alternatives output the insn directly. */
2328 /* Output a comparison operand as a symbol (e.g., >). */
2330 picochip_print_comparison (FILE * file, rtx operand, int letter)
2335 /* Output just the comparison symbol. */
2336 switch (GET_CODE (operand))
2339 fprintf (file, "!=");
2342 fprintf (file, "==");
2345 fprintf (file, ">=");
2348 fprintf (file, ">={U}");
2351 fprintf (file, "<");
2354 fprintf (file, "<{U}");
2357 fprintf (file, "<=");
2360 fprintf (file, "<={U}");
2363 fprintf (file, ">");
2366 fprintf (file, ">{U}");
2374 /* Output the comparison formatted as operand,symbol,operand */
2375 rtx op0 = XEXP (operand, 0);
2376 rtx op1 = XEXP (operand, 1);
2378 picochip_print_operand (file, op0, 0);
2379 picochip_print_comparison (file, operand, 'i');
2380 picochip_print_operand (file, op1, 0);
2384 /* This function generates a memory address operand in the given
2385 mode. That is, if the address contains a constant offset, then the
2386 offset is divided by the required mode size to compute the
2387 mode specific offset. By default, picochip_print_operand_address calls
2388 this function using the natural mode of the operand, but special
2389 operand codes can be used to invoke the computation using an
2390 unnatural mode (e.g., compute the HI aligned address of an SI mode
2393 picochip_print_memory_address (FILE * file, rtx operand,
2394 enum machine_mode mode)
2396 rtx address = XEXP (operand, 0);
2399 if (MEM != GET_CODE (operand))
2400 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2405 printf ("picochip_print_memory_address: ");
2406 print_rtl (stdout, operand);
2410 switch (GET_CODE (address))
2414 /* Grab the address components. */
2415 rtx base = XEXP (address, 0);
2416 rtx offset = XEXP (address, 1);
2418 /* Only handle reg+const addresses */
2419 if (REG == GET_CODE (base) && CONST_INT == GET_CODE (offset))
2421 /* Sanity check. If an FP+offset address is given, ensure
2422 that the offset lies within the given frame, or a lower
2424 if (REGNO (base) == STACK_POINTER_REGNUM )
2425 gcc_assert (INTVAL (offset) <= (picochip_arg_area_byte_offset () +
2428 /* Print the base register - identical for all modes. */
2429 fprintf (file, "(");
2430 picochip_print_operand (file, base, 'r');
2431 fprintf (file, ")");
2433 /* Print the constant offset with compensation for the mode. */
2437 picochip_print_operand (file, offset, 'Q');
2441 picochip_print_operand (file, offset, 'H');
2446 picochip_print_operand (file, offset, 'S');
2450 picochip_print_operand (file, offset, 'D');
2464 picochip_print_operand (file, address, 's');
2473 inner = XEXP (address, 0);
2475 /* Sanity check - the CONST memory address must be a base+offset. */
2476 gcc_assert (PLUS == GET_CODE (inner));
2478 base = XEXP (inner, 0);
2479 offset = XEXP (inner, 1);
2481 fprintf (file, "&_%s%+d", XSTR (base, 0), XINT (offset, 0));
2487 /* Register operand. Provide a zero offset. */
2488 fprintf (file, "(");
2489 picochip_print_operand (file, address, 'r');
2490 fprintf (file, ")0");
2499 /* Output an operand. Formatting letters allow particular parts of
2500 the operand to be output. */
2502 picochip_print_operand (FILE * file, rtx operand, int letter)
2505 /* Handle special cases. */
2508 /* VLIW continuation, for explicit VLIW sequences. */
2510 fprintf (file, "\\");
2515 fputc (picochip_get_vliw_alu_id (), file);
2518 /* Delay slot specifier. */
2520 /* This should be handled in asm_output_opcode. */
2523 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2525 switch (GET_CODE (operand))
2528 fprintf (file, "AND");
2531 fprintf (file, "OR");
2534 fprintf (file, "XOR");
2537 fprintf (file, "ADD");
2540 fprintf (file, "SUB");
2547 /* Symbolic instructions (e.g., lshift becomes <<). */
2549 switch (GET_CODE (operand))
2552 fprintf (file, "&");
2555 fprintf (file, "|");
2558 fprintf (file, "^");
2561 fprintf (file, "+");
2564 fprintf (file, "-");
2567 fprintf (file, "UNKNOWN_INSN");
2572 default: /* Not a punctuation character - process as normal. */
2576 switch (GET_CODE (operand))
2582 /* Write a range of registers. */
2583 fprintf (file, "R[%d:%d]", REGNO (operand) + 1, REGNO (operand));
2587 /* The upper register of a pair is requested. */
2588 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 1]);
2592 /* The lower register of a pair is requested. Equivalent to the
2593 default, but included for completeness. */
2594 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2598 /* The 3rd register of a DI mode register. */
2599 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 2]);
2603 /* The 4th register of a DI mode register. */
2604 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 3]);
2608 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2613 /* A range of letters can be used to format integers. The
2614 letters Q/H/S are used to divide the constant by the width of
2615 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2616 to obtain the upper and lower 16-bits of a 32-bit
2617 constant. Where possible, signed numbers are used, since
2618 signed representations of numbers may be more compact (e.g.,
2619 65535 can be represented as -1, which fits into a small
2620 constant, whereas 65535 requires a large constant). */
2624 fprintf (file, "%ld", INTVAL (operand));
2628 fprintf (file, "%ld", INTVAL (operand) / 2);
2632 fprintf (file, "%ld", INTVAL (operand) / 4);
2636 fprintf (file, "%d", exact_log2 (INTVAL(operand)));
2640 fprintf (file, "%hi", (short) ((INTVAL (operand) >> 16) & 0xFFFF));
2644 fprintf (file, "%hi", (short) (INTVAL (operand) & 0xFFFF));
2648 fprintf (file, "%ld", INTVAL (operand));
2658 if (GET_MODE (operand) != SFmode)
2659 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2661 REAL_VALUE_FROM_CONST_DOUBLE (rv, operand);
2662 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
2667 fprintf (file, "%hi", (short) ((val >> 16) & 0xFFFF));
2671 fprintf (file, "%hi", (short) (val & 0xFFFF));
2679 /* Output a symbol. The output format must match that of
2680 picochip_output_label. */
2682 /* Ensure that the symbol is marked as referenced. Gcc can
2683 occasionally omit the function bodies when it believes them
2684 to be unreferenced. */
2685 if (SYMBOL_REF_DECL (operand))
2686 mark_decl_referenced (SYMBOL_REF_DECL (operand));
2687 fprintf (file, "&");
2688 assemble_name (file, XSTR (operand, 0));
2692 /* This format must match that of picochip_output_label. */
2693 fprintf (file, "&");
2694 output_asm_label (operand);
2699 rtx addr = XEXP (operand, 0);
2704 if (PLUS != GET_CODE (addr))
2705 fatal_insn ("Bad address, not (reg+disp):", addr);
2707 picochip_print_operand (file, XEXP (addr, 1), 0);
2711 /* Output a memory address in byte mode notation (i.e., the
2712 constant address (if any) is the actual byte address. */
2713 picochip_print_memory_address (file, operand, QImode);
2716 /* Output a constant offset of the given mode (i.e., divide
2717 the constant by the number of units in the mode to get the
2720 picochip_print_memory_address (file, operand, QImode);
2724 picochip_print_memory_address (file, operand, HImode);
2728 picochip_print_memory_address (file, operand, SImode);
2732 picochip_print_memory_address (file, operand, SFmode);
2736 if (PLUS != GET_CODE (addr))
2737 fatal_insn ("Bad address, not (reg+disp):", addr);
2739 picochip_print_operand (file, XEXP (addr, 0), 0);
2742 /* When the mem operand is (reg + big offset) which cannot
2743 be represented in an instruction as operand, the compiler
2744 automatically generates the instruction to put in (reg +
2745 big offset) into another register. In such cases, it
2746 returns '0' as the character. This needs to be handled
2750 if (REG != GET_CODE (addr))
2751 fatal_insn ("Bad address, not register:", addr);
2753 picochip_print_operand (file, addr, 0);
2757 fprintf (file, "Unknown mem operand - letter %c ",
2759 print_rtl (file, operand);
2767 rtx const_exp = XEXP (operand, 0);
2769 /* Handle constant offsets to symbol references. */
2770 if (PLUS == GET_CODE (const_exp) &&
2771 SYMBOL_REF == GET_CODE (XEXP (const_exp, 0)) &&
2772 CONST_INT == GET_CODE (XEXP (const_exp, 1)))
2775 picochip_print_operand (file, XEXP (const_exp, 0), 0);
2776 if (INTVAL (XEXP (const_exp, 1)) >= 0)
2777 fprintf (file, "+");
2778 /* else use the - from the operand (i.e., AP-2)) */
2780 picochip_print_operand (file, XEXP (const_exp, 1), letter);
2789 /* PLUS expressions are of the form (base + offset). Different
2790 options (analagous to those of memory PLUS expressions) are used
2791 to extract the base and offset components. */
2796 picochip_print_operand (file, XEXP (operand, 0), 0);
2800 picochip_print_operand (file, XEXP (operand, 1), 0);
2805 /* If the expression is composed entirely of constants,
2806 evaluate the result. This should only occur with the
2807 picoChip specific comms instructions, which are emitted as
2808 base+offset expressions. */
2809 if (CONST_INT == GET_CODE (XEXP (operand, 0)) &&
2810 CONST_INT == GET_CODE (XEXP (operand, 1)))
2812 HOST_WIDE_INT result = (XINT (XEXP (operand, 0), 0) +
2813 XINT (XEXP (operand, 1), 0));
2814 fprintf (file, "%ld", result);
2818 fprintf (file, "(");
2819 picochip_print_operand (file, XEXP (operand, 0), 0);
2820 fprintf (file, "+");
2821 picochip_print_operand (file, XEXP (operand, 1), 0);
2822 fprintf (file, ")");
2829 /* Comparison operations. */
2840 picochip_print_comparison (file, operand, letter);
2844 fprintf (stderr, "Unknown operand encountered in %s\n", __FUNCTION__);
2845 print_rtl (file, operand);
2852 /* Output an operand address */
2854 picochip_print_operand_address (FILE * file, rtx operand)
2857 switch (GET_CODE (operand))
2861 /* This format must match that of picochip_output_label. */
2862 assemble_name (file, XSTR (operand, 0));
2866 /* Note this format must match that of picochip_output_label. */
2867 fprintf (file, "_L%d", XINT (operand, 5));
2871 /* Pass on to a specialised memory address generator. */
2872 picochip_print_memory_address (file, operand, GET_MODE (operand));
2883 /* Scheduling functions. */
2885 /* Save some of the contents of recog_data. */
2887 picochip_save_recog_data (void)
2889 picochip_saved_which_alternative = which_alternative;
2890 memcpy (&picochip_saved_recog_data, &recog_data,
2891 sizeof (struct recog_data));
2894 /* Restore some of the contents of global variable recog_data. */
2896 picochip_restore_recog_data (void)
2898 which_alternative = picochip_saved_which_alternative;
2899 memcpy (&recog_data, &picochip_saved_recog_data,
2900 sizeof (struct recog_data));
2903 /* Ensure that no var tracking notes are emitted in the middle of a
2904 three-instruction bundle. */
2906 reorder_var_tracking_notes (void)
2912 rtx queue = NULL_RTX;
2914 for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
2916 next = NEXT_INSN (insn);
2920 /* Emit queued up notes before the first instruction of a bundle. */
2921 if (GET_MODE (insn) == TImode)
2925 rtx next_queue = PREV_INSN (queue);
2926 NEXT_INSN (PREV_INSN(insn)) = queue;
2927 PREV_INSN (queue) = PREV_INSN(insn);
2928 PREV_INSN (insn) = queue;
2929 NEXT_INSN (queue) = insn;
2934 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
2936 rtx prev = PREV_INSN (insn);
2937 PREV_INSN (next) = prev;
2938 NEXT_INSN (prev) = next;
2939 PREV_INSN (insn) = queue;
2946 /* Perform machine dependent operations on the rtl chain INSNS. */
2948 picochip_reorg (void)
2950 rtx insn, insn1, vliw_start;
2951 int vliw_insn_location = 0;
2953 /* We are freeing block_for_insn in the toplev to keep compatibility
2954 with old MDEP_REORGS that are not CFG based. Recompute it now. */
2955 compute_bb_for_insn ();
2960 if (picochip_schedule_type != DFA_TYPE_NONE)
2962 timevar_push (TV_SCHED2);
2964 /* Process the instruction list, computing the sizes of each
2965 instruction, and consequently branch distances. This can
2966 result in some branches becoming short enough to be treated
2967 as a real branch instruction, rather than an assembly branch
2968 macro which may expand into multiple instructions. The
2969 benefit of shortening branches is that real branch
2970 instructions can be properly DFA scheduled, whereas macro
2972 shorten_branches (get_insns ());
2974 /* Do control and data sched analysis again,
2975 and write some more of the results to dump file. */
2981 timevar_pop (TV_SCHED2);
2985 if (picochip_schedule_type == DFA_TYPE_SPEED)
2987 /* Whenever a VLIW packet is generated, all instructions in
2988 that packet must appear to come from the same source
2989 location. The following code finds all the VLIW packets,
2990 and tags their instructions with the location of the first
2991 instruction from the packet. Clearly this will result in
2992 strange behaviour when debugging the code, but since
2993 debugging and optimisation are being used in conjunction,
2994 strange behaviour is certain to occur anyway. */
2995 /* Slight bit of change. If the vliw set contains a branch
2996 or call instruction, we pick its location.*/
2997 for (insn = get_insns (); insn; insn = next_insn (insn))
3000 /* If this is the first instruction in the VLIW packet,
3001 extract its location. */
3002 if (GET_MODE (insn) == TImode)
3005 vliw_insn_location = INSN_LOCATOR (insn);
3007 if (JUMP_P (insn) || CALL_P(insn))
3009 vliw_insn_location = INSN_LOCATOR (insn);
3010 for (insn1 = vliw_start; insn1 != insn ; insn1 = next_insn (insn1))
3011 INSN_LOCATOR (insn1) = vliw_insn_location;
3013 /* Tag subsequent instructions with the same location. */
3015 INSN_LOCATOR (insn) = vliw_insn_location;
3021 /* Locate the note marking the end of the function's prologue. If
3022 the note appears in the middle of a VLIW packet, move the note to
3023 the end. This avoids unpleasant consequences such as trying to
3024 emit prologue markers (e.g., .loc/.file directives) in the middle
3026 if (picochip_schedule_type == DFA_TYPE_SPEED)
3028 rtx prologue_end_note = NULL;
3029 rtx last_insn_in_packet = NULL;
3031 for (insn = get_insns (); insn; insn = next_insn (insn))
3033 /* The prologue end must be moved to the end of the VLIW packet. */
3034 if (NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
3036 prologue_end_note = insn;
3041 /* Find the last instruction in this packet. */
3042 for (insn = prologue_end_note; insn; insn = next_real_insn (insn))
3044 if (GET_MODE (insn) == TImode)
3047 last_insn_in_packet = insn;
3050 if (last_insn_in_packet != NULL)
3052 rtx tmp_note = emit_note_after (NOTE_KIND(prologue_end_note), last_insn_in_packet);
3053 memcpy(&NOTE_DATA (tmp_note), &NOTE_DATA(prologue_end_note), sizeof(NOTE_DATA(prologue_end_note)));
3054 delete_insn (prologue_end_note);
3057 if (picochip_flag_var_tracking)
3059 timevar_push (TV_VAR_TRACKING);
3060 variable_tracking_main ();
3061 /* We also have to deal with variable tracking notes in the middle
3063 reorder_var_tracking_notes();
3064 timevar_pop (TV_VAR_TRACKING);
3068 /* Return the ALU character identifier for the current
3069 instruction. This will be 0 or 1. */
3071 picochip_get_vliw_alu_id (void)
3075 /* Always use ALU 0 if VLIW scheduling is disabled. */
3076 if (picochip_schedule_type != DFA_TYPE_SPEED)
3079 /* Get the attribute type of the instruction. Note that this can
3080 ruin the contents of recog_data, so save/restore around the
3082 picochip_save_recog_data ();
3083 attr_type = get_attr_type (picochip_current_prescan_insn);
3084 picochip_restore_recog_data ();
3086 if (picochip_current_vliw_state.contains_pico_alu_insn)
3089 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3090 else it must be the other ALU (either basic or nonCc)
3091 instruction which goes into 1. */
3092 if (attr_type == TYPE_PICOALU)
3098 else if (picochip_current_vliw_state.contains_non_cc_alu_insn)
3100 /* Is this the non CC instruction? If it is, then stuff it into
3101 ALU 1, else it must be a picoAlu or basicAlu, in which case
3102 it goes into ALU 0. */
3103 if (attr_type == TYPE_NONCCALU)
3110 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3111 whether an ALU instruction has already been scheduled in this
3113 switch (picochip_current_vliw_state.num_alu_insns_so_far)
3116 picochip_current_vliw_state.num_alu_insns_so_far++;
3120 picochip_current_vliw_state.num_alu_insns_so_far++;
3124 internal_error ("Too many ALU instructions emitted (%d)\n",
3125 picochip_current_vliw_state.num_alu_insns_so_far);
3132 /* Reset any information about the current VLIW packing status. */
3134 picochip_reset_vliw (rtx insn)
3136 rtx local_insn = insn;
3138 /* Nothing to do if VLIW scheduling isn't being used. */
3139 if (picochip_schedule_type != DFA_TYPE_SPEED)
3143 printf ("%s on insn %d\n", __FUNCTION__, INSN_UID (insn));
3146 picochip_current_vliw_state.contains_pico_alu_insn = 0;
3147 picochip_current_vliw_state.contains_non_cc_alu_insn = 0;
3148 picochip_current_vliw_state.num_alu_insns_so_far = 0;
3149 picochip_current_vliw_state.num_cfi_labels_deferred = 0;
3150 picochip_current_vliw_state.lm_label_name[0] = 0;
3151 picochip_current_vliw_state.num_insns_in_packet = 0;
3153 /* Read through the VLIW packet, classifying the instructions where
3158 if (NOTE_P (local_insn))
3160 local_insn = NEXT_INSN (local_insn);
3163 else if (!INSN_P (local_insn))
3167 /* It is an instruction, but is it ours? */
3168 if (INSN_CODE (local_insn) != -1)
3172 picochip_current_vliw_state.num_insns_in_packet += 1;
3174 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3175 get_attr_type function can overwrite the values in
3176 the recog_data global, hence this is saved and
3177 restored around the call. Not doing so results in
3178 asm_output_opcode being called with a different
3179 instruction to final_prescan_insn, which is fatal. */
3180 picochip_save_recog_data ();
3181 attr_type = get_attr_type (local_insn);
3182 picochip_restore_recog_data ();
3184 if (attr_type == TYPE_PICOALU)
3185 picochip_current_vliw_state.contains_pico_alu_insn = 1;
3186 if (attr_type == TYPE_NONCCALU)
3187 picochip_current_vliw_state.contains_non_cc_alu_insn = 1;
3192 /* Get the next instruction. */
3193 local_insn = NEXT_INSN (local_insn);
3195 /* Keep going while the next instruction is part of the same
3196 VLIW packet (i.e., its a valid instruction and doesn't mark
3197 the start of a new VLIW packet. */
3199 while (local_insn &&
3200 (GET_MODE (local_insn) != TImode) && (INSN_CODE (local_insn) != -1));
3205 picochip_sched_reorder (FILE * file, int verbose,
3206 rtx * ready ATTRIBUTE_UNUSED,
3207 int *n_readyp ATTRIBUTE_UNUSED, int clock)
3211 fprintf (file, ";;\tClock %d\n", clock);
3213 return picochip_sched_issue_rate ();
3218 picochip_sched_lookahead (void)
3220 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3226 picochip_sched_issue_rate (void)
3231 /* Adjust the scheduling cost between the two given instructions,
3232 which have the given dependency. */
3234 picochip_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3239 printf ("Sched Adjust Cost: %d->%d is %d\n",
3240 INSN_UID (insn), INSN_UID (dep_insn), cost);
3242 printf (" Dependency type:");
3243 switch (REG_NOTE_KIND (link))
3251 case REG_DEP_OUTPUT:
3252 printf ("OUTPUT\n");
3255 printf ("Unknown (%d)\n", REG_NOTE_KIND (link));
3259 /* Anti-dependencies are used to enforce the ordering between a
3260 * branch, and any subsequent instructions. For example:
3265 * The ADD instruction must execute after the branch, and this is
3266 * enforced using an anti-dependency. Unfortunately, VLIW machines
3267 * are happy to execute anti-dependent instructions in the same
3268 * cycle, which then results in a schedule like the following being
3271 * BNE someLabel \ ADD.0 r0,r1,r2
3273 * The instruction which would normally be conditionally executed
3274 * depending upon the outcome of the branch, is now unconditionally
3275 * executed every time. To prevent this happening, any
3276 * anti-dependencies between a branch and another instruction are
3277 * promoted to become real dependencies.
3279 if ((JUMP_P (dep_insn) || CALL_P(dep_insn)) && REG_NOTE_KIND (link) == REG_DEP_ANTI)
3283 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3284 INSN_UID (insn), INSN_UID (dep_insn));
3293 /* Return the minimum of the two values */
3295 minimum (int a, int b)
3301 /* I dont expect to get to this function with a==b.*/
3306 /* This function checks if the memory of the two stores are just off by 2 bytes.
3307 It returns the lower memory operand's index.*/
3310 memory_just_off (rtx opnd1, rtx opnd2)
3312 int offset1 = 0, offset2 = 0;
3315 if (GET_CODE(XEXP(opnd1, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1, 0),1)) == CONST_INT)
3317 offset1 = INTVAL(XEXP(XEXP(opnd1, 0), 1));
3318 reg1 = REGNO(XEXP(XEXP(opnd1, 0), 0));
3322 reg1 = REGNO(XEXP(opnd1, 0));
3324 if (GET_CODE(XEXP(opnd2, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2, 0), 1)) == CONST_INT)
3326 offset2 = INTVAL(XEXP(XEXP(opnd2, 0), 1));
3327 reg2 = REGNO(XEXP(XEXP(opnd2, 0), 0));
3331 reg2 = REGNO(XEXP(opnd2, 0));
3334 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3335 should be 4 byte aligned. We can currently guarentee that only if the base
3336 address is FP(R13) and the offset is aligned. */
3338 if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
3339 return (minimum(offset1, offset2) == offset1) ? 1:2;
3345 registers_just_off (rtx opnd1, rtx opnd2)
3348 reg1 = REGNO(opnd1);
3349 reg2 = REGNO(opnd2);
3350 if (abs(reg1-reg2) == 1 && minimum(reg1, reg2) % 2 == 0)
3351 return (minimum(reg1, reg2) == reg1)?1:2;
3355 /* Check to see if the two LDWs can be peepholed together into a LDL
3356 They can be if the registers getting loaded into are contiguous
3357 and the memory addresses are contiguous as well.
3361 can be merged together into
3365 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3366 aligned address. Only FP can be assumed to be 4 byte aligned.
3367 2. The progression of addresses and the register numbers should
3368 be similar. For eg., if you swap r2 and r3 in the above instructions,
3369 the resultant pair cannot be merged.
3373 ok_to_peephole_ldw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3375 int memtest=0,regtest=0;
3376 regtest = registers_just_off(opnd1,opnd3);
3380 memtest = memory_just_off(opnd0,opnd2);
3384 if (regtest == memtest)
3391 /* Similar to LDW peephole */
3393 ok_to_peephole_stw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3395 int memtest=0,regtest=0;
3396 regtest = registers_just_off(opnd1,opnd3);
3400 memtest = memory_just_off(opnd0,opnd2);
3404 if (regtest == memtest)
3412 /* Generate a SImode register with the register number that is the smaller of the two */
3414 gen_min_reg(rtx opnd1,rtx opnd2)
3416 return gen_rtx_REG (SImode, minimum(REGNO(opnd1),REGNO(opnd2)));
3419 /* Generate a SImode memory with the address that is the smaller of the two */
3421 gen_SImode_mem(rtx opnd1,rtx opnd2)
3423 int offset1=0,offset2=0;
3425 if (GET_CODE(XEXP(opnd1,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1,0),1)) == CONST_INT)
3427 offset1 = INTVAL(XEXP(XEXP(opnd1,0),1));
3428 reg = XEXP(XEXP(opnd1,0),0);
3432 reg = XEXP(opnd1,0);
3434 if (GET_CODE(XEXP(opnd2,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2,0),1)) == CONST_INT)
3436 offset2 = INTVAL(XEXP(XEXP(opnd2,0),1));
3438 rtx address = gen_rtx_PLUS (HImode, reg, GEN_INT(minimum(offset1,offset2)));
3439 return gen_rtx_MEM(SImode,address);
3443 picochip_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int* total)
3450 /* Need to penalize immediates that need to be encoded as long constants.*/
3451 if (code == CONST_INT && !(INTVAL (x) >= 0 && INTVAL (x) < 16))
3453 *total = COSTS_N_INSNS(1);
3461 *total = COSTS_N_INSNS (outer_code != MEM);
3466 /* if_then_else come out of cbranch instructions. It will get split into
3467 a condition code generating subtraction and a branch */
3468 *total = COSTS_N_INSNS (2);
3475 if (GET_MODE(x) == SImode)
3476 *total = COSTS_N_INSNS (2);
3477 if (GET_MODE(x) == DImode)
3478 *total = COSTS_N_INSNS (4);
3482 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3483 if (GET_MODE(x) == QImode && !TARGET_HAS_BYTE_ACCESS)
3484 *total = COSTS_N_INSNS (10);
3486 /* 64-bit accesses have to be done through 2 32-bit access */
3487 if (GET_MODE(x) == DImode)
3488 *total = COSTS_N_INSNS (2);
3494 /* SImode shifts are expensive */
3495 if (GET_MODE(x) == SImode)
3496 *total = COSTS_N_INSNS (10);
3498 /* Register shift by constant is cheap. */
3499 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3500 && GET_CODE(XEXP(x, 0)) == REG
3501 && GET_CODE(XEXP(x, 1)) == CONST_INT)
3502 *total = COSTS_N_INSNS (1);
3504 *total = COSTS_N_INSNS (4);
3511 /* Divisions are more expensive than the default 7*/
3512 if (GET_MODE(x) == SImode)
3513 *total = COSTS_N_INSNS (20);
3515 *total = COSTS_N_INSNS (12);
3520 /* Look for the simple cases of multiplying register*register or
3521 register*constant. */
3522 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3523 && ((GET_CODE(XEXP(x, 0)) == REG
3524 && (GET_CODE(XEXP(x, 1)) == REG || GET_CODE(XEXP(x,1)) == CONST_INT))
3525 || (GET_CODE(XEXP(x, 0)) == ZERO_EXTEND
3526 && GET_CODE(XEXP(XEXP(x, 0),0)) == REG
3527 && GET_CODE(XEXP(x, 1)) == ZERO_EXTEND
3528 && GET_CODE(XEXP(XEXP(x, 1),0)) == REG)))
3531 /* When optimising for size, multiplication by constant
3532 should be discouraged slightly over multiplication by a
3534 if (picochip_has_mac_unit)
3536 /* Single cycle multiplication, but the result must be
3537 loaded back into a general register afterwards. */
3538 *total = COSTS_N_INSNS(2);
3541 else if (picochip_has_mul_unit)
3543 /* Single cycle multiplication. */
3544 *total = COSTS_N_INSNS(1);
3547 /* Else no multiply available. Use default cost. */
3557 if (localTotal != 0)
3559 *total = localTotal;
3570 picochip_final_prescan_insn (rtx insn, rtx * opvec ATTRIBUTE_UNUSED,
3571 int num_operands ATTRIBUTE_UNUSED)
3575 picochip_current_prescan_insn = insn;
3578 printf ("Final prescan on INSN %d with mode %s\n",
3579 INSN_UID (insn), GET_MODE_NAME (GET_MODE (insn)));
3581 /* If this is the start of a new instruction cycle, or no scheduling
3582 is used, then reset the VLIW status. */
3583 if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
3584 picochip_reset_vliw (insn);
3586 /* No VLIW scheduling occured, so don't go any further. */
3587 if (picochip_schedule_type != DFA_TYPE_SPEED)
3590 /* Look for the next printable instruction. This loop terminates on
3591 any recognisable instruction, and on any unrecognisable
3592 instruction with TImode. */
3594 for (local_insn = NEXT_INSN (local_insn); local_insn;
3595 local_insn = NEXT_INSN (local_insn))
3597 if (NOTE_P (local_insn))
3599 else if (!INSN_P (local_insn))
3601 else if (GET_MODE (local_insn) == TImode
3602 || INSN_CODE (local_insn) != -1)
3606 /* Set the continuation flag if the next instruction can be packed
3607 with the current instruction (i.e., the next instruction is
3608 valid, and isn't the start of a new cycle). */
3609 picochip_vliw_continuation = (local_insn && INSN_P (local_insn) &&
3610 (GET_MODE (local_insn) != TImode));
3614 /* Builtin functions. */
3615 /* Given a builtin function taking 2 operands (i.e., target + source),
3616 emit the RTL for the underlying instruction. */
3618 picochip_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target)
3622 enum machine_mode tmode, mode0;
3624 /* Grab the incoming argument and emit its RTL. */
3625 arg0 = TREE_VALUE (arglist);
3626 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3628 /* Determine the modes of the instruction operands. */
3629 tmode = insn_data[icode].operand[0].mode;
3630 mode0 = insn_data[icode].operand[1].mode;
3632 /* Ensure that the incoming argument RTL is in a register of the
3634 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3635 op0 = copy_to_mode_reg (mode0, op0);
3637 /* If there isn't a suitable target, emit a target register. */
3639 || GET_MODE (target) != tmode
3640 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3641 target = gen_reg_rtx (tmode);
3643 /* Emit and return the new instruction. */
3644 pat = GEN_FCN (icode) (target, op0);
3653 /* Given a builtin function taking 3 operands (i.e., target + two
3654 source), emit the RTL for the underlying instruction. */
3656 picochip_expand_builtin_3op (enum insn_code icode, tree arglist, rtx target)
3660 enum machine_mode tmode, mode0, mode1;
3662 /* Grab the function's arguments. */
3663 arg0 = TREE_VALUE (arglist);
3664 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3666 /* Emit rtl sequences for the function arguments. */
3667 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3668 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3670 /* Get the mode's of each of the instruction operands. */
3671 tmode = insn_data[icode].operand[0].mode;
3672 mode0 = insn_data[icode].operand[1].mode;
3673 mode1 = insn_data[icode].operand[2].mode;
3675 /* Ensure that each of the function argument rtl sequences are in a
3676 register of the correct mode. */
3677 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3678 op0 = copy_to_mode_reg (mode0, op0);
3679 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
3680 op1 = copy_to_mode_reg (mode1, op1);
3682 /* If no target has been given, create a register to use as the target. */
3684 || GET_MODE (target) != tmode
3685 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3686 target = gen_reg_rtx (tmode);
3688 /* Emit and return the new instruction. */
3689 pat = GEN_FCN (icode) (target, op0, op1);
3698 /* Expand a builtin function which takes two arguments, and returns a void. */
3700 picochip_expand_builtin_2opvoid (enum insn_code icode, tree arglist)
3704 enum machine_mode mode0, mode1;
3706 /* Grab the function's arguments. */
3707 arg0 = TREE_VALUE (arglist);
3708 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3710 /* Emit rtl sequences for the function arguments. */
3711 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3712 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3714 /* Get the mode's of each of the instruction operands. */
3715 mode0 = insn_data[icode].operand[0].mode;
3716 mode1 = insn_data[icode].operand[1].mode;
3718 /* Ensure that each of the function argument rtl sequences are in a
3719 register of the correct mode. */
3720 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
3721 op0 = copy_to_mode_reg (mode0, op0);
3722 if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
3723 op1 = copy_to_mode_reg (mode1, op1);
3725 /* Emit and return the new instruction. */
3726 pat = GEN_FCN (icode) (op0, op1);
3735 /* Expand an array get into the corresponding RTL. */
3737 picochip_expand_array_get (tree arglist, rtx target)
3739 tree arg0, arg1, arg2;
3740 rtx op0, op1, op2, pat;
3742 /* Grab the function's arguments. */
3743 arg0 = TREE_VALUE (arglist);
3744 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3745 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3747 /* Emit rtl sequences for the function arguments. */
3748 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3749 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3750 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3752 /* The second and third operands must be constant. Nothing else will
3754 if (CONST_INT != GET_CODE (op1))
3755 internal_error ("%s: Second source operand is not a constant",
3757 if (CONST_INT != GET_CODE (op2))
3758 internal_error ("%s: Third source operand is not a constant",
3761 /* If no target has been given, create a register to use as the target. */
3762 if (target == 0 || GET_MODE (target) != SImode)
3763 target = gen_reg_rtx (SImode);
3765 /* The first operand must be a HImode register or a constant. If it
3766 isn't, force it into a HImode register. */
3767 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3768 op0 = copy_to_mode_reg (HImode, op0);
3771 /* Emit and return the new instruction. */
3772 pat = gen_commsArrayGet (target, op0, op1, op2);
3779 /* Expand an array put into the corresponding RTL. */
3781 picochip_expand_array_put (tree arglist, rtx target)
3783 tree arg0, arg1, arg2, arg3;
3784 rtx op0, op1, op2, op3, pat;
3786 /* Grab the function's arguments. */
3787 arg0 = TREE_VALUE (arglist);
3788 arg1 = TREE_VALUE (arglist->common.chain);
3789 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3790 arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
3792 /* Emit rtl sequences for the function arguments. */
3793 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3794 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3795 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3796 op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
3798 /* The first operand must be an SImode register. */
3799 if (GET_MODE (op0) != SImode || REG != GET_CODE (op0))
3800 op0 = copy_to_mode_reg (SImode, op0);
3802 /* The second (index) operand must be a HImode register, or a
3803 constant. If it isn't, force it into a HImode register. */
3804 if (GET_MODE (op1) != HImode || REG != GET_CODE (op1))
3805 op1 = copy_to_mode_reg (HImode, op1);
3807 /* The remaining operands must be constant. Nothing else will do. */
3808 if (CONST_INT != GET_CODE (op2))
3809 internal_error ("%s: Third source operand is not a constant",
3811 if (CONST_INT != GET_CODE (op3))
3812 internal_error ("%s: Fourth source operand is not a constant",
3815 /* Emit and return the new instruction. */
3816 pat = gen_commsArrayPut (op0, op1, op2, op3);
3823 /* Expand an array testport into the corresponding RTL. */
3825 picochip_expand_array_testport (tree arglist, rtx target)
3827 tree arg0, arg1, arg2;
3828 rtx op0, op1, op2, pat;
3830 /* Grab the function's arguments. */
3831 arg0 = TREE_VALUE (arglist);
3832 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3833 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3835 /* Emit rtl sequences for the function arguments. */
3836 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3837 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3838 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3840 /* The first operand must be a HImode register, or a constant. If it
3841 isn't, force it into a HImode register. */
3842 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3843 op0 = copy_to_mode_reg (HImode, op0);
3845 /* The second and third operands must be constant. Nothing else will
3847 if (CONST_INT != GET_CODE (op1))
3848 internal_error ("%s: Second source operand is not a constant",
3850 if (CONST_INT != GET_CODE (op2))
3851 internal_error ("%s: Third source operand is not a constant",
3854 /* If no target has been given, create a HImode register to use as
3856 if (target == 0 || GET_MODE (target) != HImode)
3857 target = gen_reg_rtx (HImode);
3859 /* Emit and return the new instruction. */
3860 pat = gen_commsArrayTestPort (target, op0, op1, op2);
3867 /* Generate a unique HALT instruction by giving the instruction a
3868 unique integer. This integer makes no difference to the assembly
3869 output (other than a comment indicating the supplied id), but the
3870 presence of the unique integer prevents the compiler from combining
3871 several different halt instructions into one instruction. This
3872 means that each use of the halt instruction is unique, which in
3873 turn means that assertions work as expected. */
3875 picochip_generate_halt (void)
3877 static int currentId = 0;
3878 rtx id = GEN_INT (currentId);
3882 emit_insn (gen_halt (id));
3884 /* A barrier is inserted to prevent the compiler from thinking that
3885 it has to continue execution after the HALT.*/
3888 rtx insns = get_insns();
3896 picochip_generate_profile (tree arglist)
3898 tree arg0 = TREE_VALUE (arglist);
3899 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3902 emit_insn (gen_profile (op0));
3904 rtx insns = get_insns();
3912 /* Initialise the builtin functions. Start by initialising
3913 descriptions of different types of functions (e.g., void fn(int),
3914 int fn(void)), and then use these to define the builtins. */
3916 picochip_init_builtins (void)
3918 tree endlink = void_list_node;
3919 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
3920 tree unsigned_endlink = tree_cons (NULL_TREE, unsigned_type_node, endlink);
3921 tree long_endlink = tree_cons (NULL_TREE, long_integer_type_node, endlink);
3922 tree int_int_endlink =
3923 tree_cons (NULL_TREE, integer_type_node, int_endlink);
3924 tree int_int_int_endlink =
3925 tree_cons (NULL_TREE, integer_type_node, int_int_endlink);
3926 tree int_long_endlink =
3927 tree_cons (NULL_TREE, integer_type_node, long_endlink);
3928 tree pchar_type_node = build_pointer_type (char_type_node);
3929 tree long_int_int_int_endlink =
3930 tree_cons (NULL_TREE, long_integer_type_node, int_int_int_endlink);
3932 tree int_ftype_void, int_ftype_int, int_ftype_int_int, void_ftype_pchar;
3933 tree long_ftype_int, long_ftype_int_int, long_ftype_int_int_int;
3934 tree void_ftype_int_long, int_ftype_int_int_int,
3935 void_ftype_long_int_int_int;
3936 tree void_ftype_void, void_ftype_int, unsigned_ftype_unsigned;
3938 /* void func (void) */
3939 void_ftype_void = build_function_type (void_type_node, endlink);
3941 /* void func (void *) */
3943 = build_function_type (void_type_node,
3944 tree_cons (NULL_TREE, pchar_type_node, endlink));
3946 /* int func (void) */
3947 int_ftype_void = build_function_type (integer_type_node, endlink);
3949 /* void func (int) */
3950 void_ftype_int = build_function_type (void_type_node, int_endlink);
3952 /* int func (int) */
3953 int_ftype_int = build_function_type (integer_type_node, int_endlink);
3955 /* unsigned int func (unsigned int) */
3956 unsigned_ftype_unsigned = build_function_type (unsigned_type_node, unsigned_endlink);
3958 /* int func(int, int) */
3960 = build_function_type (integer_type_node, int_int_endlink);
3962 /* long func(int) */
3963 long_ftype_int = build_function_type (long_integer_type_node, int_endlink);
3965 /* long func(int, int) */
3967 = build_function_type (long_integer_type_node, int_int_endlink);
3969 /* long func(int, int, int) */
3970 long_ftype_int_int_int
3971 = build_function_type (long_integer_type_node, int_int_int_endlink);
3973 /* int func(int, int, int) */
3974 int_ftype_int_int_int
3975 = build_function_type (integer_type_node, int_int_int_endlink);
3977 /* void func(int, long) */
3979 = build_function_type (void_type_node, int_long_endlink);
3981 /* void func(long, int, int, int) */
3982 void_ftype_long_int_int_int
3983 = build_function_type (void_type_node, long_int_int_int_endlink);
3985 /* Initialise the sign-bit-count function. */
3986 add_builtin_function ("__builtin_sbc", int_ftype_int,
3987 PICOCHIP_BUILTIN_SBC, BUILT_IN_MD, NULL,
3989 add_builtin_function ("picoSbc", int_ftype_int, PICOCHIP_BUILTIN_SBC,
3990 BUILT_IN_MD, NULL, NULL_TREE);
3992 /* Initialise the bit reverse function. */
3993 add_builtin_function ("__builtin_profile", void_ftype_int,
3994 PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL,
3996 add_builtin_function ("picoProfile", void_ftype_int,
3997 PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL,
4000 /* Initialise the bit reverse function. */
4001 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned,
4002 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4004 add_builtin_function ("picoBrev", unsigned_ftype_unsigned,
4005 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4008 /* Initialise the byte swap function. */
4009 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned,
4010 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4012 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned,
4013 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4016 /* Initialise the ASRI function (note that while this can be coded
4017 using a signed shift in C, extra scratch registers are required,
4018 which we avoid by having a direct builtin to map to the
4020 add_builtin_function ("__builtin_asri", int_ftype_int_int,
4021 PICOCHIP_BUILTIN_ASRI, BUILT_IN_MD, NULL,
4024 /* Initialise saturating addition. */
4025 add_builtin_function ("__builtin_adds", int_ftype_int_int,
4026 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4028 add_builtin_function ("picoAdds", int_ftype_int_int,
4029 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4032 /* Initialise saturating subtraction. */
4033 add_builtin_function ("__builtin_subs", int_ftype_int_int,
4034 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4036 add_builtin_function ("picoSubs", int_ftype_int_int,
4037 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4040 /* Scalar comms builtins. */
4041 add_builtin_function ("__builtin_get", long_ftype_int,
4042 PICOCHIP_BUILTIN_GET, BUILT_IN_MD, NULL,
4044 add_builtin_function ("__builtin_put", void_ftype_int_long,
4045 PICOCHIP_BUILTIN_PUT, BUILT_IN_MD, NULL,
4047 add_builtin_function ("__builtin_testport", int_ftype_int,
4048 PICOCHIP_BUILTIN_TESTPORT, BUILT_IN_MD, NULL,
4051 /* Array comms builtins. */
4052 add_builtin_function ("__builtin_put_array",
4053 void_ftype_long_int_int_int,
4054 PICOCHIP_BUILTIN_PUT_ARRAY, BUILT_IN_MD, NULL,
4056 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int,
4057 PICOCHIP_BUILTIN_GET_ARRAY, BUILT_IN_MD, NULL,
4059 add_builtin_function ("__builtin_testport_array",
4060 int_ftype_int_int_int,
4061 PICOCHIP_BUILTIN_TESTPORT_ARRAY, BUILT_IN_MD,
4064 /* Halt instruction. Note that the builtin function is marked as
4065 having the attribute `noreturn' so that the compiler realises
4066 that the halt stops the program dead. */
4067 tree noreturn = tree_cons (get_identifier ("noreturn"), NULL, NULL);
4068 add_builtin_function ("__builtin_halt", void_ftype_void,
4069 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4071 add_builtin_function ("picoHalt", void_ftype_void,
4072 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4077 /* Expand a call to a builtin function. */
4079 picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
4080 enum machine_mode mode ATTRIBUTE_UNUSED,
4081 int ignore ATTRIBUTE_UNUSED)
4083 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4084 tree arglist = CALL_EXPR_ARGS(exp);
4085 int fcode = DECL_FUNCTION_CODE (fndecl);
4089 case PICOCHIP_BUILTIN_ASRI:
4090 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri, arglist,
4093 case PICOCHIP_BUILTIN_ADDS:
4094 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3, arglist,
4097 case PICOCHIP_BUILTIN_SUBS:
4098 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3, arglist,
4101 case PICOCHIP_BUILTIN_SBC:
4102 return picochip_expand_builtin_2op (CODE_FOR_sbc, arglist, target);
4104 case PICOCHIP_BUILTIN_BREV:
4105 return picochip_expand_builtin_2op (CODE_FOR_brev, arglist, target);
4107 case PICOCHIP_BUILTIN_BYTESWAP:
4108 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2, arglist, target);
4110 case PICOCHIP_BUILTIN_GET:
4111 return picochip_expand_builtin_2op (CODE_FOR_commsGet, arglist, target);
4113 case PICOCHIP_BUILTIN_PUT:
4114 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut, arglist);
4116 case PICOCHIP_BUILTIN_TESTPORT:
4117 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort, arglist,
4120 case PICOCHIP_BUILTIN_PUT_ARRAY:
4121 return picochip_expand_array_put (arglist, target);
4123 case PICOCHIP_BUILTIN_GET_ARRAY:
4124 return picochip_expand_array_get (arglist, target);
4126 case PICOCHIP_BUILTIN_TESTPORT_ARRAY:
4127 return picochip_expand_array_testport (arglist, target);
4129 case PICOCHIP_BUILTIN_HALT:
4130 return picochip_generate_halt ();
4132 case PICOCHIP_BUILTIN_PROFILE:
4133 return picochip_generate_profile (arglist);
4140 /* Should really do something sensible here. */
4144 /* Emit warnings. */
4146 picochip_warn_inefficient (const char *msg)
4148 if (TARGET_INEFFICIENT_WARNINGS)
4149 warning (OPT_minefficient_warnings,
4150 "%s (disable warning using -mno-inefficient-warnings)", msg);
4154 warn_of_byte_access (void)
4156 static int warned = 0;
4160 picochip_warn_inefficient
4161 ("byte access is synthesised - consider using MUL AE");
4168 picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
4169 bool outgoing ATTRIBUTE_UNUSED)
4171 enum machine_mode mode = TYPE_MODE (valtype);
4172 int unsignedp = TYPE_UNSIGNED (valtype);
4174 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4175 just as PROMOTE_MODE does. */
4176 mode = promote_mode (valtype, mode, &unsignedp, 1);
4178 return gen_rtx_REG (mode, 0);
4182 /* Check that the value of the given mode will fit in the register of
4185 picochip_hard_regno_mode_ok (int regno, enum machine_mode mode)
4188 if (GET_MODE_CLASS (mode) == MODE_CC)
4189 return regno == CC_REGNUM;
4191 /* If the CC register is being used, then only CC mode values are
4192 allowed (which have already been tested). */
4193 if (regno == CC_REGNUM || regno == ACC_REGNUM)
4196 /* Must be a valid register. */
4200 /* Modes QI and HI may be placed in any register except the CC. */
4201 if (mode == QImode || mode == HImode)
4204 /* DI must be in a quad register. */
4206 return (regno % 4 == 0);
4208 /* All other modes must be placed in a even numbered register. */
4209 return !(regno & 1);
4213 /* Extract the lower and upper components of a constant value. */
4216 picochip_get_low_const (rtx value)
4218 return gen_int_mode (INTVAL (value) & 0xFFFF, HImode);
4222 picochip_get_high_const (rtx value)
4224 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4225 return gen_int_mode ((INTVAL (value) >> 16) & 0xFFFF, HImode);
4229 /* Loading and storing QImode values to and from memory in a machine
4230 without byte access requires might require a scratch
4231 register. However, the scratch register might correspond to the
4232 register in which the value is being loaded. To ensure that a
4233 scratch register is supplied which is definitely different to the
4234 output register, request a register pair. This effectively gives a
4235 choice of two registers to choose from, so that we a guaranteed to
4236 get at least one register which is different to the output
4237 register. This trick is taken from the alpha implementation. */
4239 picochip_secondary_reload (bool in_p,
4240 rtx x ATTRIBUTE_UNUSED,
4241 enum reg_class cla ATTRIBUTE_UNUSED,
4242 enum machine_mode mode,
4243 secondary_reload_info *sri)
4245 if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
4248 sri->icode = CODE_FOR_reload_outqi;
4250 sri->icode = CODE_FOR_reload_inqi;
4253 /* We dont need to return a register class type when we need only a
4254 scratch register. It realizes the scratch register type by looking
4255 at the instruction definition for sri->icode. We only need to
4256 return the register type when we need intermediaries for copies.*/
4260 /* Return true if the given memory operand can be aligned to a
4261 word+offset memory reference (e.g., FP+3 can be converted into the
4262 memory operand FP+2, with the offset 1). */
4264 picochip_alignable_memory_operand (rtx mem_operand,
4265 enum machine_mode mode ATTRIBUTE_UNUSED)
4269 /* Not a mem operand. Refuse immediately. */
4270 if (MEM != GET_CODE (mem_operand))
4273 address = XEXP (mem_operand, 0);
4275 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4276 return ((PLUS == GET_CODE (address) &&
4277 REGNO (XEXP (address, 0)) == STACK_POINTER_REGNUM &&
4278 CONST_INT == GET_CODE (XEXP (address, 1)) &&
4279 picochip_const_ok_for_letter_p (INTVAL (XEXP (address, 1)), 'K'))
4280 || (REG == GET_CODE (address)
4281 && REGNO (address) == STACK_POINTER_REGNUM));
4285 /* Return true if the given memory reference is to a word aligned
4286 address. Currently this means it must be either SP, or
4287 SP+offset. We could replace this function with alignable
4288 memory references in the above function?. */
4290 picochip_word_aligned_memory_reference (rtx operand)
4294 /* The address must be the SP register, or a constant, aligned
4295 offset from SP which doesn't exceed the FP+offset
4297 return ((PLUS == GET_CODE (operand)
4298 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
4299 && picochip_is_aligned (INTVAL (XEXP (operand, 1)), 16)
4300 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand, 1)),
4302 || (REG == GET_CODE (operand)
4303 && REGNO (operand) == STACK_POINTER_REGNUM));
4307 /* Given an alignable memory location, convert the memory location
4308 into a HI mode access, storing the new memory reference in
4309 paligned_mem, and the number of bits by which to shift in pbitnum
4310 (i.e., given a reference to FP+3, this creates an aligned reference
4311 of FP+2, with an 8-bit shift). This code is a modification of that
4312 found in the Alpha port. */
4314 picochip_get_hi_aligned_mem (rtx ref, rtx * paligned_mem, rtx * pbitnum)
4317 HOST_WIDE_INT offset = 0;
4319 gcc_assert (GET_CODE (ref) == MEM);
4321 if (reload_in_progress && !memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
4323 base = find_replacement (&XEXP (ref, 0));
4325 gcc_assert(memory_address_p (GET_MODE (ref), base));
4329 base = XEXP (ref, 0);
4332 if (GET_CODE (base) == PLUS)
4334 offset += INTVAL (XEXP (base, 1));
4335 base = XEXP (base, 0);
4338 *paligned_mem = widen_memory_access (ref, HImode, (offset & ~1) - offset);
4345 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4349 *pbitnum = GEN_INT ((offset & 1) * 8);
4353 /* Return true if the given operand is an absolute address in memory
4354 (i.e., a symbolic offset). */
4356 picochip_absolute_memory_operand (rtx op,
4357 enum machine_mode mode ATTRIBUTE_UNUSED)
4360 if (MEM == GET_CODE (op))
4362 rtx address = XEXP (op, 0);
4364 /* Symbols are valid absolute addresses. */
4365 if (SYMBOL_REF == GET_CODE (address))
4368 /* Constant offsets to symbols are valid absolute addresses. */
4369 if (CONST == GET_CODE (address) &&
4370 PLUS == GET_CODE (XEXP (address, 0)) &&
4371 SYMBOL_REF == GET_CODE (XEXP (XEXP (address, 0), 0)) &&
4372 CONST_INT == GET_CODE (XEXP (XEXP (address, 0), 1)))
4379 /* Symbols are valid absolute addresses. */
4380 if (SYMBOL_REF == GET_CODE (XEXP (op, 0)))
4389 picochip_asm_named_section (const char *name,
4390 unsigned int flags ATTRIBUTE_UNUSED,
4391 tree decl ATTRIBUTE_UNUSED)
4393 fprintf (asm_out_file, ".section %s\n", name);
4397 /* Check if we can make a conditional copy instruction. This is emitted as an
4398 instruction to set the condition register, followed by an instruction which
4399 uses the condition registers to perform the conditional move. */
4401 picochip_check_conditional_copy (rtx * operands)
4404 rtx branch_op_0 = XEXP (operands[1], 0);
4405 rtx branch_op_1 = XEXP (operands[1], 1);
4407 /* Only HI mode conditional moves are currently allowed. Can we add
4409 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
4412 /* Is the comparison valid? Only allow operands which are registers
4413 if they are HImode. SI mode comparisons against 0 could be
4414 handled using logical operations (e.g., SIreg != 0 when low ||
4415 high). Need to find test cases to provoke this though (fixunssfdi
4416 in libgcc does, but is complicated). */
4417 if (GET_MODE (branch_op_0) != HImode ||
4418 !(register_operand (branch_op_0, GET_MODE (branch_op_0))))
4420 if (GET_MODE (branch_op_1) != HImode ||
4421 !(picochip_comparison_operand (branch_op_1, GET_MODE (branch_op_1))))