1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 Contributed by Picochip Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
49 #include "target-def.h"
50 #include "langhooks.h"
54 #include "picochip-protos.h"
56 #include "insn-attr.h" /* For DFA state_t. */
57 #include "insn-config.h" /* Required by recog.h */
58 #include "insn-codes.h" /* For CODE_FOR_? */
59 #include "optabs.h" /* For GEN_FCN */
60 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
61 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
62 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
63 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
66 /* Target AE ISA information. */
67 enum picochip_dfa_type picochip_schedule_type;
69 bool picochip_has_mul_unit = false;
70 bool picochip_has_mac_unit = false;
72 /* targetm hook function prototypes. */
74 void picochip_asm_file_start (void);
75 void picochip_asm_file_end (void);
77 void picochip_init_libfuncs (void);
78 void picochip_reorg (void);
80 int picochip_arg_partial_bytes (cumulative_args_t p_cum,
81 enum machine_mode mode,
82 tree type, bool named);
83 rtx picochip_function_arg (cumulative_args_t p_cum,
84 enum machine_mode mode,
85 const_tree type, bool named);
86 rtx picochip_incoming_function_arg (cumulative_args_t p_cum,
87 enum machine_mode mode,
88 const_tree type, bool named);
89 void picochip_arg_advance (cumulative_args_t p_cum, enum machine_mode mode,
90 const_tree type, bool named);
91 unsigned int picochip_function_arg_boundary (enum machine_mode mode,
94 int picochip_sched_lookahead (void);
95 int picochip_sched_issue_rate (void);
96 int picochip_sched_adjust_cost (rtx insn, rtx link,
97 rtx dep_insn, int cost);
98 int picochip_sched_reorder (FILE * file, int verbose, rtx * ready,
99 int *n_readyp, int clock);
101 void picochip_init_builtins (void);
102 rtx picochip_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
104 bool picochip_rtx_costs (rtx x, int code, int outer_code, int opno,
105 int* total, bool speed);
106 bool picochip_return_in_memory(const_tree type,
107 const_tree fntype ATTRIBUTE_UNUSED);
108 bool picochip_legitimate_address_p (enum machine_mode, rtx, bool);
109 rtx picochip_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
110 enum machine_mode mode);
111 int picochip_legitimize_reload_address (rtx *x, enum machine_mode mode,
112 int opnum, int type, int ind_levels);
114 rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
115 rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
116 bool outgoing ATTRIBUTE_UNUSED);
118 picochip_secondary_reload (bool in_p,
119 rtx x ATTRIBUTE_UNUSED,
120 reg_class_t cla ATTRIBUTE_UNUSED,
121 enum machine_mode mode,
122 secondary_reload_info *sri);
124 picochip_asm_named_section (const char *name,
125 unsigned int flags ATTRIBUTE_UNUSED,
126 tree decl ATTRIBUTE_UNUSED);
128 static rtx picochip_static_chain (const_tree, bool);
130 static void picochip_option_override (void);
132 /* Lookup table mapping a register number to the earliest containing
133 class. Used by REGNO_REG_CLASS. */
134 const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER] =
136 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
137 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
138 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
139 GR_REGS, FRAME_REGS, PTR_REGS, CONST_REGS,
140 ACC_REGS, CC_REGS, GR_REGS, GR_REGS
143 /* picoChip register names. */
144 const char *picochip_regnames[] = REGISTER_NAMES;
146 /* Define the maximum number of registers which may be used to pass
147 * parameters to functions. */
148 #define MAX_CALL_PARAMETER_REGS 6
151 /* Target scheduling information. */
153 /* This flag indicates whether the next instruction to be output is a
154 VLIW continuation instruction. It is used to communicate between
155 final_prescan_insn and asm_output_opcode. */
156 static int picochip_vliw_continuation = 0;
158 /* This variable is used to communicate the current instruction
159 between final_prescan_insn and functions such as asm_output_opcode,
160 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
161 current instruction. */
162 static rtx picochip_current_prescan_insn;
164 static bool picochip_is_delay_slot_pending = 0;
166 /* When final_prescan_insn is called, it computes information about
167 the current VLIW packet, and stores it in this structure. When
168 instructions are output, this state is used to make sure that the
169 instructions are output in the correct way (e.g., which ALU to use,
170 whether a macro branch was ever previously a real branch, etc.). */
173 int contains_pico_alu_insn;
174 int contains_non_cc_alu_insn;
175 int num_alu_insns_so_far;
177 /* Record how many instructions are contained in the packet. */
178 int num_insns_in_packet;
180 /* There was a case for this to be more than 1 */
181 int num_cfi_labels_deferred;
182 char cfi_label_name[2][256]; /* Used to record the name of a CFI label
183 emitted inside a VLIW packet. */
184 char lm_label_name[256]; /* Used to record the name of an LM label. */
187 struct vliw_state picochip_current_vliw_state;
189 /* Save/restore recog_data. */
190 static int picochip_saved_which_alternative;
191 static struct recog_data picochip_saved_recog_data;
193 /* Determine which ALU to use for the instruction in
194 picochip_current_prescan_insn. */
195 static char picochip_get_vliw_alu_id (void);
197 /* Initialize the GCC target structure. */
199 #undef TARGET_ASM_FUNCTION_PROLOGUE
200 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
202 #undef TARGET_ASM_FUNCTION_EPILOGUE
203 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
205 #undef TARGET_ASM_INTERNAL_LABEL
206 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
208 #undef TARGET_ASM_GLOBALIZE_LABEL
209 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
211 #undef TARGET_ASM_BYTE_OP
212 #define TARGET_ASM_BYTE_OP ".initByte "
213 #undef TARGET_ASM_ALIGNED_HI_OP
214 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
215 #undef TARGET_ASM_UNALIGNED_HI_OP
216 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
217 #undef TARGET_ASM_ALIGNED_SI_OP
218 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
219 #undef TARGET_ASM_UNALIGNED_SI_OP
220 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
222 #undef TARGET_INIT_BUILTINS
223 #define TARGET_INIT_BUILTINS picochip_init_builtins
225 #undef TARGET_EXPAND_BUILTIN
226 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
228 #undef TARGET_RTX_COSTS
229 #define TARGET_RTX_COSTS picochip_rtx_costs
231 #undef TARGET_SCHED_ISSUE_RATE
232 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
234 #undef TARGET_SCHED_REORDER
235 #define TARGET_SCHED_REORDER picochip_sched_reorder
237 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
238 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
239 picochip_sched_lookahead
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
244 #undef TARGET_ASM_NAMED_SECTION
245 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
247 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
248 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
250 #undef TARGET_INIT_LIBFUNCS
251 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
253 #undef TARGET_ASM_FILE_START
254 #define TARGET_ASM_FILE_START picochip_asm_file_start
256 #undef TARGET_ASM_FILE_END
257 #define TARGET_ASM_FILE_END picochip_asm_file_end
259 #undef TARGET_MACHINE_DEPENDENT_REORG
260 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
262 #undef TARGET_ARG_PARTIAL_BYTES
263 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
265 #undef TARGET_FUNCTION_ARG
266 #define TARGET_FUNCTION_ARG picochip_function_arg
268 #undef TARGET_FUNCTION_INCOMING_ARG
269 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
271 #undef TARGET_FUNCTION_ARG_ADVANCE
272 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
274 #undef TARGET_FUNCTION_ARG_BOUNDARY
275 #define TARGET_FUNCTION_ARG_BOUNDARY picochip_function_arg_boundary
277 #undef TARGET_PROMOTE_FUNCTION_MODE
278 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
279 #undef TARGET_PROMOTE_PROTOTYPES
280 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
282 /* Target support for Anchored Addresses optimization */
283 #undef TARGET_MIN_ANCHOR_OFFSET
284 #define TARGET_MIN_ANCHOR_OFFSET 0
285 #undef TARGET_MAX_ANCHOR_OFFSET
286 #define TARGET_MAX_ANCHOR_OFFSET 7
287 #undef TARGET_ASM_OUTPUT_ANCHOR
288 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
290 #undef TARGET_FUNCTION_VALUE
291 #define TARGET_FUNCTION_VALUE picochip_function_value
293 #undef TARGET_LIBGCC_CMP_RETURN_MODE
294 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
297 #undef TARGET_LEGITIMATE_ADDRESS_P
298 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
300 #undef TARGET_LEGITIMIZE_ADDRESS
301 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
303 /* Loading and storing QImode values to and from memory
304 usually requires a scratch register. */
305 #undef TARGET_SECONDARY_RELOAD
306 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
307 #undef DONT_USE_BUILTIN_SETJMP
308 #define DONT_USE_BUILTIN_SETJMP 1
310 /* How Large Values are Returned */
312 #undef TARGET_RETURN_IN_MEMORY
313 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
315 #undef TARGET_STATIC_CHAIN
316 #define TARGET_STATIC_CHAIN picochip_static_chain
318 #undef TARGET_OPTION_OVERRIDE
319 #define TARGET_OPTION_OVERRIDE picochip_option_override
321 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
322 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
324 /* The 2nd scheduling pass option is switched off, and a machine
325 dependent reorganisation ensures that it is run later on, after the
326 second jump optimisation. */
327 #undef TARGET_DELAY_SCHED2
328 #define TARGET_DELAY_SCHED2 true
330 /* Variable tracking should be run after all optimizations which
331 change order of insns. It also needs a valid CFG. */
332 #undef TARGET_DELAY_VARTRACK
333 #define TARGET_DELAY_VARTRACK true
335 struct gcc_target targetm = TARGET_INITIALIZER;
338 /* Only return a value in memory if it is greater than 4 bytes.
339 int_size_in_bytes returns -1 for variable size objects, which go in
340 memory always. The cast to unsigned makes -1 > 8. */
343 picochip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
345 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 4);
348 /* Allow some options to be overriden. */
351 picochip_option_override (void)
353 /* If we are optimizing for stack, dont let inliner to inline functions
354 that could potentially increase stack size.*/
355 if (flag_conserve_stack)
357 maybe_set_param_value (PARAM_LARGE_STACK_FRAME, 0,
358 global_options.x_param_values,
359 global_options_set.x_param_values);
360 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH, 0,
361 global_options.x_param_values,
362 global_options_set.x_param_values);
365 /* Turn off the elimination of unused types. The elaborator
366 generates various interesting types to represent constants,
367 generics, and so on, and it is useful to retain this information
368 in the debug output. The increased size of the debug information
369 is not really an issue for us. */
370 flag_eliminate_unused_debug_types = 0;
372 /* Even if the user specifies a -fno-omit-frame-pointer on the
373 command line, we still want to go ahead and omit frame pointer
374 usages, since we dont really have a frame pointer register.
375 So, all accesses to FP need to be converted to accesses off
377 flag_omit_frame_pointer = 1;
379 /* Turning on anchored addresses by default. This is an optimization
380 that could decrease the code size by placing anchors in data and
381 accessing offsets from the anchor for file local data variables.*/
383 flag_section_anchors = 1;
385 /* The second scheduling pass runs within picochip_reorg, to avoid
386 having the second jump optimisation trash the instruction modes
387 (e.g., instructions are changed to TImode to mark the beginning
388 of cycles). Two types of DFA scheduling are possible: space and
389 speed. In both cases, instructions are reordered to avoid stalls
390 (e.g., memory loads stall for one cycle). Speed scheduling will
391 also enable VLIW instruction packing. VLIW instructions use more
392 code space, so VLIW scheduling is disabled when scheduling for
394 if (flag_schedule_insns_after_reload)
397 picochip_schedule_type = DFA_TYPE_SPACE;
400 picochip_schedule_type = DFA_TYPE_SPEED;
401 flag_delayed_branch = 0;
405 picochip_schedule_type = DFA_TYPE_NONE;
407 /* Ensure that the debug level is always at least -g2. The flow
408 analyser works at its best if it always has debug
409 information. DWARF is non-intrusive, so it makes no difference to
410 code quality if debug is always enabled. */
411 if (debug_info_level < DINFO_LEVEL_NORMAL)
413 debug_info_level = DINFO_LEVEL_NORMAL;
414 write_symbols = DWARF2_DEBUG;
417 /* Options of the form -mae=mac, and so on will be substituted by
418 the compiler driver for the appropriate byte access and multiply
419 unit ISA options. Any unrecognised AE types will end up being
420 passed to the compiler, which should reject them as invalid. */
421 if (picochip_ae_type_string != NULL)
422 error ("invalid AE type specified (%s)", picochip_ae_type_string);
424 /* Override any specific capabilities of the instruction set. These
425 take precedence over any capabilities inferred from the AE type,
426 regardless of where the options appear on the command line. */
427 if (picochip_mul_type_string == NULL)
429 /* Default to MEM-type multiply, for historical compatibility. */
430 picochip_has_mac_unit = false;
431 picochip_has_mul_unit = true;
435 picochip_has_mac_unit = false;
436 picochip_has_mul_unit = false;
438 if (strcmp (picochip_mul_type_string, "mul") == 0)
439 picochip_has_mul_unit = true;
440 else if (strcmp (picochip_mul_type_string, "mac") == 0)
441 picochip_has_mac_unit = true;
442 else if (strcmp (picochip_mul_type_string, "none") == 0)
443 { /* Do nothing. Unit types already set to false. */ }
445 error ("invalid mul type specified (%s) - expected mac, mul or none",
446 picochip_mul_type_string);
451 /* Initialise the library functions to handle arithmetic on some of
454 picochip_init_libfuncs (void)
457 set_optab_libfunc (ashr_optab, DImode, "__ashrdi3");
458 set_optab_libfunc (ashl_optab, DImode, "__ashldi3");
459 set_optab_libfunc (lshr_optab, DImode, "__lshrdi3");
461 /* 64-bit signed multiplication. */
462 set_optab_libfunc (smul_optab, DImode, "__muldi3");
464 /* Signed division */
465 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
466 set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
469 set_optab_libfunc (smod_optab, HImode, "__modhi3");
470 set_optab_libfunc (smod_optab, DImode, "__moddi3");
472 /* 32-bit count leading Zeros*/
473 set_optab_libfunc (clz_optab, SImode, "_clzsi2");
475 /* 64-bit comparison */
476 set_optab_libfunc (ucmp_optab, DImode, "__ucmpdi2");
477 set_optab_libfunc (cmp_optab, DImode, "__cmpdi2");
479 /* 64-bit addition and subtraction*/
480 set_optab_libfunc (add_optab, DImode, "_adddi3");
481 set_optab_libfunc (sub_optab, DImode, "_subdi3");
484 /* Memcpy function */
486 picochip_expand_movmemhi (rtx *operands)
488 rtx src_addr_reg, dst_addr_reg, count_reg, src_mem, dst_mem, tmp_reg;
491 src_addr_reg = gen_reg_rtx(HImode);
492 dst_addr_reg = gen_reg_rtx(HImode);
493 count_reg = gen_reg_rtx(HImode);
494 emit_insn (gen_movhi (count_reg, operands[2]));
495 emit_insn (gen_movqi (src_addr_reg, XEXP(operands[1], 0)));
496 emit_insn (gen_movqi (dst_addr_reg, XEXP(operands[0], 0)));
497 gcc_assert (GET_CODE(count_reg) == REG);
498 start_label = gen_label_rtx ();
499 emit_label (start_label);
501 /* We can specialise the code for different alignments */
502 align = INTVAL(operands[3]);
503 size = INTVAL(operands[2]);
504 gcc_assert(align >= 0 && size >= 0);
507 if (size % 4 == 0 && align % 4 == 0)
509 src_mem = gen_rtx_MEM(SImode, src_addr_reg);
510 dst_mem = gen_rtx_MEM(SImode, dst_addr_reg);
511 tmp_reg = gen_reg_rtx(SImode);
512 emit_insn (gen_movsi (tmp_reg, src_mem));
513 emit_insn (gen_movsi (dst_mem, tmp_reg));
514 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, GEN_INT(4)));
515 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, GEN_INT(4)));
516 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-4)));
517 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
518 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
520 else if (size % 2 == 0 && align % 2 == 0)
522 src_mem = gen_rtx_MEM(HImode, src_addr_reg);
523 dst_mem = gen_rtx_MEM(HImode, dst_addr_reg);
524 tmp_reg = gen_reg_rtx(HImode);
525 emit_insn (gen_movhi (tmp_reg, src_mem));
526 emit_insn (gen_movhi (dst_mem, tmp_reg));
527 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, const2_rtx));
528 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, const2_rtx));
529 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-2)));
530 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
531 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
535 src_mem = gen_rtx_MEM(QImode, src_addr_reg);
536 dst_mem = gen_rtx_MEM(QImode, dst_addr_reg);
537 tmp_reg = gen_reg_rtx(QImode);
538 emit_insn (gen_movqi (tmp_reg, src_mem));
539 emit_insn (gen_movqi (dst_mem, tmp_reg));
540 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, const1_rtx));
541 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, const1_rtx));
542 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-1)));
543 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
544 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
551 /* Return the register class for letter C. */
553 picochip_reg_class_from_letter (unsigned c)
571 pico_leaf_reg_alloc_order[] = LEAF_REG_ALLOC_ORDER;
573 pico_nonleaf_reg_alloc_order[] = REG_ALLOC_ORDER;
576 picochip_order_regs_for_local_alloc (void)
578 /* We change the order for leaf functions alone. We put r12 at
579 the end since using it will prevent us to combine stw/ldws to
580 stl/ldl and it gives no benefit. In non-leaf functions, we
581 would anyway saveup/restore r12, so it makes sense to use it.*/
583 if (leaf_function_p())
585 memcpy ((char *)reg_alloc_order, (const char *) pico_leaf_reg_alloc_order,
586 FIRST_PSEUDO_REGISTER * sizeof (int));
590 memcpy ((char *)reg_alloc_order, (const char *) pico_nonleaf_reg_alloc_order,
591 FIRST_PSEUDO_REGISTER * sizeof (int));
595 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
597 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value, unsigned c)
602 case 'I': /* 4 bits signed. */
603 return value + 8 < 16;
604 case 'J': /* 4 bits unsigned. */
606 case 'K': /* 8 bits signed. */
607 return value + 128 < 256;
608 case 'M': /* 4-bit magnitude. */
609 return abs (value) < 16;
610 case 'N': /* 10 bits signed. */
611 return value + 512 > 1024;
612 case 'O': /* 16 bits signed. */
613 return value + 32768 < 65536;
614 default: /* Unknown letter. */
619 /* Stack utility functions. */
621 picochip_return_addr_rtx(int count, rtx frameaddr ATTRIBUTE_UNUSED)
624 return gen_rtx_REG (Pmode, LINK_REGNUM);
630 /* Emit a set of parallel register expressions used to store
631 blockmode values to pass to functions. */
633 picochip_emit_register_parallel (int size_in_units, int offset)
637 rtx vector[MAX_CALL_PARAMETER_REGS];
641 /* Compute the base register, and number of required registers. */
642 base_reg = offset / 2;
643 num_regs = size_in_units / 2;
644 if (size_in_units % 2 == 1)
647 /* Emit a register for each part of the block mode value to be
648 passed in a register. */
649 for (i = 0; i < num_regs; i++)
650 vector[i] = gen_rtx_EXPR_LIST (VOIDmode,
651 gen_rtx_REG (HImode, base_reg + i),
653 result = gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (num_regs, vector));
659 /* Emit an instruction to allocate a suitable amount of space on the
660 stack, by decrementing the stack pointer. */
662 picochip_emit_stack_allocate (int adjustment)
665 rtx stack_pointer_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
667 /* Use an addition of a negative value. */
668 insn = emit_insn (gen_addhi3 (stack_pointer_reg, stack_pointer_reg,
669 GEN_INT (-adjustment)));
671 /* Make the instruction frame related. Also add an expression note,
672 so that the correct Dwarf information is generated (see documention
673 for RTX_FRAME_RELATED_P for more details). */
674 RTX_FRAME_RELATED_P (insn) = 1;
675 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
676 gen_rtx_SET (VOIDmode, stack_pointer_reg,
677 gen_rtx_PLUS (Pmode, stack_pointer_reg,
678 GEN_INT (-adjustment))));
682 /* Emit an instruction to save a register of the given mode. The
683 offset at which to save the register is given relative to the stack
686 picochip_emit_save_register (rtx reg, int offset)
688 rtx stack_pointer, address, mem, insn;
690 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
692 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
694 mem = gen_rtx_MEM (GET_MODE (reg), address);
696 insn = emit_move_insn (mem, reg);
697 RTX_FRAME_RELATED_P (insn) = 1;
699 /* For modes other than HImode, create a note explaining that
700 multiple registers have been saved. This allows the correct DWARF
701 call frame information to be generated. */
702 switch (GET_MODE (reg))
705 /* The RTL is sufficient to explain HImode register saves. */
709 /* SImode must be broken down into parallel HImode register saves. */
717 gen_rtx_PLUS (Pmode, stack_pointer,
719 gen_rtx_REG (HImode, REGNO (reg)));
720 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 0)) = 1;
723 gen_rtx_SET (HImode, gen_rtx_MEM (HImode,
728 gen_rtx_REG (HImode, REGNO (reg) + 1));
729 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 1)) = 1;
731 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
732 gen_rtx_PARALLEL (VOIDmode, p));
739 ("unexpected mode %s encountered in picochip_emit_save_register",
740 GET_MODE_NAME (GET_MODE (reg)));
745 /* Emit an instruction to restore a register of the given mode. The
746 offset from which to restore the register is given relative to the
749 picochip_emit_restore_register (rtx reg, int offset)
751 rtx stack_pointer, address, mem;
753 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
755 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
757 mem = gen_rtx_MEM (GET_MODE (reg), address);
759 emit_move_insn (reg, mem);
763 /* Check that the given byte offset is aligned to the given number of
766 picochip_is_aligned (int byte_offset, int bit_alignment)
768 int byte_alignment = bit_alignment / BITS_PER_UNIT;
769 return (byte_offset % byte_alignment) == 0;
772 /*****************************************************************************
775 * The following section contains code which controls how the stack is
778 * The stack is laid out as follows (high addresses first):
781 * Pretend arguments (ARG PTR)
785 * Outgoing arguments (SP)
787 * The (constant) offsets of the different areas must be calculated
788 * relative to the stack area immediately below, and aligned
789 * appropriately. For example, the frame offset is computed by
790 * determining the offset of the special register area, adding the
791 * size of the special register area, and then aligning the resulting
792 * offset correctly. In turn, the special register offset is computed
793 * from the general register offset, and so on. This enables the
794 * different offsets to change size and alignment, without requiring
795 * the code for other offset calculations to be rewritten.
797 * The argument pointer, and the frame pointer are eliminated wherever
798 * possible, by replacing them with a constant offset from the stack
799 * pointer. In the rare cases where constant offsets from the stack
800 * pointer cannot be computed, another register will be allocated to
801 * serve as the argument pointer, or the frame pointer.
803 * The save registers are stored at small offsets from the caller, to
804 * enable the more efficient SP-based ISA instructions to be used.
806 ****************************************************************************/
808 /* Compute the size of an argument in units. */
810 picochip_compute_arg_size (const_tree type, enum machine_mode mode)
812 int type_size_in_units = 0;
815 type_size_in_units = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
817 type_size_in_units = GET_MODE_SIZE (mode);
819 return type_size_in_units;
823 /* Determine where the next outgoing arg should be placed. */
825 picochip_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
826 const_tree type, bool named ATTRIBUTE_UNUSED)
828 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
830 int type_align_in_units = 0;
831 int type_size_in_units;
833 int offset_overflow = 0;
835 /* VOIDmode is passed when computing the second argument to a `call'
836 pattern. This can be ignored. */
837 if (mode == VOIDmode)
840 /* Compute the alignment and size of the parameter. */
841 type_align_in_units =
842 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
843 type_size_in_units = picochip_compute_arg_size (type, mode);
845 /* Compute the correct offset (i.e., ensure that the offset meets
846 the alignment requirements). */
847 offset_overflow = *cum % type_align_in_units;
848 if (offset_overflow == 0)
851 new_offset = (*cum - offset_overflow) + type_align_in_units;
855 printf ("Function arg:\n");
856 printf (" Type valid: %s\n", (type ? "yes" : "no"));
857 printf (" Cumulative Value: %d\n", *cum);
858 printf (" Mode: %s\n", GET_MODE_NAME (mode));
859 printf (" Type size: %i units\n", type_size_in_units);
860 printf (" Alignment: %i units\n", type_align_in_units);
861 printf (" New offset: %i\n", new_offset);
865 /* If the new offset is outside the register space, return. */
866 if (new_offset >= MAX_CALL_PARAMETER_REGS * 2)
869 /* If the end of the argument is outside the register space, then
870 the argument must overlap the register space. Return the first
871 available register. */
872 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
873 return gen_rtx_REG (HImode, new_offset / 2);
875 /* Create a register of the required mode to hold the parameter. */
876 reg = new_offset / 2;
891 return gen_rtx_REG (mode, reg);
895 /* Empty blockmode values can be passed as arguments (e.g.,
896 * empty structs). These require no registers
897 * whatsoever. Non-empty blockmode values are passed in a set
898 * of parallel registers. */
899 if (type_size_in_units == 0)
902 return picochip_emit_register_parallel (type_size_in_units, new_offset);
907 (0, "defaulting to stack for %s register creation",
908 GET_MODE_NAME (mode));
916 /* Determine where the next incoming function argument will
917 appear. Normally, this works in exactly the same way as
918 picochip_function_arg, except when the function in question is a
919 varadic function. In this case, the incoming arguments all appear
920 to be passed on the stack (actually, some of the arguments are
921 passed in registers, which are then pushed onto the stack by the
922 function prologue). */
924 picochip_incoming_function_arg (cumulative_args_t cum,
925 enum machine_mode mode,
926 const_tree type, bool named)
932 return picochip_function_arg (cum, mode, type, named);
936 /* Gives the alignment boundary, in bits, of an argument with the
939 picochip_function_arg_boundary (enum machine_mode mode,
940 const_tree type ATTRIBUTE_UNUSED)
945 align = STACK_BOUNDARY;
947 align = GET_MODE_ALIGNMENT (mode);
949 if (align < PARM_BOUNDARY)
950 align = PARM_BOUNDARY;
956 /* Compute partial registers. */
958 picochip_arg_partial_bytes (cumulative_args_t p_cum, enum machine_mode mode,
959 tree type, bool named ATTRIBUTE_UNUSED)
961 int type_align_in_units = 0;
962 int type_size_in_units;
964 int offset_overflow = 0;
966 unsigned cum = *get_cumulative_args (p_cum);
968 /* VOIDmode is passed when computing the second argument to a `call'
969 pattern. This can be ignored. */
970 if (mode == VOIDmode)
973 /* Compute the alignment and size of the parameter. */
974 type_align_in_units =
975 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
976 type_size_in_units = picochip_compute_arg_size (type, mode);
978 /* Compute the correct offset (i.e., ensure that the offset meets
979 the alignment requirements). */
980 offset_overflow = cum % type_align_in_units;
981 if (offset_overflow == 0)
984 new_offset = (cum - offset_overflow) + type_align_in_units;
988 printf ("Partial function arg nregs:\n");
989 printf (" Type valid: %s\n", (type ? "yes" : "no"));
990 printf (" Cumulative Value: %d\n", cum);
991 printf (" Mode: %s\n", GET_MODE_NAME (mode));
992 printf (" Type size: %i units\n", type_size_in_units);
993 printf (" Alignment: %i units\n", type_align_in_units);
994 printf (" New offset: %i\n", new_offset);
998 /* If the new offset is outside the register space, return. */
999 if (new_offset >= (MAX_CALL_PARAMETER_REGS * 2))
1002 /* If the end of the argument is outside the register space, then
1003 the argument must overlap the register space. Return the number
1004 of bytes which are passed in registers. */
1005 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
1006 return ((MAX_CALL_PARAMETER_REGS * 2) - new_offset);
1012 /* Advance the cumulative args counter CUM. */
1014 picochip_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1015 const_tree type, bool named ATTRIBUTE_UNUSED)
1017 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1018 int type_align_in_units = 0;
1019 int type_size_in_units;
1021 int offset_overflow = 0;
1023 /* VOIDmode is passed when computing the second argument to a `call'
1024 pattern. This can be ignored. */
1025 if (mode == VOIDmode)
1028 /* Compute the alignment and size of the parameter. */
1029 type_align_in_units =
1030 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
1031 type_size_in_units = picochip_compute_arg_size (type, mode);
1033 /* Compute the correct offset (i.e., ensure that the offset meets
1034 the alignment requirements). */
1035 offset_overflow = *cum % type_align_in_units;
1036 if (offset_overflow == 0)
1039 new_offset = (*cum - offset_overflow) + type_align_in_units;
1041 /* Advance past the last argument. */
1042 new_offset += type_size_in_units;
1047 /* Determine whether a register needs saving/restoring. It does if it
1048 is live in a function, and isn't a call-used register. */
1050 picochip_reg_needs_saving (int reg_num)
1052 return df_regs_ever_live_p(reg_num) && !call_used_regs[reg_num];
1055 /* Compute and return offset of the main frame. */
1057 picochip_frame_byte_offset (void)
1059 gcc_assert(picochip_is_aligned
1060 (crtl->outgoing_args_size, BITS_PER_WORD));
1062 return crtl->outgoing_args_size;
1065 /* Return the size of the main frame. */
1067 picochip_frame_size_in_bytes (void)
1069 int frame_size = get_frame_size();
1070 int stack_align = STACK_BOUNDARY/BITS_PER_UNIT;
1071 if (!picochip_is_aligned (frame_size, STACK_BOUNDARY))
1072 frame_size = frame_size + (stack_align - frame_size%stack_align);
1073 gcc_assert(picochip_is_aligned (frame_size, STACK_BOUNDARY));
1077 /* Compute and return the size (in bytes) of the register save/restore
1078 area for the current function. This only includes the general
1079 purpose registers - the special purpose stack pointer and link
1080 registers are not included in this area. */
1082 picochip_save_area_size_in_bytes (void)
1084 int num_regs_to_save = 0;
1087 /* Read through all the registers, determining which need to be saved. */
1088 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1090 if (picochip_reg_needs_saving (i))
1091 num_regs_to_save += 1;
1094 return num_regs_to_save * UNITS_PER_WORD;
1098 /* Compute and return offset of the save area base. */
1100 picochip_save_area_byte_offset (void)
1102 int base_offset = (picochip_frame_byte_offset () +
1103 picochip_frame_size_in_bytes ());
1105 gcc_assert(picochip_is_aligned (base_offset, BITS_PER_WORD));
1111 /* Compute and return offset of the special register save area. This
1112 area can be found immediately above the normal save area. It must
1113 be aligned, to allow the registers to be saved and restored as a
1116 picochip_special_save_area_byte_offset (void)
1118 int byte_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
1119 int offset = (picochip_save_area_byte_offset () +
1120 picochip_save_area_size_in_bytes ());
1122 if ((offset % byte_alignment) != 0)
1123 offset = ((offset / byte_alignment) + 1) * byte_alignment;
1129 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1131 picochip_can_eliminate_link_sp_save (void)
1133 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1134 changing during optimizations phases. So, this function returns different
1135 values when called from initial_elimination_offset and then again when it
1136 is called from prologue/epilogue generation. This means that argument
1137 accesses become wrong. This wouldnt happen only if we were not using the
1138 stack at all. The following conditions ensures that.*/
1140 return (current_function_is_leaf &&
1141 !df_regs_ever_live_p(LINK_REGNUM) &&
1142 !df_regs_ever_live_p(STACK_POINTER_REGNUM) &&
1143 (picochip_special_save_area_byte_offset() == 0) &&
1144 (crtl->args.size == 0) &&
1145 (crtl->args.pretend_args_size == 0));
1148 /* Compute the size of the special reg save area (SP and LNK). If the
1149 SP/LNK registers don't need to be saved, this area can shrink to
1152 picochip_special_save_area_size_in_bytes (void)
1156 if (picochip_can_eliminate_link_sp_save ())
1159 return 2 * UNITS_PER_WORD;
1162 /* Return the number of pretend arguments. If this function is
1163 varadic, all the incoming arguments are effectively passed on the
1164 stack. If this function has real pretend arguments (caused by a
1165 value being passed partially on the stack and partially in
1166 registers), then return the number of registers used. */
1168 picochip_pretend_arg_area_size (void)
1171 if (crtl->args.pretend_args_size != 0)
1173 gcc_assert(crtl->args.pretend_args_size % 4 == 0);
1175 return crtl->args.pretend_args_size;
1177 else if (cfun->stdarg)
1184 /* Compute and return the offset of the pretend arguments. The pretend
1185 arguments are contiguous with the incoming arguments, and must be
1186 correctly aligned. */
1188 picochip_pretend_arg_area_byte_offset (void)
1190 int base_offset = 0;
1192 base_offset = (picochip_special_save_area_byte_offset () +
1193 picochip_special_save_area_size_in_bytes ());
1195 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1196 gcc_assert(picochip_is_aligned
1197 (base_offset + picochip_pretend_arg_area_size (), STACK_BOUNDARY));
1203 /* Compute and return the offset of the incoming arguments. If a
1204 static chain is in use, this will be passed just before the other
1205 arguments. This means that the pretend argument mechanism, used in
1206 variadic functions, doesn't work properly. Thus, static chains work
1207 on their own, as do variadic functions, but not the combination of
1208 the two. This isn't really a problem. */
1210 picochip_arg_area_byte_offset (void)
1212 int base_offset = (picochip_pretend_arg_area_byte_offset () +
1213 picochip_pretend_arg_area_size ());
1215 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1216 the alignment on a 32-bit boundary must be maintained. */
1217 if (cfun->static_chain_decl != NULL)
1219 gcc_assert (!cfun->stdarg);
1223 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1230 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED, int mode)
1233 /* Special case - only one register needed. */
1234 if (GET_MODE_CLASS (mode) == MODE_CC)
1237 /* We actually do not allocate acc0 ever. But, it seems like we need to
1238 make it look like a allocatable register for the dataflow checks to work
1239 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1244 /* General case - compute how much space in terms of units. */
1245 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1250 picochip_class_max_nregs (int reg_class, int mode)
1252 int size = ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1254 if (reg_class == ACC_REGS)
1257 if (GET_MODE_CLASS (mode) == MODE_CC)
1264 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1265 argument pointer) by replacing it with a constant offset from the
1266 main stack register. */
1268 initial_elimination_offset (int from, int to)
1270 int offset_from_sp = 0;
1272 if (FRAME_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1273 offset_from_sp = picochip_frame_byte_offset ();
1274 else if (ARG_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1275 offset_from_sp = picochip_pretend_arg_area_byte_offset ();
1279 return offset_from_sp;
1283 /* Compute and return the size of the incoming argument area. */
1285 picochip_arg_area_size_in_bytes (void)
1287 return crtl->args.size;
1290 /* Determine whether the given register is valid. When the strict mode
1291 is used, only hard registers are valid, otherwise any register is
1294 picochip_legitimate_address_register (rtx x, unsigned strict)
1297 /* Sanity check - non-registers shouldn't make it here, but... */
1298 if (REG != GET_CODE (x))
1302 return REGNO (x) < FIRST_NONHARD_REGISTER;
1308 /* Determine whether the given constant is in the range required for
1309 the given base register. */
1311 picochip_const_ok_for_base (enum machine_mode mode, int regno, int offset)
1313 HOST_WIDE_INT corrected_offset;
1315 if (GET_MODE_SIZE (mode) != 0)
1317 if (GET_MODE_SIZE(mode) <= 4)
1319 /* We used to allow incorrect offsets if strict is 0. But, this would
1320 then rely on reload doing the right thing. We have had problems
1321 there before, and on > 4.3 compiler, there are no benefits. */
1322 if (offset % GET_MODE_SIZE (mode) != 0)
1324 corrected_offset = offset / GET_MODE_SIZE (mode);
1328 if (offset % 4 != 0)
1330 corrected_offset = offset / 4;
1335 /* Default to the byte offset as supplied. */
1336 corrected_offset = offset;
1339 /* The offset from the base register can be different depending upon
1340 the base register. The stack/frame/argument pointer offsets can
1341 all be greater than a simple register-based offset. Note that the
1342 frame/argument pointer registers are actually eliminations of the
1343 stack pointer, so a value which is valid for an offset to, for
1344 example, the frame pointer, might be invalid for the stack
1345 pointer once the elimination has occurred. However, there is no
1346 need to handle this special case here, as the stack offset is
1347 always checked after elimination anyway, and the generated code
1348 seems to have identical performance. */
1349 if (regno == STACK_POINTER_REGNUM ||
1350 regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1351 return picochip_const_ok_for_letter_p (corrected_offset, 'K');
1353 return picochip_const_ok_for_letter_p (corrected_offset, 'J');
1357 /* Determine whether a given rtx is a legitimate address for machine_mode
1358 MODE. STRICT is non-zero if we're being strict - any pseudo that
1359 is not a hard register must be a memory reference. */
1361 picochip_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1365 switch (GET_CODE (x))
1368 valid = picochip_legitimate_address_register (x, strict);
1373 rtx base = XEXP (x, 0);
1374 rtx offset = XEXP (x, 1);
1375 if (strict && !REGNO_OK_FOR_BASE_P (REGNO(base)))
1381 valid = (REG == GET_CODE (base) &&
1382 picochip_legitimate_address_register (base, strict) &&
1383 CONST_INT == GET_CODE (offset) &&
1384 picochip_const_ok_for_base (mode, REGNO (base),
1390 /* The user can select whether a symbol can be used as a memory
1391 address. Typically, this will decrease execution time (no
1392 register load is required first), but will increase code size
1393 (because the symbol will be used several times, rather than
1394 loaded once into a register.*/
1395 valid = TARGET_SYMBOL_AS_ADDRESS;
1400 /* A constant memory address must be a (plus (symbol_ref)
1401 (const_int)), and is only allowed when the symbols are
1402 permitted addresses. */
1403 rtx inner = XEXP (x, 0);
1405 valid = (TARGET_SYMBOL_AS_ADDRESS &&
1406 PLUS == GET_CODE (inner) &&
1407 SYMBOL_REF == GET_CODE (XEXP (inner, 0)) &&
1408 CONST_INT == GET_CODE (XEXP (inner, 1)));
1422 /* For all memory operations, picochip allows a uconst4 offset value. It
1423 is hence beneficial to turn an
1424 addr = <reg + long_const>
1429 X = reg + long_const & FFF0
1430 diff = long_const - (long_const & FFF0)
1433 X can be reused in subsequent memory operations.
1436 picochip_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1437 enum machine_mode mode)
1444 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1460 if (GET_CODE (x) == PLUS
1461 && GET_CODE (XEXP (x, 0)) == REG
1462 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1464 int high_val, low_val, offset;
1465 offset = INTVAL (XEXP (x, 1));
1466 /* Ignore cases with negative offsets. */
1469 high_val = offset & mask_val;
1470 low_val = offset - high_val;
1473 rtx temp_reg = force_reg (Pmode, gen_rtx_PLUS (Pmode, XEXP (x, 0), GEN_INT(high_val)));
1474 x = gen_rtx_PLUS (Pmode, temp_reg, GEN_INT(low_val));
1481 /* For all memory operations, picochip allows a uconst4 offset value. It
1482 is hence beneficial to turn an
1483 addr = <reg + long_const>
1488 X = reg + long_const & FFF0
1489 diff = long_const - (long_const & FFF0)
1492 X can be reused in subsequent memory operations.
1495 picochip_legitimize_reload_address (rtx *x,
1496 enum machine_mode mode,
1497 int opnum, int type,
1498 int ind_levels ATTRIBUTE_UNUSED)
1502 if (picochip_symbol_offset(*x))
1504 *x = gen_rtx_CONST(mode, *x);
1510 /* We should recognise addresses that we created.*/
1511 if (GET_CODE (*x) == PLUS
1512 && GET_CODE (XEXP (*x, 0)) == PLUS
1513 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
1514 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
1515 && GET_CODE (XEXP (*x, 1)) == CONST_INT)
1517 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
1518 BASE_REG_CLASS, GET_MODE (*x), VOIDmode, 0, 0,
1519 opnum, (enum reload_type)type);
1523 /* Depending on mode, the offsets allowed are either 16/32/64. */
1539 if (GET_CODE (*x) == PLUS
1540 && GET_CODE (XEXP (*x, 0)) == REG
1541 && GET_CODE (XEXP (*x, 1)) == CONST_INT)
1543 int high_val, low_val, offset;
1544 offset = INTVAL (XEXP (*x, 1));
1545 /* Ignore cases with negative offsets. */
1548 high_val = offset & mask_val;
1549 low_val = offset - high_val;
1552 rtx temp_reg = gen_rtx_PLUS (Pmode, XEXP (*x, 0), GEN_INT(high_val));
1553 *x = gen_rtx_PLUS (Pmode, temp_reg, GEN_INT(low_val));
1554 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
1555 BASE_REG_CLASS, GET_MODE (*x), VOIDmode, 0, 0,
1556 opnum, (enum reload_type)type);
1564 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1566 picochip_symbol_offset (rtx operand)
1569 return (PLUS == GET_CODE (operand) &&
1570 SYMBOL_REF == GET_CODE (XEXP (operand, 0)) &&
1571 CONST_INT == GET_CODE (XEXP (operand, 1)));
1575 /* Assembly output. */
1577 /* The format here should match the format used in the output of
1578 symbol_ref's elsewhere in this file. */
1580 picochip_output_label (FILE * stream, const char name[])
1582 int is_cfi_label = (strncmp (name, "picoMark_LCFI", 13) == 0);
1584 /* If VLIW scheduling is in use, any Call Frame Information labels
1585 generated inside a packet must have their output deferred until
1586 the end of the packet. */
1587 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1588 is_cfi_label && picochip_vliw_continuation)
1590 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1592 internal_error ("LCFI labels have already been deferred");
1594 strcpy (picochip_current_vliw_state.cfi_label_name[
1595 picochip_current_vliw_state.num_cfi_labels_deferred], name);
1596 picochip_current_vliw_state.num_cfi_labels_deferred++;
1600 assemble_name (stream, name);
1602 if (strncmp (name, "picoMark_", 9) == 0)
1603 fprintf (stream, "=\n");
1605 fprintf (stream, ":\n");
1611 /* The format here should match the format used in the output of
1612 symbol_ref's elsewhere in this file. */
1614 picochip_output_labelref (FILE * stream, const char name[])
1616 fprintf (stream, "_%s", name);
1620 picochip_weaken_label (FILE * stream, const char name[])
1622 fprintf (stream, ".weak ");
1623 assemble_name (stream, name);
1624 fprintf (stream, "\n");
1627 /* Return true if the given label (or label prefix) denotes a marker
1628 label which should be emitted in the form LABEL= */
1630 picochip_is_marker_prefix (const char *prefix)
1632 return (strcmp (prefix, "L") != 0 && strcmp (prefix, "LC") != 0
1633 && strcmp (prefix, "LP") != 0);
1637 picochip_output_internal_label (FILE * stream, const char *prefix,
1641 /* Emit different types of label, based upon their prefix. They
1642 are handled differently to allow the assembler to ensure that
1643 branch target labels are properly aligned, while other labels
1644 will only serve as code markers, not branch targets. Aligning
1645 labels unnecessarily can result in much code wastage. */
1646 if (picochip_is_marker_prefix (prefix))
1648 /* Special label marker. If it appears in the middle of a VLIW
1649 packet, defer it until the end of the packet. There has
1650 never been a need to handle more than one lm label at a time. */
1651 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1652 (strcmp (prefix, "LM")) == 0 && picochip_vliw_continuation)
1654 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1655 internal_error ("LM label has already been deferred");
1657 sprintf (picochip_current_vliw_state.lm_label_name,
1658 "picoMark_%s%ld", prefix, num);
1660 else if (picochip_schedule_type == DFA_TYPE_SPEED &&
1661 (strcmp (prefix, "LCFI")) == 0 && picochip_vliw_continuation)
1663 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1665 internal_error ("LCFI labels have already been deferred.");
1667 sprintf(picochip_current_vliw_state.cfi_label_name[
1668 picochip_current_vliw_state.num_cfi_labels_deferred],
1669 "picoMark_%s%ld", prefix, num);
1670 picochip_current_vliw_state.num_cfi_labels_deferred++;
1675 fprintf (stream, "_picoMark_%s%ld=\n", prefix, num);
1682 fprintf (stream, "_%s%ld:\n", prefix, num);
1688 picochip_generate_internal_label (char *str, const char *prefix, long num)
1690 /* Two types of internal label can be generated: branch target
1691 labels and code marker labels. Branch target labels must always
1692 be aligned (since code will execute at these
1693 points). Differentiate between the two by prepending markers with
1694 a unique prefix, which can later be used in output_label to
1695 figure out which label syntax to use. */
1696 if (picochip_is_marker_prefix (prefix))
1697 sprintf (str, "picoMark_%s%ld", prefix, num);
1699 sprintf (str, "%s%ld", prefix, num);
1704 picochip_asm_output_anchor (rtx symbol)
1706 fprintf (asm_out_file, ".offsetData _%s, ",XSTR (symbol, 0));
1707 fprintf (asm_out_file, "+ " HOST_WIDE_INT_PRINT_DEC"\n",SYMBOL_REF_BLOCK_OFFSET(symbol));
1711 picochip_output_aligned_common (FILE * stream, const char *name,
1712 unsigned size, unsigned alignment)
1715 fprintf (stream, ".commonData ");
1716 assemble_name (stream, name);
1717 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1718 picochip_output_global (stream, name);
1723 picochip_output_aligned_local (FILE * stream, const char *name,
1724 unsigned size, unsigned alignment)
1727 fprintf (stream, ".commonData ");
1728 assemble_name (stream, name);
1729 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1734 picochip_output_global (FILE * stream, const char *name)
1736 fprintf (stream, ".global ");
1737 assemble_name (stream, name);
1738 fprintf (stream, "\n");
1741 /* Output an assembly language string. Output as a sequence of decimal
1742 numbers, followed by the literal string to make it obvious what the
1743 numbers represent. */
1745 picochip_output_ascii (FILE * file, const char *str, int length)
1749 fprintf (file, ".ascii ");
1751 for (i = 0; i < length; ++i)
1753 fprintf (file, "16#%x# ", (char) (str[i]));
1756 fprintf (file, " ; ");
1758 for (i = 0; i < length; ++i)
1765 fprintf (file, "\\n");
1768 fprintf (file, "\\t");
1771 fprintf (file, "\\0");
1774 fprintf (file, "%c", c);
1779 fprintf (file, "\n");
1783 /* Output the beginning of an ASM file. */
1785 picochip_asm_file_start (void)
1787 default_file_start ();
1789 fprintf (asm_out_file, "// picoChip ASM file\n");
1790 fprintf (asm_out_file, "//.file \"%s\"\n", main_input_filename);
1792 fprintf (asm_out_file, "// Has byte access: %s\n",
1793 (TARGET_HAS_BYTE_ACCESS ? "Yes" : "No"));
1795 if (TARGET_HAS_MUL_UNIT)
1796 fprintf (asm_out_file, "// Has multiply: Yes (Multiply unit)\n");
1797 else if (TARGET_HAS_MAC_UNIT)
1798 fprintf (asm_out_file, "// Has multiply: Yes (Mac unit)\n");
1800 fprintf (asm_out_file, "// Has multiply: No\n");
1803 /* Output the end of an ASM file. */
1805 picochip_asm_file_end (void)
1807 /* Include a segment end to make it easy for PERL scripts to grab
1808 segments. This is now done by assembler*/
1810 fprintf (asm_out_file, "// End of picoChip ASM file\n");
1814 /* Output frame debug information to the given stream. */
1816 picochip_output_frame_debug (FILE * file)
1820 if (current_function_is_leaf)
1821 fprintf (file, "\t\t// Leaf function\n");
1823 fprintf (file, "\t\t// Non-leaf function\n");
1825 if (picochip_can_eliminate_link_sp_save ())
1826 fprintf (file, "\t\t// Link/fp save/restore can be eliminated\n");
1828 if (cfun->static_chain_decl != NULL)
1829 fprintf (file, "\t\t// Static chain in use\n");
1831 fprintf (file, "\t\t// Incoming argument size: %d bytes\n",
1832 picochip_arg_area_size_in_bytes ());
1833 fprintf (file, "\t\t// Incoming arg offset: %d\n",
1834 picochip_arg_area_byte_offset ());
1835 fprintf (file, "\t\t// Pretend arg size: %d\n",
1836 picochip_pretend_arg_area_size ());
1837 fprintf (file, "\t\t// Pretend arg offset (ARGP): %d\n",
1838 picochip_pretend_arg_area_byte_offset ());
1839 fprintf (file, "\t\t// Special reg area size: %d bytes\n",
1840 picochip_special_save_area_size_in_bytes ());
1841 fprintf (file, "\t\t// Special reg area offset: %d\n",
1842 picochip_special_save_area_byte_offset ());
1844 /* Output which registers are saved. */
1845 fprintf (file, "\t\t// Saved regs: ");
1846 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1848 if (picochip_reg_needs_saving (i))
1849 fprintf (file, "%s ", picochip_regnames[i]);
1851 fprintf (file, "\t\t\n");
1853 fprintf (file, "\t\t// Save area size: %d bytes\n",
1854 picochip_save_area_size_in_bytes ());
1855 fprintf (file, "\t\t// Save area offset: %d\n",
1856 picochip_save_area_byte_offset ());
1858 fprintf (file, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1859 fprintf (file, "\t\t// Frame offset (FP): %d\n",
1860 picochip_frame_byte_offset ());
1862 fprintf (file, "\t\t// Outgoing argument area size: %d bytes\n",
1863 crtl->outgoing_args_size);
1867 /* Output picoChip function prologue. This contains human-readable
1868 information about the function. */
1870 picochip_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1872 /* Get the function's name, as described by its RTL. This may be
1873 different from the DECL_NAME name used in the source file. The
1874 real declaration name must be used, to ensure that the prologue
1875 emits the right information for the linker. */
1878 x = DECL_RTL (current_function_decl);
1879 gcc_assert (MEM_P (x));
1881 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1882 fnname = XSTR (x, 0);
1884 /* Note that the name of the function is given in the &_%s
1885 form. This matches the name of the function as used in labels,
1886 and function calls, and enables processCallGraph to match
1887 function calls to the name of the function, as defined here. */
1888 fprintf (file, "// picoChip Function Prologue : &_%s = %d bytes\n",
1889 fnname, picochip_arg_area_byte_offset ());
1891 picochip_output_frame_debug (file);
1892 fprintf (file, "\n");
1896 /* Output picoChip function epilogue. */
1898 picochip_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1903 x = DECL_RTL (current_function_decl);
1904 gcc_assert (MEM_P (x));
1906 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1907 fnname = XSTR (x, 0);
1908 fprintf (file, "\n// picoChip Function Epilogue : %s\n\n",
1912 /* Manipulate the asm output. Some machines only execute the code when
1913 there is actually a chance of needing it (e.g., FRV doesn't execute
1914 it if the scheduling pass wasn't used). We always execute it,
1915 simple to ensure that it is exercised more often, and bugs are more
1918 This function's prime reason for existence is to insert the VLIW
1919 separators where appropriate. The separators must be inserted
1920 before any comments which appear at the end of the file.
1924 picochip_asm_output_opcode (FILE * f, const char *ptr)
1928 /* Flag to specify when a VLIW continuation has been inserted onto
1929 the line. Continuations are either inserted before any comments,
1930 or before the end of the line is reached. The flag ensures that
1931 we don't insert continuations twice (i.e., at the comment and the
1933 int continuation_inserted = 0;
1935 /* If the instruction uses multiple lines (i.e., a new line
1936 character appears in the opcode), then ensure that no attempt is
1937 made to pack it into a VLIW. */
1938 if (strchr (ptr, '\n') != NULL && picochip_vliw_continuation)
1940 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s",
1944 /* If a delay slot is pending, output the directive to the assembler
1945 before the instruction. */
1946 if (picochip_is_delay_slot_pending)
1948 picochip_is_delay_slot_pending = 0;
1952 /* Keep going for entire opcode. All substitution performed ourselves. */
1957 /* Determine whether a VLIW continuation must be inserted before
1958 any comments, or the end of the opcode. A flag is set to show
1959 that we have inserted a continuation on this line, so that we
1960 don't try to insert another continuation when the end of the
1961 opcode is reached. The only other case for a continuation
1962 might have been a newline, but these aren't allowed in
1963 conjunction with VLIW continuations (see above code). */
1964 if (picochip_vliw_continuation &&
1965 !continuation_inserted &&
1966 ((c == '/' && (*ptr == '/')) || *ptr == '\0'))
1969 continuation_inserted = 1;
1972 /* Detect an explicit VLIW separator. */
1973 if (c == '%' && (*ptr == '|'))
1978 /* Detect the need for an ALU id operand. */
1979 else if (c == '%' && (*ptr == '#'))
1981 fputc (picochip_get_vliw_alu_id (), f);
1984 printf ("Generated ALU char at %s for insn %d\n", ptr,
1985 INSN_UID (picochip_current_prescan_insn));
1987 /* Skip past unwanted # */
1990 /* Detect the need for branch delay slot. */
1991 else if (c == '%' && (*ptr == '>'))
1993 /* Only emit delay slots (NOP's, or otherwise) when delay
1994 * slot scheduling has actually been enabled, otherwise VLIW
1995 * scheduling and delay slot scheduling output combine to
1996 * produce nasty effects. */
1997 if (flag_delayed_branch)
1999 if (dbr_sequence_length () == 0)
2000 fputs ("\n=->\tNOP", f);
2002 picochip_is_delay_slot_pending = 1;
2005 /* Skip past unwanted > */
2008 /* Detect any %digit specifiers. */
2009 else if (c == '%' && (*ptr >= '0' && *ptr <= '9'))
2012 picochip_print_operand (f, recog_data.operand[c], 0);
2013 while ((c = *ptr) >= '0' && c <= '9')
2016 /* Detect any %letterdigit specifiers. */
2017 else if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2018 || (*ptr >= 'A' && *ptr <= 'Z')))
2020 int letter = *ptr++;
2027 output_asm_label (recog_data.operand[c]);
2031 output_address (recog_data.operand[c]);
2035 picochip_print_operand (f, recog_data.operand[c], letter);
2038 while ((c = *ptr) >= '0' && c <= '9')
2043 ("picochip_asm_output_opcode - can%'t output unknown operator %c",
2049 /* Reached the end of the packet. If any labels were deferred
2050 during output, emit them now. */
2051 if (!picochip_vliw_continuation)
2053 if (picochip_current_vliw_state.num_cfi_labels_deferred != 0)
2056 assemble_name (f, picochip_current_vliw_state.cfi_label_name[0]);
2058 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
2061 assemble_name (f, picochip_current_vliw_state.cfi_label_name[1]);
2066 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
2069 assemble_name (f, picochip_current_vliw_state.lm_label_name);
2074 /* Output an end-of-packet marker if requested. */
2075 if (!picochip_vliw_continuation &&
2076 TARGET_DEBUG && picochip_schedule_type == DFA_TYPE_SPEED)
2077 fprintf (f, "\n\t//-------------- End of VLIW packet -----------------");
2082 /* Function RTL expansion. */
2084 /* Expand the prologue into RTL. */
2086 picochip_expand_prologue (void)
2088 int stack_adjustment = 0;
2089 int special_save_offset = 0;
2090 int general_save_offset = 0;
2091 int reg_save_offset = 0;
2094 stack_adjustment = picochip_arg_area_byte_offset ();
2095 general_save_offset =
2096 -(stack_adjustment - picochip_save_area_byte_offset ());
2097 special_save_offset =
2098 -(stack_adjustment - picochip_special_save_area_byte_offset ());
2100 /* Save the link registers. We could try to save just one register
2101 here. This would reduce the amount of stack space required.
2102 There hasnt been a good reason to do that so far. */
2103 if (!picochip_can_eliminate_link_sp_save ())
2104 picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
2105 special_save_offset);
2107 /* Save callee-save registers. */
2108 reg_save_offset = 0;
2109 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2111 if (picochip_reg_needs_saving (i))
2114 /* If this register is an even numbered register, and the
2115 next register also needs to be saved, use a SImode save,
2116 which does both in one instruction. Note that a special
2117 check is performed to ensure that the double word aligned
2118 store is valid (e.g., it is possible that r6, r8, r9 need
2119 to be saved, in which case once r6 has been saved, the
2120 stored offset is no longer aligned, and an STL/LDL
2121 instruction becomes invalid). Alternately, we could store all
2122 aligned registers first and then save the single one(s). */
2124 picochip_reg_needs_saving (i + 1) &&
2125 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
2127 picochip_emit_save_register (gen_rtx_REG (SImode, i),
2128 general_save_offset +
2130 reg_save_offset += 2 * UNITS_PER_WORD;
2135 picochip_emit_save_register (gen_rtx_REG (HImode, i),
2136 general_save_offset +
2138 reg_save_offset += UNITS_PER_WORD;
2144 /* Emit a stack adjustment where required. */
2145 if (stack_adjustment != 0)
2146 picochip_emit_stack_allocate (stack_adjustment);
2148 /* If this function uses varadic arguments, write any unnamed
2149 registers to the stack. */
2152 int stdarg_offset = picochip_pretend_arg_area_byte_offset ();
2154 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2155 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2157 picochip_emit_save_register (gen_rtx_REG (SImode, 0), stdarg_offset);
2158 picochip_emit_save_register (gen_rtx_REG (SImode, 2),
2160 picochip_emit_save_register (gen_rtx_REG (SImode, 4),
2167 /* Expand the epilogue into RTL. */
2169 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED)
2171 int stack_adjustment = 0;
2172 int special_save_offset = 0;
2173 int general_save_offset = 0;
2174 int reg_save_offset = 0;
2176 int use_link_fp_restore_stack_adjust = 0; /* Default to using an explicit
2179 stack_adjustment = picochip_arg_area_byte_offset ();
2180 general_save_offset =
2181 -(stack_adjustment - picochip_save_area_byte_offset ());
2182 special_save_offset =
2183 -(stack_adjustment - picochip_special_save_area_byte_offset ());
2185 /* Emit a stack adjustment where required. */
2186 if (stack_adjustment != 0)
2188 /* If the link/fp is already being restored, and the offset to
2189 their save location is small enough, don't bother adjusting
2190 the stack explicitly. */
2191 if (picochip_special_save_area_byte_offset () < 512 &&
2192 !picochip_can_eliminate_link_sp_save ())
2193 use_link_fp_restore_stack_adjust = 1;
2195 /* Explicitly restore the stack. */
2196 picochip_emit_stack_allocate (-stack_adjustment);
2199 /* Restore the Link/FP registers. Only save the link register? */
2200 if (!picochip_can_eliminate_link_sp_save ())
2202 if (use_link_fp_restore_stack_adjust)
2203 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
2204 picochip_special_save_area_byte_offset
2207 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
2208 special_save_offset);
2211 /* Restore callee-save registers. */
2212 reg_save_offset = 0;
2213 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2215 if (picochip_reg_needs_saving (i))
2218 /* If this register is an even numbered register, and the
2219 next register also needs to be saved, use a SImode save,
2220 which does both in one instruction. Note that a special
2221 check is performed to ensure that the double word aligned
2222 store is valid (e.g., it is possible that r6, r8, r9 need
2223 to be saved, in which case once r6 has been saved, the
2224 stored offset is no longer aligned, and an STL/LDL
2225 instruction becomes invalid). We could store all aligned
2226 registers first, and then save the single one(s). */
2228 picochip_reg_needs_saving (i + 1) &&
2229 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
2231 picochip_emit_restore_register (gen_rtx_REG (SImode, i),
2232 general_save_offset +
2234 reg_save_offset += 2 * UNITS_PER_WORD;
2239 picochip_emit_restore_register (gen_rtx_REG (HImode, i),
2240 general_save_offset +
2242 reg_save_offset += UNITS_PER_WORD;
2248 /* Emit a return instruction, which matches a (parallel
2249 [(return) (use r12)]) */
2252 p = rtvec_alloc (2);
2254 RTVEC_ELT (p, 0) = ret_rtx;
2255 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
2256 gen_rtx_REG (Pmode, LINK_REGNUM));
2257 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
2262 /* Assembly instruction output. */
2264 /* Test whether the given branch instruction is short, or long. Short
2265 * branches are equivalent to real branches, and may be DFA
2266 * scheduled. Long branches expand to a macro which is handled by the
2267 * elaborator, and cannot be scheduled. Occasionally, the branch
2268 * shortening pass, which is run after DFA scheduling, will change the
2269 * code layout and cause the short branch to be reverted into a long
2270 * branch. Instead of having to fix this up by emitting new assembly,
2271 * the short branch is emitted anyway. There is plenty of slack in the
2272 * calculation of long and short branches (10-bit offset, but only
2273 * 9-bits used in computation), so there is enough slack for this to
2276 picochip_is_short_branch (rtx insn)
2278 int isRealShortBranch = (get_attr_length(insn) == SHORT_BRANCH_LENGTH);
2280 return (isRealShortBranch ||
2281 picochip_current_vliw_state.num_insns_in_packet > 1);
2284 /* Output a compare-and-branch instruction (matching the cbranch
2287 picochip_output_cbranch (rtx operands[])
2290 if (HImode != GET_MODE (operands[1]) ||
2291 (HImode != GET_MODE (operands[2]) &&
2292 GET_CODE (operands[2]) != CONST_INT))
2294 internal_error ("%s: at least one operand can%'t be handled",
2298 /* Use the type of comparison to output the appropriate condition
2300 switch (GET_CODE (operands[0]))
2303 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2306 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2309 /* Reverse the operand order to be GE */
2310 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2313 /* Reverse operand order of GEU. */
2314 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2317 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2320 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2323 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2326 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2329 /* Reversed operand version of LT. */
2330 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2333 /* Reverse an LTU. */
2334 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2341 /* Output a compare-and-branch instruction (matching the cbranch
2342 pattern). This function is current unused since the cbranch
2343 split is disabled. The function is kept around so we can use
2344 it when we understand how to do cbranch split safely. */
2346 picochip_output_compare (rtx operands[])
2350 if (HImode != GET_MODE (operands[1]) ||
2351 (HImode != GET_MODE (operands[2]) &&
2352 GET_CODE (operands[2]) != CONST_INT))
2354 internal_error ("%s: at least one operand can%'t be handled",
2358 code = GET_CODE (operands[0]);
2359 /* Use the type of comparison to output the appropriate condition
2364 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2367 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2370 /* Reverse the operand order to be GE */
2371 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2374 /* Reverse operand order of GEU. */
2375 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2378 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2381 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2384 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2387 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2390 /* Reversed operand version of LT. */
2391 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2394 /* Reverse an LTU. */
2395 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2402 /* Output the branch insn part of a compare-and-branch split. */
2404 picochip_output_branch (rtx operands[], rtx insn)
2407 int code = GET_CODE(operands[2]);
2408 if (picochip_is_short_branch (insn))
2410 /* Short branches can be output directly using the
2411 appropriate instruction. */
2415 return ("BNE %l0 %>");
2417 return ("BEQ %l0 %>");
2419 return ("BGE %l0 %>");
2421 return ("BHS %l0 %>");
2423 return ("BGE %l0 %>");
2425 return ("BHS %l0 %>");
2427 return ("BLT %l0 %>");
2429 return ("BLO %l0 %>");
2431 return ("BLT %l0 %>");
2433 return ("BLO %l0 %>");
2435 internal_error ("unknown short branch in %s (type %d)",
2436 __FUNCTION__, (int) INTVAL (operands[1]));
2437 return "UNKNOWN_BRANCH";
2442 /* Long branches result in the emission of a special
2443 instruction, which the assembler expands into a suitable long
2446 /* Use the type of comparison to output the appropriate condition
2451 return ("JMPNE %l0 %>");
2453 return ("JMPEQ %l0 %>");
2455 return ("JMPGE %l0 %>");
2457 return ("JMPHS %l0 %>");
2459 return ("JMPGE %l0 %>");
2461 return ("JMPHS %l0 %>");
2463 return ("JMPLT %l0 %>");
2465 return ("JMPLO %l0 %>");
2467 return ("JMPLT %l0 %>");
2469 return ("JMPLO %l0 %>");
2472 internal_error ("unknown long branch in %s (type %d)",
2473 __FUNCTION__, (int) INTVAL (operands[1]));
2474 return "UNKNOWN_BRANCH";
2480 /* Output a jump instruction. */
2482 picochip_output_jump (rtx insn)
2484 if (picochip_is_short_branch (insn))
2487 return "JMPRA %l0%>";
2491 picochip_output_put_array (int alternative, rtx operands[])
2493 /* Local output buffer. */
2496 int portArraySize = INTVAL(operands[1]);
2497 int portBaseIndex = INTVAL(operands[2]);
2499 if (alternative == 0)
2501 sprintf (buf, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2502 portArraySize, portBaseIndex);
2503 output_asm_insn (buf, operands);
2505 else if (alternative == 1)
2507 /* Constant port id. Emit a real instruction. */
2508 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2509 if (portIndex < portBaseIndex ||
2510 portIndex >= (portBaseIndex + portArraySize))
2512 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2513 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2515 sprintf(buf, "PUT R[0:1],%d", portIndex);
2516 output_asm_insn (buf, operands);
2521 /* Both alternatives output the insn directly. */
2525 const char *picochip_output_get_array (int alternative, rtx operands[])
2527 /* Local output buffer. */
2530 int portArraySize = INTVAL(operands[1]);
2531 int portBaseIndex = INTVAL(operands[2]);
2533 if (alternative == 0)
2535 sprintf (buf, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2536 portArraySize, portBaseIndex);
2537 output_asm_insn (buf, operands);
2539 else if (alternative == 1)
2541 /* Constant port id. Emit a real instruction. */
2542 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2543 if (portIndex < portBaseIndex ||
2544 portIndex >= (portBaseIndex + portArraySize))
2546 error ("GET uses port array index %d, which is out of range [%d..%d)",
2547 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2549 sprintf(buf, "GET %d,R[0:1]", portIndex);
2550 output_asm_insn (buf, operands);
2555 /* Both alternatives output the insn directly. */
2559 const char *picochip_output_testport_array (int alternative, rtx operands[])
2561 /* Local output buffer. */
2564 int portArraySize = INTVAL(operands[2]);
2565 int portBaseIndex = INTVAL(operands[3]);
2567 if (alternative == 0)
2569 sprintf (buf, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2570 portArraySize, portBaseIndex);
2571 output_asm_insn (buf, operands);
2573 else if (alternative == 1)
2575 /* Constant port id. Emit a real instruction. */
2576 int portIndex = INTVAL(operands[1]) + portBaseIndex;
2577 if (portIndex < portBaseIndex ||
2578 portIndex >= (portBaseIndex + portArraySize))
2580 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2581 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2583 sprintf(buf, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex);
2584 output_asm_insn (buf, operands);
2589 /* Both alternatives output the insn directly. */
2593 /* Output a comparison operand as a symbol (e.g., >). */
2595 picochip_print_comparison (FILE * file, rtx operand, int letter)
2600 /* Output just the comparison symbol. */
2601 switch (GET_CODE (operand))
2604 fprintf (file, "!=");
2607 fprintf (file, "==");
2610 fprintf (file, ">=");
2613 fprintf (file, ">={U}");
2616 fprintf (file, "<");
2619 fprintf (file, "<{U}");
2622 fprintf (file, "<=");
2625 fprintf (file, "<={U}");
2628 fprintf (file, ">");
2631 fprintf (file, ">{U}");
2639 /* Output the comparison formatted as operand,symbol,operand */
2640 rtx op0 = XEXP (operand, 0);
2641 rtx op1 = XEXP (operand, 1);
2643 picochip_print_operand (file, op0, 0);
2644 picochip_print_comparison (file, operand, 'i');
2645 picochip_print_operand (file, op1, 0);
2649 /* This function generates a memory address operand in the given
2650 mode. That is, if the address contains a constant offset, then the
2651 offset is divided by the required mode size to compute the
2652 mode specific offset. By default, picochip_print_operand_address calls
2653 this function using the natural mode of the operand, but special
2654 operand codes can be used to invoke the computation using an
2655 unnatural mode (e.g., compute the HI aligned address of an SI mode
2658 picochip_print_memory_address (FILE * file, rtx operand,
2659 enum machine_mode mode)
2661 rtx address = XEXP (operand, 0);
2664 if (MEM != GET_CODE (operand))
2665 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2670 printf ("picochip_print_memory_address: ");
2671 print_rtl (stdout, operand);
2675 switch (GET_CODE (address))
2679 /* Grab the address components. */
2680 rtx base = XEXP (address, 0);
2681 rtx offset = XEXP (address, 1);
2683 /* Only handle reg+const addresses */
2684 if (REG == GET_CODE (base) && CONST_INT == GET_CODE (offset))
2686 /* Sanity check. If an FP+offset address is given, ensure
2687 that the offset lies within the given frame, or a lower
2689 if (REGNO (base) == STACK_POINTER_REGNUM )
2690 gcc_assert (INTVAL (offset) <= (picochip_arg_area_byte_offset () +
2693 /* Print the base register - identical for all modes. */
2694 fprintf (file, "(");
2695 picochip_print_operand (file, base, 'r');
2696 fprintf (file, ")");
2698 /* Print the constant offset with compensation for the mode. */
2702 picochip_print_operand (file, offset, 'Q');
2706 picochip_print_operand (file, offset, 'H');
2711 picochip_print_operand (file, offset, 'S');
2715 picochip_print_operand (file, offset, 'D');
2729 picochip_print_operand (file, address, 's');
2738 inner = XEXP (address, 0);
2740 /* Sanity check - the CONST memory address must be a base+offset. */
2741 gcc_assert (PLUS == GET_CODE (inner));
2743 base = XEXP (inner, 0);
2744 offset = XEXP (inner, 1);
2746 fprintf (file, "&_%s%+d", XSTR (base, 0), XINT (offset, 0));
2752 /* Register operand. Provide a zero offset. */
2753 fprintf (file, "(");
2754 picochip_print_operand (file, address, 'r');
2755 fprintf (file, ")0");
2764 /* Output an operand. Formatting letters allow particular parts of
2765 the operand to be output. */
2767 picochip_print_operand (FILE * file, rtx operand, int letter)
2770 /* Handle special cases. */
2773 /* VLIW continuation, for explicit VLIW sequences. */
2775 fprintf (file, "\\");
2780 fputc (picochip_get_vliw_alu_id (), file);
2783 /* Delay slot specifier. */
2785 /* This should be handled in asm_output_opcode. */
2788 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2790 switch (GET_CODE (operand))
2793 fprintf (file, "AND");
2796 fprintf (file, "OR");
2799 fprintf (file, "XOR");
2802 fprintf (file, "ADD");
2805 fprintf (file, "SUB");
2812 /* Symbolic instructions (e.g., lshift becomes <<). */
2814 switch (GET_CODE (operand))
2817 fprintf (file, "&");
2820 fprintf (file, "|");
2823 fprintf (file, "^");
2826 fprintf (file, "+");
2829 fprintf (file, "-");
2832 fprintf (file, "UNKNOWN_INSN");
2837 default: /* Not a punctuation character - process as normal. */
2841 switch (GET_CODE (operand))
2847 /* Write a range of registers. */
2848 fprintf (file, "R[%d:%d]", REGNO (operand) + 1, REGNO (operand));
2852 /* The upper register of a pair is requested. */
2853 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 1]);
2857 /* The lower register of a pair is requested. Equivalent to the
2858 default, but included for completeness. */
2859 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2863 /* The 3rd register of a DI mode register. */
2864 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 2]);
2868 /* The 4th register of a DI mode register. */
2869 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 3]);
2873 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2878 /* A range of letters can be used to format integers. The
2879 letters Q/H/S are used to divide the constant by the width of
2880 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2881 to obtain the upper and lower 16-bits of a 32-bit
2882 constant. Where possible, signed numbers are used, since
2883 signed representations of numbers may be more compact (e.g.,
2884 65535 can be represented as -1, which fits into a small
2885 constant, whereas 65535 requires a large constant). */
2889 fprintf (file, "%ld", INTVAL (operand));
2893 fprintf (file, "%ld", INTVAL (operand) / 2);
2897 fprintf (file, "%ld", INTVAL (operand) / 4);
2901 fprintf (file, "%d", exact_log2 (INTVAL(operand)));
2905 fprintf (file, "%hi", (short) ((INTVAL (operand) >> 16) & 0xFFFF));
2909 fprintf (file, "%hi", (short) (INTVAL (operand) & 0xFFFF));
2913 fprintf (file, "%ld", INTVAL (operand));
2923 if (GET_MODE (operand) != SFmode)
2924 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2926 REAL_VALUE_FROM_CONST_DOUBLE (rv, operand);
2927 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
2932 fprintf (file, "%hi", (short) ((val >> 16) & 0xFFFF));
2936 fprintf (file, "%hi", (short) (val & 0xFFFF));
2944 /* Output a symbol. The output format must match that of
2945 picochip_output_label. */
2947 /* Ensure that the symbol is marked as referenced. Gcc can
2948 occasionally omit the function bodies when it believes them
2949 to be unreferenced. */
2950 if (SYMBOL_REF_DECL (operand))
2951 mark_decl_referenced (SYMBOL_REF_DECL (operand));
2952 fprintf (file, "&");
2953 assemble_name (file, XSTR (operand, 0));
2957 /* This format must match that of picochip_output_label. */
2958 fprintf (file, "&");
2959 output_asm_label (operand);
2964 rtx addr = XEXP (operand, 0);
2969 if (PLUS != GET_CODE (addr))
2970 fatal_insn ("Bad address, not (reg+disp):", addr);
2972 picochip_print_operand (file, XEXP (addr, 1), 0);
2976 /* Output a memory address in byte mode notation (i.e., the
2977 constant address (if any) is the actual byte address. */
2978 picochip_print_memory_address (file, operand, QImode);
2981 /* Output a constant offset of the given mode (i.e., divide
2982 the constant by the number of units in the mode to get the
2985 picochip_print_memory_address (file, operand, QImode);
2989 picochip_print_memory_address (file, operand, HImode);
2993 picochip_print_memory_address (file, operand, SImode);
2997 picochip_print_memory_address (file, operand, SFmode);
3001 if (PLUS != GET_CODE (addr))
3002 fatal_insn ("Bad address, not (reg+disp):", addr);
3004 picochip_print_operand (file, XEXP (addr, 0), 0);
3007 /* When the mem operand is (reg + big offset) which cannot
3008 be represented in an instruction as operand, the compiler
3009 automatically generates the instruction to put in (reg +
3010 big offset) into another register. In such cases, it
3011 returns '0' as the character. This needs to be handled
3015 if (REG != GET_CODE (addr))
3016 fatal_insn ("Bad address, not register:", addr);
3018 picochip_print_operand (file, addr, 0);
3022 fprintf (file, "Unknown mem operand - letter %c ",
3024 print_rtl (file, operand);
3032 rtx const_exp = XEXP (operand, 0);
3034 /* Handle constant offsets to symbol references. */
3035 if (PLUS == GET_CODE (const_exp) &&
3036 SYMBOL_REF == GET_CODE (XEXP (const_exp, 0)) &&
3037 CONST_INT == GET_CODE (XEXP (const_exp, 1)))
3040 picochip_print_operand (file, XEXP (const_exp, 0), 0);
3041 if (INTVAL (XEXP (const_exp, 1)) >= 0)
3042 fprintf (file, "+");
3043 /* else use the - from the operand (i.e., AP-2)) */
3045 picochip_print_operand (file, XEXP (const_exp, 1), letter);
3054 /* PLUS expressions are of the form (base + offset). Different
3055 options (analagous to those of memory PLUS expressions) are used
3056 to extract the base and offset components. */
3061 picochip_print_operand (file, XEXP (operand, 0), 0);
3065 picochip_print_operand (file, XEXP (operand, 1), 0);
3070 /* If the expression is composed entirely of constants,
3071 evaluate the result. This should only occur with the
3072 picoChip specific comms instructions, which are emitted as
3073 base+offset expressions. */
3074 if (CONST_INT == GET_CODE (XEXP (operand, 0)) &&
3075 CONST_INT == GET_CODE (XEXP (operand, 1)))
3077 HOST_WIDE_INT result = (XINT (XEXP (operand, 0), 0) +
3078 XINT (XEXP (operand, 1), 0));
3079 fprintf (file, "%ld", result);
3083 fprintf (file, "(");
3084 picochip_print_operand (file, XEXP (operand, 0), 0);
3085 fprintf (file, "+");
3086 picochip_print_operand (file, XEXP (operand, 1), 0);
3087 fprintf (file, ")");
3094 /* Comparison operations. */
3105 picochip_print_comparison (file, operand, letter);
3109 fprintf (stderr, "Unknown operand encountered in %s\n", __FUNCTION__);
3110 print_rtl (file, operand);
3117 /* Output an operand address */
3119 picochip_print_operand_address (FILE * file, rtx operand)
3122 switch (GET_CODE (operand))
3126 /* This format must match that of picochip_output_label. */
3127 assemble_name (file, XSTR (operand, 0));
3131 /* Note this format must match that of picochip_output_label. */
3132 fprintf (file, "_L%d", XINT (operand, 5));
3136 /* Pass on to a specialised memory address generator. */
3137 picochip_print_memory_address (file, operand, GET_MODE (operand));
3148 /* Scheduling functions. */
3150 /* Save some of the contents of recog_data. */
3152 picochip_save_recog_data (void)
3154 picochip_saved_which_alternative = which_alternative;
3155 memcpy (&picochip_saved_recog_data, &recog_data,
3156 sizeof (struct recog_data));
3159 /* Restore some of the contents of global variable recog_data. */
3161 picochip_restore_recog_data (void)
3163 which_alternative = picochip_saved_which_alternative;
3164 memcpy (&recog_data, &picochip_saved_recog_data,
3165 sizeof (struct recog_data));
3168 /* Ensure that no var tracking notes are emitted in the middle of a
3169 three-instruction bundle. */
3171 reorder_var_tracking_notes (void)
3177 rtx insn, next, last_insn = NULL_RTX;
3178 rtx queue = NULL_RTX;
3180 /* Iterate through the bb and find the last non-debug insn */
3181 for (insn = BB_HEAD (bb); insn != NEXT_INSN(BB_END (bb)); insn = NEXT_INSN(insn))
3183 if (NONDEBUG_INSN_P(insn))
3187 /* In all normal cases, queue up notes and emit them just before a TImode
3188 instruction. For the last instruction, emit the queued notes just after
3189 the last instruction. */
3190 for (insn = BB_HEAD (bb); insn != NEXT_INSN(BB_END (bb)); insn = next)
3192 next = NEXT_INSN (insn);
3194 if (insn == last_insn)
3198 rtx next_queue = PREV_INSN (queue);
3199 PREV_INSN (NEXT_INSN(insn)) = queue;
3200 NEXT_INSN(queue) = NEXT_INSN(insn);
3201 PREV_INSN(queue) = insn;
3202 NEXT_INSN(insn) = queue;
3205 /* There is no more to do for this bb. break*/
3208 else if (NONDEBUG_INSN_P (insn))
3210 /* Emit queued up notes before the first instruction of a bundle. */
3211 if (GET_MODE (insn) == TImode)
3215 rtx next_queue = PREV_INSN (queue);
3216 NEXT_INSN (PREV_INSN(insn)) = queue;
3217 PREV_INSN (queue) = PREV_INSN(insn);
3218 PREV_INSN (insn) = queue;
3219 NEXT_INSN (queue) = insn;
3224 else if (NOTE_P (insn))
3226 rtx prev = PREV_INSN (insn);
3227 PREV_INSN (next) = prev;
3228 NEXT_INSN (prev) = next;
3229 /* Ignore call_arg notes. They are expected to be just after the
3230 call insn. If the call is start of a long VLIW, labels are
3231 emitted in the middle of a VLIW, which our assembler can not
3233 if (NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION)
3235 PREV_INSN (insn) = queue;
3240 /* Make sure we are not dropping debug instructions.*/
3241 gcc_assert (queue == NULL_RTX);
3245 /* Perform machine dependent operations on the rtl chain INSNS. */
3247 picochip_reorg (void)
3249 rtx insn, insn1, vliw_start = NULL_RTX;
3250 int vliw_insn_location = 0;
3252 /* We are freeing block_for_insn in the toplev to keep compatibility
3253 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3254 compute_bb_for_insn ();
3259 if (picochip_schedule_type != DFA_TYPE_NONE)
3261 timevar_push (TV_SCHED2);
3263 /* Process the instruction list, computing the sizes of each
3264 instruction, and consequently branch distances. This can
3265 result in some branches becoming short enough to be treated
3266 as a real branch instruction, rather than an assembly branch
3267 macro which may expand into multiple instructions. The
3268 benefit of shortening branches is that real branch
3269 instructions can be properly DFA scheduled, whereas macro
3271 shorten_branches (get_insns ());
3273 /* Do control and data sched analysis again,
3274 and write some more of the results to dump file. */
3280 timevar_pop (TV_SCHED2);
3284 if (picochip_schedule_type == DFA_TYPE_SPEED)
3286 /* Whenever a VLIW packet is generated, all instructions in
3287 that packet must appear to come from the same source
3288 location. The following code finds all the VLIW packets,
3289 and tags their instructions with the location of the first
3290 instruction from the packet. Clearly this will result in
3291 strange behaviour when debugging the code, but since
3292 debugging and optimisation are being used in conjunction,
3293 strange behaviour is certain to occur anyway. */
3294 /* Slight bit of change. If the vliw set contains a branch
3295 or call instruction, we pick its location.*/
3296 for (insn = get_insns (); insn; insn = next_real_insn (insn))
3299 /* If this is the first instruction in the VLIW packet,
3300 extract its location. */
3301 if (GET_MODE (insn) == TImode)
3304 vliw_insn_location = INSN_LOCATOR (insn);
3306 if (JUMP_P (insn) || CALL_P(insn))
3308 vliw_insn_location = INSN_LOCATOR (insn);
3309 for (insn1 = vliw_start; insn1 != insn ; insn1 = next_real_insn (insn1))
3310 INSN_LOCATOR (insn1) = vliw_insn_location;
3312 /* Tag subsequent instructions with the same location. */
3313 INSN_LOCATOR (insn) = vliw_insn_location;
3319 /* Locate the note marking the end of the function's prologue. If
3320 the note appears in the middle of a VLIW packet, move the note to
3321 the end. This avoids unpleasant consequences such as trying to
3322 emit prologue markers (e.g., .loc/.file directives) in the middle
3324 if (picochip_schedule_type == DFA_TYPE_SPEED)
3326 rtx prologue_end_note = NULL;
3327 rtx last_insn_in_packet = NULL;
3329 for (insn = get_insns (); insn; insn = next_insn (insn))
3331 /* The prologue end must be moved to the end of the VLIW packet. */
3332 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
3334 prologue_end_note = insn;
3339 /* Find the last instruction in this packet. */
3340 for (insn = prologue_end_note; insn; insn = next_real_insn (insn))
3342 if (GET_MODE (insn) == TImode)
3345 last_insn_in_packet = insn;
3348 if (last_insn_in_packet != NULL)
3351 = emit_note_after ((enum insn_note) NOTE_KIND (prologue_end_note),
3352 last_insn_in_packet);
3353 memcpy(&NOTE_DATA (tmp_note), &NOTE_DATA(prologue_end_note), sizeof(NOTE_DATA(prologue_end_note)));
3354 delete_insn (prologue_end_note);
3358 if (flag_var_tracking)
3360 timevar_push (TV_VAR_TRACKING);
3361 variable_tracking_main ();
3362 /* We also have to deal with variable tracking notes in the
3363 middle of VLIW packets. */
3364 reorder_var_tracking_notes();
3365 timevar_pop (TV_VAR_TRACKING);
3369 /* Return the ALU character identifier for the current
3370 instruction. This will be 0 or 1. */
3372 picochip_get_vliw_alu_id (void)
3376 /* Always use ALU 0 if VLIW scheduling is disabled. */
3377 if (picochip_schedule_type != DFA_TYPE_SPEED)
3380 /* Get the attribute type of the instruction. Note that this can
3381 ruin the contents of recog_data, so save/restore around the
3383 picochip_save_recog_data ();
3384 attr_type = get_attr_type (picochip_current_prescan_insn);
3385 picochip_restore_recog_data ();
3387 if (picochip_current_vliw_state.contains_pico_alu_insn)
3390 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3391 else it must be the other ALU (either basic or nonCc)
3392 instruction which goes into 1. */
3393 if (attr_type == TYPE_PICOALU)
3399 else if (picochip_current_vliw_state.contains_non_cc_alu_insn)
3401 /* Is this the non CC instruction? If it is, then stuff it into
3402 ALU 1, else it must be a picoAlu or basicAlu, in which case
3403 it goes into ALU 0. */
3404 if (attr_type == TYPE_NONCCALU)
3411 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3412 whether an ALU instruction has already been scheduled in this
3414 switch (picochip_current_vliw_state.num_alu_insns_so_far)
3417 picochip_current_vliw_state.num_alu_insns_so_far++;
3421 picochip_current_vliw_state.num_alu_insns_so_far++;
3425 internal_error ("too many ALU instructions emitted (%d)",
3426 picochip_current_vliw_state.num_alu_insns_so_far);
3433 /* Reset any information about the current VLIW packing status. */
3435 picochip_reset_vliw (rtx insn)
3437 rtx local_insn = insn;
3439 /* Nothing to do if VLIW scheduling isn't being used. */
3440 if (picochip_schedule_type != DFA_TYPE_SPEED)
3444 printf ("%s on insn %d\n", __FUNCTION__, INSN_UID (insn));
3447 picochip_current_vliw_state.contains_pico_alu_insn = 0;
3448 picochip_current_vliw_state.contains_non_cc_alu_insn = 0;
3449 picochip_current_vliw_state.num_alu_insns_so_far = 0;
3450 picochip_current_vliw_state.num_cfi_labels_deferred = 0;
3451 picochip_current_vliw_state.lm_label_name[0] = 0;
3452 picochip_current_vliw_state.num_insns_in_packet = 0;
3454 /* Read through the VLIW packet, classifying the instructions where
3459 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3461 local_insn = NEXT_INSN (local_insn);
3464 else if (!INSN_P (local_insn))
3468 /* It is an instruction, but is it ours? */
3469 if (INSN_CODE (local_insn) != -1)
3473 picochip_current_vliw_state.num_insns_in_packet += 1;
3475 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3476 get_attr_type function can overwrite the values in
3477 the recog_data global, hence this is saved and
3478 restored around the call. Not doing so results in
3479 asm_output_opcode being called with a different
3480 instruction to final_prescan_insn, which is fatal. */
3481 picochip_save_recog_data ();
3482 attr_type = get_attr_type (local_insn);
3483 picochip_restore_recog_data ();
3485 if (attr_type == TYPE_PICOALU)
3486 picochip_current_vliw_state.contains_pico_alu_insn = 1;
3487 if (attr_type == TYPE_NONCCALU)
3488 picochip_current_vliw_state.contains_non_cc_alu_insn = 1;
3493 /* Get the next instruction. */
3494 local_insn = NEXT_INSN (local_insn);
3496 /* Keep going while the next instruction is part of the same
3497 VLIW packet (i.e., its a valid instruction and doesn't mark
3498 the start of a new VLIW packet. */
3500 while (local_insn &&
3501 (GET_MODE (local_insn) != TImode) && (INSN_CODE (local_insn) != -1));
3506 picochip_sched_reorder (FILE * file, int verbose,
3507 rtx * ready ATTRIBUTE_UNUSED,
3508 int *n_readyp ATTRIBUTE_UNUSED, int clock)
3512 fprintf (file, ";;\tClock %d\n", clock);
3514 return picochip_sched_issue_rate ();
3519 picochip_sched_lookahead (void)
3521 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3527 picochip_sched_issue_rate (void)
3532 /* Adjust the scheduling cost between the two given instructions,
3533 which have the given dependency. */
3535 picochip_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3540 printf ("Sched Adjust Cost: %d->%d is %d\n",
3541 INSN_UID (insn), INSN_UID (dep_insn), cost);
3543 printf (" Dependency type:");
3544 switch (REG_NOTE_KIND (link))
3552 case REG_DEP_OUTPUT:
3553 printf ("OUTPUT\n");
3556 printf ("Unknown (%d)\n", REG_NOTE_KIND (link));
3560 /* Anti-dependencies are used to enforce the ordering between a
3561 * branch, and any subsequent instructions. For example:
3566 * The ADD instruction must execute after the branch, and this is
3567 * enforced using an anti-dependency. Unfortunately, VLIW machines
3568 * are happy to execute anti-dependent instructions in the same
3569 * cycle, which then results in a schedule like the following being
3572 * BNE someLabel \ ADD.0 r0,r1,r2
3574 * The instruction which would normally be conditionally executed
3575 * depending upon the outcome of the branch, is now unconditionally
3576 * executed every time. To prevent this happening, any
3577 * anti-dependencies between a branch and another instruction are
3578 * promoted to become real dependencies.
3580 if ((JUMP_P (dep_insn) || CALL_P(dep_insn)) && REG_NOTE_KIND (link) == REG_DEP_ANTI)
3584 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3585 INSN_UID (insn), INSN_UID (dep_insn));
3594 /* Return the minimum of the two values */
3596 minimum (int a, int b)
3602 /* I dont expect to get to this function with a==b.*/
3607 /* This function checks if the memory of the two stores are just off by 2 bytes.
3608 It returns the lower memory operand's index.*/
3611 memory_just_off (rtx opnd1, rtx opnd2)
3613 int offset1 = 0, offset2 = 0;
3616 if (GET_CODE(XEXP(opnd1, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1, 0),1)) == CONST_INT)
3618 offset1 = INTVAL(XEXP(XEXP(opnd1, 0), 1));
3619 reg1 = REGNO(XEXP(XEXP(opnd1, 0), 0));
3623 reg1 = REGNO(XEXP(opnd1, 0));
3625 if (GET_CODE(XEXP(opnd2, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2, 0), 1)) == CONST_INT)
3627 offset2 = INTVAL(XEXP(XEXP(opnd2, 0), 1));
3628 reg2 = REGNO(XEXP(XEXP(opnd2, 0), 0));
3632 reg2 = REGNO(XEXP(opnd2, 0));
3635 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3636 should be 4 byte aligned. We can currently guarentee that only if the base
3637 address is FP(R13) and the offset is aligned. */
3639 if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
3640 return (minimum(offset1, offset2) == offset1) ? 1:2;
3646 registers_just_off (rtx opnd1, rtx opnd2)
3649 reg1 = REGNO(opnd1);
3650 reg2 = REGNO(opnd2);
3651 if (abs(reg1-reg2) == 1 && minimum(reg1, reg2) % 2 == 0)
3652 return (minimum(reg1, reg2) == reg1)?1:2;
3656 /* Check to see if the two LDWs can be peepholed together into a LDL
3657 They can be if the registers getting loaded into are contiguous
3658 and the memory addresses are contiguous as well.
3662 can be merged together into
3666 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3667 aligned address. Only FP can be assumed to be 4 byte aligned.
3668 2. The progression of addresses and the register numbers should
3669 be similar. For eg., if you swap r2 and r3 in the above instructions,
3670 the resultant pair cannot be merged.
3674 ok_to_peephole_ldw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3676 int memtest=0,regtest=0;
3677 regtest = registers_just_off(opnd1,opnd3);
3681 memtest = memory_just_off(opnd0,opnd2);
3685 if (regtest == memtest)
3692 /* Similar to LDW peephole */
3694 ok_to_peephole_stw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3696 int memtest=0,regtest=0;
3697 regtest = registers_just_off(opnd1,opnd3);
3701 memtest = memory_just_off(opnd0,opnd2);
3705 if (regtest == memtest)
3713 /* Generate a SImode register with the register number that is the smaller of the two */
3715 gen_min_reg(rtx opnd1,rtx opnd2)
3717 return gen_rtx_REG (SImode, minimum(REGNO(opnd1),REGNO(opnd2)));
3720 /* Generate a SImode memory with the address that is the smaller of the two */
3722 gen_SImode_mem(rtx opnd1,rtx opnd2)
3724 int offset1=0,offset2=0;
3727 if (GET_CODE(XEXP(opnd1,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1,0),1)) == CONST_INT)
3729 offset1 = INTVAL(XEXP(XEXP(opnd1,0),1));
3730 reg = XEXP(XEXP(opnd1,0),0);
3734 reg = XEXP(opnd1,0);
3736 if (GET_CODE(XEXP(opnd2,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2,0),1)) == CONST_INT)
3738 offset2 = INTVAL(XEXP(XEXP(opnd2,0),1));
3740 address = gen_rtx_PLUS (HImode, reg, GEN_INT(minimum(offset1,offset2)));
3741 return gen_rtx_MEM(SImode,address);
3745 picochip_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
3746 int opno ATTRIBUTE_UNUSED, int* total, bool speed)
3753 /* Need to penalize immediates that need to be encoded as long constants.*/
3754 if (code == CONST_INT && !(INTVAL (x) >= 0 && INTVAL (x) < 16))
3756 *total = COSTS_N_INSNS(1);
3764 *total = COSTS_N_INSNS (outer_code != MEM);
3769 /* if_then_else come out of cbranch instructions. It will get split into
3770 a condition code generating subtraction and a branch */
3771 *total = COSTS_N_INSNS (2);
3778 if (GET_MODE(x) == SImode)
3779 *total = COSTS_N_INSNS (2);
3780 if (GET_MODE(x) == DImode)
3781 *total = COSTS_N_INSNS (4);
3785 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3786 if (GET_MODE(x) == QImode && !TARGET_HAS_BYTE_ACCESS)
3787 *total = COSTS_N_INSNS (10);
3789 /* 64-bit accesses have to be done through 2 32-bit access */
3790 if (GET_MODE(x) == DImode)
3791 *total = COSTS_N_INSNS (2);
3797 /* SImode shifts are expensive */
3798 if (GET_MODE(x) == SImode)
3799 *total = COSTS_N_INSNS (10);
3801 /* Register shift by constant is cheap. */
3802 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3803 && GET_CODE(XEXP(x, 0)) == REG
3804 && GET_CODE(XEXP(x, 1)) == CONST_INT)
3805 *total = COSTS_N_INSNS (1);
3807 *total = COSTS_N_INSNS (4);
3814 /* Divisions are more expensive than the default 7*/
3815 if (GET_MODE(x) == SImode)
3816 *total = COSTS_N_INSNS (20);
3818 *total = COSTS_N_INSNS (12);
3823 /* Look for the simple cases of multiplying register*register or
3824 register*constant. */
3825 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3826 && ((GET_CODE(XEXP(x, 0)) == REG
3827 && (GET_CODE(XEXP(x, 1)) == REG || GET_CODE(XEXP(x,1)) == CONST_INT))
3828 || (GET_CODE(XEXP(x, 0)) == ZERO_EXTEND
3829 && GET_CODE(XEXP(XEXP(x, 0),0)) == REG
3830 && GET_CODE(XEXP(x, 1)) == ZERO_EXTEND
3831 && GET_CODE(XEXP(XEXP(x, 1),0)) == REG)))
3834 /* When optimising for size, multiplication by constant
3835 should be discouraged slightly over multiplication by a
3837 if (picochip_has_mac_unit)
3839 /* Single cycle multiplication, but the result must be
3840 loaded back into a general register afterwards. */
3841 *total = COSTS_N_INSNS(2);
3844 else if (picochip_has_mul_unit)
3846 /* Single cycle multiplication. */
3847 *total = COSTS_N_INSNS(1);
3850 /* Else no multiply available. Use default cost. */
3860 if (localTotal != 0)
3862 *total = localTotal;
3873 picochip_final_prescan_insn (rtx insn, rtx * opvec ATTRIBUTE_UNUSED,
3874 int num_operands ATTRIBUTE_UNUSED)
3878 picochip_current_prescan_insn = insn;
3881 printf ("Final prescan on INSN %d with mode %s\n",
3882 INSN_UID (insn), GET_MODE_NAME (GET_MODE (insn)));
3884 /* If this is the start of a new instruction cycle, or no scheduling
3885 is used, then reset the VLIW status. */
3886 if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
3887 picochip_reset_vliw (insn);
3889 /* No VLIW scheduling occured, so don't go any further. */
3890 if (picochip_schedule_type != DFA_TYPE_SPEED)
3893 /* Look for the next printable instruction. This loop terminates on
3894 any recognisable instruction, and on any unrecognisable
3895 instruction with TImode. */
3897 for (local_insn = NEXT_INSN (local_insn); local_insn;
3898 local_insn = NEXT_INSN (local_insn))
3900 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3902 else if (!INSN_P (local_insn))
3904 else if (GET_MODE (local_insn) == TImode
3905 || INSN_CODE (local_insn) != -1)
3909 /* Set the continuation flag if the next instruction can be packed
3910 with the current instruction (i.e., the next instruction is
3911 valid, and isn't the start of a new cycle). */
3912 picochip_vliw_continuation = (local_insn && NONDEBUG_INSN_P (local_insn) &&
3913 (GET_MODE (local_insn) != TImode));
3917 /* Builtin functions. */
3918 /* Given a builtin function taking 2 operands (i.e., target + source),
3919 emit the RTL for the underlying instruction. */
3921 picochip_expand_builtin_2op (enum insn_code icode, tree call, rtx target)
3925 enum machine_mode tmode, mode0;
3927 /* Grab the incoming argument and emit its RTL. */
3928 arg0 = CALL_EXPR_ARG (call, 0);
3929 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3931 /* Determine the modes of the instruction operands. */
3932 tmode = insn_data[icode].operand[0].mode;
3933 mode0 = insn_data[icode].operand[1].mode;
3935 /* Ensure that the incoming argument RTL is in a register of the
3937 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3938 op0 = copy_to_mode_reg (mode0, op0);
3940 /* If there isn't a suitable target, emit a target register. */
3942 || GET_MODE (target) != tmode
3943 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3944 target = gen_reg_rtx (tmode);
3946 /* Emit and return the new instruction. */
3947 pat = GEN_FCN (icode) (target, op0);
3956 /* Given a builtin function taking 3 operands (i.e., target + two
3957 source), emit the RTL for the underlying instruction. */
3959 picochip_expand_builtin_3op (enum insn_code icode, tree call, rtx target)
3963 enum machine_mode tmode, mode0, mode1;
3965 /* Grab the function's arguments. */
3966 arg0 = CALL_EXPR_ARG (call, 0);
3967 arg1 = CALL_EXPR_ARG (call, 1);
3969 /* Emit rtl sequences for the function arguments. */
3970 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3971 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3973 /* Get the mode's of each of the instruction operands. */
3974 tmode = insn_data[icode].operand[0].mode;
3975 mode0 = insn_data[icode].operand[1].mode;
3976 mode1 = insn_data[icode].operand[2].mode;
3978 /* Ensure that each of the function argument rtl sequences are in a
3979 register of the correct mode. */
3980 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3981 op0 = copy_to_mode_reg (mode0, op0);
3982 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
3983 op1 = copy_to_mode_reg (mode1, op1);
3985 /* If no target has been given, create a register to use as the target. */
3987 || GET_MODE (target) != tmode
3988 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3989 target = gen_reg_rtx (tmode);
3991 /* Emit and return the new instruction. */
3992 pat = GEN_FCN (icode) (target, op0, op1);
4001 /* Expand a builtin function which takes two arguments, and returns a void. */
4003 picochip_expand_builtin_2opvoid (enum insn_code icode, tree call)
4007 enum machine_mode mode0, mode1;
4009 /* Grab the function's arguments. */
4010 arg0 = CALL_EXPR_ARG (call, 0);
4011 arg1 = CALL_EXPR_ARG (call, 1);
4013 /* Emit rtl sequences for the function arguments. */
4014 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4015 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4017 /* Get the mode's of each of the instruction operands. */
4018 mode0 = insn_data[icode].operand[0].mode;
4019 mode1 = insn_data[icode].operand[1].mode;
4021 /* Ensure that each of the function argument rtl sequences are in a
4022 register of the correct mode. */
4023 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
4024 op0 = copy_to_mode_reg (mode0, op0);
4025 if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
4026 op1 = copy_to_mode_reg (mode1, op1);
4028 /* Emit and return the new instruction. */
4029 pat = GEN_FCN (icode) (op0, op1);
4038 /* Expand an array get into the corresponding RTL. */
4040 picochip_expand_array_get (tree call, rtx target)
4042 tree arg0, arg1, arg2;
4043 rtx op0, op1, op2, pat;
4045 /* Grab the function's arguments. */
4046 arg0 = CALL_EXPR_ARG (call, 0);
4047 arg1 = CALL_EXPR_ARG (call, 1);
4048 arg2 = CALL_EXPR_ARG (call, 2) ;
4050 /* Emit rtl sequences for the function arguments. */
4051 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4052 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4053 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4055 /* The second and third operands must be constant. Nothing else will
4057 if (CONST_INT != GET_CODE (op1))
4058 internal_error ("%s: Second source operand is not a constant",
4060 if (CONST_INT != GET_CODE (op2))
4061 internal_error ("%s: Third source operand is not a constant",
4064 /* If no target has been given, create a register to use as the target. */
4065 if (target == 0 || GET_MODE (target) != SImode)
4066 target = gen_reg_rtx (SImode);
4068 /* The first operand must be a HImode register or a constant. If it
4069 isn't, force it into a HImode register. */
4070 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
4071 op0 = copy_to_mode_reg (HImode, op0);
4074 /* Emit and return the new instruction. */
4075 pat = gen_commsArrayGet (target, op0, op1, op2);
4082 /* Expand an array put into the corresponding RTL. */
4084 picochip_expand_array_put (tree call, rtx target)
4086 tree arg0, arg1, arg2, arg3;
4087 rtx op0, op1, op2, op3, pat;
4089 /* Grab the function's arguments. */
4090 arg0 = CALL_EXPR_ARG (call, 0);
4091 arg1 = CALL_EXPR_ARG (call, 1);
4092 arg2 = CALL_EXPR_ARG (call, 2);
4093 arg3 = CALL_EXPR_ARG (call, 3);
4095 /* Emit rtl sequences for the function arguments. */
4096 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4097 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4098 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4099 op3 = expand_expr (arg3, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4101 /* The first operand must be an SImode register. */
4102 if (GET_MODE (op0) != SImode || REG != GET_CODE (op0))
4103 op0 = copy_to_mode_reg (SImode, op0);
4105 /* The second (index) operand must be a HImode register, or a
4106 constant. If it isn't, force it into a HImode register. */
4107 if (GET_MODE (op1) != HImode || REG != GET_CODE (op1))
4108 op1 = copy_to_mode_reg (HImode, op1);
4110 /* The remaining operands must be constant. Nothing else will do. */
4111 if (CONST_INT != GET_CODE (op2))
4112 internal_error ("%s: Third source operand is not a constant",
4114 if (CONST_INT != GET_CODE (op3))
4115 internal_error ("%s: Fourth source operand is not a constant",
4118 /* Emit and return the new instruction. */
4119 pat = gen_commsArrayPut (op0, op1, op2, op3);
4126 /* Expand an array testport into the corresponding RTL. */
4128 picochip_expand_array_testport (tree call, rtx target)
4130 tree arg0, arg1, arg2;
4131 rtx op0, op1, op2, pat;
4133 /* Grab the function's arguments. */
4134 arg0 = CALL_EXPR_ARG (call, 0);
4135 arg1 = CALL_EXPR_ARG (call, 1);
4136 arg2 = CALL_EXPR_ARG (call, 2);
4138 /* Emit rtl sequences for the function arguments. */
4139 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4140 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4141 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4143 /* The first operand must be a HImode register, or a constant. If it
4144 isn't, force it into a HImode register. */
4145 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
4146 op0 = copy_to_mode_reg (HImode, op0);
4148 /* The second and third operands must be constant. Nothing else will
4150 if (CONST_INT != GET_CODE (op1))
4151 internal_error ("%s: Second source operand is not a constant",
4153 if (CONST_INT != GET_CODE (op2))
4154 internal_error ("%s: Third source operand is not a constant",
4157 /* If no target has been given, create a HImode register to use as
4159 if (target == 0 || GET_MODE (target) != HImode)
4160 target = gen_reg_rtx (HImode);
4162 /* Emit and return the new instruction. */
4163 pat = gen_commsArrayTestPort (target, op0, op1, op2);
4170 /* Generate a unique HALT instruction by giving the instruction a
4171 unique integer. This integer makes no difference to the assembly
4172 output (other than a comment indicating the supplied id), but the
4173 presence of the unique integer prevents the compiler from combining
4174 several different halt instructions into one instruction. This
4175 means that each use of the halt instruction is unique, which in
4176 turn means that assertions work as expected. */
4178 picochip_generate_halt (void)
4180 static int currentId = 0;
4182 rtx id = GEN_INT (currentId);
4186 emit_insn (gen_halt (id));
4188 /* A barrier is inserted to prevent the compiler from thinking that
4189 it has to continue execution after the HALT.*/
4192 insns = get_insns();
4199 /* Initialise the builtin functions. Start by initialising
4200 descriptions of different types of functions (e.g., void fn(int),
4201 int fn(void)), and then use these to define the builtins. */
4203 picochip_init_builtins (void)
4207 tree int_ftype_int, int_ftype_int_int;
4208 tree long_ftype_int, long_ftype_int_int_int;
4209 tree void_ftype_int_long, int_ftype_int_int_int,
4210 void_ftype_long_int_int_int;
4211 tree void_ftype_void, unsigned_ftype_unsigned;
4213 /* void func (void) */
4214 void_ftype_void = build_function_type_list (void_type_node, NULL_TREE);
4216 /* int func (int) */
4217 int_ftype_int = build_function_type_list (integer_type_node,
4218 integer_type_node, NULL_TREE);
4220 /* unsigned int func (unsigned int) */
4221 unsigned_ftype_unsigned
4222 = build_function_type_list (unsigned_type_node,
4223 unsigned_type_node, NULL_TREE);
4225 /* int func(int, int) */
4227 = build_function_type_list (integer_type_node,
4228 integer_type_node, integer_type_node,
4231 /* long func(int) */
4232 long_ftype_int = build_function_type_list (long_integer_type_node,
4233 integer_type_node, NULL_TREE);
4235 /* long func(int, int, int) */
4236 long_ftype_int_int_int
4237 = build_function_type_list (long_integer_type_node,
4238 integer_type_node, integer_type_node,
4239 integer_type_node, NULL_TREE);
4241 /* int func(int, int, int) */
4242 int_ftype_int_int_int
4243 = build_function_type_list (integer_type_node,
4244 integer_type_node, integer_type_node,
4245 integer_type_node, NULL_TREE);
4247 /* void func(int, long) */
4249 = build_function_type_list (void_type_node,
4250 integer_type_node, long_integer_type_node,
4253 /* void func(long, int, int, int) */
4254 void_ftype_long_int_int_int
4255 = build_function_type_list (void_type_node,
4256 long_integer_type_node, integer_type_node,
4257 integer_type_node, integer_type_node,
4260 /* Initialise the sign-bit-count function. */
4261 add_builtin_function ("__builtin_sbc", int_ftype_int,
4262 PICOCHIP_BUILTIN_SBC, BUILT_IN_MD, NULL,
4264 add_builtin_function ("picoSbc", int_ftype_int, PICOCHIP_BUILTIN_SBC,
4265 BUILT_IN_MD, NULL, NULL_TREE);
4267 /* Initialise the bit reverse function. */
4268 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned,
4269 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4271 add_builtin_function ("picoBrev", unsigned_ftype_unsigned,
4272 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4275 /* Initialise the byte swap function. */
4276 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned,
4277 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4279 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned,
4280 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4283 /* Initialise the ASRI function (note that while this can be coded
4284 using a signed shift in C, extra scratch registers are required,
4285 which we avoid by having a direct builtin to map to the
4287 add_builtin_function ("__builtin_asri", int_ftype_int_int,
4288 PICOCHIP_BUILTIN_ASRI, BUILT_IN_MD, NULL,
4291 /* Initialise saturating addition. */
4292 add_builtin_function ("__builtin_adds", int_ftype_int_int,
4293 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4295 add_builtin_function ("picoAdds", int_ftype_int_int,
4296 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4299 /* Initialise saturating subtraction. */
4300 add_builtin_function ("__builtin_subs", int_ftype_int_int,
4301 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4303 add_builtin_function ("picoSubs", int_ftype_int_int,
4304 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4307 /* Scalar comms builtins. */
4308 add_builtin_function ("__builtin_get", long_ftype_int,
4309 PICOCHIP_BUILTIN_GET, BUILT_IN_MD, NULL,
4311 add_builtin_function ("__builtin_put", void_ftype_int_long,
4312 PICOCHIP_BUILTIN_PUT, BUILT_IN_MD, NULL,
4314 add_builtin_function ("__builtin_testport", int_ftype_int,
4315 PICOCHIP_BUILTIN_TESTPORT, BUILT_IN_MD, NULL,
4318 /* Array comms builtins. */
4319 add_builtin_function ("__builtin_put_array",
4320 void_ftype_long_int_int_int,
4321 PICOCHIP_BUILTIN_PUT_ARRAY, BUILT_IN_MD, NULL,
4323 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int,
4324 PICOCHIP_BUILTIN_GET_ARRAY, BUILT_IN_MD, NULL,
4326 add_builtin_function ("__builtin_testport_array",
4327 int_ftype_int_int_int,
4328 PICOCHIP_BUILTIN_TESTPORT_ARRAY, BUILT_IN_MD,
4331 /* Halt instruction. Note that the builtin function is marked as
4332 having the attribute `noreturn' so that the compiler realises
4333 that the halt stops the program dead. */
4334 noreturn = tree_cons (get_identifier ("noreturn"), NULL, NULL);
4335 add_builtin_function ("__builtin_halt", void_ftype_void,
4336 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4338 add_builtin_function ("picoHalt", void_ftype_void,
4339 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4344 /* Expand a call to a builtin function. */
4346 picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
4347 enum machine_mode mode ATTRIBUTE_UNUSED,
4348 int ignore ATTRIBUTE_UNUSED)
4350 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4351 int fcode = DECL_FUNCTION_CODE (fndecl);
4355 case PICOCHIP_BUILTIN_ASRI:
4356 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri, exp,
4359 case PICOCHIP_BUILTIN_ADDS:
4360 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3, exp,
4363 case PICOCHIP_BUILTIN_SUBS:
4364 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3, exp,
4367 case PICOCHIP_BUILTIN_SBC:
4368 return picochip_expand_builtin_2op (CODE_FOR_sbc, exp, target);
4370 case PICOCHIP_BUILTIN_BREV:
4371 return picochip_expand_builtin_2op (CODE_FOR_brev, exp, target);
4373 case PICOCHIP_BUILTIN_BYTESWAP:
4374 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2, exp, target);
4376 case PICOCHIP_BUILTIN_GET:
4377 return picochip_expand_builtin_2op (CODE_FOR_commsGet, exp, target);
4379 case PICOCHIP_BUILTIN_PUT:
4380 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut, exp);
4382 case PICOCHIP_BUILTIN_TESTPORT:
4383 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort, exp,
4386 case PICOCHIP_BUILTIN_PUT_ARRAY:
4387 return picochip_expand_array_put (exp, target);
4389 case PICOCHIP_BUILTIN_GET_ARRAY:
4390 return picochip_expand_array_get (exp, target);
4392 case PICOCHIP_BUILTIN_TESTPORT_ARRAY:
4393 return picochip_expand_array_testport (exp, target);
4395 case PICOCHIP_BUILTIN_HALT:
4396 return picochip_generate_halt ();
4403 /* Should really do something sensible here. */
4407 /* Emit warnings. */
4409 picochip_warn_inefficient (const char *msg)
4411 if (TARGET_INEFFICIENT_WARNINGS)
4412 warning (OPT_minefficient_warnings,
4413 "%s (disable warning using -mno-inefficient-warnings)", msg);
4417 warn_of_byte_access (void)
4419 static int warned = 0;
4423 picochip_warn_inefficient
4424 ("byte access is synthesised - consider using MUL AE");
4431 picochip_function_value (const_tree valtype, const_tree func,
4432 bool outgoing ATTRIBUTE_UNUSED)
4434 enum machine_mode mode = TYPE_MODE (valtype);
4435 int unsignedp = TYPE_UNSIGNED (valtype);
4437 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4438 just as PROMOTE_MODE does. */
4439 mode = promote_function_mode (valtype, mode, &unsignedp, func, 1);
4441 return gen_rtx_REG (mode, 0);
4445 /* Check that the value of the given mode will fit in the register of
4448 picochip_hard_regno_mode_ok (int regno, enum machine_mode mode)
4451 if (GET_MODE_CLASS (mode) == MODE_CC)
4452 return regno == CC_REGNUM;
4454 /* If the CC register is being used, then only CC mode values are
4455 allowed (which have already been tested). */
4456 if (regno == CC_REGNUM || regno == ACC_REGNUM)
4459 /* Must be a valid register. */
4463 /* Modes QI and HI may be placed in any register except the CC. */
4464 if (mode == QImode || mode == HImode)
4467 /* DI must be in a quad register. */
4469 return (regno % 4 == 0);
4471 /* All other modes must be placed in a even numbered register. */
4472 return !(regno & 1);
4476 /* Extract the lower and upper components of a constant value. */
4479 picochip_get_low_const (rtx value)
4481 return gen_int_mode (INTVAL (value) & 0xFFFF, HImode);
4485 picochip_get_high_const (rtx value)
4487 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4488 return gen_int_mode ((INTVAL (value) >> 16) & 0xFFFF, HImode);
4492 /* Loading and storing QImode values to and from memory in a machine
4493 without byte access requires might require a scratch
4494 register. However, the scratch register might correspond to the
4495 register in which the value is being loaded. To ensure that a
4496 scratch register is supplied which is definitely different to the
4497 output register, request a register pair. This effectively gives a
4498 choice of two registers to choose from, so that we a guaranteed to
4499 get at least one register which is different to the output
4500 register. This trick is taken from the alpha implementation. */
4502 picochip_secondary_reload (bool in_p,
4503 rtx x ATTRIBUTE_UNUSED,
4504 reg_class_t cla ATTRIBUTE_UNUSED,
4505 enum machine_mode mode,
4506 secondary_reload_info *sri)
4508 if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
4511 sri->icode = CODE_FOR_reload_outqi;
4513 sri->icode = CODE_FOR_reload_inqi;
4516 /* We dont need to return a register class type when we need only a
4517 scratch register. It realizes the scratch register type by looking
4518 at the instruction definition for sri->icode. We only need to
4519 return the register type when we need intermediaries for copies.*/
4523 /* Return true if the given memory operand can be aligned to a
4524 word+offset memory reference (e.g., FP+3 can be converted into the
4525 memory operand FP+2, with the offset 1). */
4527 picochip_alignable_memory_operand (rtx mem_operand,
4528 enum machine_mode mode ATTRIBUTE_UNUSED)
4532 /* Not a mem operand. Refuse immediately. */
4533 if (MEM != GET_CODE (mem_operand))
4536 address = XEXP (mem_operand, 0);
4538 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4539 return ((PLUS == GET_CODE (address) &&
4540 REGNO (XEXP (address, 0)) == STACK_POINTER_REGNUM &&
4541 CONST_INT == GET_CODE (XEXP (address, 1)) &&
4542 picochip_const_ok_for_letter_p (INTVAL (XEXP (address, 1)), 'K'))
4543 || (REG == GET_CODE (address)
4544 && REGNO (address) == STACK_POINTER_REGNUM));
4548 /* Return true if the given memory reference is to a word aligned
4549 address. Currently this means it must be either SP, or
4550 SP+offset. We could replace this function with alignable
4551 memory references in the above function?. */
4553 picochip_word_aligned_memory_reference (rtx operand)
4557 /* The address must be the SP register, or a constant, aligned
4558 offset from SP which doesn't exceed the FP+offset
4560 return ((PLUS == GET_CODE (operand)
4561 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
4562 && picochip_is_aligned (INTVAL (XEXP (operand, 1)), 16)
4563 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand, 1)),
4565 || (REG == GET_CODE (operand)
4566 && REGNO (operand) == STACK_POINTER_REGNUM));
4570 /* Given an alignable memory location, convert the memory location
4571 into a HI mode access, storing the new memory reference in
4572 paligned_mem, and the number of bits by which to shift in pbitnum
4573 (i.e., given a reference to FP+3, this creates an aligned reference
4574 of FP+2, with an 8-bit shift). This code is a modification of that
4575 found in the Alpha port. */
4577 picochip_get_hi_aligned_mem (rtx ref, rtx * paligned_mem, rtx * pbitnum)
4580 HOST_WIDE_INT offset = 0;
4582 gcc_assert (GET_CODE (ref) == MEM);
4584 if (reload_in_progress && !memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
4586 base = find_replacement (&XEXP (ref, 0));
4588 gcc_assert(memory_address_p (GET_MODE (ref), base));
4592 base = XEXP (ref, 0);
4595 if (GET_CODE (base) == PLUS)
4597 offset += INTVAL (XEXP (base, 1));
4598 base = XEXP (base, 0);
4601 *paligned_mem = widen_memory_access (ref, HImode, (offset & ~1) - offset);
4608 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4612 *pbitnum = GEN_INT ((offset & 1) * 8);
4616 /* Return true if the given operand is an absolute address in memory
4617 (i.e., a symbolic offset). */
4619 picochip_absolute_memory_operand (rtx op,
4620 enum machine_mode mode ATTRIBUTE_UNUSED)
4623 if (MEM == GET_CODE (op))
4625 rtx address = XEXP (op, 0);
4627 /* Symbols are valid absolute addresses. */
4628 if (SYMBOL_REF == GET_CODE (address))
4631 /* Constant offsets to symbols are valid absolute addresses. */
4632 if (CONST == GET_CODE (address) &&
4633 PLUS == GET_CODE (XEXP (address, 0)) &&
4634 SYMBOL_REF == GET_CODE (XEXP (XEXP (address, 0), 0)) &&
4635 CONST_INT == GET_CODE (XEXP (XEXP (address, 0), 1)))
4642 /* Symbols are valid absolute addresses. */
4643 if (SYMBOL_REF == GET_CODE (XEXP (op, 0)))
4652 picochip_asm_named_section (const char *name,
4653 unsigned int flags ATTRIBUTE_UNUSED,
4654 tree decl ATTRIBUTE_UNUSED)
4656 fprintf (asm_out_file, ".section %s\n", name);
4660 /* Check if we can make a conditional copy instruction. This is emitted as an
4661 instruction to set the condition register, followed by an instruction which
4662 uses the condition registers to perform the conditional move. */
4664 picochip_check_conditional_copy (rtx * operands)
4667 rtx branch_op_0 = XEXP (operands[1], 0);
4668 rtx branch_op_1 = XEXP (operands[1], 1);
4670 /* Only HI mode conditional moves are currently allowed. Can we add
4672 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
4675 /* Is the comparison valid? Only allow operands which are registers
4676 if they are HImode. SI mode comparisons against 0 could be
4677 handled using logical operations (e.g., SIreg != 0 when low ||
4678 high). Need to find test cases to provoke this though (fixunssfdi
4679 in libgcc does, but is complicated). */
4680 if (register_operand(branch_op_0, GET_MODE(branch_op_0)) &&
4681 GET_MODE(branch_op_0) != HImode)
4683 if (register_operand(branch_op_1, GET_MODE(branch_op_1)) &&
4684 GET_MODE(branch_op_1) != HImode)
4693 picochip_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
4697 addr = arg_pointer_rtx;
4699 addr = plus_constant (stack_pointer_rtx, -2 * UNITS_PER_WORD);
4700 return gen_frame_mem (Pmode, addr);