1 /* Definitions of target machine for GNU compiler, for the pdp-11
2 Copyright (C) 1994, 95, 96, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 1, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* check whether load_fpu_reg or not */
24 #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11)
25 #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13)
26 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
27 #define CPU_REG_P(x) ((x)<8)
29 /* Names to predefine in the preprocessor for this target machine. */
31 #define CPP_PREDEFINES "-Dpdp11"
33 /* Print subsidiary information on the compiler version in use. */
34 #define TARGET_VERSION fprintf (stderr, " (pdp11)");
37 /* Generate DBX debugging information. */
39 /* #define DBX_DEBUGGING_INFO */
41 /* Run-time compilation parameters selecting different hardware subsets.
44 extern int target_flags;
46 /* Macro to define tables used to set the flags.
47 This is a list in braces of triplets in braces,
48 each triplet being { "NAME", VALUE, DOC }
49 where VALUE is the bits to set or minus the bits to clear and DOC
50 is the documentation for --help (NULL if intentionally undocumented).
51 An empty string NAME is used to identify the default VALUE. */
53 #define TARGET_SWITCHES \
54 { { "fpu", 1, "Use hardware floating point" }, \
55 { "soft-float", -1, "Do not use hardware floating point" }, \
56 /* return float result in ac0 */ \
57 { "ac0", 2, "Return floating point results in ac0" }, \
58 { "no-ac0", -2, "Return floating point results in memory" },\
60 { "40", 4, "Generate code for an 11/40" }, \
61 { "no-40", -4, "" }, \
63 { "45", 8, "Generate code for an 11/45" }, \
64 { "no-45", -8, "" }, \
66 { "10", -12, "Generate code for an 11/10" }, \
67 /* use movstrhi for bcopy */ \
68 { "bcopy", 16, NULL }, \
69 { "bcopy-builtin", -16, NULL }, \
70 /* use 32 bit for int */ \
71 { "int32", 32, "Use 32 bit int" }, \
72 { "no-int16", 32, "Use 32 bit int" }, \
73 { "int16", -32, "Use 16 bit int" }, \
74 { "no-int32", -32, "Use 16 bit int" }, \
75 /* use 32 bit for float */ \
76 { "float32", 64, "Use 32 bit float" }, \
77 { "no-float64", 64, "Use 32 bit float" }, \
78 { "float64", -64, "Use 64 bit float" }, \
79 { "no-float32", -64, "Use 64 bit float" }, \
80 /* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\
81 { "abshi", 128, NULL }, \
82 { "no-abshi", -128, NULL }, \
83 /* is branching expensive - on a PDP, it's actually really cheap */ \
84 /* this is just to play around and check what code gcc generates */ \
85 { "branch-expensive", 256, NULL }, \
86 { "branch-cheap", -256, NULL }, \
87 /* split instruction and data memory? */ \
88 { "split", 1024, "Target has split I&D" }, \
89 { "no-split", -1024, "Target does not have split I&D" }, \
90 /* UNIX assembler syntax? */ \
91 { "unix-asm", 2048, "Use UNIX assembler syntax" }, \
92 { "dec-asm", -2048, "Use DEC assembler syntax" }, \
94 { "", TARGET_DEFAULT, NULL} \
97 #define TARGET_DEFAULT (1 | 8 | 128 | TARGET_UNIX_ASM_DEFAULT)
99 #define TARGET_FPU (target_flags & 1)
100 #define TARGET_SOFT_FLOAT (!TARGET_FPU)
102 #define TARGET_AC0 ((target_flags & 2) && TARGET_FPU)
103 #define TARGET_NO_AC0 (! TARGET_AC0)
105 #define TARGET_45 (target_flags & 8)
106 #define TARGET_40_PLUS ((target_flags & 4) || (target_flags & 8))
107 #define TARGET_10 (! TARGET_40_PLUS)
109 #define TARGET_BCOPY_BUILTIN (! (target_flags & 16))
111 #define TARGET_INT16 (! TARGET_INT32)
112 #define TARGET_INT32 (target_flags & 32)
114 #define TARGET_FLOAT32 (target_flags & 64)
115 #define TARGET_FLOAT64 (! TARGET_FLOAT32)
117 #define TARGET_ABSHI_BUILTIN (target_flags & 128)
119 #define TARGET_BRANCH_EXPENSIVE (target_flags & 256)
120 #define TARGET_BRANCH_CHEAP (!TARGET_BRANCH_EXPENSIVE)
122 #define TARGET_SPLIT (target_flags & 1024)
123 #define TARGET_NOSPLIT (! TARGET_SPLIT)
125 #define TARGET_UNIX_ASM (target_flags & 2048)
126 #define TARGET_UNIX_ASM_DEFAULT 0
128 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0)
133 #define CHAR_TYPE_SIZE 8
134 #define SHORT_TYPE_SIZE 16
135 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32)
136 #define LONG_TYPE_SIZE 32
137 #define LONG_LONG_TYPE_SIZE 64
139 /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit
140 of saving core for huge arrays - the definitions are
141 already in md - but floats can never reside in
142 an FPU register - we keep the FPU in double float mode
144 #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64)
145 #define DOUBLE_TYPE_SIZE 64
146 #define LONG_DOUBLE_TYPE_SIZE 64
148 /* machine types from ansi */
149 #define SIZE_TYPE "unsigned int" /* definition of size_t */
150 #define WCHAR_TYPE "int" /* or long int???? */
151 #define WCHAR_TYPE_SIZE 16
153 #define PTRDIFF_TYPE "int"
155 /* target machine storage layout */
157 /* Define this if most significant bit is lowest numbered
158 in instructions that operate on numbered bit-fields. */
159 #define BITS_BIG_ENDIAN 0
161 /* Define this if most significant byte of a word is the lowest numbered. */
162 #define BYTES_BIG_ENDIAN 0
164 /* Define this if most significant word of a multiword number is numbered. */
165 #define WORDS_BIG_ENDIAN 1
167 /* number of bits in an addressable storage unit */
168 #define BITS_PER_UNIT 8
170 /* Width in bits of a "word", which is the contents of a machine register.
171 Note that this is not necessarily the width of data type `int';
172 if using 16-bit ints on a 68000, this would still be 32.
173 But on a machine with 16-bit registers, this would be 16. */
174 /* This is a machine with 16-bit registers */
175 #define BITS_PER_WORD 16
177 /* Width of a word, in units (bytes).
179 UNITS OR BYTES - seems like units */
180 #define UNITS_PER_WORD 2
182 /* Maximum sized of reasonable data type
183 DImode or Dfmode ...*/
184 #define MAX_FIXED_MODE_SIZE 64
186 /* Width in bits of a pointer.
187 See also the macro `Pmode' defined below. */
188 #define POINTER_SIZE 16
190 /* Allocation boundary (in *bits*) for storing pointers in memory. */
191 #define POINTER_BOUNDARY 16
193 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
194 #define PARM_BOUNDARY 16
196 /* Allocation boundary (in *bits*) for the code of a function. */
197 #define FUNCTION_BOUNDARY 16
199 /* Alignment of field after `int : 0' in a structure. */
200 #define EMPTY_FIELD_BOUNDARY 16
202 /* No data type wants to be aligned rounder than this. */
203 #define BIGGEST_ALIGNMENT 16
205 /* Define this if move instructions will actually fail to work
206 when given unaligned data. */
207 #define STRICT_ALIGNMENT 1
209 /* Standard register usage. */
211 /* Number of actual hardware registers.
212 The hardware registers are assigned numbers for the compiler
213 from 0 to just below FIRST_PSEUDO_REGISTER.
214 All registers that the compiler knows about must be given numbers,
215 even those that are not normally considered general registers.
217 we have 8 integer registers, plus 6 float
218 (don't use scratch float !) */
220 #define FIRST_PSEUDO_REGISTER 14
222 /* 1 for registers that have pervasive standard uses
223 and are not available for the register allocator.
225 On the pdp, these are:
228 reg 5 = fp; not necessarily!
231 /* don't let them touch fp regs for the time being !*/
233 #define FIXED_REGISTERS \
234 {0, 0, 0, 0, 0, 0, 1, 1, \
239 /* 1 for registers not available across function calls.
240 These must include the FIXED_REGISTERS and also any
241 registers that can be used without being saved.
242 The latter must include the registers where values are returned
243 and the register where structure-value addresses are passed.
244 Aside from that, you can include as many other registers as you like. */
246 /* don't know about fp */
247 #define CALL_USED_REGISTERS \
248 {1, 1, 0, 0, 0, 0, 1, 1, \
252 /* Make sure everything's fine if we *don't* have an FPU.
253 This assumes that putting a register in fixed_regs will keep the
254 compiler's mitts completely off it. We don't bother to zero it out
255 of register classes. Also fix incompatible register naming with
258 #define CONDITIONAL_REGISTER_USAGE \
264 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \
265 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
266 if (TEST_HARD_REG_BIT (x, i)) \
267 fixed_regs[i] = call_used_regs[i] = 1; \
271 call_used_regs[8] = 1; \
272 if (TARGET_UNIX_ASM) \
274 /* Change names of FPU registers for the UNIX assembler. */ \
275 reg_names[8] = "fr0"; \
276 reg_names[9] = "fr1"; \
277 reg_names[10] = "fr2"; \
278 reg_names[11] = "fr3"; \
279 reg_names[12] = "fr4"; \
280 reg_names[13] = "fr5"; \
284 /* Return number of consecutive hard regs needed starting at reg REGNO
285 to hold something of mode MODE.
286 This is ordinarily the length in words of a value of mode MODE
287 but can be less for certain modes in special long registers.
290 #define HARD_REGNO_NREGS(REGNO, MODE) \
292 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
296 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
297 On the pdp, the cpu registers can hold any mode - check alignment
299 FPU can only hold DF - simplifies life!
301 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
303 ((GET_MODE_BITSIZE(MODE) <= 16) \
304 || (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \
308 /* Value is 1 if it is a good idea to tie two pseudo registers
309 when one has mode MODE1 and one has mode MODE2.
310 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
311 for any hard reg, then this must be 0 for correct output. */
312 #define MODES_TIEABLE_P(MODE1, MODE2) 0
314 /* Specify the registers used for certain standard purposes.
315 The values of these macros are register numbers. */
317 /* the pdp11 pc overloaded on a register that the compiler knows about. */
320 /* Register to use for pushing function arguments. */
321 #define STACK_POINTER_REGNUM 6
323 /* Base register for access to local variables of the function. */
324 #define FRAME_POINTER_REGNUM 5
326 /* Value should be nonzero if functions must have frame pointers.
327 Zero means the frame pointer need not be set up (and parms
328 may be accessed via the stack pointer) in functions that seem suitable.
329 This is computed in `reload', in reload1.c.
332 #define FRAME_POINTER_REQUIRED 0
334 /* Base register for access to arguments of the function. */
335 #define ARG_POINTER_REGNUM 5
337 /* Register in which static-chain is passed to a function. */
338 /* ??? - i don't want to give up a reg for this! */
339 #define STATIC_CHAIN_REGNUM 4
341 /* Register in which address to store a structure value
342 is passed to a function.
343 let's make it an invisible first argument!!! */
345 #define STRUCT_VALUE 0
348 /* Define the classes of registers for register constraints in the
349 machine description. Also define ranges of constants.
351 One of the classes must always be named ALL_REGS and include all hard regs.
352 If there is more than one class, another class must be named NO_REGS
353 and contain no registers.
355 The name GENERAL_REGS must be the name of a class (or an alias for
356 another name such as ALL_REGS). This is the class of registers
357 that is allowed by "g" or "r" in a register constraint.
358 Also, registers outside this class are allocated only when
359 instructions express preferences for them.
361 The classes must be numbered in nondecreasing order; that is,
362 a larger-numbered class must never be contained completely
363 in a smaller-numbered class.
365 For any two classes, it is very desirable that there be another
366 class that represents their union. */
368 /* The pdp has a couple of classes:
370 MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication
371 (even numbered do 32 bit multiply)
372 LMUL_REGS long multiply registers (even numbered regs )
373 (don't need them, all 32 bit regs are even numbered!)
374 GENERAL_REGS is all cpu
375 LOAD_FPU_REGS is the first four cpu regs, they are easier to load
376 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
377 FPU_REGS is all fpu regs
380 enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES };
382 #define N_REG_CLASSES (int) LIM_REG_CLASSES
384 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */
385 #define SMALL_REGISTER_CLASSES 1
387 /* Since GENERAL_REGS is the same class as ALL_REGS,
388 don't give it a different class number; just make it an alias. */
390 /* #define GENERAL_REGS ALL_REGS */
392 /* Give names of register classes as strings for dump file. */
394 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
396 /* Define which registers fit in which classes.
397 This is an initializer for a vector of HARD_REG_SET
398 of length N_REG_CLASSES. */
400 #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}}
402 /* The same information, inverted:
403 Return the class number of the smallest class containing
404 reg number REGNO. This could be a conditional expression
405 or could index an array. */
407 #define REGNO_REG_CLASS(REGNO) \
408 ((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS))
411 /* The class value for index registers, and the one for base regs. */
412 #define INDEX_REG_CLASS GENERAL_REGS
413 #define BASE_REG_CLASS GENERAL_REGS
415 /* Get reg_class from a letter such as appears in the machine description. */
417 #define REG_CLASS_FROM_LETTER(C) \
418 ((C) == 'f' ? FPU_REGS : \
419 ((C) == 'd' ? MUL_REGS : \
420 ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS)))
423 /* The letters I, J, K, L and M in a register constraint string
424 can be used to stand for particular ranges of immediate operands.
425 This macro defines what the ranges are.
426 C is the letter, and VALUE is a constant value.
427 Return 1 if VALUE is in the range specified by C.
431 K completely random 32 bit
432 L,M,N -1,1,0 respectively
433 O where doing shifts in sequence is faster than
437 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
438 ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \
439 : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \
440 : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \
441 && ((VALUE) & 0x0000ffff) != 0) \
442 : (C) == 'L' ? ((VALUE) == 1) \
443 : (C) == 'M' ? ((VALUE) == -1) \
444 : (C) == 'N' ? ((VALUE) == 0) \
445 : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \
448 /* Similar, but for floating constants, and defining letters G and H.
449 Here VALUE is the CONST_DOUBLE rtx itself. */
451 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
452 ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0)
455 /* Letters in the range `Q' through `U' may be defined in a
456 machine-dependent fashion to stand for arbitrary operand types.
457 The machine description macro `EXTRA_CONSTRAINT' is passed the
458 operand as its first argument and the constraint letter as its
461 `Q' is for memory references using take more than 1 instruction.
462 `R' is for memory references which take 1 word for the instruction. */
464 #define EXTRA_CONSTRAINT(OP,CODE) \
465 ((GET_CODE (OP) != MEM) ? 0 \
466 : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \
467 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
468 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
471 /* Given an rtx X being reloaded into a reg required to be
472 in class CLASS, return the class of reg to actually use.
473 In general this is just CLASS; but on some machines
474 in some cases it is preferable to use a more restrictive class.
476 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
478 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
479 (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS)
481 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \
482 (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS)
484 /* Return the maximum number of consecutive registers
485 needed to represent mode MODE in a register of class CLASS. */
486 #define CLASS_MAX_NREGS(CLASS, MODE) \
487 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \
488 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \
493 /* Stack layout; function entry, exit and calling. */
495 /* Define this if pushing a word on the stack
496 makes the stack pointer a smaller address. */
497 #define STACK_GROWS_DOWNWARD
499 /* Define this if the nominal address of the stack frame
500 is at the high-address end of the local variables;
501 that is, each additional local variable allocated
502 goes at a more negative offset in the frame.
504 #define FRAME_GROWS_DOWNWARD
506 /* Offset within stack frame to start allocating local variables at.
507 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
508 first local allocated. Otherwise, it is the offset to the BEGINNING
509 of the first local allocated. */
510 #define STARTING_FRAME_OFFSET 0
512 /* If we generate an insn to push BYTES bytes,
513 this says how many the stack pointer really advances by.
514 On the pdp11, the stack is on an even boundary */
515 #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1)
517 /* current_first_parm_offset stores the # of registers pushed on the
519 extern int current_first_parm_offset;
521 /* Offset of first parameter from the argument pointer register value.
522 For the pdp11, this is non-zero to account for the return address.
524 2 - frame pointer (always saved, even when not used!!!!)
525 -- chnage some day !!!:q!
528 #define FIRST_PARM_OFFSET(FNDECL) 4
530 /* Value is 1 if returning from a function call automatically
531 pops the arguments described by the number-of-args field in the call.
532 FUNDECL is the declaration node of the function (as a tree),
533 FUNTYPE is the data type of the function (as a tree),
534 or for a library call it is an identifier node for the subroutine name. */
536 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
538 /* Define how to find the value returned by a function.
539 VALTYPE is the data type of the value (as a tree).
540 If the precise function being called is known, FUNC is its FUNCTION_DECL;
541 otherwise, FUNC is 0. */
542 #define BASE_RETURN_VALUE_REG(MODE) \
543 ((MODE) == DFmode ? 8 : 0)
545 /* On the pdp11 the value is found in R0 (or ac0???
546 not without FPU!!!! ) */
548 #define FUNCTION_VALUE(VALTYPE, FUNC) \
549 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
551 /* and the called function leaves it in the first register.
552 Difference only on machines with register windows. */
554 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
555 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
557 /* Define how to find the value returned by a library function
558 assuming the value has mode MODE. */
560 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG(MODE))
562 /* 1 if N is a possible register number for a function value
563 as seen by the caller.
564 On the pdp, the first "output" reg is the only register thus used.
566 maybe ac0 ? - as option someday! */
568 #define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8))
570 /* should probably return DImode and DFmode in memory,lest
573 have to, else we crash - exception: maybe return result in
574 ac0 if DFmode and FPU present - compatibility problem with
575 libraries for non-floating point ...
578 #define RETURN_IN_MEMORY(TYPE) \
579 (TYPE_MODE(TYPE) == DImode || (TYPE_MODE(TYPE) == DFmode && ! TARGET_AC0))
582 /* 1 if N is a possible register number for function argument passing.
585 #define FUNCTION_ARG_REGNO_P(N) 0
587 /* Define a data type for recording info about an argument list
588 during the scan of that argument list. This data type should
589 hold all necessary information about the function itself
590 and about the args processed so far, enough to enable macros
591 such as FUNCTION_ARG to determine where the next arg should go.
595 #define CUMULATIVE_ARGS int
597 /* Initialize a variable CUM of type CUMULATIVE_ARGS
598 for a call to a function whose data type is FNTYPE.
599 For a library call, FNTYPE is 0.
601 ...., the offset normally starts at 0, but starts at 1 word
602 when the function gets a structure-value-address as an
603 invisible first argument. */
605 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
608 /* Update the data in CUM to advance over an argument
609 of mode MODE and data type TYPE.
610 (TYPE is null for libcalls where that information may not be available.)
615 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
616 ((CUM) += ((MODE) != BLKmode \
617 ? (GET_MODE_SIZE (MODE)) \
618 : (int_size_in_bytes (TYPE))))
620 /* Determine where to put an argument to a function.
621 Value is zero to push the argument on the stack,
622 or a hard register in which to store the argument.
624 MODE is the argument's machine mode.
625 TYPE is the data type of the argument (as a tree).
626 This is null for libcalls where that information may
628 CUM is a variable of type CUMULATIVE_ARGS which gives info about
629 the preceding args and about the function being called.
630 NAMED is nonzero if this argument is a named parameter
631 (otherwise it is an extra parameter matching an ellipsis). */
633 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
635 /* Define where a function finds its arguments.
636 This would be different from FUNCTION_ARG if we had register windows. */
638 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
639 FUNCTION_ARG (CUM, MODE, TYPE, NAMED)
642 /* For an arg passed partly in registers and partly in memory,
643 this is the number of registers used.
644 For args passed entirely in registers or entirely in memory, zero. */
646 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
648 /* This macro generates the assembly code for function entry. */
649 #define FUNCTION_PROLOGUE(FILE, SIZE) \
650 output_function_prologue(FILE, SIZE);
652 /* Output assembler code to FILE to increment profiler label # LABELNO
653 for profiling a function entry. */
655 #define FUNCTION_PROFILER(FILE, LABELNO) \
658 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
659 the stack pointer does not matter. The value is tested only in
660 functions that have frame pointers.
661 No definition is equivalent to always zero. */
663 extern int may_call_alloca;
665 #define EXIT_IGNORE_STACK 1
667 /* This macro generates the assembly code for function exit,
668 on machines that need it. If FUNCTION_EPILOGUE is not defined
669 then individual return instructions are generated for each
670 return statement. Args are same as for FUNCTION_PROLOGUE.
673 #define FUNCTION_EPILOGUE(FILE, SIZE) \
674 output_function_epilogue(FILE, SIZE);
676 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \
679 offset = get_frame_size(); \
680 for (regno = 0; regno < 8; regno++) \
681 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
683 for (regno = 8; regno < 14; regno++) \
684 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
686 /* offset -= 2; no fp on stack frame */ \
687 (DEPTH_VAR) = offset; \
691 /* Addressing modes, and classification of registers for them. */
693 #define HAVE_POST_INCREMENT 1
694 /* #define HAVE_POST_DECREMENT 0 */
696 #define HAVE_PRE_DECREMENT 1
697 /* #define HAVE_PRE_INCREMENT 0 */
699 /* Macros to check register numbers against specific register classes. */
701 /* These assume that REGNO is a hard or pseudo reg number.
702 They give nonzero only if REGNO is a hard reg of the suitable class
703 or a pseudo reg currently allocated to a suitable hard reg.
704 Since they use reg_renumber, they are safe only once reg_renumber
705 has been allocated, which happens in local-alloc.c. */
707 #define REGNO_OK_FOR_INDEX_P(REGNO) \
708 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
709 #define REGNO_OK_FOR_BASE_P(REGNO) \
710 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
712 /* Now macros that check whether X is a register and also,
713 strictly, whether it is in a specified class.
718 /* Maximum number of registers that can appear in a valid memory address. */
720 #define MAX_REGS_PER_ADDRESS 2
722 /* Recognize any constant value that is a valid address. */
724 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
726 /* Nonzero if the constant value X is a legitimate general operand.
727 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
729 #define LEGITIMATE_CONSTANT_P(X) (1)
731 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
732 and check its validity for a certain class.
733 We have two alternate definitions for each of them.
734 The usual definition accepts all pseudo regs; the other rejects
735 them unless they have been allocated suitable hard regs.
736 The symbol REG_OK_STRICT causes the latter definition to be used.
738 Most source files want to accept pseudo regs in the hope that
739 they will get allocated to the class that the insn wants them to be in.
740 Source files for reload pass need to be strict.
741 After reload, it makes no difference, since pseudo regs have
742 been eliminated by then. */
744 #ifndef REG_OK_STRICT
746 /* Nonzero if X is a hard reg that can be used as an index
747 or if it is a pseudo reg. */
748 #define REG_OK_FOR_INDEX_P(X) (1)
749 /* Nonzero if X is a hard reg that can be used as a base reg
750 or if it is a pseudo reg. */
751 #define REG_OK_FOR_BASE_P(X) (1)
755 /* Nonzero if X is a hard reg that can be used as an index. */
756 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
757 /* Nonzero if X is a hard reg that can be used as a base reg. */
758 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
762 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
763 that is a valid memory address for an instruction.
764 The MODE argument is the machine mode for the MEM expression
765 that wants to use this address.
769 #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \
774 if (GET_CODE (operand) == REG \
775 && REG_OK_FOR_BASE_P(operand)) \
778 /* accept @#address */ \
779 if (CONSTANT_ADDRESS_P (operand)) \
783 if (GET_CODE (operand) == PLUS \
784 && GET_CODE (XEXP (operand, 0)) == REG \
785 && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \
786 && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \
790 if (GET_CODE (operand) == PRE_DEC \
791 && GET_CODE (XEXP (operand, 0)) == REG \
792 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
796 if (GET_CODE (operand) == POST_INC \
797 && GET_CODE (XEXP (operand, 0)) == REG \
798 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
801 /* handle another level of indirection ! */ \
802 if (GET_CODE(operand) != MEM) \
805 xfoob = XEXP (operand, 0); \
807 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \
808 /* also forbidden for float, because we have to handle this */ \
809 /* in output_move_double and/or output_move_quad() - we could */ \
810 /* do it, but currently it's not worth it!!! */ \
811 /* now that DFmode cannot go into CPU register file, */ \
812 /* maybe I should allow float ... */ \
813 /* but then I have to handle memory-to-memory moves in movdf ?? */ \
815 if (GET_MODE_BITSIZE(mode) > 16) \
818 /* accept @(R0) - which is @0(R0) */ \
819 if (GET_CODE (xfoob) == REG \
820 && REG_OK_FOR_BASE_P(xfoob)) \
823 /* accept @address */ \
824 if (CONSTANT_ADDRESS_P (xfoob)) \
827 /* accept @X(R0) */ \
828 if (GET_CODE (xfoob) == PLUS \
829 && GET_CODE (XEXP (xfoob, 0)) == REG \
830 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \
831 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \
834 /* accept @-(R0) */ \
835 if (GET_CODE (xfoob) == PRE_DEC \
836 && GET_CODE (XEXP (xfoob, 0)) == REG \
837 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
840 /* accept @(R0)+ */ \
841 if (GET_CODE (xfoob) == POST_INC \
842 && GET_CODE (XEXP (xfoob, 0)) == REG \
843 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
846 /* anything else is invalid */ \
851 /* Try machine-dependent ways of modifying an illegitimate address
852 to be legitimate. If we find one, return the new, valid address.
853 This macro is used in only one place: `memory_address' in explow.c.
855 OLDX is the address as it was before break_out_memory_refs was called.
856 In some cases it is useful to look at this to decide what needs to be done.
858 MODE and WIN are passed so that this macro can use
859 GO_IF_LEGITIMATE_ADDRESS.
861 It is always safe for this macro to do nothing. It exists to recognize
862 opportunities to optimize the output. */
864 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
867 /* Go to LABEL if ADDR (a legitimate address expression)
868 has an effect that depends on the machine mode it is used for.
869 On the pdp this is for predec/postinc */
871 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
872 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
877 /* Specify the machine mode that this machine uses
878 for the index in the tablejump instruction. */
879 #define CASE_VECTOR_MODE HImode
881 /* Define this if a raw index is all that is needed for a
883 #define CASE_TAKES_INDEX_RAW
885 /* Define as C expression which evaluates to nonzero if the tablejump
886 instruction expects the table to contain offsets from the address of the
888 Do not define this if the table should contain absolute addresses. */
889 /* #define CASE_VECTOR_PC_RELATIVE 1 */
891 /* Specify the tree operation to be used to convert reals to integers. */
892 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
894 /* This is the kind of divide that is easiest to do in the general case. */
895 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
897 /* Define this as 1 if `char' should by default be signed; else as 0. */
898 #define DEFAULT_SIGNED_CHAR 1
900 /* Max number of bytes we can move from memory to memory
901 in one reasonably fast instruction.
906 /* Zero extension is faster if the target is known to be zero */
907 /* #define SLOW_ZERO_EXTEND */
909 /* Nonzero if access to memory by byte is slow and undesirable. -
911 #define SLOW_BYTE_ACCESS 0
913 /* Do not break .stabs pseudos into continuations. */
914 #define DBX_CONTIN_LENGTH 0
916 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
917 is done just by pretending it is already truncated. */
918 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
921 /* Add any extra modes needed to represent the condition code.
923 CCFPmode is used for FPU, but should we use a separate reg? */
924 #define EXTRA_CC_MODES CC(CCFPmode, "CCFP")
926 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE,
927 return the mode to be used for the comparison. For floating-point, CCFPmode
930 #define SELECT_CC_MODE(OP,X,Y) \
931 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode)
933 /* We assume that the store-condition-codes instructions store 0 for false
934 and some other value for true. This is the value stored for true. */
936 /* #define STORE_FLAG_VALUE 1 */
938 /* Specify the machine mode that pointers have.
939 After generation of rtl, the compiler makes no further distinction
940 between pointers and any other objects of this machine mode. */
943 /* A function address in a call instruction
944 is a word address (for indexing purposes)
945 so give the MEM rtx a word's mode. */
946 #define FUNCTION_MODE HImode
948 /* Define this if addresses of constant functions
949 shouldn't be put through pseudo regs where they can be cse'd.
950 Desirable on machines where ordinary constants are expensive
951 but a CALL with constant address is cheap. */
952 /* #define NO_FUNCTION_CSE */
954 /* Compute the cost of computing a constant rtl expression RTX
955 whose rtx-code is CODE. The body of this macro is a portion
956 of a switch statement. If the code is computed here,
957 return it with a return statement. Otherwise, break from the switch.
959 -1, 0, 1 are cheaper for add, sub ...
962 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
964 if (INTVAL(RTX) == 0 \
965 || INTVAL(RTX) == -1 \
966 || INTVAL(RTX) == 1) \
971 /* twice as expensive as REG */ \
974 /* twice (or 4 times) as expensive as 16 bit */ \
977 /* cost of moving one register class to another */
978 #define REGISTER_MOVE_COST(CLASS1, CLASS2) register_move_cost(CLASS1, CLASS2)
980 /* Tell emit-rtl.c how to initialize special values on a per-function base. */
982 extern struct rtx_def *cc0_reg_rtx;
984 #define CC_STATUS_MDEP rtx
986 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
988 /* Tell final.c how to eliminate redundant test instructions. */
990 /* Here we define machine-dependent flags and fields in cc_status
991 (see `conditions.h'). */
993 #define CC_IN_FPU 04000
995 /* Do UPDATE_CC if EXP is a set, used in
998 floats only do compare correctly, else nullify ...
1000 get cc0 out soon ...
1003 /* Store in cc_status the expressions
1004 that the condition codes will describe
1005 after execution of an instruction whose pattern is EXP.
1006 Do not alter them if the instruction would not alter the cc's. */
1008 #define NOTICE_UPDATE_CC(EXP, INSN) \
1009 { if (GET_CODE (EXP) == SET) \
1011 notice_update_cc_on_set(EXP, INSN); \
1013 else if (GET_CODE (EXP) == PARALLEL \
1014 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
1016 notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \
1018 else if (GET_CODE (EXP) == CALL) \
1019 { /* all bets are off */ CC_STATUS_INIT; } \
1020 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1021 && cc_status.value2 \
1022 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1024 printf ("here!\n"); \
1025 cc_status.value2 = 0; \
1029 /* Control the assembler format that we output. */
1031 /* Output at beginning of assembler file. */
1034 #define ASM_FILE_START(FILE) \
1036 fprintf (FILE, "\t.data\n"), \
1037 fprintf (FILE, "$help$: . = .+8 ; space for tmp moves!\n") \
1038 /* do we need reg def's R0 = %0 etc ??? */ \
1041 #define ASM_FILE_START(FILE)
1045 /* Output to assembler file text saying following lines
1046 may contain character constants, extra white space, comments, etc. */
1048 #define ASM_APP_ON ""
1050 /* Output to assembler file text saying following lines
1051 no longer contain unusual constructs. */
1053 #define ASM_APP_OFF ""
1055 /* Output before read-only data. */
1057 #define TEXT_SECTION_ASM_OP "\t.text\n"
1059 /* Output before writable data. */
1061 #define DATA_SECTION_ASM_OP "\t.data\n"
1063 /* How to refer to registers in assembler output.
1064 This sequence is indexed by compiler's hard-register-number (see above). */
1066 #define REGISTER_NAMES \
1067 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \
1068 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" }
1070 /* How to renumber registers for dbx and gdb. */
1072 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1074 /* This is how to output the definition of a user-level label named NAME,
1075 such as the label on a static function or variable NAME. */
1077 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1078 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1080 /* This is how to output a command to make the user-level label named NAME
1081 defined for reference from other files. */
1083 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1084 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs("\n", FILE); } while (0)
1086 /* The prefix to add to user-visible assembler symbols. */
1088 #define USER_LABEL_PREFIX "_"
1090 /* This is how to output an internal numbered label where
1091 PREFIX is the class of label and NUM is the number within the class. */
1093 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1094 fprintf (FILE, "%s_%d:\n", PREFIX, NUM)
1096 /* This is how to store into the string LABEL
1097 the symbol_ref name of an internal numbered label where
1098 PREFIX is the class of label and NUM is the number within the class.
1099 This is suitable for output with `assemble_name'. */
1101 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1102 sprintf (LABEL, "*%s_%d", PREFIX, NUM)
1104 /* This is how to output an assembler line defining a `double' constant. */
1106 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1107 fprintf (FILE, "\tdouble %.20e\n", (VALUE))
1109 /* This is how to output an assembler line defining a `float' constant. */
1111 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1112 fprintf (FILE, "\tfloat %.12e\n", (VALUE))
1114 /* Likewise for `short' and `char' constants. */
1116 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1117 ( fprintf (FILE, TARGET_UNIX_ASM ? "\t" : "\t.word "), \
1118 output_addr_const_pdp11 (FILE, (VALUE)), \
1119 fprintf (FILE, " /*short*/\n"))
1121 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1122 ( fprintf (FILE, "\t.byte "), \
1123 output_addr_const_pdp11 (FILE, (VALUE)), \
1124 fprintf (FILE, " /* char */\n"))
1126 /* This is how to output an assembler line for a numeric constant byte.
1127 This won't actually be used since we define ASM_OUTPUT_CHAR.
1130 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1131 fprintf (FILE, "\t.byte %o\n", (VALUE))
1133 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1134 output_ascii (FILE, P, SIZE)
1136 /* This is how to output an element of a case-vector that is absolute. */
1138 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1139 fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE)
1141 /* This is how to output an element of a case-vector that is relative.
1142 Don't define this if it is not supported. */
1144 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
1146 /* This is how to output an assembler line
1147 that says to advance the location counter
1148 to a multiple of 2**LOG bytes.
1153 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1159 fprintf (FILE, "\t.even\n"); \
1165 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1166 fprintf (FILE, "\t.=.+ %o\n", (SIZE))
1168 /* This says how to output an assembler line
1169 to define a global common symbol. */
1171 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1172 ( fprintf ((FILE), ".globl "), \
1173 assemble_name ((FILE), (NAME)), \
1174 fprintf ((FILE), "\n"), \
1175 assemble_name ((FILE), (NAME)), \
1176 fprintf ((FILE), ": .=.+ %o\n", (ROUNDED)) \
1179 /* This says how to output an assembler line
1180 to define a local common symbol. */
1182 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1183 ( assemble_name ((FILE), (NAME)), \
1184 fprintf ((FILE), ":\t.=.+ %o\n", (ROUNDED)))
1186 /* Store in OUTPUT a string (made with alloca) containing
1187 an assembler-name for a local static variable named NAME.
1188 LABELNO is an integer which is different for each call. */
1190 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1191 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1192 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1194 /* Define the parentheses used to group arithmetic operations
1195 in assembler code. */
1197 #define ASM_OPEN_PAREN "["
1198 #define ASM_CLOSE_PAREN "]"
1200 /* Define results of standard character escape sequences. */
1201 #define TARGET_BELL 007
1202 #define TARGET_BS 010
1203 #define TARGET_TAB 011
1204 #define TARGET_NEWLINE 012
1205 #define TARGET_VT 013
1206 #define TARGET_FF 014
1207 #define TARGET_CR 015
1209 /* Print operand X (an rtx) in assembler syntax to file FILE.
1210 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1211 For `%' followed by punctuation, CODE is the punctuation and X is null.
1216 #define PRINT_OPERAND(FILE, X, CODE) \
1217 { if (CODE == '#') fprintf (FILE, "#"); \
1218 else if (GET_CODE (X) == REG) \
1219 fprintf (FILE, "%s", reg_names[REGNO (X)]); \
1220 else if (GET_CODE (X) == MEM) \
1221 output_address (XEXP (X, 0)); \
1222 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \
1223 { union { double d; int i[2]; } u; \
1224 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1225 fprintf (FILE, "#%.20e", u.d); } \
1226 else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }}
1228 /* Print a memory address as an operand to reference that memory location. */
1230 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1231 print_operand_address (FILE, ADDR)
1233 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1235 fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \
1238 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1240 fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \
1244 #define ASM_IDENTIFY_GCC(FILE) \
1245 fprintf(FILE, "gcc_compiled:\n")
1247 /* trampoline - how should i do it in separate i+d ?
1248 have some allocate_trampoline magic???
1250 the following should work for shared I/D: */
1252 /* lets see whether this works as trampoline:
1253 MV #STATIC, $4 0x940Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1254 JMP FUNCTION 0x0058 0x0000 <- FUNCTION
1257 #define TRAMPOLINE_TEMPLATE(FILE) \
1262 ASM_OUTPUT_SHORT (FILE, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \
1263 ASM_OUTPUT_SHORT (FILE, const0_rtx); \
1264 ASM_OUTPUT_SHORT (FILE, GEN_INT(0x0058)); \
1265 ASM_OUTPUT_SHORT (FILE, const0_rtx); \
1268 #define TRAMPOLINE_SIZE 8
1269 #define TRAMPOLINE_ALIGN 16
1271 /* Emit RTL insns to initialize the variable parts of a trampoline.
1272 FNADDR is an RTX for the address of the function's pure code.
1273 CXT is an RTX for the static chain value for the function. */
1275 #define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \
1280 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 2)), CXT); \
1281 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), FNADDR); \
1285 /* Some machines may desire to change what optimizations are
1286 performed for various optimization levels. This macro, if
1287 defined, is executed once just after the optimization level is
1288 determined and before the remainder of the command options have
1289 been parsed. Values set in this macro are used as the default
1290 values for the other command line options.
1292 LEVEL is the optimization level specified; 2 if -O2 is
1293 specified, 1 if -O is specified, and 0 if neither is specified. */
1295 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
1300 flag_inline_functions = 1; \
1301 flag_omit_frame_pointer = 1; \
1302 /* flag_unroll_loops = 1; */ \
1307 /* Provide the costs of a rtl expression. This is in the body of a
1310 we don't say how expensive SImode is - pretty expensive!!!
1312 there is something wrong in MULT because MULT is not
1313 as cheap as total = 2 even if we can shift!
1315 if optimizing for size make mult etc cheap, but not 1, so when
1316 in doubt the faster insn is chosen.
1319 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1321 if (optimize_size) \
1322 total = COSTS_N_INSNS(2); \
1324 total = COSTS_N_INSNS (11); \
1327 if (optimize_size) \
1328 total = COSTS_N_INSNS(2); \
1330 total = COSTS_N_INSNS (25); \
1333 if (optimize_size) \
1334 total = COSTS_N_INSNS(2); \
1336 total = COSTS_N_INSNS (26); \
1339 /* equivalent to length, so same for optimize_size */ \
1340 total = COSTS_N_INSNS (3); \
1343 /* only used for: qi->hi */ \
1344 total = COSTS_N_INSNS(1); \
1347 if (GET_MODE(X) == HImode) \
1348 total = COSTS_N_INSNS(1); \
1349 else if (GET_MODE(X) == SImode) \
1350 total = COSTS_N_INSNS(6); \
1352 total = COSTS_N_INSNS(2); \
1354 /* case LSHIFT: */ \
1358 if (optimize_size) \
1359 total = COSTS_N_INSNS(1); \
1360 else if (GET_MODE(X) == QImode) \
1362 if (GET_CODE(XEXP (X,1)) != CONST_INT) \
1363 total = COSTS_N_INSNS(8); /* worst case */ \
1365 total = COSTS_N_INSNS(INTVAL(XEXP (X,1))); \
1367 else if (GET_MODE(X) == HImode) \
1369 if (GET_CODE(XEXP (X,1)) == CONST_INT) \
1371 if (abs (INTVAL (XEXP (X, 1))) == 1) \
1372 total = COSTS_N_INSNS(1); \
1374 total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \
1376 else /* worst case */ \
1377 total = COSTS_N_INSNS (10); \
1379 else if (GET_MODE(X) == SImode) \
1381 if (GET_CODE(XEXP (X,1)) == CONST_INT) \
1382 total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \
1383 else /* worst case */ \
1384 total = COSTS_N_INSNS(18); \
1389 /* there is no point in avoiding branches on a pdp,
1390 since branches are really cheap - I just want to find out
1391 how much difference the BRANCH_COST macro makes in code */
1392 #define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1)
1395 #define COMPARE_FLAG_MODE HImode