1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005,
3 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* this is the current value returned by the macro FIRST_PARM_OFFSET
47 int current_first_parm_offset;
49 /* Routines to encode/decode pdp11 floats */
50 static void encode_pdp11_f (const struct real_format *fmt,
51 long *, const REAL_VALUE_TYPE *);
52 static void decode_pdp11_f (const struct real_format *,
53 REAL_VALUE_TYPE *, const long *);
54 static void encode_pdp11_d (const struct real_format *fmt,
55 long *, const REAL_VALUE_TYPE *);
56 static void decode_pdp11_d (const struct real_format *,
57 REAL_VALUE_TYPE *, const long *);
59 /* These two are taken from the corresponding vax descriptors
60 in real.c, changing only the encode/decode routine pointers. */
61 const struct real_format pdp11_f_format =
82 const struct real_format pdp11_d_format =
104 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
105 const REAL_VALUE_TYPE *r)
107 (*vax_f_format.encode) (fmt, buf, r);
108 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
112 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED,
113 REAL_VALUE_TYPE *r, const long *buf)
116 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
117 (*vax_f_format.decode) (fmt, r, &tbuf);
121 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
122 const REAL_VALUE_TYPE *r)
124 (*vax_d_format.encode) (fmt, buf, r);
125 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
126 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
130 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED,
131 REAL_VALUE_TYPE *r, const long *buf)
134 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
135 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
136 (*vax_d_format.decode) (fmt, r, tbuf);
139 /* This is where the condition code register lives. */
140 /* rtx cc0_reg_rtx; - no longer needed? */
142 static bool pdp11_handle_option (struct gcc_options *, struct gcc_options *,
143 const struct cl_decoded_option *, location_t);
144 static void pdp11_option_init_struct (struct gcc_options *);
145 static const char *singlemove_string (rtx *);
146 static bool pdp11_assemble_integer (rtx, unsigned int, int);
147 static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT);
148 static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT);
149 static bool pdp11_rtx_costs (rtx, int, int, int *, bool);
150 static bool pdp11_return_in_memory (const_tree, const_tree);
151 static rtx pdp11_function_value (const_tree, const_tree, bool);
152 static rtx pdp11_libcall_value (enum machine_mode, const_rtx);
153 static bool pdp11_function_value_regno_p (const unsigned int);
154 static void pdp11_trampoline_init (rtx, tree, rtx);
155 static rtx pdp11_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
157 static void pdp11_function_arg_advance (CUMULATIVE_ARGS *,
158 enum machine_mode, const_tree, bool);
159 static void pdp11_conditional_register_usage (void);
160 static bool pdp11_legitimate_constant_p (enum machine_mode, rtx);
162 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
164 static const struct default_options pdp11_option_optimization_table[] =
166 { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
167 { OPT_LEVELS_NONE, 0, NULL, 0 }
170 /* Initialize the GCC target structure. */
171 #undef TARGET_ASM_BYTE_OP
172 #define TARGET_ASM_BYTE_OP NULL
173 #undef TARGET_ASM_ALIGNED_HI_OP
174 #define TARGET_ASM_ALIGNED_HI_OP NULL
175 #undef TARGET_ASM_ALIGNED_SI_OP
176 #define TARGET_ASM_ALIGNED_SI_OP NULL
177 #undef TARGET_ASM_INTEGER
178 #define TARGET_ASM_INTEGER pdp11_assemble_integer
180 #undef TARGET_ASM_FUNCTION_PROLOGUE
181 #define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue
182 #undef TARGET_ASM_FUNCTION_EPILOGUE
183 #define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue
185 #undef TARGET_ASM_OPEN_PAREN
186 #define TARGET_ASM_OPEN_PAREN "["
187 #undef TARGET_ASM_CLOSE_PAREN
188 #define TARGET_ASM_CLOSE_PAREN "]"
190 #undef TARGET_DEFAULT_TARGET_FLAGS
191 #define TARGET_DEFAULT_TARGET_FLAGS \
192 (MASK_FPU | MASK_45 | TARGET_UNIX_ASM_DEFAULT)
193 #undef TARGET_HANDLE_OPTION
194 #define TARGET_HANDLE_OPTION pdp11_handle_option
195 #undef TARGET_OPTION_OPTIMIZATION_TABLE
196 #define TARGET_OPTION_OPTIMIZATION_TABLE pdp11_option_optimization_table
197 #undef TARGET_OPTION_INIT_STRUCT
198 #define TARGET_OPTION_INIT_STRUCT pdp11_option_init_struct
200 #undef TARGET_RTX_COSTS
201 #define TARGET_RTX_COSTS pdp11_rtx_costs
203 #undef TARGET_FUNCTION_ARG
204 #define TARGET_FUNCTION_ARG pdp11_function_arg
205 #undef TARGET_FUNCTION_ARG_ADVANCE
206 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
208 #undef TARGET_RETURN_IN_MEMORY
209 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
211 #undef TARGET_FUNCTION_VALUE
212 #define TARGET_FUNCTION_VALUE pdp11_function_value
213 #undef TARGET_LIBCALL_VALUE
214 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
215 #undef TARGET_FUNCTION_VALUE_REGNO_P
216 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
218 #undef TARGET_TRAMPOLINE_INIT
219 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
221 #undef TARGET_SECONDARY_RELOAD
222 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
224 #undef TARGET_REGISTER_MOVE_COST
225 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
227 #undef TARGET_PREFERRED_RELOAD_CLASS
228 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
230 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
231 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
233 #undef TARGET_LEGITIMATE_ADDRESS_P
234 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
236 #undef TARGET_CONDITIONAL_REGISTER_USAGE
237 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
239 #undef TARGET_ASM_FUNCTION_SECTION
240 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
242 #undef TARGET_PRINT_OPERAND
243 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand
245 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
246 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p
248 #undef TARGET_LEGITIMATE_CONSTANT_P
249 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p
251 /* Implement TARGET_HANDLE_OPTION. */
254 pdp11_handle_option (struct gcc_options *opts,
255 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
256 const struct cl_decoded_option *decoded,
257 location_t loc ATTRIBUTE_UNUSED)
259 size_t code = decoded->opt_index;
264 opts->x_target_flags &= ~(MASK_40 | MASK_45);
272 /* Implement TARGET_OPTION_INIT_STRUCT. */
275 pdp11_option_init_struct (struct gcc_options *opts)
277 opts->x_flag_finite_math_only = 0;
278 opts->x_flag_trapping_math = 0;
279 opts->x_flag_signaling_nans = 0;
283 stream is a stdio stream to output the code to.
284 size is an int: how many units of temporary storage to allocate.
285 Refer to the array `regs_ever_live' to determine which registers
286 to save; `regs_ever_live[I]' is nonzero if register number I
287 is ever used in the function. This macro is responsible for
288 knowing which registers should not be saved even if used.
292 pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
294 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
299 "\n\t; /* function prologue %s*/\n",
300 current_function_name ());
302 /* if we are outputting code for main,
303 the switch FPU to right mode if TARGET_FPU */
304 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU)
307 "\t;/* switch cpu to double float, single integer */\n");
308 fprintf(stream, "\tsetd\n");
309 fprintf(stream, "\tseti\n\n");
312 if (frame_pointer_needed)
314 fprintf(stream, "\tmov r5, -(sp)\n");
315 fprintf(stream, "\tmov sp, r5\n");
324 asm_fprintf (stream, "\tsub $%#wo, sp\n", fsize);
326 /* save CPU registers */
327 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++)
328 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
329 if (! ((regno == FRAME_POINTER_REGNUM)
330 && frame_pointer_needed))
331 fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]);
332 /* fpu regs saving */
334 /* via_ac specifies the ac to use for saving ac4, ac5 */
337 for (regno = AC0_REGNUM; regno <= AC5_REGNUM ; regno++)
340 if (LOAD_FPU_REG_P(regno)
341 && df_regs_ever_live_p (regno)
342 && ! call_used_regs[regno])
344 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[regno]);
348 /* maybe make ac4, ac5 call used regs?? */
350 if (NO_LOAD_FPU_REG_P(regno)
351 && df_regs_ever_live_p (regno)
352 && ! call_used_regs[regno])
354 gcc_assert (via_ac != -1);
355 fprintf (stream, "\tldd %s, %s\n",
356 reg_names[regno], reg_names[via_ac]);
357 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[via_ac]);
361 fprintf (stream, "\t;/* end of prologue */\n\n");
365 The function epilogue should not depend on the current stack pointer!
366 It should use the frame pointer only. This is mandatory because
367 of alloca; we also take advantage of it to omit stack adjustments
370 /* maybe we can make leaf functions faster by switching to the
371 second register file - this way we don't have to save regs!
372 leaf functions are ~ 50% of all functions (dynamically!)
374 set/clear bit 11 (dec. 2048) of status word for switching register files -
375 but how can we do this? the pdp11/45 manual says bit may only
376 be set (p.24), but not cleared!
378 switching to kernel is probably more expensive, so we'll leave it
379 like this and not use the second set of registers...
381 maybe as option if you want to generate code for kernel mode? */
384 pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
386 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
391 fprintf (stream, "\n\t; /*function epilogue */\n");
393 if (frame_pointer_needed)
395 /* hope this is safe - m68k does it also .... */
396 df_set_regs_ever_live (FRAME_POINTER_REGNUM, false);
398 for (i = PC_REGNUM, j = 0 ; i >= 0 ; i--)
399 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
402 /* remember # of pushed bytes for CPU regs */
405 /* change fp -> r5 due to the compile error on libgcc2.c */
406 for (i = PC_REGNUM ; i >= R0_REGNUM ; i--)
407 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
408 fprintf(stream, "\tmov %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
409 (-fsize-2*j--)&0xffff, reg_names[i]);
414 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
415 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
421 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
423 if (LOAD_FPU_REG_P(i)
424 && df_regs_ever_live_p (i)
425 && ! call_used_regs[i])
427 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
428 (-fsize-k)&0xffff, reg_names[i]);
432 if (NO_LOAD_FPU_REG_P(i)
433 && df_regs_ever_live_p (i)
434 && ! call_used_regs[i])
436 gcc_assert (LOAD_FPU_REG_P(via_ac));
438 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
439 (-fsize-k)&0xffff, reg_names[via_ac]);
440 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
445 fprintf(stream, "\tmov r5, sp\n");
446 fprintf (stream, "\tmov (sp)+, r5\n");
453 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
454 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
457 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
459 if (LOAD_FPU_REG_P(i)
460 && df_regs_ever_live_p (i)
461 && ! call_used_regs[i])
462 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[i]);
464 if (NO_LOAD_FPU_REG_P(i)
465 && df_regs_ever_live_p (i)
466 && ! call_used_regs[i])
468 gcc_assert (LOAD_FPU_REG_P(via_ac));
470 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[via_ac]);
471 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
475 for (i = PC_REGNUM; i >= 0; i--)
476 if (df_regs_ever_live_p (i) && !call_used_regs[i])
477 fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]);
480 fprintf((stream), "\tadd $%#" HOST_WIDE_INT_PRINT "o, sp\n",
484 fprintf (stream, "\trts pc\n");
485 fprintf (stream, "\t;/* end of epilogue*/\n\n\n");
488 /* Return the best assembler insn template
489 for moving operands[1] into operands[0] as a fullword. */
491 singlemove_string (rtx *operands)
493 if (operands[1] != const0_rtx)
500 /* Expand multi-word operands (SImode or DImode) into the 2 or 4
501 corresponding HImode operands. The number of operands is given
502 as the third argument, and the required order of the parts as
503 the fourth argument. */
505 pdp11_expand_operands (rtx *operands, rtx exops[][2], int opcount,
506 pdp11_action *action, pdp11_partorder order)
508 int words, op, w, i, sh;
509 pdp11_partorder useorder;
510 bool sameoff = false;
511 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype;
515 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16;
517 /* If either piece order is accepted and one is pre-decrement
518 while the other is post-increment, set order to be high order
519 word first. That will force the pre-decrement to be turned
520 into a pointer adjust, then offset addressing.
521 Otherwise, if either operand uses pre-decrement, that means
522 the order is low order first.
523 Otherwise, if both operands are registers and destination is
524 higher than source and they overlap, do low order word (highest
525 register number) first. */
529 if (!REG_P (operands[0]) && !REG_P (operands[1]) &&
530 !(CONSTANT_P (operands[1]) ||
531 GET_CODE (operands[1]) == CONST_DOUBLE) &&
532 ((GET_CODE (XEXP (operands[0], 0)) == POST_INC &&
533 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) ||
534 (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC &&
535 GET_CODE (XEXP (operands[1], 0)) == POST_INC)))
537 else if ((!REG_P (operands[0]) &&
538 GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ||
539 (!REG_P (operands[1]) &&
540 !(CONSTANT_P (operands[1]) ||
541 GET_CODE (operands[1]) == CONST_DOUBLE) &&
542 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
544 else if (REG_P (operands[0]) && REG_P (operands[1]) &&
545 REGNO (operands[0]) > REGNO (operands[1]) &&
546 REGNO (operands[0]) < REGNO (operands[1]) + words)
549 /* Check for source == offset from register and dest == push of
550 the same register. In that case, we have to use the same
551 offset (the one for the low order word) for all words, because
552 the push increases the offset to each source word.
553 In theory there are other cases like this, for example dest == pop,
554 but those don't occur in real life so ignore those. */
555 if (GET_CODE (operands[0]) == MEM
556 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
557 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
558 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
562 /* If the caller didn't specify order, use the one we computed,
563 or high word first if we don't care either. If the caller did
564 specify, verify we don't have a problem with that order.
565 (If it matters to the caller, constraints need to be used to
566 ensure this case doesn't occur). */
568 order = (useorder == either) ? big : useorder;
570 gcc_assert (useorder == either || useorder == order);
573 for (op = 0; op < opcount; op++)
575 /* First classify the operand. */
576 if (REG_P (operands[op]))
578 else if (CONSTANT_P (operands[op])
579 || GET_CODE (operands[op]) == CONST_DOUBLE)
581 else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC)
583 else if (GET_CODE (XEXP (operands[op], 0)) == PRE_DEC)
585 else if (!reload_in_progress || offsettable_memref_p (operands[op]))
587 else if (GET_CODE (operands[op]) == MEM)
592 /* Check for the cases that the operand constraints are not
593 supposed to allow to happen. Return failure for such cases. */
598 action[op] = no_action;
600 /* If the operand uses pre-decrement addressing but we
601 want to get the parts high order first,
602 decrement the former register explicitly
603 and change the operand into ordinary indexing. */
604 if (optype == PUSHOP && order == big)
606 gcc_assert (action != NULL);
607 action[op] = dec_before;
608 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]),
609 XEXP (XEXP (operands[op], 0), 0));
612 /* If the operand uses post-increment mode but we want
613 to get the parts low order first, change the operand
614 into ordinary indexing and remember to increment
615 the register explicitly when we're done. */
616 else if (optype == POPOP && order == little)
618 gcc_assert (action != NULL);
619 action[op] = inc_after;
620 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]),
621 XEXP (XEXP (operands[op], 0), 0));
625 if (GET_CODE (operands[op]) == CONST_DOUBLE)
627 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[op]);
628 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
631 for (i = 0; i < words; i++)
640 /* Set the output operand to be word "w" of the input. */
642 exops[i][op] = gen_rtx_REG (HImode, REGNO (operands[op]) + w);
643 else if (optype == OFFSOP)
644 exops[i][op] = adjust_address (operands[op], HImode, w * 2);
645 else if (optype == CNSTOP)
647 if (GET_CODE (operands[op]) == CONST_DOUBLE)
649 sh = 16 - (w & 1) * 16;
650 exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff);
654 sh = ((words - 1 - w) * 16);
655 exops[i][op] = gen_rtx_CONST_INT (HImode, trunc_int_for_mode (INTVAL(operands[op]) >> sh, HImode));
659 exops[i][op] = operands[op];
665 /* Output assembler code to perform a multiple-word move insn
666 with operands OPERANDS. This moves 2 or 4 words depending
667 on the machine mode of the operands. */
670 output_move_multiple (rtx *operands)
673 pdp11_action action[2];
676 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16;
678 pdp11_expand_operands (operands, exops, 2, action, either);
680 /* Check for explicit decrement before. */
681 if (action[0] == dec_before)
683 operands[0] = XEXP (operands[0], 0);
684 output_asm_insn ("sub $4,%0", operands);
686 if (action[1] == dec_before)
688 operands[1] = XEXP (operands[1], 0);
689 output_asm_insn ("sub $4,%1", operands);
693 for (i = 0; i < words; i++)
694 output_asm_insn (singlemove_string (exops[i]), exops[i]);
696 /* Check for increment after. */
697 if (action[0] == inc_after)
699 operands[0] = XEXP (operands[0], 0);
700 output_asm_insn ("add $4,%0", operands);
702 if (action[1] == inc_after)
704 operands[1] = XEXP (operands[1], 0);
705 output_asm_insn ("add $4,%1", operands);
711 /* Output an ascii string. */
713 output_ascii (FILE *file, const char *p, int size)
717 /* This used to output .byte "string", which doesn't work with the UNIX
718 assembler and I think not with DEC ones either. */
719 fprintf (file, "\t.byte ");
721 for (i = 0; i < size; i++)
723 register int c = p[i];
726 fprintf (file, "%#o", c);
735 pdp11_asm_output_var (FILE *file, const char *name, int size,
736 int align, bool global)
739 fprintf (file, "\n\t.even\n");
742 fprintf (file, ".globl ");
743 assemble_name (file, name);
745 fprintf (file, "\n");
746 assemble_name (file, name);
747 fprintf (file, ": .=.+ %#ho\n", (unsigned short)size);
751 pdp11_asm_print_operand (FILE *file, rtx x, int code)
758 else if (code == '@')
765 else if (GET_CODE (x) == REG)
766 fprintf (file, "%s", reg_names[REGNO (x)]);
767 else if (GET_CODE (x) == MEM)
768 output_address (XEXP (x, 0));
769 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != SImode)
771 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
772 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
773 fprintf (file, "$%#lo", sval[0] >> 16);
778 output_addr_const_pdp11 (file, x);
783 pdp11_asm_print_operand_punct_valid_p (unsigned char c)
785 return (c == '#' || c == '@');
789 print_operand_address (FILE *file, register rtx addr)
797 switch (GET_CODE (addr))
804 addr = XEXP (addr, 0);
809 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
814 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
819 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
825 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
826 || GET_CODE (XEXP (addr, 0)) == MEM)
828 offset = XEXP (addr, 0);
829 addr = XEXP (addr, 1);
831 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
832 || GET_CODE (XEXP (addr, 1)) == MEM)
834 offset = XEXP (addr, 1);
835 addr = XEXP (addr, 0);
837 if (GET_CODE (addr) != PLUS)
839 else if (GET_CODE (XEXP (addr, 0)) == REG)
841 breg = XEXP (addr, 0);
842 addr = XEXP (addr, 1);
844 else if (GET_CODE (XEXP (addr, 1)) == REG)
846 breg = XEXP (addr, 1);
847 addr = XEXP (addr, 0);
849 if (GET_CODE (addr) == REG)
851 gcc_assert (breg == 0);
857 gcc_assert (addr == 0);
861 output_addr_const_pdp11 (file, addr);
864 gcc_assert (GET_CODE (breg) == REG);
865 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
870 if (!again && GET_CODE (addr) == CONST_INT)
872 /* Absolute (integer number) address. */
873 if (!TARGET_UNIX_ASM)
874 fprintf (file, "@$");
876 output_addr_const_pdp11 (file, addr);
880 /* Target hook to assemble integer objects. We need to use the
881 pdp-specific version of output_addr_const. */
884 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p)
890 fprintf (asm_out_file, "\t.byte\t");
891 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff));
893 fprintf (asm_out_file, " /* char */\n");
897 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t");
898 output_addr_const_pdp11 (asm_out_file, x);
899 fprintf (asm_out_file, " /* short */\n");
902 return default_assemble_integer (x, size, aligned_p);
906 /* register move costs, indexed by regs */
908 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
910 /* NO MUL GEN LFPU NLFPU FPU ALL */
912 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
913 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
914 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
915 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
916 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
917 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
918 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
922 /* -- note that some moves are tremendously expensive,
923 because they require lots of tricks! do we have to
924 charge the costs incurred by secondary reload class
925 -- as we do here with 10 -- or not ? */
928 pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
929 reg_class_t c1, reg_class_t c2)
931 return move_costs[(int)c1][(int)c2];
935 pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
936 bool speed ATTRIBUTE_UNUSED)
941 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1)
951 /* Twice as expensive as REG. */
956 /* Twice (or 4 times) as expensive as 16 bit. */
961 /* ??? There is something wrong in MULT because MULT is not
962 as cheap as total = 2 even if we can shift! */
963 /* If optimizing for size make mult etc cheap, but not 1, so when
964 in doubt the faster insn is chosen. */
966 *total = COSTS_N_INSNS (2);
968 *total = COSTS_N_INSNS (11);
973 *total = COSTS_N_INSNS (2);
975 *total = COSTS_N_INSNS (25);
980 *total = COSTS_N_INSNS (2);
982 *total = COSTS_N_INSNS (26);
986 /* Equivalent to length, so same for optimize_size. */
987 *total = COSTS_N_INSNS (3);
991 /* Only used for qi->hi. */
992 *total = COSTS_N_INSNS (1);
996 if (GET_MODE (x) == HImode)
997 *total = COSTS_N_INSNS (1);
998 else if (GET_MODE (x) == SImode)
999 *total = COSTS_N_INSNS (6);
1001 *total = COSTS_N_INSNS (2);
1008 *total = COSTS_N_INSNS (1);
1009 else if (GET_MODE (x) == QImode)
1011 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1012 *total = COSTS_N_INSNS (8); /* worst case */
1014 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
1016 else if (GET_MODE (x) == HImode)
1018 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1020 if (abs (INTVAL (XEXP (x, 1))) == 1)
1021 *total = COSTS_N_INSNS (1);
1023 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1026 *total = COSTS_N_INSNS (10); /* worst case */
1028 else if (GET_MODE (x) == SImode)
1030 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1031 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1032 else /* worst case */
1033 *total = COSTS_N_INSNS (18);
1043 output_jump (enum rtx_code code, int inv, int length)
1047 static char buf[1000];
1048 const char *pos, *neg;
1050 if (cc_prev_status.flags & CC_NO_OVERFLOW)
1054 case GTU: code = GT; break;
1055 case LTU: code = LT; break;
1056 case GEU: code = GE; break;
1057 case LEU: code = LE; break;
1063 case EQ: pos = "beq", neg = "bne"; break;
1064 case NE: pos = "bne", neg = "beq"; break;
1065 case GT: pos = "bgt", neg = "ble"; break;
1066 case GTU: pos = "bhi", neg = "blos"; break;
1067 case LT: pos = "blt", neg = "bge"; break;
1068 case LTU: pos = "blo", neg = "bhis"; break;
1069 case GE: pos = "bge", neg = "blt"; break;
1070 case GEU: pos = "bhis", neg = "blo"; break;
1071 case LE: pos = "ble", neg = "bgt"; break;
1072 case LEU: pos = "blos", neg = "bhi"; break;
1073 default: gcc_unreachable ();
1077 /* currently we don't need this, because the tstdf and cmpdf
1078 copy the condition code immediately, and other float operations are not
1079 yet recognized as changing the FCC - if so, then the length-cost of all
1080 jump insns increases by one, because we have to potentially copy the
1082 if (cc_status.flags & CC_IN_FPU)
1083 output_asm_insn("cfcc", NULL);
1090 sprintf(buf, "%s %%l1", inv ? neg : pos);
1096 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x);
1110 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED)
1112 if (GET_CODE (SET_DEST (exp)) == CC0)
1114 cc_status.flags = 0;
1115 cc_status.value1 = SET_DEST (exp);
1116 cc_status.value2 = SET_SRC (exp);
1118 else if (GET_CODE (SET_SRC (exp)) == CALL)
1122 else if (SET_DEST(exp) == pc_rtx)
1126 else if (GET_MODE (SET_DEST(exp)) == HImode
1127 || GET_MODE (SET_DEST(exp)) == QImode)
1129 cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW;
1130 cc_status.value1 = SET_SRC (exp);
1131 cc_status.value2 = SET_DEST (exp);
1133 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
1135 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
1136 cc_status.value2 = 0;
1137 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
1139 && GET_CODE (cc_status.value2) == MEM)
1140 cc_status.value2 = 0;
1150 simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1154 /* Eliminate non-memory operations */
1155 if (GET_CODE (op) != MEM)
1159 /* dword operations really put out 2 instructions, so eliminate them. */
1160 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4))
1164 /* Decode the address now. */
1168 addr = XEXP (op, 0);
1170 switch (GET_CODE (addr))
1173 /* (R0) - no extra cost */
1178 /* -(R0), (R0)+ - cheap! */
1182 /* cheap - is encoded in addressing mode info!
1184 -- except for @(R0), which has to be @0(R0) !!! */
1186 if (GET_CODE (XEXP (addr, 0)) == REG)
1196 /* @#address - extra cost */
1200 /* X(R0) - extra cost */
1212 * output a block move:
1214 * operands[0] ... to
1215 * operands[1] ... from
1216 * operands[2] ... length
1217 * operands[3] ... alignment
1218 * operands[4] ... scratch register
1223 output_block_move(rtx *operands)
1225 static int count = 0;
1230 /* Move of zero bytes is a NOP. */
1231 if (operands[2] == const0_rtx)
1234 /* Look for moves by small constant byte counts, those we'll
1235 expand to straight line code. */
1236 if (CONSTANT_P (operands[2]))
1238 if (INTVAL (operands[2]) < 16
1239 && (!optimize_size || INTVAL (operands[2]) < 5)
1240 && INTVAL (operands[3]) == 1)
1244 for (i = 1; i <= INTVAL (operands[2]); i++)
1245 output_asm_insn("movb (%1)+, (%0)+", operands);
1249 else if (INTVAL(operands[2]) < 32
1250 && (!optimize_size || INTVAL (operands[2]) < 9)
1251 && INTVAL (operands[3]) >= 2)
1255 for (i = 1; i <= INTVAL (operands[2]) / 2; i++)
1256 output_asm_insn ("mov (%1)+, (%0)+", operands);
1257 if (INTVAL (operands[2]) & 1)
1258 output_asm_insn ("movb (%1), (%0)", operands);
1264 /* Ideally we'd look for moves that are multiples of 4 or 8
1265 bytes and handle those by unrolling the move loop. That
1266 makes for a lot of code if done at run time, but it's ok
1267 for constant counts. Also, for variable counts we have
1268 to worry about odd byte count with even aligned pointers.
1269 On 11/40 and up we handle that case; on older machines
1270 we don't and just use byte-wise moves all the time. */
1272 if (CONSTANT_P (operands[2]) )
1274 if (INTVAL (operands[3]) < 2)
1278 lastbyte = INTVAL (operands[2]) & 1;
1280 if (optimize_size || INTVAL (operands[2]) & 2)
1282 else if (INTVAL (operands[2]) & 4)
1288 /* Loop count is byte count scaled by unroll. */
1289 operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll);
1290 output_asm_insn ("mov %2, %4", operands);
1294 /* Variable byte count; use the input register
1296 operands[4] = operands[2];
1298 /* Decide whether to move by words, and check
1299 the byte count for zero. */
1300 if (TARGET_40_PLUS && INTVAL (operands[3]) > 1)
1303 output_asm_insn ("asr %4", operands);
1308 output_asm_insn ("tst %4", operands);
1310 sprintf (buf, "beq movestrhi%d", count + 1);
1311 output_asm_insn (buf, NULL);
1314 /* Output the loop label. */
1315 sprintf (buf, "\nmovestrhi%d:", count);
1316 output_asm_insn (buf, NULL);
1318 /* Output the appropriate move instructions. */
1322 output_asm_insn ("movb (%1)+, (%0)+", operands);
1326 output_asm_insn ("mov (%1)+, (%0)+", operands);
1330 output_asm_insn ("mov (%1)+, (%0)+", operands);
1331 output_asm_insn ("mov (%1)+, (%0)+", operands);
1335 output_asm_insn ("mov (%1)+, (%0)+", operands);
1336 output_asm_insn ("mov (%1)+, (%0)+", operands);
1337 output_asm_insn ("mov (%1)+, (%0)+", operands);
1338 output_asm_insn ("mov (%1)+, (%0)+", operands);
1342 /* Output the decrement and test. */
1345 sprintf (buf, "sob %%4, movestrhi%d", count);
1346 output_asm_insn (buf, operands);
1350 output_asm_insn ("dec %4", operands);
1351 sprintf (buf, "bgt movestrhi%d", count);
1352 output_asm_insn (buf, NULL);
1356 /* If constant odd byte count, move the last byte. */
1358 output_asm_insn ("movb (%1), (%0)", operands);
1359 else if (!CONSTANT_P (operands[2]))
1361 /* Output the destination label for the zero byte count check. */
1362 sprintf (buf, "\nmovestrhi%d:", count);
1363 output_asm_insn (buf, NULL);
1366 /* If we did word moves, check for trailing last byte. */
1369 sprintf (buf, "bcc movestrhi%d", count);
1370 output_asm_insn (buf, NULL);
1371 output_asm_insn ("movb (%1), (%0)", operands);
1372 sprintf (buf, "\nmovestrhi%d:", count);
1373 output_asm_insn (buf, NULL);
1381 /* This function checks whether a real value can be encoded as
1382 a literal, i.e., addressing mode 27. In that mode, real values
1383 are one word values, so the remaining 48 bits have to be zero. */
1385 legitimate_const_double_p (rtx address)
1389 REAL_VALUE_FROM_CONST_DOUBLE (r, address);
1390 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
1391 if ((sval[0] & 0xffff) == 0 && sval[1] == 0)
1396 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1398 pdp11_cannot_change_mode_class (enum machine_mode from,
1399 enum machine_mode to,
1400 enum reg_class rclass)
1402 /* Also, FPU registers contain a whole float value and the parts of
1403 it are not separately accessible.
1405 So we disallow all mode changes involving FPRs. */
1406 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to))
1409 return reg_classes_intersect_p (FPU_REGS, rclass);
1412 /* TARGET_PREFERRED_RELOAD_CLASS
1414 Given an rtx X being reloaded into a reg required to be
1415 in class CLASS, return the class of reg to actually use.
1416 In general this is just CLASS; but on some machines
1417 in some cases it is preferable to use a more restrictive class.
1419 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1422 pdp11_preferred_reload_class (rtx x, reg_class_t rclass)
1424 if (rclass == FPU_REGS)
1425 return LOAD_FPU_REGS;
1426 if (rclass == ALL_REGS)
1428 if (FLOAT_MODE_P (GET_MODE (x)))
1429 return LOAD_FPU_REGS;
1431 return GENERAL_REGS;
1436 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1438 Given an rtx X being reloaded into a reg required to be
1439 in class CLASS, return the class of reg to actually use.
1440 In general this is just CLASS; but on some machines
1441 in some cases it is preferable to use a more restrictive class.
1443 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1446 pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass)
1448 if (rclass == FPU_REGS)
1449 return LOAD_FPU_REGS;
1450 if (rclass == ALL_REGS)
1452 if (FLOAT_MODE_P (GET_MODE (x)))
1453 return LOAD_FPU_REGS;
1455 return GENERAL_REGS;
1461 /* TARGET_SECONDARY_RELOAD.
1463 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1464 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1465 can be loade/stored directly. */
1467 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
1469 reg_class_t reload_class,
1470 enum machine_mode reload_mode ATTRIBUTE_UNUSED,
1471 secondary_reload_info *sri ATTRIBUTE_UNUSED)
1473 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
1474 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
1477 return LOAD_FPU_REGS;
1480 /* Target routine to check if register to register move requires memory.
1482 The answer is yes if we're going between general register and FPU
1483 registers. The mode doesn't matter in making this check.
1486 pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2,
1487 enum machine_mode mode ATTRIBUTE_UNUSED)
1489 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS ||
1491 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS ||
1494 return (fromfloat != tofloat);
1497 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1498 that is a valid memory address for an instruction.
1499 The MODE argument is the machine mode for the MEM expression
1500 that wants to use this address.
1505 pdp11_legitimate_address_p (enum machine_mode mode,
1506 rtx operand, bool strict)
1510 /* accept @#address */
1511 if (CONSTANT_ADDRESS_P (operand))
1514 switch (GET_CODE (operand))
1518 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand));
1522 return GET_CODE (XEXP (operand, 0)) == REG
1523 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))))
1524 && CONSTANT_ADDRESS_P (XEXP (operand, 1));
1528 return GET_CODE (XEXP (operand, 0)) == REG
1529 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1533 return GET_CODE (XEXP (operand, 0)) == REG
1534 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1537 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1538 return GET_CODE (XEXP (operand, 0)) == REG
1539 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1540 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1541 && GET_CODE (XEXP (xfoob, 0)) == REG
1542 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1543 && CONSTANT_P (XEXP (xfoob, 1))
1544 && INTVAL (XEXP (xfoob,1)) == -2;
1547 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1548 return GET_CODE (XEXP (operand, 0)) == REG
1549 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1550 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1551 && GET_CODE (XEXP (xfoob, 0)) == REG
1552 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1553 && CONSTANT_P (XEXP (xfoob, 1))
1554 && INTVAL (XEXP (xfoob,1)) == 2;
1557 /* handle another level of indirection ! */
1558 xfoob = XEXP (operand, 0);
1560 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1561 also forbidden for float, because we have to handle this
1562 in output_move_double and/or output_move_quad() - we could
1563 do it, but currently it's not worth it!!!
1564 now that DFmode cannot go into CPU register file,
1565 maybe I should allow float ...
1566 but then I have to handle memory-to-memory moves in movdf ?? */
1567 if (GET_MODE_BITSIZE(mode) > 16)
1570 /* accept @address */
1571 if (CONSTANT_ADDRESS_P (xfoob))
1574 switch (GET_CODE (xfoob))
1577 /* accept @(R0) - which is @0(R0) */
1578 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob));
1582 return GET_CODE (XEXP (xfoob, 0)) == REG
1583 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))))
1584 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1));
1588 return GET_CODE (XEXP (xfoob, 0)) == REG
1589 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1593 return GET_CODE (XEXP (xfoob, 0)) == REG
1594 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1597 /* anything else is invalid */
1602 /* anything else is invalid */
1607 /* Return the class number of the smallest class containing
1608 reg number REGNO. */
1610 pdp11_regno_reg_class (int regno)
1612 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1613 return GENERAL_REGS;
1614 else if (regno > AC3_REGNUM)
1615 return NO_LOAD_FPU_REGS;
1616 else if (regno >= AC0_REGNUM)
1617 return LOAD_FPU_REGS;
1621 return GENERAL_REGS;
1626 pdp11_sp_frame_offset (void)
1628 int offset = 0, regno;
1629 offset = get_frame_size();
1630 for (regno = 0; regno <= PC_REGNUM; regno++)
1631 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1633 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++)
1634 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1640 /* Return the offset between two registers, one to be eliminated, and the other
1641 its replacement, at the start of a routine. */
1644 pdp11_initial_elimination_offset (int from, int to)
1648 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
1650 else if (from == FRAME_POINTER_REGNUM
1651 && to == HARD_FRAME_POINTER_REGNUM)
1655 gcc_assert (to == STACK_POINTER_REGNUM);
1657 /* Get the size of the register save area. */
1658 spoff = pdp11_sp_frame_offset ();
1659 if (from == FRAME_POINTER_REGNUM)
1662 gcc_assert (from == ARG_POINTER_REGNUM);
1664 /* If there is a frame pointer, that is saved too. */
1665 if (frame_pointer_needed)
1668 /* Account for the saved PC in the function call. */
1673 /* A copy of output_addr_const modified for pdp11 expression syntax.
1674 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1675 use, and for debugging output, which we don't support with this port either.
1676 So this copy should get called whenever needed.
1679 output_addr_const_pdp11 (FILE *file, rtx x)
1685 switch (GET_CODE (x))
1688 gcc_assert (flag_pic);
1693 assemble_name (file, XSTR (x, 0));
1697 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0)));
1698 assemble_name (file, buf);
1702 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1703 assemble_name (file, buf);
1711 fprintf (file, "-");
1713 fprintf (file, "%#o", i & 0xffff);
1717 /* This used to output parentheses around the expression,
1718 but that does not work on the 386 (either ATT or BSD assembler). */
1719 output_addr_const_pdp11 (file, XEXP (x, 0));
1723 if (GET_MODE (x) == VOIDmode)
1725 /* We can use %o if the number is one word and positive. */
1726 gcc_assert (!CONST_DOUBLE_HIGH (x));
1727 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x));
1730 /* We can't handle floating point constants;
1731 PRINT_OPERAND must handle them. */
1732 output_operand_lossage ("floating constant misused");
1736 /* Some assemblers need integer constants to appear last (e.g. masm). */
1737 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1739 output_addr_const_pdp11 (file, XEXP (x, 1));
1740 if (INTVAL (XEXP (x, 0)) >= 0)
1741 fprintf (file, "+");
1742 output_addr_const_pdp11 (file, XEXP (x, 0));
1746 output_addr_const_pdp11 (file, XEXP (x, 0));
1747 if (INTVAL (XEXP (x, 1)) >= 0)
1748 fprintf (file, "+");
1749 output_addr_const_pdp11 (file, XEXP (x, 1));
1754 /* Avoid outputting things like x-x or x+5-x,
1755 since some assemblers can't handle that. */
1756 x = simplify_subtraction (x);
1757 if (GET_CODE (x) != MINUS)
1760 output_addr_const_pdp11 (file, XEXP (x, 0));
1761 if (GET_CODE (XEXP (x, 1)) != CONST_INT
1762 || INTVAL (XEXP (x, 1)) >= 0)
1763 fprintf (file, "-");
1764 output_addr_const_pdp11 (file, XEXP (x, 1));
1769 output_addr_const_pdp11 (file, XEXP (x, 0));
1773 output_operand_lossage ("invalid expression as operand");
1777 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1780 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1782 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1783 in registers. The rest go into memory. */
1784 return (TYPE_MODE (type) == DImode
1785 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0)
1786 || TREE_CODE (type) == VECTOR_TYPE
1787 || COMPLEX_MODE_P (TYPE_MODE (type)));
1790 /* Worker function for TARGET_FUNCTION_VALUE.
1792 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1795 pdp11_function_value (const_tree valtype,
1796 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
1797 bool outgoing ATTRIBUTE_UNUSED)
1799 return gen_rtx_REG (TYPE_MODE (valtype),
1800 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype)));
1803 /* Worker function for TARGET_LIBCALL_VALUE. */
1806 pdp11_libcall_value (enum machine_mode mode,
1807 const_rtx fun ATTRIBUTE_UNUSED)
1809 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode));
1812 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1814 On the pdp, the first "output" reg is the only register thus used.
1816 maybe ac0 ? - as option someday! */
1819 pdp11_function_value_regno_p (const unsigned int regno)
1821 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM));
1824 /* Worker function for TARGET_TRAMPOLINE_INIT.
1826 trampoline - how should i do it in separate i+d ?
1827 have some allocate_trampoline magic???
1829 the following should work for shared I/D:
1831 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1832 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
1836 pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
1838 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
1841 gcc_assert (!TARGET_SPLIT);
1843 mem = adjust_address (m_tramp, HImode, 0);
1844 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM));
1845 mem = adjust_address (m_tramp, HImode, 2);
1846 emit_move_insn (mem, chain_value);
1847 mem = adjust_address (m_tramp, HImode, 4);
1848 emit_move_insn (mem, GEN_INT (000137));
1849 emit_move_insn (mem, fnaddr);
1852 /* Worker function for TARGET_FUNCTION_ARG.
1854 Determine where to put an argument to a function.
1855 Value is zero to push the argument on the stack,
1856 or a hard register in which to store the argument.
1858 MODE is the argument's machine mode.
1859 TYPE is the data type of the argument (as a tree).
1860 This is null for libcalls where that information may
1862 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1863 the preceding args and about the function being called.
1864 NAMED is nonzero if this argument is a named parameter
1865 (otherwise it is an extra parameter matching an ellipsis). */
1868 pdp11_function_arg (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1869 enum machine_mode mode ATTRIBUTE_UNUSED,
1870 const_tree type ATTRIBUTE_UNUSED,
1871 bool named ATTRIBUTE_UNUSED)
1876 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
1878 Update the data in CUM to advance over an argument of mode MODE and
1879 data type TYPE. (TYPE is null for libcalls where that information
1880 may not be available.) */
1883 pdp11_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1884 const_tree type, bool named ATTRIBUTE_UNUSED)
1886 *cum += (mode != BLKmode
1887 ? GET_MODE_SIZE (mode)
1888 : int_size_in_bytes (type));
1891 /* Make sure everything's fine if we *don't* have an FPU.
1892 This assumes that putting a register in fixed_regs will keep the
1893 compiler's mitts completely off it. We don't bother to zero it out
1894 of register classes. Also fix incompatible register naming with
1895 the UNIX assembler. */
1898 pdp11_conditional_register_usage (void)
1904 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]);
1905 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )
1906 if (TEST_HARD_REG_BIT (x, i))
1907 fixed_regs[i] = call_used_regs[i] = 1;
1911 call_used_regs[AC0_REGNUM] = 1;
1912 if (TARGET_UNIX_ASM)
1914 /* Change names of FPU registers for the UNIX assembler. */
1915 reg_names[8] = "fr0";
1916 reg_names[9] = "fr1";
1917 reg_names[10] = "fr2";
1918 reg_names[11] = "fr3";
1919 reg_names[12] = "fr4";
1920 reg_names[13] = "fr5";
1925 pdp11_function_section (tree decl ATTRIBUTE_UNUSED,
1926 enum node_frequency freq ATTRIBUTE_UNUSED,
1927 bool startup ATTRIBUTE_UNUSED,
1928 bool exit ATTRIBUTE_UNUSED)
1933 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1936 pdp11_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1938 return GET_CODE (x) != CONST_DOUBLE || legitimate_const_double_p (x);
1941 struct gcc_target targetm = TARGET_INITIALIZER;