1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005,
3 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "diagnostic-core.h"
41 #include "target-def.h"
44 /* this is the current value returned by the macro FIRST_PARM_OFFSET
46 int current_first_parm_offset;
48 /* Routines to encode/decode pdp11 floats */
49 static void encode_pdp11_f (const struct real_format *fmt,
50 long *, const REAL_VALUE_TYPE *);
51 static void decode_pdp11_f (const struct real_format *,
52 REAL_VALUE_TYPE *, const long *);
53 static void encode_pdp11_d (const struct real_format *fmt,
54 long *, const REAL_VALUE_TYPE *);
55 static void decode_pdp11_d (const struct real_format *,
56 REAL_VALUE_TYPE *, const long *);
58 /* These two are taken from the corresponding vax descriptors
59 in real.c, changing only the encode/decode routine pointers. */
60 const struct real_format pdp11_f_format =
81 const struct real_format pdp11_d_format =
103 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
104 const REAL_VALUE_TYPE *r)
106 (*vax_f_format.encode) (fmt, buf, r);
107 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
111 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED,
112 REAL_VALUE_TYPE *r, const long *buf)
115 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
116 (*vax_f_format.decode) (fmt, r, &tbuf);
120 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf,
121 const REAL_VALUE_TYPE *r)
123 (*vax_d_format.encode) (fmt, buf, r);
124 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
125 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
129 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED,
130 REAL_VALUE_TYPE *r, const long *buf)
133 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16);
134 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16);
135 (*vax_d_format.decode) (fmt, r, tbuf);
138 /* This is where the condition code register lives. */
139 /* rtx cc0_reg_rtx; - no longer needed? */
141 static bool pdp11_handle_option (size_t, const char *, int);
142 static void pdp11_option_init_struct (struct gcc_options *);
143 static rtx find_addr_reg (rtx);
144 static const char *singlemove_string (rtx *);
145 static bool pdp11_assemble_integer (rtx, unsigned int, int);
146 static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT);
147 static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT);
148 static bool pdp11_rtx_costs (rtx, int, int, int *, bool);
149 static bool pdp11_return_in_memory (const_tree, const_tree);
150 static rtx pdp11_function_value (const_tree, const_tree, bool);
151 static rtx pdp11_libcall_value (enum machine_mode, const_rtx);
152 static bool pdp11_function_value_regno_p (const unsigned int);
153 static void pdp11_trampoline_init (rtx, tree, rtx);
154 static rtx pdp11_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
156 static void pdp11_function_arg_advance (CUMULATIVE_ARGS *,
157 enum machine_mode, const_tree, bool);
158 static void pdp11_conditional_register_usage (void);
160 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
162 static const struct default_options pdp11_option_optimization_table[] =
164 { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
165 { OPT_LEVELS_NONE, 0, NULL, 0 }
168 /* Initialize the GCC target structure. */
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP NULL
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP NULL
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP NULL
175 #undef TARGET_ASM_INTEGER
176 #define TARGET_ASM_INTEGER pdp11_assemble_integer
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue
183 #undef TARGET_ASM_OPEN_PAREN
184 #define TARGET_ASM_OPEN_PAREN "["
185 #undef TARGET_ASM_CLOSE_PAREN
186 #define TARGET_ASM_CLOSE_PAREN "]"
188 #undef TARGET_DEFAULT_TARGET_FLAGS
189 #define TARGET_DEFAULT_TARGET_FLAGS \
190 (MASK_FPU | MASK_45 | TARGET_UNIX_ASM_DEFAULT)
191 #undef TARGET_HANDLE_OPTION
192 #define TARGET_HANDLE_OPTION pdp11_handle_option
193 #undef TARGET_OPTION_OPTIMIZATION_TABLE
194 #define TARGET_OPTION_OPTIMIZATION_TABLE pdp11_option_optimization_table
195 #undef TARGET_OPTION_INIT_STRUCT
196 #define TARGET_OPTION_INIT_STRUCT pdp11_option_init_struct
198 #undef TARGET_RTX_COSTS
199 #define TARGET_RTX_COSTS pdp11_rtx_costs
201 #undef TARGET_FUNCTION_ARG
202 #define TARGET_FUNCTION_ARG pdp11_function_arg
203 #undef TARGET_FUNCTION_ARG_ADVANCE
204 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
206 #undef TARGET_RETURN_IN_MEMORY
207 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
209 #undef TARGET_FUNCTION_VALUE
210 #define TARGET_FUNCTION_VALUE pdp11_function_value
211 #undef TARGET_LIBCALL_VALUE
212 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
213 #undef TARGET_FUNCTION_VALUE_REGNO_P
214 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
216 #undef TARGET_TRAMPOLINE_INIT
217 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
219 #undef TARGET_SECONDARY_RELOAD
220 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
222 #undef TARGET_REGISTER_MOVE_COST
223 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
225 #undef TARGET_PREFERRED_RELOAD_CLASS
226 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
228 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
229 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
231 #undef TARGET_LEGITIMATE_ADDRESS_P
232 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
234 #undef TARGET_CONDITIONAL_REGISTER_USAGE
235 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
237 #undef TARGET_ASM_FUNCTION_SECTION
238 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
241 /* Implement TARGET_HANDLE_OPTION. */
244 pdp11_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
245 int value ATTRIBUTE_UNUSED)
250 target_flags &= ~(MASK_40 | MASK_45);
258 /* Implement TARGET_OPTION_INIT_STRUCT. */
261 pdp11_option_init_struct (struct gcc_options *opts)
263 opts->x_flag_finite_math_only = 0;
264 opts->x_flag_trapping_math = 0;
265 opts->x_flag_signaling_nans = 0;
269 stream is a stdio stream to output the code to.
270 size is an int: how many units of temporary storage to allocate.
271 Refer to the array `regs_ever_live' to determine which registers
272 to save; `regs_ever_live[I]' is nonzero if register number I
273 is ever used in the function. This macro is responsible for
274 knowing which registers should not be saved even if used.
278 pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
280 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
285 "\n\t; /* function prologue %s*/\n",
286 current_function_name ());
288 /* if we are outputting code for main,
289 the switch FPU to right mode if TARGET_FPU */
290 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU)
293 "\t;/* switch cpu to double float, single integer */\n");
294 fprintf(stream, "\tsetd\n");
295 fprintf(stream, "\tseti\n\n");
298 if (frame_pointer_needed)
300 fprintf(stream, "\tmov r5, -(sp)\n");
301 fprintf(stream, "\tmov sp, r5\n");
310 asm_fprintf (stream, "\tsub $%#wo, sp\n", fsize);
312 /* save CPU registers */
313 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++)
314 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
315 if (! ((regno == FRAME_POINTER_REGNUM)
316 && frame_pointer_needed))
317 fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]);
318 /* fpu regs saving */
320 /* via_ac specifies the ac to use for saving ac4, ac5 */
323 for (regno = AC0_REGNUM; regno <= AC5_REGNUM ; regno++)
326 if (LOAD_FPU_REG_P(regno)
327 && df_regs_ever_live_p (regno)
328 && ! call_used_regs[regno])
330 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[regno]);
334 /* maybe make ac4, ac5 call used regs?? */
336 if (NO_LOAD_FPU_REG_P(regno)
337 && df_regs_ever_live_p (regno)
338 && ! call_used_regs[regno])
340 gcc_assert (via_ac != -1);
341 fprintf (stream, "\tldd %s, %s\n",
342 reg_names[regno], reg_names[via_ac]);
343 fprintf (stream, "\tstd %s, -(sp)\n", reg_names[via_ac]);
347 fprintf (stream, "\t;/* end of prologue */\n\n");
351 The function epilogue should not depend on the current stack pointer!
352 It should use the frame pointer only. This is mandatory because
353 of alloca; we also take advantage of it to omit stack adjustments
356 /* maybe we can make leaf functions faster by switching to the
357 second register file - this way we don't have to save regs!
358 leaf functions are ~ 50% of all functions (dynamically!)
360 set/clear bit 11 (dec. 2048) of status word for switching register files -
361 but how can we do this? the pdp11/45 manual says bit may only
362 be set (p.24), but not cleared!
364 switching to kernel is probably more expensive, so we'll leave it
365 like this and not use the second set of registers...
367 maybe as option if you want to generate code for kernel mode? */
370 pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
372 HOST_WIDE_INT fsize = ((size) + 1) & ~1;
377 fprintf (stream, "\n\t; /*function epilogue */\n");
379 if (frame_pointer_needed)
381 /* hope this is safe - m68k does it also .... */
382 df_set_regs_ever_live (FRAME_POINTER_REGNUM, false);
384 for (i = PC_REGNUM, j = 0 ; i >= 0 ; i--)
385 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
388 /* remember # of pushed bytes for CPU regs */
391 /* change fp -> r5 due to the compile error on libgcc2.c */
392 for (i = PC_REGNUM ; i >= R0_REGNUM ; i--)
393 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
394 fprintf(stream, "\tmov %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
395 (-fsize-2*j--)&0xffff, reg_names[i]);
400 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
401 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
407 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
409 if (LOAD_FPU_REG_P(i)
410 && df_regs_ever_live_p (i)
411 && ! call_used_regs[i])
413 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
414 (-fsize-k)&0xffff, reg_names[i]);
418 if (NO_LOAD_FPU_REG_P(i)
419 && df_regs_ever_live_p (i)
420 && ! call_used_regs[i])
422 gcc_assert (LOAD_FPU_REG_P(via_ac));
424 fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n",
425 (-fsize-k)&0xffff, reg_names[via_ac]);
426 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
431 fprintf(stream, "\tmov r5, sp\n");
432 fprintf (stream, "\tmov (sp)+, r5\n");
439 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
440 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
443 for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
445 if (LOAD_FPU_REG_P(i)
446 && df_regs_ever_live_p (i)
447 && ! call_used_regs[i])
448 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[i]);
450 if (NO_LOAD_FPU_REG_P(i)
451 && df_regs_ever_live_p (i)
452 && ! call_used_regs[i])
454 gcc_assert (LOAD_FPU_REG_P(via_ac));
456 fprintf(stream, "\tldd (sp)+, %s\n", reg_names[via_ac]);
457 fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]);
461 for (i = PC_REGNUM; i >= 0; i--)
462 if (df_regs_ever_live_p (i) && !call_used_regs[i])
463 fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]);
466 fprintf((stream), "\tadd $%#" HOST_WIDE_INT_PRINT "o, sp\n",
470 fprintf (stream, "\trts pc\n");
471 fprintf (stream, "\t;/* end of epilogue*/\n\n\n");
474 /* Return the best assembler insn template
475 for moving operands[1] into operands[0] as a fullword. */
477 singlemove_string (rtx *operands)
479 if (operands[1] != const0_rtx)
486 /* Output assembler code to perform a doubleword move insn
487 with operands OPERANDS. */
490 output_move_double (rtx *operands)
492 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
494 rtx addreg0 = 0, addreg1 = 0;
496 /* First classify both operands. */
498 if (REG_P (operands[0]))
500 else if (offsettable_memref_p (operands[0]))
502 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
504 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
506 else if (GET_CODE (operands[0]) == MEM)
511 if (REG_P (operands[1]))
513 else if (CONSTANT_P (operands[1])
515 || GET_CODE (operands[1]) == CONST_DOUBLE
519 else if (offsettable_memref_p (operands[1]))
521 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
523 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
525 else if (GET_CODE (operands[1]) == MEM)
530 /* Check for the cases that the operand constraints are not
531 supposed to allow to happen. Abort if we get one,
532 because generating code for these cases is painful. */
534 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
536 /* If one operand is decrementing and one is incrementing
537 decrement the former register explicitly
538 and change that operand into ordinary indexing. */
540 if (optype0 == PUSHOP && optype1 == POPOP)
542 operands[0] = XEXP (XEXP (operands[0], 0), 0);
543 output_asm_insn ("sub $4,%0", operands);
544 operands[0] = gen_rtx_MEM (SImode, operands[0]);
547 if (optype0 == POPOP && optype1 == PUSHOP)
549 operands[1] = XEXP (XEXP (operands[1], 0), 0);
550 output_asm_insn ("sub $4,%1", operands);
551 operands[1] = gen_rtx_MEM (SImode, operands[1]);
555 /* If an operand is an unoffsettable memory ref, find a register
556 we can increment temporarily to make it refer to the second word. */
558 if (optype0 == MEMOP)
559 addreg0 = find_addr_reg (XEXP (operands[0], 0));
561 if (optype1 == MEMOP)
562 addreg1 = find_addr_reg (XEXP (operands[1], 0));
564 /* Ok, we can do one word at a time.
565 Normally we do the low-numbered word first,
566 but if either operand is autodecrementing then we
567 do the high-numbered word first.
569 In either case, set up in LATEHALF the operands to use
570 for the high-numbered word and in some cases alter the
571 operands in OPERANDS to be suitable for the low-numbered word. */
573 if (optype0 == REGOP)
574 latehalf[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
575 else if (optype0 == OFFSOP)
576 latehalf[0] = adjust_address (operands[0], HImode, 2);
578 latehalf[0] = operands[0];
580 if (optype1 == REGOP)
581 latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1);
582 else if (optype1 == OFFSOP)
583 latehalf[1] = adjust_address (operands[1], HImode, 2);
584 else if (optype1 == CNSTOP)
586 if (CONSTANT_P (operands[1]))
588 /* now the mess begins, high word is in lower word???
590 that's what ashc makes me think, but I don't remember :-( */
591 latehalf[1] = GEN_INT (INTVAL(operands[1]) >> 16);
592 operands[1] = GEN_INT (INTVAL(operands[1]) & 0xff);
595 /* immediate 32-bit values not allowed */
596 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE);
599 latehalf[1] = operands[1];
601 /* If insn is effectively movd N(sp),-(sp) then we will do the
602 high word first. We should use the adjusted operand 1 (which is N+4(sp))
603 for the low word as well, to compensate for the first decrement of sp. */
604 if (optype0 == PUSHOP
605 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
606 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
607 operands[1] = latehalf[1];
609 /* If one or both operands autodecrementing,
610 do the two words, high-numbered first. */
612 /* Likewise, the first move would clobber the source of the second one,
613 do them in the other order. This happens only for registers;
614 such overlap can't happen in memory unless the user explicitly
615 sets it up, and that is an undefined circumstance. */
617 if (optype0 == PUSHOP || optype1 == PUSHOP
618 || (optype0 == REGOP && optype1 == REGOP
619 && REGNO (operands[0]) == REGNO (latehalf[1])))
621 /* Make any unoffsettable addresses point at high-numbered word. */
623 output_asm_insn ("add $2,%0", &addreg0);
625 output_asm_insn ("add $2,%0", &addreg1);
628 output_asm_insn (singlemove_string (latehalf), latehalf);
630 /* Undo the adds we just did. */
632 output_asm_insn ("sub $2,%0", &addreg0);
634 output_asm_insn ("sub $2,%0", &addreg1);
636 /* Do low-numbered word. */
637 return singlemove_string (operands);
640 /* Normal case: do the two words, low-numbered first. */
642 output_asm_insn (singlemove_string (operands), operands);
644 /* Make any unoffsettable addresses point at high-numbered word. */
646 output_asm_insn ("add $2,%0", &addreg0);
648 output_asm_insn ("add $2,%0", &addreg1);
651 output_asm_insn (singlemove_string (latehalf), latehalf);
653 /* Undo the adds we just did. */
655 output_asm_insn ("sub $2,%0", &addreg0);
657 output_asm_insn ("sub $2,%0", &addreg1);
661 /* Output assembler code to perform a quadword move insn
662 with operands OPERANDS. */
665 output_move_quad (rtx *operands)
667 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
669 rtx addreg0 = 0, addreg1 = 0;
671 output_asm_insn(";/* movdi/df: %1 -> %0 */", operands);
673 if (REG_P (operands[0]))
675 else if (offsettable_memref_p (operands[0]))
677 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
679 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
681 else if (GET_CODE (operands[0]) == MEM)
686 if (REG_P (operands[1]))
688 else if (CONSTANT_P (operands[1])
689 || GET_CODE (operands[1]) == CONST_DOUBLE)
691 else if (offsettable_memref_p (operands[1]))
693 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
695 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
697 else if (GET_CODE (operands[1]) == MEM)
702 /* Check for the cases that the operand constraints are not
703 supposed to allow to happen. Abort if we get one,
704 because generating code for these cases is painful. */
706 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
708 if (optype0 == REGOP || optype1 == REGOP)
710 /* check for use of clrd????
711 if you ever allow ac4 and ac5 (now we require secondary load)
712 you must check whether
713 you want to load into them or store from them -
714 then dump ac0 into $help$ movce ac4/5 to ac0, do the
715 store from ac0, and restore ac0 - if you can find
716 an unused ac[0-3], use that and you save a store and a load!*/
718 if (FPU_REG_P(REGNO(operands[0])))
720 if (GET_CODE(operands[1]) == CONST_DOUBLE)
723 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
725 if (REAL_VALUES_EQUAL (r, dconst0))
726 return "{clrd|clrf} %0";
729 return "{ldd|movf} %1, %0";
732 if (FPU_REG_P(REGNO(operands[1])))
733 return "{std|movf} %1, %0";
736 /* If one operand is decrementing and one is incrementing
737 decrement the former register explicitly
738 and change that operand into ordinary indexing. */
740 if (optype0 == PUSHOP && optype1 == POPOP)
742 operands[0] = XEXP (XEXP (operands[0], 0), 0);
743 output_asm_insn ("sub $8,%0", operands);
744 operands[0] = gen_rtx_MEM (DImode, operands[0]);
747 if (optype0 == POPOP && optype1 == PUSHOP)
749 operands[1] = XEXP (XEXP (operands[1], 0), 0);
750 output_asm_insn ("sub $8,%1", operands);
751 operands[1] = gen_rtx_MEM (SImode, operands[1]);
755 /* If an operand is an unoffsettable memory ref, find a register
756 we can increment temporarily to make it refer to the second word. */
758 if (optype0 == MEMOP)
759 addreg0 = find_addr_reg (XEXP (operands[0], 0));
761 if (optype1 == MEMOP)
762 addreg1 = find_addr_reg (XEXP (operands[1], 0));
764 /* Ok, we can do one word at a time.
765 Normally we do the low-numbered word first,
766 but if either operand is autodecrementing then we
767 do the high-numbered word first.
769 In either case, set up in LATEHALF the operands to use
770 for the high-numbered word and in some cases alter the
771 operands in OPERANDS to be suitable for the low-numbered word. */
773 if (optype0 == REGOP)
774 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
775 else if (optype0 == OFFSOP)
776 latehalf[0] = adjust_address (operands[0], SImode, 4);
778 latehalf[0] = operands[0];
780 if (optype1 == REGOP)
781 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
782 else if (optype1 == OFFSOP)
783 latehalf[1] = adjust_address (operands[1], SImode, 4);
784 else if (optype1 == CNSTOP)
786 if (GET_CODE (operands[1]) == CONST_DOUBLE)
790 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
791 REAL_VALUE_TO_TARGET_DOUBLE (r, dval);
792 latehalf[1] = GEN_INT (dval[1]);
793 operands[1] = GEN_INT (dval[0]);
795 else if (GET_CODE(operands[1]) == CONST_INT)
797 latehalf[1] = const0_rtx;
803 latehalf[1] = operands[1];
805 /* If insn is effectively movd N(sp),-(sp) then we will do the
806 high word first. We should use the adjusted operand 1 (which is N+4(sp))
807 for the low word as well, to compensate for the first decrement of sp. */
808 if (optype0 == PUSHOP
809 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
810 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
811 operands[1] = latehalf[1];
813 /* If one or both operands autodecrementing,
814 do the two words, high-numbered first. */
816 /* Likewise, the first move would clobber the source of the second one,
817 do them in the other order. This happens only for registers;
818 such overlap can't happen in memory unless the user explicitly
819 sets it up, and that is an undefined circumstance. */
821 if (optype0 == PUSHOP || optype1 == PUSHOP
822 || (optype0 == REGOP && optype1 == REGOP
823 && REGNO (operands[0]) == REGNO (latehalf[1])))
825 /* Make any unoffsettable addresses point at high-numbered word. */
827 output_asm_insn ("add $4,%0", &addreg0);
829 output_asm_insn ("add $4,%0", &addreg1);
832 output_asm_insn(output_move_double(latehalf), latehalf);
834 /* Undo the adds we just did. */
836 output_asm_insn ("sub $4,%0", &addreg0);
838 output_asm_insn ("sub $4,%0", &addreg1);
840 /* Do low-numbered word. */
841 return output_move_double (operands);
844 /* Normal case: do the two words, low-numbered first. */
846 output_asm_insn (output_move_double (operands), operands);
848 /* Make any unoffsettable addresses point at high-numbered word. */
850 output_asm_insn ("add $4,%0", &addreg0);
852 output_asm_insn ("add $4,%0", &addreg1);
855 output_asm_insn (output_move_double (latehalf), latehalf);
857 /* Undo the adds we just did. */
859 output_asm_insn ("sub $4,%0", &addreg0);
861 output_asm_insn ("sub $4,%0", &addreg1);
867 /* Return a REG that occurs in ADDR with coefficient 1.
868 ADDR can be effectively incremented by incrementing REG. */
871 find_addr_reg (rtx addr)
873 while (GET_CODE (addr) == PLUS)
875 if (GET_CODE (XEXP (addr, 0)) == REG)
876 addr = XEXP (addr, 0);
877 if (GET_CODE (XEXP (addr, 1)) == REG)
878 addr = XEXP (addr, 1);
879 if (CONSTANT_P (XEXP (addr, 0)))
880 addr = XEXP (addr, 1);
881 if (CONSTANT_P (XEXP (addr, 1)))
882 addr = XEXP (addr, 0);
884 if (GET_CODE (addr) == REG)
889 /* Output an ascii string. */
891 output_ascii (FILE *file, const char *p, int size)
895 /* This used to output .byte "string", which doesn't work with the UNIX
896 assembler and I think not with DEC ones either. */
897 fprintf (file, "\t.byte ");
899 for (i = 0; i < size; i++)
901 register int c = p[i];
904 fprintf (file, "%#o", c);
913 print_operand_address (FILE *file, register rtx addr)
921 switch (GET_CODE (addr))
928 addr = XEXP (addr, 0);
933 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
938 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
943 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
949 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
950 || GET_CODE (XEXP (addr, 0)) == MEM)
952 offset = XEXP (addr, 0);
953 addr = XEXP (addr, 1);
955 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
956 || GET_CODE (XEXP (addr, 1)) == MEM)
958 offset = XEXP (addr, 1);
959 addr = XEXP (addr, 0);
961 if (GET_CODE (addr) != PLUS)
963 else if (GET_CODE (XEXP (addr, 0)) == REG)
965 breg = XEXP (addr, 0);
966 addr = XEXP (addr, 1);
968 else if (GET_CODE (XEXP (addr, 1)) == REG)
970 breg = XEXP (addr, 1);
971 addr = XEXP (addr, 0);
973 if (GET_CODE (addr) == REG)
975 gcc_assert (breg == 0);
981 gcc_assert (addr == 0);
985 output_addr_const_pdp11 (file, addr);
988 gcc_assert (GET_CODE (breg) == REG);
989 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
994 if (!again && GET_CODE (addr) == CONST_INT)
996 /* Absolute (integer number) address. */
997 if (!TARGET_UNIX_ASM)
998 fprintf (file, "@$");
1000 output_addr_const_pdp11 (file, addr);
1004 /* Target hook to assemble integer objects. We need to use the
1005 pdp-specific version of output_addr_const. */
1008 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p)
1014 fprintf (asm_out_file, "\t.byte\t");
1015 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff));
1017 fprintf (asm_out_file, " /* char */\n");
1021 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t");
1022 output_addr_const_pdp11 (asm_out_file, x);
1023 fprintf (asm_out_file, " /* short */\n");
1026 return default_assemble_integer (x, size, aligned_p);
1030 /* register move costs, indexed by regs */
1032 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
1034 /* NO MUL GEN LFPU NLFPU FPU ALL */
1036 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
1037 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
1038 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
1039 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
1040 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
1041 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
1042 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
1046 /* -- note that some moves are tremendously expensive,
1047 because they require lots of tricks! do we have to
1048 charge the costs incurred by secondary reload class
1049 -- as we do here with 10 -- or not ? */
1052 pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1053 reg_class_t c1, reg_class_t c2)
1055 return move_costs[(int)c1][(int)c2];
1059 pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
1060 bool speed ATTRIBUTE_UNUSED)
1065 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1)
1075 /* Twice as expensive as REG. */
1080 /* Twice (or 4 times) as expensive as 16 bit. */
1085 /* ??? There is something wrong in MULT because MULT is not
1086 as cheap as total = 2 even if we can shift! */
1087 /* If optimizing for size make mult etc cheap, but not 1, so when
1088 in doubt the faster insn is chosen. */
1090 *total = COSTS_N_INSNS (2);
1092 *total = COSTS_N_INSNS (11);
1097 *total = COSTS_N_INSNS (2);
1099 *total = COSTS_N_INSNS (25);
1104 *total = COSTS_N_INSNS (2);
1106 *total = COSTS_N_INSNS (26);
1110 /* Equivalent to length, so same for optimize_size. */
1111 *total = COSTS_N_INSNS (3);
1115 /* Only used for qi->hi. */
1116 *total = COSTS_N_INSNS (1);
1120 if (GET_MODE (x) == HImode)
1121 *total = COSTS_N_INSNS (1);
1122 else if (GET_MODE (x) == SImode)
1123 *total = COSTS_N_INSNS (6);
1125 *total = COSTS_N_INSNS (2);
1132 *total = COSTS_N_INSNS (1);
1133 else if (GET_MODE (x) == QImode)
1135 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1136 *total = COSTS_N_INSNS (8); /* worst case */
1138 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
1140 else if (GET_MODE (x) == HImode)
1142 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1144 if (abs (INTVAL (XEXP (x, 1))) == 1)
1145 *total = COSTS_N_INSNS (1);
1147 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1150 *total = COSTS_N_INSNS (10); /* worst case */
1152 else if (GET_MODE (x) == SImode)
1154 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1155 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1)));
1156 else /* worst case */
1157 *total = COSTS_N_INSNS (18);
1167 output_jump (enum rtx_code code, int inv, int length)
1171 static char buf[1000];
1172 const char *pos, *neg;
1174 if (cc_prev_status.flags & CC_NO_OVERFLOW)
1178 case GTU: code = GT; break;
1179 case LTU: code = LT; break;
1180 case GEU: code = GE; break;
1181 case LEU: code = LE; break;
1187 case EQ: pos = "beq", neg = "bne"; break;
1188 case NE: pos = "bne", neg = "beq"; break;
1189 case GT: pos = "bgt", neg = "ble"; break;
1190 case GTU: pos = "bhi", neg = "blos"; break;
1191 case LT: pos = "blt", neg = "bge"; break;
1192 case LTU: pos = "blo", neg = "bhis"; break;
1193 case GE: pos = "bge", neg = "blt"; break;
1194 case GEU: pos = "bhis", neg = "blo"; break;
1195 case LE: pos = "ble", neg = "bgt"; break;
1196 case LEU: pos = "blos", neg = "bhi"; break;
1197 default: gcc_unreachable ();
1201 /* currently we don't need this, because the tstdf and cmpdf
1202 copy the condition code immediately, and other float operations are not
1203 yet recognized as changing the FCC - if so, then the length-cost of all
1204 jump insns increases by one, because we have to potentially copy the
1206 if (cc_status.flags & CC_IN_FPU)
1207 output_asm_insn("cfcc", NULL);
1214 sprintf(buf, "%s %%l1", inv ? neg : pos);
1220 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x);
1234 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED)
1236 if (GET_CODE (SET_DEST (exp)) == CC0)
1238 cc_status.flags = 0;
1239 cc_status.value1 = SET_DEST (exp);
1240 cc_status.value2 = SET_SRC (exp);
1242 else if (GET_CODE (SET_SRC (exp)) == CALL)
1246 else if (SET_DEST(exp) == pc_rtx)
1250 else if (GET_MODE (SET_DEST(exp)) == HImode
1251 || GET_MODE (SET_DEST(exp)) == QImode)
1253 cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW;
1254 cc_status.value1 = SET_SRC (exp);
1255 cc_status.value2 = SET_DEST (exp);
1257 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
1259 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
1260 cc_status.value2 = 0;
1261 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
1263 && GET_CODE (cc_status.value2) == MEM)
1264 cc_status.value2 = 0;
1274 simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1278 /* Eliminate non-memory operations */
1279 if (GET_CODE (op) != MEM)
1283 /* dword operations really put out 2 instructions, so eliminate them. */
1284 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4))
1288 /* Decode the address now. */
1292 addr = XEXP (op, 0);
1294 switch (GET_CODE (addr))
1297 /* (R0) - no extra cost */
1302 /* -(R0), (R0)+ - cheap! */
1306 /* cheap - is encoded in addressing mode info!
1308 -- except for @(R0), which has to be @0(R0) !!! */
1310 if (GET_CODE (XEXP (addr, 0)) == REG)
1320 /* @#address - extra cost */
1324 /* X(R0) - extra cost */
1336 * output a block move:
1338 * operands[0] ... to
1339 * operands[1] ... from
1340 * operands[2] ... length
1341 * operands[3] ... alignment
1342 * operands[4] ... scratch register
1347 output_block_move(rtx *operands)
1349 static int count = 0;
1352 if (GET_CODE(operands[2]) == CONST_INT
1355 if (INTVAL(operands[2]) < 16
1356 && INTVAL(operands[3]) == 1)
1360 for (i = 1; i <= INTVAL(operands[2]); i++)
1361 output_asm_insn("movb (%1)+, (%0)+", operands);
1365 else if (INTVAL(operands[2]) < 32)
1369 for (i = 1; i <= INTVAL(operands[2])/2; i++)
1370 output_asm_insn("mov (%1)+, (%0)+", operands);
1372 /* may I assume that moved quantity is
1373 multiple of alignment ???
1382 /* can do other clever things, maybe... */
1385 if (CONSTANT_P(operands[2]) )
1387 /* just move count to scratch */
1388 output_asm_insn("mov %2, %4", operands);
1392 /* just clobber the register */
1393 operands[4] = operands[2];
1397 /* switch over alignment */
1398 switch (INTVAL(operands[3]))
1414 sprintf(buf, "\nmovestrhi%d:", count);
1415 output_asm_insn(buf, NULL);
1417 output_asm_insn("movb (%1)+, (%0)+", operands);
1421 sprintf(buf, "sob %%4, movestrhi%d", count);
1422 output_asm_insn(buf, operands);
1426 output_asm_insn("dec %4", operands);
1428 sprintf(buf, "bgt movestrhi%d", count);
1429 output_asm_insn(buf, NULL);
1451 generate_compact_code:
1453 output_asm_insn("asr %4", operands);
1455 sprintf(buf, "\nmovestrhi%d:", count);
1456 output_asm_insn(buf, NULL);
1458 output_asm_insn("mov (%1)+, (%0)+", operands);
1462 sprintf(buf, "sob %%4, movestrhi%d", count);
1463 output_asm_insn(buf, operands);
1467 output_asm_insn("dec %4", operands);
1469 sprintf(buf, "bgt movestrhi%d", count);
1470 output_asm_insn(buf, NULL);
1496 goto generate_compact_code;
1498 output_asm_insn("asr %4", operands);
1499 output_asm_insn("asr %4", operands);
1501 sprintf(buf, "\nmovestrhi%d:", count);
1502 output_asm_insn(buf, NULL);
1504 output_asm_insn("mov (%1)+, (%0)+", operands);
1505 output_asm_insn("mov (%1)+, (%0)+", operands);
1509 sprintf(buf, "sob %%4, movestrhi%d", count);
1510 output_asm_insn(buf, operands);
1514 output_asm_insn("dec %4", operands);
1516 sprintf(buf, "bgt movestrhi%d", count);
1517 output_asm_insn(buf, NULL);
1547 goto generate_compact_code;
1549 output_asm_insn("asr %4", operands);
1550 output_asm_insn("asr %4", operands);
1551 output_asm_insn("asr %4", operands);
1553 sprintf(buf, "\nmovestrhi%d:", count);
1554 output_asm_insn(buf, NULL);
1556 output_asm_insn("mov (%1)+, (%0)+", operands);
1557 output_asm_insn("mov (%1)+, (%0)+", operands);
1558 output_asm_insn("mov (%1)+, (%0)+", operands);
1559 output_asm_insn("mov (%1)+, (%0)+", operands);
1563 sprintf(buf, "sob %%4, movestrhi%d", count);
1564 output_asm_insn(buf, operands);
1568 output_asm_insn("dec %4", operands);
1570 sprintf(buf, "bgt movestrhi%d", count);
1571 output_asm_insn(buf, NULL);
1584 /* This function checks whether a real value can be encoded as
1585 a literal, i.e., addressing mode 27. In that mode, real values
1586 are one word values, so the remaining 48 bits have to be zero. */
1588 legitimate_const_double_p (rtx address)
1592 REAL_VALUE_FROM_CONST_DOUBLE (r, address);
1593 REAL_VALUE_TO_TARGET_DOUBLE (r, sval);
1594 if ((sval[0] & 0xffff) == 0 && sval[1] == 0)
1599 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1601 pdp11_cannot_change_mode_class (enum machine_mode from,
1602 enum machine_mode to,
1603 enum reg_class rclass)
1605 /* Also, FPU registers contain a whole float value and the parts of
1606 it are not separately accessible.
1608 So we disallow all mode changes involving FPRs. */
1609 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to))
1612 return reg_classes_intersect_p (FPU_REGS, rclass);
1615 /* TARGET_PREFERRED_RELOAD_CLASS
1617 Given an rtx X being reloaded into a reg required to be
1618 in class CLASS, return the class of reg to actually use.
1619 In general this is just CLASS; but on some machines
1620 in some cases it is preferable to use a more restrictive class.
1622 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1625 pdp11_preferred_reload_class (rtx x, reg_class_t rclass)
1627 if (rclass == FPU_REGS)
1628 return LOAD_FPU_REGS;
1629 if (rclass == ALL_REGS)
1631 if (FLOAT_MODE_P (GET_MODE (x)))
1632 return LOAD_FPU_REGS;
1634 return GENERAL_REGS;
1639 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1641 Given an rtx X being reloaded into a reg required to be
1642 in class CLASS, return the class of reg to actually use.
1643 In general this is just CLASS; but on some machines
1644 in some cases it is preferable to use a more restrictive class.
1646 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1649 pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass)
1651 if (rclass == FPU_REGS)
1652 return LOAD_FPU_REGS;
1653 if (rclass == ALL_REGS)
1655 if (FLOAT_MODE_P (GET_MODE (x)))
1656 return LOAD_FPU_REGS;
1658 return GENERAL_REGS;
1664 /* TARGET_SECONDARY_RELOAD.
1666 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1667 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1668 can be loade/stored directly. */
1670 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
1672 reg_class_t reload_class,
1673 enum machine_mode reload_mode ATTRIBUTE_UNUSED,
1674 secondary_reload_info *sri ATTRIBUTE_UNUSED)
1676 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
1677 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
1680 return LOAD_FPU_REGS;
1683 /* Target routine to check if register to register move requires memory.
1685 The answer is yes if we're going between general register and FPU
1686 registers. The mode doesn't matter in making this check.
1689 pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2,
1690 enum machine_mode mode ATTRIBUTE_UNUSED)
1692 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS ||
1694 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS ||
1697 return (fromfloat != tofloat);
1700 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1701 that is a valid memory address for an instruction.
1702 The MODE argument is the machine mode for the MEM expression
1703 that wants to use this address.
1708 pdp11_legitimate_address_p (enum machine_mode mode,
1709 rtx operand, bool strict)
1713 /* accept @#address */
1714 if (CONSTANT_ADDRESS_P (operand))
1717 switch (GET_CODE (operand))
1721 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand));
1725 return GET_CODE (XEXP (operand, 0)) == REG
1726 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))))
1727 && CONSTANT_ADDRESS_P (XEXP (operand, 1));
1731 return GET_CODE (XEXP (operand, 0)) == REG
1732 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1736 return GET_CODE (XEXP (operand, 0)) == REG
1737 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
1740 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1741 return GET_CODE (XEXP (operand, 0)) == REG
1742 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1743 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1744 && GET_CODE (XEXP (xfoob, 0)) == REG
1745 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1746 && CONSTANT_P (XEXP (xfoob, 1))
1747 && INTVAL (XEXP (xfoob,1)) == -2;
1750 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1751 return GET_CODE (XEXP (operand, 0)) == REG
1752 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
1753 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
1754 && GET_CODE (XEXP (xfoob, 0)) == REG
1755 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
1756 && CONSTANT_P (XEXP (xfoob, 1))
1757 && INTVAL (XEXP (xfoob,1)) == 2;
1760 /* handle another level of indirection ! */
1761 xfoob = XEXP (operand, 0);
1763 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1764 also forbidden for float, because we have to handle this
1765 in output_move_double and/or output_move_quad() - we could
1766 do it, but currently it's not worth it!!!
1767 now that DFmode cannot go into CPU register file,
1768 maybe I should allow float ...
1769 but then I have to handle memory-to-memory moves in movdf ?? */
1770 if (GET_MODE_BITSIZE(mode) > 16)
1773 /* accept @address */
1774 if (CONSTANT_ADDRESS_P (xfoob))
1777 switch (GET_CODE (xfoob))
1780 /* accept @(R0) - which is @0(R0) */
1781 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob));
1785 return GET_CODE (XEXP (xfoob, 0)) == REG
1786 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))))
1787 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1));
1791 return GET_CODE (XEXP (xfoob, 0)) == REG
1792 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1796 return GET_CODE (XEXP (xfoob, 0)) == REG
1797 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
1800 /* anything else is invalid */
1805 /* anything else is invalid */
1809 /* Return the class number of the smallest class containing
1810 reg number REGNO. */
1812 pdp11_regno_reg_class (int regno)
1814 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1815 return GENERAL_REGS;
1816 else if (regno > AC3_REGNUM)
1817 return NO_LOAD_FPU_REGS;
1818 else if (regno >= AC0_REGNUM)
1819 return LOAD_FPU_REGS;
1823 return GENERAL_REGS;
1828 pdp11_sp_frame_offset (void)
1830 int offset = 0, regno;
1831 offset = get_frame_size();
1832 for (regno = 0; regno <= PC_REGNUM; regno++)
1833 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1835 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++)
1836 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1842 /* Return the offset between two registers, one to be eliminated, and the other
1843 its replacement, at the start of a routine. */
1846 pdp11_initial_elimination_offset (int from, int to)
1850 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
1852 else if (from == FRAME_POINTER_REGNUM
1853 && to == HARD_FRAME_POINTER_REGNUM)
1857 gcc_assert (to == STACK_POINTER_REGNUM);
1859 /* Get the size of the register save area. */
1860 spoff = pdp11_sp_frame_offset ();
1861 if (from == FRAME_POINTER_REGNUM)
1864 gcc_assert (from == ARG_POINTER_REGNUM);
1866 /* If there is a frame pointer, that is saved too. */
1867 if (frame_pointer_needed)
1870 /* Account for the saved PC in the function call. */
1875 /* A copy of output_addr_const modified for pdp11 expression syntax.
1876 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1877 use, and for debugging output, which we don't support with this port either.
1878 So this copy should get called whenever needed.
1881 output_addr_const_pdp11 (FILE *file, rtx x)
1887 switch (GET_CODE (x))
1890 gcc_assert (flag_pic);
1895 assemble_name (file, XSTR (x, 0));
1899 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0)));
1900 assemble_name (file, buf);
1904 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1905 assemble_name (file, buf);
1913 fprintf (file, "-");
1915 fprintf (file, "%#o", i & 0xffff);
1919 /* This used to output parentheses around the expression,
1920 but that does not work on the 386 (either ATT or BSD assembler). */
1921 output_addr_const_pdp11 (file, XEXP (x, 0));
1925 if (GET_MODE (x) == VOIDmode)
1927 /* We can use %o if the number is one word and positive. */
1928 gcc_assert (!CONST_DOUBLE_HIGH (x));
1929 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x));
1932 /* We can't handle floating point constants;
1933 PRINT_OPERAND must handle them. */
1934 output_operand_lossage ("floating constant misused");
1938 /* Some assemblers need integer constants to appear last (e.g. masm). */
1939 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1941 output_addr_const_pdp11 (file, XEXP (x, 1));
1942 if (INTVAL (XEXP (x, 0)) >= 0)
1943 fprintf (file, "+");
1944 output_addr_const_pdp11 (file, XEXP (x, 0));
1948 output_addr_const_pdp11 (file, XEXP (x, 0));
1949 if (INTVAL (XEXP (x, 1)) >= 0)
1950 fprintf (file, "+");
1951 output_addr_const_pdp11 (file, XEXP (x, 1));
1956 /* Avoid outputting things like x-x or x+5-x,
1957 since some assemblers can't handle that. */
1958 x = simplify_subtraction (x);
1959 if (GET_CODE (x) != MINUS)
1962 output_addr_const_pdp11 (file, XEXP (x, 0));
1963 if (GET_CODE (XEXP (x, 1)) != CONST_INT
1964 || INTVAL (XEXP (x, 1)) >= 0)
1965 fprintf (file, "-");
1966 output_addr_const_pdp11 (file, XEXP (x, 1));
1971 output_addr_const_pdp11 (file, XEXP (x, 0));
1975 output_operand_lossage ("invalid expression as operand");
1979 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1982 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1984 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1985 in registers. The rest go into memory. */
1986 return (TYPE_MODE (type) == DImode
1987 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0)
1988 || TREE_CODE (type) == VECTOR_TYPE
1989 || COMPLEX_MODE_P (TYPE_MODE (type)));
1992 /* Worker function for TARGET_FUNCTION_VALUE.
1994 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1997 pdp11_function_value (const_tree valtype,
1998 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
1999 bool outgoing ATTRIBUTE_UNUSED)
2001 return gen_rtx_REG (TYPE_MODE (valtype),
2002 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype)));
2005 /* Worker function for TARGET_LIBCALL_VALUE. */
2008 pdp11_libcall_value (enum machine_mode mode,
2009 const_rtx fun ATTRIBUTE_UNUSED)
2011 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode));
2014 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
2016 On the pdp, the first "output" reg is the only register thus used.
2018 maybe ac0 ? - as option someday! */
2021 pdp11_function_value_regno_p (const unsigned int regno)
2023 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM));
2026 /* Worker function for TARGET_TRAMPOLINE_INIT.
2028 trampoline - how should i do it in separate i+d ?
2029 have some allocate_trampoline magic???
2031 the following should work for shared I/D:
2033 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
2034 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
2038 pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2040 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2043 gcc_assert (!TARGET_SPLIT);
2045 mem = adjust_address (m_tramp, HImode, 0);
2046 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM));
2047 mem = adjust_address (m_tramp, HImode, 2);
2048 emit_move_insn (mem, chain_value);
2049 mem = adjust_address (m_tramp, HImode, 4);
2050 emit_move_insn (mem, GEN_INT (000137));
2051 emit_move_insn (mem, fnaddr);
2054 /* Worker function for TARGET_FUNCTION_ARG.
2056 Determine where to put an argument to a function.
2057 Value is zero to push the argument on the stack,
2058 or a hard register in which to store the argument.
2060 MODE is the argument's machine mode.
2061 TYPE is the data type of the argument (as a tree).
2062 This is null for libcalls where that information may
2064 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2065 the preceding args and about the function being called.
2066 NAMED is nonzero if this argument is a named parameter
2067 (otherwise it is an extra parameter matching an ellipsis). */
2070 pdp11_function_arg (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2071 enum machine_mode mode ATTRIBUTE_UNUSED,
2072 const_tree type ATTRIBUTE_UNUSED,
2073 bool named ATTRIBUTE_UNUSED)
2078 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
2080 Update the data in CUM to advance over an argument of mode MODE and
2081 data type TYPE. (TYPE is null for libcalls where that information
2082 may not be available.) */
2085 pdp11_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2086 const_tree type, bool named ATTRIBUTE_UNUSED)
2088 *cum += (mode != BLKmode
2089 ? GET_MODE_SIZE (mode)
2090 : int_size_in_bytes (type));
2093 /* Make sure everything's fine if we *don't* have an FPU.
2094 This assumes that putting a register in fixed_regs will keep the
2095 compiler's mitts completely off it. We don't bother to zero it out
2096 of register classes. Also fix incompatible register naming with
2097 the UNIX assembler. */
2100 pdp11_conditional_register_usage (void)
2106 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]);
2107 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )
2108 if (TEST_HARD_REG_BIT (x, i))
2109 fixed_regs[i] = call_used_regs[i] = 1;
2113 call_used_regs[AC0_REGNUM] = 1;
2114 if (TARGET_UNIX_ASM)
2116 /* Change names of FPU registers for the UNIX assembler. */
2117 reg_names[8] = "fr0";
2118 reg_names[9] = "fr1";
2119 reg_names[10] = "fr2";
2120 reg_names[11] = "fr3";
2121 reg_names[12] = "fr4";
2122 reg_names[13] = "fr5";
2127 pdp11_function_section (tree decl ATTRIBUTE_UNUSED,
2128 enum node_frequency freq ATTRIBUTE_UNUSED,
2129 bool startup ATTRIBUTE_UNUSED,
2130 bool exit ATTRIBUTE_UNUSED)
2135 struct gcc_target targetm = TARGET_INITIALIZER;