1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; millicode call delay slot description. Note it disallows delay slot
109 ;; when TARGET_PORTABLE_RUNTIME is true.
110 (define_delay (eq_attr "type" "milli")
111 [(and (eq_attr "in_call_delay" "true")
112 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
115 ;; Return and other similar instructions.
116 (define_delay (eq_attr "type" "branch,parallel_branch")
117 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
119 ;; Floating point conditional branch delay slot description and
120 (define_delay (eq_attr "type" "fbranch")
121 [(eq_attr "in_branch_delay" "true")
122 (eq_attr "in_nullified_branch_delay" "true")
125 ;; Integer conditional branch delay slot description.
126 ;; Nullification of conditional branches on the PA is dependent on the
127 ;; direction of the branch. Forward branches nullify true and
128 ;; backward branches nullify false. If the direction is unknown
129 ;; then nullification is not allowed.
130 (define_delay (eq_attr "type" "cbranch")
131 [(eq_attr "in_branch_delay" "true")
132 (and (eq_attr "in_nullified_branch_delay" "true")
133 (attr_flag "forward"))
134 (and (eq_attr "in_nullified_branch_delay" "true")
135 (attr_flag "backward"))])
137 (define_delay (and (eq_attr "type" "uncond_branch")
138 (eq (symbol_ref "following_call (insn)")
140 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
142 ;; Function units of the HPPA. The following data is for the 700 CPUs
143 ;; (Mustang CPU + Timex FPU aka PA-89) because that's what I have the docs for.
144 ;; Scheduling instructions for PA-83 machines according to the Snake
145 ;; constraints shouldn't hurt.
147 ;; (define_function_unit {name} {num-units} {n-users} {test}
148 ;; {ready-delay} {issue-delay} [{conflict-list}])
151 ;; (Noted only for documentation; units that take one cycle do not need to
154 ;; (define_function_unit "alu" 1 0
155 ;; (and (eq_attr "type" "unary,shift,nullshift,binary,move,address")
156 ;; (eq_attr "cpu" "700"))
160 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
161 ;; load: 2, fpload: 3
162 ;; store, fpstore: 3, no D-cache operations should be scheduled.
164 (define_function_unit "pa700memory" 1 0
165 (and (eq_attr "type" "load,fpload")
166 (eq_attr "cpu" "700")) 2 0)
167 (define_function_unit "pa700memory" 1 0
168 (and (eq_attr "type" "store,fpstore")
169 (eq_attr "cpu" "700")) 3 3)
171 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
173 ;; Instruction Time Unit Minimum Distance (unit contention)
180 ;; fmpyadd 3 ALU,MPY 2
181 ;; fmpysub 3 ALU,MPY 2
182 ;; fmpycfxt 3 ALU,MPY 2
185 ;; fdiv,sgl 10 MPY 10
186 ;; fdiv,dbl 12 MPY 12
187 ;; fsqrt,sgl 14 MPY 14
188 ;; fsqrt,dbl 18 MPY 18
190 (define_function_unit "pa700fp_alu" 1 0
191 (and (eq_attr "type" "fpcc")
192 (eq_attr "cpu" "700")) 4 2)
193 (define_function_unit "pa700fp_alu" 1 0
194 (and (eq_attr "type" "fpalu")
195 (eq_attr "cpu" "700")) 3 2)
196 (define_function_unit "pa700fp_mpy" 1 0
197 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
198 (eq_attr "cpu" "700")) 3 2)
199 (define_function_unit "pa700fp_mpy" 1 0
200 (and (eq_attr "type" "fpdivsgl")
201 (eq_attr "cpu" "700")) 10 10)
202 (define_function_unit "pa700fp_mpy" 1 0
203 (and (eq_attr "type" "fpdivdbl")
204 (eq_attr "cpu" "700")) 12 12)
205 (define_function_unit "pa700fp_mpy" 1 0
206 (and (eq_attr "type" "fpsqrtsgl")
207 (eq_attr "cpu" "700")) 14 14)
208 (define_function_unit "pa700fp_mpy" 1 0
209 (and (eq_attr "type" "fpsqrtdbl")
210 (eq_attr "cpu" "700")) 18 18)
212 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
213 ;; floating point computations with non-floating point computations (fp loads
214 ;; and stores are not fp computations).
217 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
218 ;; take two cycles, during which no Dcache operations should be scheduled.
219 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
220 ;; all have the same memory characteristics if one disregards cache misses.
221 (define_function_unit "pa7100memory" 1 0
222 (and (eq_attr "type" "load,fpload")
223 (eq_attr "cpu" "7100,7100LC")) 2 0)
224 (define_function_unit "pa7100memory" 1 0
225 (and (eq_attr "type" "store,fpstore")
226 (eq_attr "cpu" "7100,7100LC")) 2 2)
228 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
230 ;; Instruction Time Unit Minimum Distance (unit contention)
237 ;; fmpyadd 2 ALU,MPY 1
238 ;; fmpysub 2 ALU,MPY 1
239 ;; fmpycfxt 2 ALU,MPY 1
243 ;; fdiv,dbl 15 DIV 15
245 ;; fsqrt,dbl 15 DIV 15
247 (define_function_unit "pa7100fp_alu" 1 0
248 (and (eq_attr "type" "fpcc,fpalu")
249 (eq_attr "cpu" "7100")) 2 1)
250 (define_function_unit "pa7100fp_mpy" 1 0
251 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
252 (eq_attr "cpu" "7100")) 2 1)
253 (define_function_unit "pa7100fp_div" 1 0
254 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
255 (eq_attr "cpu" "7100")) 8 8)
256 (define_function_unit "pa7100fp_div" 1 0
257 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
258 (eq_attr "cpu" "7100")) 15 15)
260 ;; To encourage dual issue we define function units corresponding to
261 ;; the instructions which can be dual issued. This is a rather crude
262 ;; approximation, the "pa7100nonflop" test in particular could be refined.
263 (define_function_unit "pa7100flop" 1 1
265 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
266 (eq_attr "cpu" "7100")) 1 1)
268 (define_function_unit "pa7100nonflop" 1 1
270 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
271 (eq_attr "cpu" "7100")) 1 1)
274 ;; Memory subsystem works just like 7100/7150 (except for cache miss times which
275 ;; we don't model here).
277 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
278 ;; Note divides and sqrt flops lock the cpu until the flop is
279 ;; finished. fmpy and xmpyu (fmpyi) lock the cpu for one cycle.
280 ;; There's no way to avoid the penalty.
282 ;; Instruction Time Unit Minimum Distance (unit contention)
289 ;; fmpyadd,sgl 2 ALU,MPY 1
290 ;; fmpyadd,dbl 3 ALU,MPY 2
291 ;; fmpysub,sgl 2 ALU,MPY 1
292 ;; fmpysub,dbl 3 ALU,MPY 2
293 ;; fmpycfxt,sgl 2 ALU,MPY 1
294 ;; fmpycfxt,dbl 3 ALU,MPY 2
299 ;; fdiv,dbl 15 DIV 15
301 ;; fsqrt,dbl 15 DIV 15
303 (define_function_unit "pa7100LCfp_alu" 1 0
304 (and (eq_attr "type" "fpcc,fpalu")
305 (eq_attr "cpu" "7100LC,7200")) 2 1)
306 (define_function_unit "pa7100LCfp_mpy" 1 0
307 (and (eq_attr "type" "fpmulsgl")
308 (eq_attr "cpu" "7100LC,7200")) 2 1)
309 (define_function_unit "pa7100LCfp_mpy" 1 0
310 (and (eq_attr "type" "fpmuldbl")
311 (eq_attr "cpu" "7100LC,7200")) 3 2)
312 (define_function_unit "pa7100LCfp_div" 1 0
313 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
314 (eq_attr "cpu" "7100LC,7200")) 8 8)
315 (define_function_unit "pa7100LCfp_div" 1 0
316 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
317 (eq_attr "cpu" "7100LC,7200")) 15 15)
319 ;; Define the various functional units for dual-issue.
321 ;; There's only one floating point unit.
322 (define_function_unit "pa7100LCflop" 1 1
324 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
325 (eq_attr "cpu" "7100LC,7200")) 1 1)
327 ;; Shifts and memory ops execute in only one of the integer ALUs
328 (define_function_unit "pa7100LCshiftmem" 1 1
330 (eq_attr "type" "shift,nullshift,load,fpload,store,fpstore")
331 (eq_attr "cpu" "7100LC,7200")) 1 1)
333 ;; We have two basic ALUs.
334 (define_function_unit "pa7100LCalu" 2 1
336 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
337 (eq_attr "cpu" "7100LC,7200")) 1 1)
339 ;; I don't have complete information on the PA7200; however, most of
340 ;; what I've heard makes it look like a 7100LC without the store-store
341 ;; penalty. So that's how we'll model it.
343 ;; Memory. Disregarding Cache misses, memory loads and stores take
344 ;; two cycles. Any special cases are handled in pa_adjust_cost.
345 (define_function_unit "pa7200memory" 1 0
346 (and (eq_attr "type" "load,fpload,store,fpstore")
347 (eq_attr "cpu" "7200")) 2 0)
349 ;; I don't have detailed information on the PA7200 FP pipeline, so I
350 ;; treat it just like the 7100LC pipeline.
351 ;; Similarly for the multi-issue fake units.
354 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
355 ;; traditional architecture.
357 ;; The PA8000 has a large (56) entry reorder buffer that is split between
358 ;; memory and non-memory operations.
360 ;; The PA800 can issue two memory and two non-memory operations per cycle to
361 ;; the function units. Similarly, the PA8000 can retire two memory and two
362 ;; non-memory operations per cycle.
364 ;; Given the large reorder buffer, the processor can hide most latencies.
365 ;; According to HP, they've got the best results by scheduling for retirement
366 ;; bandwidth with limited latency scheduling for floating point operations.
367 ;; Latency for integer operations and memory references is ignored.
369 ;; We claim floating point operations have a 2 cycle latency and are
370 ;; fully pipelined, except for div and sqrt which are not pipelined.
372 ;; It is not necessary to define the shifter and integer alu units.
374 ;; These first two define_unit_unit descriptions model retirement from
375 ;; the reorder buffer.
376 (define_function_unit "pa8000lsu" 2 1
378 (eq_attr "type" "load,fpload,store,fpstore")
379 (eq_attr "cpu" "8000")) 1 1)
381 (define_function_unit "pa8000alu" 2 1
383 (eq_attr "type" "!load,fpload,store,fpstore")
384 (eq_attr "cpu" "8000")) 1 1)
386 ;; Claim floating point ops have a 2 cycle latency, excluding div and
387 ;; sqrt, which are not pipelined and issue to different units.
388 (define_function_unit "pa8000fmac" 2 0
390 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
391 (eq_attr "cpu" "8000")) 2 1)
393 (define_function_unit "pa8000fdiv" 2 1
395 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
396 (eq_attr "cpu" "8000")) 17 17)
398 (define_function_unit "pa8000fdiv" 2 1
400 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
401 (eq_attr "cpu" "8000")) 31 31)
404 ;; Compare instructions.
405 ;; This controls RTL generation and register allocation.
407 ;; We generate RTL for comparisons and branches by having the cmpxx
408 ;; patterns store away the operands. Then, the scc and bcc patterns
409 ;; emit RTL for both the compare and the branch.
412 (define_expand "cmpdi"
414 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
415 (match_operand:DI 1 "register_operand" "")))]
420 hppa_compare_op0 = operands[0];
421 hppa_compare_op1 = operands[1];
422 hppa_branch_type = CMP_SI;
426 (define_expand "cmpsi"
428 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
429 (match_operand:SI 1 "arith5_operand" "")))]
433 hppa_compare_op0 = operands[0];
434 hppa_compare_op1 = operands[1];
435 hppa_branch_type = CMP_SI;
439 (define_expand "cmpsf"
441 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
442 (match_operand:SF 1 "reg_or_0_operand" "")))]
443 "! TARGET_SOFT_FLOAT"
446 hppa_compare_op0 = operands[0];
447 hppa_compare_op1 = operands[1];
448 hppa_branch_type = CMP_SF;
452 (define_expand "cmpdf"
454 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
455 (match_operand:DF 1 "reg_or_0_operand" "")))]
456 "! TARGET_SOFT_FLOAT"
459 hppa_compare_op0 = operands[0];
460 hppa_compare_op1 = operands[1];
461 hppa_branch_type = CMP_DF;
467 (match_operator:CCFP 2 "comparison_operator"
468 [(match_operand:SF 0 "reg_or_0_operand" "fG")
469 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
470 "! TARGET_SOFT_FLOAT"
471 "fcmp,sgl,%Y2 %f0,%f1"
472 [(set_attr "length" "4")
473 (set_attr "type" "fpcc")])
477 (match_operator:CCFP 2 "comparison_operator"
478 [(match_operand:DF 0 "reg_or_0_operand" "fG")
479 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
480 "! TARGET_SOFT_FLOAT"
481 "fcmp,dbl,%Y2 %f0,%f1"
482 [(set_attr "length" "4")
483 (set_attr "type" "fpcc")])
488 [(set (match_operand:SI 0 "register_operand" "")
494 /* fp scc patterns rarely match, and are not a win on the PA. */
495 if (hppa_branch_type != CMP_SI)
497 /* set up operands from compare. */
498 operands[1] = hppa_compare_op0;
499 operands[2] = hppa_compare_op1;
500 /* fall through and generate default code */
504 [(set (match_operand:SI 0 "register_operand" "")
510 /* fp scc patterns rarely match, and are not a win on the PA. */
511 if (hppa_branch_type != CMP_SI)
513 operands[1] = hppa_compare_op0;
514 operands[2] = hppa_compare_op1;
518 [(set (match_operand:SI 0 "register_operand" "")
524 /* fp scc patterns rarely match, and are not a win on the PA. */
525 if (hppa_branch_type != CMP_SI)
527 operands[1] = hppa_compare_op0;
528 operands[2] = hppa_compare_op1;
532 [(set (match_operand:SI 0 "register_operand" "")
538 /* fp scc patterns rarely match, and are not a win on the PA. */
539 if (hppa_branch_type != CMP_SI)
541 operands[1] = hppa_compare_op0;
542 operands[2] = hppa_compare_op1;
546 [(set (match_operand:SI 0 "register_operand" "")
552 /* fp scc patterns rarely match, and are not a win on the PA. */
553 if (hppa_branch_type != CMP_SI)
555 operands[1] = hppa_compare_op0;
556 operands[2] = hppa_compare_op1;
560 [(set (match_operand:SI 0 "register_operand" "")
566 /* fp scc patterns rarely match, and are not a win on the PA. */
567 if (hppa_branch_type != CMP_SI)
569 operands[1] = hppa_compare_op0;
570 operands[2] = hppa_compare_op1;
573 (define_expand "sltu"
574 [(set (match_operand:SI 0 "register_operand" "")
575 (ltu:SI (match_dup 1)
580 if (hppa_branch_type != CMP_SI)
582 operands[1] = hppa_compare_op0;
583 operands[2] = hppa_compare_op1;
586 (define_expand "sgtu"
587 [(set (match_operand:SI 0 "register_operand" "")
588 (gtu:SI (match_dup 1)
593 if (hppa_branch_type != CMP_SI)
595 operands[1] = hppa_compare_op0;
596 operands[2] = hppa_compare_op1;
599 (define_expand "sleu"
600 [(set (match_operand:SI 0 "register_operand" "")
601 (leu:SI (match_dup 1)
606 if (hppa_branch_type != CMP_SI)
608 operands[1] = hppa_compare_op0;
609 operands[2] = hppa_compare_op1;
612 (define_expand "sgeu"
613 [(set (match_operand:SI 0 "register_operand" "")
614 (geu:SI (match_dup 1)
619 if (hppa_branch_type != CMP_SI)
621 operands[1] = hppa_compare_op0;
622 operands[2] = hppa_compare_op1;
625 ;; Instruction canonicalization puts immediate operands second, which
626 ;; is the reverse of what we want.
629 [(set (match_operand:SI 0 "register_operand" "=r")
630 (match_operator:SI 3 "comparison_operator"
631 [(match_operand:SI 1 "register_operand" "r")
632 (match_operand:SI 2 "arith11_operand" "rI")]))]
634 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
635 [(set_attr "type" "binary")
636 (set_attr "length" "8")])
639 [(set (match_operand:DI 0 "register_operand" "=r")
640 (match_operator:DI 3 "comparison_operator"
641 [(match_operand:DI 1 "register_operand" "r")
642 (match_operand:DI 2 "arith11_operand" "rI")]))]
644 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
645 [(set_attr "type" "binary")
646 (set_attr "length" "8")])
648 (define_insn "iorscc"
649 [(set (match_operand:SI 0 "register_operand" "=r")
650 (ior:SI (match_operator:SI 3 "comparison_operator"
651 [(match_operand:SI 1 "register_operand" "r")
652 (match_operand:SI 2 "arith11_operand" "rI")])
653 (match_operator:SI 6 "comparison_operator"
654 [(match_operand:SI 4 "register_operand" "r")
655 (match_operand:SI 5 "arith11_operand" "rI")])))]
657 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
658 [(set_attr "type" "binary")
659 (set_attr "length" "12")])
662 [(set (match_operand:DI 0 "register_operand" "=r")
663 (ior:DI (match_operator:DI 3 "comparison_operator"
664 [(match_operand:DI 1 "register_operand" "r")
665 (match_operand:DI 2 "arith11_operand" "rI")])
666 (match_operator:DI 6 "comparison_operator"
667 [(match_operand:DI 4 "register_operand" "r")
668 (match_operand:DI 5 "arith11_operand" "rI")])))]
670 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
671 [(set_attr "type" "binary")
672 (set_attr "length" "12")])
674 ;; Combiner patterns for common operations performed with the output
675 ;; from an scc insn (negscc and incscc).
676 (define_insn "negscc"
677 [(set (match_operand:SI 0 "register_operand" "=r")
678 (neg:SI (match_operator:SI 3 "comparison_operator"
679 [(match_operand:SI 1 "register_operand" "r")
680 (match_operand:SI 2 "arith11_operand" "rI")])))]
682 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
683 [(set_attr "type" "binary")
684 (set_attr "length" "8")])
687 [(set (match_operand:DI 0 "register_operand" "=r")
688 (neg:DI (match_operator:DI 3 "comparison_operator"
689 [(match_operand:DI 1 "register_operand" "r")
690 (match_operand:DI 2 "arith11_operand" "rI")])))]
692 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
693 [(set_attr "type" "binary")
694 (set_attr "length" "8")])
696 ;; Patterns for adding/subtracting the result of a boolean expression from
697 ;; a register. First we have special patterns that make use of the carry
698 ;; bit, and output only two instructions. For the cases we can't in
699 ;; general do in two instructions, the incscc pattern at the end outputs
700 ;; two or three instructions.
703 [(set (match_operand:SI 0 "register_operand" "=r")
704 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
705 (match_operand:SI 3 "arith11_operand" "rI"))
706 (match_operand:SI 1 "register_operand" "r")))]
708 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
709 [(set_attr "type" "binary")
710 (set_attr "length" "8")])
713 [(set (match_operand:DI 0 "register_operand" "=r")
714 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
715 (match_operand:DI 3 "arith11_operand" "rI"))
716 (match_operand:DI 1 "register_operand" "r")))]
718 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
719 [(set_attr "type" "binary")
720 (set_attr "length" "8")])
722 ; This need only accept registers for op3, since canonicalization
723 ; replaces geu with gtu when op3 is an integer.
725 [(set (match_operand:SI 0 "register_operand" "=r")
726 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
727 (match_operand:SI 3 "register_operand" "r"))
728 (match_operand:SI 1 "register_operand" "r")))]
730 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
731 [(set_attr "type" "binary")
732 (set_attr "length" "8")])
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
737 (match_operand:DI 3 "register_operand" "r"))
738 (match_operand:DI 1 "register_operand" "r")))]
740 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
741 [(set_attr "type" "binary")
742 (set_attr "length" "8")])
744 ; Match only integers for op3 here. This is used as canonical form of the
745 ; geu pattern when op3 is an integer. Don't match registers since we can't
746 ; make better code than the general incscc pattern.
748 [(set (match_operand:SI 0 "register_operand" "=r")
749 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
750 (match_operand:SI 3 "int11_operand" "I"))
751 (match_operand:SI 1 "register_operand" "r")))]
753 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
754 [(set_attr "type" "binary")
755 (set_attr "length" "8")])
758 [(set (match_operand:DI 0 "register_operand" "=r")
759 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
760 (match_operand:DI 3 "int11_operand" "I"))
761 (match_operand:DI 1 "register_operand" "r")))]
763 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
764 [(set_attr "type" "binary")
765 (set_attr "length" "8")])
767 (define_insn "incscc"
768 [(set (match_operand:SI 0 "register_operand" "=r,r")
769 (plus:SI (match_operator:SI 4 "comparison_operator"
770 [(match_operand:SI 2 "register_operand" "r,r")
771 (match_operand:SI 3 "arith11_operand" "rI,rI")])
772 (match_operand:SI 1 "register_operand" "0,?r")))]
775 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
776 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
777 [(set_attr "type" "binary,binary")
778 (set_attr "length" "8,12")])
781 [(set (match_operand:DI 0 "register_operand" "=r,r")
782 (plus:DI (match_operator:DI 4 "comparison_operator"
783 [(match_operand:DI 2 "register_operand" "r,r")
784 (match_operand:DI 3 "arith11_operand" "rI,rI")])
785 (match_operand:DI 1 "register_operand" "0,?r")))]
788 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
789 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
790 [(set_attr "type" "binary,binary")
791 (set_attr "length" "8,12")])
794 [(set (match_operand:SI 0 "register_operand" "=r")
795 (minus:SI (match_operand:SI 1 "register_operand" "r")
796 (gtu:SI (match_operand:SI 2 "register_operand" "r")
797 (match_operand:SI 3 "arith11_operand" "rI"))))]
799 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
800 [(set_attr "type" "binary")
801 (set_attr "length" "8")])
804 [(set (match_operand:DI 0 "register_operand" "=r")
805 (minus:DI (match_operand:DI 1 "register_operand" "r")
806 (gtu:DI (match_operand:DI 2 "register_operand" "r")
807 (match_operand:DI 3 "arith11_operand" "rI"))))]
809 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
810 [(set_attr "type" "binary")
811 (set_attr "length" "8")])
814 [(set (match_operand:SI 0 "register_operand" "=r")
815 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
816 (gtu:SI (match_operand:SI 2 "register_operand" "r")
817 (match_operand:SI 3 "arith11_operand" "rI")))
818 (match_operand:SI 4 "register_operand" "r")))]
820 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
821 [(set_attr "type" "binary")
822 (set_attr "length" "8")])
825 [(set (match_operand:DI 0 "register_operand" "=r")
826 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
827 (gtu:DI (match_operand:DI 2 "register_operand" "r")
828 (match_operand:DI 3 "arith11_operand" "rI")))
829 (match_operand:DI 4 "register_operand" "r")))]
831 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
832 [(set_attr "type" "binary")
833 (set_attr "length" "8")])
835 ; This need only accept registers for op3, since canonicalization
836 ; replaces ltu with leu when op3 is an integer.
838 [(set (match_operand:SI 0 "register_operand" "=r")
839 (minus:SI (match_operand:SI 1 "register_operand" "r")
840 (ltu:SI (match_operand:SI 2 "register_operand" "r")
841 (match_operand:SI 3 "register_operand" "r"))))]
843 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
844 [(set_attr "type" "binary")
845 (set_attr "length" "8")])
848 [(set (match_operand:DI 0 "register_operand" "=r")
849 (minus:DI (match_operand:DI 1 "register_operand" "r")
850 (ltu:DI (match_operand:DI 2 "register_operand" "r")
851 (match_operand:DI 3 "register_operand" "r"))))]
853 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
854 [(set_attr "type" "binary")
855 (set_attr "length" "8")])
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
860 (ltu:SI (match_operand:SI 2 "register_operand" "r")
861 (match_operand:SI 3 "register_operand" "r")))
862 (match_operand:SI 4 "register_operand" "r")))]
864 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
865 [(set_attr "type" "binary")
866 (set_attr "length" "8")])
869 [(set (match_operand:DI 0 "register_operand" "=r")
870 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
871 (ltu:DI (match_operand:DI 2 "register_operand" "r")
872 (match_operand:DI 3 "register_operand" "r")))
873 (match_operand:DI 4 "register_operand" "r")))]
875 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
876 [(set_attr "type" "binary")
877 (set_attr "length" "8")])
879 ; Match only integers for op3 here. This is used as canonical form of the
880 ; ltu pattern when op3 is an integer. Don't match registers since we can't
881 ; make better code than the general incscc pattern.
883 [(set (match_operand:SI 0 "register_operand" "=r")
884 (minus:SI (match_operand:SI 1 "register_operand" "r")
885 (leu:SI (match_operand:SI 2 "register_operand" "r")
886 (match_operand:SI 3 "int11_operand" "I"))))]
888 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
889 [(set_attr "type" "binary")
890 (set_attr "length" "8")])
893 [(set (match_operand:DI 0 "register_operand" "=r")
894 (minus:DI (match_operand:DI 1 "register_operand" "r")
895 (leu:DI (match_operand:DI 2 "register_operand" "r")
896 (match_operand:DI 3 "int11_operand" "I"))))]
898 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
899 [(set_attr "type" "binary")
900 (set_attr "length" "8")])
903 [(set (match_operand:SI 0 "register_operand" "=r")
904 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
905 (leu:SI (match_operand:SI 2 "register_operand" "r")
906 (match_operand:SI 3 "int11_operand" "I")))
907 (match_operand:SI 4 "register_operand" "r")))]
909 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
910 [(set_attr "type" "binary")
911 (set_attr "length" "8")])
914 [(set (match_operand:DI 0 "register_operand" "=r")
915 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
916 (leu:DI (match_operand:DI 2 "register_operand" "r")
917 (match_operand:DI 3 "int11_operand" "I")))
918 (match_operand:DI 4 "register_operand" "r")))]
920 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
921 [(set_attr "type" "binary")
922 (set_attr "length" "8")])
924 (define_insn "decscc"
925 [(set (match_operand:SI 0 "register_operand" "=r,r")
926 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
927 (match_operator:SI 4 "comparison_operator"
928 [(match_operand:SI 2 "register_operand" "r,r")
929 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
932 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
933 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
934 [(set_attr "type" "binary,binary")
935 (set_attr "length" "8,12")])
938 [(set (match_operand:DI 0 "register_operand" "=r,r")
939 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
940 (match_operator:DI 4 "comparison_operator"
941 [(match_operand:DI 2 "register_operand" "r,r")
942 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
945 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
946 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
947 [(set_attr "type" "binary,binary")
948 (set_attr "length" "8,12")])
950 ; Patterns for max and min. (There is no need for an earlyclobber in the
951 ; last alternative since the middle alternative will match if op0 == op1.)
953 (define_insn "sminsi3"
954 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
955 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
956 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
959 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
960 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
961 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
962 [(set_attr "type" "multi,multi,multi")
963 (set_attr "length" "8,8,8")])
965 (define_insn "smindi3"
966 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
967 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
968 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
971 cmpclr,*> %2,%0,%%r0\;copy %2,%0
972 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
973 cmpclr,*> %1,%r2,%0\;copy %1,%0"
974 [(set_attr "type" "multi,multi,multi")
975 (set_attr "length" "8,8,8")])
977 (define_insn "uminsi3"
978 [(set (match_operand:SI 0 "register_operand" "=r,r")
979 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
980 (match_operand:SI 2 "arith11_operand" "r,I")))]
983 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
984 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
985 [(set_attr "type" "multi,multi")
986 (set_attr "length" "8,8")])
988 (define_insn "umindi3"
989 [(set (match_operand:DI 0 "register_operand" "=r,r")
990 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
991 (match_operand:DI 2 "arith11_operand" "r,I")))]
994 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
995 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
996 [(set_attr "type" "multi,multi")
997 (set_attr "length" "8,8")])
999 (define_insn "smaxsi3"
1000 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1001 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1002 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1005 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1006 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1007 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1008 [(set_attr "type" "multi,multi,multi")
1009 (set_attr "length" "8,8,8")])
1011 (define_insn "smaxdi3"
1012 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1013 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1014 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1017 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1018 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1019 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1020 [(set_attr "type" "multi,multi,multi")
1021 (set_attr "length" "8,8,8")])
1023 (define_insn "umaxsi3"
1024 [(set (match_operand:SI 0 "register_operand" "=r,r")
1025 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1026 (match_operand:SI 2 "arith11_operand" "r,I")))]
1029 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1030 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1031 [(set_attr "type" "multi,multi")
1032 (set_attr "length" "8,8")])
1034 (define_insn "umaxdi3"
1035 [(set (match_operand:DI 0 "register_operand" "=r,r")
1036 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1037 (match_operand:DI 2 "arith11_operand" "r,I")))]
1040 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1041 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1042 [(set_attr "type" "multi,multi")
1043 (set_attr "length" "8,8")])
1045 (define_insn "abssi2"
1046 [(set (match_operand:SI 0 "register_operand" "=r")
1047 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1049 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1050 [(set_attr "type" "multi")
1051 (set_attr "length" "8")])
1053 (define_insn "absdi2"
1054 [(set (match_operand:DI 0 "register_operand" "=r")
1055 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1057 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1058 [(set_attr "type" "multi")
1059 (set_attr "length" "8")])
1061 ;;; Experimental conditional move patterns
1063 (define_expand "movsicc"
1064 [(set (match_operand:SI 0 "register_operand" "")
1066 (match_operator 1 "comparison_operator"
1069 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1070 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1074 enum rtx_code code = GET_CODE (operands[1]);
1076 if (hppa_branch_type != CMP_SI)
1079 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1080 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1083 /* operands[1] is currently the result of compare_from_rtx. We want to
1084 emit a compare of the original operands. */
1085 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1086 operands[4] = hppa_compare_op0;
1087 operands[5] = hppa_compare_op1;
1090 ;; We used to accept any register for op1.
1092 ;; However, it loses sometimes because the compiler will end up using
1093 ;; different registers for op0 and op1 in some critical cases. local-alloc
1094 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1096 ;; If/when global register allocation supports tying we should allow any
1097 ;; register for op1 again.
1099 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1101 (match_operator 5 "comparison_operator"
1102 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1103 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1104 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1108 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi 0,%0
1109 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldi %1,%0
1110 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldil L'%1,%0
1111 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1112 [(set_attr "type" "multi,multi,multi,nullshift")
1113 (set_attr "length" "8,8,8,8")])
1116 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1118 (match_operator 5 "comparison_operator"
1119 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1120 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1121 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1122 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1125 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1126 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1127 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1128 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1129 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1130 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1131 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1132 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1133 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1134 (set_attr "length" "8,8,8,8,8,8,8,8")])
1136 (define_expand "movdicc"
1137 [(set (match_operand:DI 0 "register_operand" "")
1139 (match_operator 1 "comparison_operator"
1142 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1143 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1147 enum rtx_code code = GET_CODE (operands[1]);
1149 if (hppa_branch_type != CMP_SI)
1152 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1153 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1156 /* operands[1] is currently the result of compare_from_rtx. We want to
1157 emit a compare of the original operands. */
1158 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1159 operands[4] = hppa_compare_op0;
1160 operands[5] = hppa_compare_op1;
1163 ; We need the first constraint alternative in order to avoid
1164 ; earlyclobbers on all other alternatives.
1166 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1168 (match_operator 5 "comparison_operator"
1169 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1170 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1171 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1175 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi 0,%0
1176 cmp%I4clr,*%B5 %4,%3,%0\;copy %1,%0
1177 cmp%I4clr,*%B5 %4,%3,%0\;ldi %1,%0
1178 cmp%I4clr,*%B5 %4,%3,%0\;ldil L'%1,%0
1179 cmp%I4clr,*%B5 %4,%3,%0\;depdi,z %z1,%0"
1180 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1181 (set_attr "length" "8,8,8,8,8")])
1184 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1186 (match_operator 5 "comparison_operator"
1187 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1188 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1189 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1190 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1193 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1194 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1195 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1196 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1197 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1198 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1199 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1200 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1201 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1202 (set_attr "length" "8,8,8,8,8,8,8,8")])
1204 ;; Conditional Branches
1206 (define_expand "beq"
1208 (if_then_else (eq (match_dup 1) (match_dup 2))
1209 (label_ref (match_operand 0 "" ""))
1214 if (hppa_branch_type != CMP_SI)
1216 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1217 emit_bcond_fp (NE, operands[0]);
1220 /* set up operands from compare. */
1221 operands[1] = hppa_compare_op0;
1222 operands[2] = hppa_compare_op1;
1223 /* fall through and generate default code */
1226 (define_expand "bne"
1228 (if_then_else (ne (match_dup 1) (match_dup 2))
1229 (label_ref (match_operand 0 "" ""))
1234 if (hppa_branch_type != CMP_SI)
1236 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1237 emit_bcond_fp (NE, operands[0]);
1240 operands[1] = hppa_compare_op0;
1241 operands[2] = hppa_compare_op1;
1244 (define_expand "bgt"
1246 (if_then_else (gt (match_dup 1) (match_dup 2))
1247 (label_ref (match_operand 0 "" ""))
1252 if (hppa_branch_type != CMP_SI)
1254 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1255 emit_bcond_fp (NE, operands[0]);
1258 operands[1] = hppa_compare_op0;
1259 operands[2] = hppa_compare_op1;
1262 (define_expand "blt"
1264 (if_then_else (lt (match_dup 1) (match_dup 2))
1265 (label_ref (match_operand 0 "" ""))
1270 if (hppa_branch_type != CMP_SI)
1272 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1273 emit_bcond_fp (NE, operands[0]);
1276 operands[1] = hppa_compare_op0;
1277 operands[2] = hppa_compare_op1;
1280 (define_expand "bge"
1282 (if_then_else (ge (match_dup 1) (match_dup 2))
1283 (label_ref (match_operand 0 "" ""))
1288 if (hppa_branch_type != CMP_SI)
1290 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1291 emit_bcond_fp (NE, operands[0]);
1294 operands[1] = hppa_compare_op0;
1295 operands[2] = hppa_compare_op1;
1298 (define_expand "ble"
1300 (if_then_else (le (match_dup 1) (match_dup 2))
1301 (label_ref (match_operand 0 "" ""))
1306 if (hppa_branch_type != CMP_SI)
1308 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1309 emit_bcond_fp (NE, operands[0]);
1312 operands[1] = hppa_compare_op0;
1313 operands[2] = hppa_compare_op1;
1316 (define_expand "bgtu"
1318 (if_then_else (gtu (match_dup 1) (match_dup 2))
1319 (label_ref (match_operand 0 "" ""))
1324 if (hppa_branch_type != CMP_SI)
1326 operands[1] = hppa_compare_op0;
1327 operands[2] = hppa_compare_op1;
1330 (define_expand "bltu"
1332 (if_then_else (ltu (match_dup 1) (match_dup 2))
1333 (label_ref (match_operand 0 "" ""))
1338 if (hppa_branch_type != CMP_SI)
1340 operands[1] = hppa_compare_op0;
1341 operands[2] = hppa_compare_op1;
1344 (define_expand "bgeu"
1346 (if_then_else (geu (match_dup 1) (match_dup 2))
1347 (label_ref (match_operand 0 "" ""))
1352 if (hppa_branch_type != CMP_SI)
1354 operands[1] = hppa_compare_op0;
1355 operands[2] = hppa_compare_op1;
1358 (define_expand "bleu"
1360 (if_then_else (leu (match_dup 1) (match_dup 2))
1361 (label_ref (match_operand 0 "" ""))
1366 if (hppa_branch_type != CMP_SI)
1368 operands[1] = hppa_compare_op0;
1369 operands[2] = hppa_compare_op1;
1372 ;; Match the branch patterns.
1375 ;; Note a long backward conditional branch with an annulled delay slot
1376 ;; has a length of 12.
1380 (match_operator 3 "comparison_operator"
1381 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1382 (match_operand:SI 2 "arith5_operand" "rL")])
1383 (label_ref (match_operand 0 "" ""))
1388 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1389 get_attr_length (insn), 0, insn);
1391 [(set_attr "type" "cbranch")
1392 (set (attr "length")
1393 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1396 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1399 (eq (symbol_ref "flag_pic") (const_int 0))
1403 ;; Match the negated branch.
1408 (match_operator 3 "comparison_operator"
1409 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1410 (match_operand:SI 2 "arith5_operand" "rL")])
1412 (label_ref (match_operand 0 "" ""))))]
1416 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1417 get_attr_length (insn), 1, insn);
1419 [(set_attr "type" "cbranch")
1420 (set (attr "length")
1421 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1424 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1427 (eq (symbol_ref "flag_pic") (const_int 0))
1434 (match_operator 3 "comparison_operator"
1435 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1436 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1437 (label_ref (match_operand 0 "" ""))
1442 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1443 get_attr_length (insn), 0, insn);
1445 [(set_attr "type" "cbranch")
1446 (set (attr "length")
1447 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1450 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1453 (eq (symbol_ref "flag_pic") (const_int 0))
1457 ;; Match the negated branch.
1462 (match_operator 3 "comparison_operator"
1463 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1464 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1466 (label_ref (match_operand 0 "" ""))))]
1470 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1471 get_attr_length (insn), 1, insn);
1473 [(set_attr "type" "cbranch")
1474 (set (attr "length")
1475 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1478 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1481 (eq (symbol_ref "flag_pic") (const_int 0))
1487 (match_operator 3 "cmpib_comparison_operator"
1488 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1489 (match_operand:DI 2 "arith5_operand" "rL")])
1490 (label_ref (match_operand 0 "" ""))
1495 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1496 get_attr_length (insn), 0, insn);
1498 [(set_attr "type" "cbranch")
1499 (set (attr "length")
1500 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1503 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1506 (eq (symbol_ref "flag_pic") (const_int 0))
1510 ;; Match the negated branch.
1515 (match_operator 3 "cmpib_comparison_operator"
1516 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1517 (match_operand:DI 2 "arith5_operand" "rL")])
1519 (label_ref (match_operand 0 "" ""))))]
1523 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1524 get_attr_length (insn), 1, insn);
1526 [(set_attr "type" "cbranch")
1527 (set (attr "length")
1528 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1531 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1534 (eq (symbol_ref "flag_pic") (const_int 0))
1538 ;; Branch on Bit patterns.
1542 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1544 (match_operand:SI 1 "uint5_operand" ""))
1546 (label_ref (match_operand 2 "" ""))
1551 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1552 get_attr_length (insn), 0, insn, 0);
1554 [(set_attr "type" "cbranch")
1555 (set (attr "length")
1556 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1564 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1566 (match_operand:DI 1 "uint32_operand" ""))
1568 (label_ref (match_operand 2 "" ""))
1573 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1574 get_attr_length (insn), 0, insn, 0);
1576 [(set_attr "type" "cbranch")
1577 (set (attr "length")
1578 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1586 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1588 (match_operand:SI 1 "uint5_operand" ""))
1591 (label_ref (match_operand 2 "" ""))))]
1595 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1596 get_attr_length (insn), 1, insn, 0);
1598 [(set_attr "type" "cbranch")
1599 (set (attr "length")
1600 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1608 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1610 (match_operand:DI 1 "uint32_operand" ""))
1613 (label_ref (match_operand 2 "" ""))))]
1617 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1618 get_attr_length (insn), 1, insn, 0);
1620 [(set_attr "type" "cbranch")
1621 (set (attr "length")
1622 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1630 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1632 (match_operand:SI 1 "uint5_operand" ""))
1634 (label_ref (match_operand 2 "" ""))
1639 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1640 get_attr_length (insn), 0, insn, 1);
1642 [(set_attr "type" "cbranch")
1643 (set (attr "length")
1644 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1652 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1654 (match_operand:DI 1 "uint32_operand" ""))
1656 (label_ref (match_operand 2 "" ""))
1661 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1662 get_attr_length (insn), 0, insn, 1);
1664 [(set_attr "type" "cbranch")
1665 (set (attr "length")
1666 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1674 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1676 (match_operand:SI 1 "uint5_operand" ""))
1679 (label_ref (match_operand 2 "" ""))))]
1683 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1684 get_attr_length (insn), 1, insn, 1);
1686 [(set_attr "type" "cbranch")
1687 (set (attr "length")
1688 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1696 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1698 (match_operand:DI 1 "uint32_operand" ""))
1701 (label_ref (match_operand 2 "" ""))))]
1705 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1706 get_attr_length (insn), 1, insn, 1);
1708 [(set_attr "type" "cbranch")
1709 (set (attr "length")
1710 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1715 ;; Branch on Variable Bit patterns.
1719 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1721 (match_operand:SI 1 "register_operand" "q"))
1723 (label_ref (match_operand 2 "" ""))
1728 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1729 get_attr_length (insn), 0, insn, 0);
1731 [(set_attr "type" "cbranch")
1732 (set (attr "length")
1733 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1741 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1743 (match_operand:DI 1 "register_operand" "q"))
1745 (label_ref (match_operand 2 "" ""))
1750 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1751 get_attr_length (insn), 0, insn, 0);
1753 [(set_attr "type" "cbranch")
1754 (set (attr "length")
1755 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1763 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1765 (match_operand:SI 1 "register_operand" "q"))
1768 (label_ref (match_operand 2 "" ""))))]
1772 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1773 get_attr_length (insn), 1, insn, 0);
1775 [(set_attr "type" "cbranch")
1776 (set (attr "length")
1777 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1785 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1787 (match_operand:DI 1 "register_operand" "q"))
1790 (label_ref (match_operand 2 "" ""))))]
1794 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1795 get_attr_length (insn), 1, insn, 0);
1797 [(set_attr "type" "cbranch")
1798 (set (attr "length")
1799 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1807 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1809 (match_operand:SI 1 "register_operand" "q"))
1811 (label_ref (match_operand 2 "" ""))
1816 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1817 get_attr_length (insn), 0, insn, 1);
1819 [(set_attr "type" "cbranch")
1820 (set (attr "length")
1821 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1829 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1831 (match_operand:DI 1 "register_operand" "q"))
1833 (label_ref (match_operand 2 "" ""))
1838 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1839 get_attr_length (insn), 0, insn, 1);
1841 [(set_attr "type" "cbranch")
1842 (set (attr "length")
1843 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1851 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1853 (match_operand:SI 1 "register_operand" "q"))
1856 (label_ref (match_operand 2 "" ""))))]
1860 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1861 get_attr_length (insn), 1, insn, 1);
1863 [(set_attr "type" "cbranch")
1864 (set (attr "length")
1865 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1873 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1875 (match_operand:DI 1 "register_operand" "q"))
1878 (label_ref (match_operand 2 "" ""))))]
1882 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1883 get_attr_length (insn), 1, insn, 1);
1885 [(set_attr "type" "cbranch")
1886 (set (attr "length")
1887 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1892 ;; Floating point branches
1894 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1895 (label_ref (match_operand 0 "" ""))
1897 "! TARGET_SOFT_FLOAT"
1900 if (INSN_ANNULLED_BRANCH_P (insn))
1901 return \"ftest\;b,n %0\";
1903 return \"ftest\;b%* %0\";
1905 [(set_attr "type" "fbranch")
1906 (set_attr "length" "8")])
1909 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1911 (label_ref (match_operand 0 "" ""))))]
1912 "! TARGET_SOFT_FLOAT"
1915 if (INSN_ANNULLED_BRANCH_P (insn))
1916 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
1918 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
1920 [(set_attr "type" "fbranch")
1921 (set_attr "length" "12")])
1923 ;; Move instructions
1925 (define_expand "movsi"
1926 [(set (match_operand:SI 0 "general_operand" "")
1927 (match_operand:SI 1 "general_operand" ""))]
1931 if (emit_move_sequence (operands, SImode, 0))
1935 ;; Reloading an SImode or DImode value requires a scratch register if
1936 ;; going in to or out of float point registers.
1938 (define_expand "reload_insi"
1939 [(set (match_operand:SI 0 "register_operand" "=Z")
1940 (match_operand:SI 1 "non_hard_reg_operand" ""))
1941 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1945 if (emit_move_sequence (operands, SImode, operands[2]))
1948 /* We don't want the clobber emitted, so handle this ourselves. */
1949 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1953 (define_expand "reload_outsi"
1954 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
1955 (match_operand:SI 1 "register_operand" "Z"))
1956 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1960 if (emit_move_sequence (operands, SImode, operands[2]))
1963 /* We don't want the clobber emitted, so handle this ourselves. */
1964 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1968 ;;; pic symbol references
1971 [(set (match_operand:SI 0 "register_operand" "=r")
1972 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
1973 (match_operand:SI 2 "symbolic_operand" ""))))]
1974 "flag_pic && operands[1] == pic_offset_table_rtx"
1976 [(set_attr "type" "load")
1977 (set_attr "length" "4")])
1980 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
1981 "=r,r,r,r,r,Q,*q,!f,f,*TR")
1982 (match_operand:SI 1 "move_operand"
1983 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
1984 "(register_operand (operands[0], SImode)
1985 || reg_or_0_operand (operands[1], SImode))
1986 && ! TARGET_SOFT_FLOAT"
1991 {zdepi|depwi,z} %Z1,%0
1998 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
1999 (set_attr "pa_combine_type" "addmove")
2000 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
2003 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2005 (match_operand:SI 1 "move_operand"
2006 "r,J,N,K,RQ,rM,rM"))]
2007 "(register_operand (operands[0], SImode)
2008 || reg_or_0_operand (operands[1], SImode))
2009 && TARGET_SOFT_FLOAT"
2014 {zdepi|depwi,z} %Z1,%0
2018 [(set_attr "type" "move,move,move,move,load,store,move")
2019 (set_attr "pa_combine_type" "addmove")
2020 (set_attr "length" "4,4,4,4,4,4,4")])
2023 [(set (match_operand:SI 0 "register_operand" "=r")
2024 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2025 (match_operand:SI 2 "register_operand" "r"))))]
2026 "! TARGET_DISABLE_INDEXING"
2029 /* Reload can create backwards (relative to cse) unscaled index
2030 address modes when eliminating registers and possibly for
2031 pseudos that don't get hard registers. Deal with it. */
2032 if (operands[2] == hard_frame_pointer_rtx
2033 || operands[2] == stack_pointer_rtx)
2034 return \"{ldwx|ldw} %1(%2),%0\";
2036 return \"{ldwx|ldw} %2(%1),%0\";
2038 [(set_attr "type" "load")
2039 (set_attr "length" "4")])
2042 [(set (match_operand:SI 0 "register_operand" "=r")
2043 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2044 (match_operand:SI 2 "basereg_operand" "r"))))]
2045 "! TARGET_DISABLE_INDEXING"
2048 /* Reload can create backwards (relative to cse) unscaled index
2049 address modes when eliminating registers and possibly for
2050 pseudos that don't get hard registers. Deal with it. */
2051 if (operands[1] == hard_frame_pointer_rtx
2052 || operands[1] == stack_pointer_rtx)
2053 return \"{ldwx|ldw} %2(%1),%0\";
2055 return \"{ldwx|ldw} %1(%2),%0\";
2057 [(set_attr "type" "load")
2058 (set_attr "length" "4")])
2060 ;; Load or store with base-register modification.
2062 (define_expand "pre_load"
2063 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2064 (mem (plus (match_operand 1 "register_operand" "")
2065 (match_operand 2 "pre_cint_operand" ""))))
2067 (plus (match_dup 1) (match_dup 2)))])]
2073 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2076 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2080 (define_insn "pre_ldw"
2081 [(set (match_operand:SI 0 "register_operand" "=r")
2082 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2083 (match_operand:SI 2 "pre_cint_operand" ""))))
2085 (plus:SI (match_dup 1) (match_dup 2)))]
2089 if (INTVAL (operands[2]) < 0)
2090 return \"{ldwm|ldw,mb} %2(%1),%0\";
2091 return \"{ldws|ldw},mb %2(%1),%0\";
2093 [(set_attr "type" "load")
2094 (set_attr "length" "4")])
2096 (define_insn "pre_ldd"
2097 [(set (match_operand:DI 0 "register_operand" "=r")
2098 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2099 (match_operand:DI 2 "pre_cint_operand" ""))))
2101 (plus:DI (match_dup 1) (match_dup 2)))]
2104 [(set_attr "type" "load")
2105 (set_attr "length" "4")])
2108 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2109 (match_operand:SI 1 "pre_cint_operand" "")))
2110 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2112 (plus:SI (match_dup 0) (match_dup 1)))]
2116 if (INTVAL (operands[1]) < 0)
2117 return \"{stwm|stw,mb} %r2,%1(%0)\";
2118 return \"{stws|stw},mb %r2,%1(%0)\";
2120 [(set_attr "type" "store")
2121 (set_attr "length" "4")])
2124 [(set (match_operand:SI 0 "register_operand" "=r")
2125 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2127 (plus:SI (match_dup 1)
2128 (match_operand:SI 2 "post_cint_operand" "")))]
2132 if (INTVAL (operands[2]) > 0)
2133 return \"{ldwm|ldw,ma} %2(%1),%0\";
2134 return \"{ldws|ldw},ma %2(%1),%0\";
2136 [(set_attr "type" "load")
2137 (set_attr "length" "4")])
2139 (define_expand "post_store"
2140 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2141 (match_operand 1 "reg_or_0_operand" ""))
2144 (match_operand 2 "post_cint_operand" "")))])]
2150 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2153 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2157 (define_insn "post_stw"
2158 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2159 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2161 (plus:SI (match_dup 0)
2162 (match_operand:SI 2 "post_cint_operand" "")))]
2166 if (INTVAL (operands[2]) > 0)
2167 return \"{stwm|stw,ma} %r1,%2(%0)\";
2168 return \"{stws|stw},ma %r1,%2(%0)\";
2170 [(set_attr "type" "store")
2171 (set_attr "length" "4")])
2173 (define_insn "post_std"
2174 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2175 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2177 (plus:DI (match_dup 0)
2178 (match_operand:DI 2 "post_cint_operand" "")))]
2181 [(set_attr "type" "store")
2182 (set_attr "length" "4")])
2184 ;; For loading the address of a label while generating PIC code.
2185 ;; Note since this pattern can be created at reload time (via movsi), all
2186 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2188 [(set (match_operand 0 "pmode_register_operand" "=a")
2189 (match_operand 1 "pic_label_operand" ""))]
2193 rtx label_rtx = gen_label_rtx ();
2195 extern FILE *asm_out_file;
2197 xoperands[0] = operands[0];
2198 xoperands[1] = operands[1];
2199 xoperands[2] = label_rtx;
2200 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2201 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2202 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2203 CODE_LABEL_NUMBER (label_rtx));
2205 /* If we're trying to load the address of a label that happens to be
2206 close, then we can use a shorter sequence. */
2207 if (GET_CODE (operands[1]) == LABEL_REF
2208 && INSN_ADDRESSES_SET_P ()
2209 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2210 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2212 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2213 always non-negative. */
2214 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2218 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2219 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2223 [(set_attr "type" "multi")
2224 (set_attr "length" "16")]) ; 12 or 16
2227 [(set (match_operand:SI 0 "register_operand" "=a")
2228 (plus:SI (match_operand:SI 1 "register_operand" "r")
2229 (high:SI (match_operand 2 "" ""))))]
2230 "symbolic_operand (operands[2], Pmode)
2231 && ! function_label_operand (operands[2], Pmode)
2234 [(set_attr "type" "binary")
2235 (set_attr "length" "4")])
2238 [(set (match_operand:DI 0 "register_operand" "=a")
2239 (plus:DI (match_operand:DI 1 "register_operand" "r")
2240 (high:DI (match_operand 2 "" ""))))]
2241 "symbolic_operand (operands[2], Pmode)
2242 && ! function_label_operand (operands[2], Pmode)
2246 [(set_attr "type" "binary")
2247 (set_attr "length" "4")])
2249 ; We need this to make sure CSE doesn't simplify a memory load with a
2250 ; symbolic address, whose content it think it knows. For PIC, what CSE
2251 ; think is the real value will be the address of that value.
2253 [(set (match_operand:SI 0 "register_operand" "=r")
2255 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2257 [(match_operand:SI 2 "symbolic_operand" "")] 0))))]
2263 return \"ldw RT'%G2(%1),%0\";
2265 [(set_attr "type" "load")
2266 (set_attr "length" "4")])
2269 [(set (match_operand:DI 0 "register_operand" "=r")
2271 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2273 [(match_operand:DI 2 "symbolic_operand" "")] 0))))]
2279 return \"ldd RT'%G2(%1),%0\";
2281 [(set_attr "type" "load")
2282 (set_attr "length" "4")])
2284 ;; Always use addil rather than ldil;add sequences. This allows the
2285 ;; HP linker to eliminate the dp relocation if the symbolic operand
2286 ;; lives in the TEXT space.
2288 [(set (match_operand:SI 0 "register_operand" "=a")
2289 (high:SI (match_operand 1 "" "")))]
2290 "symbolic_operand (operands[1], Pmode)
2291 && ! function_label_operand (operands[1], Pmode)
2292 && ! read_only_operand (operands[1], Pmode)
2296 if (TARGET_LONG_LOAD_STORE)
2297 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2299 return \"addil LR'%H1,%%r27\";
2301 [(set_attr "type" "binary")
2302 (set (attr "length")
2303 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2308 ;; This is for use in the prologue/epilogue code. We need it
2309 ;; to add large constants to a stack pointer or frame pointer.
2310 ;; Because of the additional %r1 pressure, we probably do not
2311 ;; want to use this in general code, so make it available
2312 ;; only after reload.
2314 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2315 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2316 (high:SI (match_operand 2 "const_int_operand" ""))))]
2320 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2321 [(set_attr "type" "binary,binary")
2322 (set_attr "length" "4,8")])
2325 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2326 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2327 (high:DI (match_operand 2 "const_int_operand" ""))))]
2328 "reload_completed && TARGET_64BIT"
2331 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2332 [(set_attr "type" "binary,binary")
2333 (set_attr "length" "4,8")])
2336 [(set (match_operand:SI 0 "register_operand" "=r")
2337 (high:SI (match_operand 1 "" "")))]
2338 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2339 && !is_function_label_plus_const (operands[1])"
2342 if (symbolic_operand (operands[1], Pmode))
2343 return \"ldil LR'%H1,%0\";
2345 return \"ldil L'%G1,%0\";
2347 [(set_attr "type" "move")
2348 (set_attr "length" "4")])
2351 [(set (match_operand:DI 0 "register_operand" "=r")
2352 (high:DI (match_operand 1 "const_int_operand" "")))]
2355 [(set_attr "type" "move")
2356 (set_attr "length" "4")])
2359 [(set (match_operand:DI 0 "register_operand" "=r")
2360 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2361 (match_operand:DI 2 "const_int_operand" "i")))]
2364 [(set_attr "type" "move")
2365 (set_attr "length" "4")])
2368 [(set (match_operand:SI 0 "register_operand" "=r")
2369 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2370 (match_operand:SI 2 "immediate_operand" "i")))]
2371 "!is_function_label_plus_const (operands[2])"
2374 if (flag_pic && symbolic_operand (operands[2], Pmode))
2376 else if (symbolic_operand (operands[2], Pmode))
2377 return \"ldo RR'%G2(%1),%0\";
2379 return \"ldo R'%G2(%1),%0\";
2381 [(set_attr "type" "move")
2382 (set_attr "length" "4")])
2384 ;; Now that a symbolic_address plus a constant is broken up early
2385 ;; in the compilation phase (for better CSE) we need a special
2386 ;; combiner pattern to load the symbolic address plus the constant
2387 ;; in only 2 instructions. (For cases where the symbolic address
2388 ;; was not a common subexpression.)
2390 [(set (match_operand:SI 0 "register_operand" "")
2391 (match_operand:SI 1 "symbolic_operand" ""))
2392 (clobber (match_operand:SI 2 "register_operand" ""))]
2393 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2394 [(set (match_dup 2) (high:SI (match_dup 1)))
2395 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2398 ;; hppa_legitimize_address goes to a great deal of trouble to
2399 ;; create addresses which use indexing. In some cases, this
2400 ;; is a lose because there isn't any store instructions which
2401 ;; allow indexed addresses (with integer register source).
2403 ;; These define_splits try to turn a 3 insn store into
2404 ;; a 2 insn store with some creative RTL rewriting.
2406 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2407 (match_operand:SI 1 "shadd_operand" ""))
2408 (plus:SI (match_operand:SI 2 "register_operand" "")
2409 (match_operand:SI 3 "const_int_operand" ""))))
2410 (match_operand:SI 4 "register_operand" ""))
2411 (clobber (match_operand:SI 5 "register_operand" ""))]
2413 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2415 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2419 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2420 (match_operand:SI 1 "shadd_operand" ""))
2421 (plus:SI (match_operand:SI 2 "register_operand" "")
2422 (match_operand:SI 3 "const_int_operand" ""))))
2423 (match_operand:HI 4 "register_operand" ""))
2424 (clobber (match_operand:SI 5 "register_operand" ""))]
2426 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2428 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2432 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2433 (match_operand:SI 1 "shadd_operand" ""))
2434 (plus:SI (match_operand:SI 2 "register_operand" "")
2435 (match_operand:SI 3 "const_int_operand" ""))))
2436 (match_operand:QI 4 "register_operand" ""))
2437 (clobber (match_operand:SI 5 "register_operand" ""))]
2439 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2441 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2444 (define_expand "movhi"
2445 [(set (match_operand:HI 0 "general_operand" "")
2446 (match_operand:HI 1 "general_operand" ""))]
2450 if (emit_move_sequence (operands, HImode, 0))
2455 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2456 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2457 "register_operand (operands[0], HImode)
2458 || reg_or_0_operand (operands[1], HImode)"
2463 {zdepi|depwi,z} %Z1,%0
2468 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2469 (set_attr "pa_combine_type" "addmove")
2470 (set_attr "length" "4,4,4,4,4,4,4,4")])
2473 [(set (match_operand:HI 0 "register_operand" "=r")
2474 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2475 (match_operand:SI 2 "register_operand" "r"))))]
2476 "! TARGET_DISABLE_INDEXING"
2479 /* Reload can create backwards (relative to cse) unscaled index
2480 address modes when eliminating registers and possibly for
2481 pseudos that don't get hard registers. Deal with it. */
2482 if (operands[2] == hard_frame_pointer_rtx
2483 || operands[2] == stack_pointer_rtx)
2484 return \"{ldhx|ldh} %1(%2),%0\";
2486 return \"{ldhx|ldh} %2(%1),%0\";
2488 [(set_attr "type" "load")
2489 (set_attr "length" "4")])
2492 [(set (match_operand:HI 0 "register_operand" "=r")
2493 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2494 (match_operand:SI 2 "basereg_operand" "r"))))]
2495 "! TARGET_DISABLE_INDEXING"
2498 /* Reload can create backwards (relative to cse) unscaled index
2499 address modes when eliminating registers and possibly for
2500 pseudos that don't get hard registers. Deal with it. */
2501 if (operands[1] == hard_frame_pointer_rtx
2502 || operands[1] == stack_pointer_rtx)
2503 return \"{ldhx|ldh} %2(%1),%0\";
2505 return \"{ldhx|ldh} %1(%2),%0\";
2507 [(set_attr "type" "load")
2508 (set_attr "length" "4")])
2510 ; Now zero extended variants.
2512 [(set (match_operand:SI 0 "register_operand" "=r")
2513 (zero_extend:SI (mem:HI
2515 (match_operand:SI 1 "basereg_operand" "r")
2516 (match_operand:SI 2 "register_operand" "r")))))]
2517 "! TARGET_DISABLE_INDEXING"
2520 /* Reload can create backwards (relative to cse) unscaled index
2521 address modes when eliminating registers and possibly for
2522 pseudos that don't get hard registers. Deal with it. */
2523 if (operands[2] == hard_frame_pointer_rtx
2524 || operands[2] == stack_pointer_rtx)
2525 return \"{ldhx|ldh} %1(%2),%0\";
2527 return \"{ldhx|ldh} %2(%1),%0\";
2529 [(set_attr "type" "load")
2530 (set_attr "length" "4")])
2533 [(set (match_operand:SI 0 "register_operand" "=r")
2534 (zero_extend:SI (mem:HI
2536 (match_operand:SI 1 "register_operand" "r")
2537 (match_operand:SI 2 "basereg_operand" "r")))))]
2538 "! TARGET_DISABLE_INDEXING"
2541 /* Reload can create backwards (relative to cse) unscaled index
2542 address modes when eliminating registers and possibly for
2543 pseudos that don't get hard registers. Deal with it. */
2544 if (operands[1] == hard_frame_pointer_rtx
2545 || operands[1] == stack_pointer_rtx)
2546 return \"{ldhx|ldh} %2(%1),%0\";
2548 return \"{ldhx|ldh} %1(%2),%0\";
2550 [(set_attr "type" "load")
2551 (set_attr "length" "4")])
2554 [(set (match_operand:HI 0 "register_operand" "=r")
2555 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2556 (match_operand:SI 2 "int5_operand" "L"))))
2558 (plus:SI (match_dup 1) (match_dup 2)))]
2560 "{ldhs|ldh},mb %2(%1),%0"
2561 [(set_attr "type" "load")
2562 (set_attr "length" "4")])
2564 ; And a zero extended variant.
2566 [(set (match_operand:SI 0 "register_operand" "=r")
2567 (zero_extend:SI (mem:HI
2569 (match_operand:SI 1 "register_operand" "+r")
2570 (match_operand:SI 2 "int5_operand" "L")))))
2572 (plus:SI (match_dup 1) (match_dup 2)))]
2574 "{ldhs|ldh},mb %2(%1),%0"
2575 [(set_attr "type" "load")
2576 (set_attr "length" "4")])
2579 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2580 (match_operand:SI 1 "int5_operand" "L")))
2581 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2583 (plus:SI (match_dup 0) (match_dup 1)))]
2585 "{sths|sth},mb %r2,%1(%0)"
2586 [(set_attr "type" "store")
2587 (set_attr "length" "4")])
2590 [(set (match_operand:HI 0 "register_operand" "=r")
2591 (high:HI (match_operand 1 "const_int_operand" "")))]
2594 [(set_attr "type" "move")
2595 (set_attr "length" "4")])
2598 [(set (match_operand:HI 0 "register_operand" "=r")
2599 (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
2600 (match_operand 2 "const_int_operand" "")))]
2603 [(set_attr "type" "move")
2604 (set_attr "length" "4")])
2606 (define_expand "movqi"
2607 [(set (match_operand:QI 0 "general_operand" "")
2608 (match_operand:QI 1 "general_operand" ""))]
2612 if (emit_move_sequence (operands, QImode, 0))
2617 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2618 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2619 "register_operand (operands[0], QImode)
2620 || reg_or_0_operand (operands[1], QImode)"
2625 {zdepi|depwi,z} %Z1,%0
2630 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2631 (set_attr "pa_combine_type" "addmove")
2632 (set_attr "length" "4,4,4,4,4,4,4,4")])
2635 [(set (match_operand:QI 0 "register_operand" "=r")
2636 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2637 (match_operand:SI 2 "register_operand" "r"))))]
2638 "! TARGET_DISABLE_INDEXING"
2641 /* Reload can create backwards (relative to cse) unscaled index
2642 address modes when eliminating registers and possibly for
2643 pseudos that don't get hard registers. Deal with it. */
2644 if (operands[2] == hard_frame_pointer_rtx
2645 || operands[2] == stack_pointer_rtx)
2646 return \"{ldbx|ldb} %1(%2),%0\";
2648 return \"{ldbx|ldb} %2(%1),%0\";
2650 [(set_attr "type" "load")
2651 (set_attr "length" "4")])
2654 [(set (match_operand:QI 0 "register_operand" "=r")
2655 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2656 (match_operand:SI 2 "basereg_operand" "r"))))]
2657 "! TARGET_DISABLE_INDEXING"
2660 /* Reload can create backwards (relative to cse) unscaled index
2661 address modes when eliminating registers and possibly for
2662 pseudos that don't get hard registers. Deal with it. */
2663 if (operands[1] == hard_frame_pointer_rtx
2664 || operands[1] == stack_pointer_rtx)
2665 return \"{ldbx|ldb} %2(%1),%0\";
2667 return \"{ldbx|ldb} %1(%2),%0\";
2669 [(set_attr "type" "load")
2670 (set_attr "length" "4")])
2672 ; Indexed byte load with zero extension to SImode or HImode.
2674 [(set (match_operand:SI 0 "register_operand" "=r")
2675 (zero_extend:SI (mem:QI
2677 (match_operand:SI 1 "basereg_operand" "r")
2678 (match_operand:SI 2 "register_operand" "r")))))]
2679 "! TARGET_DISABLE_INDEXING"
2682 /* Reload can create backwards (relative to cse) unscaled index
2683 address modes when eliminating registers and possibly for
2684 pseudos that don't get hard registers. Deal with it. */
2685 if (operands[2] == hard_frame_pointer_rtx
2686 || operands[2] == stack_pointer_rtx)
2687 return \"{ldbx|ldb} %1(%2),%0\";
2689 return \"{ldbx|ldb} %2(%1),%0\";
2691 [(set_attr "type" "load")
2692 (set_attr "length" "4")])
2695 [(set (match_operand:SI 0 "register_operand" "=r")
2696 (zero_extend:SI (mem:QI
2698 (match_operand:SI 1 "register_operand" "r")
2699 (match_operand:SI 2 "basereg_operand" "r")))))]
2700 "! TARGET_DISABLE_INDEXING"
2703 /* Reload can create backwards (relative to cse) unscaled index
2704 address modes when eliminating registers and possibly for
2705 pseudos that don't get hard registers. Deal with it. */
2706 if (operands[1] == hard_frame_pointer_rtx
2707 || operands[1] == stack_pointer_rtx)
2708 return \"{ldbx|ldb} %2(%1),%0\";
2710 return \"{ldbx|ldb} %1(%2),%0\";
2712 [(set_attr "type" "load")
2713 (set_attr "length" "4")])
2716 [(set (match_operand:HI 0 "register_operand" "=r")
2717 (zero_extend:HI (mem:QI
2719 (match_operand:SI 1 "basereg_operand" "r")
2720 (match_operand:SI 2 "register_operand" "r")))))]
2721 "! TARGET_DISABLE_INDEXING"
2724 /* Reload can create backwards (relative to cse) unscaled index
2725 address modes when eliminating registers and possibly for
2726 pseudos that don't get hard registers. Deal with it. */
2727 if (operands[2] == hard_frame_pointer_rtx
2728 || operands[2] == stack_pointer_rtx)
2729 return \"{ldbx|ldb} %1(%2),%0\";
2731 return \"{ldbx|ldb} %2(%1),%0\";
2733 [(set_attr "type" "load")
2734 (set_attr "length" "4")])
2737 [(set (match_operand:HI 0 "register_operand" "=r")
2738 (zero_extend:HI (mem:QI
2740 (match_operand:SI 1 "register_operand" "r")
2741 (match_operand:SI 2 "basereg_operand" "r")))))]
2742 "! TARGET_DISABLE_INDEXING"
2745 /* Reload can create backwards (relative to cse) unscaled index
2746 address modes when eliminating registers and possibly for
2747 pseudos that don't get hard registers. Deal with it. */
2748 if (operands[1] == hard_frame_pointer_rtx
2749 || operands[1] == stack_pointer_rtx)
2750 return \"{ldbx|ldb} %2(%1),%0\";
2752 return \"{ldbx|ldb} %1(%2),%0\";
2754 [(set_attr "type" "load")
2755 (set_attr "length" "4")])
2758 [(set (match_operand:QI 0 "register_operand" "=r")
2759 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2760 (match_operand:SI 2 "int5_operand" "L"))))
2761 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2763 "{ldbs|ldb},mb %2(%1),%0"
2764 [(set_attr "type" "load")
2765 (set_attr "length" "4")])
2767 ; Now the same thing with zero extensions.
2769 [(set (match_operand:SI 0 "register_operand" "=r")
2770 (zero_extend:SI (mem:QI (plus:SI
2771 (match_operand:SI 1 "register_operand" "+r")
2772 (match_operand:SI 2 "int5_operand" "L")))))
2773 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2775 "{ldbs|ldb},mb %2(%1),%0"
2776 [(set_attr "type" "load")
2777 (set_attr "length" "4")])
2780 [(set (match_operand:HI 0 "register_operand" "=r")
2781 (zero_extend:HI (mem:QI (plus:SI
2782 (match_operand:SI 1 "register_operand" "+r")
2783 (match_operand:SI 2 "int5_operand" "L")))))
2784 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2786 "{ldbs|ldb},mb %2(%1),%0"
2787 [(set_attr "type" "load")
2788 (set_attr "length" "4")])
2791 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2792 (match_operand:SI 1 "int5_operand" "L")))
2793 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2795 (plus:SI (match_dup 0) (match_dup 1)))]
2797 "{stbs|stb},mb %r2,%1(%0)"
2798 [(set_attr "type" "store")
2799 (set_attr "length" "4")])
2801 ;; The definition of this insn does not really explain what it does,
2802 ;; but it should suffice
2803 ;; that anything generated as this insn will be recognized as one
2804 ;; and that it will not successfully combine with anything.
2805 (define_expand "movstrsi"
2806 [(parallel [(set (match_operand:BLK 0 "" "")
2807 (match_operand:BLK 1 "" ""))
2808 (clobber (match_dup 7))
2809 (clobber (match_dup 8))
2810 (clobber (match_dup 4))
2811 (clobber (match_dup 5))
2812 (clobber (match_dup 6))
2813 (use (match_operand:SI 2 "arith_operand" ""))
2814 (use (match_operand:SI 3 "const_int_operand" ""))])]
2820 /* HP provides very fast block move library routine for the PA;
2821 this routine includes:
2823 4x4 byte at a time block moves,
2824 1x4 byte at a time with alignment checked at runtime with
2825 attempts to align the source and destination as needed
2828 With that in mind, here's the heuristics to try and guess when
2829 the inlined block move will be better than the library block
2832 If the size isn't constant, then always use the library routines.
2834 If the size is large in respect to the known alignment, then use
2835 the library routines.
2837 If the size is small in repsect to the known alignment, then open
2838 code the copy (since that will lead to better scheduling).
2840 Else use the block move pattern. */
2842 /* Undetermined size, use the library routine. */
2843 if (GET_CODE (operands[2]) != CONST_INT)
2846 size = INTVAL (operands[2]);
2847 align = INTVAL (operands[3]);
2848 align = align > 4 ? 4 : align;
2850 /* If size/alignment > 8 (eg size is large in respect to alignment),
2851 then use the library routines. */
2852 if (size / align > 16)
2855 /* This does happen, but not often enough to worry much about. */
2856 if (size / align < MOVE_RATIO)
2859 /* Fall through means we're going to use our block move pattern. */
2861 = change_address (operands[0], VOIDmode,
2862 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2864 = change_address (operands[1], VOIDmode,
2865 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2866 operands[4] = gen_reg_rtx (SImode);
2867 operands[5] = gen_reg_rtx (SImode);
2868 operands[6] = gen_reg_rtx (SImode);
2869 operands[7] = XEXP (operands[0], 0);
2870 operands[8] = XEXP (operands[1], 0);
2873 ;; The operand constraints are written like this to support both compile-time
2874 ;; and run-time determined byte count. If the count is run-time determined,
2875 ;; the register with the byte count is clobbered by the copying code, and
2876 ;; therefore it is forced to operand 2. If the count is compile-time
2877 ;; determined, we need two scratch registers for the unrolled code.
2878 (define_insn "movstrsi_internal"
2879 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
2880 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
2881 (clobber (match_dup 0))
2882 (clobber (match_dup 1))
2883 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
2884 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
2885 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
2886 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
2887 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
2889 "* return output_block_move (operands, !which_alternative);"
2890 [(set_attr "type" "multi,multi")])
2892 ;; Floating point move insns
2894 ;; This pattern forces (set (reg:DF ...) (const_double ...))
2895 ;; to be reloaded by putting the constant into memory when
2896 ;; reg is a floating point register.
2898 ;; For integer registers we use ldil;ldo to set the appropriate
2901 ;; This must come before the movdf pattern, and it must be present
2902 ;; to handle obscure reloading cases.
2904 [(set (match_operand:DF 0 "register_operand" "=?r,f")
2905 (match_operand:DF 1 "" "?F,m"))]
2906 "GET_CODE (operands[1]) == CONST_DOUBLE
2907 && operands[1] != CONST0_RTX (DFmode)
2909 && ! TARGET_SOFT_FLOAT"
2910 "* return (which_alternative == 0 ? output_move_double (operands)
2911 : \"fldd%F1 %1,%0\");"
2912 [(set_attr "type" "move,fpload")
2913 (set_attr "length" "16,4")])
2915 (define_expand "movdf"
2916 [(set (match_operand:DF 0 "general_operand" "")
2917 (match_operand:DF 1 "general_operand" ""))]
2921 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
2922 operands[1] = force_const_mem (DFmode, operands[1]);
2924 if (emit_move_sequence (operands, DFmode, 0))
2928 ;; Reloading an SImode or DImode value requires a scratch register if
2929 ;; going in to or out of float point registers.
2931 (define_expand "reload_indf"
2932 [(set (match_operand:DF 0 "register_operand" "=Z")
2933 (match_operand:DF 1 "non_hard_reg_operand" ""))
2934 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2938 if (emit_move_sequence (operands, DFmode, operands[2]))
2941 /* We don't want the clobber emitted, so handle this ourselves. */
2942 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2946 (define_expand "reload_outdf"
2947 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
2948 (match_operand:DF 1 "register_operand" "Z"))
2949 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2953 if (emit_move_sequence (operands, DFmode, operands[2]))
2956 /* We don't want the clobber emitted, so handle this ourselves. */
2957 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2962 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2963 "=f,*r,RQ,?o,?Q,f,*r,*r")
2964 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2965 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
2966 "(register_operand (operands[0], DFmode)
2967 || reg_or_0_operand (operands[1], DFmode))
2968 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
2969 && GET_CODE (operands[0]) == MEM)
2971 && ! TARGET_SOFT_FLOAT"
2974 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
2975 || operands[1] == CONST0_RTX (DFmode))
2976 return output_fp_move_double (operands);
2977 return output_move_double (operands);
2979 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
2980 (set_attr "length" "4,8,4,8,16,4,8,16")])
2983 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2985 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2987 "(register_operand (operands[0], DFmode)
2988 || reg_or_0_operand (operands[1], DFmode))
2990 && TARGET_SOFT_FLOAT"
2993 return output_move_double (operands);
2995 [(set_attr "type" "move,store,store,load,load")
2996 (set_attr "length" "8,8,16,8,16")])
2999 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3000 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3001 (match_operand:DF 1 "move_operand"
3002 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3003 "(register_operand (operands[0], DFmode)
3004 || reg_or_0_operand (operands[1], DFmode))
3005 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3017 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3018 (set_attr "pa_combine_type" "addmove")
3019 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3022 [(set (match_operand:DF 0 "register_operand" "=fx")
3023 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3024 (match_operand:SI 2 "register_operand" "r"))))]
3025 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3028 /* Reload can create backwards (relative to cse) unscaled index
3029 address modes when eliminating registers and possibly for
3030 pseudos that don't get hard registers. Deal with it. */
3031 if (operands[2] == hard_frame_pointer_rtx
3032 || operands[2] == stack_pointer_rtx)
3033 return \"{flddx|fldd} %1(%2),%0\";
3035 return \"{flddx|fldd} %2(%1),%0\";
3037 [(set_attr "type" "fpload")
3038 (set_attr "length" "4")])
3041 [(set (match_operand:DF 0 "register_operand" "=fx")
3042 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3043 (match_operand:SI 2 "basereg_operand" "r"))))]
3044 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3047 /* Reload can create backwards (relative to cse) unscaled index
3048 address modes when eliminating registers and possibly for
3049 pseudos that don't get hard registers. Deal with it. */
3050 if (operands[1] == hard_frame_pointer_rtx
3051 || operands[1] == stack_pointer_rtx)
3052 return \"{flddx|fldd} %2(%1),%0\";
3054 return \"{flddx|fldd} %1(%2),%0\";
3056 [(set_attr "type" "fpload")
3057 (set_attr "length" "4")])
3060 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3061 (match_operand:SI 2 "register_operand" "r")))
3062 (match_operand:DF 0 "register_operand" "fx"))]
3063 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3066 /* Reload can create backwards (relative to cse) unscaled index
3067 address modes when eliminating registers and possibly for
3068 pseudos that don't get hard registers. Deal with it. */
3069 if (operands[2] == hard_frame_pointer_rtx
3070 || operands[2] == stack_pointer_rtx)
3071 return \"{fstdx|fstd} %0,%1(%2)\";
3073 return \"{fstdx|fstd} %0,%2(%1)\";
3075 [(set_attr "type" "fpstore")
3076 (set_attr "length" "4")])
3079 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3080 (match_operand:SI 2 "basereg_operand" "r")))
3081 (match_operand:DF 0 "register_operand" "fx"))]
3082 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3085 /* Reload can create backwards (relative to cse) unscaled index
3086 address modes when eliminating registers and possibly for
3087 pseudos that don't get hard registers. Deal with it. */
3088 if (operands[1] == hard_frame_pointer_rtx
3089 || operands[1] == stack_pointer_rtx)
3090 return \"{fstdx|fstd} %0,%2(%1)\";
3092 return \"{fstdx|fstd} %0,%1(%2)\";
3094 [(set_attr "type" "fpstore")
3095 (set_attr "length" "4")])
3097 (define_expand "movdi"
3098 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
3099 (match_operand:DI 1 "general_operand" ""))]
3103 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3104 operands[1] = force_const_mem (DImode, operands[1]);
3106 if (emit_move_sequence (operands, DImode, 0))
3110 (define_expand "reload_indi"
3111 [(set (match_operand:DI 0 "register_operand" "=Z")
3112 (match_operand:DI 1 "non_hard_reg_operand" ""))
3113 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3117 if (emit_move_sequence (operands, DImode, operands[2]))
3120 /* We don't want the clobber emitted, so handle this ourselves. */
3121 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3125 (define_expand "reload_outdi"
3126 [(set (match_operand:DI 0 "general_operand" "")
3127 (match_operand:DI 1 "register_operand" "Z"))
3128 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3132 if (emit_move_sequence (operands, DImode, operands[2]))
3135 /* We don't want the clobber emitted, so handle this ourselves. */
3136 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3141 [(set (match_operand:DI 0 "register_operand" "=r")
3142 (high:DI (match_operand 1 "" "")))]
3146 rtx op0 = operands[0];
3147 rtx op1 = operands[1];
3149 if (GET_CODE (op1) == CONST_INT)
3151 operands[0] = operand_subword (op0, 1, 0, DImode);
3152 output_asm_insn (\"ldil L'%1,%0\", operands);
3154 operands[0] = operand_subword (op0, 0, 0, DImode);
3155 if (INTVAL (op1) < 0)
3156 output_asm_insn (\"ldi -1,%0\", operands);
3158 output_asm_insn (\"ldi 0,%0\", operands);
3161 else if (GET_CODE (op1) == CONST_DOUBLE)
3163 operands[0] = operand_subword (op0, 1, 0, DImode);
3164 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3165 output_asm_insn (\"ldil L'%1,%0\", operands);
3167 operands[0] = operand_subword (op0, 0, 0, DImode);
3168 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3169 output_asm_insn (singlemove_string (operands), operands);
3175 [(set_attr "type" "move")
3176 (set_attr "length" "8")])
3179 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3180 "=r,o,Q,r,r,r,f,f,*TR")
3181 (match_operand:DI 1 "general_operand"
3182 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3183 "(register_operand (operands[0], DImode)
3184 || reg_or_0_operand (operands[1], DImode))
3186 && ! TARGET_SOFT_FLOAT"
3189 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3190 || (operands[1] == CONST0_RTX (DImode)))
3191 return output_fp_move_double (operands);
3192 return output_move_double (operands);
3194 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3195 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3198 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3199 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3200 (match_operand:DI 1 "move_operand"
3201 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3202 "(register_operand (operands[0], DImode)
3203 || reg_or_0_operand (operands[1], DImode))
3204 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3216 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3217 (set_attr "pa_combine_type" "addmove")
3218 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3221 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3223 (match_operand:DI 1 "general_operand"
3225 "(register_operand (operands[0], DImode)
3226 || reg_or_0_operand (operands[1], DImode))
3228 && TARGET_SOFT_FLOAT"
3231 return output_move_double (operands);
3233 [(set_attr "type" "move,store,store,load,load,multi")
3234 (set_attr "length" "8,8,16,8,16,16")])
3237 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3238 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3239 (match_operand:DI 2 "immediate_operand" "i,i")))]
3243 /* Don't output a 64 bit constant, since we can't trust the assembler to
3244 handle it correctly. */
3245 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3246 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3247 if (which_alternative == 1)
3248 output_asm_insn (\"copy %1,%0\", operands);
3249 return \"ldo R'%G2(%R1),%R0\";
3251 [(set_attr "type" "move,move")
3252 (set_attr "length" "4,8")])
3254 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3255 ;; to be reloaded by putting the constant into memory when
3256 ;; reg is a floating point register.
3258 ;; For integer registers we use ldil;ldo to set the appropriate
3261 ;; This must come before the movsf pattern, and it must be present
3262 ;; to handle obscure reloading cases.
3264 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3265 (match_operand:SF 1 "" "?F,m"))]
3266 "GET_CODE (operands[1]) == CONST_DOUBLE
3267 && operands[1] != CONST0_RTX (SFmode)
3268 && ! TARGET_SOFT_FLOAT"
3269 "* return (which_alternative == 0 ? singlemove_string (operands)
3270 : \" fldw%F1 %1,%0\");"
3271 [(set_attr "type" "move,fpload")
3272 (set_attr "length" "8,4")])
3274 (define_expand "movsf"
3275 [(set (match_operand:SF 0 "general_operand" "")
3276 (match_operand:SF 1 "general_operand" ""))]
3280 if (emit_move_sequence (operands, SFmode, 0))
3284 ;; Reloading an SImode or DImode value requires a scratch register if
3285 ;; going in to or out of float point registers.
3287 (define_expand "reload_insf"
3288 [(set (match_operand:SF 0 "register_operand" "=Z")
3289 (match_operand:SF 1 "non_hard_reg_operand" ""))
3290 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3294 if (emit_move_sequence (operands, SFmode, operands[2]))
3297 /* We don't want the clobber emitted, so handle this ourselves. */
3298 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3302 (define_expand "reload_outsf"
3303 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3304 (match_operand:SF 1 "register_operand" "Z"))
3305 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3309 if (emit_move_sequence (operands, SFmode, operands[2]))
3312 /* We don't want the clobber emitted, so handle this ourselves. */
3313 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3318 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3320 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3321 "fG,rG,RQ,RQ,f,rG"))]
3322 "(register_operand (operands[0], SFmode)
3323 || reg_or_0_operand (operands[1], SFmode))
3324 && ! TARGET_SOFT_FLOAT"
3332 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3333 (set_attr "pa_combine_type" "addmove")
3334 (set_attr "length" "4,4,4,4,4,4")])
3337 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3339 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3341 "(register_operand (operands[0], SFmode)
3342 || reg_or_0_operand (operands[1], SFmode))
3343 && TARGET_SOFT_FLOAT"
3348 [(set_attr "type" "move,load,store")
3349 (set_attr "pa_combine_type" "addmove")
3350 (set_attr "length" "4,4,4")])
3353 [(set (match_operand:SF 0 "register_operand" "=fx")
3354 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3355 (match_operand:SI 2 "register_operand" "r"))))]
3356 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3359 /* Reload can create backwards (relative to cse) unscaled index
3360 address modes when eliminating registers and possibly for
3361 pseudos that don't get hard registers. Deal with it. */
3362 if (operands[2] == hard_frame_pointer_rtx
3363 || operands[2] == stack_pointer_rtx)
3364 return \"{fldwx|fldw} %1(%2),%0\";
3366 return \"{fldwx|fldw} %2(%1),%0\";
3368 [(set_attr "type" "fpload")
3369 (set_attr "length" "4")])
3372 [(set (match_operand:SF 0 "register_operand" "=fx")
3373 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3374 (match_operand:SI 2 "basereg_operand" "r"))))]
3375 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3378 /* Reload can create backwards (relative to cse) unscaled index
3379 address modes when eliminating registers and possibly for
3380 pseudos that don't get hard registers. Deal with it. */
3381 if (operands[1] == hard_frame_pointer_rtx
3382 || operands[1] == stack_pointer_rtx)
3383 return \"{fldwx|fldw} %2(%1),%0\";
3385 return \"{fldwx|fldw} %1(%2),%0\";
3387 [(set_attr "type" "fpload")
3388 (set_attr "length" "4")])
3391 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3392 (match_operand:SI 2 "register_operand" "r")))
3393 (match_operand:SF 0 "register_operand" "fx"))]
3394 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3397 /* Reload can create backwards (relative to cse) unscaled index
3398 address modes when eliminating registers and possibly for
3399 pseudos that don't get hard registers. Deal with it. */
3400 if (operands[2] == hard_frame_pointer_rtx
3401 || operands[2] == stack_pointer_rtx)
3402 return \"{fstwx|fstw} %0,%1(%2)\";
3404 return \"{fstwx|fstw} %0,%2(%1)\";
3406 [(set_attr "type" "fpstore")
3407 (set_attr "length" "4")])
3410 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3411 (match_operand:SI 2 "basereg_operand" "r")))
3412 (match_operand:SF 0 "register_operand" "fx"))]
3413 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3416 /* Reload can create backwards (relative to cse) unscaled index
3417 address modes when eliminating registers and possibly for
3418 pseudos that don't get hard registers. Deal with it. */
3419 if (operands[1] == hard_frame_pointer_rtx
3420 || operands[1] == stack_pointer_rtx)
3421 return \"{fstwx|fstw} %0,%2(%1)\";
3423 return \"{fstwx|fstw} %0,%1(%2)\";
3425 [(set_attr "type" "fpstore")
3426 (set_attr "length" "4")])
3429 ;;- zero extension instructions
3430 ;; We have define_expand for zero extension patterns to make sure the
3431 ;; operands get loaded into registers. The define_insns accept
3432 ;; memory operands. This gives us better overall code than just
3433 ;; having a pattern that does or does not accept memory operands.
3435 (define_expand "zero_extendhisi2"
3436 [(set (match_operand:SI 0 "register_operand" "")
3438 (match_operand:HI 1 "register_operand" "")))]
3443 [(set (match_operand:SI 0 "register_operand" "=r,r")
3445 (match_operand:HI 1 "move_operand" "r,RQ")))]
3446 "GET_CODE (operands[1]) != CONST_INT"
3448 {extru|extrw,u} %1,31,16,%0
3450 [(set_attr "type" "shift,load")
3451 (set_attr "length" "4,4")])
3453 (define_expand "zero_extendqihi2"
3454 [(set (match_operand:HI 0 "register_operand" "")
3456 (match_operand:QI 1 "register_operand" "")))]
3461 [(set (match_operand:HI 0 "register_operand" "=r,r")
3463 (match_operand:QI 1 "move_operand" "r,RQ")))]
3464 "GET_CODE (operands[1]) != CONST_INT"
3466 {extru|extrw,u} %1,31,8,%0
3468 [(set_attr "type" "shift,load")
3469 (set_attr "length" "4,4")])
3471 (define_expand "zero_extendqisi2"
3472 [(set (match_operand:SI 0 "register_operand" "")
3474 (match_operand:QI 1 "register_operand" "")))]
3479 [(set (match_operand:SI 0 "register_operand" "=r,r")
3481 (match_operand:QI 1 "move_operand" "r,RQ")))]
3482 "GET_CODE (operands[1]) != CONST_INT"
3484 {extru|extrw,u} %1,31,8,%0
3486 [(set_attr "type" "shift,load")
3487 (set_attr "length" "4,4")])
3489 (define_insn "zero_extendqidi2"
3490 [(set (match_operand:DI 0 "register_operand" "=r")
3491 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3493 "extrd,u %1,63,8,%0"
3494 [(set_attr "type" "shift")
3495 (set_attr "length" "4")])
3497 (define_insn "zero_extendhidi2"
3498 [(set (match_operand:DI 0 "register_operand" "=r")
3499 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3501 "extrd,u %1,63,16,%0"
3502 [(set_attr "type" "shift")
3503 (set_attr "length" "4")])
3505 (define_insn "zero_extendsidi2"
3506 [(set (match_operand:DI 0 "register_operand" "=r")
3507 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3509 "extrd,u %1,63,32,%0"
3510 [(set_attr "type" "shift")
3511 (set_attr "length" "4")])
3513 ;;- sign extension instructions
3515 (define_insn "extendhisi2"
3516 [(set (match_operand:SI 0 "register_operand" "=r")
3517 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3519 "{extrs|extrw,s} %1,31,16,%0"
3520 [(set_attr "type" "shift")
3521 (set_attr "length" "4")])
3523 (define_insn "extendqihi2"
3524 [(set (match_operand:HI 0 "register_operand" "=r")
3525 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3527 "{extrs|extrw,s} %1,31,8,%0"
3528 [(set_attr "type" "shift")
3529 (set_attr "length" "4")])
3531 (define_insn "extendqisi2"
3532 [(set (match_operand:SI 0 "register_operand" "=r")
3533 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3535 "{extrs|extrw,s} %1,31,8,%0"
3536 [(set_attr "type" "shift")
3537 (set_attr "length" "4")])
3539 (define_insn "extendqidi2"
3540 [(set (match_operand:DI 0 "register_operand" "=r")
3541 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3543 "extrd,s %1,63,8,%0"
3544 [(set_attr "type" "shift")
3545 (set_attr "length" "4")])
3547 (define_insn "extendhidi2"
3548 [(set (match_operand:DI 0 "register_operand" "=r")
3549 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3551 "extrd,s %1,63,16,%0"
3552 [(set_attr "type" "shift")
3553 (set_attr "length" "4")])
3555 (define_insn "extendsidi2"
3556 [(set (match_operand:DI 0 "register_operand" "=r")
3557 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3559 "extrd,s %1,63,32,%0"
3560 [(set_attr "type" "shift")
3561 (set_attr "length" "4")])
3564 ;; Conversions between float and double.
3566 (define_insn "extendsfdf2"
3567 [(set (match_operand:DF 0 "register_operand" "=f")
3569 (match_operand:SF 1 "register_operand" "f")))]
3570 "! TARGET_SOFT_FLOAT"
3571 "{fcnvff|fcnv},sgl,dbl %1,%0"
3572 [(set_attr "type" "fpalu")
3573 (set_attr "length" "4")])
3575 (define_insn "truncdfsf2"
3576 [(set (match_operand:SF 0 "register_operand" "=f")
3578 (match_operand:DF 1 "register_operand" "f")))]
3579 "! TARGET_SOFT_FLOAT"
3580 "{fcnvff|fcnv},dbl,sgl %1,%0"
3581 [(set_attr "type" "fpalu")
3582 (set_attr "length" "4")])
3584 ;; Conversion between fixed point and floating point.
3585 ;; Note that among the fix-to-float insns
3586 ;; the ones that start with SImode come first.
3587 ;; That is so that an operand that is a CONST_INT
3588 ;; (and therefore lacks a specific machine mode).
3589 ;; will be recognized as SImode (which is always valid)
3590 ;; rather than as QImode or HImode.
3592 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3593 ;; to be reloaded by putting the constant into memory.
3594 ;; It must come before the more general floatsisf2 pattern.
3596 [(set (match_operand:SF 0 "register_operand" "=f")
3597 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3598 "! TARGET_SOFT_FLOAT"
3599 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3600 [(set_attr "type" "fpalu")
3601 (set_attr "length" "8")])
3603 (define_insn "floatsisf2"
3604 [(set (match_operand:SF 0 "register_operand" "=f")
3605 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3606 "! TARGET_SOFT_FLOAT"
3607 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3608 [(set_attr "type" "fpalu")
3609 (set_attr "length" "4")])
3611 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3612 ;; to be reloaded by putting the constant into memory.
3613 ;; It must come before the more general floatsidf2 pattern.
3615 [(set (match_operand:DF 0 "register_operand" "=f")
3616 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3617 "! TARGET_SOFT_FLOAT"
3618 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3619 [(set_attr "type" "fpalu")
3620 (set_attr "length" "8")])
3622 (define_insn "floatsidf2"
3623 [(set (match_operand:DF 0 "register_operand" "=f")
3624 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3625 "! TARGET_SOFT_FLOAT"
3626 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3627 [(set_attr "type" "fpalu")
3628 (set_attr "length" "4")])
3630 (define_expand "floatunssisf2"
3631 [(set (subreg:SI (match_dup 2) 1)
3632 (match_operand:SI 1 "register_operand" ""))
3633 (set (subreg:SI (match_dup 2) 0)
3635 (set (match_operand:SF 0 "register_operand" "")
3636 (float:SF (match_dup 2)))]
3637 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3642 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3645 operands[2] = gen_reg_rtx (DImode);
3648 (define_expand "floatunssidf2"
3649 [(set (subreg:SI (match_dup 2) 1)
3650 (match_operand:SI 1 "register_operand" ""))
3651 (set (subreg:SI (match_dup 2) 0)
3653 (set (match_operand:DF 0 "register_operand" "")
3654 (float:DF (match_dup 2)))]
3655 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3660 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3663 operands[2] = gen_reg_rtx (DImode);
3666 (define_insn "floatdisf2"
3667 [(set (match_operand:SF 0 "register_operand" "=f")
3668 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3669 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3670 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3671 [(set_attr "type" "fpalu")
3672 (set_attr "length" "4")])
3674 (define_insn "floatdidf2"
3675 [(set (match_operand:DF 0 "register_operand" "=f")
3676 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3677 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3678 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3679 [(set_attr "type" "fpalu")
3680 (set_attr "length" "4")])
3682 ;; Convert a float to an actual integer.
3683 ;; Truncation is performed as part of the conversion.
3685 (define_insn "fix_truncsfsi2"
3686 [(set (match_operand:SI 0 "register_operand" "=f")
3687 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3688 "! TARGET_SOFT_FLOAT"
3689 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3690 [(set_attr "type" "fpalu")
3691 (set_attr "length" "4")])
3693 (define_insn "fix_truncdfsi2"
3694 [(set (match_operand:SI 0 "register_operand" "=f")
3695 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3696 "! TARGET_SOFT_FLOAT"
3697 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3698 [(set_attr "type" "fpalu")
3699 (set_attr "length" "4")])
3701 (define_insn "fix_truncsfdi2"
3702 [(set (match_operand:DI 0 "register_operand" "=f")
3703 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3704 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3705 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3706 [(set_attr "type" "fpalu")
3707 (set_attr "length" "4")])
3709 (define_insn "fix_truncdfdi2"
3710 [(set (match_operand:DI 0 "register_operand" "=f")
3711 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3712 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3713 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3714 [(set_attr "type" "fpalu")
3715 (set_attr "length" "4")])
3717 (define_insn "floatunssidf2_pa20"
3718 [(set (match_operand:DF 0 "register_operand" "=f")
3719 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3720 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3722 [(set_attr "type" "fpalu")
3723 (set_attr "length" "4")])
3725 (define_insn "floatunssisf2_pa20"
3726 [(set (match_operand:SF 0 "register_operand" "=f")
3727 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3728 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3730 [(set_attr "type" "fpalu")
3731 (set_attr "length" "4")])
3733 (define_insn "floatunsdisf2"
3734 [(set (match_operand:SF 0 "register_operand" "=f")
3735 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3736 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3737 "fcnv,udw,sgl %1,%0"
3738 [(set_attr "type" "fpalu")
3739 (set_attr "length" "4")])
3741 (define_insn "floatunsdidf2"
3742 [(set (match_operand:DF 0 "register_operand" "=f")
3743 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3744 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3745 "fcnv,udw,dbl %1,%0"
3746 [(set_attr "type" "fpalu")
3747 (set_attr "length" "4")])
3749 (define_insn "fixuns_truncsfsi2"
3750 [(set (match_operand:SI 0 "register_operand" "=f")
3751 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3752 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3753 "fcnv,t,sgl,uw %1,%0"
3754 [(set_attr "type" "fpalu")
3755 (set_attr "length" "4")])
3757 (define_insn "fixuns_truncdfsi2"
3758 [(set (match_operand:SI 0 "register_operand" "=f")
3759 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3760 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3761 "fcnv,t,dbl,uw %1,%0"
3762 [(set_attr "type" "fpalu")
3763 (set_attr "length" "4")])
3765 (define_insn "fixuns_truncsfdi2"
3766 [(set (match_operand:DI 0 "register_operand" "=f")
3767 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3768 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3769 "fcnv,t,sgl,udw %1,%0"
3770 [(set_attr "type" "fpalu")
3771 (set_attr "length" "4")])
3773 (define_insn "fixuns_truncdfdi2"
3774 [(set (match_operand:DI 0 "register_operand" "=f")
3775 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3776 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3777 "fcnv,t,dbl,udw %1,%0"
3778 [(set_attr "type" "fpalu")
3779 (set_attr "length" "4")])
3781 ;;- arithmetic instructions
3783 (define_expand "adddi3"
3784 [(set (match_operand:DI 0 "register_operand" "")
3785 (plus:DI (match_operand:DI 1 "register_operand" "")
3786 (match_operand:DI 2 "arith_operand" "")))]
3790 ;; We allow arith_operand for operands2, even though strictly speaking it
3791 ;; we would prefer to us arith11_operand since that's what the hardware
3792 ;; can actually support.
3794 ;; But the price of the extra reload in that case is worth the simplicity
3795 ;; we get by allowing a trivial adddi3 expander to be used for both
3799 [(set (match_operand:DI 0 "register_operand" "=r")
3800 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3801 (match_operand:DI 2 "arith_operand" "rI")))]
3805 if (GET_CODE (operands[2]) == CONST_INT)
3807 if (INTVAL (operands[2]) >= 0)
3808 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3810 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3813 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3815 [(set_attr "type" "binary")
3816 (set_attr "length" "8")])
3819 [(set (match_operand:DI 0 "register_operand" "=r,r")
3820 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3821 (match_operand:DI 2 "arith_operand" "r,J")))]
3824 {addl|add,l} %1,%2,%0
3826 [(set_attr "type" "binary,binary")
3827 (set_attr "pa_combine_type" "addmove")
3828 (set_attr "length" "4,4")])
3831 [(set (match_operand:DI 0 "register_operand" "=r")
3832 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3833 (match_operand:DI 2 "register_operand" "r")))]
3836 [(set_attr "type" "binary")
3837 (set_attr "length" "4")])
3840 [(set (match_operand:SI 0 "register_operand" "=r")
3841 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3842 (match_operand:SI 2 "register_operand" "r")))]
3845 [(set_attr "type" "binary")
3846 (set_attr "length" "4")])
3848 ;; define_splits to optimize cases of adding a constant integer
3849 ;; to a register when the constant does not fit in 14 bits. */
3851 [(set (match_operand:SI 0 "register_operand" "")
3852 (plus:SI (match_operand:SI 1 "register_operand" "")
3853 (match_operand:SI 2 "const_int_operand" "")))
3854 (clobber (match_operand:SI 4 "register_operand" ""))]
3855 "! cint_ok_for_move (INTVAL (operands[2]))
3856 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3857 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3858 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3861 int val = INTVAL (operands[2]);
3862 int low = (val < 0) ? -0x2000 : 0x1fff;
3863 int rest = val - low;
3865 operands[2] = GEN_INT (rest);
3866 operands[3] = GEN_INT (low);
3870 [(set (match_operand:SI 0 "register_operand" "")
3871 (plus:SI (match_operand:SI 1 "register_operand" "")
3872 (match_operand:SI 2 "const_int_operand" "")))
3873 (clobber (match_operand:SI 4 "register_operand" ""))]
3874 "! cint_ok_for_move (INTVAL (operands[2]))"
3875 [(set (match_dup 4) (match_dup 2))
3876 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3880 HOST_WIDE_INT intval = INTVAL (operands[2]);
3882 /* Try dividing the constant by 2, then 4, and finally 8 to see
3883 if we can get a constant which can be loaded into a register
3884 in a single instruction (cint_ok_for_move).
3886 If that fails, try to negate the constant and subtract it
3887 from our input operand. */
3888 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3890 operands[2] = GEN_INT (intval / 2);
3891 operands[3] = GEN_INT (2);
3893 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3895 operands[2] = GEN_INT (intval / 4);
3896 operands[3] = GEN_INT (4);
3898 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3900 operands[2] = GEN_INT (intval / 8);
3901 operands[3] = GEN_INT (8);
3903 else if (cint_ok_for_move (-intval))
3905 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3906 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3913 (define_insn "addsi3"
3914 [(set (match_operand:SI 0 "register_operand" "=r,r")
3915 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3916 (match_operand:SI 2 "arith_operand" "r,J")))]
3919 {addl|add,l} %1,%2,%0
3921 [(set_attr "type" "binary,binary")
3922 (set_attr "pa_combine_type" "addmove")
3923 (set_attr "length" "4,4")])
3925 (define_expand "subdi3"
3926 [(set (match_operand:DI 0 "register_operand" "")
3927 (minus:DI (match_operand:DI 1 "register_operand" "")
3928 (match_operand:DI 2 "register_operand" "")))]
3933 [(set (match_operand:DI 0 "register_operand" "=r")
3934 (minus:DI (match_operand:DI 1 "register_operand" "r")
3935 (match_operand:DI 2 "register_operand" "r")))]
3937 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3938 [(set_attr "type" "binary")
3939 (set_attr "length" "8")])
3942 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3943 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3944 (match_operand:DI 2 "register_operand" "r,r,r")))]
3950 [(set_attr "type" "binary,binary,move")
3951 (set_attr "length" "4,4,4")])
3953 (define_expand "subsi3"
3954 [(set (match_operand:SI 0 "register_operand" "")
3955 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3956 (match_operand:SI 2 "register_operand" "")))]
3961 [(set (match_operand:SI 0 "register_operand" "=r,r")
3962 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
3963 (match_operand:SI 2 "register_operand" "r,r")))]
3968 [(set_attr "type" "binary,binary")
3969 (set_attr "length" "4,4")])
3972 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
3973 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
3974 (match_operand:SI 2 "register_operand" "r,r,r")))]
3980 [(set_attr "type" "binary,binary,move")
3981 (set_attr "length" "4,4,4")])
3983 ;; Clobbering a "register_operand" instead of a match_scratch
3984 ;; in operand3 of millicode calls avoids spilling %r1 and
3985 ;; produces better code.
3987 ;; The mulsi3 insns set up registers for the millicode call.
3988 (define_expand "mulsi3"
3989 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3990 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3991 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3992 (clobber (match_dup 3))
3993 (clobber (reg:SI 26))
3994 (clobber (reg:SI 25))
3995 (clobber (reg:SI 31))])
3996 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4000 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
4002 rtx scratch = gen_reg_rtx (DImode);
4003 operands[1] = force_reg (SImode, operands[1]);
4004 operands[2] = force_reg (SImode, operands[2]);
4005 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4006 /* We do not want (subreg:SI (XX:DI) 1)) for TARGET_64BIT since
4007 that has no real meaning. */
4010 emit_insn (gen_rtx_SET (VOIDmode,
4012 gen_rtx_SUBREG (SImode, scratch, 0)));
4016 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4017 gen_rtx_SUBREG (SImode, scratch, 1)));
4020 operands[3] = gen_reg_rtx (SImode);
4023 (define_insn "umulsidi3"
4024 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4025 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4026 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
4027 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4029 [(set_attr "type" "fpmuldbl")
4030 (set_attr "length" "4")])
4033 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4034 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4035 (match_operand:DI 2 "uint32_operand" "f")))]
4036 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
4038 [(set_attr "type" "fpmuldbl")
4039 (set_attr "length" "4")])
4042 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4043 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4044 (match_operand:DI 2 "uint32_operand" "f")))]
4045 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
4047 [(set_attr "type" "fpmuldbl")
4048 (set_attr "length" "4")])
4051 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4052 (clobber (match_operand:SI 0 "register_operand" "=a"))
4053 (clobber (reg:SI 26))
4054 (clobber (reg:SI 25))
4055 (clobber (reg:SI 31))]
4057 "* return output_mul_insn (0, insn);"
4058 [(set_attr "type" "milli")
4059 (set (attr "length")
4061 ;; Target (or stub) within reach
4062 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4064 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4069 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4073 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4074 ;; same as NO_SPACE_REGS code
4075 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4077 (eq (symbol_ref "flag_pic")
4081 ;; Out of range and either PIC or PORTABLE_RUNTIME
4084 (define_expand "muldi3"
4085 [(set (match_operand:DI 0 "register_operand" "")
4086 (mult:DI (match_operand:DI 1 "register_operand" "")
4087 (match_operand:DI 2 "register_operand" "")))]
4088 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4091 rtx low_product = gen_reg_rtx (DImode);
4092 rtx cross_product1 = gen_reg_rtx (DImode);
4093 rtx cross_product2 = gen_reg_rtx (DImode);
4094 rtx cross_scratch = gen_reg_rtx (DImode);
4095 rtx cross_product = gen_reg_rtx (DImode);
4096 rtx op1l, op1r, op2l, op2r;
4097 rtx op1shifted, op2shifted;
4099 op1shifted = gen_reg_rtx (DImode);
4100 op2shifted = gen_reg_rtx (DImode);
4101 op1l = gen_reg_rtx (SImode);
4102 op1r = gen_reg_rtx (SImode);
4103 op2l = gen_reg_rtx (SImode);
4104 op2r = gen_reg_rtx (SImode);
4106 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
4108 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
4110 op1r = gen_rtx_SUBREG (SImode, operands[1], 0);
4111 op2r = gen_rtx_SUBREG (SImode, operands[2], 0);
4112 op1l = gen_rtx_SUBREG (SImode, op1shifted, 0);
4113 op2l = gen_rtx_SUBREG (SImode, op2shifted, 0);
4115 /* Emit multiplies for the cross products. */
4116 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
4117 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
4119 /* Emit a multiply for the low sub-word. */
4120 emit_insn (gen_umulsidi3 (low_product, op2r, op1r));
4122 /* Sum the cross products and shift them into proper position. */
4123 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
4124 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
4126 /* Add the cross product to the low product and store the result
4127 into the output operand . */
4128 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
4132 ;;; Division and mod.
4133 (define_expand "divsi3"
4134 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4135 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4136 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
4137 (clobber (match_dup 3))
4138 (clobber (match_dup 4))
4139 (clobber (reg:SI 26))
4140 (clobber (reg:SI 25))
4141 (clobber (reg:SI 31))])
4142 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4146 operands[3] = gen_reg_rtx (SImode);
4147 operands[4] = gen_reg_rtx (SImode);
4149 operands[4] = gen_rtx_REG (SImode, 2);
4150 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
4156 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4157 (clobber (match_operand:SI 1 "register_operand" "=a"))
4158 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4159 (clobber (reg:SI 26))
4160 (clobber (reg:SI 25))
4161 (clobber (reg:SI 31))]
4164 return output_div_insn (operands, 0, insn);"
4165 [(set_attr "type" "milli")
4166 (set (attr "length")
4168 ;; Target (or stub) within reach
4169 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4171 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4176 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4180 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4181 ;; same as NO_SPACE_REGS code
4182 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4184 (eq (symbol_ref "flag_pic")
4188 ;; Out of range and either PIC or PORTABLE_RUNTIME
4191 (define_expand "udivsi3"
4192 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4193 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4194 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
4195 (clobber (match_dup 3))
4196 (clobber (match_dup 4))
4197 (clobber (reg:SI 26))
4198 (clobber (reg:SI 25))
4199 (clobber (reg:SI 31))])
4200 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4204 operands[3] = gen_reg_rtx (SImode);
4205 operands[4] = gen_reg_rtx (SImode);
4207 operands[4] = gen_rtx_REG (SImode, 2);
4208 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4214 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4215 (clobber (match_operand:SI 1 "register_operand" "=a"))
4216 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4217 (clobber (reg:SI 26))
4218 (clobber (reg:SI 25))
4219 (clobber (reg:SI 31))]
4222 return output_div_insn (operands, 1, insn);"
4223 [(set_attr "type" "milli")
4224 (set (attr "length")
4226 ;; Target (or stub) within reach
4227 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4229 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4234 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4238 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4239 ;; same as NO_SPACE_REGS code
4240 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4242 (eq (symbol_ref "flag_pic")
4246 ;; Out of range and either PIC or PORTABLE_RUNTIME
4249 (define_expand "modsi3"
4250 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4251 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4252 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4253 (clobber (match_dup 3))
4254 (clobber (match_dup 4))
4255 (clobber (reg:SI 26))
4256 (clobber (reg:SI 25))
4257 (clobber (reg:SI 31))])
4258 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4262 operands[4] = gen_reg_rtx (SImode);
4264 operands[4] = gen_rtx_REG (SImode, 2);
4265 operands[3] = gen_reg_rtx (SImode);
4269 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4270 (clobber (match_operand:SI 0 "register_operand" "=a"))
4271 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4272 (clobber (reg:SI 26))
4273 (clobber (reg:SI 25))
4274 (clobber (reg:SI 31))]
4277 return output_mod_insn (0, insn);"
4278 [(set_attr "type" "milli")
4279 (set (attr "length")
4281 ;; Target (or stub) within reach
4282 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4284 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4289 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4293 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4294 ;; same as NO_SPACE_REGS code
4295 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4297 (eq (symbol_ref "flag_pic")
4301 ;; Out of range and either PIC or PORTABLE_RUNTIME
4304 (define_expand "umodsi3"
4305 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4306 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4307 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4308 (clobber (match_dup 3))
4309 (clobber (match_dup 4))
4310 (clobber (reg:SI 26))
4311 (clobber (reg:SI 25))
4312 (clobber (reg:SI 31))])
4313 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4317 operands[4] = gen_reg_rtx (SImode);
4319 operands[4] = gen_rtx_REG (SImode, 2);
4320 operands[3] = gen_reg_rtx (SImode);
4324 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4325 (clobber (match_operand:SI 0 "register_operand" "=a"))
4326 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4327 (clobber (reg:SI 26))
4328 (clobber (reg:SI 25))
4329 (clobber (reg:SI 31))]
4332 return output_mod_insn (1, insn);"
4333 [(set_attr "type" "milli")
4334 (set (attr "length")
4336 ;; Target (or stub) within reach
4337 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4339 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4344 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4348 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4349 ;; same as NO_SPACE_REGS code
4350 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4352 (eq (symbol_ref "flag_pic")
4356 ;; Out of range and either PIC or PORTABLE_RUNTIME
4359 ;;- and instructions
4360 ;; We define DImode `and` so with DImode `not` we can get
4361 ;; DImode `andn`. Other combinations are possible.
4363 (define_expand "anddi3"
4364 [(set (match_operand:DI 0 "register_operand" "")
4365 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4366 (match_operand:DI 2 "arith_double_operand" "")))]
4370 if (! register_operand (operands[1], DImode)
4371 || ! register_operand (operands[2], DImode))
4372 /* Let GCC break this into word-at-a-time operations. */
4377 [(set (match_operand:DI 0 "register_operand" "=r")
4378 (and:DI (match_operand:DI 1 "register_operand" "%r")
4379 (match_operand:DI 2 "register_operand" "r")))]
4381 "and %1,%2,%0\;and %R1,%R2,%R0"
4382 [(set_attr "type" "binary")
4383 (set_attr "length" "8")])
4386 [(set (match_operand:DI 0 "register_operand" "=r,r")
4387 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4388 (match_operand:DI 2 "and_operand" "rO,P")))]
4390 "* return output_64bit_and (operands); "
4391 [(set_attr "type" "binary")
4392 (set_attr "length" "4")])
4394 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4395 ; constant with ldil;ldo.
4396 (define_insn "andsi3"
4397 [(set (match_operand:SI 0 "register_operand" "=r,r")
4398 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4399 (match_operand:SI 2 "and_operand" "rO,P")))]
4401 "* return output_and (operands); "
4402 [(set_attr "type" "binary,shift")
4403 (set_attr "length" "4,4")])
4406 [(set (match_operand:DI 0 "register_operand" "=r")
4407 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4408 (match_operand:DI 2 "register_operand" "r")))]
4410 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4411 [(set_attr "type" "binary")
4412 (set_attr "length" "8")])
4415 [(set (match_operand:DI 0 "register_operand" "=r")
4416 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4417 (match_operand:DI 2 "register_operand" "r")))]
4420 [(set_attr "type" "binary")
4421 (set_attr "length" "4")])
4424 [(set (match_operand:SI 0 "register_operand" "=r")
4425 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4426 (match_operand:SI 2 "register_operand" "r")))]
4429 [(set_attr "type" "binary")
4430 (set_attr "length" "4")])
4432 (define_expand "iordi3"
4433 [(set (match_operand:DI 0 "register_operand" "")
4434 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4435 (match_operand:DI 2 "arith_double_operand" "")))]
4439 if (! register_operand (operands[1], DImode)
4440 || ! register_operand (operands[2], DImode))
4441 /* Let GCC break this into word-at-a-time operations. */
4446 [(set (match_operand:DI 0 "register_operand" "=r")
4447 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4448 (match_operand:DI 2 "register_operand" "r")))]
4450 "or %1,%2,%0\;or %R1,%R2,%R0"
4451 [(set_attr "type" "binary")
4452 (set_attr "length" "8")])
4455 [(set (match_operand:DI 0 "register_operand" "=r,r")
4456 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4457 (match_operand:DI 2 "ior_operand" "M,i")))]
4459 "* return output_64bit_ior (operands); "
4460 [(set_attr "type" "binary,shift")
4461 (set_attr "length" "4,4")])
4464 [(set (match_operand:DI 0 "register_operand" "=r")
4465 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4466 (match_operand:DI 2 "register_operand" "r")))]
4469 [(set_attr "type" "binary")
4470 (set_attr "length" "4")])
4472 ;; Need a define_expand because we've run out of CONST_OK... characters.
4473 (define_expand "iorsi3"
4474 [(set (match_operand:SI 0 "register_operand" "")
4475 (ior:SI (match_operand:SI 1 "register_operand" "")
4476 (match_operand:SI 2 "arith32_operand" "")))]
4480 if (! (ior_operand (operands[2], SImode)
4481 || register_operand (operands[2], SImode)))
4482 operands[2] = force_reg (SImode, operands[2]);
4486 [(set (match_operand:SI 0 "register_operand" "=r,r")
4487 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4488 (match_operand:SI 2 "ior_operand" "M,i")))]
4490 "* return output_ior (operands); "
4491 [(set_attr "type" "binary,shift")
4492 (set_attr "length" "4,4")])
4495 [(set (match_operand:SI 0 "register_operand" "=r")
4496 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4497 (match_operand:SI 2 "register_operand" "r")))]
4500 [(set_attr "type" "binary")
4501 (set_attr "length" "4")])
4503 (define_expand "xordi3"
4504 [(set (match_operand:DI 0 "register_operand" "")
4505 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4506 (match_operand:DI 2 "arith_double_operand" "")))]
4510 if (! register_operand (operands[1], DImode)
4511 || ! register_operand (operands[2], DImode))
4512 /* Let GCC break this into word-at-a-time operations. */
4517 [(set (match_operand:DI 0 "register_operand" "=r")
4518 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4519 (match_operand:DI 2 "register_operand" "r")))]
4521 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4522 [(set_attr "type" "binary")
4523 (set_attr "length" "8")])
4526 [(set (match_operand:DI 0 "register_operand" "=r")
4527 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4528 (match_operand:DI 2 "register_operand" "r")))]
4531 [(set_attr "type" "binary")
4532 (set_attr "length" "4")])
4534 (define_insn "xorsi3"
4535 [(set (match_operand:SI 0 "register_operand" "=r")
4536 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4537 (match_operand:SI 2 "register_operand" "r")))]
4540 [(set_attr "type" "binary")
4541 (set_attr "length" "4")])
4543 (define_expand "negdi2"
4544 [(set (match_operand:DI 0 "register_operand" "")
4545 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4550 [(set (match_operand:DI 0 "register_operand" "=r")
4551 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4553 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4554 [(set_attr "type" "unary")
4555 (set_attr "length" "8")])
4558 [(set (match_operand:DI 0 "register_operand" "=r")
4559 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4562 [(set_attr "type" "unary")
4563 (set_attr "length" "4")])
4565 (define_insn "negsi2"
4566 [(set (match_operand:SI 0 "register_operand" "=r")
4567 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4570 [(set_attr "type" "unary")
4571 (set_attr "length" "4")])
4573 (define_expand "one_cmpldi2"
4574 [(set (match_operand:DI 0 "register_operand" "")
4575 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4579 if (! register_operand (operands[1], DImode))
4584 [(set (match_operand:DI 0 "register_operand" "=r")
4585 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4587 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4588 [(set_attr "type" "unary")
4589 (set_attr "length" "8")])
4592 [(set (match_operand:DI 0 "register_operand" "=r")
4593 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4596 [(set_attr "type" "unary")
4597 (set_attr "length" "4")])
4599 (define_insn "one_cmplsi2"
4600 [(set (match_operand:SI 0 "register_operand" "=r")
4601 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4604 [(set_attr "type" "unary")
4605 (set_attr "length" "4")])
4607 ;; Floating point arithmetic instructions.
4609 (define_insn "adddf3"
4610 [(set (match_operand:DF 0 "register_operand" "=f")
4611 (plus:DF (match_operand:DF 1 "register_operand" "f")
4612 (match_operand:DF 2 "register_operand" "f")))]
4613 "! TARGET_SOFT_FLOAT"
4615 [(set_attr "type" "fpalu")
4616 (set_attr "pa_combine_type" "faddsub")
4617 (set_attr "length" "4")])
4619 (define_insn "addsf3"
4620 [(set (match_operand:SF 0 "register_operand" "=f")
4621 (plus:SF (match_operand:SF 1 "register_operand" "f")
4622 (match_operand:SF 2 "register_operand" "f")))]
4623 "! TARGET_SOFT_FLOAT"
4625 [(set_attr "type" "fpalu")
4626 (set_attr "pa_combine_type" "faddsub")
4627 (set_attr "length" "4")])
4629 (define_insn "subdf3"
4630 [(set (match_operand:DF 0 "register_operand" "=f")
4631 (minus:DF (match_operand:DF 1 "register_operand" "f")
4632 (match_operand:DF 2 "register_operand" "f")))]
4633 "! TARGET_SOFT_FLOAT"
4635 [(set_attr "type" "fpalu")
4636 (set_attr "pa_combine_type" "faddsub")
4637 (set_attr "length" "4")])
4639 (define_insn "subsf3"
4640 [(set (match_operand:SF 0 "register_operand" "=f")
4641 (minus:SF (match_operand:SF 1 "register_operand" "f")
4642 (match_operand:SF 2 "register_operand" "f")))]
4643 "! TARGET_SOFT_FLOAT"
4645 [(set_attr "type" "fpalu")
4646 (set_attr "pa_combine_type" "faddsub")
4647 (set_attr "length" "4")])
4649 (define_insn "muldf3"
4650 [(set (match_operand:DF 0 "register_operand" "=f")
4651 (mult:DF (match_operand:DF 1 "register_operand" "f")
4652 (match_operand:DF 2 "register_operand" "f")))]
4653 "! TARGET_SOFT_FLOAT"
4655 [(set_attr "type" "fpmuldbl")
4656 (set_attr "pa_combine_type" "fmpy")
4657 (set_attr "length" "4")])
4659 (define_insn "mulsf3"
4660 [(set (match_operand:SF 0 "register_operand" "=f")
4661 (mult:SF (match_operand:SF 1 "register_operand" "f")
4662 (match_operand:SF 2 "register_operand" "f")))]
4663 "! TARGET_SOFT_FLOAT"
4665 [(set_attr "type" "fpmulsgl")
4666 (set_attr "pa_combine_type" "fmpy")
4667 (set_attr "length" "4")])
4669 (define_insn "divdf3"
4670 [(set (match_operand:DF 0 "register_operand" "=f")
4671 (div:DF (match_operand:DF 1 "register_operand" "f")
4672 (match_operand:DF 2 "register_operand" "f")))]
4673 "! TARGET_SOFT_FLOAT"
4675 [(set_attr "type" "fpdivdbl")
4676 (set_attr "length" "4")])
4678 (define_insn "divsf3"
4679 [(set (match_operand:SF 0 "register_operand" "=f")
4680 (div:SF (match_operand:SF 1 "register_operand" "f")
4681 (match_operand:SF 2 "register_operand" "f")))]
4682 "! TARGET_SOFT_FLOAT"
4684 [(set_attr "type" "fpdivsgl")
4685 (set_attr "length" "4")])
4687 (define_insn "negdf2"
4688 [(set (match_operand:DF 0 "register_operand" "=f")
4689 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4690 "! TARGET_SOFT_FLOAT"
4694 return \"fneg,dbl %1,%0\";
4696 return \"fsub,dbl %%fr0,%1,%0\";
4698 [(set_attr "type" "fpalu")
4699 (set_attr "length" "4")])
4701 (define_insn "negsf2"
4702 [(set (match_operand:SF 0 "register_operand" "=f")
4703 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4704 "! TARGET_SOFT_FLOAT"
4708 return \"fneg,sgl %1,%0\";
4710 return \"fsub,sgl %%fr0,%1,%0\";
4712 [(set_attr "type" "fpalu")
4713 (set_attr "length" "4")])
4715 (define_insn "absdf2"
4716 [(set (match_operand:DF 0 "register_operand" "=f")
4717 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4718 "! TARGET_SOFT_FLOAT"
4720 [(set_attr "type" "fpalu")
4721 (set_attr "length" "4")])
4723 (define_insn "abssf2"
4724 [(set (match_operand:SF 0 "register_operand" "=f")
4725 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4726 "! TARGET_SOFT_FLOAT"
4728 [(set_attr "type" "fpalu")
4729 (set_attr "length" "4")])
4731 (define_insn "sqrtdf2"
4732 [(set (match_operand:DF 0 "register_operand" "=f")
4733 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4734 "! TARGET_SOFT_FLOAT"
4736 [(set_attr "type" "fpsqrtdbl")
4737 (set_attr "length" "4")])
4739 (define_insn "sqrtsf2"
4740 [(set (match_operand:SF 0 "register_operand" "=f")
4741 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4742 "! TARGET_SOFT_FLOAT"
4744 [(set_attr "type" "fpsqrtsgl")
4745 (set_attr "length" "4")])
4747 ;; PA 2.0 floating point instructions
4751 [(set (match_operand:DF 0 "register_operand" "=f")
4752 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4753 (match_operand:DF 2 "register_operand" "f"))
4754 (match_operand:DF 3 "register_operand" "f")))]
4755 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4756 "fmpyfadd,dbl %1,%2,%3,%0"
4757 [(set_attr "type" "fpmuldbl")
4758 (set_attr "length" "4")])
4761 [(set (match_operand:DF 0 "register_operand" "=f")
4762 (plus:DF (match_operand:DF 1 "register_operand" "f")
4763 (mult:DF (match_operand:DF 2 "register_operand" "f")
4764 (match_operand:DF 3 "register_operand" "f"))))]
4765 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4766 "fmpyfadd,dbl %2,%3,%1,%0"
4767 [(set_attr "type" "fpmuldbl")
4768 (set_attr "length" "4")])
4771 [(set (match_operand:SF 0 "register_operand" "=f")
4772 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4773 (match_operand:SF 2 "register_operand" "f"))
4774 (match_operand:SF 3 "register_operand" "f")))]
4775 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4776 "fmpyfadd,sgl %1,%2,%3,%0"
4777 [(set_attr "type" "fpmulsgl")
4778 (set_attr "length" "4")])
4781 [(set (match_operand:SF 0 "register_operand" "=f")
4782 (plus:SF (match_operand:SF 1 "register_operand" "f")
4783 (mult:SF (match_operand:SF 2 "register_operand" "f")
4784 (match_operand:SF 3 "register_operand" "f"))))]
4785 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4786 "fmpyfadd,sgl %2,%3,%1,%0"
4787 [(set_attr "type" "fpmulsgl")
4788 (set_attr "length" "4")])
4790 ; fmpynfadd patterns
4792 [(set (match_operand:DF 0 "register_operand" "=f")
4793 (minus:DF (match_operand:DF 1 "register_operand" "f")
4794 (mult:DF (match_operand:DF 2 "register_operand" "f")
4795 (match_operand:DF 3 "register_operand" "f"))))]
4796 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4797 "fmpynfadd,dbl %2,%3,%1,%0"
4798 [(set_attr "type" "fpmuldbl")
4799 (set_attr "length" "4")])
4802 [(set (match_operand:SF 0 "register_operand" "=f")
4803 (minus:SF (match_operand:SF 1 "register_operand" "f")
4804 (mult:SF (match_operand:SF 2 "register_operand" "f")
4805 (match_operand:SF 3 "register_operand" "f"))))]
4806 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4807 "fmpynfadd,sgl %2,%3,%1,%0"
4808 [(set_attr "type" "fpmulsgl")
4809 (set_attr "length" "4")])
4813 [(set (match_operand:DF 0 "register_operand" "=f")
4814 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4815 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4817 [(set_attr "type" "fpalu")
4818 (set_attr "length" "4")])
4821 [(set (match_operand:SF 0 "register_operand" "=f")
4822 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4823 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4825 [(set_attr "type" "fpalu")
4826 (set_attr "length" "4")])
4828 ;; Generating a fused multiply sequence is a win for this case as it will
4829 ;; reduce the latency for the fused case without impacting the plain
4832 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4833 ;; perform two operations with the result of the first feeding the second.
4835 [(set (match_operand:DF 0 "register_operand" "=f")
4836 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4837 (match_operand:DF 2 "register_operand" "f"))
4838 (match_operand:DF 3 "register_operand" "f")))
4839 (set (match_operand:DF 4 "register_operand" "=&f")
4840 (mult:DF (match_dup 1) (match_dup 2)))]
4841 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4842 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4843 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4845 [(set_attr "type" "fpmuldbl")
4846 (set_attr "length" "8")])
4848 ;; We want to split this up during scheduling since we want both insns
4849 ;; to schedule independently.
4851 [(set (match_operand:DF 0 "register_operand" "=f")
4852 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4853 (match_operand:DF 2 "register_operand" "f"))
4854 (match_operand:DF 3 "register_operand" "f")))
4855 (set (match_operand:DF 4 "register_operand" "=&f")
4856 (mult:DF (match_dup 1) (match_dup 2)))]
4857 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4858 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4859 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4864 [(set (match_operand:SF 0 "register_operand" "=f")
4865 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4866 (match_operand:SF 2 "register_operand" "f"))
4867 (match_operand:SF 3 "register_operand" "f")))
4868 (set (match_operand:SF 4 "register_operand" "=&f")
4869 (mult:SF (match_dup 1) (match_dup 2)))]
4870 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4871 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4872 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4874 [(set_attr "type" "fpmuldbl")
4875 (set_attr "length" "8")])
4877 ;; We want to split this up during scheduling since we want both insns
4878 ;; to schedule independently.
4880 [(set (match_operand:SF 0 "register_operand" "=f")
4881 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4882 (match_operand:SF 2 "register_operand" "f"))
4883 (match_operand:SF 3 "register_operand" "f")))
4884 (set (match_operand:SF 4 "register_operand" "=&f")
4885 (mult:SF (match_dup 1) (match_dup 2)))]
4886 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4887 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4888 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
4892 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
4895 [(set (match_operand:DF 0 "register_operand" "=f")
4896 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4897 (match_operand:DF 2 "register_operand" "f"))))]
4898 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4899 "fmpynfadd,dbl %1,%2,%%fr0,%0"
4900 [(set_attr "type" "fpmuldbl")
4901 (set_attr "length" "4")])
4904 [(set (match_operand:SF 0 "register_operand" "=f")
4905 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4906 (match_operand:SF 2 "register_operand" "f"))))]
4907 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4908 "fmpynfadd,sgl %1,%2,%%fr0,%0"
4909 [(set_attr "type" "fpmuldbl")
4910 (set_attr "length" "4")])
4913 [(set (match_operand:DF 0 "register_operand" "=f")
4914 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4915 (match_operand:DF 2 "register_operand" "f"))))
4916 (set (match_operand:DF 3 "register_operand" "=&f")
4917 (mult:DF (match_dup 1) (match_dup 2)))]
4918 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4919 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4920 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4922 [(set_attr "type" "fpmuldbl")
4923 (set_attr "length" "8")])
4926 [(set (match_operand:DF 0 "register_operand" "=f")
4927 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4928 (match_operand:DF 2 "register_operand" "f"))))
4929 (set (match_operand:DF 3 "register_operand" "=&f")
4930 (mult:DF (match_dup 1) (match_dup 2)))]
4931 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4932 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
4933 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
4937 [(set (match_operand:SF 0 "register_operand" "=f")
4938 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4939 (match_operand:SF 2 "register_operand" "f"))))
4940 (set (match_operand:SF 3 "register_operand" "=&f")
4941 (mult:SF (match_dup 1) (match_dup 2)))]
4942 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4943 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4944 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4946 [(set_attr "type" "fpmuldbl")
4947 (set_attr "length" "8")])
4950 [(set (match_operand:SF 0 "register_operand" "=f")
4951 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4952 (match_operand:SF 2 "register_operand" "f"))))
4953 (set (match_operand:SF 3 "register_operand" "=&f")
4954 (mult:SF (match_dup 1) (match_dup 2)))]
4955 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4956 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
4957 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
4960 ;; Now fused multiplies with the result of the multiply negated.
4962 [(set (match_operand:DF 0 "register_operand" "=f")
4963 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4964 (match_operand:DF 2 "register_operand" "f")))
4965 (match_operand:DF 3 "register_operand" "f")))]
4966 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4967 "fmpynfadd,dbl %1,%2,%3,%0"
4968 [(set_attr "type" "fpmuldbl")
4969 (set_attr "length" "4")])
4972 [(set (match_operand:SF 0 "register_operand" "=f")
4973 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4974 (match_operand:SF 2 "register_operand" "f")))
4975 (match_operand:SF 3 "register_operand" "f")))]
4976 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4977 "fmpynfadd,sgl %1,%2,%3,%0"
4978 [(set_attr "type" "fpmuldbl")
4979 (set_attr "length" "4")])
4982 [(set (match_operand:DF 0 "register_operand" "=f")
4983 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4984 (match_operand:DF 2 "register_operand" "f")))
4985 (match_operand:DF 3 "register_operand" "f")))
4986 (set (match_operand:DF 4 "register_operand" "=&f")
4987 (mult:DF (match_dup 1) (match_dup 2)))]
4988 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4989 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4990 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4992 [(set_attr "type" "fpmuldbl")
4993 (set_attr "length" "8")])
4996 [(set (match_operand:DF 0 "register_operand" "=f")
4997 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4998 (match_operand:DF 2 "register_operand" "f")))
4999 (match_operand:DF 3 "register_operand" "f")))
5000 (set (match_operand:DF 4 "register_operand" "=&f")
5001 (mult:DF (match_dup 1) (match_dup 2)))]
5002 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5003 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5004 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
5009 [(set (match_operand:SF 0 "register_operand" "=f")
5010 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5011 (match_operand:SF 2 "register_operand" "f")))
5012 (match_operand:SF 3 "register_operand" "f")))
5013 (set (match_operand:SF 4 "register_operand" "=&f")
5014 (mult:SF (match_dup 1) (match_dup 2)))]
5015 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5016 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5017 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5019 [(set_attr "type" "fpmuldbl")
5020 (set_attr "length" "8")])
5023 [(set (match_operand:SF 0 "register_operand" "=f")
5024 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5025 (match_operand:SF 2 "register_operand" "f")))
5026 (match_operand:SF 3 "register_operand" "f")))
5027 (set (match_operand:SF 4 "register_operand" "=&f")
5028 (mult:SF (match_dup 1) (match_dup 2)))]
5029 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5030 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5031 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
5036 [(set (match_operand:DF 0 "register_operand" "=f")
5037 (minus:DF (match_operand:DF 3 "register_operand" "f")
5038 (mult:DF (match_operand:DF 1 "register_operand" "f")
5039 (match_operand:DF 2 "register_operand" "f"))))
5040 (set (match_operand:DF 4 "register_operand" "=&f")
5041 (mult:DF (match_dup 1) (match_dup 2)))]
5042 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5043 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5044 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5046 [(set_attr "type" "fpmuldbl")
5047 (set_attr "length" "8")])
5050 [(set (match_operand:DF 0 "register_operand" "=f")
5051 (minus:DF (match_operand:DF 3 "register_operand" "f")
5052 (mult:DF (match_operand:DF 1 "register_operand" "f")
5053 (match_operand:DF 2 "register_operand" "f"))))
5054 (set (match_operand:DF 4 "register_operand" "=&f")
5055 (mult:DF (match_dup 1) (match_dup 2)))]
5056 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5057 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5058 (set (match_dup 0) (minus:DF (match_dup 3)
5059 (mult:DF (match_dup 1) (match_dup 2))))]
5063 [(set (match_operand:SF 0 "register_operand" "=f")
5064 (minus:SF (match_operand:SF 3 "register_operand" "f")
5065 (mult:SF (match_operand:SF 1 "register_operand" "f")
5066 (match_operand:SF 2 "register_operand" "f"))))
5067 (set (match_operand:SF 4 "register_operand" "=&f")
5068 (mult:SF (match_dup 1) (match_dup 2)))]
5069 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5070 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5071 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5073 [(set_attr "type" "fpmuldbl")
5074 (set_attr "length" "8")])
5077 [(set (match_operand:SF 0 "register_operand" "=f")
5078 (minus:SF (match_operand:SF 3 "register_operand" "f")
5079 (mult:SF (match_operand:SF 1 "register_operand" "f")
5080 (match_operand:SF 2 "register_operand" "f"))))
5081 (set (match_operand:SF 4 "register_operand" "=&f")
5082 (mult:SF (match_dup 1) (match_dup 2)))]
5083 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5084 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5085 (set (match_dup 0) (minus:SF (match_dup 3)
5086 (mult:SF (match_dup 1) (match_dup 2))))]
5090 [(set (match_operand:DF 0 "register_operand" "=f")
5091 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5092 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5093 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5094 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5096 [(set_attr "type" "fpalu")
5097 (set_attr "length" "8")])
5100 [(set (match_operand:DF 0 "register_operand" "=f")
5101 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5102 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5103 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5104 [(set (match_dup 2) (abs:DF (match_dup 1)))
5105 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
5109 [(set (match_operand:SF 0 "register_operand" "=f")
5110 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5111 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5112 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5113 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5115 [(set_attr "type" "fpalu")
5116 (set_attr "length" "8")])
5119 [(set (match_operand:SF 0 "register_operand" "=f")
5120 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5121 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5122 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5123 [(set (match_dup 2) (abs:SF (match_dup 1)))
5124 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
5127 ;;- Shift instructions
5129 ;; Optimized special case of shifting.
5132 [(set (match_operand:SI 0 "register_operand" "=r")
5133 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5137 [(set_attr "type" "load")
5138 (set_attr "length" "4")])
5141 [(set (match_operand:SI 0 "register_operand" "=r")
5142 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5146 [(set_attr "type" "load")
5147 (set_attr "length" "4")])
5150 [(set (match_operand:SI 0 "register_operand" "=r")
5151 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
5152 (match_operand:SI 3 "shadd_operand" ""))
5153 (match_operand:SI 1 "register_operand" "r")))]
5155 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
5156 [(set_attr "type" "binary")
5157 (set_attr "length" "4")])
5160 [(set (match_operand:DI 0 "register_operand" "=r")
5161 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
5162 (match_operand:DI 3 "shadd_operand" ""))
5163 (match_operand:DI 1 "register_operand" "r")))]
5165 "shladd,l %2,%O3,%1,%0"
5166 [(set_attr "type" "binary")
5167 (set_attr "length" "4")])
5169 (define_expand "ashlsi3"
5170 [(set (match_operand:SI 0 "register_operand" "")
5171 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
5172 (match_operand:SI 2 "arith32_operand" "")))]
5176 if (GET_CODE (operands[2]) != CONST_INT)
5178 rtx temp = gen_reg_rtx (SImode);
5179 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5180 if (GET_CODE (operands[1]) == CONST_INT)
5181 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
5183 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
5186 /* Make sure both inputs are not constants,
5187 there are no patterns for that. */
5188 operands[1] = force_reg (SImode, operands[1]);
5192 [(set (match_operand:SI 0 "register_operand" "=r")
5193 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5194 (match_operand:SI 2 "const_int_operand" "n")))]
5196 "{zdep|depw,z} %1,%P2,%L2,%0"
5197 [(set_attr "type" "shift")
5198 (set_attr "length" "4")])
5200 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5201 ; Doing it like this makes slightly better code since reload can
5202 ; replace a register with a known value in range -16..15 with a
5203 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5204 ; but since we have no more CONST_OK... characters, that is not
5206 (define_insn "zvdep32"
5207 [(set (match_operand:SI 0 "register_operand" "=r,r")
5208 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5209 (minus:SI (const_int 31)
5210 (match_operand:SI 2 "register_operand" "q,q"))))]
5213 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5214 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5215 [(set_attr "type" "shift,shift")
5216 (set_attr "length" "4,4")])
5218 (define_insn "zvdep_imm32"
5219 [(set (match_operand:SI 0 "register_operand" "=r")
5220 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5221 (minus:SI (const_int 31)
5222 (match_operand:SI 2 "register_operand" "q"))))]
5226 int x = INTVAL (operands[1]);
5227 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5228 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5229 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5231 [(set_attr "type" "shift")
5232 (set_attr "length" "4")])
5234 (define_insn "vdepi_ior"
5235 [(set (match_operand:SI 0 "register_operand" "=r")
5236 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5237 (minus:SI (const_int 31)
5238 (match_operand:SI 2 "register_operand" "q")))
5239 (match_operand:SI 3 "register_operand" "0")))]
5240 ; accept ...0001...1, can this be generalized?
5241 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5244 int x = INTVAL (operands[1]);
5245 operands[2] = GEN_INT (exact_log2 (x + 1));
5246 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5248 [(set_attr "type" "shift")
5249 (set_attr "length" "4")])
5251 (define_insn "vdepi_and"
5252 [(set (match_operand:SI 0 "register_operand" "=r")
5253 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5254 (minus:SI (const_int 31)
5255 (match_operand:SI 2 "register_operand" "q")))
5256 (match_operand:SI 3 "register_operand" "0")))]
5257 ; this can be generalized...!
5258 "INTVAL (operands[1]) == -2"
5261 int x = INTVAL (operands[1]);
5262 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5263 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5265 [(set_attr "type" "shift")
5266 (set_attr "length" "4")])
5268 (define_expand "ashldi3"
5269 [(set (match_operand:DI 0 "register_operand" "")
5270 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5271 (match_operand:DI 2 "arith32_operand" "")))]
5275 if (GET_CODE (operands[2]) != CONST_INT)
5277 rtx temp = gen_reg_rtx (DImode);
5278 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5279 if (GET_CODE (operands[1]) == CONST_INT)
5280 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5282 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5285 /* Make sure both inputs are not constants,
5286 there are no patterns for that. */
5287 operands[1] = force_reg (DImode, operands[1]);
5291 [(set (match_operand:DI 0 "register_operand" "=r")
5292 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5293 (match_operand:DI 2 "const_int_operand" "n")))]
5295 "depd,z %1,%p2,%Q2,%0"
5296 [(set_attr "type" "shift")
5297 (set_attr "length" "4")])
5299 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5300 ; Doing it like this makes slightly better code since reload can
5301 ; replace a register with a known value in range -16..15 with a
5302 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5303 ; but since we have no more CONST_OK... characters, that is not
5305 (define_insn "zvdep64"
5306 [(set (match_operand:DI 0 "register_operand" "=r,r")
5307 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5308 (minus:DI (const_int 63)
5309 (match_operand:DI 2 "register_operand" "q,q"))))]
5312 depd,z %1,%%sar,64,%0
5313 depdi,z %1,%%sar,64,%0"
5314 [(set_attr "type" "shift,shift")
5315 (set_attr "length" "4,4")])
5317 (define_insn "zvdep_imm64"
5318 [(set (match_operand:DI 0 "register_operand" "=r")
5319 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5320 (minus:DI (const_int 63)
5321 (match_operand:DI 2 "register_operand" "q"))))]
5325 int x = INTVAL (operands[1]);
5326 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5327 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5328 return \"depdi,z %1,%%sar,%2,%0\";
5330 [(set_attr "type" "shift")
5331 (set_attr "length" "4")])
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5336 (minus:DI (const_int 63)
5337 (match_operand:DI 2 "register_operand" "q")))
5338 (match_operand:DI 3 "register_operand" "0")))]
5339 ; accept ...0001...1, can this be generalized?
5340 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5343 int x = INTVAL (operands[1]);
5344 operands[2] = GEN_INT (exact_log2 (x + 1));
5345 return \"depdi -1,%%sar,%2,%0\";
5347 [(set_attr "type" "shift")
5348 (set_attr "length" "4")])
5351 [(set (match_operand:DI 0 "register_operand" "=r")
5352 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5353 (minus:DI (const_int 63)
5354 (match_operand:DI 2 "register_operand" "q")))
5355 (match_operand:DI 3 "register_operand" "0")))]
5356 ; this can be generalized...!
5357 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5360 int x = INTVAL (operands[1]);
5361 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5362 return \"depdi 0,%%sar,%2,%0\";
5364 [(set_attr "type" "shift")
5365 (set_attr "length" "4")])
5367 (define_expand "ashrsi3"
5368 [(set (match_operand:SI 0 "register_operand" "")
5369 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5370 (match_operand:SI 2 "arith32_operand" "")))]
5374 if (GET_CODE (operands[2]) != CONST_INT)
5376 rtx temp = gen_reg_rtx (SImode);
5377 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5378 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5384 [(set (match_operand:SI 0 "register_operand" "=r")
5385 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5386 (match_operand:SI 2 "const_int_operand" "n")))]
5388 "{extrs|extrw,s} %1,%P2,%L2,%0"
5389 [(set_attr "type" "shift")
5390 (set_attr "length" "4")])
5392 (define_insn "vextrs32"
5393 [(set (match_operand:SI 0 "register_operand" "=r")
5394 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5395 (minus:SI (const_int 31)
5396 (match_operand:SI 2 "register_operand" "q"))))]
5398 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5399 [(set_attr "type" "shift")
5400 (set_attr "length" "4")])
5402 (define_expand "ashrdi3"
5403 [(set (match_operand:DI 0 "register_operand" "")
5404 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5405 (match_operand:DI 2 "arith32_operand" "")))]
5409 if (GET_CODE (operands[2]) != CONST_INT)
5411 rtx temp = gen_reg_rtx (DImode);
5412 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5413 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5419 [(set (match_operand:DI 0 "register_operand" "=r")
5420 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5421 (match_operand:DI 2 "const_int_operand" "n")))]
5423 "extrd,s %1,%p2,%Q2,%0"
5424 [(set_attr "type" "shift")
5425 (set_attr "length" "4")])
5427 (define_insn "vextrs64"
5428 [(set (match_operand:DI 0 "register_operand" "=r")
5429 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5430 (minus:DI (const_int 63)
5431 (match_operand:DI 2 "register_operand" "q"))))]
5433 "extrd,s %1,%%sar,64,%0"
5434 [(set_attr "type" "shift")
5435 (set_attr "length" "4")])
5437 (define_insn "lshrsi3"
5438 [(set (match_operand:SI 0 "register_operand" "=r,r")
5439 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5440 (match_operand:SI 2 "arith32_operand" "q,n")))]
5443 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5444 {extru|extrw,u} %1,%P2,%L2,%0"
5445 [(set_attr "type" "shift")
5446 (set_attr "length" "4")])
5448 (define_insn "lshrdi3"
5449 [(set (match_operand:DI 0 "register_operand" "=r,r")
5450 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5451 (match_operand:DI 2 "arith32_operand" "q,n")))]
5454 shrpd %%r0,%1,%%sar,%0
5455 extrd,u %1,%p2,%Q2,%0"
5456 [(set_attr "type" "shift")
5457 (set_attr "length" "4")])
5459 (define_insn "rotrsi3"
5460 [(set (match_operand:SI 0 "register_operand" "=r,r")
5461 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5462 (match_operand:SI 2 "arith32_operand" "q,n")))]
5466 if (GET_CODE (operands[2]) == CONST_INT)
5468 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5469 return \"{shd|shrpw} %1,%1,%2,%0\";
5472 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5474 [(set_attr "type" "shift")
5475 (set_attr "length" "4")])
5477 (define_expand "rotlsi3"
5478 [(set (match_operand:SI 0 "register_operand" "")
5479 (rotate:SI (match_operand:SI 1 "register_operand" "")
5480 (match_operand:SI 2 "arith32_operand" "")))]
5484 if (GET_CODE (operands[2]) != CONST_INT)
5486 rtx temp = gen_reg_rtx (SImode);
5487 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5488 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5491 /* Else expand normally. */
5495 [(set (match_operand:SI 0 "register_operand" "=r")
5496 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5497 (match_operand:SI 2 "const_int_operand" "n")))]
5501 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5502 return \"{shd|shrpw} %1,%1,%2,%0\";
5504 [(set_attr "type" "shift")
5505 (set_attr "length" "4")])
5508 [(set (match_operand:SI 0 "register_operand" "=r")
5509 (match_operator:SI 5 "plus_xor_ior_operator"
5510 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5511 (match_operand:SI 3 "const_int_operand" "n"))
5512 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5513 (match_operand:SI 4 "const_int_operand" "n"))]))]
5514 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5515 "{shd|shrpw} %1,%2,%4,%0"
5516 [(set_attr "type" "shift")
5517 (set_attr "length" "4")])
5520 [(set (match_operand:SI 0 "register_operand" "=r")
5521 (match_operator:SI 5 "plus_xor_ior_operator"
5522 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5523 (match_operand:SI 4 "const_int_operand" "n"))
5524 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5525 (match_operand:SI 3 "const_int_operand" "n"))]))]
5526 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5527 "{shd|shrpw} %1,%2,%4,%0"
5528 [(set_attr "type" "shift")
5529 (set_attr "length" "4")])
5532 [(set (match_operand:SI 0 "register_operand" "=r")
5533 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5534 (match_operand:SI 2 "const_int_operand" ""))
5535 (match_operand:SI 3 "const_int_operand" "")))]
5536 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5539 int cnt = INTVAL (operands[2]) & 31;
5540 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5541 operands[2] = GEN_INT (31 - cnt);
5542 return \"{zdep|depw,z} %1,%2,%3,%0\";
5544 [(set_attr "type" "shift")
5545 (set_attr "length" "4")])
5547 ;; Unconditional and other jump instructions.
5549 (define_insn "return"
5551 "hppa_can_use_return_insn_p ()"
5555 return \"bve%* (%%r2)\";
5556 return \"bv%* %%r0(%%r2)\";
5558 [(set_attr "type" "branch")
5559 (set_attr "length" "4")])
5561 ;; Use a different pattern for functions which have non-trivial
5562 ;; epilogues so as not to confuse jump and reorg.
5563 (define_insn "return_internal"
5570 return \"bve%* (%%r2)\";
5571 return \"bv%* %%r0(%%r2)\";
5573 [(set_attr "type" "branch")
5574 (set_attr "length" "4")])
5576 (define_expand "prologue"
5579 "hppa_expand_prologue ();DONE;")
5581 (define_expand "sibcall_epilogue"
5586 hppa_expand_epilogue ();
5590 (define_expand "epilogue"
5595 /* Try to use the trivial return first. Else use the full
5597 if (hppa_can_use_return_insn_p ())
5598 emit_jump_insn (gen_return ());
5601 hppa_expand_epilogue ();
5602 emit_jump_insn (gen_return_internal ());
5607 ;; Special because we use the value placed in %r2 by the bl instruction
5608 ;; from within its delay slot to set the value for the 2nd parameter to
5610 (define_insn "call_profiler"
5611 [(unspec_volatile [(const_int 0)] 0)
5612 (use (match_operand:SI 0 "const_int_operand" ""))]
5614 "{bl|b,l} _mcount,%%r2\;ldo %0(%%r2),%%r25"
5615 [(set_attr "type" "multi")
5616 (set_attr "length" "8")])
5618 (define_insn "blockage"
5619 [(unspec_volatile [(const_int 2)] 0)]
5622 [(set_attr "length" "0")])
5625 [(set (pc) (label_ref (match_operand 0 "" "")))]
5629 extern int optimize;
5631 if (GET_MODE (insn) == SImode)
5634 /* An unconditional branch which can reach its target. */
5635 if (get_attr_length (insn) != 24
5636 && get_attr_length (insn) != 16)
5639 /* An unconditional branch which can not reach its target.
5641 We need to be able to use %r1 as a scratch register; however,
5642 we can never be sure whether or not it's got a live value in
5643 it. Therefore, we must restore its original value after the
5646 To make matters worse, we don't have a stack slot which we
5647 can always clobber. sp-12/sp-16 shouldn't ever have a live
5648 value during a non-optimizing compilation, so we use those
5649 slots for now. We don't support very long branches when
5650 optimizing -- they should be quite rare when optimizing.
5652 Really the way to go long term is a register scavenger; goto
5653 the target of the jump and find a register which we can use
5654 as a scratch to hold the value in %r1. */
5656 /* We don't know how to register scavenge yet. */
5660 /* First store %r1 into the stack. */
5661 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
5663 /* Now load the target address into %r1 and do an indirect jump
5664 to the value specified in %r1. Be careful to generate PIC
5669 xoperands[0] = operands[0];
5670 xoperands[1] = gen_label_rtx ();
5672 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
5674 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5675 CODE_LABEL_NUMBER (xoperands[1]));
5676 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\\n\\tbv %%r0(%%r1)\",
5680 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
5682 /* And restore the value of %r1 in the delay slot. We're not optimizing,
5683 so we know nothing else can be in the delay slot. */
5684 return \"ldw -16(%%r30),%%r1\";
5686 [(set_attr "type" "uncond_branch")
5687 (set_attr "pa_combine_type" "uncond_branch")
5688 (set (attr "length")
5689 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5690 (if_then_else (lt (abs (minus (match_dup 0)
5691 (plus (pc) (const_int 8))))
5695 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5697 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5702 ;; Subroutines of "casesi".
5703 ;; operand 0 is index
5704 ;; operand 1 is the minimum bound
5705 ;; operand 2 is the maximum bound - minimum bound + 1
5706 ;; operand 3 is CODE_LABEL for the table;
5707 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5709 (define_expand "casesi"
5710 [(match_operand:SI 0 "general_operand" "")
5711 (match_operand:SI 1 "const_int_operand" "")
5712 (match_operand:SI 2 "const_int_operand" "")
5713 (match_operand 3 "" "")
5714 (match_operand 4 "" "")]
5718 if (GET_CODE (operands[0]) != REG)
5719 operands[0] = force_reg (SImode, operands[0]);
5721 if (operands[1] != const0_rtx)
5723 rtx reg = gen_reg_rtx (SImode);
5725 operands[1] = GEN_INT (-INTVAL (operands[1]));
5726 if (!INT_14_BITS (operands[1]))
5727 operands[1] = force_reg (SImode, operands[1]);
5728 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5733 /* In 64bit mode we must make sure to wipe the upper bits of the register
5734 just in case the addition overflowed or we had random bits in the
5735 high part of the register. */
5738 rtx reg = gen_reg_rtx (DImode);
5739 emit_insn (gen_extendsidi2 (reg, operands[0]));
5740 operands[0] = gen_rtx_SUBREG (SImode, reg, 0);
5743 if (!INT_5_BITS (operands[2]))
5744 operands[2] = force_reg (SImode, operands[2]);
5746 emit_insn (gen_cmpsi (operands[0], operands[2]));
5747 emit_jump_insn (gen_bgtu (operands[4]));
5748 if (TARGET_BIG_SWITCH)
5750 rtx temp = gen_reg_rtx (SImode);
5751 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5754 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5758 (define_insn "casesi0"
5760 (mem:SI (plus:SI (pc)
5761 (match_operand:SI 0 "register_operand" "r")))
5762 (label_ref (match_operand 1 "" ""))))]
5765 [(set_attr "type" "multi")
5766 (set_attr "length" "8")])
5768 ;; Need nops for the calls because execution is supposed to continue
5769 ;; past; we don't want to nullify an instruction that we need.
5770 ;;- jump to subroutine
5772 (define_expand "call"
5773 [(parallel [(call (match_operand:SI 0 "" "")
5774 (match_operand 1 "" ""))
5775 (clobber (reg:SI 2))])]
5782 if (TARGET_PORTABLE_RUNTIME)
5783 op = force_reg (SImode, XEXP (operands[0], 0));
5785 op = XEXP (operands[0], 0);
5788 emit_move_insn (arg_pointer_rtx,
5789 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5792 /* Use two different patterns for calls to explicitly named functions
5793 and calls through function pointers. This is necessary as these two
5794 types of calls use different calling conventions, and CSE might try
5795 to change the named call into an indirect call in some cases (using
5796 two patterns keeps CSE from performing this optimization). */
5797 if (GET_CODE (op) == SYMBOL_REF)
5798 call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
5799 else if (TARGET_64BIT)
5801 rtx tmpreg = force_reg (word_mode, op);
5802 call_insn = emit_call_insn (gen_call_internal_reg_64bit (tmpreg,
5807 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5808 emit_move_insn (tmpreg, force_reg (word_mode, op));
5809 call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
5814 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5815 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5816 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5818 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
5820 /* After each call we must restore the PIC register, even if it
5821 doesn't appear to be used.
5823 This will set regs_ever_live for the callee saved register we
5824 stored the PIC register in. */
5825 emit_move_insn (pic_offset_table_rtx,
5826 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5831 (define_insn "call_internal_symref"
5832 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5833 (match_operand 1 "" "i"))
5834 (clobber (reg:SI 2))
5835 (use (const_int 0))]
5836 "! TARGET_PORTABLE_RUNTIME"
5839 output_arg_descriptor (insn);
5840 return output_call (insn, operands[0], 0);
5842 [(set_attr "type" "call")
5843 (set (attr "length")
5844 ;; If we're sure that we can either reach the target or that the
5845 ;; linker can use a long-branch stub, then the length is 4 bytes.
5847 ;; For long-calls the length will be either 52 bytes (non-pic)
5848 ;; or 68 bytes (pic). */
5849 ;; Else we have to use a long-call;
5850 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
5853 (if_then_else (eq (symbol_ref "flag_pic")
5858 (define_insn "call_internal_reg_64bit"
5859 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
5860 (match_operand 1 "" "i"))
5861 (clobber (reg:SI 2))
5862 (use (const_int 1))]
5868 /* ??? Needs more work. Length computation, split into multiple insns,
5869 do not use %r22 directly, expose delay slot. */
5870 return \"ldd 16(%0),%%r2\;ldd 24(%0),%%r27\;bve,l (%%r2),%%r2\;nop\";
5872 [(set_attr "type" "dyncall")
5873 (set (attr "length") (const_int 16))])
5875 (define_insn "call_internal_reg"
5876 [(call (mem:SI (reg:SI 22))
5877 (match_operand 0 "" "i"))
5878 (clobber (reg:SI 2))
5879 (use (const_int 1))]
5885 /* First the special case for kernels, level 0 systems, etc. */
5886 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
5887 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
5889 /* Now the normal case -- we can reach $$dyncall directly or
5890 we're sure that we can get there via a long-branch stub.
5892 No need to check target flags as the length uniquely identifies
5893 the remaining cases. */
5894 if (get_attr_length (insn) == 8)
5895 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
5897 /* Long millicode call, but we are not generating PIC or portable runtime
5899 if (get_attr_length (insn) == 12)
5900 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
5902 /* Long millicode call for portable runtime. */
5903 if (get_attr_length (insn) == 20)
5904 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
5906 /* If we're generating PIC code. */
5907 xoperands[0] = operands[0];
5908 xoperands[1] = gen_label_rtx ();
5909 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5910 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
5911 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5912 CODE_LABEL_NUMBER (xoperands[1]));
5913 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
5914 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
5915 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
5918 [(set_attr "type" "dyncall")
5919 (set (attr "length")
5921 ;; First NO_SPACE_REGS
5922 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
5926 ;; Target (or stub) within reach
5927 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
5929 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5933 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
5934 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5936 (eq (symbol_ref "flag_pic")
5940 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
5944 ;; Out of range PIC case
5947 (define_expand "call_value"
5948 [(parallel [(set (match_operand 0 "" "")
5949 (call (match_operand:SI 1 "" "")
5950 (match_operand 2 "" "")))
5951 (clobber (reg:SI 2))])]
5958 if (TARGET_PORTABLE_RUNTIME)
5959 op = force_reg (word_mode, XEXP (operands[1], 0));
5961 op = XEXP (operands[1], 0);
5964 emit_move_insn (arg_pointer_rtx,
5965 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5968 /* Use two different patterns for calls to explicitly named functions
5969 and calls through function pointers. This is necessary as these two
5970 types of calls use different calling conventions, and CSE might try
5971 to change the named call into an indirect call in some cases (using
5972 two patterns keeps CSE from performing this optimization). */
5973 if (GET_CODE (op) == SYMBOL_REF)
5974 call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
5977 else if (TARGET_64BIT)
5979 rtx tmpreg = force_reg (word_mode, op);
5981 = emit_call_insn (gen_call_value_internal_reg_64bit (operands[0],
5987 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5988 emit_move_insn (tmpreg, force_reg (word_mode, op));
5989 call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
5994 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5995 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5996 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5998 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6000 /* After each call we must restore the PIC register, even if it
6001 doesn't appear to be used.
6003 This will set regs_ever_live for the callee saved register we
6004 stored the PIC register in. */
6005 emit_move_insn (pic_offset_table_rtx,
6006 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6011 (define_insn "call_value_internal_symref"
6012 [(set (match_operand 0 "" "=rf")
6013 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6014 (match_operand 2 "" "i")))
6015 (clobber (reg:SI 2))
6016 (use (const_int 0))]
6017 ;;- Don't use operand 1 for most machines.
6018 "! TARGET_PORTABLE_RUNTIME"
6021 output_arg_descriptor (insn);
6022 return output_call (insn, operands[1], 0);
6024 [(set_attr "type" "call")
6025 (set (attr "length")
6026 ;; If we're sure that we can either reach the target or that the
6027 ;; linker can use a long-branch stub, then the length is 4 bytes.
6029 ;; For long-calls the length will be either 52 bytes (non-pic)
6030 ;; or 68 bytes (pic). */
6031 ;; Else we have to use a long-call;
6032 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6035 (if_then_else (eq (symbol_ref "flag_pic")
6040 (define_insn "call_value_internal_reg_64bit"
6041 [(set (match_operand 0 "" "=rf")
6042 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6043 (match_operand 2 "" "i")))
6044 (clobber (reg:SI 2))
6045 (use (const_int 1))]
6049 /* ??? Needs more work. Length computation, split into multiple insns,
6050 do not use %r22 directly, expose delay slot. */
6051 return \"ldd 16(%1),%%r2\;ldd 24(%1),%%r27\;bve,l (%%r2),%%r2\;nop\";
6053 [(set_attr "type" "dyncall")
6054 (set (attr "length") (const_int 16))])
6056 (define_insn "call_value_internal_reg"
6057 [(set (match_operand 0 "" "=rf")
6058 (call (mem:SI (reg:SI 22))
6059 (match_operand 1 "" "i")))
6060 (clobber (reg:SI 2))
6061 (use (const_int 1))]
6067 /* First the special case for kernels, level 0 systems, etc. */
6068 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
6069 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
6071 /* Now the normal case -- we can reach $$dyncall directly or
6072 we're sure that we can get there via a long-branch stub.
6074 No need to check target flags as the length uniquely identifies
6075 the remaining cases. */
6076 if (get_attr_length (insn) == 8)
6077 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
6079 /* Long millicode call, but we are not generating PIC or portable runtime
6081 if (get_attr_length (insn) == 12)
6082 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
6084 /* Long millicode call for portable runtime. */
6085 if (get_attr_length (insn) == 20)
6086 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
6088 /* If we're generating PIC code. */
6089 xoperands[0] = operands[1];
6090 xoperands[1] = gen_label_rtx ();
6091 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
6092 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
6093 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6094 CODE_LABEL_NUMBER (xoperands[1]));
6095 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
6096 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
6097 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
6100 [(set_attr "type" "dyncall")
6101 (set (attr "length")
6103 ;; First NO_SPACE_REGS
6104 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
6108 ;; Target (or stub) within reach
6109 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6111 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6115 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
6116 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6118 (eq (symbol_ref "flag_pic")
6122 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
6126 ;; Out of range PIC case
6129 ;; Call subroutine returning any type.
6131 (define_expand "untyped_call"
6132 [(parallel [(call (match_operand 0 "" "")
6134 (match_operand 1 "" "")
6135 (match_operand 2 "" "")])]
6141 emit_call_insn (gen_call (operands[0], const0_rtx));
6143 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6145 rtx set = XVECEXP (operands[2], 0, i);
6146 emit_move_insn (SET_DEST (set), SET_SRC (set));
6149 /* The optimizer does not know that the call sets the function value
6150 registers we stored in the result block. We avoid problems by
6151 claiming that all hard registers are used and clobbered at this
6153 emit_insn (gen_blockage ());
6158 (define_expand "sibcall"
6159 [(parallel [(call (match_operand:SI 0 "" "")
6160 (match_operand 1 "" ""))
6161 (clobber (reg:SI 0))])]
6162 "! TARGET_PORTABLE_RUNTIME"
6168 op = XEXP (operands[0], 0);
6170 /* We do not allow indirect sibling calls. */
6171 call_insn = emit_call_insn (gen_sibcall_internal_symref (op, operands[1]));
6175 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6176 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6177 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6179 /* After each call we must restore the PIC register, even if it
6180 doesn't appear to be used.
6182 This will set regs_ever_live for the callee saved register we
6183 stored the PIC register in. */
6184 emit_move_insn (pic_offset_table_rtx,
6185 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6190 (define_insn "sibcall_internal_symref"
6191 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6192 (match_operand 1 "" "i"))
6193 (clobber (reg:SI 0))
6195 (use (const_int 0))]
6196 "! TARGET_PORTABLE_RUNTIME"
6199 output_arg_descriptor (insn);
6200 return output_call (insn, operands[0], 1);
6202 [(set_attr "type" "call")
6203 (set (attr "length")
6204 ;; If we're sure that we can either reach the target or that the
6205 ;; linker can use a long-branch stub, then the length is 4 bytes.
6207 ;; For long-calls the length will be either 52 bytes (non-pic)
6208 ;; or 68 bytes (pic). */
6209 ;; Else we have to use a long-call;
6210 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6213 (if_then_else (eq (symbol_ref "flag_pic")
6218 (define_expand "sibcall_value"
6219 [(parallel [(set (match_operand 0 "" "")
6220 (call (match_operand:SI 1 "" "")
6221 (match_operand 2 "" "")))
6222 (clobber (reg:SI 0))])]
6223 "! TARGET_PORTABLE_RUNTIME"
6229 op = XEXP (operands[1], 0);
6231 /* We do not allow indirect sibling calls. */
6232 call_insn = emit_call_insn (gen_sibcall_value_internal_symref (operands[0],
6237 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6238 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6239 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6241 /* After each call we must restore the PIC register, even if it
6242 doesn't appear to be used.
6244 This will set regs_ever_live for the callee saved register we
6245 stored the PIC register in. */
6246 emit_move_insn (pic_offset_table_rtx,
6247 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6252 (define_insn "sibcall_value_internal_symref"
6253 [(set (match_operand 0 "" "=rf")
6254 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6255 (match_operand 2 "" "i")))
6256 (clobber (reg:SI 0))
6258 (use (const_int 0))]
6259 ;;- Don't use operand 1 for most machines.
6260 "! TARGET_PORTABLE_RUNTIME"
6263 output_arg_descriptor (insn);
6264 return output_call (insn, operands[1], 1);
6266 [(set_attr "type" "call")
6267 (set (attr "length")
6268 ;; If we're sure that we can either reach the target or that the
6269 ;; linker can use a long-branch stub, then the length is 4 bytes.
6271 ;; For long-calls the length will be either 52 bytes (non-pic)
6272 ;; or 68 bytes (pic). */
6273 ;; Else we have to use a long-call;
6274 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6277 (if_then_else (eq (symbol_ref "flag_pic")
6286 [(set_attr "type" "move")
6287 (set_attr "length" "4")])
6289 ;; These are just placeholders so we know where branch tables
6291 (define_insn "begin_brtab"
6296 /* Only GAS actually supports this pseudo-op. */
6298 return \".begin_brtab\";
6302 [(set_attr "type" "move")
6303 (set_attr "length" "0")])
6305 (define_insn "end_brtab"
6310 /* Only GAS actually supports this pseudo-op. */
6312 return \".end_brtab\";
6316 [(set_attr "type" "move")
6317 (set_attr "length" "0")])
6319 ;;; EH does longjmp's from and within the data section. Thus,
6320 ;;; an interspace branch is required for the longjmp implementation.
6321 ;;; Registers r1 and r2 are not saved in the jmpbuf environment.
6322 ;;; Thus, they can be used as scratch registers for the jump.
6323 (define_expand "interspace_jump"
6325 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6326 (clobber (match_dup 1))])]
6330 operands[1] = gen_rtx_REG (word_mode, 2);
6334 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6335 (clobber (reg:SI 2))]
6337 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6338 [(set_attr "type" "branch")
6339 (set_attr "length" "12")])
6342 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6343 (clobber (reg:DI 2))]
6345 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6346 [(set_attr "type" "branch")
6347 (set_attr "length" "12")])
6349 (define_expand "builtin_longjmp"
6350 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6354 /* The elements of the buffer are, in order: */
6355 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6356 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4));
6357 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6358 rtx pv = gen_rtx_REG (Pmode, 1);
6360 /* This bit is the same as expand_builtin_longjmp. */
6361 emit_move_insn (hard_frame_pointer_rtx, fp);
6362 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6363 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6364 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6366 /* Load the label we are jumping through into r1 so that we know
6367 where to look for it when we get back to setjmp's function for
6368 restoring the gp. */
6369 emit_move_insn (pv, lab);
6370 emit_jump_insn (gen_interspace_jump (pv));
6374 ;;; Hope this is only within a function...
6375 (define_insn "indirect_jump"
6376 [(set (pc) (match_operand 0 "register_operand" "r"))]
6377 "GET_MODE (operands[0]) == word_mode"
6379 [(set_attr "type" "branch")
6380 (set_attr "length" "4")])
6382 (define_expand "extzv"
6383 [(set (match_operand 0 "register_operand" "")
6384 (zero_extract (match_operand 1 "register_operand" "")
6385 (match_operand 2 "uint32_operand" "")
6386 (match_operand 3 "uint32_operand" "")))]
6391 emit_insn (gen_extzv_64 (operands[0], operands[1],
6392 operands[2], operands[3]));
6394 emit_insn (gen_extzv_32 (operands[0], operands[1],
6395 operands[2], operands[3]));
6399 (define_insn "extzv_32"
6400 [(set (match_operand:SI 0 "register_operand" "=r")
6401 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6402 (match_operand:SI 2 "uint5_operand" "")
6403 (match_operand:SI 3 "uint5_operand" "")))]
6405 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
6406 [(set_attr "type" "shift")
6407 (set_attr "length" "4")])
6410 [(set (match_operand:SI 0 "register_operand" "=r")
6411 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6413 (match_operand:SI 3 "register_operand" "q")))]
6415 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
6416 [(set_attr "type" "shift")
6417 (set_attr "length" "4")])
6419 (define_insn "extzv_64"
6420 [(set (match_operand:DI 0 "register_operand" "=r")
6421 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6422 (match_operand:DI 2 "uint32_operand" "")
6423 (match_operand:DI 3 "uint32_operand" "")))]
6425 "extrd,u %1,%3+%2-1,%2,%0"
6426 [(set_attr "type" "shift")
6427 (set_attr "length" "4")])
6430 [(set (match_operand:DI 0 "register_operand" "=r")
6431 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6433 (match_operand:DI 3 "register_operand" "q")))]
6435 "extrd,u %1,%%sar,1,%0"
6436 [(set_attr "type" "shift")
6437 (set_attr "length" "4")])
6439 (define_expand "extv"
6440 [(set (match_operand 0 "register_operand" "")
6441 (sign_extract (match_operand 1 "register_operand" "")
6442 (match_operand 2 "uint32_operand" "")
6443 (match_operand 3 "uint32_operand" "")))]
6448 emit_insn (gen_extv_64 (operands[0], operands[1],
6449 operands[2], operands[3]));
6451 emit_insn (gen_extv_32 (operands[0], operands[1],
6452 operands[2], operands[3]));
6456 (define_insn "extv_32"
6457 [(set (match_operand:SI 0 "register_operand" "=r")
6458 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6459 (match_operand:SI 2 "uint5_operand" "")
6460 (match_operand:SI 3 "uint5_operand" "")))]
6462 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
6463 [(set_attr "type" "shift")
6464 (set_attr "length" "4")])
6467 [(set (match_operand:SI 0 "register_operand" "=r")
6468 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6470 (match_operand:SI 3 "register_operand" "q")))]
6472 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
6473 [(set_attr "type" "shift")
6474 (set_attr "length" "4")])
6476 (define_insn "extv_64"
6477 [(set (match_operand:DI 0 "register_operand" "=r")
6478 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6479 (match_operand:DI 2 "uint32_operand" "")
6480 (match_operand:DI 3 "uint32_operand" "")))]
6482 "extrd,s %1,%3+%2-1,%2,%0"
6483 [(set_attr "type" "shift")
6484 (set_attr "length" "4")])
6487 [(set (match_operand:DI 0 "register_operand" "=r")
6488 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6490 (match_operand:DI 3 "register_operand" "q")))]
6492 "extrd,s %1,%%sar,1,%0"
6493 [(set_attr "type" "shift")
6494 (set_attr "length" "4")])
6496 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
6497 (define_expand "insv"
6498 [(set (zero_extract (match_operand 0 "register_operand" "")
6499 (match_operand 1 "uint32_operand" "")
6500 (match_operand 2 "uint32_operand" ""))
6501 (match_operand 3 "arith5_operand" ""))]
6506 emit_insn (gen_insv_64 (operands[0], operands[1],
6507 operands[2], operands[3]));
6509 emit_insn (gen_insv_32 (operands[0], operands[1],
6510 operands[2], operands[3]));
6514 (define_insn "insv_32"
6515 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
6516 (match_operand:SI 1 "uint5_operand" "")
6517 (match_operand:SI 2 "uint5_operand" ""))
6518 (match_operand:SI 3 "arith5_operand" "r,L"))]
6521 {dep|depw} %3,%2+%1-1,%1,%0
6522 {depi|depwi} %3,%2+%1-1,%1,%0"
6523 [(set_attr "type" "shift,shift")
6524 (set_attr "length" "4,4")])
6526 ;; Optimize insertion of const_int values of type 1...1xxxx.
6528 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
6529 (match_operand:SI 1 "uint5_operand" "")
6530 (match_operand:SI 2 "uint5_operand" ""))
6531 (match_operand:SI 3 "const_int_operand" ""))]
6532 "(INTVAL (operands[3]) & 0x10) != 0 &&
6533 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6536 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6537 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
6539 [(set_attr "type" "shift")
6540 (set_attr "length" "4")])
6542 (define_insn "insv_64"
6543 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
6544 (match_operand:DI 1 "uint32_operand" "")
6545 (match_operand:DI 2 "uint32_operand" ""))
6546 (match_operand:DI 3 "arith32_operand" "r,L"))]
6549 depd %3,%2+%1-1,%1,%0
6550 depdi %3,%2+%1-1,%1,%0"
6551 [(set_attr "type" "shift,shift")
6552 (set_attr "length" "4,4")])
6554 ;; Optimize insertion of const_int values of type 1...1xxxx.
6556 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
6557 (match_operand:DI 1 "uint32_operand" "")
6558 (match_operand:DI 2 "uint32_operand" ""))
6559 (match_operand:DI 3 "const_int_operand" ""))]
6560 "(INTVAL (operands[3]) & 0x10) != 0
6562 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6565 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6566 return \"depdi %3,%2+%1-1,%1,%0\";
6568 [(set_attr "type" "shift")
6569 (set_attr "length" "4")])
6572 [(set (match_operand:DI 0 "register_operand" "=r")
6573 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
6576 "depd,z %1,31,32,%0"
6577 [(set_attr "type" "shift")
6578 (set_attr "length" "4")])
6580 ;; This insn is used for some loop tests, typically loops reversed when
6581 ;; strength reduction is used. It is actually created when the instruction
6582 ;; combination phase combines the special loop test. Since this insn
6583 ;; is both a jump insn and has an output, it must deal with its own
6584 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
6585 ;; to not choose the register alternatives in the event a reload is needed.
6586 (define_insn "decrement_and_branch_until_zero"
6589 (match_operator 2 "comparison_operator"
6590 [(plus:SI (match_operand:SI 0 "register_operand" "+!r,!*f,!*m")
6591 (match_operand:SI 1 "int5_operand" "L,L,L"))
6593 (label_ref (match_operand 3 "" ""))
6596 (plus:SI (match_dup 0) (match_dup 1)))
6597 (clobber (match_scratch:SI 4 "=X,r,r"))]
6599 "* return output_dbra (operands, insn, which_alternative); "
6600 ;; Do not expect to understand this the first time through.
6601 [(set_attr "type" "cbranch,multi,multi")
6602 (set (attr "length")
6603 (if_then_else (eq_attr "alternative" "0")
6604 ;; Loop counter in register case
6605 ;; Short branch has length of 4
6606 ;; Long branch has length of 8
6607 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6612 ;; Loop counter in FP reg case.
6613 ;; Extra goo to deal with additional reload insns.
6614 (if_then_else (eq_attr "alternative" "1")
6615 (if_then_else (lt (match_dup 3) (pc))
6617 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
6622 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6626 ;; Loop counter in memory case.
6627 ;; Extra goo to deal with additional reload insns.
6628 (if_then_else (lt (match_dup 3) (pc))
6630 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6635 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6638 (const_int 16))))))])
6643 (match_operator 2 "movb_comparison_operator"
6644 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6645 (label_ref (match_operand 3 "" ""))
6647 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
6650 "* return output_movb (operands, insn, which_alternative, 0); "
6651 ;; Do not expect to understand this the first time through.
6652 [(set_attr "type" "cbranch,multi,multi,multi")
6653 (set (attr "length")
6654 (if_then_else (eq_attr "alternative" "0")
6655 ;; Loop counter in register case
6656 ;; Short branch has length of 4
6657 ;; Long branch has length of 8
6658 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6663 ;; Loop counter in FP reg case.
6664 ;; Extra goo to deal with additional reload insns.
6665 (if_then_else (eq_attr "alternative" "1")
6666 (if_then_else (lt (match_dup 3) (pc))
6668 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6673 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6677 ;; Loop counter in memory or sar case.
6678 ;; Extra goo to deal with additional reload insns.
6680 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6683 (const_int 12)))))])
6685 ;; Handle negated branch.
6689 (match_operator 2 "movb_comparison_operator"
6690 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6692 (label_ref (match_operand 3 "" ""))))
6693 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
6696 "* return output_movb (operands, insn, which_alternative, 1); "
6697 ;; Do not expect to understand this the first time through.
6698 [(set_attr "type" "cbranch,multi,multi,multi")
6699 (set (attr "length")
6700 (if_then_else (eq_attr "alternative" "0")
6701 ;; Loop counter in register case
6702 ;; Short branch has length of 4
6703 ;; Long branch has length of 8
6704 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6709 ;; Loop counter in FP reg case.
6710 ;; Extra goo to deal with additional reload insns.
6711 (if_then_else (eq_attr "alternative" "1")
6712 (if_then_else (lt (match_dup 3) (pc))
6714 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6719 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6723 ;; Loop counter in memory or SAR case.
6724 ;; Extra goo to deal with additional reload insns.
6726 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6729 (const_int 12)))))])
6732 [(set (pc) (label_ref (match_operand 3 "" "" )))
6733 (set (match_operand:SI 0 "ireg_operand" "=r")
6734 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
6735 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
6736 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
6739 return output_parallel_addb (operands, get_attr_length (insn));
6741 [(set_attr "type" "parallel_branch")
6742 (set (attr "length")
6743 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6749 [(set (pc) (label_ref (match_operand 2 "" "" )))
6750 (set (match_operand:SF 0 "ireg_operand" "=r")
6751 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
6755 return output_parallel_movb (operands, get_attr_length (insn));
6757 [(set_attr "type" "parallel_branch")
6758 (set (attr "length")
6759 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6765 [(set (pc) (label_ref (match_operand 2 "" "" )))
6766 (set (match_operand:SI 0 "ireg_operand" "=r")
6767 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
6771 return output_parallel_movb (operands, get_attr_length (insn));
6773 [(set_attr "type" "parallel_branch")
6774 (set (attr "length")
6775 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6781 [(set (pc) (label_ref (match_operand 2 "" "" )))
6782 (set (match_operand:HI 0 "ireg_operand" "=r")
6783 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
6787 return output_parallel_movb (operands, get_attr_length (insn));
6789 [(set_attr "type" "parallel_branch")
6790 (set (attr "length")
6791 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6797 [(set (pc) (label_ref (match_operand 2 "" "" )))
6798 (set (match_operand:QI 0 "ireg_operand" "=r")
6799 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
6803 return output_parallel_movb (operands, get_attr_length (insn));
6805 [(set_attr "type" "parallel_branch")
6806 (set (attr "length")
6807 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6813 [(set (match_operand 0 "register_operand" "=f")
6814 (mult (match_operand 1 "register_operand" "f")
6815 (match_operand 2 "register_operand" "f")))
6816 (set (match_operand 3 "register_operand" "+f")
6817 (plus (match_operand 4 "register_operand" "f")
6818 (match_operand 5 "register_operand" "f")))]
6819 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6820 && reload_completed && fmpyaddoperands (operands)"
6823 if (GET_MODE (operands[0]) == DFmode)
6825 if (rtx_equal_p (operands[3], operands[5]))
6826 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
6828 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
6832 if (rtx_equal_p (operands[3], operands[5]))
6833 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
6835 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
6838 [(set_attr "type" "fpalu")
6839 (set_attr "length" "4")])
6842 [(set (match_operand 3 "register_operand" "+f")
6843 (plus (match_operand 4 "register_operand" "f")
6844 (match_operand 5 "register_operand" "f")))
6845 (set (match_operand 0 "register_operand" "=f")
6846 (mult (match_operand 1 "register_operand" "f")
6847 (match_operand 2 "register_operand" "f")))]
6848 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6849 && reload_completed && fmpyaddoperands (operands)"
6852 if (GET_MODE (operands[0]) == DFmode)
6854 if (rtx_equal_p (operands[3], operands[5]))
6855 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
6857 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
6861 if (rtx_equal_p (operands[3], operands[5]))
6862 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
6864 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
6867 [(set_attr "type" "fpalu")
6868 (set_attr "length" "4")])
6871 [(set (match_operand 0 "register_operand" "=f")
6872 (mult (match_operand 1 "register_operand" "f")
6873 (match_operand 2 "register_operand" "f")))
6874 (set (match_operand 3 "register_operand" "+f")
6875 (minus (match_operand 4 "register_operand" "f")
6876 (match_operand 5 "register_operand" "f")))]
6877 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6878 && reload_completed && fmpysuboperands (operands)"
6881 if (GET_MODE (operands[0]) == DFmode)
6882 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
6884 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
6886 [(set_attr "type" "fpalu")
6887 (set_attr "length" "4")])
6890 [(set (match_operand 3 "register_operand" "+f")
6891 (minus (match_operand 4 "register_operand" "f")
6892 (match_operand 5 "register_operand" "f")))
6893 (set (match_operand 0 "register_operand" "=f")
6894 (mult (match_operand 1 "register_operand" "f")
6895 (match_operand 2 "register_operand" "f")))]
6896 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6897 && reload_completed && fmpysuboperands (operands)"
6900 if (GET_MODE (operands[0]) == DFmode)
6901 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
6903 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
6905 [(set_attr "type" "fpalu")
6906 (set_attr "length" "4")])
6908 ;; Clean up turds left by reload.
6910 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
6911 (match_operand 1 "register_operand" "fr"))
6912 (set (match_operand 2 "register_operand" "fr")
6914 "! TARGET_SOFT_FLOAT
6915 && GET_CODE (operands[0]) == MEM
6916 && ! MEM_VOLATILE_P (operands[0])
6917 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6918 && GET_MODE (operands[0]) == GET_MODE (operands[2])
6919 && GET_MODE (operands[0]) == DFmode
6920 && GET_CODE (operands[1]) == REG
6921 && GET_CODE (operands[2]) == REG
6922 && ! side_effects_p (XEXP (operands[0], 0))
6923 && REGNO_REG_CLASS (REGNO (operands[1]))
6924 == REGNO_REG_CLASS (REGNO (operands[2]))"
6929 if (FP_REG_P (operands[1]))
6930 output_asm_insn (output_fp_move_double (operands), operands);
6932 output_asm_insn (output_move_double (operands), operands);
6934 if (rtx_equal_p (operands[1], operands[2]))
6937 xoperands[0] = operands[2];
6938 xoperands[1] = operands[1];
6940 if (FP_REG_P (xoperands[1]))
6941 output_asm_insn (output_fp_move_double (xoperands), xoperands);
6943 output_asm_insn (output_move_double (xoperands), xoperands);
6949 [(set (match_operand 0 "register_operand" "fr")
6950 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
6951 (set (match_operand 2 "register_operand" "fr")
6953 "! TARGET_SOFT_FLOAT
6954 && GET_CODE (operands[1]) == MEM
6955 && ! MEM_VOLATILE_P (operands[1])
6956 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6957 && GET_MODE (operands[0]) == GET_MODE (operands[2])
6958 && GET_MODE (operands[0]) == DFmode
6959 && GET_CODE (operands[0]) == REG
6960 && GET_CODE (operands[2]) == REG
6961 && ! side_effects_p (XEXP (operands[1], 0))
6962 && REGNO_REG_CLASS (REGNO (operands[0]))
6963 == REGNO_REG_CLASS (REGNO (operands[2]))"
6968 if (FP_REG_P (operands[0]))
6969 output_asm_insn (output_fp_move_double (operands), operands);
6971 output_asm_insn (output_move_double (operands), operands);
6973 xoperands[0] = operands[2];
6974 xoperands[1] = operands[0];
6976 if (FP_REG_P (xoperands[1]))
6977 output_asm_insn (output_fp_move_double (xoperands), xoperands);
6979 output_asm_insn (output_move_double (xoperands), xoperands);
6984 ;; Flush the I and D cache line found at the address in operand 0.
6985 ;; This is used by the trampoline code for nested functions.
6986 ;; So long as the trampoline itself is less than 32 bytes this
6989 (define_insn "dcacheflush"
6990 [(unspec_volatile [(const_int 1)] 0)
6991 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
6992 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
6994 "fdc 0(%0)\;fdc 0(%1)\;sync"
6995 [(set_attr "type" "multi")
6996 (set_attr "length" "12")])
6998 (define_insn "icacheflush"
6999 [(unspec_volatile [(const_int 2)] 0)
7000 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7001 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
7002 (use (match_operand 2 "pmode_register_operand" "r"))
7003 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
7004 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
7006 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
7007 [(set_attr "type" "multi")
7008 (set_attr "length" "52")])
7010 ;; An out-of-line prologue.
7011 (define_insn "outline_prologue_call"
7012 [(unspec_volatile [(const_int 0)] 0)
7013 (clobber (reg:SI 31))
7014 (clobber (reg:SI 22))
7015 (clobber (reg:SI 21))
7016 (clobber (reg:SI 20))
7017 (clobber (reg:SI 19))
7018 (clobber (reg:SI 1))]
7022 extern int frame_pointer_needed;
7024 /* We need two different versions depending on whether or not we
7025 need a frame pointer. Also note that we return to the instruction
7026 immediately after the branch rather than two instructions after the
7027 break as normally is the case. */
7028 if (frame_pointer_needed)
7030 /* Must import the magic millicode routine(s). */
7031 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
7033 if (TARGET_PORTABLE_RUNTIME)
7035 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
7036 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
7040 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
7044 /* Must import the magic millicode routine(s). */
7045 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
7047 if (TARGET_PORTABLE_RUNTIME)
7049 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
7050 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
7053 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
7057 [(set_attr "type" "multi")
7058 (set_attr "length" "8")])
7060 ;; An out-of-line epilogue.
7061 (define_insn "outline_epilogue_call"
7062 [(unspec_volatile [(const_int 1)] 0)
7065 (clobber (reg:SI 31))
7066 (clobber (reg:SI 22))
7067 (clobber (reg:SI 21))
7068 (clobber (reg:SI 20))
7069 (clobber (reg:SI 19))
7070 (clobber (reg:SI 2))
7071 (clobber (reg:SI 1))]
7075 extern int frame_pointer_needed;
7077 /* We need two different versions depending on whether or not we
7078 need a frame pointer. Also note that we return to the instruction
7079 immediately after the branch rather than two instructions after the
7080 break as normally is the case. */
7081 if (frame_pointer_needed)
7083 /* Must import the magic millicode routine. */
7084 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
7086 /* The out-of-line prologue will make sure we return to the right
7088 if (TARGET_PORTABLE_RUNTIME)
7090 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
7091 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
7095 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
7099 /* Must import the magic millicode routine. */
7100 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
7102 /* The out-of-line prologue will make sure we return to the right
7104 if (TARGET_PORTABLE_RUNTIME)
7106 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
7107 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
7110 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
7114 [(set_attr "type" "multi")
7115 (set_attr "length" "8")])
7117 ;; Given a function pointer, canonicalize it so it can be
7118 ;; reliably compared to another function pointer. */
7119 (define_expand "canonicalize_funcptr_for_compare"
7120 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
7121 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7122 (clobber (match_dup 2))
7123 (clobber (reg:SI 26))
7124 (clobber (reg:SI 22))
7125 (clobber (reg:SI 31))])
7126 (set (match_operand:SI 0 "register_operand" "")
7128 "! TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7131 operands[2] = gen_reg_rtx (SImode);
7132 if (GET_CODE (operands[1]) != REG)
7134 rtx tmp = gen_reg_rtx (Pmode);
7135 emit_move_insn (tmp, operands[1]);
7141 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7142 (clobber (match_operand:SI 0 "register_operand" "=a"))
7143 (clobber (reg:SI 26))
7144 (clobber (reg:SI 22))
7145 (clobber (reg:SI 31))]
7149 /* Must import the magic millicode routine. */
7150 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
7152 /* This is absolutely amazing.
7154 First, copy our input parameter into %r29 just in case we don't
7155 need to call $$sh_func_adrs. */
7156 output_asm_insn (\"copy %%r26,%%r29\", NULL);
7158 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
7159 we use %r26 unchanged. */
7160 if (get_attr_length (insn) == 32)
7161 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
7162 else if (get_attr_length (insn) == 40)
7163 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
7164 else if (get_attr_length (insn) == 44)
7165 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
7167 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
7169 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
7170 4096, then we use %r26 unchanged. */
7171 if (get_attr_length (insn) == 32)
7172 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
7174 else if (get_attr_length (insn) == 40)
7175 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
7177 else if (get_attr_length (insn) == 44)
7178 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
7181 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
7184 /* Else call $$sh_func_adrs to extract the function's real add24. */
7185 return output_millicode_call (insn,
7186 gen_rtx_SYMBOL_REF (SImode,
7187 \"$$sh_func_adrs\"));
7189 [(set_attr "type" "multi")
7190 (set (attr "length")
7192 ;; Target (or stub) within reach
7193 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
7195 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7200 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
7204 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
7205 ;; same as NO_SPACE_REGS code
7206 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7208 (eq (symbol_ref "flag_pic")
7213 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
7217 ;; Out of range and PIC
7220 ;; On the PA, the PIC register is call clobbered, so it must
7221 ;; be saved & restored around calls by the caller. If the call
7222 ;; doesn't return normally (nonlocal goto, or an exception is
7223 ;; thrown), then the code at the exception handler label must
7224 ;; restore the PIC register.
7225 (define_expand "exception_receiver"
7227 "!TARGET_PORTABLE_RUNTIME && flag_pic"
7230 /* Load the PIC register from the stack slot (in our caller's
7232 emit_move_insn (pic_offset_table_rtx,
7233 gen_rtx_MEM (SImode,
7234 plus_constant (stack_pointer_rtx, -32)));
7235 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
7236 emit_insn (gen_blockage ());